/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the AArch64 target                         *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 101;
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(2),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_s8,
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_s128,
  GILLT_v2s32,
  GILLT_v2s64,
  GILLT_v4s16,
  GILLT_v4s32,
  GILLT_v8s8,
  GILLT_v8s16,
  GILLT_v16s8,
  GILLT_nxv1s1,
  GILLT_nxv2s1,
  GILLT_nxv2s16,
  GILLT_nxv2s32,
  GILLT_nxv2s64,
  GILLT_nxv4s1,
  GILLT_nxv4s16,
  GILLT_nxv4s32,
  GILLT_nxv8s1,
  GILLT_nxv8s16,
  GILLT_nxv16s1,
  GILLT_nxv16s8,
};
const static size_t NumTypeObjects = 24;
const static LLT TypeObjects[] = {
  LLT::scalar(8),
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::scalar(128),
  LLT::vector(ElementCount::getFixed(2), 32),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(4), 16),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(8), 8),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(16), 8),
  LLT::vector(ElementCount::getScalable(1), 1),
  LLT::vector(ElementCount::getScalable(2), 1),
  LLT::vector(ElementCount::getScalable(2), 16),
  LLT::vector(ElementCount::getScalable(2), 32),
  LLT::vector(ElementCount::getScalable(2), 64),
  LLT::vector(ElementCount::getScalable(4), 1),
  LLT::vector(ElementCount::getScalable(4), 16),
  LLT::vector(ElementCount::getScalable(4), 32),
  LLT::vector(ElementCount::getScalable(8), 1),
  LLT::vector(ElementCount::getScalable(8), 16),
  LLT::vector(ElementCount::getScalable(16), 1),
  LLT::vector(ElementCount::getScalable(16), 8),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasPAuthBit = 6,
  Feature_HasJSBit = 8,
  Feature_HasComplxNumBit = 69,
  Feature_HasRCPC_IMMOBit = 90,
  Feature_HasFPARMv8Bit = 7,
  Feature_HasNEONBit = 5,
  Feature_HasSM4Bit = 68,
  Feature_HasSHA3Bit = 67,
  Feature_HasSHA2Bit = 19,
  Feature_HasAESBit = 18,
  Feature_HasDotProdBit = 2,
  Feature_HasCRCBit = 10,
  Feature_HasCSSCBit = 20,
  Feature_HasNoCSSCBit = 32,
  Feature_HasLSEBit = 33,
  Feature_HasNoLSEBit = 100,
  Feature_HasRDMBit = 16,
  Feature_HasFullFP16Bit = 13,
  Feature_HasNoFullFP16Bit = 87,
  Feature_HasFP16FMLBit = 4,
  Feature_HasFuseAESBit = 81,
  Feature_HasSVEBit = 26,
  Feature_HasSVE2Bit = 27,
  Feature_HasSVE2p1Bit = 47,
  Feature_HasSVEAESBit = 29,
  Feature_HasSVESM4Bit = 30,
  Feature_HasSVESHA3Bit = 98,
  Feature_HasSVEBitPermBit = 40,
  Feature_HasSMEandIsNonStreamingSafeBit = 60,
  Feature_HasSMEBit = 53,
  Feature_HasSMEF64F64Bit = 55,
  Feature_HasSMEF16F16Bit = 57,
  Feature_HasSMEI16I64Bit = 58,
  Feature_HasSME2andIsNonStreamingSafeBit = 64,
  Feature_HasSME2Bit = 62,
  Feature_HasSME2p1Bit = 66,
  Feature_HasFP8Bit = 21,
  Feature_HasFAMINMAXBit = 22,
  Feature_HasFP8FMABit = 23,
  Feature_HasSSVE_FP8FMABit = 50,
  Feature_HasFP8DOT2Bit = 24,
  Feature_HasSSVE_FP8DOT2Bit = 44,
  Feature_HasFP8DOT4Bit = 25,
  Feature_HasSSVE_FP8DOT4Bit = 51,
  Feature_HasLUTBit = 52,
  Feature_HasSME_LUTv2Bit = 65,
  Feature_HasSMEF8F16Bit = 56,
  Feature_HasSMEF8F32Bit = 54,
  Feature_HasSME_MOP4Bit = 59,
  Feature_HasSME_TMOPBit = 63,
  Feature_HasCMPBRBit = 88,
  Feature_HasFPRCVTBit = 14,
  Feature_HasLSFEBit = 34,
  Feature_HasSVE_or_SMEBit = 0,
  Feature_HasNonStreamingSVE_or_SME2p1Bit = 97,
  Feature_HasNonStreamingSVE_or_SME2p2Bit = 41,
  Feature_HasNonStreamingSVE_or_SSVE_AESBit = 28,
  Feature_HasNonStreamingSVE_or_SSVE_BitPermBit = 39,
  Feature_HasNonStreamingSVE_or_SSVE_FEXPABit = 43,
  Feature_HasSVE2_or_SMEBit = 36,
  Feature_HasNonStreamingSVE2_or_SME2Bit = 49,
  Feature_HasSVE2p1_or_SMEBit = 61,
  Feature_HasSVE2p1_or_SME2Bit = 46,
  Feature_HasSVE2p1_or_SME2p1Bit = 48,
  Feature_HasSVE2p1_or_StreamingSME2Bit = 31,
  Feature_HasSVE2p2_or_SME2p2Bit = 35,
  Feature_HasNonStreamingSVE2p2_or_SME2p2Bit = 42,
  Feature_HasSMEF16F16_or_SMEF8F16Bit = 99,
  Feature_HasNEONandIsStreamingSafeBit = 17,
  Feature_HasNEONandIsSME2p2StreamingSafeBit = 77,
  Feature_HasRCPCBit = 89,
  Feature_HasFRInt3264Bit = 15,
  Feature_HasMTEBit = 11,
  Feature_HasTMEBit = 9,
  Feature_HasMatMulInt8Bit = 3,
  Feature_HasMatMulFP32Bit = 96,
  Feature_HasMatMulFP64Bit = 45,
  Feature_HasLS64Bit = 84,
  Feature_HasHBCBit = 12,
  Feature_HasRCPC3Bit = 85,
  Feature_HasGCSBit = 1,
  Feature_HasCPABit = 86,
  Feature_IsLEBit = 75,
  Feature_IsBEBit = 80,
  Feature_UseExperimentalZeroingPseudosBit = 38,
  Feature_UseAlternateSExtLoadCVTF32Bit = 79,
  Feature_UseScalarIncVLBit = 37,
  Feature_NoUseScalarIncVLBit = 93,
  Feature_HasFastIncVLBit = 94,
  Feature_UseSVEFPLD1RBit = 92,
  Feature_UseLDAPURBit = 91,
  Feature_AllowMisalignedMemAccessesBit = 95,
  Feature_NotForCodeSizeBit = 78,
  Feature_UseSTRQroBit = 76,
  Feature_TailCallX16X17Bit = 71,
  Feature_TailCallX17Bit = 82,
  Feature_TailCallNotX16Bit = 83,
  Feature_TailCallAnyBit = 70,
  Feature_SLSBLRMitigationBit = 74,
  Feature_NoSLSBLRMitigationBit = 73,
  Feature_OptimizedGISelOrOtherSelectorBit = 72,
};

PredicateBitset AArch64InstructionSelector::
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
  PredicateBitset Features{};
  if (Subtarget->hasPAuth())
    Features.set(Feature_HasPAuthBit);
  if (Subtarget->hasJS())
    Features.set(Feature_HasJSBit);
  if (Subtarget->hasComplxNum())
    Features.set(Feature_HasComplxNumBit);
  if (Subtarget->hasRCPC_IMMO())
    Features.set(Feature_HasRCPC_IMMOBit);
  if (Subtarget->hasFPARMv8())
    Features.set(Feature_HasFPARMv8Bit);
  if (Subtarget->isNeonAvailable())
    Features.set(Feature_HasNEONBit);
  if (Subtarget->hasSM4())
    Features.set(Feature_HasSM4Bit);
  if (Subtarget->hasSHA3())
    Features.set(Feature_HasSHA3Bit);
  if (Subtarget->hasSHA2())
    Features.set(Feature_HasSHA2Bit);
  if (Subtarget->hasAES())
    Features.set(Feature_HasAESBit);
  if (Subtarget->hasDotProd())
    Features.set(Feature_HasDotProdBit);
  if (Subtarget->hasCRC())
    Features.set(Feature_HasCRCBit);
  if (Subtarget->hasCSSC())
    Features.set(Feature_HasCSSCBit);
  if (!Subtarget->hasCSSC())
    Features.set(Feature_HasNoCSSCBit);
  if (Subtarget->hasLSE())
    Features.set(Feature_HasLSEBit);
  if (!Subtarget->hasLSE())
    Features.set(Feature_HasNoLSEBit);
  if (Subtarget->hasRDM())
    Features.set(Feature_HasRDMBit);
  if (Subtarget->hasFullFP16())
    Features.set(Feature_HasFullFP16Bit);
  if (!Subtarget->hasFullFP16())
    Features.set(Feature_HasNoFullFP16Bit);
  if (Subtarget->hasFP16FML())
    Features.set(Feature_HasFP16FMLBit);
  if (Subtarget->hasFuseAES())
    Features.set(Feature_HasFuseAESBit);
  if (Subtarget->isSVEAvailable())
    Features.set(Feature_HasSVEBit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2())
    Features.set(Feature_HasSVE2Bit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1())
    Features.set(Feature_HasSVE2p1Bit);
  if (Subtarget->hasSVEAES())
    Features.set(Feature_HasSVEAESBit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVESM4())
    Features.set(Feature_HasSVESM4Bit);
  if (Subtarget->hasSVESHA3())
    Features.set(Feature_HasSVESHA3Bit);
  if (Subtarget->hasSVEBitPerm())
    Features.set(Feature_HasSVEBitPermBit);
  if (Subtarget->hasSME())
    Features.set(Feature_HasSMEandIsNonStreamingSafeBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME())
    Features.set(Feature_HasSMEBit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF64F64())
    Features.set(Feature_HasSMEF64F64Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF16F16())
    Features.set(Feature_HasSMEF16F16Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEI16I64())
    Features.set(Feature_HasSMEI16I64Bit);
  if (Subtarget->hasSME2())
    Features.set(Feature_HasSME2andIsNonStreamingSafeBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME2())
    Features.set(Feature_HasSME2Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSME2p1())
    Features.set(Feature_HasSME2p1Bit);
  if (Subtarget->hasFP8())
    Features.set(Feature_HasFP8Bit);
  if (Subtarget->hasFAMINMAX())
    Features.set(Feature_HasFAMINMAXBit);
  if (Subtarget->hasFP8FMA())
    Features.set(Feature_HasFP8FMABit);
  if (Subtarget->hasSSVE_FP8FMA() || (Subtarget->hasSVE2() && Subtarget->hasFP8FMA()))
    Features.set(Feature_HasSSVE_FP8FMABit);
  if (Subtarget->hasFP8DOT2())
    Features.set(Feature_HasFP8DOT2Bit);
  if (Subtarget->hasSSVE_FP8DOT2() || (Subtarget->hasSVE2() && Subtarget->hasFP8DOT2()))
    Features.set(Feature_HasSSVE_FP8DOT2Bit);
  if (Subtarget->hasFP8DOT4())
    Features.set(Feature_HasFP8DOT4Bit);
  if (Subtarget->hasSSVE_FP8DOT4() || (Subtarget->hasSVE2() && Subtarget->hasFP8DOT4()))
    Features.set(Feature_HasSSVE_FP8DOT4Bit);
  if (Subtarget->hasLUT())
    Features.set(Feature_HasLUTBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME_LUTv2())
    Features.set(Feature_HasSME_LUTv2Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF8F16())
    Features.set(Feature_HasSMEF8F16Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF8F32())
    Features.set(Feature_HasSMEF8F32Bit);
  if ((Subtarget->isStreaming() && Subtarget->hasSME_MOP4()))
    Features.set(Feature_HasSME_MOP4Bit);
  if ((Subtarget->isStreaming() && Subtarget->hasSME_TMOP()))
    Features.set(Feature_HasSME_TMOPBit);
  if (Subtarget->hasCMPBR())
    Features.set(Feature_HasCMPBRBit);
  if (Subtarget->hasFPRCVT())
    Features.set(Feature_HasFPRCVTBit);
  if (Subtarget->hasLSFE())
    Features.set(Feature_HasLSFEBit);
  if (Subtarget->isSVEorStreamingSVEAvailable())
    Features.set(Feature_HasSVE_or_SMEBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1()))
    Features.set(Feature_HasNonStreamingSVE_or_SME2p1Bit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNonStreamingSVE_or_SME2p2Bit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_AESBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_BitPermBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_FEXPABit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME()))
    Features.set(Feature_HasSVE2_or_SMEBit);
  if ((Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2()))
    Features.set(Feature_HasNonStreamingSVE2_or_SME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME()))
    Features.set(Feature_HasSVE2p1_or_SMEBit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2()))
    Features.set(Feature_HasSVE2p1_or_SME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2p1()))
    Features.set(Feature_HasSVE2p1_or_SME2p1Bit);
  if ((Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVE2p1()) ||(Subtarget->isStreaming() && Subtarget->hasSME2()))
    Features.set(Feature_HasSVE2p1_or_StreamingSME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2()))
    Features.set(Feature_HasSVE2p2_or_SME2p2Bit);
  if ((Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNonStreamingSVE2p2_or_SME2p2Bit);
  if (Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16()))
    Features.set(Feature_HasSMEF16F16_or_SMEF8F16Bit);
  if (Subtarget->hasNEON())
    Features.set(Feature_HasNEONandIsStreamingSafeBit);
  if (Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNEONandIsSME2p2StreamingSafeBit);
  if (Subtarget->hasRCPC())
    Features.set(Feature_HasRCPCBit);
  if (Subtarget->hasFRInt3264())
    Features.set(Feature_HasFRInt3264Bit);
  if (Subtarget->hasMTE())
    Features.set(Feature_HasMTEBit);
  if (Subtarget->hasTME())
    Features.set(Feature_HasTMEBit);
  if (Subtarget->hasMatMulInt8())
    Features.set(Feature_HasMatMulInt8Bit);
  if (Subtarget->hasMatMulFP32())
    Features.set(Feature_HasMatMulFP32Bit);
  if (Subtarget->hasMatMulFP64())
    Features.set(Feature_HasMatMulFP64Bit);
  if (Subtarget->hasLS64())
    Features.set(Feature_HasLS64Bit);
  if (Subtarget->hasHBC())
    Features.set(Feature_HasHBCBit);
  if (Subtarget->hasRCPC3())
    Features.set(Feature_HasRCPC3Bit);
  if (Subtarget->hasGCS())
    Features.set(Feature_HasGCSBit);
  if (Subtarget->hasCPA())
    Features.set(Feature_HasCPABit);
  if (Subtarget->isLittleEndian())
    Features.set(Feature_IsLEBit);
  if (!Subtarget->isLittleEndian())
    Features.set(Feature_IsBEBit);
  if (Subtarget->useExperimentalZeroingPseudos())
    Features.set(Feature_UseExperimentalZeroingPseudosBit);
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
    Features.set(Feature_UseAlternateSExtLoadCVTF32Bit);
  if (Subtarget->useScalarIncVL())
    Features.set(Feature_UseScalarIncVLBit);
  if (!Subtarget->useScalarIncVL())
    Features.set(Feature_NoUseScalarIncVLBit);
  if (!Subtarget->hasDisableFastIncVL())
    Features.set(Feature_HasFastIncVLBit);
  if (!Subtarget->noSVEFPLD1R())
    Features.set(Feature_UseSVEFPLD1RBit);
  if (!Subtarget->avoidLDAPUR())
    Features.set(Feature_UseLDAPURBit);
  if (!Subtarget->requiresStrictAlign())
    Features.set(Feature_AllowMisalignedMemAccessesBit);
  return Features;
}

void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset AArch64InstructionSelector::
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features{};
  if (!shouldOptForSize(MF))
    Features.set(Feature_NotForCodeSizeBit);
  if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF))
    Features.set(Feature_UseSTRQroBit);
  if (  MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallX16X17Bit);
  if ( MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallX17Bit);
  if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallNotX16Bit);
  if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallAnyBit);
  if ( MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
    Features.set(Feature_SLSBLRMitigationBit);
  if ( !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
    Features.set(Feature_NoSLSBLRMitigationBit);
  if (!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized())
    Features.set(Feature_OptimizedGISelOrOtherSelectorBit);
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HasAES,
  GIFBS_HasCPA,
  GIFBS_HasCRC,
  GIFBS_HasCSSC,
  GIFBS_HasDotProd,
  GIFBS_HasFP8,
  GIFBS_HasFP8DOT2,
  GIFBS_HasFP8DOT4,
  GIFBS_HasFP8FMA,
  GIFBS_HasFPARMv8,
  GIFBS_HasFRInt3264,
  GIFBS_HasFullFP16,
  GIFBS_HasFuseAES,
  GIFBS_HasGCS,
  GIFBS_HasLSE,
  GIFBS_HasLSFE,
  GIFBS_HasLUT,
  GIFBS_HasMTE,
  GIFBS_HasMatMulInt8,
  GIFBS_HasNEON,
  GIFBS_HasNEONandIsSME2p2StreamingSafe,
  GIFBS_HasNEONandIsStreamingSafe,
  GIFBS_HasNoCSSC,
  GIFBS_HasNoFullFP16,
  GIFBS_HasNoLSE,
  GIFBS_HasNonStreamingSVE2p2_or_SME2p2,
  GIFBS_HasNonStreamingSVE_or_SME2p2,
  GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA,
  GIFBS_HasPAuth,
  GIFBS_HasRCPC,
  GIFBS_HasRCPC_IMMO,
  GIFBS_HasRDM,
  GIFBS_HasSHA2,
  GIFBS_HasSHA3,
  GIFBS_HasSM4,
  GIFBS_HasSME,
  GIFBS_HasSME2,
  GIFBS_HasSMEF16F16,
  GIFBS_HasSMEF64F64,
  GIFBS_HasSMEF8F16,
  GIFBS_HasSMEF8F32,
  GIFBS_HasSMEI16I64,
  GIFBS_HasSME_MOP4,
  GIFBS_HasSMEandIsNonStreamingSafe,
  GIFBS_HasSSVE_FP8DOT2,
  GIFBS_HasSSVE_FP8DOT4,
  GIFBS_HasSSVE_FP8FMA,
  GIFBS_HasSVE,
  GIFBS_HasSVE2,
  GIFBS_HasSVE2_or_SME,
  GIFBS_HasSVE2p1_or_SME,
  GIFBS_HasSVE2p1_or_SME2,
  GIFBS_HasSVE2p1_or_SME2p1,
  GIFBS_HasSVESM4,
  GIFBS_HasSVE_or_SME,
  GIFBS_HasTME,
  GIFBS_IsBE,
  GIFBS_IsLE,
  GIFBS_OptimizedGISelOrOtherSelector,
  GIFBS_UseSTRQro,
  GIFBS_HasComplxNum_HasNEON,
  GIFBS_HasFAMINMAX_HasNEON,
  GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasFP16FML_HasNEON,
  GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasFPARMv8_HasJS,
  GIFBS_HasFPRCVT_HasNEON,
  GIFBS_HasFullFP16_HasNEON,
  GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe,
  GIFBS_HasFullFP16_HasNEONandIsStreamingSafe,
  GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasMatMulFP32_HasSVE,
  GIFBS_HasMatMulFP64_HasSVE,
  GIFBS_HasMatMulFP64_HasSVE_or_SME,
  GIFBS_HasMatMulInt8_HasSVE,
  GIFBS_HasMatMulInt8_HasSVE_or_SME,
  GIFBS_HasNEON_HasRCPC3,
  GIFBS_HasNEON_HasRDM,
  GIFBS_HasNonStreamingSVE_or_SME2p1_HasSVESHA3,
  GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES,
  GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm,
  GIFBS_HasRCPC_IMMO_UseLDAPUR,
  GIFBS_HasSMEF16F16_HasSME_MOP4,
  GIFBS_HasSMEF64F64_HasSME_MOP4,
  GIFBS_HasSMEF8F16_HasSME_MOP4,
  GIFBS_HasSMEF8F32_HasSME_MOP4,
  GIFBS_HasSMEI16I64_HasSME_MOP4,
  GIFBS_HasSVE_or_SME_IsLE,
  GIFBS_HasSVE_or_SME_UseScalarIncVL,
  GIFBS_IsLE_UseSTRQro,
  GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE,
  GIFBS_HasComplxNum_HasFullFP16_HasNEON,
  GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HasAESBit, },
  {Feature_HasCPABit, },
  {Feature_HasCRCBit, },
  {Feature_HasCSSCBit, },
  {Feature_HasDotProdBit, },
  {Feature_HasFP8Bit, },
  {Feature_HasFP8DOT2Bit, },
  {Feature_HasFP8DOT4Bit, },
  {Feature_HasFP8FMABit, },
  {Feature_HasFPARMv8Bit, },
  {Feature_HasFRInt3264Bit, },
  {Feature_HasFullFP16Bit, },
  {Feature_HasFuseAESBit, },
  {Feature_HasGCSBit, },
  {Feature_HasLSEBit, },
  {Feature_HasLSFEBit, },
  {Feature_HasLUTBit, },
  {Feature_HasMTEBit, },
  {Feature_HasMatMulInt8Bit, },
  {Feature_HasNEONBit, },
  {Feature_HasNEONandIsSME2p2StreamingSafeBit, },
  {Feature_HasNEONandIsStreamingSafeBit, },
  {Feature_HasNoCSSCBit, },
  {Feature_HasNoFullFP16Bit, },
  {Feature_HasNoLSEBit, },
  {Feature_HasNonStreamingSVE2p2_or_SME2p2Bit, },
  {Feature_HasNonStreamingSVE_or_SME2p2Bit, },
  {Feature_HasNonStreamingSVE_or_SSVE_FEXPABit, },
  {Feature_HasPAuthBit, },
  {Feature_HasRCPCBit, },
  {Feature_HasRCPC_IMMOBit, },
  {Feature_HasRDMBit, },
  {Feature_HasSHA2Bit, },
  {Feature_HasSHA3Bit, },
  {Feature_HasSM4Bit, },
  {Feature_HasSMEBit, },
  {Feature_HasSME2Bit, },
  {Feature_HasSMEF16F16Bit, },
  {Feature_HasSMEF64F64Bit, },
  {Feature_HasSMEF8F16Bit, },
  {Feature_HasSMEF8F32Bit, },
  {Feature_HasSMEI16I64Bit, },
  {Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEandIsNonStreamingSafeBit, },
  {Feature_HasSSVE_FP8DOT2Bit, },
  {Feature_HasSSVE_FP8DOT4Bit, },
  {Feature_HasSSVE_FP8FMABit, },
  {Feature_HasSVEBit, },
  {Feature_HasSVE2Bit, },
  {Feature_HasSVE2_or_SMEBit, },
  {Feature_HasSVE2p1_or_SMEBit, },
  {Feature_HasSVE2p1_or_SME2Bit, },
  {Feature_HasSVE2p1_or_SME2p1Bit, },
  {Feature_HasSVESM4Bit, },
  {Feature_HasSVE_or_SMEBit, },
  {Feature_HasTMEBit, },
  {Feature_IsBEBit, },
  {Feature_IsLEBit, },
  {Feature_OptimizedGISelOrOtherSelectorBit, },
  {Feature_UseSTRQroBit, },
  {Feature_HasComplxNumBit, Feature_HasNEONBit, },
  {Feature_HasFAMINMAXBit, Feature_HasNEONBit, },
  {Feature_HasFAMINMAXBit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasFP16FMLBit, Feature_HasNEONBit, },
  {Feature_HasFP8Bit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasFPARMv8Bit, Feature_HasJSBit, },
  {Feature_HasFPRCVTBit, Feature_HasNEONBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONandIsSME2p2StreamingSafeBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONandIsStreamingSafeBit, },
  {Feature_HasLUTBit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasMatMulFP32Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulFP64Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulFP64Bit, Feature_HasSVE_or_SMEBit, },
  {Feature_HasMatMulInt8Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulInt8Bit, Feature_HasSVE_or_SMEBit, },
  {Feature_HasNEONBit, Feature_HasRCPC3Bit, },
  {Feature_HasNEONBit, Feature_HasRDMBit, },
  {Feature_HasNonStreamingSVE_or_SME2p1Bit, Feature_HasSVESHA3Bit, },
  {Feature_HasNonStreamingSVE_or_SSVE_AESBit, Feature_HasSVEAESBit, },
  {Feature_HasNonStreamingSVE_or_SSVE_BitPermBit, Feature_HasSVEBitPermBit, },
  {Feature_HasRCPC_IMMOBit, Feature_UseLDAPURBit, },
  {Feature_HasSMEF16F16Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF64F64Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF8F16Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF8F32Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEI16I64Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSVE_or_SMEBit, Feature_IsLEBit, },
  {Feature_HasSVE_or_SMEBit, Feature_UseScalarIncVLBit, },
  {Feature_IsLEBit, Feature_UseSTRQroBit, },
  {Feature_AllowMisalignedMemAccessesBit, Feature_HasSVE_or_SMEBit, Feature_IsLEBit, },
  {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
  {Feature_HasNEONBit, Feature_NotForCodeSizeBit, Feature_UseAlternateSExtLoadCVTF32Bit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
  GICP_gi_addsub_shifted_imm32,
  GICP_gi_addsub_shifted_imm64,
  GICP_gi_am_indexed128,
  GICP_gi_am_indexed16,
  GICP_gi_am_indexed32,
  GICP_gi_am_indexed64,
  GICP_gi_am_indexed8,
  GICP_gi_am_unscaled128,
  GICP_gi_am_unscaled16,
  GICP_gi_am_unscaled32,
  GICP_gi_am_unscaled64,
  GICP_gi_am_unscaled8,
  GICP_gi_arith_extended_reg32_i32,
  GICP_gi_arith_extended_reg32_i64,
  GICP_gi_arith_extended_reg32to64_i64,
  GICP_gi_arith_shifted_reg32,
  GICP_gi_arith_shifted_reg64,
  GICP_gi_extract_high_v16i8,
  GICP_gi_extract_high_v4f32,
  GICP_gi_extract_high_v4i32,
  GICP_gi_extract_high_v8f16,
  GICP_gi_extract_high_v8i16,
  GICP_gi_logical_shifted_reg32,
  GICP_gi_logical_shifted_reg64,
  GICP_gi_neg_addsub_shifted_imm32,
  GICP_gi_neg_addsub_shifted_imm64,
  GICP_gi_ro_Windexed128,
  GICP_gi_ro_Windexed16,
  GICP_gi_ro_Windexed32,
  GICP_gi_ro_Windexed64,
  GICP_gi_ro_Windexed8,
  GICP_gi_ro_Xindexed128,
  GICP_gi_ro_Xindexed16,
  GICP_gi_ro_Xindexed32,
  GICP_gi_ro_Xindexed64,
  GICP_gi_ro_Xindexed8,
};
// See constructor for table contents

AArch64InstructionSelector::ComplexMatcherMemFn
AArch64InstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64
  &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32
  &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v16i8
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4f32
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4i32
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8f16
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8i16
  &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32
  &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64
  &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32
  &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64
  &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128
  &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16
  &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32
  &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64
  &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8
  &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128
  &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16
  &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32
  &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64
  &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8
};

// PatFrag predicates.
enum {
  GICXXPred_MI_Predicate_add_and_or_is_add = GICXXPred_Invalid + 1,
  GICXXPred_MI_Predicate_ldaxr_1,
  GICXXPred_MI_Predicate_ldaxr_2,
  GICXXPred_MI_Predicate_ldaxr_4,
  GICXXPred_MI_Predicate_ldaxr_8,
  GICXXPred_MI_Predicate_ldxr_1,
  GICXXPred_MI_Predicate_ldxr_2,
  GICXXPred_MI_Predicate_ldxr_4,
  GICXXPred_MI_Predicate_ldxr_8,
  GICXXPred_MI_Predicate_or_disjoint,
  GICXXPred_MI_Predicate_stlxr_1,
  GICXXPred_MI_Predicate_stlxr_2,
  GICXXPred_MI_Predicate_stlxr_4,
  GICXXPred_MI_Predicate_stlxr_8,
  GICXXPred_MI_Predicate_stxr_1,
  GICXXPred_MI_Predicate_stxr_2,
  GICXXPred_MI_Predicate_stxr_4,
  GICXXPred_MI_Predicate_stxr_8,
};
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  switch (PredicateID) {
  case GICXXPred_MI_Predicate_add_and_or_is_add: {
    
         return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));
      
  }
  case GICXXPred_MI_Predicate_ldaxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_ldaxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_ldaxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_ldaxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_ldxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_ldxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_ldxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_ldxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_or_disjoint: {
    
        return MI.getFlag(MachineInstr::Disjoint);
      
  }
  case GICXXPred_MI_Predicate_stlxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_stlxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_stlxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_stlxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_stxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_stxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_stxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_stxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_MO_Predicate_top16Zero = GICXXPred_Invalid + 1,
  GICXXPred_MO_Predicate_top32Zero,
  GICXXPred_MO_Predicate_topbitsallzero32,
  GICXXPred_MO_Predicate_topbitsallzero64,
};
bool AArch64InstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
  const auto &Operands = State.RecordedOperands;
  Register Reg = MO.getReg();
  (void)Operands;
  (void)Reg;
  switch (PredicateID) {
  case GICXXPred_MO_Predicate_top16Zero: {
    
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16)); 
  }
  case GICXXPred_MO_Predicate_top32Zero: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32)); 
  }
  case GICXXPred_MO_Predicate_topbitsallzero32: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31)); 
  }
  case GICXXPred_MO_Predicate_topbitsallzero64: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63)); 
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_VectorIndex0 = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_VectorIndex0_timm,
  GICXXPred_I64_Predicate_VectorIndex1,
  GICXXPred_I64_Predicate_VectorIndex1_timm,
  GICXXPred_I64_Predicate_VectorIndex032b,
  GICXXPred_I64_Predicate_VectorIndex032b_timm,
  GICXXPred_I64_Predicate_VectorIndex132b,
  GICXXPred_I64_Predicate_VectorIndex132b_timm,
  GICXXPred_I64_Predicate_VectorIndexB,
  GICXXPred_I64_Predicate_VectorIndexB32b,
  GICXXPred_I64_Predicate_VectorIndexB32b_timm,
  GICXXPred_I64_Predicate_VectorIndexB_timm,
  GICXXPred_I64_Predicate_VectorIndexD,
  GICXXPred_I64_Predicate_VectorIndexD32b,
  GICXXPred_I64_Predicate_VectorIndexD32b_timm,
  GICXXPred_I64_Predicate_VectorIndexD_timm,
  GICXXPred_I64_Predicate_VectorIndexH,
  GICXXPred_I64_Predicate_VectorIndexH32b,
  GICXXPred_I64_Predicate_VectorIndexH32b_timm,
  GICXXPred_I64_Predicate_VectorIndexH_timm,
  GICXXPred_I64_Predicate_VectorIndexS,
  GICXXPred_I64_Predicate_VectorIndexS32b,
  GICXXPred_I64_Predicate_VectorIndexS32b_timm,
  GICXXPred_I64_Predicate_VectorIndexS_timm,
  GICXXPred_I64_Predicate_complexrotateop,
  GICXXPred_I64_Predicate_complexrotateopodd,
  GICXXPred_I64_Predicate_extq_timm32_0_1m8,
  GICXXPred_I64_Predicate_extq_timm32_0_3m4,
  GICXXPred_I64_Predicate_extq_timm32_0_7m2,
  GICXXPred_I64_Predicate_i64imm_32bit,
  GICXXPred_I64_Predicate_i64imm_32bit_tgt,
  GICXXPred_I64_Predicate_imm0_1,
  GICXXPred_I64_Predicate_imm0_3,
  GICXXPred_I64_Predicate_imm0_7,
  GICXXPred_I64_Predicate_imm0_15,
  GICXXPred_I64_Predicate_imm0_31,
  GICXXPred_I64_Predicate_imm0_63,
  GICXXPred_I64_Predicate_imm0_127,
  GICXXPred_I64_Predicate_imm0_127_64b,
  GICXXPred_I64_Predicate_imm0_255,
  GICXXPred_I64_Predicate_imm32_0_7,
  GICXXPred_I64_Predicate_imm32_0_15,
  GICXXPred_I64_Predicate_imm32_0_31,
  GICXXPred_I64_Predicate_imm64_0_65535,
  GICXXPred_I64_Predicate_maski8_or_more,
  GICXXPred_I64_Predicate_maski16_or_more,
  GICXXPred_I64_Predicate_rprfop,
  GICXXPred_I64_Predicate_s64imm_32bit,
  GICXXPred_I64_Predicate_simm4s1,
  GICXXPred_I64_Predicate_simm4s2,
  GICXXPred_I64_Predicate_simm4s3,
  GICXXPred_I64_Predicate_simm4s4,
  GICXXPred_I64_Predicate_simm4s16,
  GICXXPred_I64_Predicate_simm4s32,
  GICXXPred_I64_Predicate_simm5_8b,
  GICXXPred_I64_Predicate_simm5_8b_tgt,
  GICXXPred_I64_Predicate_simm5_16b,
  GICXXPred_I64_Predicate_simm5_16b_tgt,
  GICXXPred_I64_Predicate_simm5_32b,
  GICXXPred_I64_Predicate_simm5_32b_tgt,
  GICXXPred_I64_Predicate_simm5_64b,
  GICXXPred_I64_Predicate_simm5_64b_tgt,
  GICXXPred_I64_Predicate_simm6_32b,
  GICXXPred_I64_Predicate_simm6s1,
  GICXXPred_I64_Predicate_simm8_32b,
  GICXXPred_I64_Predicate_simm8_64b,
  GICXXPred_I64_Predicate_simm9,
  GICXXPred_I64_Predicate_sme_elm_idx0_0,
  GICXXPred_I64_Predicate_sme_elm_idx0_1,
  GICXXPred_I64_Predicate_sme_elm_idx0_3,
  GICXXPred_I64_Predicate_sme_elm_idx0_7,
  GICXXPred_I64_Predicate_sme_elm_idx0_15,
  GICXXPred_I64_Predicate_svcr_op,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_b,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_d,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_h,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_q,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_s,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm,
  GICXXPred_I64_Predicate_sve_incdec_imm,
  GICXXPred_I64_Predicate_sve_pred_enum,
  GICXXPred_I64_Predicate_sve_prfop,
  GICXXPred_I64_Predicate_sve_vec_len_specifier_enum,
  GICXXPred_I64_Predicate_tbz_imm0_31_diag,
  GICXXPred_I64_Predicate_tbz_imm0_31_nodiag,
  GICXXPred_I64_Predicate_tbz_imm32_63,
  GICXXPred_I64_Predicate_timm0_1,
  GICXXPred_I64_Predicate_timm0_31,
  GICXXPred_I64_Predicate_timm0_63,
  GICXXPred_I64_Predicate_timm32_0_0,
  GICXXPred_I64_Predicate_timm32_0_1,
  GICXXPred_I64_Predicate_timm32_0_3,
  GICXXPred_I64_Predicate_timm32_0_7,
  GICXXPred_I64_Predicate_timm32_0_15,
  GICXXPred_I64_Predicate_timm32_0_31,
  GICXXPred_I64_Predicate_timm32_0_255,
  GICXXPred_I64_Predicate_timm32_0_65535,
  GICXXPred_I64_Predicate_timm32_1_1,
  GICXXPred_I64_Predicate_timm32_1_3,
  GICXXPred_I64_Predicate_timm32_1_7,
  GICXXPred_I64_Predicate_timm64_0_65535,
  GICXXPred_I64_Predicate_tuimm5s2,
  GICXXPred_I64_Predicate_tuimm5s4,
  GICXXPred_I64_Predicate_tuimm5s8,
  GICXXPred_I64_Predicate_tvecshiftL8,
  GICXXPred_I64_Predicate_tvecshiftL16,
  GICXXPred_I64_Predicate_tvecshiftL32,
  GICXXPred_I64_Predicate_tvecshiftL64,
  GICXXPred_I64_Predicate_tvecshiftR8,
  GICXXPred_I64_Predicate_tvecshiftR16,
  GICXXPred_I64_Predicate_tvecshiftR32,
  GICXXPred_I64_Predicate_tvecshiftR64,
  GICXXPred_I64_Predicate_ubsan_trap_imm,
  GICXXPred_I64_Predicate_uimm0s2range,
  GICXXPred_I64_Predicate_uimm0s4range,
  GICXXPred_I64_Predicate_uimm1s2range,
  GICXXPred_I64_Predicate_uimm1s4range,
  GICXXPred_I64_Predicate_uimm2s2range,
  GICXXPred_I64_Predicate_uimm2s4range,
  GICXXPred_I64_Predicate_uimm3s2range,
  GICXXPred_I64_Predicate_uimm3s8,
  GICXXPred_I64_Predicate_uimm5s2,
  GICXXPred_I64_Predicate_uimm5s4,
  GICXXPred_I64_Predicate_uimm5s8,
  GICXXPred_I64_Predicate_uimm6,
  GICXXPred_I64_Predicate_uimm6_32b,
  GICXXPred_I64_Predicate_uimm6_64b,
  GICXXPred_I64_Predicate_uimm6s1,
  GICXXPred_I64_Predicate_uimm6s2,
  GICXXPred_I64_Predicate_uimm6s4,
  GICXXPred_I64_Predicate_uimm6s8,
  GICXXPred_I64_Predicate_uimm6s16,
  GICXXPred_I64_Predicate_uimm8_32b,
  GICXXPred_I64_Predicate_uimm8_64b,
  GICXXPred_I64_Predicate_uimm16,
  GICXXPred_I64_Predicate_vecshiftL8,
  GICXXPred_I64_Predicate_vecshiftL16,
  GICXXPred_I64_Predicate_vecshiftL32,
  GICXXPred_I64_Predicate_vecshiftL64,
  GICXXPred_I64_Predicate_vecshiftR8,
  GICXXPred_I64_Predicate_vecshiftR16,
  GICXXPred_I64_Predicate_vecshiftR16Narrow,
  GICXXPred_I64_Predicate_vecshiftR32,
  GICXXPred_I64_Predicate_vecshiftR32Narrow,
  GICXXPred_I64_Predicate_vecshiftR64,
  GICXXPred_I64_Predicate_vecshiftR64Narrow,
};
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_VectorIndex0: {
     return ((uint64_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex0_timm: {
     return ((uint64_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex1: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex1_timm: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex032b: {
     return ((uint32_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex032b_timm: {
     return ((uint32_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex132b: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex132b_timm: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB32b: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB32b_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD32b: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD32b_timm: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD_timm: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH32b: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH32b_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS32b: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS32b_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_complexrotateop: {
     return Imm >= 0 && Imm <= 270;  
  }
  case GICXXPred_I64_Predicate_complexrotateopodd: {
     return Imm >= 0 && Imm <= 270;  
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_1m8: {
    
      return ((uint32_t)Imm) < 2;
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_3m4: {
    
      return ((uint32_t)Imm) < 4;
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_7m2: {
    
      return ((uint32_t)Imm) < 8;
  }
  case GICXXPred_I64_Predicate_i64imm_32bit: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  case GICXXPred_I64_Predicate_i64imm_32bit_tgt: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  case GICXXPred_I64_Predicate_imm0_1: {
    
      return ((uint64_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_imm0_3: {
    
      return ((uint64_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_imm0_7: {
    
      return ((uint64_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_imm0_15: {
    
      return ((uint64_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_imm0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_imm0_63: {
    
      return ((uint64_t)Imm) < 64;
    
  }
  case GICXXPred_I64_Predicate_imm0_127: {
    
      return ((uint32_t)Imm) < 128;
    
  }
  case GICXXPred_I64_Predicate_imm0_127_64b: {
    
      return ((uint64_t)Imm) < 128;
    
  }
  case GICXXPred_I64_Predicate_imm0_255: {
    
      return ((uint32_t)Imm) < 256;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_7: {
    
      return ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_15: {
    
      return ((uint32_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_imm64_0_65535: {
    
      return ((uint64_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_maski8_or_more: {
     return (Imm & 0xff) == 0xff; 
  }
  case GICXXPred_I64_Predicate_maski16_or_more: {
     return (Imm & 0xffff) == 0xffff; 
  }
  case GICXXPred_I64_Predicate_rprfop: {
    
        return (((uint32_t)Imm) <= 63);
      
  }
  case GICXXPred_I64_Predicate_s64imm_32bit: {
    
      int64_t Imm64 = static_cast<int64_t>(Imm);
      return Imm64 >= std::numeric_limits<int32_t>::min() &&
             Imm64 <= std::numeric_limits<int32_t>::max();
    
    llvm_unreachable("s64imm_32bit should have returned");
  }
  case GICXXPred_I64_Predicate_simm4s1: {
     return Imm >=-8  && Imm <= 7; 
  }
  case GICXXPred_I64_Predicate_simm4s2: {
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s3: {
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s4: {
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s16: {
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s32: {
     return Imm >=-256  && Imm <= 224 && (Imm % 32) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm5_8b: {
     return (int8_t)Imm >= -16 && (int8_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_8b_tgt: {
     return (int8_t)Imm >= -16 && (int8_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_16b: {
     return (int16_t)Imm >= -16 && (int16_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_16b_tgt: {
     return (int16_t)Imm >= -16 && (int16_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_32b: {
     return Imm >= -16 && Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_32b_tgt: {
     return (int32_t)Imm >= -16 && (int32_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_64b: {
     return Imm >= -16 && Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_64b_tgt: {
     return (int64_t)Imm >= -16 && (int64_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm6_32b: {
     return Imm >= -32 && Imm < 32; 
  }
  case GICXXPred_I64_Predicate_simm6s1: {
     return Imm >= -32 && Imm < 32; 
  }
  case GICXXPred_I64_Predicate_simm8_32b: {
     return Imm >= -128 && Imm < 128; 
  }
  case GICXXPred_I64_Predicate_simm8_64b: {
     return Imm >= -128 && Imm < 128; 
  }
  case GICXXPred_I64_Predicate_simm9: {
     return Imm >= -256 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_0: {
    
      return ((uint32_t)Imm) == 0;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_1: {
    
      return ((uint32_t)Imm) <= 1;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_3: {
    
      return ((uint32_t)Imm) <= 3;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_7: {
    
      return ((uint32_t)Imm) <= 7;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_15: {
    
      return ((uint32_t)Imm) <= 15;
    
  }
  case GICXXPred_I64_Predicate_svcr_op: {
    
        return AArch64SVCR::lookupSVCRByEncoding(Imm) != nullptr;
      
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b: {
     return ((uint64_t)Imm) < 64; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm: {
     return ((uint64_t)Imm) < 64; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h: {
     return ((uint64_t)Imm) < 32; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm: {
     return ((uint64_t)Imm) < 32; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_sve_incdec_imm: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_sve_pred_enum: {
    
      return (((uint32_t)Imm) < 32);
      
  }
  case GICXXPred_I64_Predicate_sve_prfop: {
    
        return (((uint32_t)Imm) <= 15);
      
  }
  case GICXXPred_I64_Predicate_sve_vec_len_specifier_enum: {
    
      return (((uint32_t)Imm) < 2);
      
  }
  case GICXXPred_I64_Predicate_tbz_imm0_31_diag: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_tbz_imm0_31_nodiag: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_tbz_imm32_63: {
    
      return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
    
  }
  case GICXXPred_I64_Predicate_timm0_1: {
    
      return ((uint64_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_timm0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_timm0_63: {
    
      return ((uint64_t)Imm) < 64;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_0: {
    
      return ((uint32_t)Imm) == 0;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_1: {
    
      return ((uint32_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_3: {
    
      return ((uint32_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_7: {
    
      return ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_15: {
    
      return ((uint32_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_31: {
    
      return ((uint32_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_255: {
    
      return ((uint32_t)Imm) < 256;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_65535: {
    
      return ((uint32_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_1: {
    
        return ((uint32_t)Imm) == 1;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_3: {
    
      return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_7: {
    
      return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_timm64_0_65535: {
    
      return ((uint64_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_tuimm5s2: {
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_tuimm5s4: {
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_tuimm5s8: {
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_tvecshiftL8: {
    
      return (((uint32_t)Imm) < 8);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftL16: {
    
      return (((uint32_t)Imm) < 16);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftL32: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftL64: {
    
      return (((uint32_t)Imm) < 64);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftR8: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftR16: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftR32: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
    
  }
  case GICXXPred_I64_Predicate_tvecshiftR64: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
    
  }
  case GICXXPred_I64_Predicate_ubsan_trap_imm: {
    
      return isUInt<8>(Imm);
    
  }
  case GICXXPred_I64_Predicate_uimm0s2range: {
     return Imm == 0; 
  }
  case GICXXPred_I64_Predicate_uimm0s4range: {
     return Imm == 0; 
  }
  case GICXXPred_I64_Predicate_uimm1s2range: {
     return Imm >= 0 && Imm <= 2 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm1s4range: {
     return Imm >= 0 && Imm <= 4 && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm2s2range: {
     return Imm >= 0 && Imm <= 6 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm2s4range: {
     return Imm >= 0 && Imm <= 12 && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm3s2range: {
     return Imm >= 0 && Imm <= 14 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm3s8: {
     return Imm >= 0 && Imm <= 56 && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s2: {
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s4: {
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s8: {
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6_32b: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6_64b: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6s1: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6s2: {
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s4: {
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s8: {
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s16: {
     return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm8_32b: {
     return Imm >= 0 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_uimm8_64b: {
     return Imm >= 0 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_uimm16: {
    return Imm >= 0 && Imm < 65536;
  }
  case GICXXPred_I64_Predicate_vecshiftL8: {
    
      return (((uint32_t)Imm) < 8);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL16: {
    
      return (((uint32_t)Imm) < 16);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL32: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL64: {
    
      return (((uint32_t)Imm) < 64);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR8: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR16: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR16Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR32: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR32Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR64: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR64Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APFloat_Predicate_fpimm0 = GICXXPred_Invalid + 1,
  GICXXPred_APFloat_Predicate_fpimm16,
  GICXXPred_APFloat_Predicate_fpimm32,
  GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4,
  GICXXPred_APFloat_Predicate_fpimm64,
  GICXXPred_APFloat_Predicate_fpimm_half,
  GICXXPred_APFloat_Predicate_fpimm_minus0,
  GICXXPred_APFloat_Predicate_fpimm_one,
  GICXXPred_APFloat_Predicate_fpimm_two,
  GICXXPred_APFloat_Predicate_fpimmbf16,
  GICXXPred_APFloat_Predicate_simdimmtype10,
};
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APFloat_Predicate_fpimm0: {
    
      return Imm.isExactlyValue(+0.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm16: {
    
          return AArch64_AM::getFP16Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm32: {
    
          return AArch64_AM::getFP32Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4: {
    
          uint64_t Enc = Imm.bitcastToAPInt().getZExtValue();
          return Enc != 0 && AArch64_AM::isAdvSIMDModImmType4(Enc << 32 | Enc);
        
    llvm_unreachable("fpimm32SIMDModImmType4 should have returned");
  }
  case GICXXPred_APFloat_Predicate_fpimm64: {
    
          return AArch64_AM::getFP64Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm_half: {
    
      return Imm.isExactlyValue(+0.5);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_minus0: {
    
      return Imm.isExactlyValue(-0.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_one: {
    
      return Imm.isExactlyValue(+1.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_two: {
    
      return Imm.isExactlyValue(+2.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimmbf16: {
    
          return AArch64_AM::getFP16Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_simdimmtype10: {
    
          return AArch64_AM::isAdvSIMDModImmType10(
                     Imm.bitcastToAPInt().getZExtValue());
        
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APInt_Predicate_logical_imm32 = GICXXPred_Invalid + 1,
  GICXXPred_APInt_Predicate_logical_imm64,
};
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APInt_Predicate_logical_imm32: {
    
      return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
    
  }
  case GICXXPred_APInt_Predicate_logical_imm64: {
    
      return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool AArch64InstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("AArch64InstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
  GICR_renderFPImm16,
  GICR_renderFPImm32,
  GICR_renderFPImm32SIMDModImmType4,
  GICR_renderFPImm64,
  GICR_renderLogicalImm32,
  GICR_renderLogicalImm64,
  GICR_renderTruncImm,
  GICR_renderUbsanTrap,
};
AArch64InstructionSelector::CustomRendererFn
AArch64InstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
  &AArch64InstructionSelector::renderFPImm16,
  &AArch64InstructionSelector::renderFPImm32,
  &AArch64InstructionSelector::renderFPImm32SIMDModImmType4,
  &AArch64InstructionSelector::renderFPImm64,
  &AArch64InstructionSelector::renderLogicalImm32,
  &AArch64InstructionSelector::renderLogicalImm64,
  &AArch64InstructionSelector::renderTruncImm,
  &AArch64InstructionSelector::renderUbsanTrap,
};

bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

bool AArch64InstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("AArch64InstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24),  uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
#else
#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32),  uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
#endif
const uint8_t *AArch64InstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
     /*      0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(908), /*)*//*default:*//*Label 155*/ GIMT_Encode4(443543),
     /*     10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(3430),
     /*     14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(37037),
     /*     18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(51889),
     /*     22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(54654),
     /*     26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(54736), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(54818),
     /*     50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(62564),
     /*     54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(88103), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    114 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(100563), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    126 */ /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(108087), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    142 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(118169),
     /*    146 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(118660),
     /*    150 */ /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 12*/ GIMT_Encode4(119151),
     /*    154 */ /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 13*/ GIMT_Encode4(119419),
     /*    158 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 14*/ GIMT_Encode4(119569),
     /*    162 */ /*TargetOpcode::G_READCYCLECOUNTER*//*Label 15*/ GIMT_Encode4(120060), GIMT_Encode4(0),
     /*    170 */ /*TargetOpcode::G_LOAD*//*Label 16*/ GIMT_Encode4(120093),
     /*    174 */ /*TargetOpcode::G_SEXTLOAD*//*Label 17*/ GIMT_Encode4(129031),
     /*    178 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 18*/ GIMT_Encode4(130081), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    194 */ /*TargetOpcode::G_STORE*//*Label 19*/ GIMT_Encode4(133130), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    206 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 20*/ GIMT_Encode4(146656),
     /*    210 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 21*/ GIMT_Encode4(148007),
     /*    214 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 22*/ GIMT_Encode4(148999),
     /*    218 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 23*/ GIMT_Encode4(149991),
     /*    222 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 24*/ GIMT_Encode4(151483), GIMT_Encode4(0),
     /*    230 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 25*/ GIMT_Encode4(152975),
     /*    234 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 26*/ GIMT_Encode4(153967),
     /*    238 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 27*/ GIMT_Encode4(154959),
     /*    242 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 28*/ GIMT_Encode4(155951),
     /*    246 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 29*/ GIMT_Encode4(156943),
     /*    250 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 30*/ GIMT_Encode4(157935),
     /*    254 */ /*TargetOpcode::G_ATOMICRMW_FADD*//*Label 31*/ GIMT_Encode4(158927), GIMT_Encode4(0),
     /*    262 */ /*TargetOpcode::G_ATOMICRMW_FMAX*//*Label 32*/ GIMT_Encode4(159632),
     /*    266 */ /*TargetOpcode::G_ATOMICRMW_FMIN*//*Label 33*/ GIMT_Encode4(160337),
     /*    270 */ /*TargetOpcode::G_ATOMICRMW_FMAXIMUM*//*Label 34*/ GIMT_Encode4(161042),
     /*    274 */ /*TargetOpcode::G_ATOMICRMW_FMINIMUM*//*Label 35*/ GIMT_Encode4(161747), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    294 */ /*TargetOpcode::G_FENCE*//*Label 36*/ GIMT_Encode4(162452), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    314 */ /*TargetOpcode::G_INTRINSIC*//*Label 37*/ GIMT_Encode4(162503),
     /*    318 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 38*/ GIMT_Encode4(267690), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    330 */ /*TargetOpcode::G_ANYEXT*//*Label 39*/ GIMT_Encode4(279206),
     /*    334 */ /*TargetOpcode::G_TRUNC*//*Label 40*/ GIMT_Encode4(279496), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    350 */ /*TargetOpcode::G_CONSTANT*//*Label 41*/ GIMT_Encode4(280933),
     /*    354 */ /*TargetOpcode::G_FCONSTANT*//*Label 42*/ GIMT_Encode4(281053), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    366 */ /*TargetOpcode::G_SEXT*//*Label 43*/ GIMT_Encode4(281294),
     /*    370 */ /*TargetOpcode::G_SEXT_INREG*//*Label 44*/ GIMT_Encode4(283192),
     /*    374 */ /*TargetOpcode::G_ZEXT*//*Label 45*/ GIMT_Encode4(284846),
     /*    378 */ /*TargetOpcode::G_SHL*//*Label 46*/ GIMT_Encode4(287625),
     /*    382 */ /*TargetOpcode::G_LSHR*//*Label 47*/ GIMT_Encode4(288450),
     /*    386 */ /*TargetOpcode::G_ASHR*//*Label 48*/ GIMT_Encode4(288994), GIMT_Encode4(0),
     /*    394 */ /*TargetOpcode::G_FSHR*//*Label 49*/ GIMT_Encode4(289819),
     /*    398 */ /*TargetOpcode::G_ROTR*//*Label 50*/ GIMT_Encode4(289949), GIMT_Encode4(0),
     /*    406 */ /*TargetOpcode::G_ICMP*//*Label 51*/ GIMT_Encode4(290491), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    422 */ /*TargetOpcode::G_SELECT*//*Label 52*/ GIMT_Encode4(298268), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    466 */ /*TargetOpcode::G_UMULH*//*Label 53*/ GIMT_Encode4(299313),
     /*    470 */ /*TargetOpcode::G_SMULH*//*Label 54*/ GIMT_Encode4(299797),
     /*    474 */ /*TargetOpcode::G_UADDSAT*//*Label 55*/ GIMT_Encode4(300281),
     /*    478 */ /*TargetOpcode::G_SADDSAT*//*Label 56*/ GIMT_Encode4(300753),
     /*    482 */ /*TargetOpcode::G_USUBSAT*//*Label 57*/ GIMT_Encode4(303129),
     /*    486 */ /*TargetOpcode::G_SSUBSAT*//*Label 58*/ GIMT_Encode4(303601), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    530 */ /*TargetOpcode::G_FADD*//*Label 59*/ GIMT_Encode4(304991),
     /*    534 */ /*TargetOpcode::G_FSUB*//*Label 60*/ GIMT_Encode4(306789),
     /*    538 */ /*TargetOpcode::G_FMUL*//*Label 61*/ GIMT_Encode4(307527),
     /*    542 */ /*TargetOpcode::G_FMA*//*Label 62*/ GIMT_Encode4(312143), GIMT_Encode4(0),
     /*    550 */ /*TargetOpcode::G_FDIV*//*Label 63*/ GIMT_Encode4(328416), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    598 */ /*TargetOpcode::G_FNEG*//*Label 64*/ GIMT_Encode4(329032),
     /*    602 */ /*TargetOpcode::G_FPEXT*//*Label 65*/ GIMT_Encode4(332539),
     /*    606 */ /*TargetOpcode::G_FPTRUNC*//*Label 66*/ GIMT_Encode4(332787),
     /*    610 */ /*TargetOpcode::G_FPTOSI*//*Label 67*/ GIMT_Encode4(332975),
     /*    614 */ /*TargetOpcode::G_FPTOUI*//*Label 68*/ GIMT_Encode4(333952),
     /*    618 */ /*TargetOpcode::G_SITOFP*//*Label 69*/ GIMT_Encode4(334929),
     /*    622 */ /*TargetOpcode::G_UITOFP*//*Label 70*/ GIMT_Encode4(339557),
     /*    626 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 71*/ GIMT_Encode4(343563),
     /*    630 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 72*/ GIMT_Encode4(343883),
     /*    634 */ /*TargetOpcode::G_FABS*//*Label 73*/ GIMT_Encode4(344203), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    646 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 74*/ GIMT_Encode4(345060),
     /*    650 */ /*TargetOpcode::G_FMINNUM*//*Label 75*/ GIMT_Encode4(345342),
     /*    654 */ /*TargetOpcode::G_FMAXNUM*//*Label 76*/ GIMT_Encode4(345720),
     /*    658 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 77*/ GIMT_Encode4(346098),
     /*    662 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 78*/ GIMT_Encode4(346448),
     /*    666 */ /*TargetOpcode::G_FMINIMUM*//*Label 79*/ GIMT_Encode4(346798),
     /*    670 */ /*TargetOpcode::G_FMAXIMUM*//*Label 80*/ GIMT_Encode4(347501), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    710 */ /*TargetOpcode::G_PTR_ADD*//*Label 81*/ GIMT_Encode4(348204), GIMT_Encode4(0),
     /*    718 */ /*TargetOpcode::G_SMIN*//*Label 82*/ GIMT_Encode4(348704),
     /*    722 */ /*TargetOpcode::G_SMAX*//*Label 83*/ GIMT_Encode4(349108),
     /*    726 */ /*TargetOpcode::G_UMIN*//*Label 84*/ GIMT_Encode4(349512),
     /*    730 */ /*TargetOpcode::G_UMAX*//*Label 85*/ GIMT_Encode4(349916),
     /*    734 */ /*TargetOpcode::G_ABS*//*Label 86*/ GIMT_Encode4(350320),
     /*    738 */ /*TargetOpcode::G_LROUND*//*Label 87*/ GIMT_Encode4(351135),
     /*    742 */ /*TargetOpcode::G_LLROUND*//*Label 88*/ GIMT_Encode4(351301),
     /*    746 */ /*TargetOpcode::G_BR*//*Label 89*/ GIMT_Encode4(351400), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    762 */ /*TargetOpcode::G_EXTRACT_SUBVECTOR*//*Label 90*/ GIMT_Encode4(351416),
     /*    766 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 91*/ GIMT_Encode4(356788),
     /*    770 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 92*/ GIMT_Encode4(389710), GIMT_Encode4(0),
     /*    778 */ /*TargetOpcode::G_SPLAT_VECTOR*//*Label 93*/ GIMT_Encode4(392628), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    790 */ /*TargetOpcode::G_CTTZ*//*Label 94*/ GIMT_Encode4(394948), GIMT_Encode4(0),
     /*    798 */ /*TargetOpcode::G_CTLZ*//*Label 95*/ GIMT_Encode4(395100), GIMT_Encode4(0),
     /*    806 */ /*TargetOpcode::G_CTPOP*//*Label 96*/ GIMT_Encode4(395774),
     /*    810 */ /*TargetOpcode::G_BSWAP*//*Label 97*/ GIMT_Encode4(395934),
     /*    814 */ /*TargetOpcode::G_BITREVERSE*//*Label 98*/ GIMT_Encode4(396248),
     /*    818 */ /*TargetOpcode::G_FCEIL*//*Label 99*/ GIMT_Encode4(396402), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    866 */ /*TargetOpcode::G_FSQRT*//*Label 100*/ GIMT_Encode4(396893),
     /*    870 */ /*TargetOpcode::G_FFLOOR*//*Label 101*/ GIMT_Encode4(397193),
     /*    874 */ /*TargetOpcode::G_FRINT*//*Label 102*/ GIMT_Encode4(397684),
     /*    878 */ /*TargetOpcode::G_FNEARBYINT*//*Label 103*/ GIMT_Encode4(398175), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    906 */ /*TargetOpcode::G_STRICT_FADD*//*Label 104*/ GIMT_Encode4(398666),
     /*    910 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 105*/ GIMT_Encode4(399792),
     /*    914 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 106*/ GIMT_Encode4(400408),
     /*    918 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 107*/ GIMT_Encode4(404130), GIMT_Encode4(0),
     /*    926 */ /*TargetOpcode::G_STRICT_FMA*//*Label 108*/ GIMT_Encode4(404746),
     /*    930 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 109*/ GIMT_Encode4(420353), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    966 */ /*TargetOpcode::G_TRAP*//*Label 110*/ GIMT_Encode4(420653),
     /*    970 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 111*/ GIMT_Encode4(420667),
     /*    974 */ /*TargetOpcode::G_UBSANTRAP*//*Label 112*/ GIMT_Encode4(420688), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    986 */ /*TargetOpcode::G_VECREDUCE_FADD*//*Label 113*/ GIMT_Encode4(420713), GIMT_Encode4(0),
     /*    994 */ /*TargetOpcode::G_VECREDUCE_FMAX*//*Label 114*/ GIMT_Encode4(421023),
     /*    998 */ /*TargetOpcode::G_VECREDUCE_FMIN*//*Label 115*/ GIMT_Encode4(421194),
     /*   1002 */ /*TargetOpcode::G_VECREDUCE_FMAXIMUM*//*Label 116*/ GIMT_Encode4(421365),
     /*   1006 */ /*TargetOpcode::G_VECREDUCE_FMINIMUM*//*Label 117*/ GIMT_Encode4(421536),
     /*   1010 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 118*/ GIMT_Encode4(421707), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   1030 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 119*/ GIMT_Encode4(422836),
     /*   1034 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 120*/ GIMT_Encode4(423039),
     /*   1038 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 121*/ GIMT_Encode4(423242),
     /*   1042 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 122*/ GIMT_Encode4(423445), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3298 */ /*AArch64::G_AARCH64_PREFETCH*//*Label 123*/ GIMT_Encode4(423648), GIMT_Encode4(0),
     /*   3306 */ /*AArch64::G_BSP*//*Label 124*/ GIMT_Encode4(423788),
     /*   3310 */ /*AArch64::G_DUP*//*Label 125*/ GIMT_Encode4(424776),
     /*   3314 */ /*AArch64::G_DUPLANE16*//*Label 126*/ GIMT_Encode4(426759),
     /*   3318 */ /*AArch64::G_DUPLANE32*//*Label 127*/ GIMT_Encode4(427014),
     /*   3322 */ /*AArch64::G_DUPLANE64*//*Label 128*/ GIMT_Encode4(427269),
     /*   3326 */ /*AArch64::G_DUPLANE8*//*Label 129*/ GIMT_Encode4(427415),
     /*   3330 */ /*AArch64::G_EXT*//*Label 130*/ GIMT_Encode4(427594),
     /*   3334 */ /*AArch64::G_FCMEQ*//*Label 131*/ GIMT_Encode4(429244),
     /*   3338 */ /*AArch64::G_FCMGE*//*Label 132*/ GIMT_Encode4(429803),
     /*   3342 */ /*AArch64::G_FCMGT*//*Label 133*/ GIMT_Encode4(430895),
     /*   3346 */ /*AArch64::G_REV16*//*Label 134*/ GIMT_Encode4(431987),
     /*   3350 */ /*AArch64::G_REV32*//*Label 135*/ GIMT_Encode4(432141),
     /*   3354 */ /*AArch64::G_REV64*//*Label 136*/ GIMT_Encode4(432317),
     /*   3358 */ /*AArch64::G_SADDLP*//*Label 137*/ GIMT_Encode4(432591),
     /*   3362 */ /*AArch64::G_SADDLV*//*Label 138*/ GIMT_Encode4(432797),
     /*   3366 */ /*AArch64::G_SDOT*//*Label 139*/ GIMT_Encode4(433196),
     /*   3370 */ /*AArch64::G_SITOF*//*Label 140*/ GIMT_Encode4(433566),
     /*   3374 */ /*AArch64::G_SMULL*//*Label 141*/ GIMT_Encode4(433683),
     /*   3378 */ /*AArch64::G_TRN1*//*Label 142*/ GIMT_Encode4(434916),
     /*   3382 */ /*AArch64::G_TRN2*//*Label 143*/ GIMT_Encode4(435696),
     /*   3386 */ /*AArch64::G_UADDLP*//*Label 144*/ GIMT_Encode4(436476),
     /*   3390 */ /*AArch64::G_UADDLV*//*Label 145*/ GIMT_Encode4(436682),
     /*   3394 */ /*AArch64::G_UDOT*//*Label 146*/ GIMT_Encode4(437549),
     /*   3398 */ /*AArch64::G_UITOF*//*Label 147*/ GIMT_Encode4(437919),
     /*   3402 */ /*AArch64::G_UMULL*//*Label 148*/ GIMT_Encode4(438036),
     /*   3406 */ /*AArch64::G_UZP1*//*Label 149*/ GIMT_Encode4(439269),
     /*   3410 */ /*AArch64::G_UZP2*//*Label 150*/ GIMT_Encode4(440049),
     /*   3414 */ /*AArch64::G_VASHR*//*Label 151*/ GIMT_Encode4(440829),
     /*   3418 */ /*AArch64::G_VLSHR*//*Label 152*/ GIMT_Encode4(441527),
     /*   3422 */ /*AArch64::G_ZIP1*//*Label 153*/ GIMT_Encode4(441983),
     /*   3426 */ /*AArch64::G_ZIP2*//*Label 154*/ GIMT_Encode4(442763),
     /*   3430 */ // Label 0: @3430
     /*   3430 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 169*/ GIMT_Encode4(37036),
     /*   3441 */ /*GILLT_s32*//*Label 156*/ GIMT_Encode4(3529),
     /*   3445 */ /*GILLT_s64*//*Label 157*/ GIMT_Encode4(6308), GIMT_Encode4(0),
     /*   3453 */ /*GILLT_v2s32*//*Label 158*/ GIMT_Encode4(12248),
     /*   3457 */ /*GILLT_v2s64*//*Label 159*/ GIMT_Encode4(15856),
     /*   3461 */ /*GILLT_v4s16*//*Label 160*/ GIMT_Encode4(21758),
     /*   3465 */ /*GILLT_v4s32*//*Label 161*/ GIMT_Encode4(25256),
     /*   3469 */ /*GILLT_v8s8*//*Label 162*/ GIMT_Encode4(31434),
     /*   3473 */ /*GILLT_v8s16*//*Label 163*/ GIMT_Encode4(32284),
     /*   3477 */ /*GILLT_v16s8*//*Label 164*/ GIMT_Encode4(35862), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3497 */ /*GILLT_nxv2s64*//*Label 165*/ GIMT_Encode4(36586), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3509 */ /*GILLT_nxv4s32*//*Label 166*/ GIMT_Encode4(36958), GIMT_Encode4(0),
     /*   3517 */ /*GILLT_nxv8s16*//*Label 167*/ GIMT_Encode4(36984), GIMT_Encode4(0),
     /*   3525 */ /*GILLT_nxv16s8*//*Label 168*/ GIMT_Encode4(37010),
     /*   3529 */ // Label 156: @3529
     /*   3529 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6307),
     /*   3534 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   3537 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   3540 */   GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3573), // Rule ID 13503 //
     /*   3545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   3549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   3553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*   3560 */     // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   3560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*   3563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   3565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   3567 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   3571 */     GIR_RootConstrainSelectedInstOperands,
     /*   3572 */     // GIR_Coverage, 13503,
     /*   3572 */     GIR_EraseRootFromParent_Done,
     /*   3573 */   // Label 171: @3573
     /*   3573 */   GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3725), // Rule ID 13942 //
     /*   3578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3585 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   3589 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   3593 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   3597 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   3601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   3605 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   3608 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   3613 */     // MIs[2] pattern
     /*   3613 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   3616 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   3621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3625 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   3627 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   3627 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   3630 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   3634 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3639 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   3641 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   3644 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   3648 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3653 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   3656 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   3660 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   3663 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3668 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3673 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3678 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   3681 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   3685 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3690 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   3693 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   3697 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   3700 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   3702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   3705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   3707 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   3714 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3719 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   3724 */     // GIR_Coverage, 13942,
     /*   3724 */     GIR_EraseRootFromParent_Done,
     /*   3725 */   // Label 172: @3725
     /*   3725 */   GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3877), // Rule ID 15804 //
     /*   3730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   3741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   3745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   3749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   3753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   3757 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   3760 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   3765 */     // MIs[2] pattern
     /*   3765 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   3768 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   3773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3777 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   3779 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   3779 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   3782 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   3786 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3791 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   3793 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   3796 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   3800 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3805 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   3808 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   3812 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   3815 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3820 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3825 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3830 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   3833 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   3837 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3842 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   3845 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   3849 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   3852 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   3854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   3857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   3859 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   3866 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3871 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   3876 */     // GIR_Coverage, 15804,
     /*   3876 */     GIR_EraseRootFromParent_Done,
     /*   3877 */   // Label 173: @3877
     /*   3877 */   GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(4029), // Rule ID 15816 //
     /*   3882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   3893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   3897 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   3901 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   3905 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   3909 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   3912 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   3917 */     // MIs[2] pattern
     /*   3917 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   3920 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   3925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3929 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   3931 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   3931 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   3934 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   3938 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3943 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   3945 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   3948 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   3952 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3957 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   3960 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   3964 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   3967 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3972 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3977 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3982 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   3985 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   3989 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3994 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   3997 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4001 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4004 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4011 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4018 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4023 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4028 */     // GIR_Coverage, 15816,
     /*   4028 */     GIR_EraseRootFromParent_Done,
     /*   4029 */   // Label 174: @4029
     /*   4029 */   GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(4181), // Rule ID 15828 //
     /*   4034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4045 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4049 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4053 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4057 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4061 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4064 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   4069 */     // MIs[2] pattern
     /*   4069 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4072 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4077 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4081 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4083 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4083 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4086 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4090 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4095 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4097 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4100 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4104 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4109 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4112 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   4116 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4119 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4124 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4129 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4134 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4137 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   4141 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4146 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4149 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4153 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4156 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4163 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4170 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4175 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4180 */     // GIR_Coverage, 15828,
     /*   4180 */     GIR_EraseRootFromParent_Done,
     /*   4181 */   // Label 175: @4181
     /*   4181 */   GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(4214), // Rule ID 91 //
     /*   4186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   4190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   4194 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*   4201 */     // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   4201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*   4204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   4206 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   4208 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   4212 */     GIR_RootConstrainSelectedInstOperands,
     /*   4213 */     // GIR_Coverage, 91,
     /*   4213 */     GIR_EraseRootFromParent_Done,
     /*   4214 */   // Label 176: @4214
     /*   4214 */   GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(4366), // Rule ID 2656 //
     /*   4219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4226 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4230 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4234 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4238 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4250 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4253 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   4258 */     // MIs[2] pattern
     /*   4258 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4261 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4266 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4268 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4268 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4271 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4275 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4280 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4282 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4285 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4289 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4294 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4297 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4301 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4304 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4309 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4314 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4319 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4322 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   4326 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4331 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4334 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4338 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4341 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4348 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4355 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4360 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4365 */     // GIR_Coverage, 2656,
     /*   4365 */     GIR_EraseRootFromParent_Done,
     /*   4366 */   // Label 177: @4366
     /*   4366 */   GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(4518), // Rule ID 10068 //
     /*   4371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4378 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4382 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4386 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4390 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4394 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4398 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4402 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4405 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   4410 */     // MIs[2] pattern
     /*   4410 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4413 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4418 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4420 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4420 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4423 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4427 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4432 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4434 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4437 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4441 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4446 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4449 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4453 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4456 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4461 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4466 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   4478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4483 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4486 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4490 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4493 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4500 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4507 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4512 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4517 */     // GIR_Coverage, 10068,
     /*   4517 */     GIR_EraseRootFromParent_Done,
     /*   4518 */   // Label 178: @4518
     /*   4518 */   GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(4670), // Rule ID 10080 //
     /*   4523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4530 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4542 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4554 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4557 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   4562 */     // MIs[2] pattern
     /*   4562 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4565 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4570 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4572 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4572 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4575 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4579 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4584 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4586 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4589 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4593 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4598 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4601 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4605 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4613 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4618 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4623 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4626 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   4630 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4635 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4638 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4642 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4645 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4652 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4659 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4664 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4669 */     // GIR_Coverage, 10080,
     /*   4669 */     GIR_EraseRootFromParent_Done,
     /*   4670 */   // Label 179: @4670
     /*   4670 */   GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(4822), // Rule ID 10092 //
     /*   4675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4682 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4686 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4690 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4694 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4698 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4702 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4706 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4709 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   4714 */     // MIs[2] pattern
     /*   4714 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4717 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4722 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4724 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4724 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4727 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4731 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4736 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4738 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4741 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4745 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4750 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4753 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4757 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4765 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4770 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4775 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4778 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   4782 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4787 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4790 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4794 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4797 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4804 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4811 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4816 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4821 */     // GIR_Coverage, 10092,
     /*   4821 */     GIR_EraseRootFromParent_Done,
     /*   4822 */   // Label 180: @4822
     /*   4822 */   GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(4979), // Rule ID 15847 //
     /*   4827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   4830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4842 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4846 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4850 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4854 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   4857 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   4862 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*   4866 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   4868 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   4873 */     // MIs[2] pred
     /*   4873 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   4878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4882 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4884 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   4884 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4887 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4891 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4898 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4901 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4905 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4910 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4913 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   4917 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4920 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4925 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4930 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4935 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4938 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*   4942 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4947 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   4951 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4954 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4961 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4968 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4973 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4978 */     // GIR_Coverage, 15847,
     /*   4978 */     GIR_EraseRootFromParent_Done,
     /*   4979 */   // Label 181: @4979
     /*   4979 */   GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(5136), // Rule ID 15848 //
     /*   4984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   4987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5003 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5007 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5011 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5014 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5019 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*   5023 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5025 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5030 */     // MIs[2] pred
     /*   5030 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5039 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5041 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5041 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5044 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5048 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5053 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5055 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5058 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5062 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5067 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5070 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5074 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5077 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5082 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5087 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*   5099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5104 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5108 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5111 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5118 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5125 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5130 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5135 */     // GIR_Coverage, 15848,
     /*   5135 */     GIR_EraseRootFromParent_Done,
     /*   5136 */   // Label 182: @5136
     /*   5136 */   GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(5293), // Rule ID 15849 //
     /*   5141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5160 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5168 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5171 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5176 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*   5180 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5182 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5187 */     // MIs[2] pred
     /*   5187 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5192 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5196 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5198 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5198 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5201 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5205 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5210 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5212 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5215 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5219 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5224 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5227 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5231 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5234 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5239 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5244 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5249 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*   5256 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5261 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5265 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5275 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5282 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5287 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5292 */     // GIR_Coverage, 15849,
     /*   5292 */     GIR_EraseRootFromParent_Done,
     /*   5293 */   // Label 183: @5293
     /*   5293 */   GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(5450), // Rule ID 15850 //
     /*   5298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5305 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5309 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5313 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5317 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5321 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5325 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5328 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5333 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*   5337 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5339 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5344 */     // MIs[2] pred
     /*   5344 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5349 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5353 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5355 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5355 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5358 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5362 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5367 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5369 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5372 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5376 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5381 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5384 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5388 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5391 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5396 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5401 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5406 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5409 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*   5413 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5418 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5422 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5425 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5432 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5439 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5444 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5449 */     // GIR_Coverage, 15850,
     /*   5449 */     GIR_EraseRootFromParent_Done,
     /*   5450 */   // Label 184: @5450
     /*   5450 */   GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(5607), // Rule ID 10184 //
     /*   5455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5462 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5466 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5470 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5474 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5478 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5482 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5486 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5489 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5494 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*   5498 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5500 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5505 */     // MIs[2] pred
     /*   5505 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5510 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5512 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5512 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5515 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5519 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5524 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5526 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5529 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5533 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5538 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5541 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   5545 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5548 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5553 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5558 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5563 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5566 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*   5570 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5575 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5579 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5582 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5589 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5596 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5601 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5606 */     // GIR_Coverage, 10184,
     /*   5606 */     GIR_EraseRootFromParent_Done,
     /*   5607 */   // Label 185: @5607
     /*   5607 */   GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(5764), // Rule ID 10185 //
     /*   5612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5635 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5639 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5643 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5646 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5651 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*   5655 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5657 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5662 */     // MIs[2] pred
     /*   5662 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5667 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5669 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5669 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5672 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5676 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5681 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5683 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5686 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5690 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5695 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5698 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   5702 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5705 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5710 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5715 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5720 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5723 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*   5727 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5732 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5736 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5739 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5746 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5753 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5758 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5763 */     // GIR_Coverage, 10185,
     /*   5763 */     GIR_EraseRootFromParent_Done,
     /*   5764 */   // Label 186: @5764
     /*   5764 */   GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(5921), // Rule ID 10186 //
     /*   5769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5776 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5800 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5803 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5808 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*   5812 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5814 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5819 */     // MIs[2] pred
     /*   5819 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5824 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5826 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5826 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5829 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5833 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5838 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5840 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5843 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5847 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5852 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5855 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   5859 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5862 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5867 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5872 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5877 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5880 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*   5884 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5889 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5893 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5903 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5915 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5920 */     // GIR_Coverage, 10186,
     /*   5920 */     GIR_EraseRootFromParent_Done,
     /*   5921 */   // Label 187: @5921
     /*   5921 */   GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(6078), // Rule ID 10187 //
     /*   5926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5933 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5957 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5960 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5965 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*   5969 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5971 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5976 */     // MIs[2] pred
     /*   5976 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5981 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5983 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5983 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5986 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5990 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5995 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5997 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   6000 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   6004 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6009 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   6012 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   6016 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   6019 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6024 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6029 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6034 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   6037 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*   6041 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6046 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   6050 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   6053 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6060 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   6067 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   6077 */     // GIR_Coverage, 10187,
     /*   6077 */     GIR_EraseRootFromParent_Done,
     /*   6078 */   // Label 188: @6078
     /*   6078 */   GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(6111), // Rule ID 13507 //
     /*   6083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6087 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*   6098 */     // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
     /*   6098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
     /*   6101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6103 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6105 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*   6109 */     GIR_RootConstrainSelectedInstOperands,
     /*   6110 */     // GIR_Coverage, 13507,
     /*   6110 */     GIR_EraseRootFromParent_Done,
     /*   6111 */   // Label 189: @6111
     /*   6111 */   GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(6147), // Rule ID 14087 //
     /*   6116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*   6131 */     // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   6131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*   6134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6138 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   6142 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*   6145 */     GIR_RootConstrainSelectedInstOperands,
     /*   6146 */     // GIR_Coverage, 14087,
     /*   6146 */     GIR_EraseRootFromParent_Done,
     /*   6147 */   // Label 190: @6147
     /*   6147 */   GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(6180), // Rule ID 97 //
     /*   6152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6156 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*   6167 */     // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)  =>  (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
     /*   6167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
     /*   6170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6172 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6174 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*   6178 */     GIR_RootConstrainSelectedInstOperands,
     /*   6179 */     // GIR_Coverage, 97,
     /*   6179 */     GIR_EraseRootFromParent_Done,
     /*   6180 */   // Label 191: @6180
     /*   6180 */   GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(6216), // Rule ID 3954 //
     /*   6185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6189 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*   6200 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   6200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*   6203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6205 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6207 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   6211 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*   6214 */     GIR_RootConstrainSelectedInstOperands,
     /*   6215 */     // GIR_Coverage, 3954,
     /*   6215 */     GIR_EraseRootFromParent_Done,
     /*   6216 */   // Label 192: @6216
     /*   6216 */   GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(6249), // Rule ID 13505 //
     /*   6221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*   6236 */     // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*   6236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
     /*   6239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6243 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*   6247 */     GIR_RootConstrainSelectedInstOperands,
     /*   6248 */     // GIR_Coverage, 13505,
     /*   6248 */     GIR_EraseRootFromParent_Done,
     /*   6249 */   // Label 193: @6249
     /*   6249 */   GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6282), // Rule ID 95 //
     /*   6254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*   6269 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*   6269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
     /*   6272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6274 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6276 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*   6280 */     GIR_RootConstrainSelectedInstOperands,
     /*   6281 */     // GIR_Coverage, 95,
     /*   6281 */     GIR_EraseRootFromParent_Done,
     /*   6282 */   // Label 194: @6282
     /*   6282 */   GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(6306), // Rule ID 93 //
     /*   6287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6291 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6299 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*   6299 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDWrr),
     /*   6304 */     GIR_RootConstrainSelectedInstOperands,
     /*   6305 */     // GIR_Coverage, 93,
     /*   6305 */     GIR_Done,
     /*   6306 */   // Label 195: @6306
     /*   6306 */   GIM_Reject,
     /*   6307 */ // Label 170: @6307
     /*   6307 */ GIM_Reject,
     /*   6308 */ // Label 157: @6308
     /*   6308 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(12247),
     /*   6313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   6316 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   6319 */   GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(6455), // Rule ID 5425 //
     /*   6324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6328 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6332 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6336 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6340 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6344 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6348 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6352 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6357 */     // MIs[1] Operand 2
     /*   6357 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6368 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6372 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6376 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6380 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6384 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6388 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6392 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6397 */     // MIs[3] Operand 2
     /*   6397 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6408 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6410 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6410 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6413 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6417 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6422 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6426 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6430 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6437 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6444 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6449 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6454 */     // GIR_Coverage, 5425,
     /*   6454 */     GIR_EraseRootFromParent_Done,
     /*   6455 */   // Label 197: @6455
     /*   6455 */   GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(6591), // Rule ID 5424 //
     /*   6460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6484 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6488 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6493 */     // MIs[1] Operand 2
     /*   6493 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6504 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6508 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6512 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6516 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6520 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   6524 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6528 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6533 */     // MIs[3] Operand 2
     /*   6533 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6544 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6546 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6546 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6549 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6553 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6558 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6562 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6573 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6580 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6585 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6590 */     // GIR_Coverage, 5424,
     /*   6590 */     GIR_EraseRootFromParent_Done,
     /*   6591 */   // Label 198: @6591
     /*   6591 */   GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(6727), // Rule ID 5434 //
     /*   6596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6612 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6616 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   6620 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6624 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6629 */     // MIs[1] Operand 2
     /*   6629 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6640 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6644 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6648 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6652 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6656 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   6660 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6664 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6669 */     // MIs[3] Operand 2
     /*   6669 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6680 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6682 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6682 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6685 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv2i32_v2i64),
     /*   6689 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6694 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6698 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6702 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6709 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6716 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6721 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6726 */     // GIR_Coverage, 5434,
     /*   6726 */     GIR_EraseRootFromParent_Done,
     /*   6727 */   // Label 199: @6727
     /*   6727 */   GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(6863), // Rule ID 5423 //
     /*   6732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6736 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6740 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6744 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6748 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6752 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   6756 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6760 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6765 */     // MIs[1] Operand 2
     /*   6765 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6776 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6780 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6784 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6788 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6792 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6796 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6800 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6805 */     // MIs[3] Operand 2
     /*   6805 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6816 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6818 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6830 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6834 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6838 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6845 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6852 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6857 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6862 */     // GIR_Coverage, 5423,
     /*   6862 */     GIR_EraseRootFromParent_Done,
     /*   6863 */   // Label 200: @6863
     /*   6863 */   GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(6999), // Rule ID 5422 //
     /*   6868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6872 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6876 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6880 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6884 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6888 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   6892 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6896 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6901 */     // MIs[1] Operand 2
     /*   6901 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6912 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6916 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6920 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6924 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6928 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   6932 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6936 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6941 */     // MIs[3] Operand 2
     /*   6941 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6952 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6954 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6954 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6957 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6961 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6966 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6970 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6974 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6981 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6988 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6993 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6998 */     // GIR_Coverage, 5422,
     /*   6998 */     GIR_EraseRootFromParent_Done,
     /*   6999 */   // Label 201: @6999
     /*   6999 */   GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(7067), // Rule ID 6989 //
     /*   7004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7008 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7012 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7016 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7020 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7024 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7029 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /*   7033 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   7037 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7041 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   7045 */     // MIs[2] Rn
     /*   7045 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   7050 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /*   7054 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   7056 */     // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
     /*   7056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /*   7059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*   7065 */     GIR_RootConstrainSelectedInstOperands,
     /*   7066 */     // GIR_Coverage, 6989,
     /*   7066 */     GIR_EraseRootFromParent_Done,
     /*   7067 */   // Label 202: @7067
     /*   7067 */   GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7135), // Rule ID 14245 //
     /*   7072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7080 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7084 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7088 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7092 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7097 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /*   7101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   7105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7109 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   7113 */     // MIs[2] Rn
     /*   7113 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   7118 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /*   7122 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   7124 */     // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
     /*   7124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /*   7127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*   7133 */     GIR_RootConstrainSelectedInstOperands,
     /*   7134 */     // GIR_Coverage, 14245,
     /*   7134 */     GIR_EraseRootFromParent_Done,
     /*   7135 */   // Label 203: @7135
     /*   7135 */   GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(7168), // Rule ID 13504 //
     /*   7140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*   7155 */     // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*   7155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*   7158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7160 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   7162 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   7166 */     GIR_RootConstrainSelectedInstOperands,
     /*   7167 */     // GIR_Coverage, 13504,
     /*   7167 */     GIR_EraseRootFromParent_Done,
     /*   7168 */   // Label 204: @7168
     /*   7168 */   GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(7301), // Rule ID 4006 //
     /*   7173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7193 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7197 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   7201 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   7205 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7210 */     // MIs[2] Operand 2
     /*   7210 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*   7221 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7225 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7229 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7233 */     // MIs[3] Operand 1
     /*   7233 */     // No operand predicates
     /*   7233 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7237 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7239 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7239 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   7242 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7246 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7251 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7256 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   7258 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7261 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7265 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7270 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   7276 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7281 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7291 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7294 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   7297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7299 */     GIR_RootConstrainSelectedInstOperands,
     /*   7300 */     // GIR_Coverage, 4006,
     /*   7300 */     GIR_EraseRootFromParent_Done,
     /*   7301 */   // Label 205: @7301
     /*   7301 */   GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(7396), // Rule ID 4004 //
     /*   7306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7322 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7326 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7330 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7334 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7338 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7343 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7347 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7351 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7355 */     // MIs[3] Operand 1
     /*   7355 */     // No operand predicates
     /*   7355 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7359 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7361 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7361 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7364 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7368 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7373 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7378 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7389 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7394 */     GIR_RootConstrainSelectedInstOperands,
     /*   7395 */     // GIR_Coverage, 4004,
     /*   7395 */     GIR_EraseRootFromParent_Done,
     /*   7396 */   // Label 206: @7396
     /*   7396 */   GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(7491), // Rule ID 4005 //
     /*   7401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7429 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7433 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7438 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7442 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7446 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*   7450 */     // MIs[3] Operand 1
     /*   7450 */     // No operand predicates
     /*   7450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7454 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7456 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7456 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7459 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7463 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7468 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7473 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   7478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7484 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7489 */     GIR_RootConstrainSelectedInstOperands,
     /*   7490 */     // GIR_Coverage, 4005,
     /*   7490 */     GIR_EraseRootFromParent_Done,
     /*   7491 */   // Label 207: @7491
     /*   7491 */   GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7524), // Rule ID 92 //
     /*   7496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7500 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7504 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*   7511 */     // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*   7511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*   7514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7516 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   7518 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   7522 */     GIR_RootConstrainSelectedInstOperands,
     /*   7523 */     // GIR_Coverage, 92,
     /*   7523 */     GIR_EraseRootFromParent_Done,
     /*   7524 */   // Label 208: @7524
     /*   7524 */   GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7657), // Rule ID 14097 //
     /*   7529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7533 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   7541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   7561 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   7565 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7570 */     // MIs[2] Operand 2
     /*   7570 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*   7581 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7585 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7589 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7593 */     // MIs[3] Operand 1
     /*   7593 */     // No operand predicates
     /*   7593 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7595 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7595 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   7598 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7602 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7607 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7612 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   7614 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7617 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7621 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7626 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   7632 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7637 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7647 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7650 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   7653 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   7655 */     GIR_RootConstrainSelectedInstOperands,
     /*   7656 */     // GIR_Coverage, 14097,
     /*   7656 */     GIR_EraseRootFromParent_Done,
     /*   7657 */   // Label 209: @7657
     /*   7657 */   GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7752), // Rule ID 14095 //
     /*   7662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7666 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   7674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7686 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7690 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7694 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7698 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7703 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7707 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7711 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7715 */     // MIs[3] Operand 1
     /*   7715 */     // No operand predicates
     /*   7715 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7717 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7717 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7720 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7724 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7729 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7734 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7745 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7748 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   7750 */     GIR_RootConstrainSelectedInstOperands,
     /*   7751 */     // GIR_Coverage, 14095,
     /*   7751 */     GIR_EraseRootFromParent_Done,
     /*   7752 */   // Label 210: @7752
     /*   7752 */   GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(7847), // Rule ID 14096 //
     /*   7757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7761 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7765 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   7769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7777 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7789 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7793 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7798 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7802 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7806 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*   7810 */     // MIs[3] Operand 1
     /*   7810 */     // No operand predicates
     /*   7810 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7812 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7812 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7815 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7819 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7824 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7829 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   7834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7840 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   7845 */     GIR_RootConstrainSelectedInstOperands,
     /*   7846 */     // GIR_Coverage, 14096,
     /*   7846 */     GIR_EraseRootFromParent_Done,
     /*   7847 */   // Label 211: @7847
     /*   7847 */   GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(7929), // Rule ID 13515 //
     /*   7852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7868 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7872 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7876 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7880 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7884 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7889 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7893 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7897 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   7901 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7906 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7910 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7912 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   7912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   7925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7927 */     GIR_RootConstrainSelectedInstOperands,
     /*   7928 */     // GIR_Coverage, 13515,
     /*   7928 */     GIR_EraseRootFromParent_Done,
     /*   7929 */   // Label 212: @7929
     /*   7929 */   GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(8011), // Rule ID 13516 //
     /*   7934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7962 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7966 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7971 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7975 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7979 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   7983 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7992 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7994 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   7994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   7997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7999 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8003 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8009 */     GIR_RootConstrainSelectedInstOperands,
     /*   8010 */     // GIR_Coverage, 13516,
     /*   8010 */     GIR_EraseRootFromParent_Done,
     /*   8011 */   // Label 213: @8011
     /*   8011 */   GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(8093), // Rule ID 123 //
     /*   8016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8020 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8032 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8036 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8048 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8052 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8057 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8061 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8065 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8069 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8074 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8076 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   8079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8081 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8089 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8091 */     GIR_RootConstrainSelectedInstOperands,
     /*   8092 */     // GIR_Coverage, 123,
     /*   8092 */     GIR_EraseRootFromParent_Done,
     /*   8093 */   // Label 214: @8093
     /*   8093 */   GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(8175), // Rule ID 125 //
     /*   8098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8102 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8122 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8126 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8130 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8134 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8139 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8143 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8147 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8151 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8156 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8158 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8171 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8173 */     GIR_RootConstrainSelectedInstOperands,
     /*   8174 */     // GIR_Coverage, 125,
     /*   8174 */     GIR_EraseRootFromParent_Done,
     /*   8175 */   // Label 215: @8175
     /*   8175 */   GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(8233), // Rule ID 13937 //
     /*   8180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8187 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8191 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8195 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8198 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   8203 */     // MIs[1] pattern
     /*   8203 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8206 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8215 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8217 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   8220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8231 */     GIR_RootConstrainSelectedInstOperands,
     /*   8232 */     // GIR_Coverage, 13937,
     /*   8232 */     GIR_EraseRootFromParent_Done,
     /*   8233 */   // Label 216: @8233
     /*   8233 */   GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(8291), // Rule ID 15799 //
     /*   8238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8245 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8249 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8253 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8256 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   8261 */     // MIs[1] pattern
     /*   8261 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8264 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8273 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8275 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   8278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8289 */     GIR_RootConstrainSelectedInstOperands,
     /*   8290 */     // GIR_Coverage, 15799,
     /*   8290 */     GIR_EraseRootFromParent_Done,
     /*   8291 */   // Label 217: @8291
     /*   8291 */   GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(8349), // Rule ID 15811 //
     /*   8296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8303 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8307 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8311 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8314 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   8319 */     // MIs[1] pattern
     /*   8319 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8322 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8327 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8331 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8333 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   8336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8347 */     GIR_RootConstrainSelectedInstOperands,
     /*   8348 */     // GIR_Coverage, 15811,
     /*   8348 */     GIR_EraseRootFromParent_Done,
     /*   8349 */   // Label 218: @8349
     /*   8349 */   GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(8407), // Rule ID 15823 //
     /*   8354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8369 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8372 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   8377 */     // MIs[1] pattern
     /*   8377 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8380 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8389 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8391 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   8394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8405 */     GIR_RootConstrainSelectedInstOperands,
     /*   8406 */     // GIR_Coverage, 15823,
     /*   8406 */     GIR_EraseRootFromParent_Done,
     /*   8407 */   // Label 219: @8407
     /*   8407 */   GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8504), // Rule ID 4021 //
     /*   8412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8416 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8420 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8424 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8428 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8432 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8437 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   8441 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8445 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8449 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8458 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8460 */     // (add:{ *:[i64] } (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8460 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8463 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8467 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8472 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8478 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8483 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8493 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   8500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8502 */     GIR_RootConstrainSelectedInstOperands,
     /*   8503 */     // GIR_Coverage, 4021,
     /*   8503 */     GIR_EraseRootFromParent_Done,
     /*   8504 */   // Label 220: @8504
     /*   8504 */   GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8601), // Rule ID 14107 //
     /*   8509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8521 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8525 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8537 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8541 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8546 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8555 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8557 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8557 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8560 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8564 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8569 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8575 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8580 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8590 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8593 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   8597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8599 */     GIR_RootConstrainSelectedInstOperands,
     /*   8600 */     // GIR_Coverage, 14107,
     /*   8600 */     GIR_EraseRootFromParent_Done,
     /*   8601 */   // Label 221: @8601
     /*   8601 */   GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(8659), // Rule ID 2653 //
     /*   8606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8613 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8625 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8628 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   8633 */     // MIs[1] pattern
     /*   8633 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8636 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8641 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8643 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   8646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8648 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   8650 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8657 */     GIR_RootConstrainSelectedInstOperands,
     /*   8658 */     // GIR_Coverage, 2653,
     /*   8658 */     GIR_EraseRootFromParent_Done,
     /*   8659 */   // Label 222: @8659
     /*   8659 */   GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(8717), // Rule ID 10065 //
     /*   8664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8671 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8683 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8686 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   8691 */     // MIs[1] pattern
     /*   8691 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8694 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8699 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8701 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   8704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8706 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   8708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8715 */     GIR_RootConstrainSelectedInstOperands,
     /*   8716 */     // GIR_Coverage, 10065,
     /*   8716 */     GIR_EraseRootFromParent_Done,
     /*   8717 */   // Label 223: @8717
     /*   8717 */   GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(8775), // Rule ID 10077 //
     /*   8722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8741 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8744 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   8749 */     // MIs[1] pattern
     /*   8749 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8752 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8757 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8759 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   8762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8764 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   8766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8773 */     GIR_RootConstrainSelectedInstOperands,
     /*   8774 */     // GIR_Coverage, 10077,
     /*   8774 */     GIR_EraseRootFromParent_Done,
     /*   8775 */   // Label 224: @8775
     /*   8775 */   GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8833), // Rule ID 10089 //
     /*   8780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8787 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8791 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8795 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8799 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8802 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   8807 */     // MIs[1] pattern
     /*   8807 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8810 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8815 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8817 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   8820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8822 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   8824 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8831 */     GIR_RootConstrainSelectedInstOperands,
     /*   8832 */     // GIR_Coverage, 10089,
     /*   8832 */     GIR_EraseRootFromParent_Done,
     /*   8833 */   // Label 225: @8833
     /*   8833 */   GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(8930), // Rule ID 14108 //
     /*   8838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8842 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8846 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8850 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8854 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8858 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8862 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8867 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   8871 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8875 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8879 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8884 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8886 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8886 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8889 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8893 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8898 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8904 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8909 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8919 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   8926 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8928 */     GIR_RootConstrainSelectedInstOperands,
     /*   8929 */     // GIR_Coverage, 14108,
     /*   8929 */     GIR_EraseRootFromParent_Done,
     /*   8930 */   // Label 226: @8930
     /*   8930 */   GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(9027), // Rule ID 14109 //
     /*   8935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8939 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8959 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8963 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8967 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8971 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8976 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8981 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8983 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8983 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8986 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8990 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8995 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   9001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   9006 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   9014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   9016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   9019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9023 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   9025 */     GIR_RootConstrainSelectedInstOperands,
     /*   9026 */     // GIR_Coverage, 14109,
     /*   9026 */     GIR_EraseRootFromParent_Done,
     /*   9027 */   // Label 227: @9027
     /*   9027 */   GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(9190), // Rule ID 14217 //
     /*   9032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9048 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9052 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*   9056 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9060 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   9064 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9069 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9074 */     // MIs[1] Operand 2
     /*   9074 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9085 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9089 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9091 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9091 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9094 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9098 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9103 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9105 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9108 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9112 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9117 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9120 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*   9124 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9127 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9132 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9137 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9142 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9145 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*   9149 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9154 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9157 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   9161 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*   9165 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9172 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9179 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9184 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9189 */     // GIR_Coverage, 14217,
     /*   9189 */     GIR_EraseRootFromParent_Done,
     /*   9190 */   // Label 228: @9190
     /*   9190 */   GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(9353), // Rule ID 14214 //
     /*   9195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9211 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9215 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*   9219 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9223 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   9227 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9232 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9237 */     // MIs[1] Operand 2
     /*   9237 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9248 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9252 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9254 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9254 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9257 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9261 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9266 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9268 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9271 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9275 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9280 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9283 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*   9287 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9290 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9295 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9300 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9305 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9308 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*   9312 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9317 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9320 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   9324 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*   9328 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9335 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9342 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9347 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9352 */     // GIR_Coverage, 14214,
     /*   9352 */     GIR_EraseRootFromParent_Done,
     /*   9353 */   // Label 229: @9353
     /*   9353 */   GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(9503), // Rule ID 14223 //
     /*   9358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9374 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9378 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   9382 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9386 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9391 */     // MIs[1] Operand 2
     /*   9391 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9402 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9406 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9408 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9408 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9411 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9415 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9420 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9422 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9425 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9429 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9434 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9437 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   9441 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9444 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9449 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9454 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9459 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9462 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*   9466 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9471 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9474 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9478 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9485 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9492 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9497 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9502 */     // GIR_Coverage, 14223,
     /*   9502 */     GIR_EraseRootFromParent_Done,
     /*   9503 */   // Label 230: @9503
     /*   9503 */   GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9653), // Rule ID 14226 //
     /*   9508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9512 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9516 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9520 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9524 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9528 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   9532 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9536 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9541 */     // MIs[1] Operand 2
     /*   9541 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9552 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9556 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9558 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9558 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9561 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9565 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9570 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9572 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9575 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9579 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9584 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9587 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   9591 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9594 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9599 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9604 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9609 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9612 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*   9616 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9621 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9624 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9628 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9635 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9642 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9647 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9652 */     // GIR_Coverage, 14226,
     /*   9652 */     GIR_EraseRootFromParent_Done,
     /*   9653 */   // Label 231: @9653
     /*   9653 */   GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(9803), // Rule ID 14222 //
     /*   9658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9674 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9678 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   9682 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9691 */     // MIs[1] Operand 2
     /*   9691 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9706 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9708 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9708 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9711 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9715 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9720 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9722 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9725 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9729 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9734 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9737 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   9741 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9744 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9749 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9754 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9759 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9762 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*   9766 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9771 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9774 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9778 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9785 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9792 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9797 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9802 */     // GIR_Coverage, 14222,
     /*   9802 */     GIR_EraseRootFromParent_Done,
     /*   9803 */   // Label 232: @9803
     /*   9803 */   GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(9966), // Rule ID 5407 //
     /*   9808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9812 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9824 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9828 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9832 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*   9836 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9840 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   9844 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9849 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9854 */     // MIs[1] Operand 2
     /*   9854 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9865 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9867 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9867 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9870 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9874 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9879 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9881 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9884 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9888 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9893 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9896 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*   9900 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9903 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9908 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9913 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9918 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9921 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*   9925 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9930 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9933 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   9937 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*   9941 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9948 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9955 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9960 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9965 */     // GIR_Coverage, 5407,
     /*   9965 */     GIR_EraseRootFromParent_Done,
     /*   9966 */   // Label 233: @9966
     /*   9966 */   GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(10129), // Rule ID 5404 //
     /*   9971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9975 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9979 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9983 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9987 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9991 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9995 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*   9999 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10003 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  10007 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10012 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10017 */     // MIs[1] Operand 2
     /*  10017 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10028 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10030 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10030 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10033 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10037 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10042 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10044 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10047 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10051 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10056 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10059 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  10063 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10066 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10071 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10076 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10081 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10084 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  10088 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10093 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10096 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  10100 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  10104 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10111 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10118 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10123 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10128 */     // GIR_Coverage, 5404,
     /*  10128 */     GIR_EraseRootFromParent_Done,
     /*  10129 */   // Label 234: @10129
     /*  10129 */   GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(10279), // Rule ID 5431 //
     /*  10134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10138 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10142 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10146 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10150 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  10162 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10166 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10171 */     // MIs[1] Operand 2
     /*  10171 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10182 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10184 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10184 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10187 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10191 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10196 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10198 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10201 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10205 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10210 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10213 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10217 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10220 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10225 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10230 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10235 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10238 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  10242 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10247 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10250 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10254 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10261 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10268 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10273 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10278 */     // GIR_Coverage, 5431,
     /*  10278 */     GIR_EraseRootFromParent_Done,
     /*  10279 */   // Label 235: @10279
     /*  10279 */   GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(10429), // Rule ID 5437 //
     /*  10284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10288 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10300 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10304 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10308 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  10312 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10316 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10321 */     // MIs[1] Operand 2
     /*  10321 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10334 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10334 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10337 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10341 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10346 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10348 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10351 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10355 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10360 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10363 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10367 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10370 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10375 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10380 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  10392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10397 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10400 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10404 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10411 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10418 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10423 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10428 */     // GIR_Coverage, 5437,
     /*  10428 */     GIR_EraseRootFromParent_Done,
     /*  10429 */   // Label 236: @10429
     /*  10429 */   GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(10579), // Rule ID 5430 //
     /*  10434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10438 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10442 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10446 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10450 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10454 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10458 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  10462 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10466 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10471 */     // MIs[1] Operand 2
     /*  10471 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10482 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10484 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10484 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10487 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10491 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10496 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10498 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10501 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10505 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10510 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10513 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10517 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10520 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10525 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10530 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10535 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10538 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  10542 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10547 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10550 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10554 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10561 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10568 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10573 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10578 */     // GIR_Coverage, 5430,
     /*  10578 */     GIR_EraseRootFromParent_Done,
     /*  10579 */   // Label 237: @10579
     /*  10579 */   GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(10612), // Rule ID 13508 //
     /*  10584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  10599 */     // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
     /*  10599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
     /*  10602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  10606 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*  10610 */     GIR_RootConstrainSelectedInstOperands,
     /*  10611 */     // GIR_Coverage, 13508,
     /*  10611 */     GIR_EraseRootFromParent_Done,
     /*  10612 */   // Label 238: @10612
     /*  10612 */   GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(10648), // Rule ID 14088 //
     /*  10617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  10632 */     // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  10632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  10635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  10639 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  10643 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  10646 */     GIR_RootConstrainSelectedInstOperands,
     /*  10647 */     // GIR_Coverage, 14088,
     /*  10647 */     GIR_EraseRootFromParent_Done,
     /*  10648 */   // Label 239: @10648
     /*  10648 */   GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(10760), // Rule ID 4020 //
     /*  10653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  10661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  10665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  10669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  10673 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  10678 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  10683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10687 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  10689 */     // (add:{ *:[i64] } (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  10689 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  10692 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10696 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10701 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  10707 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  10712 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10717 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  10720 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10724 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10729 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  10735 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  10740 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  10748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10750 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  10753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  10756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*  10758 */     GIR_RootConstrainSelectedInstOperands,
     /*  10759 */     // GIR_Coverage, 4020,
     /*  10759 */     GIR_EraseRootFromParent_Done,
     /*  10760 */   // Label 240: @10760
     /*  10760 */   GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(10793), // Rule ID 98 //
     /*  10765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  10780 */     // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)  =>  (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
     /*  10780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
     /*  10783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10785 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  10787 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*  10791 */     GIR_RootConstrainSelectedInstOperands,
     /*  10792 */     // GIR_Coverage, 98,
     /*  10792 */     GIR_EraseRootFromParent_Done,
     /*  10793 */   // Label 241: @10793
     /*  10793 */   GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(10829), // Rule ID 3955 //
     /*  10798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10802 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  10813 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  10813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  10816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10818 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  10820 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  10824 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  10827 */     GIR_RootConstrainSelectedInstOperands,
     /*  10828 */     // GIR_Coverage, 3955,
     /*  10828 */     GIR_EraseRootFromParent_Done,
     /*  10829 */   // Label 242: @10829
     /*  10829 */   GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(10941), // Rule ID 14106 //
     /*  10834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  10850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  10854 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  10858 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  10863 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  10868 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  10870 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  10870 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  10873 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10877 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10882 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  10888 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  10893 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10898 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  10901 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10905 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10910 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  10916 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  10921 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  10929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10931 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  10934 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  10937 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  10939 */     GIR_RootConstrainSelectedInstOperands,
     /*  10940 */     // GIR_Coverage, 14106,
     /*  10940 */     GIR_EraseRootFromParent_Done,
     /*  10941 */   // Label 243: @10941
     /*  10941 */   GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(10974), // Rule ID 13506 //
     /*  10946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10950 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  10961 */     // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  10961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*  10964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10966 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  10968 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  10972 */     GIR_RootConstrainSelectedInstOperands,
     /*  10973 */     // GIR_Coverage, 13506,
     /*  10973 */     GIR_EraseRootFromParent_Done,
     /*  10974 */   // Label 244: @10974
     /*  10974 */   GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(11037), // Rule ID 15839 //
     /*  10979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  10982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10986 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  10990 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  10994 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  10997 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11002 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  11006 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11008 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11013 */     // MIs[1] pred
     /*  11013 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11018 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11022 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11024 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*  11027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11035 */     GIR_RootConstrainSelectedInstOperands,
     /*  11036 */     // GIR_Coverage, 15839,
     /*  11036 */     GIR_EraseRootFromParent_Done,
     /*  11037 */   // Label 245: @11037
     /*  11037 */   GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(11100), // Rule ID 15840 //
     /*  11042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11049 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11053 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11057 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11060 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  11069 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11071 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11076 */     // MIs[1] pred
     /*  11076 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11081 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11087 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*  11090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11092 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11098 */     GIR_RootConstrainSelectedInstOperands,
     /*  11099 */     // GIR_Coverage, 15840,
     /*  11099 */     GIR_EraseRootFromParent_Done,
     /*  11100 */   // Label 246: @11100
     /*  11100 */   GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(11163), // Rule ID 15841 //
     /*  11105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11112 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11116 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11120 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11123 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11128 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  11132 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11134 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11139 */     // MIs[1] pred
     /*  11139 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11148 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11150 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*  11153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11159 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11161 */     GIR_RootConstrainSelectedInstOperands,
     /*  11162 */     // GIR_Coverage, 15841,
     /*  11162 */     GIR_EraseRootFromParent_Done,
     /*  11163 */   // Label 247: @11163
     /*  11163 */   GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(11226), // Rule ID 15842 //
     /*  11168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11175 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11179 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11183 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11186 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11191 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  11195 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11197 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11202 */     // MIs[1] pred
     /*  11202 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11207 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11211 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11213 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*  11216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11218 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11224 */     GIR_RootConstrainSelectedInstOperands,
     /*  11225 */     // GIR_Coverage, 15842,
     /*  11225 */     GIR_EraseRootFromParent_Done,
     /*  11226 */   // Label 248: @11226
     /*  11226 */   GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(11259), // Rule ID 96 //
     /*  11231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11235 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  11246 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  11246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*  11249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11251 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11253 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  11257 */     GIR_RootConstrainSelectedInstOperands,
     /*  11258 */     // GIR_Coverage, 96,
     /*  11258 */     GIR_EraseRootFromParent_Done,
     /*  11259 */   // Label 249: @11259
     /*  11259 */   GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(11322), // Rule ID 10176 //
     /*  11264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11271 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11275 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11279 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11283 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11286 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  11295 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11297 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11302 */     // MIs[1] pred
     /*  11302 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11307 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11309 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*  11312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11318 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11320 */     GIR_RootConstrainSelectedInstOperands,
     /*  11321 */     // GIR_Coverage, 10176,
     /*  11321 */     GIR_EraseRootFromParent_Done,
     /*  11322 */   // Label 250: @11322
     /*  11322 */   GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(11385), // Rule ID 10177 //
     /*  11327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11334 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11346 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11349 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11354 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  11358 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11360 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11365 */     // MIs[1] pred
     /*  11365 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11370 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11372 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*  11375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11381 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11383 */     GIR_RootConstrainSelectedInstOperands,
     /*  11384 */     // GIR_Coverage, 10177,
     /*  11384 */     GIR_EraseRootFromParent_Done,
     /*  11385 */   // Label 251: @11385
     /*  11385 */   GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(11448), // Rule ID 10178 //
     /*  11390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11397 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11409 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11412 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  11421 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11423 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11428 */     // MIs[1] pred
     /*  11428 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11433 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11435 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*  11438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11440 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11444 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11446 */     GIR_RootConstrainSelectedInstOperands,
     /*  11447 */     // GIR_Coverage, 10178,
     /*  11447 */     GIR_EraseRootFromParent_Done,
     /*  11448 */   // Label 252: @11448
     /*  11448 */   GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(11511), // Rule ID 10179 //
     /*  11453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11460 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11472 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11475 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11480 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  11484 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11486 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11491 */     // MIs[1] pred
     /*  11491 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11496 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11498 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*  11501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11503 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11507 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11509 */     GIR_RootConstrainSelectedInstOperands,
     /*  11510 */     // GIR_Coverage, 10179,
     /*  11510 */     GIR_EraseRootFromParent_Done,
     /*  11511 */   // Label 253: @11511
     /*  11511 */   GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(11567), // Rule ID 13616 //
     /*  11516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11531 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11534 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  11539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11543 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11554 */     // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 670:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  11557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11561 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11565 */     GIR_RootConstrainSelectedInstOperands,
     /*  11566 */     // GIR_Coverage, 13616,
     /*  11566 */     GIR_EraseRootFromParent_Done,
     /*  11567 */   // Label 254: @11567
     /*  11567 */   GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(11623), // Rule ID 13628 //
     /*  11572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11579 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11583 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11587 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11590 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  11595 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11599 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11608 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11610 */     // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 735:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  11613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11615 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11621 */     GIR_RootConstrainSelectedInstOperands,
     /*  11622 */     // GIR_Coverage, 13628,
     /*  11622 */     GIR_EraseRootFromParent_Done,
     /*  11623 */   // Label 255: @11623
     /*  11623 */   GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(11690), // Rule ID 13844 //
     /*  11628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  11643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11647 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11652 */     // MIs[1] imm
     /*  11652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  11656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  11660 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  11664 */     // MIs[2] Operand 1
     /*  11664 */     // No operand predicates
     /*  11664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11668 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  11672 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  11674 */     // (add:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  11674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  11677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  11685 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  11688 */     GIR_RootConstrainSelectedInstOperands,
     /*  11689 */     // GIR_Coverage, 13844,
     /*  11689 */     GIR_EraseRootFromParent_Done,
     /*  11690 */   // Label 256: @11690
     /*  11690 */   GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(11757), // Rule ID 13847 //
     /*  11695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11702 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11706 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  11710 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11714 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11719 */     // MIs[1] imm
     /*  11719 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  11723 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  11727 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  11731 */     // MIs[2] Operand 1
     /*  11731 */     // No operand predicates
     /*  11731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11735 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  11739 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  11741 */     // (add:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  11741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  11744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  11752 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  11755 */     GIR_RootConstrainSelectedInstOperands,
     /*  11756 */     // GIR_Coverage, 13847,
     /*  11756 */     GIR_EraseRootFromParent_Done,
     /*  11757 */   // Label 257: @11757
     /*  11757 */   GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(11813), // Rule ID 1001 //
     /*  11762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11781 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11784 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  11789 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11793 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11798 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11800 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 670:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  11803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11805 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  11807 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11811 */     GIR_RootConstrainSelectedInstOperands,
     /*  11812 */     // GIR_Coverage, 1001,
     /*  11812 */     GIR_EraseRootFromParent_Done,
     /*  11813 */   // Label 258: @11813
     /*  11813 */   GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(11869), // Rule ID 1062 //
     /*  11818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11825 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11837 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11840 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  11845 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11849 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11854 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11856 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 735:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  11859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11861 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  11863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11867 */     GIR_RootConstrainSelectedInstOperands,
     /*  11868 */     // GIR_Coverage, 1062,
     /*  11868 */     GIR_EraseRootFromParent_Done,
     /*  11869 */   // Label 259: @11869
     /*  11869 */   GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(11936), // Rule ID 2125 //
     /*  11874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11881 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11885 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11889 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  11893 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11897 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11902 */     // MIs[1] imm
     /*  11902 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  11906 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  11910 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  11914 */     // MIs[2] Operand 1
     /*  11914 */     // No operand predicates
     /*  11914 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  11918 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  11920 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  11920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  11923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11925 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  11927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  11931 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  11934 */     GIR_RootConstrainSelectedInstOperands,
     /*  11935 */     // GIR_Coverage, 2125,
     /*  11935 */     GIR_EraseRootFromParent_Done,
     /*  11936 */   // Label 260: @11936
     /*  11936 */   GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(12003), // Rule ID 2134 //
     /*  11941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11948 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  11960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11964 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11969 */     // MIs[1] imm
     /*  11969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  11973 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  11977 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  11981 */     // MIs[2] Operand 1
     /*  11981 */     // No operand predicates
     /*  11981 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  11985 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  11987 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  11987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  11990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11992 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  11994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  11998 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  12001 */     GIR_RootConstrainSelectedInstOperands,
     /*  12002 */     // GIR_Coverage, 2134,
     /*  12002 */     GIR_EraseRootFromParent_Done,
     /*  12003 */   // Label 261: @12003
     /*  12003 */   GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(12051), // Rule ID 13615 //
     /*  12008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12015 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12019 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  12023 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12036 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12038 */     // (add:{ *:[v1i64] } (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  12041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12045 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12049 */     GIR_RootConstrainSelectedInstOperands,
     /*  12050 */     // GIR_Coverage, 13615,
     /*  12050 */     GIR_EraseRootFromParent_Done,
     /*  12051 */   // Label 262: @12051
     /*  12051 */   GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(12099), // Rule ID 13627 //
     /*  12056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12067 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  12071 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12084 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12086 */     // (add:{ *:[v1i64] } (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  12089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12091 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12093 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12097 */     GIR_RootConstrainSelectedInstOperands,
     /*  12098 */     // GIR_Coverage, 13627,
     /*  12098 */     GIR_EraseRootFromParent_Done,
     /*  12099 */   // Label 263: @12099
     /*  12099 */   GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(12147), // Rule ID 1000 //
     /*  12104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12115 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12119 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  12123 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12132 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12134 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  12137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12139 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12145 */     GIR_RootConstrainSelectedInstOperands,
     /*  12146 */     // GIR_Coverage, 1000,
     /*  12146 */     GIR_EraseRootFromParent_Done,
     /*  12147 */   // Label 264: @12147
     /*  12147 */   GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(12195), // Rule ID 1061 //
     /*  12152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  12171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12175 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12180 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12182 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  12185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12187 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12193 */     GIR_RootConstrainSelectedInstOperands,
     /*  12194 */     // GIR_Coverage, 1061,
     /*  12194 */     GIR_EraseRootFromParent_Done,
     /*  12195 */   // Label 265: @12195
     /*  12195 */   GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(12219), // Rule ID 94 //
     /*  12200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12204 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12212 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  12212 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDXrr),
     /*  12217 */     GIR_RootConstrainSelectedInstOperands,
     /*  12218 */     // GIR_Coverage, 94,
     /*  12218 */     GIR_Done,
     /*  12219 */   // Label 266: @12219
     /*  12219 */   GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(12246), // Rule ID 1611 //
     /*  12224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12231 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12239 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  12239 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv1i64),
     /*  12244 */     GIR_RootConstrainSelectedInstOperands,
     /*  12245 */     // GIR_Coverage, 1611,
     /*  12245 */     GIR_Done,
     /*  12246 */   // Label 267: @12246
     /*  12246 */   GIM_Reject,
     /*  12247 */ // Label 196: @12247
     /*  12247 */ GIM_Reject,
     /*  12248 */ // Label 158: @12248
     /*  12248 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(15855),
     /*  12253 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12256 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12259 */   GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(12447), // Rule ID 7010 //
     /*  12264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /*  12276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12292 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12296 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12301 */     // MIs[2] Operand 2
     /*  12301 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  12312 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  12316 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12320 */     // MIs[3] Rn
     /*  12320 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12325 */     // MIs[3] Operand 2
     /*  12325 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(2),
     /*  12336 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  12340 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_ZIP2),
     /*  12344 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12348 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12352 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  12356 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12360 */     // MIs[5] Rn
     /*  12360 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12365 */     // MIs[5] Operand 2
     /*  12365 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(0),
     /*  12376 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6]
     /*  12380 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12384 */     // MIs[6] Rn
     /*  12384 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12389 */     // MIs[6] Operand 2
     /*  12389 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(2),
     /*  12400 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  12402 */     // (add:{ *:[v2i32] } (AArch64zip1:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })), (AArch64zip2:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /*  12402 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  12405 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  12409 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  12414 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12418 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12422 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  12424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  12427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12429 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  12436 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12441 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12446 */     // GIR_Coverage, 7010,
     /*  12446 */     GIR_EraseRootFromParent_Done,
     /*  12447 */   // Label 269: @12447
     /*  12447 */   GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(12635), // Rule ID 14256 //
     /*  12452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12460 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /*  12464 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12468 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12472 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12476 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12480 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12484 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12489 */     // MIs[2] Operand 2
     /*  12489 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  12500 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  12504 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12508 */     // MIs[3] Rn
     /*  12508 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12513 */     // MIs[3] Operand 2
     /*  12513 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(2),
     /*  12524 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  12528 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_ZIP1),
     /*  12532 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12536 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12540 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  12544 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12548 */     // MIs[5] Rn
     /*  12548 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12553 */     // MIs[5] Operand 2
     /*  12553 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(0),
     /*  12564 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6]
     /*  12568 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12572 */     // MIs[6] Rn
     /*  12572 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12577 */     // MIs[6] Operand 2
     /*  12577 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(2),
     /*  12588 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  12590 */     // (add:{ *:[v2i32] } (AArch64zip2:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })), (AArch64zip1:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /*  12590 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  12593 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  12597 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  12602 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12606 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12610 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  12612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  12615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12617 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  12624 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12629 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12634 */     // GIR_Coverage, 14256,
     /*  12634 */     GIR_EraseRootFromParent_Done,
     /*  12635 */   // Label 270: @12635
     /*  12635 */   GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(12771), // Rule ID 5421 //
     /*  12640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12644 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12648 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12652 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12656 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12660 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  12664 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12668 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12673 */     // MIs[1] Operand 2
     /*  12673 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  12684 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  12688 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12692 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12696 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  12700 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  12704 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12708 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12713 */     // MIs[3] Operand 2
     /*  12713 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  12724 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  12726 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  12726 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  12729 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  12733 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  12738 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12742 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  12746 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  12748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  12751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12753 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  12760 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12765 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12770 */     // GIR_Coverage, 5421,
     /*  12770 */     GIR_EraseRootFromParent_Done,
     /*  12771 */   // Label 271: @12771
     /*  12771 */   GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(12907), // Rule ID 5420 //
     /*  12776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  12800 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12804 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12809 */     // MIs[1] Operand 2
     /*  12809 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  12820 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  12824 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12828 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12832 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  12836 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  12840 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12844 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12849 */     // MIs[3] Operand 2
     /*  12849 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  12860 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  12862 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  12862 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  12865 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  12869 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  12874 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  12878 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  12882 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  12884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  12887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12889 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  12896 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12901 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12906 */     // GIR_Coverage, 5420,
     /*  12906 */     GIR_EraseRootFromParent_Done,
     /*  12907 */   // Label 272: @12907
     /*  12907 */   GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(13043), // Rule ID 5433 //
     /*  12912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12928 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12932 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  12936 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12940 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12945 */     // MIs[1] Operand 2
     /*  12945 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  12956 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  12960 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12964 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12968 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  12972 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  12976 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  12980 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12985 */     // MIs[3] Operand 2
     /*  12985 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  12996 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  12998 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  12998 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13001 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i16_v4i32),
     /*  13005 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13010 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13014 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13018 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13025 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13032 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13037 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13042 */     // GIR_Coverage, 5433,
     /*  13042 */     GIR_EraseRootFromParent_Done,
     /*  13043 */   // Label 273: @13043
     /*  13043 */   GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(13179), // Rule ID 5419 //
     /*  13048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13064 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13068 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13072 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13076 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13081 */     // MIs[1] Operand 2
     /*  13081 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13092 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13096 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13100 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13104 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13108 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13112 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13116 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13121 */     // MIs[3] Operand 2
     /*  13121 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13132 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13134 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13134 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13137 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13141 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13146 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13150 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13154 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13161 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13168 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13173 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13178 */     // GIR_Coverage, 5419,
     /*  13178 */     GIR_EraseRootFromParent_Done,
     /*  13179 */   // Label 274: @13179
     /*  13179 */   GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(13315), // Rule ID 5418 //
     /*  13184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13196 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13200 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13204 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13208 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13212 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13217 */     // MIs[1] Operand 2
     /*  13217 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13228 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13232 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13236 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13240 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13244 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13248 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13252 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13257 */     // MIs[3] Operand 2
     /*  13257 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13268 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13270 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13270 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13273 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13277 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13282 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13286 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13290 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13297 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13309 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13314 */     // GIR_Coverage, 5418,
     /*  13314 */     GIR_EraseRootFromParent_Done,
     /*  13315 */   // Label 275: @13315
     /*  13315 */   GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(13478), // Rule ID 14216 //
     /*  13320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13328 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13332 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13336 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13340 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  13344 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13348 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  13352 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13357 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13362 */     // MIs[1] Operand 2
     /*  13362 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13377 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13379 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13379 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13382 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  13386 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13391 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  13393 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  13396 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  13400 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13405 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  13408 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  13412 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  13415 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13420 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13425 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13430 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13433 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  13437 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13442 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  13445 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13449 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  13453 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13460 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13467 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13472 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13477 */     // GIR_Coverage, 14216,
     /*  13477 */     GIR_EraseRootFromParent_Done,
     /*  13478 */   // Label 276: @13478
     /*  13478 */   GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(13641), // Rule ID 14213 //
     /*  13483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13499 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13503 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  13507 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13511 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  13515 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13520 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13525 */     // MIs[1] Operand 2
     /*  13525 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13540 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13542 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13542 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13545 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  13549 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13554 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  13556 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  13559 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  13563 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13568 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  13571 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  13575 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  13578 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13583 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13588 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13593 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13596 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  13600 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13605 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  13608 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13612 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  13616 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13623 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13630 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13635 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13640 */     // GIR_Coverage, 14213,
     /*  13640 */     GIR_EraseRootFromParent_Done,
     /*  13641 */   // Label 277: @13641
     /*  13641 */   GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(13791), // Rule ID 14221 //
     /*  13646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13658 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13662 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13666 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13670 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13674 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13679 */     // MIs[1] Operand 2
     /*  13679 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13694 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13696 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13696 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13699 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  13703 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13708 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  13710 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  13713 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  13717 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13722 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  13725 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  13729 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  13732 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13737 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13742 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13747 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13750 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  13754 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13759 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  13762 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  13766 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13773 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13780 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13785 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13790 */     // GIR_Coverage, 14221,
     /*  13790 */     GIR_EraseRootFromParent_Done,
     /*  13791 */   // Label 278: @13791
     /*  13791 */   GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(13941), // Rule ID 14225 //
     /*  13796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13812 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13816 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  13820 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13824 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13829 */     // MIs[1] Operand 2
     /*  13829 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13844 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13846 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13846 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13849 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  13853 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13858 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  13860 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  13863 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  13867 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13872 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  13875 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  13879 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  13882 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13887 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13892 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13897 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13900 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  13904 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13909 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  13912 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  13916 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13923 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13930 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13935 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13940 */     // GIR_Coverage, 14225,
     /*  13940 */     GIR_EraseRootFromParent_Done,
     /*  13941 */   // Label 279: @13941
     /*  13941 */   GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(14091), // Rule ID 14220 //
     /*  13946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13962 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13966 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13970 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13974 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13979 */     // MIs[1] Operand 2
     /*  13979 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13994 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13996 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13996 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13999 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14003 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14008 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14010 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14013 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14017 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14022 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14025 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  14029 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14032 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14037 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14042 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  14054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14059 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14062 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14066 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14073 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14080 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14085 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14090 */     // GIR_Coverage, 14220,
     /*  14090 */     GIR_EraseRootFromParent_Done,
     /*  14091 */   // Label 280: @14091
     /*  14091 */   GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(14254), // Rule ID 5406 //
     /*  14096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14100 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14104 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14108 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14112 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14116 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14120 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  14124 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14128 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  14132 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14137 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14142 */     // MIs[1] Operand 2
     /*  14142 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14153 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14155 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14155 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14158 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14162 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14167 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14169 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14172 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14176 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14181 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14184 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  14188 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14191 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14196 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14201 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14206 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14209 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  14213 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14218 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14221 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14225 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14229 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14236 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14243 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14248 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14253 */     // GIR_Coverage, 5406,
     /*  14253 */     GIR_EraseRootFromParent_Done,
     /*  14254 */   // Label 281: @14254
     /*  14254 */   GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(14417), // Rule ID 5403 //
     /*  14259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14263 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14279 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14283 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  14287 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14291 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  14295 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14300 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14305 */     // MIs[1] Operand 2
     /*  14305 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14316 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14318 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14318 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14321 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14325 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14330 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14332 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14335 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14339 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14344 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14347 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  14351 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14354 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14359 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14364 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14369 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14372 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  14376 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14381 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14384 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14388 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14392 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14399 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14406 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14411 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14416 */     // GIR_Coverage, 5403,
     /*  14416 */     GIR_EraseRootFromParent_Done,
     /*  14417 */   // Label 282: @14417
     /*  14417 */   GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(14567), // Rule ID 5429 //
     /*  14422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14430 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14434 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14438 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14442 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14446 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  14450 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14454 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14459 */     // MIs[1] Operand 2
     /*  14459 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14470 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14472 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14472 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14475 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14479 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14486 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14489 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14493 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14498 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14501 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  14505 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14508 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14513 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14518 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14523 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14526 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  14530 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14535 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14538 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14542 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14549 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14561 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14566 */     // GIR_Coverage, 5429,
     /*  14566 */     GIR_EraseRootFromParent_Done,
     /*  14567 */   // Label 283: @14567
     /*  14567 */   GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(14717), // Rule ID 5436 //
     /*  14572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14576 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14580 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14584 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14588 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14592 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14596 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  14600 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14604 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14609 */     // MIs[1] Operand 2
     /*  14609 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14620 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14622 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14622 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14625 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14629 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14634 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14636 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14639 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14643 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14648 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14651 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  14655 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14658 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14663 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14668 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14673 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14676 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  14680 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14685 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14688 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14692 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14699 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14706 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14711 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14716 */     // GIR_Coverage, 5436,
     /*  14716 */     GIR_EraseRootFromParent_Done,
     /*  14717 */   // Label 284: @14717
     /*  14717 */   GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(14867), // Rule ID 5428 //
     /*  14722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14726 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14742 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14746 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  14750 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14754 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14759 */     // MIs[1] Operand 2
     /*  14759 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14770 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14772 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14772 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14775 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14779 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14784 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14786 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14789 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14793 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14798 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14801 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  14805 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14808 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14813 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14818 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14823 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14826 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  14830 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14835 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14838 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14842 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14849 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14856 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14861 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14866 */     // GIR_Coverage, 5428,
     /*  14866 */     GIR_EraseRootFromParent_Done,
     /*  14867 */   // Label 285: @14867
     /*  14867 */   GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(14936), // Rule ID 13650 //
     /*  14872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  14875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  14887 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  14890 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  14895 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  14899 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  14903 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14908 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14917 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  14919 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  14919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  14922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14924 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  14926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  14930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  14934 */     GIR_RootConstrainSelectedInstOperands,
     /*  14935 */     // GIR_Coverage, 13650,
     /*  14935 */     GIR_EraseRootFromParent_Done,
     /*  14936 */   // Label 286: @14936
     /*  14936 */   GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(15005), // Rule ID 13662 //
     /*  14941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  14944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  14956 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  14959 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  14964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  14968 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  14972 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14977 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14986 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  14988 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  14988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
     /*  14991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  14995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  14999 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  15003 */     GIR_RootConstrainSelectedInstOperands,
     /*  15004 */     // GIR_Coverage, 13662,
     /*  15004 */     GIR_EraseRootFromParent_Done,
     /*  15005 */   // Label 287: @15005
     /*  15005 */   GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(15061), // Rule ID 13612 //
     /*  15010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15025 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15028 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  15033 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15037 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15046 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15048 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 670:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15059 */     GIR_RootConstrainSelectedInstOperands,
     /*  15060 */     // GIR_Coverage, 13612,
     /*  15060 */     GIR_EraseRootFromParent_Done,
     /*  15061 */   // Label 288: @15061
     /*  15061 */   GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(15117), // Rule ID 13624 //
     /*  15066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15077 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15081 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15084 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  15089 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15093 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15102 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15104 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 735:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15115 */     GIR_RootConstrainSelectedInstOperands,
     /*  15116 */     // GIR_Coverage, 13624,
     /*  15116 */     GIR_EraseRootFromParent_Done,
     /*  15117 */   // Label 289: @15117
     /*  15117 */   GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(15184), // Rule ID 13864 //
     /*  15122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  15137 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15141 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15146 */     // MIs[1] imm
     /*  15146 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  15150 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  15154 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15158 */     // MIs[2] Operand 1
     /*  15158 */     // No operand predicates
     /*  15158 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15162 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15166 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15168 */     // (add:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  15168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  15171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  15182 */     GIR_RootConstrainSelectedInstOperands,
     /*  15183 */     // GIR_Coverage, 13864,
     /*  15183 */     GIR_EraseRootFromParent_Done,
     /*  15184 */   // Label 290: @15184
     /*  15184 */   GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(15251), // Rule ID 13885 //
     /*  15189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15196 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15200 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  15204 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15208 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15213 */     // MIs[1] imm
     /*  15213 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  15217 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  15221 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15225 */     // MIs[2] Operand 1
     /*  15225 */     // No operand predicates
     /*  15225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15229 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15233 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15235 */     // (add:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  15235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  15238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15246 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  15249 */     GIR_RootConstrainSelectedInstOperands,
     /*  15250 */     // GIR_Coverage, 13885,
     /*  15250 */     GIR_EraseRootFromParent_Done,
     /*  15251 */   // Label 291: @15251
     /*  15251 */   GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(15320), // Rule ID 1369 //
     /*  15256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15263 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15275 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  15278 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  15283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  15287 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  15291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15301 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15303 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  15303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  15306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15308 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15310 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  15318 */     GIR_RootConstrainSelectedInstOperands,
     /*  15319 */     // GIR_Coverage, 1369,
     /*  15319 */     GIR_EraseRootFromParent_Done,
     /*  15320 */   // Label 292: @15320
     /*  15320 */   GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(15389), // Rule ID 1492 //
     /*  15325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15332 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15336 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15340 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15344 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  15347 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  15352 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  15356 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  15360 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15365 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15370 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15372 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  15372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
     /*  15375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15377 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  15387 */     GIR_RootConstrainSelectedInstOperands,
     /*  15388 */     // GIR_Coverage, 1492,
     /*  15388 */     GIR_EraseRootFromParent_Done,
     /*  15389 */   // Label 293: @15389
     /*  15389 */   GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(15445), // Rule ID 997 //
     /*  15394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15413 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15416 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  15421 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15425 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15430 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15432 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 670:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15437 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15443 */     GIR_RootConstrainSelectedInstOperands,
     /*  15444 */     // GIR_Coverage, 997,
     /*  15444 */     GIR_EraseRootFromParent_Done,
     /*  15445 */   // Label 294: @15445
     /*  15445 */   GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(15501), // Rule ID 1058 //
     /*  15450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15457 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15469 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15472 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  15477 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15481 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15486 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15488 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 735:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15499 */     GIR_RootConstrainSelectedInstOperands,
     /*  15500 */     // GIR_Coverage, 1058,
     /*  15500 */     GIR_EraseRootFromParent_Done,
     /*  15501 */   // Label 295: @15501
     /*  15501 */   GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(15568), // Rule ID 2242 //
     /*  15506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  15525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15529 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15534 */     // MIs[1] imm
     /*  15534 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  15538 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  15542 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15546 */     // MIs[2] Operand 1
     /*  15546 */     // No operand predicates
     /*  15546 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15550 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15552 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  15552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  15555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15563 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  15566 */     GIR_RootConstrainSelectedInstOperands,
     /*  15567 */     // GIR_Coverage, 2242,
     /*  15567 */     GIR_EraseRootFromParent_Done,
     /*  15568 */   // Label 296: @15568
     /*  15568 */   GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(15635), // Rule ID 2301 //
     /*  15573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15580 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15584 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15588 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  15592 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15596 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15601 */     // MIs[1] imm
     /*  15601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  15605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  15609 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15613 */     // MIs[2] Operand 1
     /*  15613 */     // No operand predicates
     /*  15613 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15617 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15619 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  15619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  15622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15624 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15626 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15630 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  15633 */     GIR_RootConstrainSelectedInstOperands,
     /*  15634 */     // GIR_Coverage, 2301,
     /*  15634 */     GIR_EraseRootFromParent_Done,
     /*  15635 */   // Label 297: @15635
     /*  15635 */   GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(15683), // Rule ID 13611 //
     /*  15640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15647 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15651 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  15655 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15659 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15668 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15670 */     // (add:{ *:[v2i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15675 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15681 */     GIR_RootConstrainSelectedInstOperands,
     /*  15682 */     // GIR_Coverage, 13611,
     /*  15682 */     GIR_EraseRootFromParent_Done,
     /*  15683 */   // Label 298: @15683
     /*  15683 */   GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(15731), // Rule ID 13623 //
     /*  15688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  15703 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15707 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15712 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15716 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15718 */     // (add:{ *:[v2i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15729 */     GIR_RootConstrainSelectedInstOperands,
     /*  15730 */     // GIR_Coverage, 13623,
     /*  15730 */     GIR_EraseRootFromParent_Done,
     /*  15731 */   // Label 299: @15731
     /*  15731 */   GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(15779), // Rule ID 996 //
     /*  15736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15743 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15751 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  15755 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15759 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15764 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15766 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15771 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15773 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15777 */     GIR_RootConstrainSelectedInstOperands,
     /*  15778 */     // GIR_Coverage, 996,
     /*  15778 */     GIR_EraseRootFromParent_Done,
     /*  15779 */   // Label 300: @15779
     /*  15779 */   GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(15827), // Rule ID 1057 //
     /*  15784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15791 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  15803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15807 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15812 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15814 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15819 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15825 */     GIR_RootConstrainSelectedInstOperands,
     /*  15826 */     // GIR_Coverage, 1057,
     /*  15826 */     GIR_EraseRootFromParent_Done,
     /*  15827 */   // Label 301: @15827
     /*  15827 */   GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(15854), // Rule ID 1108 //
     /*  15832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15839 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15847 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  15847 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i32),
     /*  15852 */     GIR_RootConstrainSelectedInstOperands,
     /*  15853 */     // GIR_Coverage, 1108,
     /*  15853 */     GIR_Done,
     /*  15854 */   // Label 302: @15854
     /*  15854 */   GIM_Reject,
     /*  15855 */ // Label 268: @15855
     /*  15855 */ GIM_Reject,
     /*  15856 */ // Label 159: @15856
     /*  15856 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(21757),
     /*  15861 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  15864 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  15867 */   GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(15985), // Rule ID 13793 //
     /*  15872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  15887 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15891 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  15895 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  15899 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  15903 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  15907 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  15911 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  15915 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  15919 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  15923 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15928 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  15932 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  15936 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  15940 */     // MIs[4] Operand 1
     /*  15940 */     // No operand predicates
     /*  15940 */     // MIs[2] Operand 2
     /*  15940 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  15951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15955 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  15957 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  15964 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  15964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  15967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15969 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  15976 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  15980 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  15983 */     GIR_RootConstrainSelectedInstOperands,
     /*  15984 */     // GIR_Coverage, 13793,
     /*  15984 */     GIR_EraseRootFromParent_Done,
     /*  15985 */   // Label 304: @15985
     /*  15985 */   GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(16103), // Rule ID 13794 //
     /*  15990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  16005 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16009 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16021 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16025 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16029 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16033 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16037 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16041 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16046 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16050 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16054 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16058 */     // MIs[4] Operand 1
     /*  16058 */     // No operand predicates
     /*  16058 */     // MIs[2] Operand 2
     /*  16058 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16069 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16073 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16075 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16082 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  16085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16098 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16101 */     GIR_RootConstrainSelectedInstOperands,
     /*  16102 */     // GIR_Coverage, 13794,
     /*  16102 */     GIR_EraseRootFromParent_Done,
     /*  16103 */   // Label 305: @16103
     /*  16103 */   GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(16221), // Rule ID 13829 //
     /*  16108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16115 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16119 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  16123 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16127 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16131 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  16135 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16139 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16143 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16147 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16151 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16155 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16159 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16164 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16168 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16172 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16176 */     // MIs[4] Operand 1
     /*  16176 */     // No operand predicates
     /*  16176 */     // MIs[2] Operand 2
     /*  16176 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16187 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16191 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16193 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16200 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  16203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16212 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16216 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16219 */     GIR_RootConstrainSelectedInstOperands,
     /*  16220 */     // GIR_Coverage, 13829,
     /*  16220 */     GIR_EraseRootFromParent_Done,
     /*  16221 */   // Label 306: @16221
     /*  16221 */   GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(16339), // Rule ID 13830 //
     /*  16226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  16241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16245 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16249 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16253 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16257 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16261 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16265 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16269 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16273 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16277 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16282 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16286 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16290 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16294 */     // MIs[4] Operand 1
     /*  16294 */     // No operand predicates
     /*  16294 */     // MIs[2] Operand 2
     /*  16294 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16305 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16309 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16311 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16318 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  16321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16330 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16334 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16337 */     GIR_RootConstrainSelectedInstOperands,
     /*  16338 */     // GIR_Coverage, 13830,
     /*  16338 */     GIR_EraseRootFromParent_Done,
     /*  16339 */   // Label 307: @16339
     /*  16339 */   GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(16457), // Rule ID 2046 //
     /*  16344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16351 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  16363 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16367 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16371 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  16375 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16379 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16383 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16387 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16391 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16395 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16399 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16404 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16408 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16412 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16416 */     // MIs[4] Operand 1
     /*  16416 */     // No operand predicates
     /*  16416 */     // MIs[2] Operand 2
     /*  16416 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16427 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16429 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16436 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  16439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16441 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16448 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16452 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16455 */     GIR_RootConstrainSelectedInstOperands,
     /*  16456 */     // GIR_Coverage, 2046,
     /*  16456 */     GIR_EraseRootFromParent_Done,
     /*  16457 */   // Label 308: @16457
     /*  16457 */   GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(16575), // Rule ID 13792 //
     /*  16462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16469 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16477 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  16481 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16485 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16489 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16493 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16497 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16501 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16505 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16509 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16513 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16517 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16522 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16526 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16530 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16534 */     // MIs[4] Operand 1
     /*  16534 */     // No operand predicates
     /*  16534 */     // MIs[2] Operand 2
     /*  16534 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16545 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16547 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16554 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  16557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16559 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16570 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16573 */     GIR_RootConstrainSelectedInstOperands,
     /*  16574 */     // GIR_Coverage, 13792,
     /*  16574 */     GIR_EraseRootFromParent_Done,
     /*  16575 */   // Label 309: @16575
     /*  16575 */   GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(16693), // Rule ID 2098 //
     /*  16580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16587 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16595 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  16599 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16603 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  16611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16615 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16619 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16623 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16627 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16631 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16635 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16640 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16644 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16648 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16652 */     // MIs[4] Operand 1
     /*  16652 */     // No operand predicates
     /*  16652 */     // MIs[2] Operand 2
     /*  16652 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16663 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16665 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16672 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  16675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16677 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16688 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16691 */     GIR_RootConstrainSelectedInstOperands,
     /*  16692 */     // GIR_Coverage, 2098,
     /*  16692 */     GIR_EraseRootFromParent_Done,
     /*  16693 */   // Label 310: @16693
     /*  16693 */   GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(16811), // Rule ID 13828 //
     /*  16698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16705 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  16717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16721 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16725 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16729 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16733 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16737 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16741 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16745 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16749 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16753 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16758 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16762 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16766 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16770 */     // MIs[4] Operand 1
     /*  16770 */     // No operand predicates
     /*  16770 */     // MIs[2] Operand 2
     /*  16770 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16781 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16783 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16790 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  16793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16795 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16806 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16809 */     GIR_RootConstrainSelectedInstOperands,
     /*  16810 */     // GIR_Coverage, 13828,
     /*  16810 */     GIR_EraseRootFromParent_Done,
     /*  16811 */   // Label 311: @16811
     /*  16811 */   GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(16898), // Rule ID 13694 //
     /*  16816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  16831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16835 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16839 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  16843 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  16846 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  16851 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16855 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  16859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16863 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  16865 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16872 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16879 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  16879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
     /*  16882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  16896 */     GIR_RootConstrainSelectedInstOperands,
     /*  16897 */     // GIR_Coverage, 13694,
     /*  16897 */     GIR_EraseRootFromParent_Done,
     /*  16898 */   // Label 312: @16898
     /*  16898 */   GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(16985), // Rule ID 13722 //
     /*  16903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  16918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16922 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  16926 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  16930 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  16933 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  16938 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16942 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  16946 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16950 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  16952 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16959 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16966 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  16966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
     /*  16969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16971 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  16983 */     GIR_RootConstrainSelectedInstOperands,
     /*  16984 */     // GIR_Coverage, 13722,
     /*  16984 */     GIR_EraseRootFromParent_Done,
     /*  16985 */   // Label 313: @16985
     /*  16985 */   GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(17072), // Rule ID 1703 //
     /*  16990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  17021 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  17024 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  17029 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17033 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  17037 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17039 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17046 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17053 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))))  =>  (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
     /*  17056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17058 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17070 */     GIR_RootConstrainSelectedInstOperands,
     /*  17071 */     // GIR_Coverage, 1703,
     /*  17071 */     GIR_EraseRootFromParent_Done,
     /*  17072 */   // Label 314: @17072
     /*  17072 */   GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(17159), // Rule ID 1781 //
     /*  17077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17084 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17100 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17104 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  17108 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  17111 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  17116 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17120 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  17124 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17126 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17133 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17140 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))))  =>  (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
     /*  17143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17145 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17157 */     GIR_RootConstrainSelectedInstOperands,
     /*  17158 */     // GIR_Coverage, 1781,
     /*  17158 */     GIR_EraseRootFromParent_Done,
     /*  17159 */   // Label 315: @17159
     /*  17159 */   GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(17274), // Rule ID 13788 //
     /*  17164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17171 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17175 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17179 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17183 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17187 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17191 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17195 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17199 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17203 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17207 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17211 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17215 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17220 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17224 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17228 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17232 */     // MIs[4] Operand 1
     /*  17232 */     // No operand predicates
     /*  17232 */     // MIs[2] Operand 2
     /*  17232 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  17243 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17248 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17252 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17254 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  17257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  17265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17269 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17272 */     GIR_RootConstrainSelectedInstOperands,
     /*  17273 */     // GIR_Coverage, 13788,
     /*  17273 */     GIR_EraseRootFromParent_Done,
     /*  17274 */   // Label 316: @17274
     /*  17274 */   GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(17389), // Rule ID 13787 //
     /*  17279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17294 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17298 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17315 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17319 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17323 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17327 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17331 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17335 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17340 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17344 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17348 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17352 */     // MIs[4] Operand 1
     /*  17352 */     // No operand predicates
     /*  17352 */     // MIs[2] Operand 2
     /*  17352 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  17363 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17367 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17369 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  17372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  17380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17384 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17387 */     GIR_RootConstrainSelectedInstOperands,
     /*  17388 */     // GIR_Coverage, 13787,
     /*  17388 */     GIR_EraseRootFromParent_Done,
     /*  17389 */   // Label 317: @17389
     /*  17389 */   GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(17504), // Rule ID 13824 //
     /*  17394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17409 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17413 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17417 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17421 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17425 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17429 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17433 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17437 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17441 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17445 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17450 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17454 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17458 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17462 */     // MIs[4] Operand 1
     /*  17462 */     // No operand predicates
     /*  17462 */     // MIs[2] Operand 2
     /*  17462 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  17473 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17478 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17482 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17484 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  17487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  17495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17499 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17502 */     GIR_RootConstrainSelectedInstOperands,
     /*  17503 */     // GIR_Coverage, 13824,
     /*  17503 */     GIR_EraseRootFromParent_Done,
     /*  17504 */   // Label 318: @17504
     /*  17504 */   GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(17619), // Rule ID 13823 //
     /*  17509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17524 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17528 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17532 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17545 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17549 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17553 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17557 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17561 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17565 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17570 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17574 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17578 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17582 */     // MIs[4] Operand 1
     /*  17582 */     // No operand predicates
     /*  17582 */     // MIs[2] Operand 2
     /*  17582 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  17593 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17597 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17599 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  17602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  17610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17614 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17617 */     GIR_RootConstrainSelectedInstOperands,
     /*  17618 */     // GIR_Coverage, 13823,
     /*  17618 */     GIR_EraseRootFromParent_Done,
     /*  17619 */   // Label 319: @17619
     /*  17619 */   GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(17688), // Rule ID 1805 //
     /*  17624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  17639 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17643 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  17647 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  17651 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17655 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17657 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17664 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17671 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  17674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  17676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17686 */     GIR_RootConstrainSelectedInstOperands,
     /*  17687 */     // GIR_Coverage, 1805,
     /*  17687 */     GIR_EraseRootFromParent_Done,
     /*  17688 */   // Label 320: @17688
     /*  17688 */   GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(17757), // Rule ID 1804 //
     /*  17693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  17708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17712 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  17716 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17720 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17724 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17726 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17733 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17740 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  17743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  17745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17755 */     GIR_RootConstrainSelectedInstOperands,
     /*  17756 */     // GIR_Coverage, 1804,
     /*  17756 */     GIR_EraseRootFromParent_Done,
     /*  17757 */   // Label 321: @17757
     /*  17757 */   GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(17826), // Rule ID 1721 //
     /*  17762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  17777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  17785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  17789 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17793 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17795 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17802 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17809 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i32_v2i64),
     /*  17812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  17814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17824 */     GIR_RootConstrainSelectedInstOperands,
     /*  17825 */     // GIR_Coverage, 1721,
     /*  17825 */     GIR_EraseRootFromParent_Done,
     /*  17826 */   // Label 322: @17826
     /*  17826 */   GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(17895), // Rule ID 1803 //
     /*  17831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17846 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17850 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  17854 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  17858 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17862 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17864 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17871 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17878 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  17881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  17883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17893 */     GIR_RootConstrainSelectedInstOperands,
     /*  17894 */     // GIR_Coverage, 1803,
     /*  17894 */     GIR_EraseRootFromParent_Done,
     /*  17895 */   // Label 323: @17895
     /*  17895 */   GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(17964), // Rule ID 1802 //
     /*  17900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17911 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17915 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17919 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  17923 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  17927 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17931 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  17933 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17940 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17947 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  17947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  17950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  17952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  17962 */     GIR_RootConstrainSelectedInstOperands,
     /*  17963 */     // GIR_Coverage, 1802,
     /*  17963 */     GIR_EraseRootFromParent_Done,
     /*  17964 */   // Label 324: @17964
     /*  17964 */   GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(18079), // Rule ID 13786 //
     /*  17969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17980 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17984 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17988 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17992 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18004 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18008 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18012 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18016 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18020 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18024 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18029 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18033 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18037 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18041 */     // MIs[4] Operand 1
     /*  18041 */     // No operand predicates
     /*  18041 */     // MIs[2] Operand 2
     /*  18041 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18052 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18057 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18059 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  18062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18064 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18066 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  18070 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18077 */     GIR_RootConstrainSelectedInstOperands,
     /*  18078 */     // GIR_Coverage, 13786,
     /*  18078 */     GIR_EraseRootFromParent_Done,
     /*  18079 */   // Label 325: @18079
     /*  18079 */   GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(18194), // Rule ID 2044 //
     /*  18084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18091 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18095 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18099 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  18103 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18107 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18111 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18116 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  18120 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18124 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18128 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18132 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18136 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18140 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18144 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18149 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18153 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18157 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18161 */     // MIs[4] Operand 1
     /*  18161 */     // No operand predicates
     /*  18161 */     // MIs[2] Operand 2
     /*  18161 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18172 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18174 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  18177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18179 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18181 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  18185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18189 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18192 */     GIR_RootConstrainSelectedInstOperands,
     /*  18193 */     // GIR_Coverage, 2044,
     /*  18193 */     GIR_EraseRootFromParent_Done,
     /*  18194 */   // Label 326: @18194
     /*  18194 */   GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(18309), // Rule ID 13822 //
     /*  18199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18206 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18210 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18214 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18218 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18222 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18226 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18230 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18234 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18238 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18242 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18246 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18250 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18254 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18259 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18263 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18267 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18271 */     // MIs[4] Operand 1
     /*  18271 */     // No operand predicates
     /*  18271 */     // MIs[2] Operand 2
     /*  18271 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18282 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18287 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18289 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  18292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18294 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  18300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18304 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18307 */     GIR_RootConstrainSelectedInstOperands,
     /*  18308 */     // GIR_Coverage, 13822,
     /*  18308 */     GIR_EraseRootFromParent_Done,
     /*  18309 */   // Label 327: @18309
     /*  18309 */   GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(18424), // Rule ID 2096 //
     /*  18314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18337 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18346 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  18350 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18354 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18358 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18362 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18366 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18370 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18374 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18379 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18383 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18387 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18391 */     // MIs[4] Operand 1
     /*  18391 */     // No operand predicates
     /*  18391 */     // MIs[2] Operand 2
     /*  18391 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18402 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18404 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  18407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18409 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18411 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  18415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18419 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18422 */     GIR_RootConstrainSelectedInstOperands,
     /*  18423 */     // GIR_Coverage, 2096,
     /*  18423 */     GIR_EraseRootFromParent_Done,
     /*  18424 */   // Label 328: @18424
     /*  18424 */   GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(18491), // Rule ID 13706 //
     /*  18429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  18444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18448 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18456 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  18458 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18465 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18472 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
     /*  18475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18489 */     GIR_RootConstrainSelectedInstOperands,
     /*  18490 */     // GIR_Coverage, 13706,
     /*  18490 */     GIR_EraseRootFromParent_Done,
     /*  18491 */   // Label 329: @18491
     /*  18491 */   GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(18558), // Rule ID 13740 //
     /*  18496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18507 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18511 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18515 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18519 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18523 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  18525 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18532 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18539 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
     /*  18542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18556 */     GIR_RootConstrainSelectedInstOperands,
     /*  18557 */     // GIR_Coverage, 13740,
     /*  18557 */     GIR_EraseRootFromParent_Done,
     /*  18558 */   // Label 330: @18558
     /*  18558 */   GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(18625), // Rule ID 1733 //
     /*  18563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18570 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18574 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18578 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  18582 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18586 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18590 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  18592 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18599 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18606 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
     /*  18609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18611 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18623 */     GIR_RootConstrainSelectedInstOperands,
     /*  18624 */     // GIR_Coverage, 1733,
     /*  18624 */     GIR_EraseRootFromParent_Done,
     /*  18625 */   // Label 331: @18625
     /*  18625 */   GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(18692), // Rule ID 1823 //
     /*  18630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18637 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18653 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18657 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  18659 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18666 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18673 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
     /*  18676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18678 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18690 */     GIR_RootConstrainSelectedInstOperands,
     /*  18691 */     // GIR_Coverage, 1823,
     /*  18691 */     GIR_EraseRootFromParent_Done,
     /*  18692 */   // Label 332: @18692
     /*  18692 */   GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(18773), // Rule ID 13692 //
     /*  18697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18716 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18720 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  18724 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  18727 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  18732 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18736 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  18740 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18745 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18754 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18756 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  18756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  18759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18761 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  18767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  18771 */     GIR_RootConstrainSelectedInstOperands,
     /*  18772 */     // GIR_Coverage, 13692,
     /*  18772 */     GIR_EraseRootFromParent_Done,
     /*  18773 */   // Label 333: @18773
     /*  18773 */   GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(18854), // Rule ID 13720 //
     /*  18778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18797 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18801 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  18805 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  18808 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  18813 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18817 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  18821 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18826 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18831 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18835 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18837 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  18837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
     /*  18840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  18848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  18852 */     GIR_RootConstrainSelectedInstOperands,
     /*  18853 */     // GIR_Coverage, 13720,
     /*  18853 */     GIR_EraseRootFromParent_Done,
     /*  18854 */   // Label 334: @18854
     /*  18854 */   GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(18935), // Rule ID 1701 //
     /*  18859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18866 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18882 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18886 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  18890 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  18893 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  18898 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18902 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  18906 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18911 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18916 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18918 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  18918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  18921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18923 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18925 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  18929 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  18933 */     GIR_RootConstrainSelectedInstOperands,
     /*  18934 */     // GIR_Coverage, 1701,
     /*  18934 */     GIR_EraseRootFromParent_Done,
     /*  18935 */   // Label 335: @18935
     /*  18935 */   GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(19016), // Rule ID 1779 //
     /*  18940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18947 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  18971 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  18974 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  18979 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18983 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  18987 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18992 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18997 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18999 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  18999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
     /*  19002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19004 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  19010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  19014 */     GIR_RootConstrainSelectedInstOperands,
     /*  19015 */     // GIR_Coverage, 1779,
     /*  19015 */     GIR_EraseRootFromParent_Done,
     /*  19016 */   // Label 336: @19016
     /*  19016 */   GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(19108), // Rule ID 13791 //
     /*  19021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19040 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19044 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19048 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19052 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19056 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19060 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19065 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19069 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19073 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19077 */     // MIs[3] Operand 1
     /*  19077 */     // No operand predicates
     /*  19077 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19082 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19086 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19088 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19095 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19099 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19103 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19106 */     GIR_RootConstrainSelectedInstOperands,
     /*  19107 */     // GIR_Coverage, 13791,
     /*  19107 */     GIR_EraseRootFromParent_Done,
     /*  19108 */   // Label 337: @19108
     /*  19108 */   GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(19200), // Rule ID 13790 //
     /*  19113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19120 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19124 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19128 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19132 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19136 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19141 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19145 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19149 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19153 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19157 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19162 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19166 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19170 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19174 */     // MIs[3] Operand 1
     /*  19174 */     // No operand predicates
     /*  19174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19178 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19180 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19185 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19187 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19191 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19195 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19198 */     GIR_RootConstrainSelectedInstOperands,
     /*  19199 */     // GIR_Coverage, 13790,
     /*  19199 */     GIR_EraseRootFromParent_Done,
     /*  19200 */   // Label 338: @19200
     /*  19200 */   GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(19292), // Rule ID 13827 //
     /*  19205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19212 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19220 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19224 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19228 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19232 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19236 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19240 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19244 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19249 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19253 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19257 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19261 */     // MIs[3] Operand 1
     /*  19261 */     // No operand predicates
     /*  19261 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19266 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19270 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19272 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19283 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19287 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19290 */     GIR_RootConstrainSelectedInstOperands,
     /*  19291 */     // GIR_Coverage, 13827,
     /*  19291 */     GIR_EraseRootFromParent_Done,
     /*  19292 */   // Label 339: @19292
     /*  19292 */   GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(19384), // Rule ID 13826 //
     /*  19297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19316 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19320 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19325 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19329 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19333 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19337 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19341 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19346 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19350 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19354 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19358 */     // MIs[3] Operand 1
     /*  19358 */     // No operand predicates
     /*  19358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19362 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19364 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19371 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19375 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19379 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19382 */     GIR_RootConstrainSelectedInstOperands,
     /*  19383 */     // GIR_Coverage, 13826,
     /*  19383 */     GIR_EraseRootFromParent_Done,
     /*  19384 */   // Label 340: @19384
     /*  19384 */   GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(19476), // Rule ID 13789 //
     /*  19389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19396 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19412 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19424 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19428 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19432 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19437 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19441 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19445 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19449 */     // MIs[3] Operand 1
     /*  19449 */     // No operand predicates
     /*  19449 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19454 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19456 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19461 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19471 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19474 */     GIR_RootConstrainSelectedInstOperands,
     /*  19475 */     // GIR_Coverage, 13789,
     /*  19475 */     GIR_EraseRootFromParent_Done,
     /*  19476 */   // Label 341: @19476
     /*  19476 */   GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(19568), // Rule ID 2045 //
     /*  19481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19488 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19492 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19496 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19500 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19504 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19508 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19513 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19517 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19521 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19525 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19529 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19534 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19538 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19542 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19546 */     // MIs[3] Operand 1
     /*  19546 */     // No operand predicates
     /*  19546 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19548 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19553 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19555 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19563 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19566 */     GIR_RootConstrainSelectedInstOperands,
     /*  19567 */     // GIR_Coverage, 2045,
     /*  19567 */     GIR_EraseRootFromParent_Done,
     /*  19568 */   // Label 342: @19568
     /*  19568 */   GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(19660), // Rule ID 13825 //
     /*  19573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19580 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19584 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19588 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19592 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19596 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19600 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19604 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19608 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19612 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19616 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19621 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19625 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19629 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19633 */     // MIs[3] Operand 1
     /*  19633 */     // No operand predicates
     /*  19633 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19638 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19640 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19645 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19651 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19655 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19658 */     GIR_RootConstrainSelectedInstOperands,
     /*  19659 */     // GIR_Coverage, 13825,
     /*  19659 */     GIR_EraseRootFromParent_Done,
     /*  19660 */   // Label 343: @19660
     /*  19660 */   GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(19752), // Rule ID 2097 //
     /*  19665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19672 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19680 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19684 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19688 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19692 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19697 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19701 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19705 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19709 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19713 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19718 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19722 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19726 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19730 */     // MIs[3] Operand 1
     /*  19730 */     // No operand predicates
     /*  19730 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19732 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19737 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19743 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19747 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19750 */     GIR_RootConstrainSelectedInstOperands,
     /*  19751 */     // GIR_Coverage, 2097,
     /*  19751 */     GIR_EraseRootFromParent_Done,
     /*  19752 */   // Label 344: @19752
     /*  19752 */   GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(19803), // Rule ID 13734 //
     /*  19757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19764 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19768 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  19772 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19780 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19782 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19789 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  19792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  19794 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  19796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  19801 */     GIR_RootConstrainSelectedInstOperands,
     /*  19802 */     // GIR_Coverage, 13734,
     /*  19802 */     GIR_EraseRootFromParent_Done,
     /*  19803 */   // Label 345: @19803
     /*  19803 */   GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(19854), // Rule ID 13700 //
     /*  19808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  19823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19827 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19831 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19833 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19840 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
     /*  19843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  19845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  19847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  19852 */     GIR_RootConstrainSelectedInstOperands,
     /*  19853 */     // GIR_Coverage, 13700,
     /*  19853 */     GIR_EraseRootFromParent_Done,
     /*  19854 */   // Label 346: @19854
     /*  19854 */   GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(19905), // Rule ID 13733 //
     /*  19859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  19874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19882 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19884 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19891 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  19894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  19896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  19898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  19903 */     GIR_RootConstrainSelectedInstOperands,
     /*  19904 */     // GIR_Coverage, 13733,
     /*  19904 */     GIR_EraseRootFromParent_Done,
     /*  19905 */   // Label 347: @19905
     /*  19905 */   GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(19956), // Rule ID 1817 //
     /*  19910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  19929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19933 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19935 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19942 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  19945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  19947 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  19949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  19954 */     GIR_RootConstrainSelectedInstOperands,
     /*  19955 */     // GIR_Coverage, 1817,
     /*  19955 */     GIR_EraseRootFromParent_Done,
     /*  19956 */   // Label 348: @19956
     /*  19956 */   GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(20007), // Rule ID 1727 //
     /*  19961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19968 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19972 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19976 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  19980 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19984 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19986 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19993 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
     /*  19996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  19998 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  20000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20005 */     GIR_RootConstrainSelectedInstOperands,
     /*  20006 */     // GIR_Coverage, 1727,
     /*  20006 */     GIR_EraseRootFromParent_Done,
     /*  20007 */   // Label 349: @20007
     /*  20007 */   GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(20058), // Rule ID 1816 //
     /*  20012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20019 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20031 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20035 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20037 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20044 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  20047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20049 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  20051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20056 */     GIR_RootConstrainSelectedInstOperands,
     /*  20057 */     // GIR_Coverage, 1816,
     /*  20057 */     GIR_EraseRootFromParent_Done,
     /*  20058 */   // Label 350: @20058
     /*  20058 */   GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(20114), // Rule ID 13618 //
     /*  20063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20070 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20074 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20078 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20081 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  20086 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20090 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20099 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20101 */     // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 670:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  20104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20108 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20112 */     GIR_RootConstrainSelectedInstOperands,
     /*  20113 */     // GIR_Coverage, 13618,
     /*  20113 */     GIR_EraseRootFromParent_Done,
     /*  20114 */   // Label 351: @20114
     /*  20114 */   GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(20170), // Rule ID 13630 //
     /*  20119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20126 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20130 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20134 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20137 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  20142 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20146 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20151 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20155 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20157 */     // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 735:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  20160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20168 */     GIR_RootConstrainSelectedInstOperands,
     /*  20169 */     // GIR_Coverage, 13630,
     /*  20169 */     GIR_EraseRootFromParent_Done,
     /*  20170 */   // Label 352: @20170
     /*  20170 */   GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(20237), // Rule ID 13868 //
     /*  20175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  20190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20194 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20199 */     // MIs[1] imm
     /*  20199 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20203 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20207 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20211 */     // MIs[2] Operand 1
     /*  20211 */     // No operand predicates
     /*  20211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20215 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20219 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20221 */     // (add:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  20221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  20224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20232 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  20235 */     GIR_RootConstrainSelectedInstOperands,
     /*  20236 */     // GIR_Coverage, 13868,
     /*  20236 */     GIR_EraseRootFromParent_Done,
     /*  20237 */   // Label 353: @20237
     /*  20237 */   GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(20304), // Rule ID 13889 //
     /*  20242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  20257 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20261 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20266 */     // MIs[1] imm
     /*  20266 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20270 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20274 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20278 */     // MIs[2] Operand 1
     /*  20278 */     // No operand predicates
     /*  20278 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20282 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20286 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20288 */     // (add:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  20288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  20291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20299 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  20302 */     GIR_RootConstrainSelectedInstOperands,
     /*  20303 */     // GIR_Coverage, 13889,
     /*  20303 */     GIR_EraseRootFromParent_Done,
     /*  20304 */   // Label 354: @20304
     /*  20304 */   GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(20360), // Rule ID 1003 //
     /*  20309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20316 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20328 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20331 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  20336 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20340 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20345 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20347 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 670:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  20350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20352 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20358 */     GIR_RootConstrainSelectedInstOperands,
     /*  20359 */     // GIR_Coverage, 1003,
     /*  20359 */     GIR_EraseRootFromParent_Done,
     /*  20360 */   // Label 355: @20360
     /*  20360 */   GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(20416), // Rule ID 1064 //
     /*  20365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20372 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20380 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20384 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20387 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  20392 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20396 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20401 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20403 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 735:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  20406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20408 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20414 */     GIR_RootConstrainSelectedInstOperands,
     /*  20415 */     // GIR_Coverage, 1064,
     /*  20415 */     GIR_EraseRootFromParent_Done,
     /*  20416 */   // Label 356: @20416
     /*  20416 */   GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(20483), // Rule ID 2246 //
     /*  20421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20428 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  20440 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20444 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20449 */     // MIs[1] imm
     /*  20449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20457 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20461 */     // MIs[2] Operand 1
     /*  20461 */     // No operand predicates
     /*  20461 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20465 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20467 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  20467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  20470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20472 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20474 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20478 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  20481 */     GIR_RootConstrainSelectedInstOperands,
     /*  20482 */     // GIR_Coverage, 2246,
     /*  20482 */     GIR_EraseRootFromParent_Done,
     /*  20483 */   // Label 357: @20483
     /*  20483 */   GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(20550), // Rule ID 2305 //
     /*  20488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20495 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  20507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20516 */     // MIs[1] imm
     /*  20516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20524 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20528 */     // MIs[2] Operand 1
     /*  20528 */     // No operand predicates
     /*  20528 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20532 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20534 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  20534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  20537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20539 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20541 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20545 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  20548 */     GIR_RootConstrainSelectedInstOperands,
     /*  20549 */     // GIR_Coverage, 2305,
     /*  20549 */     GIR_EraseRootFromParent_Done,
     /*  20550 */   // Label 358: @20550
     /*  20550 */   GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(20620), // Rule ID 7006 //
     /*  20555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20559 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20563 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /*  20567 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20571 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  20575 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20580 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20585 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20589 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP2),
     /*  20593 */     // MIs[2] Rn
     /*  20593 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  20598 */     // MIs[2] Rm
     /*  20598 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  20603 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20605 */     // (add:{ *:[v2i64] } (AArch64zip1:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm), (AArch64zip2:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm))  =>  (ADDPv2i64:{ *:[v2i64] } ?:{ *:[v2i64] }:$Rn, ?:{ *:[v2i64] }:$Rm)
     /*  20605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /*  20608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  20618 */     GIR_RootConstrainSelectedInstOperands,
     /*  20619 */     // GIR_Coverage, 7006,
     /*  20619 */     GIR_EraseRootFromParent_Done,
     /*  20620 */   // Label 359: @20620
     /*  20620 */   GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(20690), // Rule ID 14252 //
     /*  20625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20633 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /*  20637 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20641 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  20645 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20650 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20655 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20659 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP1),
     /*  20663 */     // MIs[2] Rn
     /*  20663 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  20668 */     // MIs[2] Rm
     /*  20668 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  20673 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20675 */     // (add:{ *:[v2i64] } (AArch64zip2:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm), (AArch64zip1:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm))  =>  (ADDPv2i64:{ *:[v2i64] } ?:{ *:[v2i64] }:$Rn, ?:{ *:[v2i64] }:$Rm)
     /*  20675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /*  20678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  20688 */     GIR_RootConstrainSelectedInstOperands,
     /*  20689 */     // GIR_Coverage, 14252,
     /*  20689 */     GIR_EraseRootFromParent_Done,
     /*  20690 */   // Label 360: @20690
     /*  20690 */   GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(20753), // Rule ID 1801 //
     /*  20695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20702 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20706 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20710 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20714 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20719 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20723 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20727 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20731 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20736 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20738 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  20738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  20741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20743 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20751 */     GIR_RootConstrainSelectedInstOperands,
     /*  20752 */     // GIR_Coverage, 1801,
     /*  20752 */     GIR_EraseRootFromParent_Done,
     /*  20753 */   // Label 361: @20753
     /*  20753 */   GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(20816), // Rule ID 1800 //
     /*  20758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20765 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20777 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20782 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20786 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20790 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20794 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20799 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20801 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  20801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  20804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20810 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20814 */     GIR_RootConstrainSelectedInstOperands,
     /*  20815 */     // GIR_Coverage, 1800,
     /*  20815 */     GIR_EraseRootFromParent_Done,
     /*  20816 */   // Label 362: @20816
     /*  20816 */   GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(20879), // Rule ID 1720 //
     /*  20821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20832 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  20836 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20840 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20845 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20849 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  20853 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20857 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20862 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20864 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  20864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv2i32_v2i64),
     /*  20867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20869 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20873 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20877 */     GIR_RootConstrainSelectedInstOperands,
     /*  20878 */     // GIR_Coverage, 1720,
     /*  20878 */     GIR_EraseRootFromParent_Done,
     /*  20879 */   // Label 363: @20879
     /*  20879 */   GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(20942), // Rule ID 1799 //
     /*  20884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20891 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20895 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20899 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20903 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20908 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20912 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20916 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20920 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20925 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20927 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  20927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  20930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20940 */     GIR_RootConstrainSelectedInstOperands,
     /*  20941 */     // GIR_Coverage, 1799,
     /*  20941 */     GIR_EraseRootFromParent_Done,
     /*  20942 */   // Label 364: @20942
     /*  20942 */   GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(21005), // Rule ID 1798 //
     /*  20947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20954 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20958 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20962 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20966 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20971 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  20975 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20979 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20983 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20988 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  20990 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  20990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  20993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20999 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  21003 */     GIR_RootConstrainSelectedInstOperands,
     /*  21004 */     // GIR_Coverage, 1798,
     /*  21004 */     GIR_EraseRootFromParent_Done,
     /*  21005 */   // Label 365: @21005
     /*  21005 */   GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(21066), // Rule ID 13705 //
     /*  21010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  21025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21038 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21047 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21049 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*  21052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21056 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21060 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21064 */     GIR_RootConstrainSelectedInstOperands,
     /*  21065 */     // GIR_Coverage, 13705,
     /*  21065 */     GIR_EraseRootFromParent_Done,
     /*  21066 */   // Label 366: @21066
     /*  21066 */   GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(21127), // Rule ID 13739 //
     /*  21071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  21086 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21090 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21094 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21099 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21108 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21110 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  21113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21125 */     GIR_RootConstrainSelectedInstOperands,
     /*  21126 */     // GIR_Coverage, 13739,
     /*  21126 */     GIR_EraseRootFromParent_Done,
     /*  21127 */   // Label 367: @21127
     /*  21127 */   GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(21175), // Rule ID 13732 //
     /*  21132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21151 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21160 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21162 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  21165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21167 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  21169 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21173 */     GIR_RootConstrainSelectedInstOperands,
     /*  21174 */     // GIR_Coverage, 13732,
     /*  21174 */     GIR_EraseRootFromParent_Done,
     /*  21175 */   // Label 368: @21175
     /*  21175 */   GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(21223), // Rule ID 13617 //
     /*  21180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21187 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21191 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  21195 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  21199 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21208 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21210 */     // (add:{ *:[v2i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  21210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  21213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21217 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21221 */     GIR_RootConstrainSelectedInstOperands,
     /*  21222 */     // GIR_Coverage, 13617,
     /*  21222 */     GIR_EraseRootFromParent_Done,
     /*  21223 */   // Label 369: @21223
     /*  21223 */   GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(21271), // Rule ID 13699 //
     /*  21228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  21243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21247 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21252 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21256 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21258 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  21261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  21265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21269 */     GIR_RootConstrainSelectedInstOperands,
     /*  21270 */     // GIR_Coverage, 13699,
     /*  21270 */     GIR_EraseRootFromParent_Done,
     /*  21271 */   // Label 370: @21271
     /*  21271 */   GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(21319), // Rule ID 13629 //
     /*  21276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  21291 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  21295 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21304 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21306 */     // (add:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  21306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  21309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21313 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21317 */     GIR_RootConstrainSelectedInstOperands,
     /*  21318 */     // GIR_Coverage, 13629,
     /*  21318 */     GIR_EraseRootFromParent_Done,
     /*  21319 */   // Label 371: @21319
     /*  21319 */   GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(21367), // Rule ID 13731 //
     /*  21324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21343 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21352 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21354 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  21357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  21361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21365 */     GIR_RootConstrainSelectedInstOperands,
     /*  21366 */     // GIR_Coverage, 13731,
     /*  21366 */     GIR_EraseRootFromParent_Done,
     /*  21367 */   // Label 372: @21367
     /*  21367 */   GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(21428), // Rule ID 1732 //
     /*  21372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21379 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  21391 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21395 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21399 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21404 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21409 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21411 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*  21414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21416 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21418 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21426 */     GIR_RootConstrainSelectedInstOperands,
     /*  21427 */     // GIR_Coverage, 1732,
     /*  21427 */     GIR_EraseRootFromParent_Done,
     /*  21428 */   // Label 373: @21428
     /*  21428 */   GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(21489), // Rule ID 1822 //
     /*  21433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21440 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  21452 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21456 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21465 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21472 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  21475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21477 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21479 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21487 */     GIR_RootConstrainSelectedInstOperands,
     /*  21488 */     // GIR_Coverage, 1822,
     /*  21488 */     GIR_EraseRootFromParent_Done,
     /*  21489 */   // Label 374: @21489
     /*  21489 */   GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(21537), // Rule ID 1815 //
     /*  21494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21522 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21524 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  21527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21529 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  21531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21535 */     GIR_RootConstrainSelectedInstOperands,
     /*  21536 */     // GIR_Coverage, 1815,
     /*  21536 */     GIR_EraseRootFromParent_Done,
     /*  21537 */   // Label 375: @21537
     /*  21537 */   GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(21585), // Rule ID 1002 //
     /*  21542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21549 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21553 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21557 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  21561 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  21565 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21570 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21572 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  21572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  21575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21577 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21583 */     GIR_RootConstrainSelectedInstOperands,
     /*  21584 */     // GIR_Coverage, 1002,
     /*  21584 */     GIR_EraseRootFromParent_Done,
     /*  21585 */   // Label 376: @21585
     /*  21585 */   GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(21633), // Rule ID 1726 //
     /*  21590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21597 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21601 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  21609 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21613 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21618 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21620 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  21623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21625 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  21627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21631 */     GIR_RootConstrainSelectedInstOperands,
     /*  21632 */     // GIR_Coverage, 1726,
     /*  21632 */     GIR_EraseRootFromParent_Done,
     /*  21633 */   // Label 377: @21633
     /*  21633 */   GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(21681), // Rule ID 1063 //
     /*  21638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21645 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21649 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21653 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  21657 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  21661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21666 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21668 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  21668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  21671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21673 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21679 */     GIR_RootConstrainSelectedInstOperands,
     /*  21680 */     // GIR_Coverage, 1063,
     /*  21680 */     GIR_EraseRootFromParent_Done,
     /*  21681 */   // Label 378: @21681
     /*  21681 */   GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(21729), // Rule ID 1814 //
     /*  21686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21714 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21716 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  21719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21721 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  21723 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  21727 */     GIR_RootConstrainSelectedInstOperands,
     /*  21728 */     // GIR_Coverage, 1814,
     /*  21728 */     GIR_EraseRootFromParent_Done,
     /*  21729 */   // Label 379: @21729
     /*  21729 */   GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(21756), // Rule ID 1110 //
     /*  21734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21741 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21749 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  21749 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i64),
     /*  21754 */     GIR_RootConstrainSelectedInstOperands,
     /*  21755 */     // GIR_Coverage, 1110,
     /*  21755 */     GIR_Done,
     /*  21756 */   // Label 380: @21756
     /*  21756 */   GIM_Reject,
     /*  21757 */ // Label 303: @21757
     /*  21757 */ GIM_Reject,
     /*  21758 */ // Label 160: @21758
     /*  21758 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(25255),
     /*  21763 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  21766 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  21769 */   GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(21905), // Rule ID 5417 //
     /*  21774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21778 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21782 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  21786 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  21790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  21794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21798 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  21802 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21807 */     // MIs[1] Operand 2
     /*  21807 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  21818 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  21822 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  21826 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  21830 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  21834 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21838 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  21842 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21847 */     // MIs[3] Operand 2
     /*  21847 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  21858 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  21860 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  21860 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  21863 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  21867 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  21872 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  21876 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  21880 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  21882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  21885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21887 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  21894 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21904 */     // GIR_Coverage, 5417,
     /*  21904 */     GIR_EraseRootFromParent_Done,
     /*  21905 */   // Label 382: @21905
     /*  21905 */   GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(22041), // Rule ID 5416 //
     /*  21910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21918 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  21922 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  21926 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  21930 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21934 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  21938 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21943 */     // MIs[1] Operand 2
     /*  21943 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  21954 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  21958 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  21962 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  21966 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  21970 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21974 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  21978 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21983 */     // MIs[3] Operand 2
     /*  21983 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  21994 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  21996 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  21996 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  21999 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  22003 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22012 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  22016 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22023 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22030 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22035 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22040 */     // GIR_Coverage, 5416,
     /*  22040 */     GIR_EraseRootFromParent_Done,
     /*  22041 */   // Label 383: @22041
     /*  22041 */   GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(22177), // Rule ID 5432 //
     /*  22046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22054 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22058 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22062 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22066 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  22070 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22074 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22079 */     // MIs[1] Operand 2
     /*  22079 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22090 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  22094 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22098 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22102 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  22106 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  22110 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22114 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22119 */     // MIs[3] Operand 2
     /*  22119 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  22130 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  22132 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  22132 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  22135 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i8_v8i16),
     /*  22139 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22144 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22148 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  22152 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22159 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22166 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22171 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22176 */     // GIR_Coverage, 5432,
     /*  22176 */     GIR_EraseRootFromParent_Done,
     /*  22177 */   // Label 384: @22177
     /*  22177 */   GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(22313), // Rule ID 5415 //
     /*  22182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22198 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22202 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22206 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22210 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22215 */     // MIs[1] Operand 2
     /*  22215 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22226 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  22230 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22234 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22238 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  22242 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  22246 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22250 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22255 */     // MIs[3] Operand 2
     /*  22255 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  22266 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  22268 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  22268 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  22271 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  22275 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22280 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22284 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  22288 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22295 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22302 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22307 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22312 */     // GIR_Coverage, 5415,
     /*  22312 */     GIR_EraseRootFromParent_Done,
     /*  22313 */   // Label 385: @22313
     /*  22313 */   GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(22449), // Rule ID 5414 //
     /*  22318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22342 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22346 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22351 */     // MIs[1] Operand 2
     /*  22351 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22362 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  22366 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22370 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22374 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  22378 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22382 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22386 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22391 */     // MIs[3] Operand 2
     /*  22391 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  22402 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  22404 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  22404 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  22407 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  22411 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22416 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22420 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  22424 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22431 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22438 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22443 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22448 */     // GIR_Coverage, 5414,
     /*  22448 */     GIR_EraseRootFromParent_Done,
     /*  22449 */   // Label 386: @22449
     /*  22449 */   GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(22582), // Rule ID 14257 //
     /*  22454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22458 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22462 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22466 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22470 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22474 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  22478 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22482 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  22486 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22491 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  22495 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  22499 */     // MIs[1] Operand 2
     /*  22499 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22510 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  22514 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  22518 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  22522 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  22526 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  22530 */     // MIs[5] Rn
     /*  22530 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  22535 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  22537 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, (undef:{ *:[v8i16] })), 0:{ *:[i64] }), (trunc:{ *:[v4i16] } (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$Rn)))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /*  22537 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  22540 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  22544 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22549 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22553 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22557 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22564 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22571 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22576 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22581 */     // GIR_Coverage, 14257,
     /*  22581 */     GIR_EraseRootFromParent_Done,
     /*  22582 */   // Label 387: @22582
     /*  22582 */   GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(22715), // Rule ID 7011 //
     /*  22587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22595 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  22599 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  22603 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22607 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  22611 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22615 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22620 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  22624 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22628 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22632 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  22636 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_UZP2),
     /*  22640 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  22644 */     // MIs[4] Rn
     /*  22644 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  22649 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  22653 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  22657 */     // MIs[3] Operand 2
     /*  22657 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  22668 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  22670 */     // (add:{ *:[v4i16] } (trunc:{ *:[v4i16] } (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$Rn)), (extract_subvector:{ *:[v4i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, (undef:{ *:[v8i16] })), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /*  22670 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  22673 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  22677 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22682 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22686 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22690 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22697 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22704 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22709 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22714 */     // GIR_Coverage, 7011,
     /*  22714 */     GIR_EraseRootFromParent_Done,
     /*  22715 */   // Label 388: @22715
     /*  22715 */   GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(22878), // Rule ID 14215 //
     /*  22720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  22744 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22748 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  22752 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22757 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22762 */     // MIs[1] Operand 2
     /*  22762 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22777 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22779 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  22779 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  22782 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  22786 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22791 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  22793 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  22796 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  22800 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22805 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  22808 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  22812 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  22815 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22820 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22825 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22830 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  22833 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  22837 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22842 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  22845 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22849 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  22853 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  22855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22860 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22867 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22872 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22877 */     // GIR_Coverage, 14215,
     /*  22877 */     GIR_EraseRootFromParent_Done,
     /*  22878 */   // Label 389: @22878
     /*  22878 */   GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(23041), // Rule ID 14212 //
     /*  22883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22887 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22891 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  22895 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  22899 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22903 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  22907 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  22911 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  22915 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22920 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22925 */     // MIs[1] Operand 2
     /*  22925 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  22936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22940 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22942 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  22942 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  22945 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  22949 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22954 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  22956 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  22959 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  22963 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22968 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  22971 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  22975 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  22978 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22983 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22988 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22993 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  22996 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  23000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23005 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23012 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  23016 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23023 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23030 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23035 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23040 */     // GIR_Coverage, 14212,
     /*  23040 */     GIR_EraseRootFromParent_Done,
     /*  23041 */   // Label 390: @23041
     /*  23041 */   GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(23191), // Rule ID 14219 //
     /*  23046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23054 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23058 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23062 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23066 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23070 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23074 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23079 */     // MIs[1] Operand 2
     /*  23079 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23094 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23096 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23096 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23099 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23103 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23108 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23110 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23113 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23117 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23122 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23125 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  23129 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23132 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23137 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23142 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23147 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23150 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  23154 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23159 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23162 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  23166 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23173 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23180 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23185 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23190 */     // GIR_Coverage, 14219,
     /*  23190 */     GIR_EraseRootFromParent_Done,
     /*  23191 */   // Label 391: @23191
     /*  23191 */   GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(23341), // Rule ID 14224 //
     /*  23196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23200 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23204 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23208 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23212 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23216 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  23220 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23224 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23229 */     // MIs[1] Operand 2
     /*  23229 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23244 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23246 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23246 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23249 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23253 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23258 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23260 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23263 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23267 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23272 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23275 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  23279 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23282 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23287 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23292 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23297 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23300 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  23304 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23309 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23312 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  23316 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23323 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23330 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23335 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23340 */     // GIR_Coverage, 14224,
     /*  23340 */     GIR_EraseRootFromParent_Done,
     /*  23341 */   // Label 392: @23341
     /*  23341 */   GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(23491), // Rule ID 14218 //
     /*  23346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23350 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23354 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23358 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23362 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23366 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23370 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23374 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23379 */     // MIs[1] Operand 2
     /*  23379 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23390 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23394 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23396 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23396 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23399 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23403 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23408 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23410 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23413 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23417 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23422 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23425 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  23429 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23432 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23437 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23442 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23447 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23450 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  23454 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23459 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23462 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  23466 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23473 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23480 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23485 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23490 */     // GIR_Coverage, 14218,
     /*  23490 */     GIR_EraseRootFromParent_Done,
     /*  23491 */   // Label 393: @23491
     /*  23491 */   GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(23654), // Rule ID 5405 //
     /*  23496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23500 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  23524 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23528 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  23532 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23537 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23542 */     // MIs[1] Operand 2
     /*  23542 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23553 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23555 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23555 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23558 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23562 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23567 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23569 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23572 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23576 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23581 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23584 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  23588 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23591 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23596 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23601 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23609 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  23613 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23618 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23621 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23625 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  23629 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23636 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23648 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23653 */     // GIR_Coverage, 5405,
     /*  23653 */     GIR_EraseRootFromParent_Done,
     /*  23654 */   // Label 394: @23654
     /*  23654 */   GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(23817), // Rule ID 5402 //
     /*  23659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23663 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23675 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23683 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  23687 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23691 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  23695 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23700 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23705 */     // MIs[1] Operand 2
     /*  23705 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23716 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23718 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23718 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23721 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23725 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23730 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23732 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23735 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23739 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23744 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23747 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  23751 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23754 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23759 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23764 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23769 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23772 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  23776 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23781 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23784 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23788 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  23792 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23799 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23806 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23811 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23816 */     // GIR_Coverage, 5402,
     /*  23816 */     GIR_EraseRootFromParent_Done,
     /*  23817 */   // Label 395: @23817
     /*  23817 */   GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(23967), // Rule ID 5427 //
     /*  23822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23826 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23830 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23834 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23838 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23850 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23854 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23859 */     // MIs[1] Operand 2
     /*  23859 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  23872 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23872 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  23875 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  23879 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23884 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  23886 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  23889 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  23893 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23898 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  23901 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  23905 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  23908 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23913 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23918 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23923 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23926 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  23930 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23935 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  23938 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  23942 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23949 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23956 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23961 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23966 */     // GIR_Coverage, 5427,
     /*  23966 */     GIR_EraseRootFromParent_Done,
     /*  23967 */   // Label 396: @23967
     /*  23967 */   GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(24117), // Rule ID 5435 //
     /*  23972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23980 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23984 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23988 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23992 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23996 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  24000 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24004 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24009 */     // MIs[1] Operand 2
     /*  24009 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24020 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24022 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24022 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24025 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24029 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24034 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24036 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24039 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24043 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24048 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24051 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  24055 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24058 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24063 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24068 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24073 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24076 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  24080 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24085 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24088 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  24092 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24099 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24106 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24111 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24116 */     // GIR_Coverage, 5435,
     /*  24116 */     GIR_EraseRootFromParent_Done,
     /*  24117 */   // Label 397: @24117
     /*  24117 */   GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(24267), // Rule ID 5426 //
     /*  24122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24126 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24134 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24138 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  24150 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24154 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24159 */     // MIs[1] Operand 2
     /*  24159 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24170 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24172 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24172 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24175 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24179 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24184 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24186 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24189 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24193 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24198 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24201 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  24205 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24208 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24213 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24218 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24223 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24226 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  24230 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24235 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24238 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  24242 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24249 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24256 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24266 */     // GIR_Coverage, 5426,
     /*  24266 */     GIR_EraseRootFromParent_Done,
     /*  24267 */   // Label 398: @24267
     /*  24267 */   GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(24336), // Rule ID 13646 //
     /*  24272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24287 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  24290 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  24295 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  24299 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  24303 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24308 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24313 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24317 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24319 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  24319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  24322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24326 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24330 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  24334 */     GIR_RootConstrainSelectedInstOperands,
     /*  24335 */     // GIR_Coverage, 13646,
     /*  24335 */     GIR_EraseRootFromParent_Done,
     /*  24336 */   // Label 399: @24336
     /*  24336 */   GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(24405), // Rule ID 13658 //
     /*  24341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24348 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24352 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24356 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  24359 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  24364 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  24368 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  24372 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24377 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24382 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24386 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24388 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  24388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
     /*  24391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  24403 */     GIR_RootConstrainSelectedInstOperands,
     /*  24404 */     // GIR_Coverage, 13658,
     /*  24404 */     GIR_EraseRootFromParent_Done,
     /*  24405 */   // Label 400: @24405
     /*  24405 */   GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(24461), // Rule ID 13608 //
     /*  24410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24417 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24421 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24425 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  24428 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  24433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24437 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24446 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24448 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 670:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  24448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  24451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24459 */     GIR_RootConstrainSelectedInstOperands,
     /*  24460 */     // GIR_Coverage, 13608,
     /*  24460 */     GIR_EraseRootFromParent_Done,
     /*  24461 */   // Label 401: @24461
     /*  24461 */   GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(24517), // Rule ID 13620 //
     /*  24466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24477 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24481 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  24484 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  24489 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24502 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24504 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 735:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  24504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  24507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24509 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24511 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24515 */     GIR_RootConstrainSelectedInstOperands,
     /*  24516 */     // GIR_Coverage, 13620,
     /*  24516 */     GIR_EraseRootFromParent_Done,
     /*  24517 */   // Label 402: @24517
     /*  24517 */   GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(24584), // Rule ID 13860 //
     /*  24522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  24537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  24541 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24546 */     // MIs[1] imm
     /*  24546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  24550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  24554 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  24558 */     // MIs[2] Operand 1
     /*  24558 */     // No operand predicates
     /*  24558 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24562 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  24566 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24568 */     // (add:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  24568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  24571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  24579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  24582 */     GIR_RootConstrainSelectedInstOperands,
     /*  24583 */     // GIR_Coverage, 13860,
     /*  24583 */     GIR_EraseRootFromParent_Done,
     /*  24584 */   // Label 403: @24584
     /*  24584 */   GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(24651), // Rule ID 13881 //
     /*  24589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24600 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  24604 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  24608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24613 */     // MIs[1] imm
     /*  24613 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  24617 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  24621 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  24625 */     // MIs[2] Operand 1
     /*  24625 */     // No operand predicates
     /*  24625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24629 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  24633 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24635 */     // (add:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  24635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  24638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  24642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  24646 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  24649 */     GIR_RootConstrainSelectedInstOperands,
     /*  24650 */     // GIR_Coverage, 13881,
     /*  24650 */     GIR_EraseRootFromParent_Done,
     /*  24651 */   // Label 404: @24651
     /*  24651 */   GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(24720), // Rule ID 1365 //
     /*  24656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24663 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24675 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  24678 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  24683 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  24687 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  24691 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24696 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24701 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24703 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  24703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  24706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24708 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  24710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  24718 */     GIR_RootConstrainSelectedInstOperands,
     /*  24719 */     // GIR_Coverage, 1365,
     /*  24719 */     GIR_EraseRootFromParent_Done,
     /*  24720 */   // Label 405: @24720
     /*  24720 */   GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(24789), // Rule ID 1488 //
     /*  24725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24732 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24736 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24740 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24744 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  24747 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  24752 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  24756 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  24760 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24770 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24772 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  24772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
     /*  24775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24777 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  24779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24783 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  24787 */     GIR_RootConstrainSelectedInstOperands,
     /*  24788 */     // GIR_Coverage, 1488,
     /*  24788 */     GIR_EraseRootFromParent_Done,
     /*  24789 */   // Label 406: @24789
     /*  24789 */   GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(24845), // Rule ID 993 //
     /*  24794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24801 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24805 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24809 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24813 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  24816 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  24821 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24825 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24830 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24832 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 670:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  24832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  24835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24837 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  24839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24843 */     GIR_RootConstrainSelectedInstOperands,
     /*  24844 */     // GIR_Coverage, 993,
     /*  24844 */     GIR_EraseRootFromParent_Done,
     /*  24845 */   // Label 407: @24845
     /*  24845 */   GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(24901), // Rule ID 1054 //
     /*  24850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24861 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24865 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  24869 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  24872 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  24877 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24881 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24886 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  24888 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 735:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  24888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  24891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24893 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  24895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  24899 */     GIR_RootConstrainSelectedInstOperands,
     /*  24900 */     // GIR_Coverage, 1054,
     /*  24900 */     GIR_EraseRootFromParent_Done,
     /*  24901 */   // Label 408: @24901
     /*  24901 */   GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(24968), // Rule ID 2238 //
     /*  24906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24913 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  24925 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  24929 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24934 */     // MIs[1] imm
     /*  24934 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  24938 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  24942 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  24946 */     // MIs[2] Operand 1
     /*  24946 */     // No operand predicates
     /*  24946 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  24950 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24952 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  24952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  24955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24957 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  24959 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  24963 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  24966 */     GIR_RootConstrainSelectedInstOperands,
     /*  24967 */     // GIR_Coverage, 2238,
     /*  24967 */     GIR_EraseRootFromParent_Done,
     /*  24968 */   // Label 409: @24968
     /*  24968 */   GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(25035), // Rule ID 2297 //
     /*  24973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  24976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24980 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  24992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  24996 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25001 */     // MIs[1] imm
     /*  25001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  25005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25009 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  25013 */     // MIs[2] Operand 1
     /*  25013 */     // No operand predicates
     /*  25013 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  25017 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  25019 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  25019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  25022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25024 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25030 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  25033 */     GIR_RootConstrainSelectedInstOperands,
     /*  25034 */     // GIR_Coverage, 2297,
     /*  25034 */     GIR_EraseRootFromParent_Done,
     /*  25035 */   // Label 410: @25035
     /*  25035 */   GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(25083), // Rule ID 13607 //
     /*  25040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25047 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25051 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  25055 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25059 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25064 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25068 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25070 */     // (add:{ *:[v4i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  25073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25081 */     GIR_RootConstrainSelectedInstOperands,
     /*  25082 */     // GIR_Coverage, 13607,
     /*  25082 */     GIR_EraseRootFromParent_Done,
     /*  25083 */   // Label 411: @25083
     /*  25083 */   GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(25131), // Rule ID 13619 //
     /*  25088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25095 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25099 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  25103 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25107 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25112 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25116 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25118 */     // (add:{ *:[v4i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  25121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25129 */     GIR_RootConstrainSelectedInstOperands,
     /*  25130 */     // GIR_Coverage, 13619,
     /*  25130 */     GIR_EraseRootFromParent_Done,
     /*  25131 */   // Label 412: @25131
     /*  25131 */   GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(25179), // Rule ID 992 //
     /*  25136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  25155 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25159 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25164 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25166 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  25169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25171 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25173 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25177 */     GIR_RootConstrainSelectedInstOperands,
     /*  25178 */     // GIR_Coverage, 992,
     /*  25178 */     GIR_EraseRootFromParent_Done,
     /*  25179 */   // Label 413: @25179
     /*  25179 */   GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(25227), // Rule ID 1053 //
     /*  25184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25191 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25199 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  25203 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25207 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25212 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25214 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  25217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25219 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25221 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25225 */     GIR_RootConstrainSelectedInstOperands,
     /*  25226 */     // GIR_Coverage, 1053,
     /*  25226 */     GIR_EraseRootFromParent_Done,
     /*  25227 */   // Label 414: @25227
     /*  25227 */   GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(25254), // Rule ID 1106 //
     /*  25232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25239 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25243 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25247 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  25247 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i16),
     /*  25252 */     GIR_RootConstrainSelectedInstOperands,
     /*  25253 */     // GIR_Coverage, 1106,
     /*  25253 */     GIR_Done,
     /*  25254 */   // Label 415: @25254
     /*  25254 */   GIM_Reject,
     /*  25255 */ // Label 381: @25255
     /*  25255 */ GIM_Reject,
     /*  25256 */ // Label 161: @25256
     /*  25256 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(31433),
     /*  25261 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  25264 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  25267 */   GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(25385), // Rule ID 13784 //
     /*  25272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  25287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25295 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  25299 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25303 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25307 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25311 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25315 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25319 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25323 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25328 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25332 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25336 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25340 */     // MIs[4] Operand 1
     /*  25340 */     // No operand predicates
     /*  25340 */     // MIs[2] Operand 2
     /*  25340 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25355 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25357 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25364 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  25367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25380 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25383 */     GIR_RootConstrainSelectedInstOperands,
     /*  25384 */     // GIR_Coverage, 13784,
     /*  25384 */     GIR_EraseRootFromParent_Done,
     /*  25385 */   // Label 417: @25385
     /*  25385 */   GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(25503), // Rule ID 13785 //
     /*  25390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  25405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25421 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25425 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25429 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25433 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25437 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25441 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25446 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25450 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25454 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25458 */     // MIs[4] Operand 1
     /*  25458 */     // No operand predicates
     /*  25458 */     // MIs[2] Operand 2
     /*  25458 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25469 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25473 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25475 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25482 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  25485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25498 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25501 */     GIR_RootConstrainSelectedInstOperands,
     /*  25502 */     // GIR_Coverage, 13785,
     /*  25502 */     GIR_EraseRootFromParent_Done,
     /*  25503 */   // Label 418: @25503
     /*  25503 */   GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(25621), // Rule ID 13820 //
     /*  25508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25519 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  25523 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25527 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25531 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  25535 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25539 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25543 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25547 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25551 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25555 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25559 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25564 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25568 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25572 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25576 */     // MIs[4] Operand 1
     /*  25576 */     // No operand predicates
     /*  25576 */     // MIs[2] Operand 2
     /*  25576 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25591 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25593 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25600 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  25603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25616 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25619 */     GIR_RootConstrainSelectedInstOperands,
     /*  25620 */     // GIR_Coverage, 13820,
     /*  25620 */     GIR_EraseRootFromParent_Done,
     /*  25621 */   // Label 419: @25621
     /*  25621 */   GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(25739), // Rule ID 13821 //
     /*  25626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25633 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25637 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  25641 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25645 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25649 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25653 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25657 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25661 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25665 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25669 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25673 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25677 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25682 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25686 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25690 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25694 */     // MIs[4] Operand 1
     /*  25694 */     // No operand predicates
     /*  25694 */     // MIs[2] Operand 2
     /*  25694 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25709 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25711 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25718 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  25721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25734 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25737 */     GIR_RootConstrainSelectedInstOperands,
     /*  25738 */     // GIR_Coverage, 13821,
     /*  25738 */     GIR_EraseRootFromParent_Done,
     /*  25739 */   // Label 420: @25739
     /*  25739 */   GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(25857), // Rule ID 2043 //
     /*  25744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25751 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25755 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25759 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  25763 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25767 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25771 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  25775 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25779 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25783 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25787 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25791 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25795 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25799 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25804 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25808 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25812 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25816 */     // MIs[4] Operand 1
     /*  25816 */     // No operand predicates
     /*  25816 */     // MIs[2] Operand 2
     /*  25816 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25827 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25829 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25836 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  25839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25841 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25852 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25855 */     GIR_RootConstrainSelectedInstOperands,
     /*  25856 */     // GIR_Coverage, 2043,
     /*  25856 */     GIR_EraseRootFromParent_Done,
     /*  25857 */   // Label 421: @25857
     /*  25857 */   GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(25975), // Rule ID 13783 //
     /*  25862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25869 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  25881 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25885 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  25889 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25893 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25897 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25901 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  25905 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  25909 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25913 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  25917 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  25922 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  25926 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  25930 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  25934 */     // MIs[4] Operand 1
     /*  25934 */     // No operand predicates
     /*  25934 */     // MIs[2] Operand 2
     /*  25934 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  25945 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  25947 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  25954 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  25954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  25957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25959 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  25966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  25970 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  25973 */     GIR_RootConstrainSelectedInstOperands,
     /*  25974 */     // GIR_Coverage, 13783,
     /*  25974 */     GIR_EraseRootFromParent_Done,
     /*  25975 */   // Label 422: @25975
     /*  25975 */   GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(26093), // Rule ID 2095 //
     /*  25980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25987 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  25999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  26011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26015 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26019 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26023 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26027 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26031 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26035 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26040 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26044 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26048 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26052 */     // MIs[4] Operand 1
     /*  26052 */     // No operand predicates
     /*  26052 */     // MIs[2] Operand 2
     /*  26052 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  26063 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26065 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26072 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  26075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26077 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  26088 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  26091 */     GIR_RootConstrainSelectedInstOperands,
     /*  26092 */     // GIR_Coverage, 2095,
     /*  26092 */     GIR_EraseRootFromParent_Done,
     /*  26093 */   // Label 423: @26093
     /*  26093 */   GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(26211), // Rule ID 13819 //
     /*  26098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26105 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26113 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  26117 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26121 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26125 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26129 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26133 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26137 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26141 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26145 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26149 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26153 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26158 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26162 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26166 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26170 */     // MIs[4] Operand 1
     /*  26170 */     // No operand predicates
     /*  26170 */     // MIs[2] Operand 2
     /*  26170 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  26181 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26183 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26190 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  26193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26195 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  26206 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  26209 */     GIR_RootConstrainSelectedInstOperands,
     /*  26210 */     // GIR_Coverage, 13819,
     /*  26210 */     GIR_EraseRootFromParent_Done,
     /*  26211 */   // Label 424: @26211
     /*  26211 */   GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(26298), // Rule ID 13690 //
     /*  26216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  26231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  26243 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  26246 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  26251 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26255 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  26259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26263 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  26265 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26272 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26279 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  26279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
     /*  26282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  26296 */     GIR_RootConstrainSelectedInstOperands,
     /*  26297 */     // GIR_Coverage, 13690,
     /*  26297 */     GIR_EraseRootFromParent_Done,
     /*  26298 */   // Label 425: @26298
     /*  26298 */   GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(26385), // Rule ID 13718 //
     /*  26303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  26318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  26330 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  26333 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  26338 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26342 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  26346 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  26352 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26359 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26366 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  26366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
     /*  26369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26371 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  26383 */     GIR_RootConstrainSelectedInstOperands,
     /*  26384 */     // GIR_Coverage, 13718,
     /*  26384 */     GIR_EraseRootFromParent_Done,
     /*  26385 */   // Label 426: @26385
     /*  26385 */   GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(26472), // Rule ID 1699 //
     /*  26390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26397 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  26409 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  26421 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  26424 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  26429 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26433 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  26437 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  26439 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26446 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26453 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))))  =>  (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  26453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
     /*  26456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26458 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  26470 */     GIR_RootConstrainSelectedInstOperands,
     /*  26471 */     // GIR_Coverage, 1699,
     /*  26471 */     GIR_EraseRootFromParent_Done,
     /*  26472 */   // Label 427: @26472
     /*  26472 */   GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(26559), // Rule ID 1777 //
     /*  26477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26484 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26488 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26492 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  26496 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26500 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26504 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  26508 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  26511 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  26516 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26520 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  26524 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  26526 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26533 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  26540 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))))  =>  (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  26540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
     /*  26543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26545 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  26552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  26557 */     GIR_RootConstrainSelectedInstOperands,
     /*  26558 */     // GIR_Coverage, 1777,
     /*  26558 */     GIR_EraseRootFromParent_Done,
     /*  26559 */   // Label 428: @26559
     /*  26559 */   GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(26674), // Rule ID 13779 //
     /*  26564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  26579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26583 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26587 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26591 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26595 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26599 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26603 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26607 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26611 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26615 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26620 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26624 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26628 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26632 */     // MIs[4] Operand 1
     /*  26632 */     // No operand predicates
     /*  26632 */     // MIs[2] Operand 2
     /*  26632 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  26643 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26652 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26654 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  26657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26659 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  26665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  26669 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  26672 */     GIR_RootConstrainSelectedInstOperands,
     /*  26673 */     // GIR_Coverage, 13779,
     /*  26673 */     GIR_EraseRootFromParent_Done,
     /*  26674 */   // Label 429: @26674
     /*  26674 */   GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(26789), // Rule ID 13778 //
     /*  26679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26686 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26690 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  26694 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26698 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26707 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  26711 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26715 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26719 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26723 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26727 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26731 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26735 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26740 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26744 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26748 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26752 */     // MIs[4] Operand 1
     /*  26752 */     // No operand predicates
     /*  26752 */     // MIs[2] Operand 2
     /*  26752 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  26763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26767 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26769 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  26772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26780 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  26784 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  26787 */     GIR_RootConstrainSelectedInstOperands,
     /*  26788 */     // GIR_Coverage, 13778,
     /*  26788 */     GIR_EraseRootFromParent_Done,
     /*  26789 */   // Label 430: @26789
     /*  26789 */   GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(26904), // Rule ID 13815 //
     /*  26794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  26809 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26813 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26817 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  26821 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26825 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26829 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26833 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26837 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26841 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26845 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26850 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26854 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26858 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26862 */     // MIs[4] Operand 1
     /*  26862 */     // No operand predicates
     /*  26862 */     // MIs[2] Operand 2
     /*  26862 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  26873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26882 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26884 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  26887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  26895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  26899 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  26902 */     GIR_RootConstrainSelectedInstOperands,
     /*  26903 */     // GIR_Coverage, 13815,
     /*  26903 */     GIR_EraseRootFromParent_Done,
     /*  26904 */   // Label 431: @26904
     /*  26904 */   GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(27019), // Rule ID 13814 //
     /*  26909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  26924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26928 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26932 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  26941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  26945 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26949 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  26953 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  26957 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  26961 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  26965 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  26970 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  26974 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  26978 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  26982 */     // MIs[4] Operand 1
     /*  26982 */     // No operand predicates
     /*  26982 */     // MIs[2] Operand 2
     /*  26982 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  26993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26997 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  26999 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  26999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  27002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27004 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  27010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27014 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27017 */     GIR_RootConstrainSelectedInstOperands,
     /*  27018 */     // GIR_Coverage, 13814,
     /*  27018 */     GIR_EraseRootFromParent_Done,
     /*  27019 */   // Label 432: @27019
     /*  27019 */   GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(27088), // Rule ID 1797 //
     /*  27024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  27039 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27043 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  27047 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  27051 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27055 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  27057 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27064 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27071 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  27074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  27076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27086 */     GIR_RootConstrainSelectedInstOperands,
     /*  27087 */     // GIR_Coverage, 1797,
     /*  27087 */     GIR_EraseRootFromParent_Done,
     /*  27088 */   // Label 433: @27088
     /*  27088 */   GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(27157), // Rule ID 1796 //
     /*  27093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  27108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27112 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  27116 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  27120 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27124 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  27126 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27133 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27140 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  27143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  27145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27155 */     GIR_RootConstrainSelectedInstOperands,
     /*  27156 */     // GIR_Coverage, 1796,
     /*  27156 */     GIR_EraseRootFromParent_Done,
     /*  27157 */   // Label 434: @27157
     /*  27157 */   GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(27226), // Rule ID 1719 //
     /*  27162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  27177 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27181 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  27185 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  27189 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27193 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  27195 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27202 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27209 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i16_v4i32),
     /*  27212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  27214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27224 */     GIR_RootConstrainSelectedInstOperands,
     /*  27225 */     // GIR_Coverage, 1719,
     /*  27225 */     GIR_EraseRootFromParent_Done,
     /*  27226 */   // Label 435: @27226
     /*  27226 */   GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(27295), // Rule ID 1795 //
     /*  27231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27238 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27242 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  27246 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  27254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  27258 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27262 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  27264 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27271 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27278 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  27281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  27283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27293 */     GIR_RootConstrainSelectedInstOperands,
     /*  27294 */     // GIR_Coverage, 1795,
     /*  27294 */     GIR_EraseRootFromParent_Done,
     /*  27295 */   // Label 436: @27295
     /*  27295 */   GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(27364), // Rule ID 1794 //
     /*  27300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27307 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  27315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27319 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  27323 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  27327 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27331 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  27333 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27340 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27347 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  27350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  27352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27362 */     GIR_RootConstrainSelectedInstOperands,
     /*  27363 */     // GIR_Coverage, 1794,
     /*  27363 */     GIR_EraseRootFromParent_Done,
     /*  27364 */   // Label 437: @27364
     /*  27364 */   GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(27479), // Rule ID 13777 //
     /*  27369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27392 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27404 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27408 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27412 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27416 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27420 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27424 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27429 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27433 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27437 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27441 */     // MIs[4] Operand 1
     /*  27441 */     // No operand predicates
     /*  27441 */     // MIs[2] Operand 2
     /*  27441 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  27452 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  27457 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27459 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  27462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27464 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27466 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  27470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27474 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27477 */     GIR_RootConstrainSelectedInstOperands,
     /*  27478 */     // GIR_Coverage, 13777,
     /*  27478 */     GIR_EraseRootFromParent_Done,
     /*  27479 */   // Label 438: @27479
     /*  27479 */   GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(27594), // Rule ID 2041 //
     /*  27484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27491 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27507 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  27516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27524 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27528 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27532 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27536 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27540 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27544 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27549 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27553 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27557 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27561 */     // MIs[4] Operand 1
     /*  27561 */     // No operand predicates
     /*  27561 */     // MIs[2] Operand 2
     /*  27561 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  27572 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27574 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  27577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27579 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  27585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27589 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27592 */     GIR_RootConstrainSelectedInstOperands,
     /*  27593 */     // GIR_Coverage, 2041,
     /*  27593 */     GIR_EraseRootFromParent_Done,
     /*  27594 */   // Label 439: @27594
     /*  27594 */   GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(27709), // Rule ID 13813 //
     /*  27599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27606 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27610 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27614 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27618 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27622 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27626 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27630 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27634 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27638 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27642 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27646 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27650 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27654 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27659 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27663 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27667 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27671 */     // MIs[4] Operand 1
     /*  27671 */     // No operand predicates
     /*  27671 */     // MIs[2] Operand 2
     /*  27671 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  27682 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  27687 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27689 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  27692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27694 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  27700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27704 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27707 */     GIR_RootConstrainSelectedInstOperands,
     /*  27708 */     // GIR_Coverage, 13813,
     /*  27708 */     GIR_EraseRootFromParent_Done,
     /*  27709 */   // Label 440: @27709
     /*  27709 */   GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(27824), // Rule ID 2093 //
     /*  27714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27721 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27725 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27729 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27733 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27737 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27741 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  27746 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27750 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27754 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27758 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27762 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27766 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27770 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27774 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27779 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27783 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27787 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27791 */     // MIs[4] Operand 1
     /*  27791 */     // No operand predicates
     /*  27791 */     // MIs[2] Operand 2
     /*  27791 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  27802 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27804 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  27807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27809 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  27815 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27819 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27822 */     GIR_RootConstrainSelectedInstOperands,
     /*  27823 */     // GIR_Coverage, 2093,
     /*  27823 */     GIR_EraseRootFromParent_Done,
     /*  27824 */   // Label 441: @27824
     /*  27824 */   GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(27891), // Rule ID 13704 //
     /*  27829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27848 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27852 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27856 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  27858 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27865 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27872 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
     /*  27875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27889 */     GIR_RootConstrainSelectedInstOperands,
     /*  27890 */     // GIR_Coverage, 13704,
     /*  27890 */     GIR_EraseRootFromParent_Done,
     /*  27891 */   // Label 442: @27891
     /*  27891 */   GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(27958), // Rule ID 13738 //
     /*  27896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27911 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27915 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27919 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27923 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  27925 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27932 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27939 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  27939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
     /*  27942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  27956 */     GIR_RootConstrainSelectedInstOperands,
     /*  27957 */     // GIR_Coverage, 13738,
     /*  27957 */     GIR_EraseRootFromParent_Done,
     /*  27958 */   // Label 443: @27958
     /*  27958 */   GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(28025), // Rule ID 1731 //
     /*  27963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27970 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27974 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27978 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27982 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27986 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27990 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  27992 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27999 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28006 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
     /*  28009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28011 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28023 */     GIR_RootConstrainSelectedInstOperands,
     /*  28024 */     // GIR_Coverage, 1731,
     /*  28024 */     GIR_EraseRootFromParent_Done,
     /*  28025 */   // Label 444: @28025
     /*  28025 */   GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(28092), // Rule ID 1821 //
     /*  28030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28037 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28045 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28049 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28053 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28057 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  28059 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28066 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28073 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
     /*  28076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28078 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28090 */     GIR_RootConstrainSelectedInstOperands,
     /*  28091 */     // GIR_Coverage, 1821,
     /*  28091 */     GIR_EraseRootFromParent_Done,
     /*  28092 */   // Label 445: @28092
     /*  28092 */   GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(28173), // Rule ID 13688 //
     /*  28097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28104 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28108 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28112 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28116 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28120 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  28124 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  28127 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  28132 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28136 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  28140 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28145 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28154 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28156 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  28156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  28159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  28167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  28171 */     GIR_RootConstrainSelectedInstOperands,
     /*  28172 */     // GIR_Coverage, 13688,
     /*  28172 */     GIR_EraseRootFromParent_Done,
     /*  28173 */   // Label 446: @28173
     /*  28173 */   GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(28254), // Rule ID 13716 //
     /*  28178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28185 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28189 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28193 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  28205 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  28208 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  28213 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28217 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  28221 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28226 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28235 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28237 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  28237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
     /*  28240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  28248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  28252 */     GIR_RootConstrainSelectedInstOperands,
     /*  28253 */     // GIR_Coverage, 13716,
     /*  28253 */     GIR_EraseRootFromParent_Done,
     /*  28254 */   // Label 447: @28254
     /*  28254 */   GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(28335), // Rule ID 1697 //
     /*  28259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28266 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28270 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28274 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28278 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28286 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  28290 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  28293 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  28298 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28302 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  28306 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28311 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28316 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28318 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  28318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  28321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28323 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  28329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  28333 */     GIR_RootConstrainSelectedInstOperands,
     /*  28334 */     // GIR_Coverage, 1697,
     /*  28334 */     GIR_EraseRootFromParent_Done,
     /*  28335 */   // Label 448: @28335
     /*  28335 */   GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(28416), // Rule ID 1775 //
     /*  28340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28363 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28367 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  28371 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  28374 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  28379 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28383 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  28387 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28392 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28397 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28399 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  28399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
     /*  28402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28404 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  28410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  28414 */     GIR_RootConstrainSelectedInstOperands,
     /*  28415 */     // GIR_Coverage, 1775,
     /*  28415 */     GIR_EraseRootFromParent_Done,
     /*  28416 */   // Label 449: @28416
     /*  28416 */   GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(28508), // Rule ID 13782 //
     /*  28421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28428 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28432 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28436 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28440 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28444 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28448 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28452 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28456 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28460 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28465 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28469 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28473 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28477 */     // MIs[3] Operand 1
     /*  28477 */     // No operand predicates
     /*  28477 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28486 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28488 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  28499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28506 */     GIR_RootConstrainSelectedInstOperands,
     /*  28507 */     // GIR_Coverage, 13782,
     /*  28507 */     GIR_EraseRootFromParent_Done,
     /*  28508 */   // Label 450: @28508
     /*  28508 */   GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(28600), // Rule ID 13781 //
     /*  28513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28528 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28532 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28536 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28541 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  28545 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28549 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28553 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28557 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28562 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28566 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28570 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28574 */     // MIs[3] Operand 1
     /*  28574 */     // No operand predicates
     /*  28574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28578 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28580 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  28591 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28595 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28598 */     GIR_RootConstrainSelectedInstOperands,
     /*  28599 */     // GIR_Coverage, 13781,
     /*  28599 */     GIR_EraseRootFromParent_Done,
     /*  28600 */   // Label 451: @28600
     /*  28600 */   GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(28692), // Rule ID 13818 //
     /*  28605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28612 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28616 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28620 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28624 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28628 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28632 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28636 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28640 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28644 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28649 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28653 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28657 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28661 */     // MIs[3] Operand 1
     /*  28661 */     // No operand predicates
     /*  28661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28670 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28672 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  28675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  28683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28687 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28690 */     GIR_RootConstrainSelectedInstOperands,
     /*  28691 */     // GIR_Coverage, 13818,
     /*  28691 */     GIR_EraseRootFromParent_Done,
     /*  28692 */   // Label 452: @28692
     /*  28692 */   GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(28784), // Rule ID 13817 //
     /*  28697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28716 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28720 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28725 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  28729 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28733 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28737 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28741 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28746 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28750 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28754 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28758 */     // MIs[3] Operand 1
     /*  28758 */     // No operand predicates
     /*  28758 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28762 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28764 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  28767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28769 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28771 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  28775 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28779 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28782 */     GIR_RootConstrainSelectedInstOperands,
     /*  28783 */     // GIR_Coverage, 13817,
     /*  28783 */     GIR_EraseRootFromParent_Done,
     /*  28784 */   // Label 453: @28784
     /*  28784 */   GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(28876), // Rule ID 13780 //
     /*  28789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28796 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28812 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28824 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28828 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28832 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28837 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28841 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28845 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28849 */     // MIs[3] Operand 1
     /*  28849 */     // No operand predicates
     /*  28849 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28854 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28856 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28861 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  28867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28871 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28874 */     GIR_RootConstrainSelectedInstOperands,
     /*  28875 */     // GIR_Coverage, 13780,
     /*  28875 */     GIR_EraseRootFromParent_Done,
     /*  28876 */   // Label 454: @28876
     /*  28876 */   GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(28968), // Rule ID 2042 //
     /*  28881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28888 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28896 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28900 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28904 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28908 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  28917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28925 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  28929 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28934 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  28938 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28942 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28946 */     // MIs[3] Operand 1
     /*  28946 */     // No operand predicates
     /*  28946 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  28948 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28953 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  28955 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  28959 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  28963 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  28966 */     GIR_RootConstrainSelectedInstOperands,
     /*  28967 */     // GIR_Coverage, 2042,
     /*  28967 */     GIR_EraseRootFromParent_Done,
     /*  28968 */   // Label 455: @28968
     /*  28968 */   GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(29060), // Rule ID 13816 //
     /*  28973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28980 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28996 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29000 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  29004 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29008 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29012 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  29016 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29021 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  29025 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29029 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29033 */     // MIs[3] Operand 1
     /*  29033 */     // No operand predicates
     /*  29033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29038 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  29040 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  29043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29045 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29047 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  29055 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  29058 */     GIR_RootConstrainSelectedInstOperands,
     /*  29059 */     // GIR_Coverage, 13816,
     /*  29059 */     GIR_EraseRootFromParent_Done,
     /*  29060 */   // Label 456: @29060
     /*  29060 */   GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(29152), // Rule ID 2094 //
     /*  29065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29072 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29080 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  29084 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29088 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29092 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29097 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29101 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29105 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29109 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  29113 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29118 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  29122 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29126 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29130 */     // MIs[3] Operand 1
     /*  29130 */     // No operand predicates
     /*  29130 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  29132 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  29135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29137 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29139 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  29147 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  29150 */     GIR_RootConstrainSelectedInstOperands,
     /*  29151 */     // GIR_Coverage, 2094,
     /*  29151 */     GIR_EraseRootFromParent_Done,
     /*  29152 */   // Label 457: @29152
     /*  29152 */   GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(29203), // Rule ID 13730 //
     /*  29157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  29172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29176 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29180 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29182 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29189 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  29192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  29196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29201 */     GIR_RootConstrainSelectedInstOperands,
     /*  29202 */     // GIR_Coverage, 13730,
     /*  29202 */     GIR_EraseRootFromParent_Done,
     /*  29203 */   // Label 458: @29203
     /*  29203 */   GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(29254), // Rule ID 13698 //
     /*  29208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29215 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29219 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  29223 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29227 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29231 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29233 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29240 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
     /*  29243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  29247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29252 */     GIR_RootConstrainSelectedInstOperands,
     /*  29253 */     // GIR_Coverage, 13698,
     /*  29253 */     GIR_EraseRootFromParent_Done,
     /*  29254 */   // Label 459: @29254
     /*  29254 */   GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(29305), // Rule ID 13729 //
     /*  29259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  29274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29278 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29282 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29284 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29291 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  29294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  29298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29303 */     GIR_RootConstrainSelectedInstOperands,
     /*  29304 */     // GIR_Coverage, 13729,
     /*  29304 */     GIR_EraseRootFromParent_Done,
     /*  29305 */   // Label 460: @29305
     /*  29305 */   GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(29356), // Rule ID 1813 //
     /*  29310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  29329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29333 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29335 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29342 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  29345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29347 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  29349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29354 */     GIR_RootConstrainSelectedInstOperands,
     /*  29355 */     // GIR_Coverage, 1813,
     /*  29355 */     GIR_EraseRootFromParent_Done,
     /*  29356 */   // Label 461: @29356
     /*  29356 */   GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(29407), // Rule ID 1725 //
     /*  29361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29368 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  29380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29384 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29386 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29393 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
     /*  29396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29398 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  29400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29405 */     GIR_RootConstrainSelectedInstOperands,
     /*  29406 */     // GIR_Coverage, 1725,
     /*  29406 */     GIR_EraseRootFromParent_Done,
     /*  29407 */   // Label 462: @29407
     /*  29407 */   GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(29458), // Rule ID 1812 //
     /*  29412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29423 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29427 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  29431 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29435 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29437 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29444 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  29447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  29449 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  29451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  29456 */     GIR_RootConstrainSelectedInstOperands,
     /*  29457 */     // GIR_Coverage, 1812,
     /*  29457 */     GIR_EraseRootFromParent_Done,
     /*  29458 */   // Label 463: @29458
     /*  29458 */   GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(29527), // Rule ID 13652 //
     /*  29463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29474 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29478 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  29481 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  29486 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  29490 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  29494 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29499 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29508 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29510 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 669:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  29510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  29513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29517 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29521 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  29525 */     GIR_RootConstrainSelectedInstOperands,
     /*  29526 */     // GIR_Coverage, 13652,
     /*  29526 */     GIR_EraseRootFromParent_Done,
     /*  29527 */   // Label 464: @29527
     /*  29527 */   GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(29596), // Rule ID 13664 //
     /*  29532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29547 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  29550 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  29555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  29559 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  29563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29568 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29573 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29577 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29579 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 734:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  29579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
     /*  29582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  29594 */     GIR_RootConstrainSelectedInstOperands,
     /*  29595 */     // GIR_Coverage, 13664,
     /*  29595 */     GIR_EraseRootFromParent_Done,
     /*  29596 */   // Label 465: @29596
     /*  29596 */   GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(29652), // Rule ID 13614 //
     /*  29601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29616 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  29619 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  29624 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  29628 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29633 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29637 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29639 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 670:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  29639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  29642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29650 */     GIR_RootConstrainSelectedInstOperands,
     /*  29651 */     // GIR_Coverage, 13614,
     /*  29651 */     GIR_EraseRootFromParent_Done,
     /*  29652 */   // Label 466: @29652
     /*  29652 */   GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(29708), // Rule ID 13626 //
     /*  29657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29672 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  29675 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  29680 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  29684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29689 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29693 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29695 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 735:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  29695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  29698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29706 */     GIR_RootConstrainSelectedInstOperands,
     /*  29707 */     // GIR_Coverage, 13626,
     /*  29707 */     GIR_EraseRootFromParent_Done,
     /*  29708 */   // Label 467: @29708
     /*  29708 */   GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(29775), // Rule ID 13866 //
     /*  29713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  29728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  29732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29737 */     // MIs[1] imm
     /*  29737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29745 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  29749 */     // MIs[2] Operand 1
     /*  29749 */     // No operand predicates
     /*  29749 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29753 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  29757 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  29759 */     // (add:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  29759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  29762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29770 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  29773 */     GIR_RootConstrainSelectedInstOperands,
     /*  29774 */     // GIR_Coverage, 13866,
     /*  29774 */     GIR_EraseRootFromParent_Done,
     /*  29775 */   // Label 468: @29775
     /*  29775 */   GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(29842), // Rule ID 13887 //
     /*  29780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  29795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  29799 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29804 */     // MIs[1] imm
     /*  29804 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29808 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29812 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  29816 */     // MIs[2] Operand 1
     /*  29816 */     // No operand predicates
     /*  29816 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29820 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  29824 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  29826 */     // (add:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  29826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  29829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29833 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29837 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  29840 */     GIR_RootConstrainSelectedInstOperands,
     /*  29841 */     // GIR_Coverage, 13887,
     /*  29841 */     GIR_EraseRootFromParent_Done,
     /*  29842 */   // Label 469: @29842
     /*  29842 */   GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(29911), // Rule ID 1371 //
     /*  29847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29854 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29866 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  29869 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  29874 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  29878 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  29882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29892 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29894 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 669:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  29894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  29897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29899 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29901 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29905 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  29909 */     GIR_RootConstrainSelectedInstOperands,
     /*  29910 */     // GIR_Coverage, 1371,
     /*  29910 */     GIR_EraseRootFromParent_Done,
     /*  29911 */   // Label 470: @29911
     /*  29911 */   GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(29980), // Rule ID 1494 //
     /*  29916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29923 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  29935 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  29938 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  29943 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  29947 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  29951 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29956 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29961 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29963 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 734:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  29963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
     /*  29966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29968 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29970 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  29978 */     GIR_RootConstrainSelectedInstOperands,
     /*  29979 */     // GIR_Coverage, 1494,
     /*  29979 */     GIR_EraseRootFromParent_Done,
     /*  29980 */   // Label 471: @29980
     /*  29980 */   GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(30036), // Rule ID 999 //
     /*  29985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  30004 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  30007 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  30012 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  30016 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30021 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30023 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 670:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  30026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30028 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30034 */     GIR_RootConstrainSelectedInstOperands,
     /*  30035 */     // GIR_Coverage, 999,
     /*  30035 */     GIR_EraseRootFromParent_Done,
     /*  30036 */   // Label 472: @30036
     /*  30036 */   GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(30092), // Rule ID 1060 //
     /*  30041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30048 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  30060 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  30063 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  30068 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  30072 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30077 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30079 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 735:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  30082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30084 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30090 */     GIR_RootConstrainSelectedInstOperands,
     /*  30091 */     // GIR_Coverage, 1060,
     /*  30091 */     GIR_EraseRootFromParent_Done,
     /*  30092 */   // Label 473: @30092
     /*  30092 */   GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(30159), // Rule ID 2244 //
     /*  30097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30104 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30108 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30112 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  30116 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  30120 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30125 */     // MIs[1] imm
     /*  30125 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  30129 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30133 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  30137 */     // MIs[2] Operand 1
     /*  30137 */     // No operand predicates
     /*  30137 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  30141 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30143 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  30143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  30146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30148 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30154 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  30157 */     GIR_RootConstrainSelectedInstOperands,
     /*  30158 */     // GIR_Coverage, 2244,
     /*  30158 */     GIR_EraseRootFromParent_Done,
     /*  30159 */   // Label 474: @30159
     /*  30159 */   GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(30226), // Rule ID 2303 //
     /*  30164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30171 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30175 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30179 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  30183 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  30187 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30192 */     // MIs[1] imm
     /*  30192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  30196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30200 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  30204 */     // MIs[2] Operand 1
     /*  30204 */     // No operand predicates
     /*  30204 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  30208 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30210 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  30210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  30213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30215 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30217 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30221 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  30224 */     GIR_RootConstrainSelectedInstOperands,
     /*  30225 */     // GIR_Coverage, 2303,
     /*  30225 */     GIR_EraseRootFromParent_Done,
     /*  30226 */   // Label 475: @30226
     /*  30226 */   GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(30296), // Rule ID 7007 //
     /*  30231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  30243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  30247 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  30251 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30256 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30261 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30265 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  30269 */     // MIs[2] Rn
     /*  30269 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  30274 */     // MIs[2] Rm
     /*  30274 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  30279 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30281 */     // (add:{ *:[v4i32] } (AArch64uzp1:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm), (AArch64uzp2:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm))  =>  (ADDPv4i32:{ *:[v4i32] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rm)
     /*  30281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  30284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  30294 */     GIR_RootConstrainSelectedInstOperands,
     /*  30295 */     // GIR_Coverage, 7007,
     /*  30295 */     GIR_EraseRootFromParent_Done,
     /*  30296 */   // Label 476: @30296
     /*  30296 */   GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(30366), // Rule ID 14253 //
     /*  30301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30305 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30309 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  30313 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  30317 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  30321 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30326 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  30339 */     // MIs[2] Rn
     /*  30339 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  30344 */     // MIs[2] Rm
     /*  30344 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  30349 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30351 */     // (add:{ *:[v4i32] } (AArch64uzp2:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm), (AArch64uzp1:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm))  =>  (ADDPv4i32:{ *:[v4i32] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rm)
     /*  30351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  30354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  30364 */     GIR_RootConstrainSelectedInstOperands,
     /*  30365 */     // GIR_Coverage, 14253,
     /*  30365 */     GIR_EraseRootFromParent_Done,
     /*  30366 */   // Label 477: @30366
     /*  30366 */   GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(30429), // Rule ID 1793 //
     /*  30371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30378 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30382 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30386 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30390 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30395 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30399 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30403 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30407 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30412 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30414 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  30417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30423 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30427 */     GIR_RootConstrainSelectedInstOperands,
     /*  30428 */     // GIR_Coverage, 1793,
     /*  30428 */     GIR_EraseRootFromParent_Done,
     /*  30429 */   // Label 478: @30429
     /*  30429 */   GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(30492), // Rule ID 1792 //
     /*  30434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30441 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30445 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30449 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30453 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30458 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30462 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30466 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30470 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30475 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30477 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  30480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30482 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30486 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30490 */     GIR_RootConstrainSelectedInstOperands,
     /*  30491 */     // GIR_Coverage, 1792,
     /*  30491 */     GIR_EraseRootFromParent_Done,
     /*  30492 */   // Label 479: @30492
     /*  30492 */   GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(30555), // Rule ID 1718 //
     /*  30497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  30512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30516 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30525 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  30529 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30533 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30538 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30540 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i16_v4i32),
     /*  30543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30549 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30553 */     GIR_RootConstrainSelectedInstOperands,
     /*  30554 */     // GIR_Coverage, 1718,
     /*  30554 */     GIR_EraseRootFromParent_Done,
     /*  30555 */   // Label 480: @30555
     /*  30555 */   GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(30618), // Rule ID 1791 //
     /*  30560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30592 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30596 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30601 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30603 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  30606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30616 */     GIR_RootConstrainSelectedInstOperands,
     /*  30617 */     // GIR_Coverage, 1791,
     /*  30617 */     GIR_EraseRootFromParent_Done,
     /*  30618 */   // Label 481: @30618
     /*  30618 */   GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(30681), // Rule ID 1790 //
     /*  30623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30642 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30647 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  30651 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30655 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30659 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  30666 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  30669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30679 */     GIR_RootConstrainSelectedInstOperands,
     /*  30680 */     // GIR_Coverage, 1790,
     /*  30680 */     GIR_EraseRootFromParent_Done,
     /*  30681 */   // Label 482: @30681
     /*  30681 */   GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(30742), // Rule ID 13703 //
     /*  30686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  30701 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30705 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30714 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30719 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30723 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30725 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  30728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30730 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30736 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  30740 */     GIR_RootConstrainSelectedInstOperands,
     /*  30741 */     // GIR_Coverage, 13703,
     /*  30741 */     GIR_EraseRootFromParent_Done,
     /*  30742 */   // Label 483: @30742
     /*  30742 */   GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(30803), // Rule ID 13737 //
     /*  30747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  30762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30766 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30775 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30784 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30786 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  30789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  30801 */     GIR_RootConstrainSelectedInstOperands,
     /*  30802 */     // GIR_Coverage, 13737,
     /*  30802 */     GIR_EraseRootFromParent_Done,
     /*  30803 */   // Label 484: @30803
     /*  30803 */   GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(30851), // Rule ID 13728 //
     /*  30808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30827 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30832 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30836 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30838 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  30841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  30845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  30849 */     GIR_RootConstrainSelectedInstOperands,
     /*  30850 */     // GIR_Coverage, 13728,
     /*  30850 */     GIR_EraseRootFromParent_Done,
     /*  30851 */   // Label 485: @30851
     /*  30851 */   GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(30899), // Rule ID 13613 //
     /*  30856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  30871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30875 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30884 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30886 */     // (add:{ *:[v4i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  30889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30897 */     GIR_RootConstrainSelectedInstOperands,
     /*  30898 */     // GIR_Coverage, 13613,
     /*  30898 */     GIR_EraseRootFromParent_Done,
     /*  30899 */   // Label 486: @30899
     /*  30899 */   GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(30947), // Rule ID 13697 //
     /*  30904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  30919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30923 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30932 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30934 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  30934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  30937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  30941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  30945 */     GIR_RootConstrainSelectedInstOperands,
     /*  30946 */     // GIR_Coverage, 13697,
     /*  30946 */     GIR_EraseRootFromParent_Done,
     /*  30947 */   // Label 487: @30947
     /*  30947 */   GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(30995), // Rule ID 13625 //
     /*  30952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  30967 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30971 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30980 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30982 */     // (add:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  30985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30987 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30993 */     GIR_RootConstrainSelectedInstOperands,
     /*  30994 */     // GIR_Coverage, 13625,
     /*  30994 */     GIR_EraseRootFromParent_Done,
     /*  30995 */   // Label 488: @30995
     /*  30995 */   GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(31043), // Rule ID 13727 //
     /*  31000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31007 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31011 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  31015 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31019 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31028 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31030 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  31033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  31037 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  31041 */     GIR_RootConstrainSelectedInstOperands,
     /*  31042 */     // GIR_Coverage, 13727,
     /*  31042 */     GIR_EraseRootFromParent_Done,
     /*  31043 */   // Label 489: @31043
     /*  31043 */   GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(31104), // Rule ID 1730 //
     /*  31048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31055 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31059 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31063 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  31067 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31071 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  31075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31087 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  31090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31092 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  31102 */     GIR_RootConstrainSelectedInstOperands,
     /*  31103 */     // GIR_Coverage, 1730,
     /*  31103 */     GIR_EraseRootFromParent_Done,
     /*  31104 */   // Label 490: @31104
     /*  31104 */   GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(31165), // Rule ID 1820 //
     /*  31109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31116 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31120 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31124 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  31128 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31132 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  31136 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31141 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31146 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31148 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  31151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31153 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  31163 */     GIR_RootConstrainSelectedInstOperands,
     /*  31164 */     // GIR_Coverage, 1820,
     /*  31164 */     GIR_EraseRootFromParent_Done,
     /*  31165 */   // Label 491: @31165
     /*  31165 */   GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(31213), // Rule ID 1811 //
     /*  31170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31177 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  31189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31193 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31200 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  31203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31205 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  31207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  31211 */     GIR_RootConstrainSelectedInstOperands,
     /*  31212 */     // GIR_Coverage, 1811,
     /*  31212 */     GIR_EraseRootFromParent_Done,
     /*  31213 */   // Label 492: @31213
     /*  31213 */   GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(31261), // Rule ID 998 //
     /*  31218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  31237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  31241 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31246 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31248 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  31248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  31251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31253 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31259 */     GIR_RootConstrainSelectedInstOperands,
     /*  31260 */     // GIR_Coverage, 998,
     /*  31260 */     GIR_EraseRootFromParent_Done,
     /*  31261 */   // Label 493: @31261
     /*  31261 */   GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(31309), // Rule ID 1724 //
     /*  31266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31273 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  31285 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31289 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31294 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31296 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  31299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31301 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  31303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  31307 */     GIR_RootConstrainSelectedInstOperands,
     /*  31308 */     // GIR_Coverage, 1724,
     /*  31308 */     GIR_EraseRootFromParent_Done,
     /*  31309 */   // Label 494: @31309
     /*  31309 */   GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(31357), // Rule ID 1059 //
     /*  31314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  31333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  31337 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31342 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31344 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  31344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  31347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31349 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31355 */     GIR_RootConstrainSelectedInstOperands,
     /*  31356 */     // GIR_Coverage, 1059,
     /*  31356 */     GIR_EraseRootFromParent_Done,
     /*  31357 */   // Label 495: @31357
     /*  31357 */   GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(31405), // Rule ID 1810 //
     /*  31362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31369 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  31381 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31385 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31390 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31392 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  31395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31397 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  31399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  31403 */     GIR_RootConstrainSelectedInstOperands,
     /*  31404 */     // GIR_Coverage, 1810,
     /*  31404 */     GIR_EraseRootFromParent_Done,
     /*  31405 */   // Label 496: @31405
     /*  31405 */   GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(31432), // Rule ID 1109 //
     /*  31410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31417 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31421 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31425 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  31425 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
     /*  31430 */     GIR_RootConstrainSelectedInstOperands,
     /*  31431 */     // GIR_Coverage, 1109,
     /*  31431 */     GIR_Done,
     /*  31432 */   // Label 497: @31432
     /*  31432 */   GIM_Reject,
     /*  31433 */ // Label 416: @31433
     /*  31433 */ GIM_Reject,
     /*  31434 */ // Label 162: @31434
     /*  31434 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(32283),
     /*  31439 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  31442 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  31445 */   GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(31578), // Rule ID 14258 //
     /*  31450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  31462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  31466 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  31470 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  31474 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  31478 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  31482 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31487 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  31491 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  31495 */     // MIs[1] Operand 2
     /*  31495 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  31506 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  31510 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  31514 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  31518 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  31522 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  31526 */     // MIs[5] Rn
     /*  31526 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  31531 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  31533 */     // (add:{ *:[v8i8] } (extract_subvector:{ *:[v8i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, (undef:{ *:[v16i8] })), 0:{ *:[i64] }), (trunc:{ *:[v8i8] } (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$Rn)))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /*  31533 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  31536 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  31540 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  31545 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  31549 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  31553 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  31555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  31558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31560 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  31567 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31572 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31577 */     // GIR_Coverage, 14258,
     /*  31577 */     GIR_EraseRootFromParent_Done,
     /*  31578 */   // Label 499: @31578
     /*  31578 */   GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(31711), // Rule ID 7012 //
     /*  31583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31587 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31591 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  31595 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  31599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  31603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  31607 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  31611 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31616 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  31620 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  31624 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  31628 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  31632 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_UZP2),
     /*  31636 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  31640 */     // MIs[4] Rn
     /*  31640 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  31645 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  31649 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  31653 */     // MIs[3] Operand 2
     /*  31653 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  31664 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  31666 */     // (add:{ *:[v8i8] } (trunc:{ *:[v8i8] } (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$Rn)), (extract_subvector:{ *:[v8i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, (undef:{ *:[v16i8] })), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /*  31666 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  31669 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  31673 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  31678 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  31682 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  31686 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  31688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  31691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31693 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  31700 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31710 */     // GIR_Coverage, 7012,
     /*  31710 */     GIR_EraseRootFromParent_Done,
     /*  31711 */   // Label 500: @31711
     /*  31711 */   GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(31780), // Rule ID 13642 //
     /*  31716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  31731 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  31734 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  31739 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  31743 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  31747 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31752 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31757 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31761 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31763 */     // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  31763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  31766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31770 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  31774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  31778 */     GIR_RootConstrainSelectedInstOperands,
     /*  31779 */     // GIR_Coverage, 13642,
     /*  31779 */     GIR_EraseRootFromParent_Done,
     /*  31780 */   // Label 501: @31780
     /*  31780 */   GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(31849), // Rule ID 13654 //
     /*  31785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31792 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31796 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  31800 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  31803 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  31808 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  31812 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  31816 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31821 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31826 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31830 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31832 */     // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  31832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
     /*  31835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  31843 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  31847 */     GIR_RootConstrainSelectedInstOperands,
     /*  31848 */     // GIR_Coverage, 13654,
     /*  31848 */     GIR_EraseRootFromParent_Done,
     /*  31849 */   // Label 502: @31849
     /*  31849 */   GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(31916), // Rule ID 13856 //
     /*  31854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31861 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31865 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  31869 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  31873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31878 */     // MIs[1] imm
     /*  31878 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  31882 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  31886 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  31890 */     // MIs[2] Operand 1
     /*  31890 */     // No operand predicates
     /*  31890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31894 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31898 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31900 */     // (add:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  31900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  31903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31907 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31911 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  31914 */     GIR_RootConstrainSelectedInstOperands,
     /*  31915 */     // GIR_Coverage, 13856,
     /*  31915 */     GIR_EraseRootFromParent_Done,
     /*  31916 */   // Label 503: @31916
     /*  31916 */   GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(31983), // Rule ID 13877 //
     /*  31921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  31936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  31940 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31945 */     // MIs[1] imm
     /*  31945 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  31949 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  31953 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  31957 */     // MIs[2] Operand 1
     /*  31957 */     // No operand predicates
     /*  31957 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31961 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31965 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31967 */     // (add:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  31967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  31970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31978 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  31981 */     GIR_RootConstrainSelectedInstOperands,
     /*  31982 */     // GIR_Coverage, 13877,
     /*  31982 */     GIR_EraseRootFromParent_Done,
     /*  31983 */   // Label 504: @31983
     /*  31983 */   GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(32052), // Rule ID 1361 //
     /*  31988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31995 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31999 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32003 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32007 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  32010 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  32015 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32019 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32023 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32028 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32033 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32035 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  32035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  32038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32040 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32042 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  32046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  32050 */     GIR_RootConstrainSelectedInstOperands,
     /*  32051 */     // GIR_Coverage, 1361,
     /*  32051 */     GIR_EraseRootFromParent_Done,
     /*  32052 */   // Label 505: @32052
     /*  32052 */   GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(32121), // Rule ID 1484 //
     /*  32057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32064 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32076 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  32079 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  32084 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32088 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32092 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32097 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32102 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32104 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  32104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
     /*  32107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32109 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  32115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  32119 */     GIR_RootConstrainSelectedInstOperands,
     /*  32120 */     // GIR_Coverage, 1484,
     /*  32120 */     GIR_EraseRootFromParent_Done,
     /*  32121 */   // Label 506: @32121
     /*  32121 */   GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(32188), // Rule ID 2234 //
     /*  32126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32133 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32137 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32141 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  32145 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32149 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32154 */     // MIs[1] imm
     /*  32154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  32158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  32162 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  32166 */     // MIs[2] Operand 1
     /*  32166 */     // No operand predicates
     /*  32166 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  32170 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32172 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  32172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  32175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32177 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32183 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  32186 */     GIR_RootConstrainSelectedInstOperands,
     /*  32187 */     // GIR_Coverage, 2234,
     /*  32187 */     GIR_EraseRootFromParent_Done,
     /*  32188 */   // Label 507: @32188
     /*  32188 */   GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(32255), // Rule ID 2293 //
     /*  32193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  32212 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32216 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32221 */     // MIs[1] imm
     /*  32221 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  32225 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  32229 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  32233 */     // MIs[2] Operand 1
     /*  32233 */     // No operand predicates
     /*  32233 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  32237 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32239 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  32239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  32242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32244 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32250 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  32253 */     GIR_RootConstrainSelectedInstOperands,
     /*  32254 */     // GIR_Coverage, 2293,
     /*  32254 */     GIR_EraseRootFromParent_Done,
     /*  32255 */   // Label 508: @32255
     /*  32255 */   GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(32282), // Rule ID 1104 //
     /*  32260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32267 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32275 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  32275 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i8),
     /*  32280 */     GIR_RootConstrainSelectedInstOperands,
     /*  32281 */     // GIR_Coverage, 1104,
     /*  32281 */     GIR_Done,
     /*  32282 */   // Label 509: @32282
     /*  32282 */   GIM_Reject,
     /*  32283 */ // Label 498: @32283
     /*  32283 */ GIM_Reject,
     /*  32284 */ // Label 163: @32284
     /*  32284 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(35861),
     /*  32289 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  32292 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  32295 */   GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(32382), // Rule ID 13686 //
     /*  32300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32307 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32319 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32323 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32327 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  32330 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  32335 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32339 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32347 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32349 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32356 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32363 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
     /*  32366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32380 */     GIR_RootConstrainSelectedInstOperands,
     /*  32381 */     // GIR_Coverage, 13686,
     /*  32381 */     GIR_EraseRootFromParent_Done,
     /*  32382 */   // Label 511: @32382
     /*  32382 */   GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(32469), // Rule ID 13714 //
     /*  32387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32406 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32410 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32414 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  32417 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  32422 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32426 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32434 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32436 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32443 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32450 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
     /*  32453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32467 */     GIR_RootConstrainSelectedInstOperands,
     /*  32468 */     // GIR_Coverage, 13714,
     /*  32468 */     GIR_EraseRootFromParent_Done,
     /*  32469 */   // Label 512: @32469
     /*  32469 */   GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(32556), // Rule ID 1695 //
     /*  32474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32481 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32497 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32501 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32505 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  32508 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  32513 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32517 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32521 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32523 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32530 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32537 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))))  =>  (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
     /*  32540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32542 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32554 */     GIR_RootConstrainSelectedInstOperands,
     /*  32555 */     // GIR_Coverage, 1695,
     /*  32555 */     GIR_EraseRootFromParent_Done,
     /*  32556 */   // Label 513: @32556
     /*  32556 */   GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(32643), // Rule ID 1773 //
     /*  32561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32568 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32580 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  32592 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  32595 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  32600 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  32604 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  32608 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32610 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32617 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32624 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))))  =>  (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
     /*  32627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32629 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32641 */     GIR_RootConstrainSelectedInstOperands,
     /*  32642 */     // GIR_Coverage, 1773,
     /*  32642 */     GIR_EraseRootFromParent_Done,
     /*  32643 */   // Label 514: @32643
     /*  32643 */   GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(32712), // Rule ID 1789 //
     /*  32648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32663 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32667 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32671 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32675 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32679 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32681 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32688 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32695 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  32698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32710 */     GIR_RootConstrainSelectedInstOperands,
     /*  32711 */     // GIR_Coverage, 1789,
     /*  32711 */     GIR_EraseRootFromParent_Done,
     /*  32712 */   // Label 515: @32712
     /*  32712 */   GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(32781), // Rule ID 1788 //
     /*  32717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32744 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32748 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32750 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32757 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32764 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  32767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32779 */     GIR_RootConstrainSelectedInstOperands,
     /*  32780 */     // GIR_Coverage, 1788,
     /*  32780 */     GIR_EraseRootFromParent_Done,
     /*  32781 */   // Label 516: @32781
     /*  32781 */   GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(32850), // Rule ID 1717 //
     /*  32786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  32801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32805 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32809 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  32813 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32817 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32819 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32826 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32833 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv16i8_v8i16),
     /*  32836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32848 */     GIR_RootConstrainSelectedInstOperands,
     /*  32849 */     // GIR_Coverage, 1717,
     /*  32849 */     GIR_EraseRootFromParent_Done,
     /*  32850 */   // Label 517: @32850
     /*  32850 */   GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(32919), // Rule ID 1787 //
     /*  32855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32874 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32878 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32882 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32886 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32888 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32895 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32902 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  32905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32917 */     GIR_RootConstrainSelectedInstOperands,
     /*  32918 */     // GIR_Coverage, 1787,
     /*  32918 */     GIR_EraseRootFromParent_Done,
     /*  32919 */   // Label 518: @32919
     /*  32919 */   GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(32988), // Rule ID 1786 //
     /*  32924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32931 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32935 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32939 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32943 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32947 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32951 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  32955 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32957 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32964 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  32971 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  32971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  32974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  32981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  32986 */     GIR_RootConstrainSelectedInstOperands,
     /*  32987 */     // GIR_Coverage, 1786,
     /*  32987 */     GIR_EraseRootFromParent_Done,
     /*  32988 */   // Label 519: @32988
     /*  32988 */   GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(33055), // Rule ID 13702 //
     /*  32993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  33008 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33012 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33016 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33020 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33022 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33029 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33036 */     // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
     /*  33039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33041 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  33048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  33053 */     GIR_RootConstrainSelectedInstOperands,
     /*  33054 */     // GIR_Coverage, 13702,
     /*  33054 */     GIR_EraseRootFromParent_Done,
     /*  33055 */   // Label 520: @33055
     /*  33055 */   GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(33122), // Rule ID 13736 //
     /*  33060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33067 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33071 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  33075 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33079 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33087 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33089 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33096 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33103 */     // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
     /*  33106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  33115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  33120 */     GIR_RootConstrainSelectedInstOperands,
     /*  33121 */     // GIR_Coverage, 13736,
     /*  33121 */     GIR_EraseRootFromParent_Done,
     /*  33122 */   // Label 521: @33122
     /*  33122 */   GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(33189), // Rule ID 1729 //
     /*  33127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33134 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  33146 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33150 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33154 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33156 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33163 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33170 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
     /*  33173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33175 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  33182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  33187 */     GIR_RootConstrainSelectedInstOperands,
     /*  33188 */     // GIR_Coverage, 1729,
     /*  33188 */     GIR_EraseRootFromParent_Done,
     /*  33189 */   // Label 522: @33189
     /*  33189 */   GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(33256), // Rule ID 1819 //
     /*  33194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33201 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33205 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33209 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  33213 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33217 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33221 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33223 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33230 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33237 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
     /*  33240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  33249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  33254 */     GIR_RootConstrainSelectedInstOperands,
     /*  33255 */     // GIR_Coverage, 1819,
     /*  33255 */     GIR_EraseRootFromParent_Done,
     /*  33256 */   // Label 523: @33256
     /*  33256 */   GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(33337), // Rule ID 13684 //
     /*  33261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33288 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  33291 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  33296 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33300 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  33304 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33309 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33318 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  33320 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  33320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  33323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  33331 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  33335 */     GIR_RootConstrainSelectedInstOperands,
     /*  33336 */     // GIR_Coverage, 13684,
     /*  33336 */     GIR_EraseRootFromParent_Done,
     /*  33337 */   // Label 524: @33337
     /*  33337 */   GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(33418), // Rule ID 13712 //
     /*  33342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33349 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33353 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33357 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33369 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  33372 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  33377 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33381 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  33385 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33390 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  33401 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  33401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
     /*  33404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  33412 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  33416 */     GIR_RootConstrainSelectedInstOperands,
     /*  33417 */     // GIR_Coverage, 13712,
     /*  33417 */     GIR_EraseRootFromParent_Done,
     /*  33418 */   // Label 525: @33418
     /*  33418 */   GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(33499), // Rule ID 1693 //
     /*  33423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33430 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33446 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33450 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33454 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  33457 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  33462 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33466 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  33470 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33475 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33480 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  33482 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  33482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  33485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33487 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33489 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  33493 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  33497 */     GIR_RootConstrainSelectedInstOperands,
     /*  33498 */     // GIR_Coverage, 1693,
     /*  33498 */     GIR_EraseRootFromParent_Done,
     /*  33499 */   // Label 526: @33499
     /*  33499 */   GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(33580), // Rule ID 1771 //
     /*  33504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33511 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33519 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33523 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33527 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33531 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33535 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  33538 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  33543 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33547 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  33551 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33556 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33561 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  33563 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  33563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
     /*  33566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33568 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33570 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
     /*  33574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /*  33578 */     GIR_RootConstrainSelectedInstOperands,
     /*  33579 */     // GIR_Coverage, 1771,
     /*  33579 */     GIR_EraseRootFromParent_Done,
     /*  33580 */   // Label 527: @33580
     /*  33580 */   GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(33631), // Rule ID 13726 //
     /*  33585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  33600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33608 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33610 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33617 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  33620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  33624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33629 */     GIR_RootConstrainSelectedInstOperands,
     /*  33630 */     // GIR_Coverage, 13726,
     /*  33630 */     GIR_EraseRootFromParent_Done,
     /*  33631 */   // Label 528: @33631
     /*  33631 */   GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(33682), // Rule ID 13696 //
     /*  33636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33643 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33647 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  33651 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33659 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33661 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33668 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
     /*  33671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  33675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33680 */     GIR_RootConstrainSelectedInstOperands,
     /*  33681 */     // GIR_Coverage, 13696,
     /*  33681 */     GIR_EraseRootFromParent_Done,
     /*  33682 */   // Label 529: @33682
     /*  33682 */   GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(33733), // Rule ID 13725 //
     /*  33687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33710 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33712 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33719 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  33722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  33726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33731 */     GIR_RootConstrainSelectedInstOperands,
     /*  33732 */     // GIR_Coverage, 13725,
     /*  33732 */     GIR_EraseRootFromParent_Done,
     /*  33733 */   // Label 530: @33733
     /*  33733 */   GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(33784), // Rule ID 1809 //
     /*  33738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  33757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33761 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33763 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33770 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  33773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33775 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33782 */     GIR_RootConstrainSelectedInstOperands,
     /*  33783 */     // GIR_Coverage, 1809,
     /*  33783 */     GIR_EraseRootFromParent_Done,
     /*  33784 */   // Label 531: @33784
     /*  33784 */   GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(33835), // Rule ID 1723 //
     /*  33789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33796 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  33808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33812 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33814 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33821 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
     /*  33824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33826 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33833 */     GIR_RootConstrainSelectedInstOperands,
     /*  33834 */     // GIR_Coverage, 1723,
     /*  33834 */     GIR_EraseRootFromParent_Done,
     /*  33835 */   // Label 532: @33835
     /*  33835 */   GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(33886), // Rule ID 1808 //
     /*  33840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33847 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33851 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33855 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33859 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33863 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33865 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  33872 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  33872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  33875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33877 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  33884 */     GIR_RootConstrainSelectedInstOperands,
     /*  33885 */     // GIR_Coverage, 1808,
     /*  33885 */     GIR_EraseRootFromParent_Done,
     /*  33886 */   // Label 533: @33886
     /*  33886 */   GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(33955), // Rule ID 13648 //
     /*  33891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33906 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  33909 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  33914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  33918 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  33922 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33927 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33932 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33936 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33938 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 669:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  33938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  33941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  33949 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  33953 */     GIR_RootConstrainSelectedInstOperands,
     /*  33954 */     // GIR_Coverage, 13648,
     /*  33954 */     GIR_EraseRootFromParent_Done,
     /*  33955 */   // Label 534: @33955
     /*  33955 */   GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(34024), // Rule ID 13660 //
     /*  33960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33967 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33971 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  33975 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  33978 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  33983 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  33987 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  33991 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33996 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34001 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34005 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34007 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 734:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  34007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
     /*  34010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34012 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  34022 */     GIR_RootConstrainSelectedInstOperands,
     /*  34023 */     // GIR_Coverage, 13660,
     /*  34023 */     GIR_EraseRootFromParent_Done,
     /*  34024 */   // Label 535: @34024
     /*  34024 */   GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(34080), // Rule ID 13610 //
     /*  34029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34044 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  34047 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  34052 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  34056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34065 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34067 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 670:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  34067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  34070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34074 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34078 */     GIR_RootConstrainSelectedInstOperands,
     /*  34079 */     // GIR_Coverage, 13610,
     /*  34079 */     GIR_EraseRootFromParent_Done,
     /*  34080 */   // Label 536: @34080
     /*  34080 */   GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(34136), // Rule ID 13622 //
     /*  34085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34092 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34096 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34100 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  34103 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  34108 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  34112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34117 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34121 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34123 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 735:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  34123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  34126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34134 */     GIR_RootConstrainSelectedInstOperands,
     /*  34135 */     // GIR_Coverage, 13622,
     /*  34135 */     GIR_EraseRootFromParent_Done,
     /*  34136 */   // Label 537: @34136
     /*  34136 */   GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(34203), // Rule ID 13862 //
     /*  34141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  34156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34160 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34165 */     // MIs[1] imm
     /*  34165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  34169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  34173 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  34177 */     // MIs[2] Operand 1
     /*  34177 */     // No operand predicates
     /*  34177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34181 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34185 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34187 */     // (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  34187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  34190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34194 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34198 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  34201 */     GIR_RootConstrainSelectedInstOperands,
     /*  34202 */     // GIR_Coverage, 13862,
     /*  34202 */     GIR_EraseRootFromParent_Done,
     /*  34203 */   // Label 538: @34203
     /*  34203 */   GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(34270), // Rule ID 13883 //
     /*  34208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34215 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34219 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  34223 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34227 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34232 */     // MIs[1] imm
     /*  34232 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  34236 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  34240 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  34244 */     // MIs[2] Operand 1
     /*  34244 */     // No operand predicates
     /*  34244 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34248 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34252 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34254 */     // (add:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  34254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  34257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34265 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  34268 */     GIR_RootConstrainSelectedInstOperands,
     /*  34269 */     // GIR_Coverage, 13883,
     /*  34269 */     GIR_EraseRootFromParent_Done,
     /*  34270 */   // Label 539: @34270
     /*  34270 */   GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(34339), // Rule ID 1367 //
     /*  34275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34294 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  34297 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  34302 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  34306 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  34310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34315 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34320 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34322 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 669:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  34322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  34325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34327 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34333 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  34337 */     GIR_RootConstrainSelectedInstOperands,
     /*  34338 */     // GIR_Coverage, 1367,
     /*  34338 */     GIR_EraseRootFromParent_Done,
     /*  34339 */   // Label 540: @34339
     /*  34339 */   GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(34408), // Rule ID 1490 //
     /*  34344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34351 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34363 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  34366 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  34371 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  34375 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  34379 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34384 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34389 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34391 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 734:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  34391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
     /*  34394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34396 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  34406 */     GIR_RootConstrainSelectedInstOperands,
     /*  34407 */     // GIR_Coverage, 1490,
     /*  34407 */     GIR_EraseRootFromParent_Done,
     /*  34408 */   // Label 541: @34408
     /*  34408 */   GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(34464), // Rule ID 995 //
     /*  34413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34428 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34432 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  34435 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  34440 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  34444 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34449 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34451 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 670:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  34451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  34454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34456 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34458 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34462 */     GIR_RootConstrainSelectedInstOperands,
     /*  34463 */     // GIR_Coverage, 995,
     /*  34463 */     GIR_EraseRootFromParent_Done,
     /*  34464 */   // Label 542: @34464
     /*  34464 */   GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(34520), // Rule ID 1056 //
     /*  34469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34476 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34480 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34484 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  34488 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  34491 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  34496 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  34500 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34505 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34507 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 735:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  34507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  34510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34512 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34514 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  34518 */     GIR_RootConstrainSelectedInstOperands,
     /*  34519 */     // GIR_Coverage, 1056,
     /*  34519 */     GIR_EraseRootFromParent_Done,
     /*  34520 */   // Label 543: @34520
     /*  34520 */   GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(34587), // Rule ID 2240 //
     /*  34525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34532 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34536 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34540 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  34544 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34548 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34553 */     // MIs[1] imm
     /*  34553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  34557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  34561 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  34565 */     // MIs[2] Operand 1
     /*  34565 */     // No operand predicates
     /*  34565 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34569 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34571 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  34571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  34574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34576 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34578 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34582 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  34585 */     GIR_RootConstrainSelectedInstOperands,
     /*  34586 */     // GIR_Coverage, 2240,
     /*  34586 */     GIR_EraseRootFromParent_Done,
     /*  34587 */   // Label 544: @34587
     /*  34587 */   GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(34654), // Rule ID 2299 //
     /*  34592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34599 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  34611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34615 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34620 */     // MIs[1] imm
     /*  34620 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  34624 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  34628 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  34632 */     // MIs[2] Operand 1
     /*  34632 */     // No operand predicates
     /*  34632 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34636 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34638 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  34638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  34641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34643 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34645 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34649 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  34652 */     GIR_RootConstrainSelectedInstOperands,
     /*  34653 */     // GIR_Coverage, 2299,
     /*  34653 */     GIR_EraseRootFromParent_Done,
     /*  34654 */   // Label 545: @34654
     /*  34654 */   GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(34724), // Rule ID 7008 //
     /*  34659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  34671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34675 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  34679 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34689 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34693 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  34697 */     // MIs[2] Rn
     /*  34697 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  34702 */     // MIs[2] Rm
     /*  34702 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  34707 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34709 */     // (add:{ *:[v8i16] } (AArch64uzp1:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm), (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm))  =>  (ADDPv8i16:{ *:[v8i16] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rm)
     /*  34709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  34712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34722 */     GIR_RootConstrainSelectedInstOperands,
     /*  34723 */     // GIR_Coverage, 7008,
     /*  34723 */     GIR_EraseRootFromParent_Done,
     /*  34724 */   // Label 546: @34724
     /*  34724 */   GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(34794), // Rule ID 14254 //
     /*  34729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  34741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34745 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  34749 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34754 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34759 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34763 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  34767 */     // MIs[2] Rn
     /*  34767 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  34772 */     // MIs[2] Rm
     /*  34772 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  34777 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34779 */     // (add:{ *:[v8i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm), (AArch64uzp1:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm))  =>  (ADDPv8i16:{ *:[v8i16] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rm)
     /*  34779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  34782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34792 */     GIR_RootConstrainSelectedInstOperands,
     /*  34793 */     // GIR_Coverage, 14254,
     /*  34793 */     GIR_EraseRootFromParent_Done,
     /*  34794 */   // Label 547: @34794
     /*  34794 */   GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(34857), // Rule ID 1785 //
     /*  34799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34818 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34823 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34827 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34831 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34835 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34840 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34842 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  34845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34847 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  34855 */     GIR_RootConstrainSelectedInstOperands,
     /*  34856 */     // GIR_Coverage, 1785,
     /*  34856 */     GIR_EraseRootFromParent_Done,
     /*  34857 */   // Label 548: @34857
     /*  34857 */   GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(34920), // Rule ID 1784 //
     /*  34862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34881 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34886 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34890 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  34894 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34898 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34903 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34905 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  34908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34910 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  34918 */     GIR_RootConstrainSelectedInstOperands,
     /*  34919 */     // GIR_Coverage, 1784,
     /*  34919 */     GIR_EraseRootFromParent_Done,
     /*  34920 */   // Label 549: @34920
     /*  34920 */   GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(34983), // Rule ID 1716 //
     /*  34925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  34940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34944 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  34957 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34961 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34966 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34968 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i8_v8i16),
     /*  34971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  34981 */     GIR_RootConstrainSelectedInstOperands,
     /*  34982 */     // GIR_Coverage, 1716,
     /*  34982 */     GIR_EraseRootFromParent_Done,
     /*  34983 */   // Label 550: @34983
     /*  34983 */   GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(35046), // Rule ID 1783 //
     /*  34988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35003 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35007 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  35020 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35024 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35029 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35031 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  35034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  35044 */     GIR_RootConstrainSelectedInstOperands,
     /*  35045 */     // GIR_Coverage, 1783,
     /*  35045 */     GIR_EraseRootFromParent_Done,
     /*  35046 */   // Label 551: @35046
     /*  35046 */   GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(35109), // Rule ID 1782 //
     /*  35051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35066 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35070 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35075 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35079 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35083 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35087 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35092 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35094 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  35097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35099 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35103 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  35107 */     GIR_RootConstrainSelectedInstOperands,
     /*  35108 */     // GIR_Coverage, 1782,
     /*  35108 */     GIR_EraseRootFromParent_Done,
     /*  35109 */   // Label 552: @35109
     /*  35109 */   GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(35170), // Rule ID 13701 //
     /*  35114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35121 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35125 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  35129 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35133 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35137 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35142 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35151 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35153 */     // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  35156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  35168 */     GIR_RootConstrainSelectedInstOperands,
     /*  35169 */     // GIR_Coverage, 13701,
     /*  35169 */     GIR_EraseRootFromParent_Done,
     /*  35170 */   // Label 553: @35170
     /*  35170 */   GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(35231), // Rule ID 13735 //
     /*  35175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  35190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35194 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35203 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35212 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35214 */     // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  35217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35221 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35225 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  35229 */     GIR_RootConstrainSelectedInstOperands,
     /*  35230 */     // GIR_Coverage, 13735,
     /*  35230 */     GIR_EraseRootFromParent_Done,
     /*  35231 */   // Label 554: @35231
     /*  35231 */   GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(35279), // Rule ID 13724 //
     /*  35236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35243 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35247 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  35251 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35255 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35264 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35266 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  35269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35271 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35273 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35277 */     GIR_RootConstrainSelectedInstOperands,
     /*  35278 */     // GIR_Coverage, 13724,
     /*  35278 */     GIR_EraseRootFromParent_Done,
     /*  35279 */   // Label 555: @35279
     /*  35279 */   GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(35327), // Rule ID 13609 //
     /*  35284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35295 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  35299 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  35303 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35312 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35314 */     // (add:{ *:[v8i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  35314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  35317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35325 */     GIR_RootConstrainSelectedInstOperands,
     /*  35326 */     // GIR_Coverage, 13609,
     /*  35326 */     GIR_EraseRootFromParent_Done,
     /*  35327 */   // Label 556: @35327
     /*  35327 */   GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(35375), // Rule ID 13695 //
     /*  35332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  35347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35351 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35356 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35360 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35362 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  35365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35373 */     GIR_RootConstrainSelectedInstOperands,
     /*  35374 */     // GIR_Coverage, 13695,
     /*  35374 */     GIR_EraseRootFromParent_Done,
     /*  35375 */   // Label 557: @35375
     /*  35375 */   GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(35423), // Rule ID 13621 //
     /*  35380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  35395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  35399 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35404 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35408 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35410 */     // (add:{ *:[v8i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  35410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  35413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35417 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35421 */     GIR_RootConstrainSelectedInstOperands,
     /*  35422 */     // GIR_Coverage, 13621,
     /*  35422 */     GIR_EraseRootFromParent_Done,
     /*  35423 */   // Label 558: @35423
     /*  35423 */   GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(35471), // Rule ID 13723 //
     /*  35428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35439 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35443 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35447 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35456 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35458 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  35461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35469 */     GIR_RootConstrainSelectedInstOperands,
     /*  35470 */     // GIR_Coverage, 13723,
     /*  35470 */     GIR_EraseRootFromParent_Done,
     /*  35471 */   // Label 559: @35471
     /*  35471 */   GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(35532), // Rule ID 1728 //
     /*  35476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35483 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  35495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35503 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35508 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35513 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35515 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  35518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35520 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  35530 */     GIR_RootConstrainSelectedInstOperands,
     /*  35531 */     // GIR_Coverage, 1728,
     /*  35531 */     GIR_EraseRootFromParent_Done,
     /*  35532 */   // Label 560: @35532
     /*  35532 */   GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(35593), // Rule ID 1818 //
     /*  35537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35544 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35548 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35552 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  35556 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35560 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35564 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35569 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35576 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  35579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35581 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  35591 */     GIR_RootConstrainSelectedInstOperands,
     /*  35592 */     // GIR_Coverage, 1818,
     /*  35592 */     GIR_EraseRootFromParent_Done,
     /*  35593 */   // Label 561: @35593
     /*  35593 */   GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(35641), // Rule ID 1807 //
     /*  35598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35605 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  35617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35621 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35626 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35628 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  35631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35633 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  35635 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35639 */     GIR_RootConstrainSelectedInstOperands,
     /*  35640 */     // GIR_Coverage, 1807,
     /*  35640 */     GIR_EraseRootFromParent_Done,
     /*  35641 */   // Label 562: @35641
     /*  35641 */   GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(35689), // Rule ID 994 //
     /*  35646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35653 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  35665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  35669 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35674 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35676 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  35676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  35679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35681 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35687 */     GIR_RootConstrainSelectedInstOperands,
     /*  35688 */     // GIR_Coverage, 994,
     /*  35688 */     GIR_EraseRootFromParent_Done,
     /*  35689 */   // Label 563: @35689
     /*  35689 */   GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(35737), // Rule ID 1722 //
     /*  35694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35701 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  35713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35722 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35724 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  35727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35729 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  35731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35735 */     GIR_RootConstrainSelectedInstOperands,
     /*  35736 */     // GIR_Coverage, 1722,
     /*  35736 */     GIR_EraseRootFromParent_Done,
     /*  35737 */   // Label 564: @35737
     /*  35737 */   GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(35785), // Rule ID 1055 //
     /*  35742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35753 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35757 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  35761 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  35765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35770 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35772 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  35772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  35775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35777 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  35783 */     GIR_RootConstrainSelectedInstOperands,
     /*  35784 */     // GIR_Coverage, 1055,
     /*  35784 */     GIR_EraseRootFromParent_Done,
     /*  35785 */   // Label 565: @35785
     /*  35785 */   GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(35833), // Rule ID 1806 //
     /*  35790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35797 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35809 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35813 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  35818 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35820 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  35820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  35823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35825 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  35827 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  35831 */     GIR_RootConstrainSelectedInstOperands,
     /*  35832 */     // GIR_Coverage, 1806,
     /*  35832 */     GIR_EraseRootFromParent_Done,
     /*  35833 */   // Label 566: @35833
     /*  35833 */   GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(35860), // Rule ID 1107 //
     /*  35838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35849 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35853 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  35853 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i16),
     /*  35858 */     GIR_RootConstrainSelectedInstOperands,
     /*  35859 */     // GIR_Coverage, 1107,
     /*  35859 */     GIR_Done,
     /*  35860 */   // Label 567: @35860
     /*  35860 */   GIM_Reject,
     /*  35861 */ // Label 510: @35861
     /*  35861 */ GIM_Reject,
     /*  35862 */ // Label 164: @35862
     /*  35862 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(36585),
     /*  35867 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  35870 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  35873 */   GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(35942), // Rule ID 13644 //
     /*  35878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35885 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35889 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  35893 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  35896 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  35901 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  35905 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  35909 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35914 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35919 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35923 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35925 */     // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 669:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  35928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35930 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  35936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  35940 */     GIR_RootConstrainSelectedInstOperands,
     /*  35941 */     // GIR_Coverage, 13644,
     /*  35941 */     GIR_EraseRootFromParent_Done,
     /*  35942 */   // Label 569: @35942
     /*  35942 */   GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(36011), // Rule ID 13656 //
     /*  35947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35954 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35958 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  35962 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  35965 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  35970 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  35974 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  35978 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35983 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35992 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35994 */     // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 734:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
     /*  35997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36005 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  36009 */     GIR_RootConstrainSelectedInstOperands,
     /*  36010 */     // GIR_Coverage, 13656,
     /*  36010 */     GIR_EraseRootFromParent_Done,
     /*  36011 */   // Label 570: @36011
     /*  36011 */   GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(36078), // Rule ID 13858 //
     /*  36016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  36031 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36035 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36040 */     // MIs[1] imm
     /*  36040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  36048 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  36052 */     // MIs[2] Operand 1
     /*  36052 */     // No operand predicates
     /*  36052 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36056 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36060 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36062 */     // (add:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  36062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  36065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36073 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  36076 */     GIR_RootConstrainSelectedInstOperands,
     /*  36077 */     // GIR_Coverage, 13858,
     /*  36077 */     GIR_EraseRootFromParent_Done,
     /*  36078 */   // Label 571: @36078
     /*  36078 */   GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(36145), // Rule ID 13879 //
     /*  36083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  36098 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36102 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36107 */     // MIs[1] imm
     /*  36107 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36111 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  36115 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  36119 */     // MIs[2] Operand 1
     /*  36119 */     // No operand predicates
     /*  36119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36123 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36127 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36129 */     // (add:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  36129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  36132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36140 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  36143 */     GIR_RootConstrainSelectedInstOperands,
     /*  36144 */     // GIR_Coverage, 13879,
     /*  36144 */     GIR_EraseRootFromParent_Done,
     /*  36145 */   // Label 572: @36145
     /*  36145 */   GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(36214), // Rule ID 1363 //
     /*  36150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36157 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36169 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  36172 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /*  36177 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36181 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  36185 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36190 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36195 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36197 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 669:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  36200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36202 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36204 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36208 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  36212 */     GIR_RootConstrainSelectedInstOperands,
     /*  36213 */     // GIR_Coverage, 1363,
     /*  36213 */     GIR_EraseRootFromParent_Done,
     /*  36214 */   // Label 573: @36214
     /*  36214 */   GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(36283), // Rule ID 1486 //
     /*  36219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36226 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36230 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36234 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36238 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  36241 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /*  36246 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36250 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  36254 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36259 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36264 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36266 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 734:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
     /*  36269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36271 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36273 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36277 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /*  36281 */     GIR_RootConstrainSelectedInstOperands,
     /*  36282 */     // GIR_Coverage, 1486,
     /*  36282 */     GIR_EraseRootFromParent_Done,
     /*  36283 */   // Label 574: @36283
     /*  36283 */   GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(36350), // Rule ID 2236 //
     /*  36288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36295 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36299 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36303 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  36307 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36311 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36316 */     // MIs[1] imm
     /*  36316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36320 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  36324 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  36328 */     // MIs[2] Operand 1
     /*  36328 */     // No operand predicates
     /*  36328 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36334 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  36334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  36337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36339 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36341 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36345 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  36348 */     GIR_RootConstrainSelectedInstOperands,
     /*  36349 */     // GIR_Coverage, 2236,
     /*  36349 */     GIR_EraseRootFromParent_Done,
     /*  36350 */   // Label 575: @36350
     /*  36350 */   GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(36417), // Rule ID 2295 //
     /*  36355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36362 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36366 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36370 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  36374 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36383 */     // MIs[1] imm
     /*  36383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36387 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  36391 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  36395 */     // MIs[2] Operand 1
     /*  36395 */     // No operand predicates
     /*  36395 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36401 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  36401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  36404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36406 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36412 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  36415 */     GIR_RootConstrainSelectedInstOperands,
     /*  36416 */     // GIR_Coverage, 2295,
     /*  36416 */     GIR_EraseRootFromParent_Done,
     /*  36417 */   // Label 576: @36417
     /*  36417 */   GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(36487), // Rule ID 7009 //
     /*  36422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  36434 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36438 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36447 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36452 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  36456 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  36460 */     // MIs[2] Rn
     /*  36460 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  36465 */     // MIs[2] Rm
     /*  36465 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  36470 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36472 */     // (add:{ *:[v16i8] } (AArch64uzp1:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm), (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm))  =>  (ADDPv16i8:{ *:[v16i8] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm)
     /*  36472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  36475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  36485 */     GIR_RootConstrainSelectedInstOperands,
     /*  36486 */     // GIR_Coverage, 7009,
     /*  36486 */     GIR_EraseRootFromParent_Done,
     /*  36487 */   // Label 577: @36487
     /*  36487 */   GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(36557), // Rule ID 14255 //
     /*  36492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36500 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  36504 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  36508 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36512 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  36526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  36530 */     // MIs[2] Rn
     /*  36530 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  36535 */     // MIs[2] Rm
     /*  36535 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  36540 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36542 */     // (add:{ *:[v16i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm), (AArch64uzp1:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm))  =>  (ADDPv16i8:{ *:[v16i8] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm)
     /*  36542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  36545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36547 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36551 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  36555 */     GIR_RootConstrainSelectedInstOperands,
     /*  36556 */     // GIR_Coverage, 14255,
     /*  36556 */     GIR_EraseRootFromParent_Done,
     /*  36557 */   // Label 578: @36557
     /*  36557 */   GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(36584), // Rule ID 1105 //
     /*  36562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36569 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36573 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36577 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36577 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv16i8),
     /*  36582 */     GIR_RootConstrainSelectedInstOperands,
     /*  36583 */     // GIR_Coverage, 1105,
     /*  36583 */     GIR_Done,
     /*  36584 */   // Label 579: @36584
     /*  36584 */   GIM_Reject,
     /*  36585 */ // Label 568: @36585
     /*  36585 */ GIM_Reject,
     /*  36586 */ // Label 165: @36586
     /*  36586 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(36957),
     /*  36591 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36594 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  36597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  36601 */   GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(36663), // Rule ID 15442 //
     /*  36606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  36617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36621 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  36625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  36629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  36633 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  36637 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  36648 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36650 */     // (add:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  36653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  36657 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  36661 */     GIR_RootConstrainSelectedInstOperands,
     /*  36662 */     // GIR_Coverage, 15442,
     /*  36662 */     GIR_EraseRootFromParent_Done,
     /*  36663 */   // Label 581: @36663
     /*  36663 */   GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(36725), // Rule ID 15441 //
     /*  36668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36671 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36675 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  36679 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36683 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  36687 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36691 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  36695 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  36699 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  36710 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36712 */     // (add:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  36715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  36719 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  36723 */     GIR_RootConstrainSelectedInstOperands,
     /*  36724 */     // GIR_Coverage, 15441,
     /*  36724 */     GIR_EraseRootFromParent_Done,
     /*  36725 */   // Label 582: @36725
     /*  36725 */   GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(36787), // Rule ID 15440 //
     /*  36730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  36741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36745 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  36749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  36753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  36757 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  36761 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  36772 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36774 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  36777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36779 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  36781 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  36785 */     GIR_RootConstrainSelectedInstOperands,
     /*  36786 */     // GIR_Coverage, 15440,
     /*  36786 */     GIR_EraseRootFromParent_Done,
     /*  36787 */   // Label 583: @36787
     /*  36787 */   GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(36849), // Rule ID 9015 //
     /*  36792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  36803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36807 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  36811 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  36815 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  36819 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  36823 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  36834 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36836 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] })))  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  36839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36841 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  36843 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  36847 */     GIR_RootConstrainSelectedInstOperands,
     /*  36848 */     // GIR_Coverage, 9015,
     /*  36848 */     GIR_EraseRootFromParent_Done,
     /*  36849 */   // Label 584: @36849
     /*  36849 */   GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(36895), // Rule ID 15443 //
     /*  36854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  36865 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36869 */     // MIs[1] Operand 2
     /*  36869 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  36880 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36882 */     // (add:{ *:[nxv2i64] } (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i32:{ *:[Other] }), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_SXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_SXTW_ZZZ_D_0),
     /*  36885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  36889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  36893 */     GIR_RootConstrainSelectedInstOperands,
     /*  36894 */     // GIR_Coverage, 15443,
     /*  36894 */     GIR_EraseRootFromParent_Done,
     /*  36895 */   // Label 585: @36895
     /*  36895 */   GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(36941), // Rule ID 9016 //
     /*  36900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  36903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  36911 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  36915 */     // MIs[1] Operand 2
     /*  36915 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  36926 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36928 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i32:{ *:[Other] }))  =>  (ADR_SXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_SXTW_ZZZ_D_0),
     /*  36931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  36933 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  36935 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  36939 */     GIR_RootConstrainSelectedInstOperands,
     /*  36940 */     // GIR_Coverage, 9016,
     /*  36940 */     GIR_EraseRootFromParent_Done,
     /*  36941 */   // Label 586: @36941
     /*  36941 */   GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(36956), // Rule ID 2780 //
     /*  36946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  36949 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  36949 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_D),
     /*  36954 */     GIR_RootConstrainSelectedInstOperands,
     /*  36955 */     // GIR_Coverage, 2780,
     /*  36955 */     GIR_Done,
     /*  36956 */   // Label 587: @36956
     /*  36956 */   GIM_Reject,
     /*  36957 */ // Label 580: @36957
     /*  36957 */ GIM_Reject,
     /*  36958 */ // Label 166: @36958
     /*  36958 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(36983), // Rule ID 2779 //
     /*  36963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  36966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  36969 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  36972 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  36976 */   // (add:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  36976 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_S),
     /*  36981 */   GIR_RootConstrainSelectedInstOperands,
     /*  36982 */   // GIR_Coverage, 2779,
     /*  36982 */   GIR_Done,
     /*  36983 */ // Label 588: @36983
     /*  36983 */ GIM_Reject,
     /*  36984 */ // Label 167: @36984
     /*  36984 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(37009), // Rule ID 2778 //
     /*  36989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  36992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  36995 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  36998 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  37002 */   // (add:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  37002 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_H),
     /*  37007 */   GIR_RootConstrainSelectedInstOperands,
     /*  37008 */   // GIR_Coverage, 2778,
     /*  37008 */   GIR_Done,
     /*  37009 */ // Label 589: @37009
     /*  37009 */ GIM_Reject,
     /*  37010 */ // Label 168: @37010
     /*  37010 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(37035), // Rule ID 2777 //
     /*  37015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  37018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  37021 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  37024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  37028 */   // (add:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  37028 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_B),
     /*  37033 */   GIR_RootConstrainSelectedInstOperands,
     /*  37034 */   // GIR_Coverage, 2777,
     /*  37034 */   GIR_Done,
     /*  37035 */ // Label 590: @37035
     /*  37035 */ GIM_Reject,
     /*  37036 */ // Label 169: @37036
     /*  37036 */ GIM_Reject,
     /*  37037 */ // Label 1: @37037
     /*  37037 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 604*/ GIMT_Encode4(51888),
     /*  37048 */ /*GILLT_s32*//*Label 591*/ GIMT_Encode4(37136),
     /*  37052 */ /*GILLT_s64*//*Label 592*/ GIMT_Encode4(38618), GIMT_Encode4(0),
     /*  37060 */ /*GILLT_v2s32*//*Label 593*/ GIMT_Encode4(42524),
     /*  37064 */ /*GILLT_v2s64*//*Label 594*/ GIMT_Encode4(44015),
     /*  37068 */ /*GILLT_v4s16*//*Label 595*/ GIMT_Encode4(46475),
     /*  37072 */ /*GILLT_v4s32*//*Label 596*/ GIMT_Encode4(47966),
     /*  37076 */ /*GILLT_v8s8*//*Label 597*/ GIMT_Encode4(50426),
     /*  37080 */ /*GILLT_v8s16*//*Label 598*/ GIMT_Encode4(50501),
     /*  37084 */ /*GILLT_v16s8*//*Label 599*/ GIMT_Encode4(51709), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  37104 */ /*GILLT_nxv2s64*//*Label 600*/ GIMT_Encode4(51784), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  37116 */ /*GILLT_nxv4s32*//*Label 601*/ GIMT_Encode4(51810), GIMT_Encode4(0),
     /*  37124 */ /*GILLT_nxv8s16*//*Label 602*/ GIMT_Encode4(51836), GIMT_Encode4(0),
     /*  37132 */ /*GILLT_nxv16s8*//*Label 603*/ GIMT_Encode4(51862),
     /*  37136 */ // Label 591: @37136
     /*  37136 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(38617),
     /*  37141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  37144 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  37147 */   GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(37299), // Rule ID 10062 //
     /*  37152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  37155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  37175 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37179 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  37183 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  37186 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*  37191 */     // MIs[2] pattern
     /*  37191 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  37194 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  37199 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37201 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  37201 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  37204 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  37208 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37213 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  37215 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  37218 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  37222 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37227 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  37230 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  37234 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  37237 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37242 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37247 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37252 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37255 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
     /*  37259 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37264 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  37267 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  37271 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  37274 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  37276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37281 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  37288 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37293 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  37298 */     // GIR_Coverage, 10062,
     /*  37298 */     GIR_EraseRootFromParent_Done,
     /*  37299 */   // Label 606: @37299
     /*  37299 */   GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(37451), // Rule ID 10074 //
     /*  37304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  37307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37311 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  37327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  37335 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  37338 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*  37343 */     // MIs[2] pattern
     /*  37343 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  37346 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  37351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37353 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  37353 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  37356 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  37360 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37365 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  37367 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  37370 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  37374 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37379 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  37382 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  37386 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  37389 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37394 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37399 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37404 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37407 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
     /*  37411 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37416 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  37419 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  37423 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  37426 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  37428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37433 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  37440 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37445 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  37450 */     // GIR_Coverage, 10074,
     /*  37450 */     GIR_EraseRootFromParent_Done,
     /*  37451 */   // Label 607: @37451
     /*  37451 */   GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(37603), // Rule ID 10086 //
     /*  37456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  37459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37463 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37475 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  37479 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37483 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  37487 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  37490 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*  37495 */     // MIs[2] pattern
     /*  37495 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  37498 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  37503 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37505 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  37505 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  37508 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  37512 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37517 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  37519 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  37522 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  37526 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37531 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  37534 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  37538 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  37541 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37546 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37551 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37556 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37559 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
     /*  37563 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37568 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  37571 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  37575 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  37578 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  37580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37585 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  37592 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37597 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  37602 */     // GIR_Coverage, 10086,
     /*  37602 */     GIR_EraseRootFromParent_Done,
     /*  37603 */   // Label 608: @37603
     /*  37603 */   GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(37755), // Rule ID 10098 //
     /*  37608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  37611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37615 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37619 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37623 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37627 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  37631 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37635 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  37639 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  37642 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*  37647 */     // MIs[2] pattern
     /*  37647 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  37650 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  37655 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37657 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  37657 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  37660 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  37664 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37669 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  37671 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  37674 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  37678 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37683 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  37686 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  37690 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  37693 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37698 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37703 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37708 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37711 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
     /*  37715 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37720 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  37723 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  37727 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  37730 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  37732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37737 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  37744 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37749 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  37754 */     // GIR_Coverage, 10098,
     /*  37754 */     GIR_EraseRootFromParent_Done,
     /*  37755 */   // Label 609: @37755
     /*  37755 */   GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(37817), // Rule ID 3986 //
     /*  37760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37764 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  37768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  37776 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  37780 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  37784 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37789 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37794 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  37796 */     // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  37796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  37799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  37809 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  37815 */     GIR_RootConstrainSelectedInstOperands,
     /*  37816 */     // GIR_Coverage, 3986,
     /*  37816 */     GIR_EraseRootFromParent_Done,
     /*  37817 */   // Label 610: @37817
     /*  37817 */   GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(37974), // Rule ID 10200 //
     /*  37822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  37825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37829 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  37845 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37849 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  37853 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  37856 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  37861 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  37865 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  37867 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  37872 */     // MIs[2] pred
     /*  37872 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  37877 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37879 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  37879 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  37882 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  37886 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37891 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  37893 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  37896 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  37900 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37905 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  37908 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  37912 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  37915 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37920 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  37925 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37930 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37933 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_B),
     /*  37937 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37942 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  37946 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  37949 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  37951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37956 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  37963 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37968 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  37973 */     // GIR_Coverage, 10200,
     /*  37973 */     GIR_EraseRootFromParent_Done,
     /*  37974 */   // Label 611: @37974
     /*  37974 */   GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(38131), // Rule ID 10201 //
     /*  37979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  37982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37986 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  37990 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37994 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  37998 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  38002 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38006 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  38010 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  38013 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  38018 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  38022 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  38024 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  38029 */     // MIs[2] pred
     /*  38029 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  38034 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  38036 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  38036 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  38039 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  38043 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38048 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  38050 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  38053 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  38057 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38062 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  38065 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  38069 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  38072 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38077 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38082 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  38090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_H),
     /*  38094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38099 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  38103 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  38106 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  38111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38113 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  38120 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38125 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  38130 */     // GIR_Coverage, 10201,
     /*  38130 */     GIR_EraseRootFromParent_Done,
     /*  38131 */   // Label 612: @38131
     /*  38131 */   GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(38288), // Rule ID 10202 //
     /*  38136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  38139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  38155 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  38159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  38167 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  38170 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  38175 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  38179 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  38181 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  38186 */     // MIs[2] pred
     /*  38186 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  38191 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  38193 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  38193 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  38196 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  38200 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38205 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  38207 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  38210 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  38214 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38219 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  38222 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  38226 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  38229 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38234 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38239 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38244 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  38247 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_S),
     /*  38251 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38256 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  38260 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  38263 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  38268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38270 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  38277 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38282 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  38287 */     // GIR_Coverage, 10202,
     /*  38287 */     GIR_EraseRootFromParent_Done,
     /*  38288 */   // Label 613: @38288
     /*  38288 */   GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(38445), // Rule ID 10203 //
     /*  38293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  38296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38300 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  38312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  38316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38320 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  38324 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  38327 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  38332 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  38336 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  38338 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  38343 */     // MIs[2] pred
     /*  38343 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  38348 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  38350 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  38350 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  38353 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  38357 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38362 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  38364 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  38367 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  38371 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38376 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  38379 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  38383 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  38386 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38391 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  38396 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38401 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  38404 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_D),
     /*  38408 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38413 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  38417 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  38420 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  38425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38427 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  38434 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38439 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  38444 */     // GIR_Coverage, 10203,
     /*  38444 */     GIR_EraseRootFromParent_Done,
     /*  38445 */   // Label 614: @38445
     /*  38445 */   GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(38481), // Rule ID 3951 //
     /*  38450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38454 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  38458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*  38465 */     // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3)  =>  (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3)
     /*  38465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrx),
     /*  38468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38470 */     GIR_RootToRootCopy, /*OpIdx*/1, // R2
     /*  38472 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
     /*  38476 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  38479 */     GIR_RootConstrainSelectedInstOperands,
     /*  38480 */     // GIR_Coverage, 3951,
     /*  38480 */     GIR_EraseRootFromParent_Done,
     /*  38481 */   // Label 615: @38481
     /*  38481 */   GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(38514), // Rule ID 3956 //
     /*  38486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  38490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*  38501 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*  38501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*  38504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38506 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38508 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  38512 */     GIR_RootConstrainSelectedInstOperands,
     /*  38513 */     // GIR_Coverage, 3956,
     /*  38513 */     GIR_EraseRootFromParent_Done,
     /*  38514 */   // Label 616: @38514
     /*  38514 */   GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(38550), // Rule ID 3945 //
     /*  38519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  38527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*  38534 */     // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*  38534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*  38537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38539 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38541 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  38545 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  38548 */     GIR_RootConstrainSelectedInstOperands,
     /*  38549 */     // GIR_Coverage, 3945,
     /*  38549 */     GIR_EraseRootFromParent_Done,
     /*  38550 */   // Label 617: @38550
     /*  38550 */   GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(38586), // Rule ID 3949 //
     /*  38555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38559 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*  38570 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm)  =>  (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm)
     /*  38570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrs),
     /*  38573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38575 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38577 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
     /*  38581 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  38584 */     GIR_RootConstrainSelectedInstOperands,
     /*  38585 */     // GIR_Coverage, 3949,
     /*  38585 */     GIR_EraseRootFromParent_Done,
     /*  38586 */   // Label 618: @38586
     /*  38586 */   GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(38616), // Rule ID 3947 //
     /*  38591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38595 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  38603 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  38603 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrr),
     /*  38608 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
     /*  38614 */     GIR_RootConstrainSelectedInstOperands,
     /*  38615 */     // GIR_Coverage, 3947,
     /*  38615 */     GIR_Done,
     /*  38616 */   // Label 619: @38616
     /*  38616 */   GIM_Reject,
     /*  38617 */ // Label 605: @38617
     /*  38617 */ GIM_Reject,
     /*  38618 */ // Label 592: @38618
     /*  38618 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(42523),
     /*  38623 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  38626 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  38629 */   GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(38765), // Rule ID 5449 //
     /*  38634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38642 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38646 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38650 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38654 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  38658 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38662 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38667 */     // MIs[1] Operand 2
     /*  38667 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  38678 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  38682 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38686 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38690 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  38694 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  38698 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38702 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38707 */     // MIs[3] Operand 2
     /*  38707 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  38718 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  38720 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  38720 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  38723 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  38727 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38732 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  38736 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  38740 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  38745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38747 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  38754 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38759 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38764 */     // GIR_Coverage, 5449,
     /*  38764 */     GIR_EraseRootFromParent_Done,
     /*  38765 */   // Label 621: @38765
     /*  38765 */   GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(38901), // Rule ID 5448 //
     /*  38770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38782 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  38794 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38798 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38803 */     // MIs[1] Operand 2
     /*  38803 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  38814 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  38818 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38822 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38826 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  38830 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  38834 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38838 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38843 */     // MIs[3] Operand 2
     /*  38843 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  38854 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  38856 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  38856 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  38859 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  38863 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38868 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  38872 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  38876 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  38881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38883 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  38890 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38895 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38900 */     // GIR_Coverage, 5448,
     /*  38900 */     GIR_EraseRootFromParent_Done,
     /*  38901 */   // Label 622: @38901
     /*  38901 */   GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(39037), // Rule ID 5458 //
     /*  38906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38922 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  38926 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  38930 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38934 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38939 */     // MIs[1] Operand 2
     /*  38939 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  38950 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  38954 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  38958 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  38962 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  38966 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  38970 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  38974 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38979 */     // MIs[3] Operand 2
     /*  38979 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  38990 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  38992 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  38992 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  38995 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv2i32_v2i64),
     /*  38999 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39004 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  39012 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39019 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  39026 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39031 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39036 */     // GIR_Coverage, 5458,
     /*  39036 */     GIR_EraseRootFromParent_Done,
     /*  39037 */   // Label 623: @39037
     /*  39037 */   GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(39173), // Rule ID 5447 //
     /*  39042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  39054 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  39058 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39066 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  39070 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39075 */     // MIs[1] Operand 2
     /*  39075 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  39086 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  39090 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  39094 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  39098 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  39102 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  39106 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  39110 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39115 */     // MIs[3] Operand 2
     /*  39115 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  39126 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  39128 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  39128 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  39131 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  39135 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39140 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39144 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  39148 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39155 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  39162 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39167 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39172 */     // GIR_Coverage, 5447,
     /*  39172 */     GIR_EraseRootFromParent_Done,
     /*  39173 */   // Label 624: @39173
     /*  39173 */   GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(39309), // Rule ID 5446 //
     /*  39178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  39190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  39194 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39198 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39202 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  39206 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39211 */     // MIs[1] Operand 2
     /*  39211 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  39222 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  39226 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  39230 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  39234 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  39238 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39242 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  39246 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39251 */     // MIs[3] Operand 2
     /*  39251 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  39262 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  39264 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  39264 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  39267 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  39271 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39276 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39280 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  39284 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39291 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  39298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  39303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39308 */     // GIR_Coverage, 5446,
     /*  39308 */     GIR_EraseRootFromParent_Done,
     /*  39309 */   // Label 625: @39309
     /*  39309 */   GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(39446), // Rule ID 4003 //
     /*  39314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39318 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39338 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39342 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  39346 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  39350 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39355 */     // MIs[2] Operand 2
     /*  39355 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  39366 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  39370 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  39374 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  39378 */     // MIs[3] Operand 1
     /*  39378 */     // No operand predicates
     /*  39378 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  39380 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  39380 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  39383 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  39387 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39392 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  39397 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  39399 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  39402 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39406 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39411 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  39417 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39422 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  39430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39432 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39435 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  39438 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39444 */     GIR_RootConstrainSelectedInstOperands,
     /*  39445 */     // GIR_Coverage, 4003,
     /*  39445 */     GIR_EraseRootFromParent_Done,
     /*  39446 */   // Label 626: @39446
     /*  39446 */   GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(39545), // Rule ID 4001 //
     /*  39451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39455 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39463 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39467 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39471 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  39483 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39487 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39492 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  39496 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  39500 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  39504 */     // MIs[3] Operand 1
     /*  39504 */     // No operand predicates
     /*  39504 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  39506 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  39506 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  39509 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  39513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39518 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  39523 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  39528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39530 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39534 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39537 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39543 */     GIR_RootConstrainSelectedInstOperands,
     /*  39544 */     // GIR_Coverage, 4001,
     /*  39544 */     GIR_EraseRootFromParent_Done,
     /*  39545 */   // Label 627: @39545
     /*  39545 */   GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(39644), // Rule ID 4002 //
     /*  39550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39554 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39570 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39574 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39578 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39582 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39586 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39591 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  39595 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  39599 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  39603 */     // MIs[3] Operand 1
     /*  39603 */     // No operand predicates
     /*  39603 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  39605 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  39605 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  39608 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  39612 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39617 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  39622 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  39627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39629 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39633 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39636 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39642 */     GIR_RootConstrainSelectedInstOperands,
     /*  39643 */     // GIR_Coverage, 4002,
     /*  39643 */     GIR_EraseRootFromParent_Done,
     /*  39644 */   // Label 628: @39644
     /*  39644 */   GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(39730), // Rule ID 3996 //
     /*  39649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39653 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39673 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39677 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  39681 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39685 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39690 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  39694 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  39698 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  39702 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39707 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  39709 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  39709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  39712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  39722 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39728 */     GIR_RootConstrainSelectedInstOperands,
     /*  39729 */     // GIR_Coverage, 3996,
     /*  39729 */     GIR_EraseRootFromParent_Done,
     /*  39730 */   // Label 629: @39730
     /*  39730 */   GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(39816), // Rule ID 3997 //
     /*  39735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39739 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39755 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39759 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39763 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39767 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39771 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39776 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  39780 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39784 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  39788 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39793 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  39795 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  39795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  39798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39800 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  39804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  39808 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39814 */     GIR_RootConstrainSelectedInstOperands,
     /*  39815 */     // GIR_Coverage, 3997,
     /*  39815 */     GIR_EraseRootFromParent_Done,
     /*  39816 */   // Label 630: @39816
     /*  39816 */   GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(39917), // Rule ID 4023 //
     /*  39821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39825 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39841 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39845 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  39850 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  39854 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39858 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39862 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39867 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  39869 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  39869 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  39872 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39876 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39881 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  39887 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39892 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  39900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39902 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39905 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  39909 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  39915 */     GIR_RootConstrainSelectedInstOperands,
     /*  39916 */     // GIR_Coverage, 4023,
     /*  39916 */     GIR_EraseRootFromParent_Done,
     /*  39917 */   // Label 631: @39917
     /*  39917 */   GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(40018), // Rule ID 14110 //
     /*  39922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39926 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  39930 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39934 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  39938 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  39942 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  39946 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  39950 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  39954 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  39958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39963 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  39968 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  39970 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  39970 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  39973 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  39977 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39982 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  39988 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  39993 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  39998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  40001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40003 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  40006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  40010 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  40016 */     GIR_RootConstrainSelectedInstOperands,
     /*  40017 */     // GIR_Coverage, 14110,
     /*  40017 */     GIR_EraseRootFromParent_Done,
     /*  40018 */   // Label 632: @40018
     /*  40018 */   GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(40134), // Rule ID 4022 //
     /*  40023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40027 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  40031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40039 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40043 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40047 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  40052 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  40057 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40059 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  40059 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  40062 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40066 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40071 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  40077 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40082 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  40090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40099 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  40105 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40110 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  40118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40120 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  40123 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  40126 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  40132 */     GIR_RootConstrainSelectedInstOperands,
     /*  40133 */     // GIR_Coverage, 4022,
     /*  40133 */     GIR_EraseRootFromParent_Done,
     /*  40134 */   // Label 633: @40134
     /*  40134 */   GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(40267), // Rule ID 4009 //
     /*  40139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40155 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40159 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40163 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40167 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  40171 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  40175 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40180 */     // MIs[2] Operand 2
     /*  40180 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  40191 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  40195 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  40199 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  40203 */     // MIs[3] Operand 1
     /*  40203 */     // No operand predicates
     /*  40203 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  40205 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  40205 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  40208 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  40212 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40217 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  40222 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  40224 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  40227 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40231 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40236 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  40242 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40247 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  40255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40257 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  40260 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  40263 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  40265 */     GIR_RootConstrainSelectedInstOperands,
     /*  40266 */     // GIR_Coverage, 4009,
     /*  40266 */     GIR_EraseRootFromParent_Done,
     /*  40267 */   // Label 634: @40267
     /*  40267 */   GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(40362), // Rule ID 4007 //
     /*  40272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40276 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40292 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40296 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40300 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  40304 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  40308 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40313 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  40317 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  40321 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  40325 */     // MIs[3] Operand 1
     /*  40325 */     // No operand predicates
     /*  40325 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  40327 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  40327 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  40330 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  40334 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40339 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  40344 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  40346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  40349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  40355 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  40358 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  40360 */     GIR_RootConstrainSelectedInstOperands,
     /*  40361 */     // GIR_Coverage, 4007,
     /*  40361 */     GIR_EraseRootFromParent_Done,
     /*  40362 */   // Label 635: @40362
     /*  40362 */   GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(40457), // Rule ID 4008 //
     /*  40367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40371 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40375 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40379 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40383 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40387 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40391 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40395 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  40399 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  40403 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40408 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  40412 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  40416 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  40420 */     // MIs[3] Operand 1
     /*  40420 */     // No operand predicates
     /*  40420 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  40422 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  40422 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  40425 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  40429 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40434 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  40439 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  40441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  40444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  40450 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  40453 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  40455 */     GIR_RootConstrainSelectedInstOperands,
     /*  40456 */     // GIR_Coverage, 4008,
     /*  40456 */     GIR_EraseRootFromParent_Done,
     /*  40457 */   // Label 636: @40457
     /*  40457 */   GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(40539), // Rule ID 124 //
     /*  40462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40466 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40474 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40478 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40482 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40486 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40490 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  40494 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  40498 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40503 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  40507 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  40511 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  40515 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40520 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  40522 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  40522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  40525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  40531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  40535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  40537 */     GIR_RootConstrainSelectedInstOperands,
     /*  40538 */     // GIR_Coverage, 124,
     /*  40538 */     GIR_EraseRootFromParent_Done,
     /*  40539 */   // Label 637: @40539
     /*  40539 */   GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(40621), // Rule ID 126 //
     /*  40544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40548 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40552 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40556 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40560 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40564 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  40576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  40580 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40585 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  40589 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  40593 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  40597 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40602 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  40604 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  40604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  40607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  40613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  40617 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  40619 */     GIR_RootConstrainSelectedInstOperands,
     /*  40620 */     // GIR_Coverage, 126,
     /*  40620 */     GIR_EraseRootFromParent_Done,
     /*  40621 */   // Label 638: @40621
     /*  40621 */   GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(40683), // Rule ID 3987 //
     /*  40626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40630 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  40634 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40638 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40642 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40646 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40650 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40655 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40660 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40662 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  40662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  40665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  40667 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  40671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  40675 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  40681 */     GIR_RootConstrainSelectedInstOperands,
     /*  40682 */     // GIR_Coverage, 3987,
     /*  40682 */     GIR_EraseRootFromParent_Done,
     /*  40683 */   // Label 639: @40683
     /*  40683 */   GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(40741), // Rule ID 10059 //
     /*  40688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40695 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40707 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  40710 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*  40715 */     // MIs[1] pattern
     /*  40715 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  40718 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40723 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40725 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  40725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
     /*  40728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  40730 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  40732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  40736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  40739 */     GIR_RootConstrainSelectedInstOperands,
     /*  40740 */     // GIR_Coverage, 10059,
     /*  40740 */     GIR_EraseRootFromParent_Done,
     /*  40741 */   // Label 640: @40741
     /*  40741 */   GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(40799), // Rule ID 10071 //
     /*  40746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40753 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40757 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40761 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40765 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  40768 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*  40773 */     // MIs[1] pattern
     /*  40773 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  40776 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40781 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40783 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  40783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
     /*  40786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  40788 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  40790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  40794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  40797 */     GIR_RootConstrainSelectedInstOperands,
     /*  40798 */     // GIR_Coverage, 10071,
     /*  40798 */     GIR_EraseRootFromParent_Done,
     /*  40799 */   // Label 641: @40799
     /*  40799 */   GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(40857), // Rule ID 10083 //
     /*  40804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40811 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40823 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  40826 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*  40831 */     // MIs[1] pattern
     /*  40831 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  40834 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40839 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40841 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  40841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
     /*  40844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  40846 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  40848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  40852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  40855 */     GIR_RootConstrainSelectedInstOperands,
     /*  40856 */     // GIR_Coverage, 10083,
     /*  40856 */     GIR_EraseRootFromParent_Done,
     /*  40857 */   // Label 642: @40857
     /*  40857 */   GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(40915), // Rule ID 10095 //
     /*  40862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40869 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40881 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  40884 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*  40889 */     // MIs[1] pattern
     /*  40889 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  40892 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40897 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40899 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  40899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
     /*  40902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  40904 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  40906 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  40910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  40913 */     GIR_RootConstrainSelectedInstOperands,
     /*  40914 */     // GIR_Coverage, 10095,
     /*  40914 */     GIR_EraseRootFromParent_Done,
     /*  40915 */   // Label 643: @40915
     /*  40915 */   GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(41012), // Rule ID 4025 //
     /*  40920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40924 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  40936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40940 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  40944 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  40949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  40953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  40957 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  40961 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40966 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40968 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  40968 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  40971 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40975 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40980 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  40986 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40991 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  40999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  41001 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  41004 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  41008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  41010 */     GIR_RootConstrainSelectedInstOperands,
     /*  41011 */     // GIR_Coverage, 4025,
     /*  41011 */     GIR_EraseRootFromParent_Done,
     /*  41012 */   // Label 644: @41012
     /*  41012 */   GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(41109), // Rule ID 14111 //
     /*  41017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41021 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41025 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41029 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  41033 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41037 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  41041 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41045 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  41049 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  41053 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41058 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  41063 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41065 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  41065 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  41068 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41072 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41077 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  41083 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41088 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  41096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  41098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  41101 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  41105 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  41107 */     GIR_RootConstrainSelectedInstOperands,
     /*  41108 */     // GIR_Coverage, 14111,
     /*  41108 */     GIR_EraseRootFromParent_Done,
     /*  41109 */   // Label 645: @41109
     /*  41109 */   GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(41272), // Rule ID 5413 //
     /*  41114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  41130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  41134 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41138 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  41142 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  41146 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  41150 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41155 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41160 */     // MIs[1] Operand 2
     /*  41160 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  41171 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41173 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLSLv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  41173 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  41176 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41180 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41185 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41187 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  41190 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41194 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41199 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41202 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  41206 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  41209 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41214 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41219 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41224 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  41227 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_v2i64),
     /*  41231 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41236 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41239 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  41243 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  41247 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41254 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  41261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41266 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41271 */     // GIR_Coverage, 5413,
     /*  41271 */     GIR_EraseRootFromParent_Done,
     /*  41272 */   // Label 646: @41272
     /*  41272 */   GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(41435), // Rule ID 5410 //
     /*  41277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41281 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  41293 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  41297 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41301 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  41305 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  41309 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  41313 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41318 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41323 */     // MIs[1] Operand 2
     /*  41323 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  41334 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41336 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLSLv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  41336 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  41339 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41343 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41348 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41350 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  41353 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41357 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41362 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41365 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  41369 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  41372 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41377 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41382 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41387 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  41390 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_v2i64),
     /*  41394 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41399 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41402 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  41406 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  41410 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41417 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  41424 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41429 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41434 */     // GIR_Coverage, 5410,
     /*  41434 */     GIR_EraseRootFromParent_Done,
     /*  41435 */   // Label 647: @41435
     /*  41435 */   GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(41585), // Rule ID 5455 //
     /*  41440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41444 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  41456 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  41460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  41468 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  41472 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41477 */     // MIs[1] Operand 2
     /*  41477 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  41488 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41490 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  41490 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  41493 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41497 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41502 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41504 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  41507 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41511 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41516 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41519 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41523 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  41526 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41531 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41536 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41541 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  41544 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  41548 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41553 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41556 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  41560 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41567 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  41574 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41579 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41584 */     // GIR_Coverage, 5455,
     /*  41584 */     GIR_EraseRootFromParent_Done,
     /*  41585 */   // Label 648: @41585
     /*  41585 */   GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(41735), // Rule ID 5461 //
     /*  41590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  41606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  41610 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41614 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  41618 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  41622 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41627 */     // MIs[1] Operand 2
     /*  41627 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  41638 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41640 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SSUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  41640 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  41643 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41647 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41652 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41654 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  41657 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41661 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41666 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41669 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41673 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  41676 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41681 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41686 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41691 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  41694 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv2i32_v2i64),
     /*  41698 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41703 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41706 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  41710 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41717 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  41724 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41729 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41734 */     // GIR_Coverage, 5461,
     /*  41734 */     GIR_EraseRootFromParent_Done,
     /*  41735 */   // Label 649: @41735
     /*  41735 */   GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(41885), // Rule ID 5454 //
     /*  41740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41744 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  41756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  41760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  41768 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  41772 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41777 */     // MIs[1] Operand 2
     /*  41777 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  41788 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41790 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  41790 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  41793 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41797 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41802 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41804 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  41807 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41811 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41816 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41819 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41823 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  41826 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41831 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41836 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41841 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  41844 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  41848 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41853 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41856 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  41860 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41867 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  41874 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  41879 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  41884 */     // GIR_Coverage, 5454,
     /*  41884 */     GIR_EraseRootFromParent_Done,
     /*  41885 */   // Label 650: @41885
     /*  41885 */   GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(41921), // Rule ID 3952 //
     /*  41890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41894 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  41898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  41905 */     // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3)  =>  (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3)
     /*  41905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrx),
     /*  41908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  41910 */     GIR_RootToRootCopy, /*OpIdx*/1, // R2
     /*  41912 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
     /*  41916 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  41919 */     GIR_RootConstrainSelectedInstOperands,
     /*  41920 */     // GIR_Coverage, 3952,
     /*  41920 */     GIR_EraseRootFromParent_Done,
     /*  41921 */   // Label 651: @41921
     /*  41921 */   GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(41954), // Rule ID 3957 //
     /*  41926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  41930 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  41941 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  41941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*  41944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  41946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  41948 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  41952 */     GIR_RootConstrainSelectedInstOperands,
     /*  41953 */     // GIR_Coverage, 3957,
     /*  41953 */     GIR_EraseRootFromParent_Done,
     /*  41954 */   // Label 652: @41954
     /*  41954 */   GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(42066), // Rule ID 4024 //
     /*  41959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41963 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41967 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41971 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  41975 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41979 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  41983 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  41988 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  41993 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  41995 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  41995 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  41998 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42002 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42007 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  42013 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42018 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  42026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42035 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  42041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  42054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  42059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  42062 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  42064 */     GIR_RootConstrainSelectedInstOperands,
     /*  42065 */     // GIR_Coverage, 4024,
     /*  42065 */     GIR_EraseRootFromParent_Done,
     /*  42066 */   // Label 653: @42066
     /*  42066 */   GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(42102), // Rule ID 3946 //
     /*  42071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  42079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*  42086 */     // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  42086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  42089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42091 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42093 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  42097 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  42100 */     GIR_RootConstrainSelectedInstOperands,
     /*  42101 */     // GIR_Coverage, 3946,
     /*  42101 */     GIR_EraseRootFromParent_Done,
     /*  42102 */   // Label 654: @42102
     /*  42102 */   GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(42138), // Rule ID 3950 //
     /*  42107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  42122 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm)  =>  (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm)
     /*  42122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrs),
     /*  42125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42127 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42129 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
     /*  42133 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  42136 */     GIR_RootConstrainSelectedInstOperands,
     /*  42137 */     // GIR_Coverage, 3950,
     /*  42137 */     GIR_EraseRootFromParent_Done,
     /*  42138 */   // Label 655: @42138
     /*  42138 */   GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(42201), // Rule ID 10192 //
     /*  42143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  42146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42150 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42154 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  42158 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  42162 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  42165 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  42170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  42174 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  42176 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  42181 */     // MIs[1] pred
     /*  42181 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  42186 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42188 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  42188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_B),
     /*  42191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  42193 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  42197 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42199 */     GIR_RootConstrainSelectedInstOperands,
     /*  42200 */     // GIR_Coverage, 10192,
     /*  42200 */     GIR_EraseRootFromParent_Done,
     /*  42201 */   // Label 656: @42201
     /*  42201 */   GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(42264), // Rule ID 10193 //
     /*  42206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  42209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42213 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42217 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  42221 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  42225 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  42228 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  42233 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  42237 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  42239 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  42244 */     // MIs[1] pred
     /*  42244 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  42249 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42251 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  42251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_H),
     /*  42254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  42256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  42260 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42262 */     GIR_RootConstrainSelectedInstOperands,
     /*  42263 */     // GIR_Coverage, 10193,
     /*  42263 */     GIR_EraseRootFromParent_Done,
     /*  42264 */   // Label 657: @42264
     /*  42264 */   GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(42327), // Rule ID 10194 //
     /*  42269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  42272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42276 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  42284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  42288 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  42291 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  42296 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  42300 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  42302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  42307 */     // MIs[1] pred
     /*  42307 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  42312 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42314 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  42314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_S),
     /*  42317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  42319 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  42323 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42325 */     GIR_RootConstrainSelectedInstOperands,
     /*  42326 */     // GIR_Coverage, 10194,
     /*  42326 */     GIR_EraseRootFromParent_Done,
     /*  42327 */   // Label 658: @42327
     /*  42327 */   GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(42390), // Rule ID 10195 //
     /*  42332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  42335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42339 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42343 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  42347 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  42351 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  42354 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  42359 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  42363 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  42365 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  42370 */     // MIs[1] pred
     /*  42370 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  42375 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42377 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  42377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_D),
     /*  42380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  42382 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  42386 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42388 */     GIR_RootConstrainSelectedInstOperands,
     /*  42389 */     // GIR_Coverage, 10195,
     /*  42389 */     GIR_EraseRootFromParent_Done,
     /*  42390 */   // Label 659: @42390
     /*  42390 */   GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(42429), // Rule ID 1659 //
     /*  42395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  42398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42406 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  42412 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  42414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42418 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42420 */     // (sub:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (NEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /*  42420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
     /*  42423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42425 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  42427 */     GIR_RootConstrainSelectedInstOperands,
     /*  42428 */     // GIR_Coverage, 1659,
     /*  42428 */     GIR_EraseRootFromParent_Done,
     /*  42429 */   // Label 660: @42429
     /*  42429 */   GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(42465), // Rule ID 5296 //
     /*  42434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42438 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42442 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  42448 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  42450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42454 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  42456 */     // (sub:{ *:[i64] } immAllZerosV:{ *:[i64] }, FPR64:{ *:[i64] }:$Rn)  =>  (NEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /*  42456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
     /*  42459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42461 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  42463 */     GIR_RootConstrainSelectedInstOperands,
     /*  42464 */     // GIR_Coverage, 5296,
     /*  42464 */     GIR_EraseRootFromParent_Done,
     /*  42465 */   // Label 661: @42465
     /*  42465 */   GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(42492), // Rule ID 1648 //
     /*  42470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  42473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42481 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42485 */     // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  42485 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv1i64),
     /*  42490 */     GIR_RootConstrainSelectedInstOperands,
     /*  42491 */     // GIR_Coverage, 1648,
     /*  42491 */     GIR_Done,
     /*  42492 */   // Label 662: @42492
     /*  42492 */   GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(42522), // Rule ID 3948 //
     /*  42497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42509 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  42509 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrr),
     /*  42514 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
     /*  42520 */     GIR_RootConstrainSelectedInstOperands,
     /*  42521 */     // GIR_Coverage, 3948,
     /*  42521 */     GIR_Done,
     /*  42522 */   // Label 663: @42522
     /*  42522 */   GIM_Reject,
     /*  42523 */ // Label 620: @42523
     /*  42523 */ GIM_Reject,
     /*  42524 */ // Label 593: @42524
     /*  42524 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(44014),
     /*  42529 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42532 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  42535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42539 */   GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(42671), // Rule ID 5445 //
     /*  42544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42548 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42552 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42564 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42568 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42573 */     // MIs[1] Operand 2
     /*  42573 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42584 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42588 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42592 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42596 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42600 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42604 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42608 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42613 */     // MIs[3] Operand 2
     /*  42613 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42624 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42626 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  42626 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  42629 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  42633 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42638 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42642 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42646 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42653 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42660 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42665 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42670 */     // GIR_Coverage, 5445,
     /*  42670 */     GIR_EraseRootFromParent_Done,
     /*  42671 */   // Label 665: @42671
     /*  42671 */   GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(42803), // Rule ID 5444 //
     /*  42676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42680 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42684 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42688 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42692 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42696 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42700 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42705 */     // MIs[1] Operand 2
     /*  42705 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42716 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42720 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42724 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42728 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42732 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42736 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42740 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42745 */     // MIs[3] Operand 2
     /*  42745 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42756 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42758 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  42758 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  42761 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  42765 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42770 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42774 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42778 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42785 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42792 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42797 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42802 */     // GIR_Coverage, 5444,
     /*  42802 */     GIR_EraseRootFromParent_Done,
     /*  42803 */   // Label 666: @42803
     /*  42803 */   GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(42935), // Rule ID 5457 //
     /*  42808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42816 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  42828 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42832 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42837 */     // MIs[1] Operand 2
     /*  42837 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42848 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42852 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42856 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42860 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42864 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  42868 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42872 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42877 */     // MIs[3] Operand 2
     /*  42877 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42888 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42890 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  42890 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  42893 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i16_v4i32),
     /*  42897 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42902 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42906 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42910 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42917 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42924 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42929 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42934 */     // GIR_Coverage, 5457,
     /*  42934 */     GIR_EraseRootFromParent_Done,
     /*  42935 */   // Label 667: @42935
     /*  42935 */   GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(43067), // Rule ID 5443 //
     /*  42940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42952 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42956 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42960 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  42964 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42969 */     // MIs[1] Operand 2
     /*  42969 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42980 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42984 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42988 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  42992 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42996 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  43000 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43004 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43009 */     // MIs[3] Operand 2
     /*  43009 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  43020 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  43022 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43022 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43025 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  43029 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43034 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43038 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  43042 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43049 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43056 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43061 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43066 */     // GIR_Coverage, 5443,
     /*  43066 */     GIR_EraseRootFromParent_Done,
     /*  43067 */   // Label 668: @43067
     /*  43067 */   GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(43199), // Rule ID 5442 //
     /*  43072 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  43076 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43080 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43084 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43088 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43092 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43096 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43101 */     // MIs[1] Operand 2
     /*  43101 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43112 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  43116 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43120 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43124 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  43128 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43132 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43136 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43141 */     // MIs[3] Operand 2
     /*  43141 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  43152 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  43154 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43154 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43157 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  43161 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43166 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43170 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  43174 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43181 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43188 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43193 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43198 */     // GIR_Coverage, 5442,
     /*  43198 */     GIR_EraseRootFromParent_Done,
     /*  43199 */   // Label 669: @43199
     /*  43199 */   GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(43358), // Rule ID 5412 //
     /*  43204 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43208 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43212 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43216 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  43228 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43232 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  43236 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43241 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43246 */     // MIs[1] Operand 2
     /*  43246 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43257 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43259 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLSLv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43259 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  43262 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  43266 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43271 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  43273 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  43276 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  43280 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43285 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  43288 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  43292 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  43295 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43300 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43305 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43310 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43313 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_v4i32),
     /*  43317 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43322 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  43325 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43329 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  43333 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43340 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43347 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43352 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43357 */     // GIR_Coverage, 5412,
     /*  43357 */     GIR_EraseRootFromParent_Done,
     /*  43358 */   // Label 670: @43358
     /*  43358 */   GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(43517), // Rule ID 5409 //
     /*  43363 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43379 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43383 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  43387 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43391 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  43395 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43400 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43405 */     // MIs[1] Operand 2
     /*  43405 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43416 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43418 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLSLv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43418 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  43421 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  43425 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43430 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  43432 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  43435 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  43439 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43444 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  43447 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  43451 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  43454 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43459 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43464 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43469 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43472 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_v4i32),
     /*  43476 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43481 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  43484 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43488 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  43492 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43499 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43506 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43511 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43516 */     // GIR_Coverage, 5409,
     /*  43516 */     GIR_EraseRootFromParent_Done,
     /*  43517 */   // Label 671: @43517
     /*  43517 */   GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(43663), // Rule ID 5453 //
     /*  43522 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43534 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  43546 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43550 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43555 */     // MIs[1] Operand 2
     /*  43555 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43566 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43568 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43568 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  43571 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  43575 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43580 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  43582 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  43585 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  43589 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43594 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  43597 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  43601 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  43604 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43609 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43614 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43619 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43622 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  43626 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43631 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  43634 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  43638 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43645 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43652 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43657 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43662 */     // GIR_Coverage, 5453,
     /*  43662 */     GIR_EraseRootFromParent_Done,
     /*  43663 */   // Label 672: @43663
     /*  43663 */   GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(43809), // Rule ID 5460 //
     /*  43668 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43672 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43676 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43680 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43684 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43688 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  43692 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43696 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43701 */     // MIs[1] Operand 2
     /*  43701 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43712 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43714 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SSUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43714 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  43717 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  43721 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43726 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  43728 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  43731 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  43735 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43740 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  43743 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  43747 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  43750 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i16_v4i32),
     /*  43772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43777 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  43780 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  43784 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43791 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43798 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43803 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43808 */     // GIR_Coverage, 5460,
     /*  43808 */     GIR_EraseRootFromParent_Done,
     /*  43809 */   // Label 673: @43809
     /*  43809 */   GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(43955), // Rule ID 5452 //
     /*  43814 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43818 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43822 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  43826 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  43830 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43834 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43838 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  43842 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43847 */     // MIs[1] Operand 2
     /*  43847 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  43858 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43860 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  43860 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  43863 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  43867 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43872 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  43874 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  43877 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  43881 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43886 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  43889 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  43893 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  43896 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43901 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43906 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43911 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  43914 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  43918 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43923 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  43926 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  43930 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  43937 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  43944 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43949 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  43954 */     // GIR_Coverage, 5452,
     /*  43954 */     GIR_EraseRootFromParent_Done,
     /*  43955 */   // Label 674: @43955
     /*  43955 */   GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(43990), // Rule ID 973 //
     /*  43960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  43963 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  43967 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  43973 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  43975 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  43979 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  43981 */     // (sub:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn)  =>  (NEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /*  43981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i32),
     /*  43984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  43988 */     GIR_RootConstrainSelectedInstOperands,
     /*  43989 */     // GIR_Coverage, 973,
     /*  43989 */     GIR_EraseRootFromParent_Done,
     /*  43990 */   // Label 675: @43990
     /*  43990 */   GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(44013), // Rule ID 1480 //
     /*  43995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  43998 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44006 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  44006 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i32),
     /*  44011 */     GIR_RootConstrainSelectedInstOperands,
     /*  44012 */     // GIR_Coverage, 1480,
     /*  44012 */     GIR_Done,
     /*  44013 */   // Label 676: @44013
     /*  44013 */   GIM_Reject,
     /*  44014 */ // Label 664: @44014
     /*  44014 */ GIM_Reject,
     /*  44015 */ // Label 594: @44015
     /*  44015 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(46474),
     /*  44020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  44023 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  44026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44030 */   GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(44144), // Rule ID 2052 //
     /*  44035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44038 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  44050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44058 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  44062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44066 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44070 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44074 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44078 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44082 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44086 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44091 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44095 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44099 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  44103 */     // MIs[4] Operand 1
     /*  44103 */     // No operand predicates
     /*  44103 */     // MIs[2] Operand 2
     /*  44103 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  44114 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  44116 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44123 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  44123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_indexed),
     /*  44126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44128 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  44130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44139 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  44142 */     GIR_RootConstrainSelectedInstOperands,
     /*  44143 */     // GIR_Coverage, 2052,
     /*  44143 */     GIR_EraseRootFromParent_Done,
     /*  44144 */   // Label 678: @44144
     /*  44144 */   GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(44258), // Rule ID 13800 //
     /*  44149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  44164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44172 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44176 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44180 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44184 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44188 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44192 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44196 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44200 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44205 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44209 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44213 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  44217 */     // MIs[4] Operand 1
     /*  44217 */     // No operand predicates
     /*  44217 */     // MIs[2] Operand 2
     /*  44217 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  44228 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  44230 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44237 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (SMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  44237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_indexed),
     /*  44240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  44244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44253 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  44256 */     GIR_RootConstrainSelectedInstOperands,
     /*  44257 */     // GIR_Coverage, 13800,
     /*  44257 */     GIR_EraseRootFromParent_Done,
     /*  44258 */   // Label 679: @44258
     /*  44258 */   GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(44372), // Rule ID 2104 //
     /*  44263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44266 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44270 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44274 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  44278 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44282 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  44290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44294 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44298 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44302 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44306 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44310 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44314 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44319 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44323 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44327 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  44331 */     // MIs[4] Operand 1
     /*  44331 */     // No operand predicates
     /*  44331 */     // MIs[2] Operand 2
     /*  44331 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  44342 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  44344 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44351 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (UMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  44351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_indexed),
     /*  44354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44356 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  44358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44367 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  44370 */     GIR_RootConstrainSelectedInstOperands,
     /*  44371 */     // GIR_Coverage, 2104,
     /*  44371 */     GIR_EraseRootFromParent_Done,
     /*  44372 */   // Label 680: @44372
     /*  44372 */   GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(44486), // Rule ID 13836 //
     /*  44377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44380 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  44392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44396 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44400 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44404 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44408 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44412 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44416 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44420 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44424 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44428 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44433 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44437 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44441 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  44445 */     // MIs[4] Operand 1
     /*  44445 */     // No operand predicates
     /*  44445 */     // MIs[2] Operand 2
     /*  44445 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  44456 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  44458 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44465 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (UMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  44465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_indexed),
     /*  44468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44470 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  44472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44481 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  44484 */     GIR_RootConstrainSelectedInstOperands,
     /*  44485 */     // GIR_Coverage, 13836,
     /*  44485 */     GIR_EraseRootFromParent_Done,
     /*  44486 */   // Label 681: @44486
     /*  44486 */   GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(44551), // Rule ID 1859 //
     /*  44491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  44498 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  44502 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  44510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  44514 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44518 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44520 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44527 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44534 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  44534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  44537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  44549 */     GIR_RootConstrainSelectedInstOperands,
     /*  44550 */     // GIR_Coverage, 1859,
     /*  44550 */     GIR_EraseRootFromParent_Done,
     /*  44551 */   // Label 682: @44551
     /*  44551 */   GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(44616), // Rule ID 1858 //
     /*  44556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44559 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  44563 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  44567 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  44575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44579 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44583 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44585 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44592 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44599 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  44599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  44602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  44614 */     GIR_RootConstrainSelectedInstOperands,
     /*  44615 */     // GIR_Coverage, 1858,
     /*  44615 */     GIR_EraseRootFromParent_Done,
     /*  44616 */   // Label 683: @44616
     /*  44616 */   GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(44681), // Rule ID 1763 //
     /*  44621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  44628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  44632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44636 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  44640 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  44644 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44648 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44650 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44657 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44664 */     // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SSUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  44664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i32_v2i64),
     /*  44667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  44679 */     GIR_RootConstrainSelectedInstOperands,
     /*  44680 */     // GIR_Coverage, 1763,
     /*  44680 */     GIR_EraseRootFromParent_Done,
     /*  44681 */   // Label 684: @44681
     /*  44681 */   GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(44746), // Rule ID 1857 //
     /*  44686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44689 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  44693 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44697 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44701 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  44705 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  44709 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44713 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44715 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44722 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44729 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  44729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  44732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  44744 */     GIR_RootConstrainSelectedInstOperands,
     /*  44745 */     // GIR_Coverage, 1857,
     /*  44745 */     GIR_EraseRootFromParent_Done,
     /*  44746 */   // Label 685: @44746
     /*  44746 */   GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(44811), // Rule ID 1856 //
     /*  44751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  44758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44766 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  44770 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44774 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44778 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44780 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44787 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  44794 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  44794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  44797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  44804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  44809 */     GIR_RootConstrainSelectedInstOperands,
     /*  44810 */     // GIR_Coverage, 1856,
     /*  44810 */     GIR_EraseRootFromParent_Done,
     /*  44811 */   // Label 686: @44811
     /*  44811 */   GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(44922), // Rule ID 13798 //
     /*  44816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44819 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  44831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44839 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44843 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44847 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44851 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44855 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44859 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44863 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44867 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44872 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44876 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44880 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  44884 */     // MIs[4] Operand 1
     /*  44884 */     // No operand predicates
     /*  44884 */     // MIs[2] Operand 2
     /*  44884 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  44895 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44900 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  44902 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  44902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  44905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44907 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  44909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  44913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44917 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  44920 */     GIR_RootConstrainSelectedInstOperands,
     /*  44921 */     // GIR_Coverage, 13798,
     /*  44921 */     GIR_EraseRootFromParent_Done,
     /*  44922 */   // Label 687: @44922
     /*  44922 */   GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(45033), // Rule ID 2050 //
     /*  44927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  44930 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  44942 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44946 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44950 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44955 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  44959 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44963 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44967 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  44971 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  44975 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  44979 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  44983 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44988 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  44992 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  44996 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45000 */     // MIs[4] Operand 1
     /*  45000 */     // No operand predicates
     /*  45000 */     // MIs[2] Operand 2
     /*  45000 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  45011 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  45013 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  45016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45018 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45020 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  45028 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  45031 */     GIR_RootConstrainSelectedInstOperands,
     /*  45032 */     // GIR_Coverage, 2050,
     /*  45032 */     GIR_EraseRootFromParent_Done,
     /*  45033 */   // Label 688: @45033
     /*  45033 */   GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(45144), // Rule ID 13834 //
     /*  45038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45041 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45045 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45049 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  45053 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45057 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  45069 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45073 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  45077 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45081 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45085 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  45089 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45094 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  45098 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45102 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45106 */     // MIs[4] Operand 1
     /*  45106 */     // No operand predicates
     /*  45106 */     // MIs[2] Operand 2
     /*  45106 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  45117 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45122 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  45124 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  45127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45129 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  45135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  45139 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  45142 */     GIR_RootConstrainSelectedInstOperands,
     /*  45143 */     // GIR_Coverage, 13834,
     /*  45143 */     GIR_EraseRootFromParent_Done,
     /*  45144 */   // Label 689: @45144
     /*  45144 */   GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(45255), // Rule ID 2102 //
     /*  45149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  45164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45172 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  45181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  45185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45189 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  45193 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45197 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45201 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  45205 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45210 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  45214 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45218 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45222 */     // MIs[4] Operand 1
     /*  45222 */     // No operand predicates
     /*  45222 */     // MIs[2] Operand 2
     /*  45222 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  45233 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  45235 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  45238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45240 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  45250 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  45253 */     GIR_RootConstrainSelectedInstOperands,
     /*  45254 */     // GIR_Coverage, 2102,
     /*  45254 */     GIR_EraseRootFromParent_Done,
     /*  45255 */   // Label 690: @45255
     /*  45255 */   GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(45318), // Rule ID 1739 //
     /*  45260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45263 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  45275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45283 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45285 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45292 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45299 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  45299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_v2i64),
     /*  45302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45304 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  45311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  45316 */     GIR_RootConstrainSelectedInstOperands,
     /*  45317 */     // GIR_Coverage, 1739,
     /*  45317 */     GIR_EraseRootFromParent_Done,
     /*  45318 */   // Label 691: @45318
     /*  45318 */   GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(45381), // Rule ID 1829 //
     /*  45323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45326 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  45338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45342 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45346 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45348 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45355 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45362 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  45362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_v2i64),
     /*  45365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45367 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  45374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  45379 */     GIR_RootConstrainSelectedInstOperands,
     /*  45380 */     // GIR_Coverage, 1829,
     /*  45380 */     GIR_EraseRootFromParent_Done,
     /*  45381 */   // Label 692: @45381
     /*  45381 */   GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(45469), // Rule ID 13799 //
     /*  45386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45389 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45393 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45397 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  45401 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45405 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45409 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45413 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45417 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45421 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  45425 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45430 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  45434 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45438 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45442 */     // MIs[3] Operand 1
     /*  45442 */     // No operand predicates
     /*  45442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45447 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  45449 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  45452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45454 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45456 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  45460 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45464 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  45467 */     GIR_RootConstrainSelectedInstOperands,
     /*  45468 */     // GIR_Coverage, 13799,
     /*  45468 */     GIR_EraseRootFromParent_Done,
     /*  45469 */   // Label 693: @45469
     /*  45469 */   GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(45557), // Rule ID 2051 //
     /*  45474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  45489 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45493 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45497 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  45506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45510 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45514 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  45518 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45523 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  45527 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45531 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45535 */     // MIs[3] Operand 1
     /*  45535 */     // No operand predicates
     /*  45535 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  45537 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  45540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45542 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45552 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  45555 */     GIR_RootConstrainSelectedInstOperands,
     /*  45556 */     // GIR_Coverage, 2051,
     /*  45556 */     GIR_EraseRootFromParent_Done,
     /*  45557 */   // Label 694: @45557
     /*  45557 */   GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(45645), // Rule ID 13835 //
     /*  45562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45565 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  45577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45581 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45585 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45589 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45593 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45597 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  45601 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45606 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  45610 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45614 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45618 */     // MIs[3] Operand 1
     /*  45618 */     // No operand predicates
     /*  45618 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45623 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  45625 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  45628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45630 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  45636 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45640 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  45643 */     GIR_RootConstrainSelectedInstOperands,
     /*  45644 */     // GIR_Coverage, 13835,
     /*  45644 */     GIR_EraseRootFromParent_Done,
     /*  45645 */   // Label 695: @45645
     /*  45645 */   GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(45733), // Rule ID 2103 //
     /*  45650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45653 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  45665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  45673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45678 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  45682 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  45686 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  45690 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  45694 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45699 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  45703 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  45707 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  45711 */     // MIs[3] Operand 1
     /*  45711 */     // No operand predicates
     /*  45711 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  45713 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  45713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  45716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45718 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  45720 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45724 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45728 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  45731 */     GIR_RootConstrainSelectedInstOperands,
     /*  45732 */     // GIR_Coverage, 2103,
     /*  45732 */     GIR_EraseRootFromParent_Done,
     /*  45733 */   // Label 696: @45733
     /*  45733 */   GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(45780), // Rule ID 1871 //
     /*  45738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45741 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45745 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45749 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  45753 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45757 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45759 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45766 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  45766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
     /*  45769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45771 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  45778 */     GIR_RootConstrainSelectedInstOperands,
     /*  45779 */     // GIR_Coverage, 1871,
     /*  45779 */     GIR_EraseRootFromParent_Done,
     /*  45780 */   // Label 697: @45780
     /*  45780 */   GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(45827), // Rule ID 1769 //
     /*  45785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45788 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45792 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45796 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  45800 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45804 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45806 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45813 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SSUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  45813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i32_v2i64),
     /*  45816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45818 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  45825 */     GIR_RootConstrainSelectedInstOperands,
     /*  45826 */     // GIR_Coverage, 1769,
     /*  45826 */     GIR_EraseRootFromParent_Done,
     /*  45827 */   // Label 698: @45827
     /*  45827 */   GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(45874), // Rule ID 1870 //
     /*  45832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45835 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45839 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45843 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  45847 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45851 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45853 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  45860 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  45860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
     /*  45863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45865 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  45872 */     GIR_RootConstrainSelectedInstOperands,
     /*  45873 */     // GIR_Coverage, 1870,
     /*  45873 */     GIR_EraseRootFromParent_Done,
     /*  45874 */   // Label 699: @45874
     /*  45874 */   GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(45933), // Rule ID 1855 //
     /*  45879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45882 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  45886 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  45890 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45894 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45899 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  45903 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  45907 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45911 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45916 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  45918 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  45918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  45921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45931 */     GIR_RootConstrainSelectedInstOperands,
     /*  45932 */     // GIR_Coverage, 1855,
     /*  45932 */     GIR_EraseRootFromParent_Done,
     /*  45933 */   // Label 700: @45933
     /*  45933 */   GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(45992), // Rule ID 1854 //
     /*  45938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45941 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  45945 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  45949 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45958 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  45962 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  45966 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45970 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45975 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  45977 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  45977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  45980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45982 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  45986 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45990 */     GIR_RootConstrainSelectedInstOperands,
     /*  45991 */     // GIR_Coverage, 1854,
     /*  45991 */     GIR_EraseRootFromParent_Done,
     /*  45992 */   // Label 701: @45992
     /*  45992 */   GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(46051), // Rule ID 1762 //
     /*  45997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46008 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46017 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  46021 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46025 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46029 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46034 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  46036 */     // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv2i32_v2i64),
     /*  46039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46041 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  46045 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  46049 */     GIR_RootConstrainSelectedInstOperands,
     /*  46050 */     // GIR_Coverage, 1762,
     /*  46050 */     GIR_EraseRootFromParent_Done,
     /*  46051 */   // Label 702: @46051
     /*  46051 */   GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(46110), // Rule ID 1853 //
     /*  46056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46059 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46063 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46067 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46071 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  46080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46084 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46088 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46093 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  46095 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  46098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46100 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  46104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  46108 */     GIR_RootConstrainSelectedInstOperands,
     /*  46109 */     // GIR_Coverage, 1853,
     /*  46109 */     GIR_EraseRootFromParent_Done,
     /*  46110 */   // Label 703: @46110
     /*  46110 */   GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(46169), // Rule ID 1852 //
     /*  46115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46118 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46122 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46126 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46130 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46135 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  46139 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46143 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46147 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46152 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  46154 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  46157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  46163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  46167 */     GIR_RootConstrainSelectedInstOperands,
     /*  46168 */     // GIR_Coverage, 1852,
     /*  46168 */     GIR_EraseRootFromParent_Done,
     /*  46169 */   // Label 704: @46169
     /*  46169 */   GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(46204), // Rule ID 975 //
     /*  46174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46181 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  46187 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  46189 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46193 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46195 */     // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn)  =>  (NEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /*  46195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i64),
     /*  46198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  46202 */     GIR_RootConstrainSelectedInstOperands,
     /*  46203 */     // GIR_Coverage, 975,
     /*  46203 */     GIR_EraseRootFromParent_Done,
     /*  46204 */   // Label 705: @46204
     /*  46204 */   GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(46261), // Rule ID 1738 //
     /*  46209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46212 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46216 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46220 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  46224 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46228 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  46232 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46242 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46244 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_v2i64),
     /*  46247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46249 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  46251 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  46255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  46259 */     GIR_RootConstrainSelectedInstOperands,
     /*  46260 */     // GIR_Coverage, 1738,
     /*  46260 */     GIR_EraseRootFromParent_Done,
     /*  46261 */   // Label 706: @46261
     /*  46261 */   GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(46318), // Rule ID 1828 //
     /*  46266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46269 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  46281 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46285 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  46289 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46294 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46301 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_v2i64),
     /*  46304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46306 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  46308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  46312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  46316 */     GIR_RootConstrainSelectedInstOperands,
     /*  46317 */     // GIR_Coverage, 1828,
     /*  46317 */     GIR_EraseRootFromParent_Done,
     /*  46318 */   // Label 707: @46318
     /*  46318 */   GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(46362), // Rule ID 1869 //
     /*  46323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46326 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46342 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46347 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46349 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  46352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46354 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  46356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  46360 */     GIR_RootConstrainSelectedInstOperands,
     /*  46361 */     // GIR_Coverage, 1869,
     /*  46361 */     GIR_EraseRootFromParent_Done,
     /*  46362 */   // Label 708: @46362
     /*  46362 */   GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(46406), // Rule ID 1768 //
     /*  46367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46370 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46391 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46393 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv2i32_v2i64),
     /*  46396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46398 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  46400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  46404 */     GIR_RootConstrainSelectedInstOperands,
     /*  46405 */     // GIR_Coverage, 1768,
     /*  46405 */     GIR_EraseRootFromParent_Done,
     /*  46406 */   // Label 709: @46406
     /*  46406 */   GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(46450), // Rule ID 1868 //
     /*  46411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46414 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46435 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  46437 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  46437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  46440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46442 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  46444 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  46448 */     GIR_RootConstrainSelectedInstOperands,
     /*  46449 */     // GIR_Coverage, 1868,
     /*  46449 */     GIR_EraseRootFromParent_Done,
     /*  46450 */   // Label 710: @46450
     /*  46450 */   GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(46473), // Rule ID 1482 //
     /*  46455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46458 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46466 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  46466 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i64),
     /*  46471 */     GIR_RootConstrainSelectedInstOperands,
     /*  46472 */     // GIR_Coverage, 1482,
     /*  46472 */     GIR_Done,
     /*  46473 */   // Label 711: @46473
     /*  46473 */   GIM_Reject,
     /*  46474 */ // Label 677: @46474
     /*  46474 */ GIM_Reject,
     /*  46475 */ // Label 595: @46475
     /*  46475 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(47965),
     /*  46480 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46483 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  46486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46490 */   GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(46622), // Rule ID 5441 //
     /*  46495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46519 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46524 */     // MIs[1] Operand 2
     /*  46524 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46535 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46539 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46543 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46547 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46551 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46555 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46559 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46564 */     // MIs[3] Operand 2
     /*  46564 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46575 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46577 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  46577 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  46580 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  46584 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46589 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46593 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46597 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46604 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46611 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46616 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46621 */     // GIR_Coverage, 5441,
     /*  46621 */     GIR_EraseRootFromParent_Done,
     /*  46622 */   // Label 713: @46622
     /*  46622 */   GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(46754), // Rule ID 5440 //
     /*  46627 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46631 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46635 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46639 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46643 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46647 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46651 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46656 */     // MIs[1] Operand 2
     /*  46656 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46667 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46671 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46675 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46679 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46683 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46687 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46691 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46696 */     // MIs[3] Operand 2
     /*  46696 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46707 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46709 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  46709 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  46712 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  46716 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46721 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46725 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46729 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46736 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46743 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46748 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46753 */     // GIR_Coverage, 5440,
     /*  46753 */     GIR_EraseRootFromParent_Done,
     /*  46754 */   // Label 714: @46754
     /*  46754 */   GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(46886), // Rule ID 5456 //
     /*  46759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46763 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46767 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46771 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46775 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46779 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46783 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46788 */     // MIs[1] Operand 2
     /*  46788 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46799 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46803 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46807 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46811 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46815 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46819 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46823 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46828 */     // MIs[3] Operand 2
     /*  46828 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46839 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46841 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  46841 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  46844 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i8_v8i16),
     /*  46848 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46853 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46857 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46861 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46868 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46875 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46880 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46885 */     // GIR_Coverage, 5456,
     /*  46885 */     GIR_EraseRootFromParent_Done,
     /*  46886 */   // Label 715: @46886
     /*  46886 */   GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(47018), // Rule ID 5439 //
     /*  46891 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46895 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46899 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46903 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46907 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46911 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46915 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46920 */     // MIs[1] Operand 2
     /*  46920 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46931 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46935 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46939 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  46943 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46947 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46951 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  46955 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46960 */     // MIs[3] Operand 2
     /*  46960 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46971 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46973 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  46973 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  46976 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  46980 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46985 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46989 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46993 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47000 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47007 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47012 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47017 */     // GIR_Coverage, 5439,
     /*  47017 */     GIR_EraseRootFromParent_Done,
     /*  47018 */   // Label 716: @47018
     /*  47018 */   GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(47150), // Rule ID 5438 //
     /*  47023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  47027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47031 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47035 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47039 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  47043 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47047 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47052 */     // MIs[1] Operand 2
     /*  47052 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47063 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  47067 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47071 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47075 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  47079 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  47083 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47087 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47092 */     // MIs[3] Operand 2
     /*  47092 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  47103 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  47105 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47105 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47108 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  47112 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47117 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  47121 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  47125 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47132 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47139 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47144 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47149 */     // GIR_Coverage, 5438,
     /*  47149 */     GIR_EraseRootFromParent_Done,
     /*  47150 */   // Label 717: @47150
     /*  47150 */   GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(47309), // Rule ID 5411 //
     /*  47155 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47159 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47163 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47167 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47171 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47175 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  47179 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47183 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  47187 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47192 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47197 */     // MIs[1] Operand 2
     /*  47197 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47208 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47210 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLSLv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47210 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  47213 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47217 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47222 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47224 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  47227 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47231 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47236 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47239 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  47243 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47246 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47251 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47256 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47261 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47264 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i8_v8i16),
     /*  47268 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47273 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47276 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  47280 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  47284 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47291 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47308 */     // GIR_Coverage, 5411,
     /*  47308 */     GIR_EraseRootFromParent_Done,
     /*  47309 */   // Label 718: @47309
     /*  47309 */   GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(47468), // Rule ID 5408 //
     /*  47314 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47326 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47330 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47334 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  47338 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47342 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  47346 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47351 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47356 */     // MIs[1] Operand 2
     /*  47356 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47367 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47369 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLSLv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47369 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  47372 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47376 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47381 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47383 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  47386 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47390 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47395 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47398 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  47402 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47405 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47410 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47415 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47420 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47423 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i8_v8i16),
     /*  47427 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47432 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47435 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  47439 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  47443 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47450 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47457 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47462 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47467 */     // GIR_Coverage, 5408,
     /*  47467 */     GIR_EraseRootFromParent_Done,
     /*  47468 */   // Label 719: @47468
     /*  47468 */   GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(47614), // Rule ID 5451 //
     /*  47473 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47485 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47489 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47493 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  47497 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47501 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47506 */     // MIs[1] Operand 2
     /*  47506 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47517 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47519 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47519 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  47522 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47526 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47531 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47533 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  47536 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47540 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47545 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47548 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47552 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47555 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47560 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47565 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47570 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47573 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  47577 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47582 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47585 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47589 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47596 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47603 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47608 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47613 */     // GIR_Coverage, 5451,
     /*  47613 */     GIR_EraseRootFromParent_Done,
     /*  47614 */   // Label 720: @47614
     /*  47614 */   GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(47760), // Rule ID 5459 //
     /*  47619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47635 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47639 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  47643 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47647 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47652 */     // MIs[1] Operand 2
     /*  47652 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47663 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47665 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SSUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47665 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  47668 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47672 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47677 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47679 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  47682 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47686 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47691 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47694 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47698 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47701 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47706 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47711 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47716 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47719 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i8_v8i16),
     /*  47723 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47728 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47731 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47735 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47742 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47749 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47754 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47759 */     // GIR_Coverage, 5459,
     /*  47759 */     GIR_EraseRootFromParent_Done,
     /*  47760 */   // Label 721: @47760
     /*  47760 */   GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(47906), // Rule ID 5450 //
     /*  47765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  47781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  47789 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  47793 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47798 */     // MIs[1] Operand 2
     /*  47798 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47809 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47811 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  47811 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  47814 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47818 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47823 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47825 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  47828 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47832 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47837 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47840 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47844 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47847 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47852 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47857 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47862 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  47865 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  47869 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47874 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47877 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47881 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47888 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47895 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47905 */     // GIR_Coverage, 5450,
     /*  47905 */     GIR_EraseRootFromParent_Done,
     /*  47906 */   // Label 722: @47906
     /*  47906 */   GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(47941), // Rule ID 971 //
     /*  47911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  47918 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  47924 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  47926 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47930 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  47932 */     // (sub:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn)  =>  (NEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /*  47932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i16),
     /*  47935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  47937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  47939 */     GIR_RootConstrainSelectedInstOperands,
     /*  47940 */     // GIR_Coverage, 971,
     /*  47940 */     GIR_EraseRootFromParent_Done,
     /*  47941 */   // Label 723: @47941
     /*  47941 */   GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(47964), // Rule ID 1478 //
     /*  47946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47949 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47957 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  47957 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i16),
     /*  47962 */     GIR_RootConstrainSelectedInstOperands,
     /*  47963 */     // GIR_Coverage, 1478,
     /*  47963 */     GIR_Done,
     /*  47964 */   // Label 724: @47964
     /*  47964 */   GIM_Reject,
     /*  47965 */ // Label 712: @47965
     /*  47965 */ GIM_Reject,
     /*  47966 */ // Label 596: @47966
     /*  47966 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(50425),
     /*  47971 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47974 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  47977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47981 */   GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(48095), // Rule ID 2049 //
     /*  47986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47989 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47993 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47997 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48001 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48005 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48009 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  48013 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48017 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48021 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48025 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48029 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48033 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48037 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48042 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48046 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48050 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48054 */     // MIs[4] Operand 1
     /*  48054 */     // No operand predicates
     /*  48054 */     // MIs[2] Operand 2
     /*  48054 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  48065 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48067 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48074 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_indexed),
     /*  48077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48079 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48090 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48093 */     GIR_RootConstrainSelectedInstOperands,
     /*  48094 */     // GIR_Coverage, 2049,
     /*  48094 */     GIR_EraseRootFromParent_Done,
     /*  48095 */   // Label 726: @48095
     /*  48095 */   GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(48209), // Rule ID 13797 //
     /*  48100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48103 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48115 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48119 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48127 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48131 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48135 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48139 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48143 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48147 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48151 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48156 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48160 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48164 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48168 */     // MIs[4] Operand 1
     /*  48168 */     // No operand predicates
     /*  48168 */     // MIs[2] Operand 2
     /*  48168 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  48179 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48181 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48188 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (SMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_indexed),
     /*  48191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48193 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48200 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48204 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48207 */     GIR_RootConstrainSelectedInstOperands,
     /*  48208 */     // GIR_Coverage, 13797,
     /*  48208 */     GIR_EraseRootFromParent_Done,
     /*  48209 */   // Label 727: @48209
     /*  48209 */   GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(48323), // Rule ID 2101 //
     /*  48214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48217 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  48229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48233 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48237 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  48241 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48245 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48249 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48253 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48257 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48261 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48265 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48270 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48274 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48278 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48282 */     // MIs[4] Operand 1
     /*  48282 */     // No operand predicates
     /*  48282 */     // MIs[2] Operand 2
     /*  48282 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  48293 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48295 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48302 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (UMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_indexed),
     /*  48305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48307 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48318 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48321 */     GIR_RootConstrainSelectedInstOperands,
     /*  48322 */     // GIR_Coverage, 2101,
     /*  48322 */     GIR_EraseRootFromParent_Done,
     /*  48323 */   // Label 728: @48323
     /*  48323 */   GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(48437), // Rule ID 13833 //
     /*  48328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48331 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48335 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48339 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  48343 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48347 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48351 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48355 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48359 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48363 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48367 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48371 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48375 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48379 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48384 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48388 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48392 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48396 */     // MIs[4] Operand 1
     /*  48396 */     // No operand predicates
     /*  48396 */     // MIs[2] Operand 2
     /*  48396 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  48407 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48409 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48416 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (UMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_indexed),
     /*  48419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48421 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48432 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48435 */     GIR_RootConstrainSelectedInstOperands,
     /*  48436 */     // GIR_Coverage, 13833,
     /*  48436 */     GIR_EraseRootFromParent_Done,
     /*  48437 */   // Label 729: @48437
     /*  48437 */   GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(48502), // Rule ID 1851 //
     /*  48442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48445 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48449 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48453 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48457 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48461 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48465 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48469 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48471 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48478 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48485 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  48485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  48488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48500 */     GIR_RootConstrainSelectedInstOperands,
     /*  48501 */     // GIR_Coverage, 1851,
     /*  48501 */     GIR_EraseRootFromParent_Done,
     /*  48502 */   // Label 730: @48502
     /*  48502 */   GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(48567), // Rule ID 1850 //
     /*  48507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48530 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48534 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48536 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48543 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48550 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  48550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  48553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48565 */     GIR_RootConstrainSelectedInstOperands,
     /*  48566 */     // GIR_Coverage, 1850,
     /*  48566 */     GIR_EraseRootFromParent_Done,
     /*  48567 */   // Label 731: @48567
     /*  48567 */   GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(48632), // Rule ID 1761 //
     /*  48572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48575 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48579 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  48583 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48587 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48591 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  48595 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48599 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48601 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48608 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48615 */     // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SSUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  48615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i16_v4i32),
     /*  48618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48630 */     GIR_RootConstrainSelectedInstOperands,
     /*  48631 */     // GIR_Coverage, 1761,
     /*  48631 */     GIR_EraseRootFromParent_Done,
     /*  48632 */   // Label 732: @48632
     /*  48632 */   GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(48697), // Rule ID 1849 //
     /*  48637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48660 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48666 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48673 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48680 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  48680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  48683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48695 */     GIR_RootConstrainSelectedInstOperands,
     /*  48696 */     // GIR_Coverage, 1849,
     /*  48696 */     GIR_EraseRootFromParent_Done,
     /*  48697 */   // Label 733: @48697
     /*  48697 */   GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(48762), // Rule ID 1848 //
     /*  48702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48717 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48721 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48725 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48729 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48731 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48738 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  48745 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  48745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  48748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48760 */     GIR_RootConstrainSelectedInstOperands,
     /*  48761 */     // GIR_Coverage, 1848,
     /*  48761 */     GIR_EraseRootFromParent_Done,
     /*  48762 */   // Label 734: @48762
     /*  48762 */   GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(48873), // Rule ID 13795 //
     /*  48767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48770 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48782 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48786 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48798 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48802 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48806 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48810 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48814 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48818 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48823 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48827 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48831 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48835 */     // MIs[4] Operand 1
     /*  48835 */     // No operand predicates
     /*  48835 */     // MIs[2] Operand 2
     /*  48835 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48846 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48851 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48853 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  48856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48858 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  48864 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48868 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48871 */     GIR_RootConstrainSelectedInstOperands,
     /*  48872 */     // GIR_Coverage, 13795,
     /*  48872 */     GIR_EraseRootFromParent_Done,
     /*  48873 */   // Label 735: @48873
     /*  48873 */   GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(48984), // Rule ID 2047 //
     /*  48878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48881 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48885 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48889 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48893 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  48897 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  48901 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  48910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48914 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48918 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48922 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  48926 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  48930 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48934 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  48939 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48943 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48947 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  48951 */     // MIs[4] Operand 1
     /*  48951 */     // No operand predicates
     /*  48951 */     // MIs[2] Operand 2
     /*  48951 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48962 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48964 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  48967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48969 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  48975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48979 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48982 */     GIR_RootConstrainSelectedInstOperands,
     /*  48983 */     // GIR_Coverage, 2047,
     /*  48983 */     GIR_EraseRootFromParent_Done,
     /*  48984 */   // Label 736: @48984
     /*  48984 */   GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(49095), // Rule ID 13831 //
     /*  48989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  49016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  49020 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49024 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  49028 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49032 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49036 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  49040 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49045 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  49049 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49053 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49057 */     // MIs[4] Operand 1
     /*  49057 */     // No operand predicates
     /*  49057 */     // MIs[2] Operand 2
     /*  49057 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  49068 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49073 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  49075 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  49078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49080 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  49086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  49090 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  49093 */     GIR_RootConstrainSelectedInstOperands,
     /*  49094 */     // GIR_Coverage, 13831,
     /*  49094 */     GIR_EraseRootFromParent_Done,
     /*  49095 */   // Label 737: @49095
     /*  49095 */   GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(49206), // Rule ID 2099 //
     /*  49100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49103 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49115 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49119 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49123 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49128 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  49132 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  49136 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49140 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  49144 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49148 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49152 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  49156 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49161 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  49165 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49169 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49173 */     // MIs[4] Operand 1
     /*  49173 */     // No operand predicates
     /*  49173 */     // MIs[2] Operand 2
     /*  49173 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  49184 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  49186 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  49189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49191 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49193 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49197 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  49201 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  49204 */     GIR_RootConstrainSelectedInstOperands,
     /*  49205 */     // GIR_Coverage, 2099,
     /*  49205 */     GIR_EraseRootFromParent_Done,
     /*  49206 */   // Label 738: @49206
     /*  49206 */   GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(49269), // Rule ID 1737 //
     /*  49211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49214 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  49226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49234 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49236 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49243 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49250 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  49250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_v4i32),
     /*  49253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49255 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  49262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  49267 */     GIR_RootConstrainSelectedInstOperands,
     /*  49268 */     // GIR_Coverage, 1737,
     /*  49268 */     GIR_EraseRootFromParent_Done,
     /*  49269 */   // Label 739: @49269
     /*  49269 */   GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(49332), // Rule ID 1827 //
     /*  49274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49277 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49281 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49285 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49289 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49293 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49297 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49299 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49306 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49313 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  49313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_v4i32),
     /*  49316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49318 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  49325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  49330 */     GIR_RootConstrainSelectedInstOperands,
     /*  49331 */     // GIR_Coverage, 1827,
     /*  49331 */     GIR_EraseRootFromParent_Done,
     /*  49332 */   // Label 740: @49332
     /*  49332 */   GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(49420), // Rule ID 13796 //
     /*  49337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49340 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49348 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  49352 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49356 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49360 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  49364 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49368 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49372 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49376 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49381 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49385 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49389 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49393 */     // MIs[3] Operand 1
     /*  49393 */     // No operand predicates
     /*  49393 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49398 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49400 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  49403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49405 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  49411 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49415 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49418 */     GIR_RootConstrainSelectedInstOperands,
     /*  49419 */     // GIR_Coverage, 13796,
     /*  49419 */     GIR_EraseRootFromParent_Done,
     /*  49420 */   // Label 741: @49420
     /*  49420 */   GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(49508), // Rule ID 2048 //
     /*  49425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49428 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  49440 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49444 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49448 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49453 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  49457 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49461 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49465 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49469 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49474 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49478 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49482 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49486 */     // MIs[3] Operand 1
     /*  49486 */     // No operand predicates
     /*  49486 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49488 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  49491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49506 */     GIR_RootConstrainSelectedInstOperands,
     /*  49507 */     // GIR_Coverage, 2048,
     /*  49507 */     GIR_EraseRootFromParent_Done,
     /*  49508 */   // Label 742: @49508
     /*  49508 */   GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(49596), // Rule ID 13832 //
     /*  49513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49516 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49528 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49532 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49536 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  49540 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49544 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49548 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49552 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49557 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49561 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49565 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49569 */     // MIs[3] Operand 1
     /*  49569 */     // No operand predicates
     /*  49569 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49574 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49576 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  49579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49581 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  49587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49591 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49594 */     GIR_RootConstrainSelectedInstOperands,
     /*  49595 */     // GIR_Coverage, 13832,
     /*  49595 */     GIR_EraseRootFromParent_Done,
     /*  49596 */   // Label 743: @49596
     /*  49596 */   GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(49684), // Rule ID 2100 //
     /*  49601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49604 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49616 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49620 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  49624 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49629 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  49633 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  49637 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  49641 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49645 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  49650 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49654 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49658 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  49662 */     // MIs[3] Operand 1
     /*  49662 */     // No operand predicates
     /*  49662 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49664 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  49667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49669 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49679 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49682 */     GIR_RootConstrainSelectedInstOperands,
     /*  49683 */     // GIR_Coverage, 2100,
     /*  49683 */     GIR_EraseRootFromParent_Done,
     /*  49684 */   // Label 744: @49684
     /*  49684 */   GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(49731), // Rule ID 1867 //
     /*  49689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49692 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49708 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49710 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49717 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  49717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
     /*  49720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49722 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49729 */     GIR_RootConstrainSelectedInstOperands,
     /*  49730 */     // GIR_Coverage, 1867,
     /*  49730 */     GIR_EraseRootFromParent_Done,
     /*  49731 */   // Label 745: @49731
     /*  49731 */   GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(49778), // Rule ID 1767 //
     /*  49736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49739 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49755 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49757 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49764 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SSUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  49764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i16_v4i32),
     /*  49767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49769 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49776 */     GIR_RootConstrainSelectedInstOperands,
     /*  49777 */     // GIR_Coverage, 1767,
     /*  49777 */     GIR_EraseRootFromParent_Done,
     /*  49778 */   // Label 746: @49778
     /*  49778 */   GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(49825), // Rule ID 1866 //
     /*  49783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49790 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49794 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49798 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49802 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49804 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  49811 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  49811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
     /*  49814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49816 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49823 */     GIR_RootConstrainSelectedInstOperands,
     /*  49824 */     // GIR_Coverage, 1866,
     /*  49824 */     GIR_EraseRootFromParent_Done,
     /*  49825 */   // Label 747: @49825
     /*  49825 */   GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(49884), // Rule ID 1847 //
     /*  49830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49850 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49854 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49858 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49862 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49867 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49869 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  49869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  49872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49882 */     GIR_RootConstrainSelectedInstOperands,
     /*  49883 */     // GIR_Coverage, 1847,
     /*  49883 */     GIR_EraseRootFromParent_Done,
     /*  49884 */   // Label 748: @49884
     /*  49884 */   GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(49943), // Rule ID 1846 //
     /*  49889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49896 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49900 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49904 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49909 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49913 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49917 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49921 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49926 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49928 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  49928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  49931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49933 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49941 */     GIR_RootConstrainSelectedInstOperands,
     /*  49942 */     // GIR_Coverage, 1846,
     /*  49942 */     GIR_EraseRootFromParent_Done,
     /*  49943 */   // Label 749: @49943
     /*  49943 */   GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(50002), // Rule ID 1760 //
     /*  49948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49963 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49968 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49976 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  49980 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49985 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49987 */     // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  49987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i16_v4i32),
     /*  49990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  50000 */     GIR_RootConstrainSelectedInstOperands,
     /*  50001 */     // GIR_Coverage, 1760,
     /*  50001 */     GIR_EraseRootFromParent_Done,
     /*  50002 */   // Label 750: @50002
     /*  50002 */   GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(50061), // Rule ID 1845 //
     /*  50007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50035 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50044 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50046 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  50049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  50055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  50059 */     GIR_RootConstrainSelectedInstOperands,
     /*  50060 */     // GIR_Coverage, 1845,
     /*  50060 */     GIR_EraseRootFromParent_Done,
     /*  50061 */   // Label 751: @50061
     /*  50061 */   GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(50120), // Rule ID 1844 //
     /*  50066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50069 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50073 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50077 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50081 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50086 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50090 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50094 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50098 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50105 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  50108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50110 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  50114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  50118 */     GIR_RootConstrainSelectedInstOperands,
     /*  50119 */     // GIR_Coverage, 1844,
     /*  50119 */     GIR_EraseRootFromParent_Done,
     /*  50120 */   // Label 752: @50120
     /*  50120 */   GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(50155), // Rule ID 974 //
     /*  50125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50128 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50132 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  50138 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  50140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50144 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50146 */     // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn)  =>  (NEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /*  50146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i32),
     /*  50149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50151 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  50153 */     GIR_RootConstrainSelectedInstOperands,
     /*  50154 */     // GIR_Coverage, 974,
     /*  50154 */     GIR_EraseRootFromParent_Done,
     /*  50155 */   // Label 753: @50155
     /*  50155 */   GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(50212), // Rule ID 1736 //
     /*  50160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50163 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  50175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50179 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  50183 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50188 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50193 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50195 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_v4i32),
     /*  50198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50200 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  50202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  50206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  50210 */     GIR_RootConstrainSelectedInstOperands,
     /*  50211 */     // GIR_Coverage, 1736,
     /*  50211 */     GIR_EraseRootFromParent_Done,
     /*  50212 */   // Label 754: @50212
     /*  50212 */   GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(50269), // Rule ID 1826 //
     /*  50217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50220 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  50232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  50240 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50245 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50250 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50252 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_v4i32),
     /*  50255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50257 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  50259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  50263 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  50267 */     GIR_RootConstrainSelectedInstOperands,
     /*  50268 */     // GIR_Coverage, 1826,
     /*  50268 */     GIR_EraseRootFromParent_Done,
     /*  50269 */   // Label 755: @50269
     /*  50269 */   GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(50313), // Rule ID 1865 //
     /*  50274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50277 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50281 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50285 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50289 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50293 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50298 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50300 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  50303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50305 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  50307 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  50311 */     GIR_RootConstrainSelectedInstOperands,
     /*  50312 */     // GIR_Coverage, 1865,
     /*  50312 */     GIR_EraseRootFromParent_Done,
     /*  50313 */   // Label 756: @50313
     /*  50313 */   GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(50357), // Rule ID 1766 //
     /*  50318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  50333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50337 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50342 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50344 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i16_v4i32),
     /*  50347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50349 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  50351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  50355 */     GIR_RootConstrainSelectedInstOperands,
     /*  50356 */     // GIR_Coverage, 1766,
     /*  50356 */     GIR_EraseRootFromParent_Done,
     /*  50357 */   // Label 757: @50357
     /*  50357 */   GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(50401), // Rule ID 1864 //
     /*  50362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50386 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50388 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  50388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  50391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50393 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  50395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  50399 */     GIR_RootConstrainSelectedInstOperands,
     /*  50400 */     // GIR_Coverage, 1864,
     /*  50400 */     GIR_EraseRootFromParent_Done,
     /*  50401 */   // Label 758: @50401
     /*  50401 */   GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(50424), // Rule ID 1481 //
     /*  50406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50409 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50417 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  50417 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i32),
     /*  50422 */     GIR_RootConstrainSelectedInstOperands,
     /*  50423 */     // GIR_Coverage, 1481,
     /*  50423 */     GIR_Done,
     /*  50424 */   // Label 759: @50424
     /*  50424 */   GIM_Reject,
     /*  50425 */ // Label 725: @50425
     /*  50425 */ GIM_Reject,
     /*  50426 */ // Label 597: @50426
     /*  50426 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(50500),
     /*  50431 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50434 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  50437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50441 */   GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(50476), // Rule ID 969 //
     /*  50446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50453 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  50459 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  50461 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50465 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50467 */     // (sub:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn)  =>  (NEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /*  50467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i8),
     /*  50470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  50474 */     GIR_RootConstrainSelectedInstOperands,
     /*  50475 */     // GIR_Coverage, 969,
     /*  50475 */     GIR_EraseRootFromParent_Done,
     /*  50476 */   // Label 761: @50476
     /*  50476 */   GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(50499), // Rule ID 1476 //
     /*  50481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50484 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50492 */     // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  50492 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i8),
     /*  50497 */     GIR_RootConstrainSelectedInstOperands,
     /*  50498 */     // GIR_Coverage, 1476,
     /*  50498 */     GIR_Done,
     /*  50499 */   // Label 762: @50499
     /*  50499 */   GIM_Reject,
     /*  50500 */ // Label 760: @50500
     /*  50500 */ GIM_Reject,
     /*  50501 */ // Label 598: @50501
     /*  50501 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(51708),
     /*  50506 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50509 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  50512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50516 */   GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(50581), // Rule ID 1843 //
     /*  50521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50524 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50528 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50532 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50536 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50540 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50544 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50548 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50550 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50557 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50564 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  50567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50579 */     GIR_RootConstrainSelectedInstOperands,
     /*  50580 */     // GIR_Coverage, 1843,
     /*  50580 */     GIR_EraseRootFromParent_Done,
     /*  50581 */   // Label 764: @50581
     /*  50581 */   GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(50646), // Rule ID 1842 //
     /*  50586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50597 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50609 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50613 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50615 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50622 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50629 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  50632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50644 */     GIR_RootConstrainSelectedInstOperands,
     /*  50645 */     // GIR_Coverage, 1842,
     /*  50645 */     GIR_EraseRootFromParent_Done,
     /*  50646 */   // Label 765: @50646
     /*  50646 */   GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(50711), // Rule ID 1759 //
     /*  50651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  50662 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50666 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50670 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  50674 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50678 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50680 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50687 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50694 */     // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SSUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv16i8_v8i16),
     /*  50697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50709 */     GIR_RootConstrainSelectedInstOperands,
     /*  50710 */     // GIR_Coverage, 1759,
     /*  50710 */     GIR_EraseRootFromParent_Done,
     /*  50711 */   // Label 766: @50711
     /*  50711 */   GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(50776), // Rule ID 1841 //
     /*  50716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50719 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50723 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50727 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50731 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50735 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50739 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50743 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50745 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50752 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50759 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  50762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50774 */     GIR_RootConstrainSelectedInstOperands,
     /*  50775 */     // GIR_Coverage, 1841,
     /*  50775 */     GIR_EraseRootFromParent_Done,
     /*  50776 */   // Label 767: @50776
     /*  50776 */   GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(50841), // Rule ID 1840 //
     /*  50781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  50800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50804 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50808 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50810 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50817 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50824 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  50827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  50829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50839 */     GIR_RootConstrainSelectedInstOperands,
     /*  50840 */     // GIR_Coverage, 1840,
     /*  50840 */     GIR_EraseRootFromParent_Done,
     /*  50841 */   // Label 768: @50841
     /*  50841 */   GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(50904), // Rule ID 1735 //
     /*  50846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50849 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  50861 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50865 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  50869 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50871 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50878 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50885 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv16i8_v8i16),
     /*  50888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50890 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  50892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50902 */     GIR_RootConstrainSelectedInstOperands,
     /*  50903 */     // GIR_Coverage, 1735,
     /*  50903 */     GIR_EraseRootFromParent_Done,
     /*  50904 */   // Label 769: @50904
     /*  50904 */   GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(50967), // Rule ID 1825 //
     /*  50909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50912 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  50924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50928 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  50932 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50934 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50941 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  50948 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  50948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv16i8_v8i16),
     /*  50951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50953 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  50955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  50960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  50965 */     GIR_RootConstrainSelectedInstOperands,
     /*  50966 */     // GIR_Coverage, 1825,
     /*  50966 */     GIR_EraseRootFromParent_Done,
     /*  50967 */   // Label 770: @50967
     /*  50967 */   GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(51014), // Rule ID 1863 //
     /*  50972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  50975 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50979 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50983 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50987 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50991 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  50993 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  51000 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  51000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
     /*  51003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51005 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  51012 */     GIR_RootConstrainSelectedInstOperands,
     /*  51013 */     // GIR_Coverage, 1863,
     /*  51013 */     GIR_EraseRootFromParent_Done,
     /*  51014 */   // Label 771: @51014
     /*  51014 */   GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(51061), // Rule ID 1765 //
     /*  51019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51022 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51026 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51030 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  51034 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51038 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51040 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  51047 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SSUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  51047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv16i8_v8i16),
     /*  51050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51052 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  51059 */     GIR_RootConstrainSelectedInstOperands,
     /*  51060 */     // GIR_Coverage, 1765,
     /*  51060 */     GIR_EraseRootFromParent_Done,
     /*  51061 */   // Label 772: @51061
     /*  51061 */   GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(51108), // Rule ID 1862 //
     /*  51066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51069 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51077 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51081 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51087 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  51094 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  51094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
     /*  51097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51099 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  51106 */     GIR_RootConstrainSelectedInstOperands,
     /*  51107 */     // GIR_Coverage, 1862,
     /*  51107 */     GIR_EraseRootFromParent_Done,
     /*  51108 */   // Label 773: @51108
     /*  51108 */   GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(51167), // Rule ID 1839 //
     /*  51113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51128 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51133 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  51137 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51141 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51145 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51150 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51152 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  51155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51157 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51161 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51165 */     GIR_RootConstrainSelectedInstOperands,
     /*  51166 */     // GIR_Coverage, 1839,
     /*  51166 */     GIR_EraseRootFromParent_Done,
     /*  51167 */   // Label 774: @51167
     /*  51167 */   GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(51226), // Rule ID 1838 //
     /*  51172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51175 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51179 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51183 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51187 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  51196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51200 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51204 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51209 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51211 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  51214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51224 */     GIR_RootConstrainSelectedInstOperands,
     /*  51225 */     // GIR_Coverage, 1838,
     /*  51225 */     GIR_EraseRootFromParent_Done,
     /*  51226 */   // Label 775: @51226
     /*  51226 */   GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(51285), // Rule ID 1758 //
     /*  51231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  51242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51246 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51251 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  51255 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  51259 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51263 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51268 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51270 */     // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i8_v8i16),
     /*  51273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51275 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51283 */     GIR_RootConstrainSelectedInstOperands,
     /*  51284 */     // GIR_Coverage, 1758,
     /*  51284 */     GIR_EraseRootFromParent_Done,
     /*  51285 */   // Label 776: @51285
     /*  51285 */   GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(51344), // Rule ID 1837 //
     /*  51290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51293 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51297 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51301 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51305 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51310 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  51314 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51318 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51322 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51327 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51329 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  51332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51334 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51338 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51342 */     GIR_RootConstrainSelectedInstOperands,
     /*  51343 */     // GIR_Coverage, 1837,
     /*  51343 */     GIR_EraseRootFromParent_Done,
     /*  51344 */   // Label 777: @51344
     /*  51344 */   GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(51403), // Rule ID 1836 //
     /*  51349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51352 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51356 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51360 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51364 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51369 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  51373 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51377 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51381 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51386 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51388 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  51391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51393 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51401 */     GIR_RootConstrainSelectedInstOperands,
     /*  51402 */     // GIR_Coverage, 1836,
     /*  51402 */     GIR_EraseRootFromParent_Done,
     /*  51403 */   // Label 778: @51403
     /*  51403 */   GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(51438), // Rule ID 972 //
     /*  51408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51415 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  51421 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  51423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51427 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51429 */     // (sub:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn)  =>  (NEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /*  51429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i16),
     /*  51432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51434 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  51436 */     GIR_RootConstrainSelectedInstOperands,
     /*  51437 */     // GIR_Coverage, 972,
     /*  51437 */     GIR_EraseRootFromParent_Done,
     /*  51438 */   // Label 779: @51438
     /*  51438 */   GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(51495), // Rule ID 1734 //
     /*  51443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  51458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51462 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  51466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51471 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51476 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51478 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i8_v8i16),
     /*  51481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51483 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51485 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51489 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  51493 */     GIR_RootConstrainSelectedInstOperands,
     /*  51494 */     // GIR_Coverage, 1734,
     /*  51494 */     GIR_EraseRootFromParent_Done,
     /*  51495 */   // Label 780: @51495
     /*  51495 */   GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(51552), // Rule ID 1824 //
     /*  51500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51503 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51507 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51511 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  51515 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51519 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  51523 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51528 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51533 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51535 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i8_v8i16),
     /*  51538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51540 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  51546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  51550 */     GIR_RootConstrainSelectedInstOperands,
     /*  51551 */     // GIR_Coverage, 1824,
     /*  51551 */     GIR_EraseRootFromParent_Done,
     /*  51552 */   // Label 781: @51552
     /*  51552 */   GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(51596), // Rule ID 1861 //
     /*  51557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51560 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51564 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51568 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51572 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51581 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51583 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  51586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51588 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  51594 */     GIR_RootConstrainSelectedInstOperands,
     /*  51595 */     // GIR_Coverage, 1861,
     /*  51595 */     GIR_EraseRootFromParent_Done,
     /*  51596 */   // Label 782: @51596
     /*  51596 */   GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(51640), // Rule ID 1764 //
     /*  51601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51604 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  51616 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51620 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51625 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51627 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i8_v8i16),
     /*  51630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  51638 */     GIR_RootConstrainSelectedInstOperands,
     /*  51639 */     // GIR_Coverage, 1764,
     /*  51639 */     GIR_EraseRootFromParent_Done,
     /*  51640 */   // Label 783: @51640
     /*  51640 */   GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(51684), // Rule ID 1860 //
     /*  51645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51664 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51669 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51671 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  51671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  51674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51676 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  51678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  51682 */     GIR_RootConstrainSelectedInstOperands,
     /*  51683 */     // GIR_Coverage, 1860,
     /*  51683 */     GIR_EraseRootFromParent_Done,
     /*  51684 */   // Label 784: @51684
     /*  51684 */   GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(51707), // Rule ID 1479 //
     /*  51689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51692 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51696 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51700 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  51700 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i16),
     /*  51705 */     GIR_RootConstrainSelectedInstOperands,
     /*  51706 */     // GIR_Coverage, 1479,
     /*  51706 */     GIR_Done,
     /*  51707 */   // Label 785: @51707
     /*  51707 */   GIM_Reject,
     /*  51708 */ // Label 763: @51708
     /*  51708 */ GIM_Reject,
     /*  51709 */ // Label 599: @51709
     /*  51709 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(51783),
     /*  51714 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  51717 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  51720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51724 */   GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(51759), // Rule ID 970 //
     /*  51729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51736 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  51742 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  51744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51748 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51750 */     // (sub:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn)  =>  (NEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /*  51750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv16i8),
     /*  51753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  51757 */     GIR_RootConstrainSelectedInstOperands,
     /*  51758 */     // GIR_Coverage, 970,
     /*  51758 */     GIR_EraseRootFromParent_Done,
     /*  51759 */   // Label 787: @51759
     /*  51759 */   GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(51782), // Rule ID 1477 //
     /*  51764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51767 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51771 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51775 */     // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  51775 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv16i8),
     /*  51780 */     GIR_RootConstrainSelectedInstOperands,
     /*  51781 */     // GIR_Coverage, 1477,
     /*  51781 */     GIR_Done,
     /*  51782 */   // Label 788: @51782
     /*  51782 */   GIM_Reject,
     /*  51783 */ // Label 786: @51783
     /*  51783 */ GIM_Reject,
     /*  51784 */ // Label 600: @51784
     /*  51784 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(51809), // Rule ID 7537 //
     /*  51789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  51792 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  51795 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  51798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  51802 */   // (sub:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  51802 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_D),
     /*  51807 */   GIR_RootConstrainSelectedInstOperands,
     /*  51808 */   // GIR_Coverage, 7537,
     /*  51808 */   GIR_Done,
     /*  51809 */ // Label 789: @51809
     /*  51809 */ GIM_Reject,
     /*  51810 */ // Label 601: @51810
     /*  51810 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(51835), // Rule ID 7536 //
     /*  51815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  51818 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  51821 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  51824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  51828 */   // (sub:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  51828 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_S),
     /*  51833 */   GIR_RootConstrainSelectedInstOperands,
     /*  51834 */   // GIR_Coverage, 7536,
     /*  51834 */   GIR_Done,
     /*  51835 */ // Label 790: @51835
     /*  51835 */ GIM_Reject,
     /*  51836 */ // Label 602: @51836
     /*  51836 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(51861), // Rule ID 7535 //
     /*  51841 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  51844 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  51847 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  51850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  51854 */   // (sub:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  51854 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_H),
     /*  51859 */   GIR_RootConstrainSelectedInstOperands,
     /*  51860 */   // GIR_Coverage, 7535,
     /*  51860 */   GIR_Done,
     /*  51861 */ // Label 791: @51861
     /*  51861 */ GIM_Reject,
     /*  51862 */ // Label 603: @51862
     /*  51862 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(51887), // Rule ID 7534 //
     /*  51867 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  51870 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  51873 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  51876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  51880 */   // (sub:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  51880 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_B),
     /*  51885 */   GIR_RootConstrainSelectedInstOperands,
     /*  51886 */   // GIR_Coverage, 7534,
     /*  51886 */   GIR_Done,
     /*  51887 */ // Label 792: @51887
     /*  51887 */ GIM_Reject,
     /*  51888 */ // Label 604: @51888
     /*  51888 */ GIM_Reject,
     /*  51889 */ // Label 2: @51889
     /*  51889 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 801*/ GIMT_Encode4(54653),
     /*  51900 */ /*GILLT_s32*//*Label 793*/ GIMT_Encode4(51940),
     /*  51904 */ /*GILLT_s64*//*Label 794*/ GIMT_Encode4(52097), GIMT_Encode4(0),
     /*  51912 */ /*GILLT_v2s32*//*Label 795*/ GIMT_Encode4(53577), GIMT_Encode4(0),
     /*  51920 */ /*GILLT_v4s16*//*Label 796*/ GIMT_Encode4(53915),
     /*  51924 */ /*GILLT_v4s32*//*Label 797*/ GIMT_Encode4(54253),
     /*  51928 */ /*GILLT_v8s8*//*Label 798*/ GIMT_Encode4(54419),
     /*  51932 */ /*GILLT_v8s16*//*Label 799*/ GIMT_Encode4(54453),
     /*  51936 */ /*GILLT_v16s8*//*Label 800*/ GIMT_Encode4(54619),
     /*  51940 */ // Label 793: @51940
     /*  51940 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(52096),
     /*  51945 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  51948 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  51951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  51955 */   GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(52010), // Rule ID 3988 //
     /*  51960 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51964 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  51968 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  51972 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  51976 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  51980 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  51985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  51989 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51991 */     // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm)  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  51991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  51994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52000 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  52002 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52008 */     GIR_RootConstrainSelectedInstOperands,
     /*  52009 */     // GIR_Coverage, 3988,
     /*  52009 */     GIR_EraseRootFromParent_Done,
     /*  52010 */   // Label 803: @52010
     /*  52010 */   GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(52065), // Rule ID 14091 //
     /*  52015 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52019 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52023 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  52027 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  52031 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  52035 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  52039 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52044 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  52046 */     // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  52046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  52049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52055 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  52057 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52063 */     GIR_RootConstrainSelectedInstOperands,
     /*  52064 */     // GIR_Coverage, 14091,
     /*  52064 */     GIR_EraseRootFromParent_Done,
     /*  52065 */   // Label 804: @52065
     /*  52065 */   GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(52095), // Rule ID 3984 //
     /*  52070 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52078 */     // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  52078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDWrrr),
     /*  52081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  52085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  52087 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52093 */     GIR_RootConstrainSelectedInstOperands,
     /*  52094 */     // GIR_Coverage, 3984,
     /*  52094 */     GIR_EraseRootFromParent_Done,
     /*  52095 */   // Label 805: @52095
     /*  52095 */   GIM_Reject,
     /*  52096 */ // Label 802: @52096
     /*  52096 */ GIM_Reject,
     /*  52097 */ // Label 794: @52097
     /*  52097 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(53576),
     /*  52102 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  52105 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  52108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52112 */   GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(52258), // Rule ID 3993 //
     /*  52117 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52121 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  52125 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52129 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  52133 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52138 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /*  52149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  52157 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  52161 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  52165 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52170 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295),
     /*  52181 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52183 */     // (mul:{ *:[i64] } (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, 4294967295:{ *:[i64] }))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  52183 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  52186 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52190 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52195 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  52201 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52206 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52211 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52214 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52218 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52223 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  52229 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52234 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  52242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52244 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52247 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  52250 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52256 */     GIR_RootConstrainSelectedInstOperands,
     /*  52257 */     // GIR_Coverage, 3993,
     /*  52257 */     GIR_EraseRootFromParent_Done,
     /*  52258 */   // Label 807: @52258
     /*  52258 */   GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(52362), // Rule ID 3994 //
     /*  52263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  52271 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52275 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  52279 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52284 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /*  52295 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52299 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52303 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  52307 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52312 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52314 */     // (mul:{ *:[i64] } (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  52314 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52317 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52321 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52326 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  52332 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  52345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52347 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  52354 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52360 */     GIR_RootConstrainSelectedInstOperands,
     /*  52361 */     // GIR_Coverage, 3994,
     /*  52361 */     GIR_EraseRootFromParent_Done,
     /*  52362 */   // Label 808: @52362
     /*  52362 */   GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(52466), // Rule ID 14094 //
     /*  52367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  52379 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52384 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52388 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  52392 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  52396 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  52400 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52405 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295),
     /*  52416 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52418 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  52418 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52421 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52425 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52430 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  52436 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52441 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  52449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52451 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52454 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  52458 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52464 */     GIR_RootConstrainSelectedInstOperands,
     /*  52465 */     // GIR_Coverage, 14094,
     /*  52465 */     GIR_EraseRootFromParent_Done,
     /*  52466 */   // Label 809: @52466
     /*  52466 */   GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(52521), // Rule ID 3989 //
     /*  52471 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52475 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  52479 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52483 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  52487 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  52491 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52496 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52500 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  52502 */     // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm)  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  52502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  52505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52507 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  52513 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52519 */     GIR_RootConstrainSelectedInstOperands,
     /*  52520 */     // GIR_Coverage, 3989,
     /*  52520 */     GIR_EraseRootFromParent_Done,
     /*  52521 */   // Label 810: @52521
     /*  52521 */   GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(52576), // Rule ID 14092 //
     /*  52526 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  52538 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  52546 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  52550 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52555 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  52557 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  52557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  52560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52566 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  52568 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52574 */     GIR_RootConstrainSelectedInstOperands,
     /*  52575 */     // GIR_Coverage, 14092,
     /*  52575 */     GIR_EraseRootFromParent_Done,
     /*  52576 */   // Label 811: @52576
     /*  52576 */   GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(52689), // Rule ID 4000 //
     /*  52581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  52589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52593 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52598 */     // MIs[1] Operand 2
     /*  52598 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  52609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52617 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  52621 */     // MIs[2] Operand 1
     /*  52621 */     // No operand predicates
     /*  52621 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52623 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  52623 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  52626 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  52630 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52635 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  52640 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  52642 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52645 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52649 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52654 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  52660 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52665 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  52673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52675 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  52681 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52687 */     GIR_RootConstrainSelectedInstOperands,
     /*  52688 */     // GIR_Coverage, 4000,
     /*  52688 */     GIR_EraseRootFromParent_Done,
     /*  52689 */   // Label 812: @52689
     /*  52689 */   GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(52764), // Rule ID 3998 //
     /*  52694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  52702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  52706 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52711 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52715 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52719 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  52723 */     // MIs[2] Operand 1
     /*  52723 */     // No operand predicates
     /*  52723 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52725 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  52725 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52728 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  52732 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52737 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  52742 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  52744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  52747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  52753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52756 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52762 */     GIR_RootConstrainSelectedInstOperands,
     /*  52763 */     // GIR_Coverage, 3998,
     /*  52763 */     GIR_EraseRootFromParent_Done,
     /*  52764 */   // Label 813: @52764
     /*  52764 */   GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(52839), // Rule ID 3999 //
     /*  52769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  52781 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52794 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  52798 */     // MIs[2] Operand 1
     /*  52798 */     // No operand predicates
     /*  52798 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52800 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  52800 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52803 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  52807 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52812 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  52817 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  52819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  52822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52824 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  52828 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52831 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52837 */     GIR_RootConstrainSelectedInstOperands,
     /*  52838 */     // GIR_Coverage, 3999,
     /*  52838 */     GIR_EraseRootFromParent_Done,
     /*  52839 */   // Label 814: @52839
     /*  52839 */   GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(52977), // Rule ID 3990 //
     /*  52844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  52852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52856 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52861 */     // MIs[1] Operand 2
     /*  52861 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  52872 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52876 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  52880 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  52884 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52889 */     // MIs[2] Operand 2
     /*  52889 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  52900 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52902 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, i32:{ *:[Other] }))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  52902 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  52905 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52909 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52914 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  52920 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52925 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52930 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  52933 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  52937 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  52942 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  52948 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  52953 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  52961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52963 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  52966 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  52969 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  52975 */     GIR_RootConstrainSelectedInstOperands,
     /*  52976 */     // GIR_Coverage, 3990,
     /*  52976 */     GIR_EraseRootFromParent_Done,
     /*  52977 */   // Label 815: @52977
     /*  52977 */   GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(53077), // Rule ID 3991 //
     /*  52982 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52986 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  52990 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  52994 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  52999 */     // MIs[1] Operand 2
     /*  52999 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  53010 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53014 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53018 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  53022 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53027 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53029 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53029 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  53032 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53036 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53041 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  53047 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53052 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  53060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53062 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  53065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53069 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53075 */     GIR_RootConstrainSelectedInstOperands,
     /*  53076 */     // GIR_Coverage, 3991,
     /*  53076 */     GIR_EraseRootFromParent_Done,
     /*  53077 */   // Label 816: @53077
     /*  53077 */   GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(53177), // Rule ID 14093 //
     /*  53082 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53086 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53090 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  53094 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53099 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53103 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  53107 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  53111 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53116 */     // MIs[2] Operand 2
     /*  53116 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  53127 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53129 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53129 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  53132 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53136 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53141 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  53147 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53152 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  53160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53162 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  53165 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53169 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53175 */     GIR_RootConstrainSelectedInstOperands,
     /*  53176 */     // GIR_Coverage, 14093,
     /*  53176 */     GIR_EraseRootFromParent_Done,
     /*  53177 */   // Label 817: @53177
     /*  53177 */   GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(53239), // Rule ID 3992 //
     /*  53182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  53194 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53199 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53203 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53207 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  53211 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53216 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53218 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  53221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53223 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53231 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53237 */     GIR_RootConstrainSelectedInstOperands,
     /*  53238 */     // GIR_Coverage, 3992,
     /*  53238 */     GIR_EraseRootFromParent_Done,
     /*  53239 */   // Label 818: @53239
     /*  53239 */   GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(53301), // Rule ID 3995 //
     /*  53244 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53248 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53252 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  53256 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53261 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53265 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53269 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  53273 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53278 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53280 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  53283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53285 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53289 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53293 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53299 */     GIR_RootConstrainSelectedInstOperands,
     /*  53300 */     // GIR_Coverage, 3995,
     /*  53300 */     GIR_EraseRootFromParent_Done,
     /*  53301 */   // Label 819: @53301
     /*  53301 */   GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(53378), // Rule ID 4019 //
     /*  53306 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  53311 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53315 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53319 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  53323 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53328 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53330 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53330 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  53333 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53337 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53342 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  53348 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53353 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  53361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53363 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  53366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53370 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53376 */     GIR_RootConstrainSelectedInstOperands,
     /*  53377 */     // GIR_Coverage, 4019,
     /*  53377 */     GIR_EraseRootFromParent_Done,
     /*  53378 */   // Label 820: @53378
     /*  53378 */   GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(53455), // Rule ID 14105 //
     /*  53383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53391 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  53395 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53400 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  53405 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53407 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  53407 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  53410 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53414 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53419 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  53425 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53430 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  53438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53440 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  53443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53447 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53453 */     GIR_RootConstrainSelectedInstOperands,
     /*  53454 */     // GIR_Coverage, 14105,
     /*  53454 */     GIR_EraseRootFromParent_Done,
     /*  53455 */   // Label 821: @53455
     /*  53455 */   GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(53545), // Rule ID 4018 //
     /*  53460 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  53465 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  53470 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  53470 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  53473 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53477 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53482 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  53488 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53493 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53498 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  53501 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  53505 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  53510 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  53516 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  53521 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  53529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53531 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  53534 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  53537 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53543 */     GIR_RootConstrainSelectedInstOperands,
     /*  53544 */     // GIR_Coverage, 4018,
     /*  53544 */     GIR_EraseRootFromParent_Done,
     /*  53545 */   // Label 822: @53545
     /*  53545 */   GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(53575), // Rule ID 3985 //
     /*  53550 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  53558 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  53558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDXrrr),
     /*  53561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53563 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  53567 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  53573 */     GIR_RootConstrainSelectedInstOperands,
     /*  53574 */     // GIR_Coverage, 3985,
     /*  53574 */     GIR_EraseRootFromParent_Done,
     /*  53575 */   // Label 823: @53575
     /*  53575 */   GIM_Reject,
     /*  53576 */ // Label 806: @53576
     /*  53576 */ GIM_Reject,
     /*  53577 */ // Label 795: @53577
     /*  53577 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(53914),
     /*  53582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  53585 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  53588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53592 */   GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(53678), // Rule ID 13774 //
     /*  53597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  53608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53612 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  53616 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  53620 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53624 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53628 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53633 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53637 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53641 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  53645 */     // MIs[3] Operand 1
     /*  53645 */     // No operand predicates
     /*  53645 */     // MIs[1] Operand 2
     /*  53645 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  53656 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53660 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  53662 */     // (mul:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  53665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53667 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  53669 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53673 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  53676 */     GIR_RootConstrainSelectedInstOperands,
     /*  53677 */     // GIR_Coverage, 13774,
     /*  53677 */     GIR_EraseRootFromParent_Done,
     /*  53678 */   // Label 825: @53678
     /*  53678 */   GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(53764), // Rule ID 2038 //
     /*  53683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53686 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  53698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  53706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  53710 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53714 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53718 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53723 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53727 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53731 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  53735 */     // MIs[3] Operand 1
     /*  53735 */     // No operand predicates
     /*  53735 */     // MIs[1] Operand 2
     /*  53735 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  53746 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  53748 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  53751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53753 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53759 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  53762 */     GIR_RootConstrainSelectedInstOperands,
     /*  53763 */     // GIR_Coverage, 2038,
     /*  53763 */     GIR_EraseRootFromParent_Done,
     /*  53764 */   // Label 826: @53764
     /*  53764 */   GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(53827), // Rule ID 13775 //
     /*  53769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53776 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  53780 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53784 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  53788 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53793 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  53797 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53801 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  53805 */     // MIs[2] Operand 1
     /*  53805 */     // No operand predicates
     /*  53805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53809 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53811 */     // (mul:{ *:[v2i32] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  53814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  53818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53822 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  53825 */     GIR_RootConstrainSelectedInstOperands,
     /*  53826 */     // GIR_Coverage, 13775,
     /*  53826 */     GIR_EraseRootFromParent_Done,
     /*  53827 */   // Label 827: @53827
     /*  53827 */   GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(53890), // Rule ID 2039 //
     /*  53832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53835 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53839 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53843 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  53847 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  53851 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  53855 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53860 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  53864 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53868 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  53872 */     // MIs[2] Operand 1
     /*  53872 */     // No operand predicates
     /*  53872 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53874 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  53877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53879 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53885 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  53888 */     GIR_RootConstrainSelectedInstOperands,
     /*  53889 */     // GIR_Coverage, 2039,
     /*  53889 */     GIR_EraseRootFromParent_Done,
     /*  53890 */   // Label 828: @53890
     /*  53890 */   GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(53913), // Rule ID 1356 //
     /*  53895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53906 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  53906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32),
     /*  53911 */     GIR_RootConstrainSelectedInstOperands,
     /*  53912 */     // GIR_Coverage, 1356,
     /*  53912 */     GIR_Done,
     /*  53913 */   // Label 829: @53913
     /*  53913 */   GIM_Reject,
     /*  53914 */ // Label 824: @53914
     /*  53914 */ GIM_Reject,
     /*  53915 */ // Label 796: @53915
     /*  53915 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(54252),
     /*  53920 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53923 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  53926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53930 */   GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(54016), // Rule ID 13771 //
     /*  53935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  53946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  53950 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  53954 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  53958 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  53962 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53966 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  53971 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53975 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53979 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  53983 */     // MIs[3] Operand 1
     /*  53983 */     // No operand predicates
     /*  53983 */     // MIs[1] Operand 2
     /*  53983 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  53994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53998 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  54000 */     // (mul:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  54003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54005 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54011 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  54014 */     GIR_RootConstrainSelectedInstOperands,
     /*  54015 */     // GIR_Coverage, 13771,
     /*  54015 */     GIR_EraseRootFromParent_Done,
     /*  54016 */   // Label 831: @54016
     /*  54016 */   GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(54102), // Rule ID 2035 //
     /*  54021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54024 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  54036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  54044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  54048 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54052 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  54056 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  54061 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  54065 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54069 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  54073 */     // MIs[3] Operand 1
     /*  54073 */     // No operand predicates
     /*  54073 */     // MIs[1] Operand 2
     /*  54073 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  54084 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  54086 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  54089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54091 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54093 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54097 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  54100 */     GIR_RootConstrainSelectedInstOperands,
     /*  54101 */     // GIR_Coverage, 2035,
     /*  54101 */     GIR_EraseRootFromParent_Done,
     /*  54102 */   // Label 832: @54102
     /*  54102 */   GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(54165), // Rule ID 13772 //
     /*  54107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  54118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54122 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54126 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  54131 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54135 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54139 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  54143 */     // MIs[2] Operand 1
     /*  54143 */     // No operand predicates
     /*  54143 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54147 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54149 */     // (mul:{ *:[v4i16] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  54152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54160 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54163 */     GIR_RootConstrainSelectedInstOperands,
     /*  54164 */     // GIR_Coverage, 13772,
     /*  54164 */     GIR_EraseRootFromParent_Done,
     /*  54165 */   // Label 833: @54165
     /*  54165 */   GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(54228), // Rule ID 2036 //
     /*  54170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54173 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  54185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54193 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  54198 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54202 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54206 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  54210 */     // MIs[2] Operand 1
     /*  54210 */     // No operand predicates
     /*  54210 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54212 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  54215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54217 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54223 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54226 */     GIR_RootConstrainSelectedInstOperands,
     /*  54227 */     // GIR_Coverage, 2036,
     /*  54227 */     GIR_EraseRootFromParent_Done,
     /*  54228 */   // Label 834: @54228
     /*  54228 */   GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(54251), // Rule ID 1354 //
     /*  54233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54244 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  54244 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16),
     /*  54249 */     GIR_RootConstrainSelectedInstOperands,
     /*  54250 */     // GIR_Coverage, 1354,
     /*  54250 */     GIR_Done,
     /*  54251 */   // Label 835: @54251
     /*  54251 */   GIM_Reject,
     /*  54252 */ // Label 830: @54252
     /*  54252 */ GIM_Reject,
     /*  54253 */ // Label 797: @54253
     /*  54253 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(54418),
     /*  54258 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  54261 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  54264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54268 */   GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(54331), // Rule ID 13776 //
     /*  54273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54280 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  54284 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  54288 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54292 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54297 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54301 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54305 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  54309 */     // MIs[2] Operand 1
     /*  54309 */     // No operand predicates
     /*  54309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54313 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54315 */     // (mul:{ *:[v4i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4i32] }:$Rn)  =>  (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
     /*  54318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54320 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54326 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54329 */     GIR_RootConstrainSelectedInstOperands,
     /*  54330 */     // GIR_Coverage, 13776,
     /*  54330 */     GIR_EraseRootFromParent_Done,
     /*  54331 */   // Label 837: @54331
     /*  54331 */   GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(54394), // Rule ID 2040 //
     /*  54336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54339 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54343 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54347 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  54351 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  54355 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54359 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54364 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54368 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54372 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  54376 */     // MIs[2] Operand 1
     /*  54376 */     // No operand predicates
     /*  54376 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54378 */     // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
     /*  54381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54383 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54389 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54392 */     GIR_RootConstrainSelectedInstOperands,
     /*  54393 */     // GIR_Coverage, 2040,
     /*  54393 */     GIR_EraseRootFromParent_Done,
     /*  54394 */   // Label 838: @54394
     /*  54394 */   GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(54417), // Rule ID 1357 //
     /*  54399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54402 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54410 */     // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  54410 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32),
     /*  54415 */     GIR_RootConstrainSelectedInstOperands,
     /*  54416 */     // GIR_Coverage, 1357,
     /*  54416 */     GIR_Done,
     /*  54417 */   // Label 839: @54417
     /*  54417 */   GIM_Reject,
     /*  54418 */ // Label 836: @54418
     /*  54418 */ GIM_Reject,
     /*  54419 */ // Label 798: @54419
     /*  54419 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(54452), // Rule ID 1352 //
     /*  54424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54427 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54430 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  54433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54437 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54441 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54445 */   // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54445 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i8),
     /*  54450 */   GIR_RootConstrainSelectedInstOperands,
     /*  54451 */   // GIR_Coverage, 1352,
     /*  54451 */   GIR_Done,
     /*  54452 */ // Label 840: @54452
     /*  54452 */ GIM_Reject,
     /*  54453 */ // Label 799: @54453
     /*  54453 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(54618),
     /*  54458 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54461 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  54464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54468 */   GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(54531), // Rule ID 13773 //
     /*  54473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54476 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54480 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  54484 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54488 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54492 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  54497 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54501 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54505 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  54509 */     // MIs[2] Operand 1
     /*  54509 */     // No operand predicates
     /*  54509 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54513 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54515 */     // (mul:{ *:[v8i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8i16] }:$Rn)  =>  (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
     /*  54518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54520 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54526 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54529 */     GIR_RootConstrainSelectedInstOperands,
     /*  54530 */     // GIR_Coverage, 13773,
     /*  54530 */     GIR_EraseRootFromParent_Done,
     /*  54531 */   // Label 842: @54531
     /*  54531 */   GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(54594), // Rule ID 2037 //
     /*  54536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54539 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54547 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  54551 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  54559 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  54564 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  54568 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  54572 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  54576 */     // MIs[2] Operand 1
     /*  54576 */     // No operand predicates
     /*  54576 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54578 */     // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  54578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
     /*  54581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54583 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  54589 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  54592 */     GIR_RootConstrainSelectedInstOperands,
     /*  54593 */     // GIR_Coverage, 2037,
     /*  54593 */     GIR_EraseRootFromParent_Done,
     /*  54594 */   // Label 843: @54594
     /*  54594 */   GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(54617), // Rule ID 1355 //
     /*  54599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54602 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54606 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54610 */     // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  54610 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16),
     /*  54615 */     GIR_RootConstrainSelectedInstOperands,
     /*  54616 */     // GIR_Coverage, 1355,
     /*  54616 */     GIR_Done,
     /*  54617 */   // Label 844: @54617
     /*  54617 */   GIM_Reject,
     /*  54618 */ // Label 841: @54618
     /*  54618 */ GIM_Reject,
     /*  54619 */ // Label 800: @54619
     /*  54619 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(54652), // Rule ID 1353 //
     /*  54624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  54630 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  54633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54637 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54641 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54645 */   // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54645 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv16i8),
     /*  54650 */   GIR_RootConstrainSelectedInstOperands,
     /*  54651 */   // GIR_Coverage, 1353,
     /*  54651 */   GIR_Done,
     /*  54652 */ // Label 845: @54652
     /*  54652 */ GIM_Reject,
     /*  54653 */ // Label 801: @54653
     /*  54653 */ GIM_Reject,
     /*  54654 */ // Label 3: @54654
     /*  54654 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 848*/ GIMT_Encode4(54735),
     /*  54665 */ /*GILLT_s32*//*Label 846*/ GIMT_Encode4(54673),
     /*  54669 */ /*GILLT_s64*//*Label 847*/ GIMT_Encode4(54704),
     /*  54673 */ // Label 846: @54673
     /*  54673 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(54703), // Rule ID 117 //
     /*  54678 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  54681 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  54684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54688 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54692 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54696 */   // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  54696 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
     /*  54701 */   GIR_RootConstrainSelectedInstOperands,
     /*  54702 */   // GIR_Coverage, 117,
     /*  54702 */   GIR_Done,
     /*  54703 */ // Label 849: @54703
     /*  54703 */ GIM_Reject,
     /*  54704 */ // Label 847: @54704
     /*  54704 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(54734), // Rule ID 118 //
     /*  54709 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  54712 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  54715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54719 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54723 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54727 */   // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  54727 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
     /*  54732 */   GIR_RootConstrainSelectedInstOperands,
     /*  54733 */   // GIR_Coverage, 118,
     /*  54733 */   GIR_Done,
     /*  54734 */ // Label 850: @54734
     /*  54734 */ GIM_Reject,
     /*  54735 */ // Label 848: @54735
     /*  54735 */ GIM_Reject,
     /*  54736 */ // Label 4: @54736
     /*  54736 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 853*/ GIMT_Encode4(54817),
     /*  54747 */ /*GILLT_s32*//*Label 851*/ GIMT_Encode4(54755),
     /*  54751 */ /*GILLT_s64*//*Label 852*/ GIMT_Encode4(54786),
     /*  54755 */ // Label 851: @54755
     /*  54755 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(54785), // Rule ID 115 //
     /*  54760 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  54763 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  54766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54770 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54774 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54778 */   // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  54778 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
     /*  54783 */   GIR_RootConstrainSelectedInstOperands,
     /*  54784 */   // GIR_Coverage, 115,
     /*  54784 */   GIR_Done,
     /*  54785 */ // Label 854: @54785
     /*  54785 */ GIM_Reject,
     /*  54786 */ // Label 852: @54786
     /*  54786 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(54816), // Rule ID 116 //
     /*  54791 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  54794 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  54797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54801 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54805 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  54809 */   // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  54809 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
     /*  54814 */   GIR_RootConstrainSelectedInstOperands,
     /*  54815 */   // GIR_Coverage, 116,
     /*  54815 */   GIR_Done,
     /*  54816 */ // Label 855: @54816
     /*  54816 */ GIM_Reject,
     /*  54817 */ // Label 853: @54817
     /*  54817 */ GIM_Reject,
     /*  54818 */ // Label 5: @54818
     /*  54818 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 874*/ GIMT_Encode4(62563),
     /*  54829 */ /*GILLT_s32*//*Label 856*/ GIMT_Encode4(54917),
     /*  54833 */ /*GILLT_s64*//*Label 857*/ GIMT_Encode4(55415), GIMT_Encode4(0),
     /*  54841 */ /*GILLT_v2s32*//*Label 858*/ GIMT_Encode4(56850),
     /*  54845 */ /*GILLT_v2s64*//*Label 859*/ GIMT_Encode4(57010),
     /*  54849 */ /*GILLT_v4s16*//*Label 860*/ GIMT_Encode4(57170),
     /*  54853 */ /*GILLT_v4s32*//*Label 861*/ GIMT_Encode4(57330),
     /*  54857 */ /*GILLT_v8s8*//*Label 862*/ GIMT_Encode4(57490),
     /*  54861 */ /*GILLT_v8s16*//*Label 863*/ GIMT_Encode4(57650),
     /*  54865 */ /*GILLT_v16s8*//*Label 864*/ GIMT_Encode4(57810),
     /*  54869 */ /*GILLT_nxv1s1*//*Label 865*/ GIMT_Encode4(57970),
     /*  54873 */ /*GILLT_nxv2s1*//*Label 866*/ GIMT_Encode4(58511), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  54885 */ /*GILLT_nxv2s64*//*Label 867*/ GIMT_Encode4(59052),
     /*  54889 */ /*GILLT_nxv4s1*//*Label 868*/ GIMT_Encode4(59524), GIMT_Encode4(0),
     /*  54897 */ /*GILLT_nxv4s32*//*Label 869*/ GIMT_Encode4(60065),
     /*  54901 */ /*GILLT_nxv8s1*//*Label 870*/ GIMT_Encode4(60537),
     /*  54905 */ /*GILLT_nxv8s16*//*Label 871*/ GIMT_Encode4(61078),
     /*  54909 */ /*GILLT_nxv16s1*//*Label 872*/ GIMT_Encode4(61550),
     /*  54913 */ /*GILLT_nxv16s8*//*Label 873*/ GIMT_Encode4(62091),
     /*  54917 */ // Label 856: @54917
     /*  54917 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(55414),
     /*  54922 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  54925 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  54928 */   GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(54983), // Rule ID 13527 //
     /*  54933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  54945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  54949 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  54953 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  54957 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54961 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54963 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  54970 */     // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  54970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
     /*  54973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54977 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  54981 */     GIR_RootConstrainSelectedInstOperands,
     /*  54982 */     // GIR_Coverage, 13527,
     /*  54982 */     GIR_EraseRootFromParent_Done,
     /*  54983 */   // Label 876: @54983
     /*  54983 */   GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(55038), // Rule ID 162 //
     /*  54988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  54996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  55004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  55012 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  55016 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55018 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  55025 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  55025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
     /*  55028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55030 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55032 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  55036 */     GIR_RootConstrainSelectedInstOperands,
     /*  55037 */     // GIR_Coverage, 162,
     /*  55037 */     GIR_EraseRootFromParent_Done,
     /*  55038 */   // Label 877: @55038
     /*  55038 */   GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(55107), // Rule ID 5710 //
     /*  55043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55047 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55051 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  55055 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  55059 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55063 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55068 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  55072 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  55076 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  55080 */     // MIs[2] Operand 1
     /*  55080 */     // No operand predicates
     /*  55080 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  55091 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  55093 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), 255:{ *:[i32] })  =>  (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /*  55093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  55096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  55102 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  55105 */     GIR_RootConstrainSelectedInstOperands,
     /*  55106 */     // GIR_Coverage, 5710,
     /*  55106 */     GIR_EraseRootFromParent_Done,
     /*  55107 */   // Label 878: @55107
     /*  55107 */   GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(55176), // Rule ID 5711 //
     /*  55112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  55124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  55128 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55132 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55137 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  55141 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  55145 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  55149 */     // MIs[2] Operand 1
     /*  55149 */     // No operand predicates
     /*  55149 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  55160 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  55162 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 65535:{ *:[i32] })  =>  (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /*  55162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  55165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  55171 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  55174 */     GIR_RootConstrainSelectedInstOperands,
     /*  55175 */     // GIR_Coverage, 5711,
     /*  55175 */     GIR_EraseRootFromParent_Done,
     /*  55176 */   // Label 879: @55176
     /*  55176 */   GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(55229), // Rule ID 13525 //
     /*  55181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55185 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55189 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  55193 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55197 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  55201 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55206 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  55210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55214 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55216 */     // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  55216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
     /*  55219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  55223 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55227 */     GIR_RootConstrainSelectedInstOperands,
     /*  55228 */     // GIR_Coverage, 13525,
     /*  55228 */     GIR_EraseRootFromParent_Done,
     /*  55229 */   // Label 880: @55229
     /*  55229 */   GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(55282), // Rule ID 160 //
     /*  55234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55238 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55242 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55246 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  55250 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55254 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  55258 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55263 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  55267 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55269 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  55269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
     /*  55272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55274 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55280 */     GIR_RootConstrainSelectedInstOperands,
     /*  55281 */     // GIR_Coverage, 160,
     /*  55281 */     GIR_EraseRootFromParent_Done,
     /*  55282 */   // Label 881: @55282
     /*  55282 */   GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(55323), // Rule ID 142 //
     /*  55287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  55291 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  55303 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  55307 */     // MIs[1] Operand 1
     /*  55307 */     // No operand predicates
     /*  55307 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55309 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  55309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
     /*  55312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55314 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55316 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  55321 */     GIR_RootConstrainSelectedInstOperands,
     /*  55322 */     // GIR_Coverage, 142,
     /*  55322 */     GIR_EraseRootFromParent_Done,
     /*  55323 */   // Label 882: @55323
     /*  55323 */   GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(55356), // Rule ID 13523 //
     /*  55328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  55343 */     // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  55343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
     /*  55346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  55350 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  55354 */     GIR_RootConstrainSelectedInstOperands,
     /*  55355 */     // GIR_Coverage, 13523,
     /*  55355 */     GIR_EraseRootFromParent_Done,
     /*  55356 */   // Label 883: @55356
     /*  55356 */   GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(55389), // Rule ID 158 //
     /*  55361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  55376 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  55376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
     /*  55379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55381 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55383 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  55387 */     GIR_RootConstrainSelectedInstOperands,
     /*  55388 */     // GIR_Coverage, 158,
     /*  55388 */     GIR_EraseRootFromParent_Done,
     /*  55389 */   // Label 884: @55389
     /*  55389 */   GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(55413), // Rule ID 156 //
     /*  55394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55398 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55402 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55406 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  55406 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDWrr),
     /*  55411 */     GIR_RootConstrainSelectedInstOperands,
     /*  55412 */     // GIR_Coverage, 156,
     /*  55412 */     GIR_Done,
     /*  55413 */   // Label 885: @55413
     /*  55413 */   GIM_Reject,
     /*  55414 */ // Label 875: @55414
     /*  55414 */ GIM_Reject,
     /*  55415 */ // Label 857: @55415
     /*  55415 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(56849),
     /*  55420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  55423 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  55426 */   GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(55481), // Rule ID 13528 //
     /*  55431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55439 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  55443 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  55447 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55451 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  55455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55459 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55461 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  55468 */     // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  55468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
     /*  55471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  55475 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  55479 */     GIR_RootConstrainSelectedInstOperands,
     /*  55480 */     // GIR_Coverage, 13528,
     /*  55480 */     GIR_EraseRootFromParent_Done,
     /*  55481 */   // Label 887: @55481
     /*  55481 */   GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(55536), // Rule ID 163 //
     /*  55486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55498 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  55502 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  55506 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55510 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  55514 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55516 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  55523 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  55523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
     /*  55526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55528 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55530 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  55534 */     GIR_RootConstrainSelectedInstOperands,
     /*  55535 */     // GIR_Coverage, 163,
     /*  55535 */     GIR_EraseRootFromParent_Done,
     /*  55536 */   // Label 888: @55536
     /*  55536 */   GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(55649), // Rule ID 5712 //
     /*  55541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55545 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55549 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  55553 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55557 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  55561 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  55565 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  55569 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  55573 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55578 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  55582 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  55586 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  55590 */     // MIs[3] Operand 1
     /*  55590 */     // No operand predicates
     /*  55590 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  55601 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  55603 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)), 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), sub_32:{ *:[i32] })
     /*  55603 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55606 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  55610 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55615 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  55619 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
     /*  55622 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  55624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  55627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  55632 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  55638 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55648 */     // GIR_Coverage, 5712,
     /*  55648 */     GIR_EraseRootFromParent_Done,
     /*  55649 */   // Label 889: @55649
     /*  55649 */   GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(55762), // Rule ID 5713 //
     /*  55654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  55666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  55674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  55678 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  55682 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  55686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55691 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  55695 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  55699 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  55703 */     // MIs[3] Operand 1
     /*  55703 */     // No operand predicates
     /*  55703 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  55714 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  55716 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), sub_32:{ *:[i32] })
     /*  55716 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55719 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  55723 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55728 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  55732 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
     /*  55735 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  55737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  55740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  55745 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  55751 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55756 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55761 */     // GIR_Coverage, 5713,
     /*  55761 */     GIR_EraseRootFromParent_Done,
     /*  55762 */   // Label 890: @55762
     /*  55762 */   GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(55861), // Rule ID 7186 //
     /*  55767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55771 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55775 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  55779 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  55782 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  55787 */     // MIs[1] addr
     /*  55787 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  55791 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  55796 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
     /*  55800 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  55811 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55813 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>, 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  55813 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55816 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
     /*  55820 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55825 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  55829 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  55834 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  55836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  55839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  55844 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  55850 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55855 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55860 */     // GIR_Coverage, 7186,
     /*  55860 */     GIR_EraseRootFromParent_Done,
     /*  55861 */   // Label 891: @55861
     /*  55861 */   GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(55960), // Rule ID 7187 //
     /*  55866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  55878 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  55881 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  55886 */     // MIs[1] addr
     /*  55886 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  55890 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  55895 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
     /*  55899 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  55910 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55912 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>, 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  55912 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55915 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
     /*  55919 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55924 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  55928 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  55933 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  55935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  55938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  55943 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  55949 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55959 */     // GIR_Coverage, 7187,
     /*  55959 */     GIR_EraseRootFromParent_Done,
     /*  55960 */   // Label 892: @55960
     /*  55960 */   GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(56059), // Rule ID 7188 //
     /*  55965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  55969 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55973 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  55977 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  55980 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  55985 */     // MIs[1] addr
     /*  55985 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  55989 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  55994 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
     /*  55998 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  56009 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56011 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  56011 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56014 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
     /*  56018 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56023 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  56027 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  56032 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  56037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  56039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  56042 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  56048 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56053 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56058 */     // GIR_Coverage, 7188,
     /*  56058 */     GIR_EraseRootFromParent_Done,
     /*  56059 */   // Label 893: @56059
     /*  56059 */   GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(56158), // Rule ID 7193 //
     /*  56064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  56076 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  56079 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  56084 */     // MIs[1] addr
     /*  56084 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  56088 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  56093 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
     /*  56097 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  56108 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56110 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>, 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  56110 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56113 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
     /*  56117 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56122 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  56126 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  56131 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  56136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  56138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  56141 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  56147 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56157 */     // GIR_Coverage, 7193,
     /*  56157 */     GIR_EraseRootFromParent_Done,
     /*  56158 */   // Label 894: @56158
     /*  56158 */   GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(56257), // Rule ID 7194 //
     /*  56163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  56175 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  56178 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  56183 */     // MIs[1] addr
     /*  56183 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  56187 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  56192 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
     /*  56196 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  56207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56209 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>, 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  56209 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56212 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
     /*  56216 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56221 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  56225 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  56230 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  56235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  56237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  56240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  56246 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56251 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56256 */     // GIR_Coverage, 7194,
     /*  56256 */     GIR_EraseRootFromParent_Done,
     /*  56257 */   // Label 895: @56257
     /*  56257 */   GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(56356), // Rule ID 7195 //
     /*  56262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  56274 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  56277 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  56282 */     // MIs[1] addr
     /*  56282 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  56286 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  56291 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
     /*  56295 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  56306 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56308 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  56308 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56311 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
     /*  56315 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56320 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  56324 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  56329 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  56334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  56336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  56339 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  56345 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56350 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56355 */     // GIR_Coverage, 7195,
     /*  56355 */     GIR_EraseRootFromParent_Done,
     /*  56356 */   // Label 896: @56356
     /*  56356 */   GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(56409), // Rule ID 13526 //
     /*  56361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56386 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  56390 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56394 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56396 */     // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  56396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
     /*  56399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  56403 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  56407 */     GIR_RootConstrainSelectedInstOperands,
     /*  56408 */     // GIR_Coverage, 13526,
     /*  56408 */     GIR_EraseRootFromParent_Done,
     /*  56409 */   // Label 897: @56409
     /*  56409 */   GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(56462), // Rule ID 161 //
     /*  56414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56434 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56438 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56443 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  56447 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56449 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }))  =>  (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  56449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
     /*  56452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56454 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  56456 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  56460 */     GIR_RootConstrainSelectedInstOperands,
     /*  56461 */     // GIR_Coverage, 161,
     /*  56461 */     GIR_EraseRootFromParent_Done,
     /*  56462 */   // Label 898: @56462
     /*  56462 */   GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(56562), // Rule ID 4037 //
     /*  56467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56475 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  56486 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (ORRWrr:{ *:[i32] } WZR:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  56486 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  56489 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56493 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56498 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56504 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56509 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56514 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56517 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
     /*  56521 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56526 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56532 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  56535 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  56540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  56542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  56545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  56551 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  56556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56561 */     // GIR_Coverage, 4037,
     /*  56561 */     GIR_EraseRootFromParent_Done,
     /*  56562 */   // Label 899: @56562
     /*  56562 */   GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(56603), // Rule ID 143 //
     /*  56567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  56571 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56575 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56579 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  56583 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  56587 */     // MIs[1] Operand 1
     /*  56587 */     // No operand predicates
     /*  56587 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56589 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  56589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXri),
     /*  56592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56594 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  56596 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  56601 */     GIR_RootConstrainSelectedInstOperands,
     /*  56602 */     // GIR_Coverage, 143,
     /*  56602 */     GIR_EraseRootFromParent_Done,
     /*  56603 */   // Label 900: @56603
     /*  56603 */   GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(56636), // Rule ID 13524 //
     /*  56608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56612 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  56623 */     // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  56623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
     /*  56626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  56630 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  56634 */     GIR_RootConstrainSelectedInstOperands,
     /*  56635 */     // GIR_Coverage, 13524,
     /*  56635 */     GIR_EraseRootFromParent_Done,
     /*  56636 */   // Label 901: @56636
     /*  56636 */   GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(56669), // Rule ID 159 //
     /*  56641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56645 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  56656 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  56656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
     /*  56659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56661 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  56663 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  56667 */     GIR_RootConstrainSelectedInstOperands,
     /*  56668 */     // GIR_Coverage, 159,
     /*  56668 */     GIR_EraseRootFromParent_Done,
     /*  56669 */   // Label 902: @56669
     /*  56669 */   GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(56733), // Rule ID 14199 //
     /*  56674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56689 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56693 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56697 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  56706 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  56712 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  56714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56718 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56720 */     // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS)  =>  (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  56720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  56723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56725 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  56727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  56731 */     GIR_RootConstrainSelectedInstOperands,
     /*  56732 */     // GIR_Coverage, 14199,
     /*  56732 */     GIR_EraseRootFromParent_Done,
     /*  56733 */   // Label 903: @56733
     /*  56733 */   GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(56797), // Rule ID 5092 //
     /*  56738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56761 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56770 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  56774 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  56780 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  56782 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56784 */     // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }))  =>  (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  56784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  56787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56789 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  56791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  56795 */     GIR_RootConstrainSelectedInstOperands,
     /*  56796 */     // GIR_Coverage, 5092,
     /*  56796 */     GIR_EraseRootFromParent_Done,
     /*  56797 */   // Label 904: @56797
     /*  56797 */   GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(56821), // Rule ID 157 //
     /*  56802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56806 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56814 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  56814 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDXrr),
     /*  56819 */     GIR_RootConstrainSelectedInstOperands,
     /*  56820 */     // GIR_Coverage, 157,
     /*  56820 */     GIR_Done,
     /*  56821 */   // Label 905: @56821
     /*  56821 */   GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(56848), // Rule ID 2484 //
     /*  56826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56833 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56837 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56841 */     // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  56841 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  56846 */     GIR_RootConstrainSelectedInstOperands,
     /*  56847 */     // GIR_Coverage, 2484,
     /*  56847 */     GIR_Done,
     /*  56848 */   // Label 906: @56848
     /*  56848 */   GIM_Reject,
     /*  56849 */ // Label 886: @56849
     /*  56849 */ GIM_Reject,
     /*  56850 */ // Label 858: @56850
     /*  56850 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(57009),
     /*  56855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  56858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  56861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56865 */   GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(56925), // Rule ID 14198 //
     /*  56870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56881 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  56885 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  56889 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56894 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  56898 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  56904 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  56906 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56910 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56912 */     // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS)  =>  (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  56912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  56915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56917 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  56919 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  56923 */     GIR_RootConstrainSelectedInstOperands,
     /*  56924 */     // GIR_Coverage, 14198,
     /*  56924 */     GIR_EraseRootFromParent_Done,
     /*  56925 */   // Label 908: @56925
     /*  56925 */   GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(56985), // Rule ID 5091 //
     /*  56930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56933 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  56945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  56949 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  56953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56958 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  56962 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  56968 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  56970 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56972 */     // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }))  =>  (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  56972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  56975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56977 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  56979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  56983 */     GIR_RootConstrainSelectedInstOperands,
     /*  56984 */     // GIR_Coverage, 5091,
     /*  56984 */     GIR_EraseRootFromParent_Done,
     /*  56985 */   // Label 909: @56985
     /*  56985 */   GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(57008), // Rule ID 2483 //
     /*  56990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  56993 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  56997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57001 */     // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  57001 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  57006 */     GIR_RootConstrainSelectedInstOperands,
     /*  57007 */     // GIR_Coverage, 2483,
     /*  57007 */     GIR_Done,
     /*  57008 */   // Label 910: @57008
     /*  57008 */   GIM_Reject,
     /*  57009 */ // Label 907: @57009
     /*  57009 */ GIM_Reject,
     /*  57010 */ // Label 859: @57010
     /*  57010 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(57169),
     /*  57015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  57018 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  57021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57025 */   GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(57085), // Rule ID 14202 //
     /*  57030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57033 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57037 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57041 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  57045 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  57049 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57054 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57058 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57064 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57066 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57070 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57072 */     // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS)  =>  (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  57072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57077 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  57079 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57083 */     GIR_RootConstrainSelectedInstOperands,
     /*  57084 */     // GIR_Coverage, 14202,
     /*  57084 */     GIR_EraseRootFromParent_Done,
     /*  57085 */   // Label 912: @57085
     /*  57085 */   GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(57145), // Rule ID 5095 //
     /*  57090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57093 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57105 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  57109 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  57113 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57118 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57122 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57128 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57130 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57132 */     // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }))  =>  (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  57132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57137 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  57139 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57143 */     GIR_RootConstrainSelectedInstOperands,
     /*  57144 */     // GIR_Coverage, 5095,
     /*  57144 */     GIR_EraseRootFromParent_Done,
     /*  57145 */   // Label 913: @57145
     /*  57145 */   GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(57168), // Rule ID 2487 //
     /*  57150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57153 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57157 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57161 */     // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  57161 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  57166 */     GIR_RootConstrainSelectedInstOperands,
     /*  57167 */     // GIR_Coverage, 2487,
     /*  57167 */     GIR_Done,
     /*  57168 */   // Label 914: @57168
     /*  57168 */   GIM_Reject,
     /*  57169 */ // Label 911: @57169
     /*  57169 */ GIM_Reject,
     /*  57170 */ // Label 860: @57170
     /*  57170 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(57329),
     /*  57175 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  57178 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  57181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57185 */   GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(57245), // Rule ID 14197 //
     /*  57190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57201 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  57205 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  57209 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57218 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57224 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57226 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57230 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57232 */     // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS)  =>  (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  57232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  57235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57237 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  57239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57243 */     GIR_RootConstrainSelectedInstOperands,
     /*  57244 */     // GIR_Coverage, 14197,
     /*  57244 */     GIR_EraseRootFromParent_Done,
     /*  57245 */   // Label 916: @57245
     /*  57245 */   GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(57305), // Rule ID 5090 //
     /*  57250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57253 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57257 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57261 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57265 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  57269 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  57273 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57278 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57282 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57288 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57290 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57292 */     // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }))  =>  (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  57292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  57295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57297 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  57299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57303 */     GIR_RootConstrainSelectedInstOperands,
     /*  57304 */     // GIR_Coverage, 5090,
     /*  57304 */     GIR_EraseRootFromParent_Done,
     /*  57305 */   // Label 917: @57305
     /*  57305 */   GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(57328), // Rule ID 2482 //
     /*  57310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57313 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57317 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57321 */     // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  57321 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  57326 */     GIR_RootConstrainSelectedInstOperands,
     /*  57327 */     // GIR_Coverage, 2482,
     /*  57327 */     GIR_Done,
     /*  57328 */   // Label 918: @57328
     /*  57328 */   GIM_Reject,
     /*  57329 */ // Label 915: @57329
     /*  57329 */ GIM_Reject,
     /*  57330 */ // Label 861: @57330
     /*  57330 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(57489),
     /*  57335 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57338 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  57341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57345 */   GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(57405), // Rule ID 14201 //
     /*  57350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57353 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57357 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57361 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57365 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  57369 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57374 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57378 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57384 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57386 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57390 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57392 */     // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS)  =>  (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  57392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57397 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  57399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57403 */     GIR_RootConstrainSelectedInstOperands,
     /*  57404 */     // GIR_Coverage, 14201,
     /*  57404 */     GIR_EraseRootFromParent_Done,
     /*  57405 */   // Label 920: @57405
     /*  57405 */   GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(57465), // Rule ID 5094 //
     /*  57410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57413 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57417 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57421 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57425 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57429 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  57433 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57438 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57442 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57448 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57452 */     // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }))  =>  (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  57452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57457 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  57459 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57463 */     GIR_RootConstrainSelectedInstOperands,
     /*  57464 */     // GIR_Coverage, 5094,
     /*  57464 */     GIR_EraseRootFromParent_Done,
     /*  57465 */   // Label 921: @57465
     /*  57465 */   GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(57488), // Rule ID 2486 //
     /*  57470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57473 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57477 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57481 */     // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  57481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  57486 */     GIR_RootConstrainSelectedInstOperands,
     /*  57487 */     // GIR_Coverage, 2486,
     /*  57487 */     GIR_Done,
     /*  57488 */   // Label 922: @57488
     /*  57488 */   GIM_Reject,
     /*  57489 */ // Label 919: @57489
     /*  57489 */ GIM_Reject,
     /*  57490 */ // Label 862: @57490
     /*  57490 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(57649),
     /*  57495 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  57498 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  57501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57505 */   GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(57565), // Rule ID 13665 //
     /*  57510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57521 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  57525 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  57529 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57534 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57538 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57544 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57546 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57550 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57552 */     // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn)  =>  (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  57552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  57555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57563 */     GIR_RootConstrainSelectedInstOperands,
     /*  57564 */     // GIR_Coverage, 13665,
     /*  57564 */     GIR_EraseRootFromParent_Done,
     /*  57565 */   // Label 924: @57565
     /*  57565 */   GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(57625), // Rule ID 1601 //
     /*  57570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57573 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  57589 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  57593 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57598 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57602 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57608 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57610 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57612 */     // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }))  =>  (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  57612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  57615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57617 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57623 */     GIR_RootConstrainSelectedInstOperands,
     /*  57624 */     // GIR_Coverage, 1601,
     /*  57624 */     GIR_EraseRootFromParent_Done,
     /*  57625 */   // Label 925: @57625
     /*  57625 */   GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(57648), // Rule ID 1599 //
     /*  57630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57641 */     // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  57641 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  57646 */     GIR_RootConstrainSelectedInstOperands,
     /*  57647 */     // GIR_Coverage, 1599,
     /*  57647 */     GIR_Done,
     /*  57648 */   // Label 926: @57648
     /*  57648 */   GIM_Reject,
     /*  57649 */ // Label 923: @57649
     /*  57649 */ GIM_Reject,
     /*  57650 */ // Label 863: @57650
     /*  57650 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(57809),
     /*  57655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57658 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  57661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57665 */   GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(57725), // Rule ID 14200 //
     /*  57670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57685 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  57689 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57698 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57704 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57710 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57712 */     // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS)  =>  (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  57712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57717 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  57719 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57723 */     GIR_RootConstrainSelectedInstOperands,
     /*  57724 */     // GIR_Coverage, 14200,
     /*  57724 */     GIR_EraseRootFromParent_Done,
     /*  57725 */   // Label 928: @57725
     /*  57725 */   GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(57785), // Rule ID 5093 //
     /*  57730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57733 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57749 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  57753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57758 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57762 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57768 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57770 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57772 */     // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }))  =>  (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  57772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57777 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  57779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  57783 */     GIR_RootConstrainSelectedInstOperands,
     /*  57784 */     // GIR_Coverage, 5093,
     /*  57784 */     GIR_EraseRootFromParent_Done,
     /*  57785 */   // Label 929: @57785
     /*  57785 */   GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(57808), // Rule ID 2485 //
     /*  57790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57793 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57797 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57801 */     // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  57801 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  57806 */     GIR_RootConstrainSelectedInstOperands,
     /*  57807 */     // GIR_Coverage, 2485,
     /*  57807 */     GIR_Done,
     /*  57808 */   // Label 930: @57808
     /*  57808 */   GIM_Reject,
     /*  57809 */ // Label 927: @57809
     /*  57809 */ GIM_Reject,
     /*  57810 */ // Label 864: @57810
     /*  57810 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(57969),
     /*  57815 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  57818 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  57821 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57825 */   GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(57885), // Rule ID 13666 //
     /*  57830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  57845 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  57849 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57854 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57858 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57864 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57866 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57872 */     // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn)  =>  (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  57872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57883 */     GIR_RootConstrainSelectedInstOperands,
     /*  57884 */     // GIR_Coverage, 13666,
     /*  57884 */     GIR_EraseRootFromParent_Done,
     /*  57885 */   // Label 932: @57885
     /*  57885 */   GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(57945), // Rule ID 1602 //
     /*  57890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57893 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  57905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  57909 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  57913 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57918 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57922 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  57928 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  57930 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57932 */     // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }))  =>  (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  57932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  57935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57937 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57943 */     GIR_RootConstrainSelectedInstOperands,
     /*  57944 */     // GIR_Coverage, 1602,
     /*  57944 */     GIR_EraseRootFromParent_Done,
     /*  57945 */   // Label 933: @57945
     /*  57945 */   GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(57968), // Rule ID 1600 //
     /*  57950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57953 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57957 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57961 */     // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  57961 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  57966 */     GIR_RootConstrainSelectedInstOperands,
     /*  57967 */     // GIR_Coverage, 1600,
     /*  57967 */     GIR_Done,
     /*  57968 */   // Label 934: @57968
     /*  57968 */   GIM_Reject,
     /*  57969 */ // Label 931: @57969
     /*  57969 */ GIM_Reject,
     /*  57970 */ // Label 865: @57970
     /*  57970 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(58510),
     /*  57975 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  57978 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  57981 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  57985 */   GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(58042), // Rule ID 15397 //
     /*  57990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  57993 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57997 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58001 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58005 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58009 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58013 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58017 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58021 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58025 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58027 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] }), nxv1i1:{ *:[nxv1i1] }:$Op2), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58032 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58040 */     GIR_RootConstrainSelectedInstOperands,
     /*  58041 */     // GIR_Coverage, 15397,
     /*  58041 */     GIR_EraseRootFromParent_Done,
     /*  58042 */   // Label 936: @58042
     /*  58042 */   GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(58099), // Rule ID 15400 //
     /*  58047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58054 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58058 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58062 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58066 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58070 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58074 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58078 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58082 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58084 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] }), nxv1i1:{ *:[nxv1i1] }:$Op2), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58091 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58093 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58097 */     GIR_RootConstrainSelectedInstOperands,
     /*  58098 */     // GIR_Coverage, 15400,
     /*  58098 */     GIR_EraseRootFromParent_Done,
     /*  58099 */   // Label 937: @58099
     /*  58099 */   GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(58156), // Rule ID 15396 //
     /*  58104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58115 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58119 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58127 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58131 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58135 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58139 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58141 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] })), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58154 */     GIR_RootConstrainSelectedInstOperands,
     /*  58155 */     // GIR_Coverage, 15396,
     /*  58155 */     GIR_EraseRootFromParent_Done,
     /*  58156 */   // Label 938: @58156
     /*  58156 */   GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(58213), // Rule ID 15399 //
     /*  58161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58188 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58192 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58196 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58198 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] })), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58211 */     GIR_RootConstrainSelectedInstOperands,
     /*  58212 */     // GIR_Coverage, 15399,
     /*  58212 */     GIR_EraseRootFromParent_Done,
     /*  58213 */   // Label 939: @58213
     /*  58213 */   GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(58270), // Rule ID 15395 //
     /*  58218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58233 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58237 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58241 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58245 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58249 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58253 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58255 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] }), nxv1i1:{ *:[nxv1i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58260 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58262 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58264 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58268 */     GIR_RootConstrainSelectedInstOperands,
     /*  58269 */     // GIR_Coverage, 15395,
     /*  58269 */     GIR_EraseRootFromParent_Done,
     /*  58270 */   // Label 940: @58270
     /*  58270 */   GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(58327), // Rule ID 15398 //
     /*  58275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58282 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58286 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58290 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58294 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58298 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58302 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58306 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58310 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58312 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] }), nxv1i1:{ *:[nxv1i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58317 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58319 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58325 */     GIR_RootConstrainSelectedInstOperands,
     /*  58326 */     // GIR_Coverage, 15398,
     /*  58326 */     GIR_EraseRootFromParent_Done,
     /*  58327 */   // Label 941: @58327
     /*  58327 */   GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(58384), // Rule ID 8554 //
     /*  58332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58335 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58339 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58343 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58347 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58351 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58355 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58359 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58363 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58367 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58369 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58374 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58376 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58378 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58382 */     GIR_RootConstrainSelectedInstOperands,
     /*  58383 */     // GIR_Coverage, 8554,
     /*  58383 */     GIR_EraseRootFromParent_Done,
     /*  58384 */   // Label 942: @58384
     /*  58384 */   GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(58441), // Rule ID 8555 //
     /*  58389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58392 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58396 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58400 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  58404 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  58408 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58412 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58416 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58420 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58424 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58426 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58431 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58433 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58435 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58439 */     GIR_RootConstrainSelectedInstOperands,
     /*  58440 */     // GIR_Coverage, 8555,
     /*  58440 */     GIR_EraseRootFromParent_Done,
     /*  58441 */   // Label 943: @58441
     /*  58441 */   GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(58488), // Rule ID 10820 //
     /*  58446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58449 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  58453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  58457 */     // (and:{ *:[nxv1i1] } PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2)
     /*  58457 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  58460 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  58464 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  58469 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  58472 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  58474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  58477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58479 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  58482 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  58484 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  58486 */     GIR_RootConstrainSelectedInstOperands,
     /*  58487 */     // GIR_Coverage, 10820,
     /*  58487 */     GIR_EraseRootFromParent_Done,
     /*  58488 */   // Label 944: @58488
     /*  58488 */   GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(58509), // Rule ID 2753 //
     /*  58493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58496 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  58496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  58499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58501 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58503 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  58507 */     GIR_RootConstrainSelectedInstOperands,
     /*  58508 */     // GIR_Coverage, 2753,
     /*  58508 */     GIR_EraseRootFromParent_Done,
     /*  58509 */   // Label 945: @58509
     /*  58509 */   GIM_Reject,
     /*  58510 */ // Label 935: @58510
     /*  58510 */ GIM_Reject,
     /*  58511 */ // Label 866: @58511
     /*  58511 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(59051),
     /*  58516 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58519 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  58526 */   GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(58583), // Rule ID 15388 //
     /*  58531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58542 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58546 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58550 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58554 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58558 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58562 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58566 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58568 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] }), nxv2i1:{ *:[nxv2i1] }:$Op2), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58577 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58581 */     GIR_RootConstrainSelectedInstOperands,
     /*  58582 */     // GIR_Coverage, 15388,
     /*  58582 */     GIR_EraseRootFromParent_Done,
     /*  58583 */   // Label 947: @58583
     /*  58583 */   GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(58640), // Rule ID 15391 //
     /*  58588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58595 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58599 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58603 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58615 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58619 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58623 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58625 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] }), nxv2i1:{ *:[nxv2i1] }:$Op2), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58630 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58638 */     GIR_RootConstrainSelectedInstOperands,
     /*  58639 */     // GIR_Coverage, 15391,
     /*  58639 */     GIR_EraseRootFromParent_Done,
     /*  58640 */   // Label 948: @58640
     /*  58640 */   GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(58697), // Rule ID 15387 //
     /*  58645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58656 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58660 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58664 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58668 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58672 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58676 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58680 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58682 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] })), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58691 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58695 */     GIR_RootConstrainSelectedInstOperands,
     /*  58696 */     // GIR_Coverage, 15387,
     /*  58696 */     GIR_EraseRootFromParent_Done,
     /*  58697 */   // Label 949: @58697
     /*  58697 */   GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(58754), // Rule ID 15390 //
     /*  58702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58729 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58733 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58737 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58739 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] })), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  58748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58752 */     GIR_RootConstrainSelectedInstOperands,
     /*  58753 */     // GIR_Coverage, 15390,
     /*  58753 */     GIR_EraseRootFromParent_Done,
     /*  58754 */   // Label 950: @58754
     /*  58754 */   GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(58811), // Rule ID 15386 //
     /*  58759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58762 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58766 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58770 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58774 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58778 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58782 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58786 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58790 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58794 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58796 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] }), nxv2i1:{ *:[nxv2i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58801 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58803 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58809 */     GIR_RootConstrainSelectedInstOperands,
     /*  58810 */     // GIR_Coverage, 15386,
     /*  58810 */     GIR_EraseRootFromParent_Done,
     /*  58811 */   // Label 951: @58811
     /*  58811 */   GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(58868), // Rule ID 15389 //
     /*  58816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58835 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  58839 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58843 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58847 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58851 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58853 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] }), nxv2i1:{ *:[nxv2i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58858 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58860 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58862 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  58866 */     GIR_RootConstrainSelectedInstOperands,
     /*  58867 */     // GIR_Coverage, 15389,
     /*  58867 */     GIR_EraseRootFromParent_Done,
     /*  58868 */   // Label 952: @58868
     /*  58868 */   GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(58925), // Rule ID 8550 //
     /*  58873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58876 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58880 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58884 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58888 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58892 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58896 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58900 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  58904 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58908 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58910 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58915 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58917 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58919 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58923 */     GIR_RootConstrainSelectedInstOperands,
     /*  58924 */     // GIR_Coverage, 8550,
     /*  58924 */     GIR_EraseRootFromParent_Done,
     /*  58925 */   // Label 953: @58925
     /*  58925 */   GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(58982), // Rule ID 8551 //
     /*  58930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  58945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  58949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  58957 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  58961 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  58965 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58967 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  58967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  58970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  58972 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58974 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  58976 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  58980 */     GIR_RootConstrainSelectedInstOperands,
     /*  58981 */     // GIR_Coverage, 8551,
     /*  58981 */     GIR_EraseRootFromParent_Done,
     /*  58982 */   // Label 954: @58982
     /*  58982 */   GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(59029), // Rule ID 10819 //
     /*  58987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  58990 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  58994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  58998 */     // (and:{ *:[nxv2i1] } PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2)
     /*  58998 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  59001 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  59005 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59010 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  59013 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  59018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59020 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59023 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  59025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  59027 */     GIR_RootConstrainSelectedInstOperands,
     /*  59028 */     // GIR_Coverage, 10819,
     /*  59028 */     GIR_EraseRootFromParent_Done,
     /*  59029 */   // Label 955: @59029
     /*  59029 */   GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(59050), // Rule ID 2752 //
     /*  59034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59037 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  59037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  59040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59042 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59044 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59046 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  59048 */     GIR_RootConstrainSelectedInstOperands,
     /*  59049 */     // GIR_Coverage, 2752,
     /*  59049 */     GIR_EraseRootFromParent_Done,
     /*  59050 */   // Label 956: @59050
     /*  59050 */   GIM_Reject,
     /*  59051 */ // Label 946: @59051
     /*  59051 */ GIM_Reject,
     /*  59052 */ // Label 867: @59052
     /*  59052 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(59523),
     /*  59057 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59060 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  59067 */   GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(59122), // Rule ID 15326 //
     /*  59072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59083 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59087 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59099 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59103 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59107 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59109 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59116 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59120 */     GIR_RootConstrainSelectedInstOperands,
     /*  59121 */     // GIR_Coverage, 15326,
     /*  59121 */     GIR_EraseRootFromParent_Done,
     /*  59122 */   // Label 958: @59122
     /*  59122 */   GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(59177), // Rule ID 15329 //
     /*  59127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59134 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59138 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59142 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59146 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59150 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59154 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59158 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59162 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59164 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59175 */     GIR_RootConstrainSelectedInstOperands,
     /*  59176 */     // GIR_Coverage, 15329,
     /*  59176 */     GIR_EraseRootFromParent_Done,
     /*  59177 */   // Label 959: @59177
     /*  59177 */   GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(59232), // Rule ID 15325 //
     /*  59182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59185 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59189 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59193 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59197 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59201 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59205 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59209 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59213 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59217 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59219 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59226 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59230 */     GIR_RootConstrainSelectedInstOperands,
     /*  59231 */     // GIR_Coverage, 15325,
     /*  59231 */     GIR_EraseRootFromParent_Done,
     /*  59232 */   // Label 960: @59232
     /*  59232 */   GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(59287), // Rule ID 15328 //
     /*  59237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59240 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59244 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59248 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59252 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59256 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59260 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59264 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59268 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59272 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59274 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59281 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59285 */     GIR_RootConstrainSelectedInstOperands,
     /*  59286 */     // GIR_Coverage, 15328,
     /*  59286 */     GIR_EraseRootFromParent_Done,
     /*  59287 */   // Label 961: @59287
     /*  59287 */   GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(59342), // Rule ID 15324 //
     /*  59292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59307 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59311 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59315 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59319 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59323 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59327 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59329 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59334 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59336 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59340 */     GIR_RootConstrainSelectedInstOperands,
     /*  59341 */     // GIR_Coverage, 15324,
     /*  59341 */     GIR_EraseRootFromParent_Done,
     /*  59342 */   // Label 962: @59342
     /*  59342 */   GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(59397), // Rule ID 15327 //
     /*  59347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59350 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59354 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59358 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59362 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59366 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59370 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59374 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59378 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59382 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59384 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59389 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59391 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59395 */     GIR_RootConstrainSelectedInstOperands,
     /*  59396 */     // GIR_Coverage, 15327,
     /*  59396 */     GIR_EraseRootFromParent_Done,
     /*  59397 */   // Label 963: @59397
     /*  59397 */   GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(59452), // Rule ID 7574 //
     /*  59402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59429 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59433 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59437 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59439 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59444 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59450 */     GIR_RootConstrainSelectedInstOperands,
     /*  59451 */     // GIR_Coverage, 7574,
     /*  59451 */     GIR_EraseRootFromParent_Done,
     /*  59452 */   // Label 964: @59452
     /*  59452 */   GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(59507), // Rule ID 7575 //
     /*  59457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59464 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59468 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  59472 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  59476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59484 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59488 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59492 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59494 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  59497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  59499 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59505 */     GIR_RootConstrainSelectedInstOperands,
     /*  59506 */     // GIR_Coverage, 7575,
     /*  59506 */     GIR_EraseRootFromParent_Done,
     /*  59507 */   // Label 965: @59507
     /*  59507 */   GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(59522), // Rule ID 3161 //
     /*  59512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59515 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  59515 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  59520 */     GIR_RootConstrainSelectedInstOperands,
     /*  59521 */     // GIR_Coverage, 3161,
     /*  59521 */     GIR_Done,
     /*  59522 */   // Label 966: @59522
     /*  59522 */   GIM_Reject,
     /*  59523 */ // Label 957: @59523
     /*  59523 */ GIM_Reject,
     /*  59524 */ // Label 868: @59524
     /*  59524 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(60064),
     /*  59529 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59532 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  59539 */   GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(59596), // Rule ID 15379 //
     /*  59544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59547 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59551 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59555 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59559 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59563 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59567 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59571 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59575 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59579 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59581 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] }), nxv4i1:{ *:[nxv4i1] }:$Op2), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59586 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59594 */     GIR_RootConstrainSelectedInstOperands,
     /*  59595 */     // GIR_Coverage, 15379,
     /*  59595 */     GIR_EraseRootFromParent_Done,
     /*  59596 */   // Label 968: @59596
     /*  59596 */   GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(59653), // Rule ID 15382 //
     /*  59601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59608 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59612 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59616 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59620 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59624 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59628 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59632 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59636 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59638 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] }), nxv4i1:{ *:[nxv4i1] }:$Op2), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59651 */     GIR_RootConstrainSelectedInstOperands,
     /*  59652 */     // GIR_Coverage, 15382,
     /*  59652 */     GIR_EraseRootFromParent_Done,
     /*  59653 */   // Label 969: @59653
     /*  59653 */   GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(59710), // Rule ID 15378 //
     /*  59658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59673 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59677 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59681 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59685 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59689 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59693 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59695 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] })), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59708 */     GIR_RootConstrainSelectedInstOperands,
     /*  59709 */     // GIR_Coverage, 15378,
     /*  59709 */     GIR_EraseRootFromParent_Done,
     /*  59710 */   // Label 970: @59710
     /*  59710 */   GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(59767), // Rule ID 15381 //
     /*  59715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59722 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59726 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59730 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59734 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59738 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59742 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59746 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59750 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59752 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] })), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59759 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  59761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59765 */     GIR_RootConstrainSelectedInstOperands,
     /*  59766 */     // GIR_Coverage, 15381,
     /*  59766 */     GIR_EraseRootFromParent_Done,
     /*  59767 */   // Label 971: @59767
     /*  59767 */   GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(59824), // Rule ID 15377 //
     /*  59772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59783 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59787 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59791 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59795 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59799 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59803 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59807 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59809 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] }), nxv4i1:{ *:[nxv4i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59814 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59816 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59822 */     GIR_RootConstrainSelectedInstOperands,
     /*  59823 */     // GIR_Coverage, 15377,
     /*  59823 */     GIR_EraseRootFromParent_Done,
     /*  59824 */   // Label 972: @59824
     /*  59824 */   GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(59881), // Rule ID 15380 //
     /*  59829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59832 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59836 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59840 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59844 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59848 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59852 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59856 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59860 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59864 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59866 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] }), nxv4i1:{ *:[nxv4i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59871 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59873 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  59879 */     GIR_RootConstrainSelectedInstOperands,
     /*  59880 */     // GIR_Coverage, 15380,
     /*  59880 */     GIR_EraseRootFromParent_Done,
     /*  59881 */   // Label 973: @59881
     /*  59881 */   GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(59938), // Rule ID 8546 //
     /*  59886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59897 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59901 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59905 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59909 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59913 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  59917 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59921 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59923 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59928 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59930 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59936 */     GIR_RootConstrainSelectedInstOperands,
     /*  59937 */     // GIR_Coverage, 8546,
     /*  59937 */     GIR_EraseRootFromParent_Done,
     /*  59938 */   // Label 974: @59938
     /*  59938 */   GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(59995), // Rule ID 8547 //
     /*  59943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  59946 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59950 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59954 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  59958 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  59962 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  59966 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  59970 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  59974 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  59978 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  59980 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  59980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  59983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  59985 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59987 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  59989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  59993 */     GIR_RootConstrainSelectedInstOperands,
     /*  59994 */     // GIR_Coverage, 8547,
     /*  59994 */     GIR_EraseRootFromParent_Done,
     /*  59995 */   // Label 975: @59995
     /*  59995 */   GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(60042), // Rule ID 10818 //
     /*  60000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60003 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  60007 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  60011 */     // (and:{ *:[nxv4i1] } PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2)
     /*  60011 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  60014 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /*  60018 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60023 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  60026 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  60031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60033 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  60038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  60040 */     GIR_RootConstrainSelectedInstOperands,
     /*  60041 */     // GIR_Coverage, 10818,
     /*  60041 */     GIR_EraseRootFromParent_Done,
     /*  60042 */   // Label 976: @60042
     /*  60042 */   GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(60063), // Rule ID 2751 //
     /*  60047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60050 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  60050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  60053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60055 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60057 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  60061 */     GIR_RootConstrainSelectedInstOperands,
     /*  60062 */     // GIR_Coverage, 2751,
     /*  60062 */     GIR_EraseRootFromParent_Done,
     /*  60063 */   // Label 977: @60063
     /*  60063 */   GIM_Reject,
     /*  60064 */ // Label 967: @60064
     /*  60064 */ GIM_Reject,
     /*  60065 */ // Label 869: @60065
     /*  60065 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(60536),
     /*  60070 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60073 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  60080 */   GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(60135), // Rule ID 15317 //
     /*  60085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60100 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60104 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60108 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60112 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60116 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60120 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60122 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60127 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60133 */     GIR_RootConstrainSelectedInstOperands,
     /*  60134 */     // GIR_Coverage, 15317,
     /*  60134 */     GIR_EraseRootFromParent_Done,
     /*  60135 */   // Label 979: @60135
     /*  60135 */   GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(60190), // Rule ID 15320 //
     /*  60140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60151 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60155 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60167 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60171 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60175 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60177 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60184 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60188 */     GIR_RootConstrainSelectedInstOperands,
     /*  60189 */     // GIR_Coverage, 15320,
     /*  60189 */     GIR_EraseRootFromParent_Done,
     /*  60190 */   // Label 980: @60190
     /*  60190 */   GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(60245), // Rule ID 15316 //
     /*  60195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60218 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60222 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60226 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60230 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60232 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60243 */     GIR_RootConstrainSelectedInstOperands,
     /*  60244 */     // GIR_Coverage, 15316,
     /*  60244 */     GIR_EraseRootFromParent_Done,
     /*  60245 */   // Label 981: @60245
     /*  60245 */   GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(60300), // Rule ID 15319 //
     /*  60250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60269 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60273 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60277 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60281 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60285 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60287 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60294 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60298 */     GIR_RootConstrainSelectedInstOperands,
     /*  60299 */     // GIR_Coverage, 15319,
     /*  60299 */     GIR_EraseRootFromParent_Done,
     /*  60300 */   // Label 982: @60300
     /*  60300 */   GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(60355), // Rule ID 15315 //
     /*  60305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60312 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60316 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60320 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60324 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60328 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60332 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60336 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60340 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60342 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60347 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60353 */     GIR_RootConstrainSelectedInstOperands,
     /*  60354 */     // GIR_Coverage, 15315,
     /*  60354 */     GIR_EraseRootFromParent_Done,
     /*  60355 */   // Label 983: @60355
     /*  60355 */   GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(60410), // Rule ID 15318 //
     /*  60360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60363 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60367 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60371 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60375 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60379 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60383 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60387 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60391 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60395 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60397 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60402 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60408 */     GIR_RootConstrainSelectedInstOperands,
     /*  60409 */     // GIR_Coverage, 15318,
     /*  60409 */     GIR_EraseRootFromParent_Done,
     /*  60410 */   // Label 984: @60410
     /*  60410 */   GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(60465), // Rule ID 7570 //
     /*  60415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60430 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60434 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60438 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60442 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60446 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60452 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60457 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60459 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60463 */     GIR_RootConstrainSelectedInstOperands,
     /*  60464 */     // GIR_Coverage, 7570,
     /*  60464 */     GIR_EraseRootFromParent_Done,
     /*  60465 */   // Label 985: @60465
     /*  60465 */   GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(60520), // Rule ID 7571 //
     /*  60470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60477 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60481 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  60485 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  60489 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60493 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60497 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60501 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60505 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60507 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  60510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  60512 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60514 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60518 */     GIR_RootConstrainSelectedInstOperands,
     /*  60519 */     // GIR_Coverage, 7571,
     /*  60519 */     GIR_EraseRootFromParent_Done,
     /*  60520 */   // Label 986: @60520
     /*  60520 */   GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(60535), // Rule ID 3160 //
     /*  60525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60528 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  60528 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  60533 */     GIR_RootConstrainSelectedInstOperands,
     /*  60534 */     // GIR_Coverage, 3160,
     /*  60534 */     GIR_Done,
     /*  60535 */   // Label 987: @60535
     /*  60535 */   GIM_Reject,
     /*  60536 */ // Label 978: @60536
     /*  60536 */ GIM_Reject,
     /*  60537 */ // Label 870: @60537
     /*  60537 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(61077),
     /*  60542 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60545 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60548 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  60552 */   GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(60609), // Rule ID 15370 //
     /*  60557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60568 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60572 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60576 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60580 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60584 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60588 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60592 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60594 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] }), nxv8i1:{ *:[nxv8i1] }:$Op2), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60599 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60601 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60607 */     GIR_RootConstrainSelectedInstOperands,
     /*  60608 */     // GIR_Coverage, 15370,
     /*  60608 */     GIR_EraseRootFromParent_Done,
     /*  60609 */   // Label 989: @60609
     /*  60609 */   GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(60666), // Rule ID 15373 //
     /*  60614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60625 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60629 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60633 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60637 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60641 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60645 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60649 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60651 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] }), nxv8i1:{ *:[nxv8i1] }:$Op2), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60656 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60664 */     GIR_RootConstrainSelectedInstOperands,
     /*  60665 */     // GIR_Coverage, 15373,
     /*  60665 */     GIR_EraseRootFromParent_Done,
     /*  60666 */   // Label 990: @60666
     /*  60666 */   GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(60723), // Rule ID 15369 //
     /*  60671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60674 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60678 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60682 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60686 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60702 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60706 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60708 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] })), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60717 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60721 */     GIR_RootConstrainSelectedInstOperands,
     /*  60722 */     // GIR_Coverage, 15369,
     /*  60722 */     GIR_EraseRootFromParent_Done,
     /*  60723 */   // Label 991: @60723
     /*  60723 */   GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(60780), // Rule ID 15372 //
     /*  60728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60731 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60735 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60739 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60743 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60755 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60759 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60763 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60765 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] })), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60772 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  60774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60778 */     GIR_RootConstrainSelectedInstOperands,
     /*  60779 */     // GIR_Coverage, 15372,
     /*  60779 */     GIR_EraseRootFromParent_Done,
     /*  60780 */   // Label 992: @60780
     /*  60780 */   GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(60837), // Rule ID 15368 //
     /*  60785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60800 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60804 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60808 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60812 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60816 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60820 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60822 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] }), nxv8i1:{ *:[nxv8i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60827 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60829 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60835 */     GIR_RootConstrainSelectedInstOperands,
     /*  60836 */     // GIR_Coverage, 15368,
     /*  60836 */     GIR_EraseRootFromParent_Done,
     /*  60837 */   // Label 993: @60837
     /*  60837 */   GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(60894), // Rule ID 15371 //
     /*  60842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60845 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60849 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60853 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60857 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  60865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60869 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60873 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60877 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60879 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] }), nxv8i1:{ *:[nxv8i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60884 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60886 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60888 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  60892 */     GIR_RootConstrainSelectedInstOperands,
     /*  60893 */     // GIR_Coverage, 15371,
     /*  60893 */     GIR_EraseRootFromParent_Done,
     /*  60894 */   // Label 994: @60894
     /*  60894 */   GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(60951), // Rule ID 8542 //
     /*  60899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60918 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60922 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60926 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  60930 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60934 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60936 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60941 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60943 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  60945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  60949 */     GIR_RootConstrainSelectedInstOperands,
     /*  60950 */     // GIR_Coverage, 8542,
     /*  60950 */     GIR_EraseRootFromParent_Done,
     /*  60951 */   // Label 995: @60951
     /*  60951 */   GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(61008), // Rule ID 8543 //
     /*  60956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  60959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60967 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  60971 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  60975 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60979 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  60983 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  60987 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  60991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60993 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  60993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  60996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  60998 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61000 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61006 */     GIR_RootConstrainSelectedInstOperands,
     /*  61007 */     // GIR_Coverage, 8543,
     /*  61007 */     GIR_EraseRootFromParent_Done,
     /*  61008 */   // Label 996: @61008
     /*  61008 */   GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(61055), // Rule ID 10817 //
     /*  61013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61016 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  61020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  61024 */     // (and:{ *:[nxv8i1] } PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2)
     /*  61024 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  61027 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /*  61031 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  61036 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  61039 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  61041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  61044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61046 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  61049 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  61051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  61053 */     GIR_RootConstrainSelectedInstOperands,
     /*  61054 */     // GIR_Coverage, 10817,
     /*  61054 */     GIR_EraseRootFromParent_Done,
     /*  61055 */   // Label 997: @61055
     /*  61055 */   GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(61076), // Rule ID 2750 //
     /*  61060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61063 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  61063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  61066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61068 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61070 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  61074 */     GIR_RootConstrainSelectedInstOperands,
     /*  61075 */     // GIR_Coverage, 2750,
     /*  61075 */     GIR_EraseRootFromParent_Done,
     /*  61076 */   // Label 998: @61076
     /*  61076 */   GIM_Reject,
     /*  61077 */ // Label 988: @61077
     /*  61077 */ GIM_Reject,
     /*  61078 */ // Label 871: @61078
     /*  61078 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(61549),
     /*  61083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61086 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  61093 */   GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(61148), // Rule ID 15308 //
     /*  61098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61101 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61105 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61109 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61113 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61117 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61121 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61125 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61129 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61135 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61142 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61146 */     GIR_RootConstrainSelectedInstOperands,
     /*  61147 */     // GIR_Coverage, 15308,
     /*  61147 */     GIR_EraseRootFromParent_Done,
     /*  61148 */   // Label 1000: @61148
     /*  61148 */   GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(61203), // Rule ID 15311 //
     /*  61153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61172 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61176 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61180 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61184 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61188 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61190 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61195 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61197 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61201 */     GIR_RootConstrainSelectedInstOperands,
     /*  61202 */     // GIR_Coverage, 15311,
     /*  61202 */     GIR_EraseRootFromParent_Done,
     /*  61203 */   // Label 1001: @61203
     /*  61203 */   GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(61258), // Rule ID 15307 //
     /*  61208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61215 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61219 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61223 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61227 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61231 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61235 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61239 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61243 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61245 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61256 */     GIR_RootConstrainSelectedInstOperands,
     /*  61257 */     // GIR_Coverage, 15307,
     /*  61257 */     GIR_EraseRootFromParent_Done,
     /*  61258 */   // Label 1002: @61258
     /*  61258 */   GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(61313), // Rule ID 15310 //
     /*  61263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61278 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61286 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61290 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61294 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61298 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61300 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61305 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61307 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61311 */     GIR_RootConstrainSelectedInstOperands,
     /*  61312 */     // GIR_Coverage, 15310,
     /*  61312 */     GIR_EraseRootFromParent_Done,
     /*  61313 */   // Label 1003: @61313
     /*  61313 */   GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(61368), // Rule ID 15306 //
     /*  61318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61333 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61345 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61349 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61353 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61355 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61360 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61366 */     GIR_RootConstrainSelectedInstOperands,
     /*  61367 */     // GIR_Coverage, 15306,
     /*  61367 */     GIR_EraseRootFromParent_Done,
     /*  61368 */   // Label 1004: @61368
     /*  61368 */   GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(61423), // Rule ID 15309 //
     /*  61373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61380 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61384 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61388 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61392 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61396 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61400 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61404 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61408 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61410 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61415 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61417 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61421 */     GIR_RootConstrainSelectedInstOperands,
     /*  61422 */     // GIR_Coverage, 15309,
     /*  61422 */     GIR_EraseRootFromParent_Done,
     /*  61423 */   // Label 1005: @61423
     /*  61423 */   GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(61478), // Rule ID 7566 //
     /*  61428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61431 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61435 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61439 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61443 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61455 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61459 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61463 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61465 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61470 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61476 */     GIR_RootConstrainSelectedInstOperands,
     /*  61477 */     // GIR_Coverage, 7566,
     /*  61477 */     GIR_EraseRootFromParent_Done,
     /*  61478 */   // Label 1006: @61478
     /*  61478 */   GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(61533), // Rule ID 7567 //
     /*  61483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  61498 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  61502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61510 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61514 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61518 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61520 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  61523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  61525 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61531 */     GIR_RootConstrainSelectedInstOperands,
     /*  61532 */     // GIR_Coverage, 7567,
     /*  61532 */     GIR_EraseRootFromParent_Done,
     /*  61533 */   // Label 1007: @61533
     /*  61533 */   GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(61548), // Rule ID 3159 //
     /*  61538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61541 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  61541 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  61546 */     GIR_RootConstrainSelectedInstOperands,
     /*  61547 */     // GIR_Coverage, 3159,
     /*  61547 */     GIR_Done,
     /*  61548 */   // Label 1008: @61548
     /*  61548 */   GIM_Reject,
     /*  61549 */ // Label 999: @61549
     /*  61549 */ GIM_Reject,
     /*  61550 */ // Label 872: @61550
     /*  61550 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(62090),
     /*  61555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61558 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  61565 */   GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(61622), // Rule ID 15361 //
     /*  61570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61573 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61577 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61581 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61585 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61589 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61593 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61597 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61601 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61605 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61607 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] }), nxv16i1:{ *:[nxv16i1] }:$Op2), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61620 */     GIR_RootConstrainSelectedInstOperands,
     /*  61621 */     // GIR_Coverage, 15361,
     /*  61621 */     GIR_EraseRootFromParent_Done,
     /*  61622 */   // Label 1010: @61622
     /*  61622 */   GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(61679), // Rule ID 15364 //
     /*  61627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61646 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61650 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61654 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61658 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61662 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61664 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] }), nxv16i1:{ *:[nxv16i1] }:$Op2), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61669 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61673 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61677 */     GIR_RootConstrainSelectedInstOperands,
     /*  61678 */     // GIR_Coverage, 15364,
     /*  61678 */     GIR_EraseRootFromParent_Done,
     /*  61679 */   // Label 1011: @61679
     /*  61679 */   GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(61736), // Rule ID 15360 //
     /*  61684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61687 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61691 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61695 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61699 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61703 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61707 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61711 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61715 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61719 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61721 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] })), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61734 */     GIR_RootConstrainSelectedInstOperands,
     /*  61735 */     // GIR_Coverage, 15360,
     /*  61735 */     GIR_EraseRootFromParent_Done,
     /*  61736 */   // Label 1012: @61736
     /*  61736 */   GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(61793), // Rule ID 15363 //
     /*  61741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61756 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61768 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61772 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61776 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61778 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] })), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  61787 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61791 */     GIR_RootConstrainSelectedInstOperands,
     /*  61792 */     // GIR_Coverage, 15363,
     /*  61792 */     GIR_EraseRootFromParent_Done,
     /*  61793 */   // Label 1013: @61793
     /*  61793 */   GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(61850), // Rule ID 15359 //
     /*  61798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61809 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61813 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61817 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61821 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61825 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61829 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61833 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61835 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] }), nxv16i1:{ *:[nxv16i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61840 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61842 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61848 */     GIR_RootConstrainSelectedInstOperands,
     /*  61849 */     // GIR_Coverage, 15359,
     /*  61849 */     GIR_EraseRootFromParent_Done,
     /*  61850 */   // Label 1014: @61850
     /*  61850 */   GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(61907), // Rule ID 15362 //
     /*  61855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61866 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61870 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61874 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  61878 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61882 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  61886 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61890 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61892 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] }), nxv16i1:{ *:[nxv16i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61897 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61899 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61901 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  61905 */     GIR_RootConstrainSelectedInstOperands,
     /*  61906 */     // GIR_Coverage, 15362,
     /*  61906 */     GIR_EraseRootFromParent_Done,
     /*  61907 */   // Label 1015: @61907
     /*  61907 */   GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(61964), // Rule ID 8538 //
     /*  61912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61935 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61939 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  61943 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  61947 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61949 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  61949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  61952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  61954 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61956 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  61958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  61962 */     GIR_RootConstrainSelectedInstOperands,
     /*  61963 */     // GIR_Coverage, 8538,
     /*  61963 */     GIR_EraseRootFromParent_Done,
     /*  61964 */   // Label 1016: @61964
     /*  61964 */   GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(62021), // Rule ID 8539 //
     /*  61969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61972 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61976 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61980 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  61984 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  61988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61992 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  61996 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62000 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62004 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62006 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  62006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62011 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62013 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62019 */     GIR_RootConstrainSelectedInstOperands,
     /*  62020 */     // GIR_Coverage, 8539,
     /*  62020 */     GIR_EraseRootFromParent_Done,
     /*  62021 */   // Label 1017: @62021
     /*  62021 */   GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(62068), // Rule ID 10816 //
     /*  62026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62029 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  62033 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  62037 */     // (and:{ *:[nxv16i1] } PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2)
     /*  62037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  62040 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /*  62044 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  62049 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  62052 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  62054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  62057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  62062 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  62064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  62066 */     GIR_RootConstrainSelectedInstOperands,
     /*  62067 */     // GIR_Coverage, 10816,
     /*  62067 */     GIR_EraseRootFromParent_Done,
     /*  62068 */   // Label 1018: @62068
     /*  62068 */   GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(62089), // Rule ID 2749 //
     /*  62073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62076 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  62076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  62079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62081 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  62087 */     GIR_RootConstrainSelectedInstOperands,
     /*  62088 */     // GIR_Coverage, 2749,
     /*  62088 */     GIR_EraseRootFromParent_Done,
     /*  62089 */   // Label 1019: @62089
     /*  62089 */   GIM_Reject,
     /*  62090 */ // Label 1009: @62090
     /*  62090 */ GIM_Reject,
     /*  62091 */ // Label 873: @62091
     /*  62091 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(62562),
     /*  62096 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62099 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  62106 */   GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(62161), // Rule ID 15299 //
     /*  62111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62114 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62118 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62122 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62126 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62130 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62134 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62138 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62142 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62146 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62148 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62159 */     GIR_RootConstrainSelectedInstOperands,
     /*  62160 */     // GIR_Coverage, 15299,
     /*  62160 */     GIR_EraseRootFromParent_Done,
     /*  62161 */   // Label 1021: @62161
     /*  62161 */   GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(62216), // Rule ID 15302 //
     /*  62166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62177 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62181 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62185 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62189 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62193 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62197 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62201 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62203 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62214 */     GIR_RootConstrainSelectedInstOperands,
     /*  62215 */     // GIR_Coverage, 15302,
     /*  62215 */     GIR_EraseRootFromParent_Done,
     /*  62216 */   // Label 1022: @62216
     /*  62216 */   GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(62271), // Rule ID 15298 //
     /*  62221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62240 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62244 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62248 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62252 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62256 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62258 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62269 */     GIR_RootConstrainSelectedInstOperands,
     /*  62270 */     // GIR_Coverage, 15298,
     /*  62270 */     GIR_EraseRootFromParent_Done,
     /*  62271 */   // Label 1023: @62271
     /*  62271 */   GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(62326), // Rule ID 15301 //
     /*  62276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62295 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62299 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62303 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62307 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62311 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62313 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62324 */     GIR_RootConstrainSelectedInstOperands,
     /*  62325 */     // GIR_Coverage, 15301,
     /*  62325 */     GIR_EraseRootFromParent_Done,
     /*  62326 */   // Label 1024: @62326
     /*  62326 */   GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(62381), // Rule ID 15297 //
     /*  62331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62334 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62338 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62342 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62346 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62350 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62354 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62358 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62362 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62366 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62368 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62373 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62375 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62379 */     GIR_RootConstrainSelectedInstOperands,
     /*  62380 */     // GIR_Coverage, 15297,
     /*  62380 */     GIR_EraseRootFromParent_Done,
     /*  62381 */   // Label 1025: @62381
     /*  62381 */   GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(62436), // Rule ID 15300 //
     /*  62386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62401 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62405 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62409 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62413 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62417 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62421 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62423 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62428 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62434 */     GIR_RootConstrainSelectedInstOperands,
     /*  62435 */     // GIR_Coverage, 15300,
     /*  62435 */     GIR_EraseRootFromParent_Done,
     /*  62436 */   // Label 1026: @62436
     /*  62436 */   GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(62491), // Rule ID 7562 //
     /*  62441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62452 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62456 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62468 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62472 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62476 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62478 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62483 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62485 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62489 */     GIR_RootConstrainSelectedInstOperands,
     /*  62490 */     // GIR_Coverage, 7562,
     /*  62490 */     GIR_EraseRootFromParent_Done,
     /*  62491 */   // Label 1027: @62491
     /*  62491 */   GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(62546), // Rule ID 7563 //
     /*  62496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  62511 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  62515 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62519 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62523 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62527 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, uint8_t(-1),
     /*  62531 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62533 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  62536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  62538 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62540 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62544 */     GIR_RootConstrainSelectedInstOperands,
     /*  62545 */     // GIR_Coverage, 7563,
     /*  62545 */     GIR_EraseRootFromParent_Done,
     /*  62546 */   // Label 1028: @62546
     /*  62546 */   GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(62561), // Rule ID 3158 //
     /*  62551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62554 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  62554 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  62559 */     GIR_RootConstrainSelectedInstOperands,
     /*  62560 */     // GIR_Coverage, 3158,
     /*  62560 */     GIR_Done,
     /*  62561 */   // Label 1029: @62561
     /*  62561 */   GIM_Reject,
     /*  62562 */ // Label 1020: @62562
     /*  62562 */ GIM_Reject,
     /*  62563 */ // Label 874: @62563
     /*  62563 */ GIM_Reject,
     /*  62564 */ // Label 6: @62564
     /*  62564 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1048*/ GIMT_Encode4(88102),
     /*  62575 */ /*GILLT_s32*//*Label 1030*/ GIMT_Encode4(62663),
     /*  62579 */ /*GILLT_s64*//*Label 1031*/ GIMT_Encode4(63023), GIMT_Encode4(0),
     /*  62587 */ /*GILLT_v2s32*//*Label 1032*/ GIMT_Encode4(64922),
     /*  62591 */ /*GILLT_v2s64*//*Label 1033*/ GIMT_Encode4(66230),
     /*  62595 */ /*GILLT_v4s16*//*Label 1034*/ GIMT_Encode4(67538),
     /*  62599 */ /*GILLT_v4s32*//*Label 1035*/ GIMT_Encode4(68846),
     /*  62603 */ /*GILLT_v8s8*//*Label 1036*/ GIMT_Encode4(70154),
     /*  62607 */ /*GILLT_v8s16*//*Label 1037*/ GIMT_Encode4(71462),
     /*  62611 */ /*GILLT_v16s8*//*Label 1038*/ GIMT_Encode4(72770),
     /*  62615 */ /*GILLT_nxv1s1*//*Label 1039*/ GIMT_Encode4(74078),
     /*  62619 */ /*GILLT_nxv2s1*//*Label 1040*/ GIMT_Encode4(74110), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  62631 */ /*GILLT_nxv2s64*//*Label 1041*/ GIMT_Encode4(74142),
     /*  62635 */ /*GILLT_nxv4s1*//*Label 1042*/ GIMT_Encode4(77608), GIMT_Encode4(0),
     /*  62643 */ /*GILLT_nxv4s32*//*Label 1043*/ GIMT_Encode4(77640),
     /*  62647 */ /*GILLT_nxv8s1*//*Label 1044*/ GIMT_Encode4(81106),
     /*  62651 */ /*GILLT_nxv8s16*//*Label 1045*/ GIMT_Encode4(81138),
     /*  62655 */ /*GILLT_nxv16s1*//*Label 1046*/ GIMT_Encode4(84604),
     /*  62659 */ /*GILLT_nxv16s8*//*Label 1047*/ GIMT_Encode4(84636),
     /*  62663 */ // Label 1030: @62663
     /*  62663 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(63022),
     /*  62668 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  62671 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  62674 */   GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(62729), // Rule ID 13549 //
     /*  62679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62691 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  62695 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  62699 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  62703 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62707 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  62709 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  62716 */     // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  62716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
     /*  62719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  62723 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  62727 */     GIR_RootConstrainSelectedInstOperands,
     /*  62728 */     // GIR_Coverage, 13549,
     /*  62728 */     GIR_EraseRootFromParent_Done,
     /*  62729 */   // Label 1050: @62729
     /*  62729 */   GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(62784), // Rule ID 178 //
     /*  62734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62738 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62746 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62750 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  62754 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  62758 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  62762 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  62764 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  62771 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  62771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
     /*  62774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62776 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  62778 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  62782 */     GIR_RootConstrainSelectedInstOperands,
     /*  62783 */     // GIR_Coverage, 178,
     /*  62783 */     GIR_EraseRootFromParent_Done,
     /*  62784 */   // Label 1051: @62784
     /*  62784 */   GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(62825), // Rule ID 146 //
     /*  62789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  62793 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62797 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62801 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  62805 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  62809 */     // MIs[1] Operand 1
     /*  62809 */     // No operand predicates
     /*  62809 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  62811 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  62811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWri),
     /*  62814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62816 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  62818 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  62823 */     GIR_RootConstrainSelectedInstOperands,
     /*  62824 */     // GIR_Coverage, 146,
     /*  62824 */     GIR_EraseRootFromParent_Done,
     /*  62825 */   // Label 1052: @62825
     /*  62825 */   GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(62858), // Rule ID 13551 //
     /*  62830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62834 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  62845 */     // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  62845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
     /*  62848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  62852 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  62856 */     GIR_RootConstrainSelectedInstOperands,
     /*  62857 */     // GIR_Coverage, 13551,
     /*  62857 */     GIR_EraseRootFromParent_Done,
     /*  62858 */   // Label 1053: @62858
     /*  62858 */   GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(62891), // Rule ID 182 //
     /*  62863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  62878 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  62878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
     /*  62881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62883 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  62885 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  62889 */     GIR_RootConstrainSelectedInstOperands,
     /*  62890 */     // GIR_Coverage, 182,
     /*  62890 */     GIR_EraseRootFromParent_Done,
     /*  62891 */   // Label 1054: @62891
     /*  62891 */   GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(62944), // Rule ID 13547 //
     /*  62896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  62912 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  62916 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62921 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  62925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62929 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  62931 */     // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  62931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  62934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  62938 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  62942 */     GIR_RootConstrainSelectedInstOperands,
     /*  62943 */     // GIR_Coverage, 13547,
     /*  62943 */     GIR_EraseRootFromParent_Done,
     /*  62944 */   // Label 1055: @62944
     /*  62944 */   GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(62997), // Rule ID 176 //
     /*  62949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62953 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  62969 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  62973 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  62978 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  62982 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  62984 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  62984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  62987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  62989 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  62991 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  62995 */     GIR_RootConstrainSelectedInstOperands,
     /*  62996 */     // GIR_Coverage, 176,
     /*  62996 */     GIR_EraseRootFromParent_Done,
     /*  62997 */   // Label 1056: @62997
     /*  62997 */   GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(63021), // Rule ID 180 //
     /*  63002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  63006 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  63010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  63014 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  63014 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
     /*  63019 */     GIR_RootConstrainSelectedInstOperands,
     /*  63020 */     // GIR_Coverage, 180,
     /*  63020 */     GIR_Done,
     /*  63021 */   // Label 1057: @63021
     /*  63021 */   GIM_Reject,
     /*  63022 */ // Label 1049: @63022
     /*  63022 */ GIM_Reject,
     /*  63023 */ // Label 1031: @63023
     /*  63023 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(64921),
     /*  63028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  63031 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  63034 */   GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(63156), // Rule ID 4050 //
     /*  63039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63043 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63047 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63051 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63055 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63059 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63063 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  63067 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63071 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63075 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63080 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
     /*  63084 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(71777214294589695),
     /*  63095 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  63099 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63103 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*  63107 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  63111 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  63115 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  63119 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  63123 */     // MIs[4] Rn
     /*  63123 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63128 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
     /*  63132 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(-71777214294589696),
     /*  63143 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63145 */     // (or:{ *:[i64] } (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }), (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }))  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /*  63145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /*  63148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  63150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  63154 */     GIR_RootConstrainSelectedInstOperands,
     /*  63155 */     // GIR_Coverage, 4050,
     /*  63155 */     GIR_EraseRootFromParent_Done,
     /*  63156 */   // Label 1059: @63156
     /*  63156 */   GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(63278), // Rule ID 14114 //
     /*  63161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63177 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63181 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63185 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  63189 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63193 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63197 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63202 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
     /*  63206 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(-71777214294589696),
     /*  63217 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  63221 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63225 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*  63229 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  63233 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  63237 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  63241 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  63245 */     // MIs[4] Rn
     /*  63245 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63250 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
     /*  63254 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(71777214294589695),
     /*  63265 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63267 */     // (or:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }), (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }))  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /*  63267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /*  63270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  63272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  63276 */     GIR_RootConstrainSelectedInstOperands,
     /*  63277 */     // GIR_Coverage, 14114,
     /*  63277 */     GIR_EraseRootFromParent_Done,
     /*  63278 */   // Label 1060: @63278
     /*  63278 */   GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(63333), // Rule ID 13550 //
     /*  63283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63287 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63291 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63295 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63299 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63303 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  63307 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63311 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  63313 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  63320 */     // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  63320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
     /*  63323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  63325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  63327 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  63331 */     GIR_RootConstrainSelectedInstOperands,
     /*  63332 */     // GIR_Coverage, 13550,
     /*  63332 */     GIR_EraseRootFromParent_Done,
     /*  63333 */   // Label 1061: @63333
     /*  63333 */   GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(63388), // Rule ID 179 //
     /*  63338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63342 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  63346 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63350 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63354 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63358 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63362 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  63366 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  63368 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  63375 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  63375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
     /*  63378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  63380 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  63382 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  63386 */     GIR_RootConstrainSelectedInstOperands,
     /*  63387 */     // GIR_Coverage, 179,
     /*  63387 */     GIR_EraseRootFromParent_Done,
     /*  63388 */   // Label 1062: @63388
     /*  63388 */   GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(63497), // Rule ID 13909 //
     /*  63393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63412 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63424 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63428 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63432 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63437 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  63441 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  63447 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  63449 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63454 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  63458 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63462 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /*  63466 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63471 */     // MIs[4] LHS
     /*  63471 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63476 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63478 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  63478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  63481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  63483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  63487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  63491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  63495 */     GIR_RootConstrainSelectedInstOperands,
     /*  63496 */     // GIR_Coverage, 13909,
     /*  63496 */     GIR_EraseRootFromParent_Done,
     /*  63497 */   // Label 1063: @63497
     /*  63497 */   GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(63606), // Rule ID 13908 //
     /*  63502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63513 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63517 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63521 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63525 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63529 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63533 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63537 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63541 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63546 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  63550 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  63556 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  63558 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63563 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  63567 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63571 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  63575 */     // MIs[4] LHS
     /*  63575 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63580 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63585 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63587 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  63587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  63590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  63592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  63596 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  63600 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  63604 */     GIR_RootConstrainSelectedInstOperands,
     /*  63605 */     // GIR_Coverage, 13908,
     /*  63605 */     GIR_EraseRootFromParent_Done,
     /*  63606 */   // Label 1064: @63606
     /*  63606 */   GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(63715), // Rule ID 13911 //
     /*  63611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63626 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63630 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63634 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63639 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63643 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63647 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63651 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63655 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63660 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  63664 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  63670 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  63672 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  63676 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63680 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /*  63684 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63689 */     // MIs[4] LHS
     /*  63689 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63694 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63696 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  63696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  63699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  63701 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  63705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  63709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  63713 */     GIR_RootConstrainSelectedInstOperands,
     /*  63714 */     // GIR_Coverage, 13911,
     /*  63714 */     GIR_EraseRootFromParent_Done,
     /*  63715 */   // Label 1065: @63715
     /*  63715 */   GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(63824), // Rule ID 13910 //
     /*  63720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63739 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63743 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63748 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63752 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63756 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63760 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63764 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63769 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  63773 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  63779 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  63781 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  63785 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63789 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  63793 */     // MIs[4] LHS
     /*  63793 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  63798 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63803 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63805 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  63805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  63808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  63810 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  63814 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  63818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  63822 */     GIR_RootConstrainSelectedInstOperands,
     /*  63823 */     // GIR_Coverage, 13910,
     /*  63823 */     GIR_EraseRootFromParent_Done,
     /*  63824 */   // Label 1066: @63824
     /*  63824 */   GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(63933), // Rule ID 2478 //
     /*  63829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63848 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63852 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63857 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63862 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  63866 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63870 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63874 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63878 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  63882 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63886 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  63890 */     // MIs[3] LHS
     /*  63890 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  63895 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  63899 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  63905 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  63907 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63912 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  63914 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  63914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  63917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  63919 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  63923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  63927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  63931 */     GIR_RootConstrainSelectedInstOperands,
     /*  63932 */     // GIR_Coverage, 2478,
     /*  63932 */     GIR_EraseRootFromParent_Done,
     /*  63933 */   // Label 1067: @63933
     /*  63933 */   GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(64042), // Rule ID 13906 //
     /*  63938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  63941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63953 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  63957 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  63961 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63966 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  63971 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  63975 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  63979 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63983 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  63987 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  63991 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63995 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  63999 */     // MIs[3] LHS
     /*  63999 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  64004 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  64008 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64014 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  64016 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64021 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  64023 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  64023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  64026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  64032 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  64036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  64040 */     GIR_RootConstrainSelectedInstOperands,
     /*  64041 */     // GIR_Coverage, 13906,
     /*  64041 */     GIR_EraseRootFromParent_Done,
     /*  64042 */   // Label 1068: @64042
     /*  64042 */   GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(64151), // Rule ID 13905 //
     /*  64047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  64062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64070 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64080 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  64084 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  64088 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64092 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  64096 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64101 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  64105 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64109 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  64113 */     // MIs[3] LHS
     /*  64113 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  64118 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  64122 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64128 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  64130 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  64132 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  64132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  64135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  64141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  64145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  64149 */     GIR_RootConstrainSelectedInstOperands,
     /*  64150 */     // GIR_Coverage, 13905,
     /*  64150 */     GIR_EraseRootFromParent_Done,
     /*  64151 */   // Label 1069: @64151
     /*  64151 */   GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(64260), // Rule ID 13907 //
     /*  64156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  64171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64175 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64179 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64184 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64189 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  64193 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  64197 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64201 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  64205 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64210 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  64214 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64218 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  64222 */     // MIs[3] LHS
     /*  64222 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  64227 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  64231 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64237 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  64239 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  64241 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  64241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  64244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  64250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  64254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  64258 */     GIR_RootConstrainSelectedInstOperands,
     /*  64259 */     // GIR_Coverage, 13907,
     /*  64259 */     GIR_EraseRootFromParent_Done,
     /*  64260 */   // Label 1070: @64260
     /*  64260 */   GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(64301), // Rule ID 147 //
     /*  64265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  64269 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  64281 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  64285 */     // MIs[1] Operand 1
     /*  64285 */     // No operand predicates
     /*  64285 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  64287 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  64287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXri),
     /*  64290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64292 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  64294 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  64299 */     GIR_RootConstrainSelectedInstOperands,
     /*  64300 */     // GIR_Coverage, 147,
     /*  64300 */     GIR_EraseRootFromParent_Done,
     /*  64301 */   // Label 1071: @64301
     /*  64301 */   GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(64334), // Rule ID 13552 //
     /*  64306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  64321 */     // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  64321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
     /*  64324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64326 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  64328 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  64332 */     GIR_RootConstrainSelectedInstOperands,
     /*  64333 */     // GIR_Coverage, 13552,
     /*  64333 */     GIR_EraseRootFromParent_Done,
     /*  64334 */   // Label 1072: @64334
     /*  64334 */   GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(64367), // Rule ID 183 //
     /*  64339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64343 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  64354 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  64354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
     /*  64357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64359 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  64361 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  64365 */     GIR_RootConstrainSelectedInstOperands,
     /*  64366 */     // GIR_Coverage, 183,
     /*  64366 */     GIR_EraseRootFromParent_Done,
     /*  64367 */   // Label 1073: @64367
     /*  64367 */   GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(64434), // Rule ID 13845 //
     /*  64372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64379 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64383 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  64387 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64391 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64396 */     // MIs[1] imm
     /*  64396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  64404 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  64408 */     // MIs[2] Operand 1
     /*  64408 */     // No operand predicates
     /*  64408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64412 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  64416 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64418 */     // (or:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  64418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  64421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  64425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  64429 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  64432 */     GIR_RootConstrainSelectedInstOperands,
     /*  64433 */     // GIR_Coverage, 13845,
     /*  64433 */     GIR_EraseRootFromParent_Done,
     /*  64434 */   // Label 1074: @64434
     /*  64434 */   GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(64501), // Rule ID 13848 //
     /*  64439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  64454 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64458 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64463 */     // MIs[1] imm
     /*  64463 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64467 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  64471 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  64475 */     // MIs[2] Operand 1
     /*  64475 */     // No operand predicates
     /*  64475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64479 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  64483 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64485 */     // (or:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  64485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  64488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  64492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  64496 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  64499 */     GIR_RootConstrainSelectedInstOperands,
     /*  64500 */     // GIR_Coverage, 13848,
     /*  64500 */     GIR_EraseRootFromParent_Done,
     /*  64501 */   // Label 1075: @64501
     /*  64501 */   GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(64554), // Rule ID 13548 //
     /*  64506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64522 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64526 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64531 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  64535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64539 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  64541 */     // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  64541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  64544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  64548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  64552 */     GIR_RootConstrainSelectedInstOperands,
     /*  64553 */     // GIR_Coverage, 13548,
     /*  64553 */     GIR_EraseRootFromParent_Done,
     /*  64554 */   // Label 1076: @64554
     /*  64554 */   GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(64621), // Rule ID 2126 //
     /*  64559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64566 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64574 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  64578 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64582 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64587 */     // MIs[1] imm
     /*  64587 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64591 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  64595 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  64599 */     // MIs[2] Operand 1
     /*  64599 */     // No operand predicates
     /*  64599 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  64603 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64605 */     // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  64605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  64608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64610 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  64612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  64616 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  64619 */     GIR_RootConstrainSelectedInstOperands,
     /*  64620 */     // GIR_Coverage, 2126,
     /*  64620 */     GIR_EraseRootFromParent_Done,
     /*  64621 */   // Label 1077: @64621
     /*  64621 */   GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(64688), // Rule ID 2135 //
     /*  64626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  64645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64649 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64654 */     // MIs[1] imm
     /*  64654 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64658 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  64662 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  64666 */     // MIs[2] Operand 1
     /*  64666 */     // No operand predicates
     /*  64666 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  64670 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64672 */     // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  64672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  64675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  64677 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  64679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  64683 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  64686 */     GIR_RootConstrainSelectedInstOperands,
     /*  64687 */     // GIR_Coverage, 2135,
     /*  64687 */     GIR_EraseRootFromParent_Done,
     /*  64688 */   // Label 1078: @64688
     /*  64688 */   GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(64741), // Rule ID 177 //
     /*  64693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64713 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64722 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  64726 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  64728 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }))  =>  (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  64728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  64731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64733 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  64735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  64739 */     GIR_RootConstrainSelectedInstOperands,
     /*  64740 */     // GIR_Coverage, 177,
     /*  64740 */     GIR_EraseRootFromParent_Done,
     /*  64741 */   // Label 1079: @64741
     /*  64741 */   GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(64805), // Rule ID 14205 //
     /*  64746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64753 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64757 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64761 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64765 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64769 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64774 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64778 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64784 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  64786 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64790 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64792 */     // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS)  =>  (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  64792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  64795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64797 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  64799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  64803 */     GIR_RootConstrainSelectedInstOperands,
     /*  64804 */     // GIR_Coverage, 14205,
     /*  64804 */     GIR_EraseRootFromParent_Done,
     /*  64805 */   // Label 1080: @64805
     /*  64805 */   GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(64869), // Rule ID 5104 //
     /*  64810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  64833 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  64837 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64846 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64852 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  64854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64856 */     // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }))  =>  (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  64856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  64859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  64861 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  64863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  64867 */     GIR_RootConstrainSelectedInstOperands,
     /*  64868 */     // GIR_Coverage, 5104,
     /*  64868 */     GIR_EraseRootFromParent_Done,
     /*  64869 */   // Label 1081: @64869
     /*  64869 */   GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(64893), // Rule ID 181 //
     /*  64874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64878 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64882 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  64886 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  64886 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRXrr),
     /*  64891 */     GIR_RootConstrainSelectedInstOperands,
     /*  64892 */     // GIR_Coverage, 181,
     /*  64892 */     GIR_Done,
     /*  64893 */   // Label 1082: @64893
     /*  64893 */   GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(64920), // Rule ID 5110 //
     /*  64898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64905 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64909 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64913 */     // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  64913 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  64918 */     GIR_RootConstrainSelectedInstOperands,
     /*  64919 */     // GIR_Coverage, 5110,
     /*  64919 */     GIR_Done,
     /*  64920 */   // Label 1083: @64920
     /*  64920 */   GIM_Reject,
     /*  64921 */ // Label 1058: @64921
     /*  64921 */ GIM_Reject,
     /*  64922 */ // Label 1032: @64922
     /*  64922 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(66229),
     /*  64927 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  64930 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  64933 */   GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(65042), // Rule ID 13902 //
     /*  64938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  64941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  64953 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  64957 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  64961 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64965 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64969 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  64973 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  64977 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64982 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  64986 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  64992 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  64994 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  64999 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  65003 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65007 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65011 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65016 */     // MIs[4] LHS
     /*  65016 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  65021 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65023 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  65032 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  65036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  65040 */     GIR_RootConstrainSelectedInstOperands,
     /*  65041 */     // GIR_Coverage, 13902,
     /*  65041 */     GIR_EraseRootFromParent_Done,
     /*  65042 */   // Label 1085: @65042
     /*  65042 */   GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(65151), // Rule ID 13901 //
     /*  65047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65070 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65074 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65078 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65082 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65086 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65091 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  65095 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65101 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  65103 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65108 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  65112 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65116 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65120 */     // MIs[4] LHS
     /*  65120 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  65125 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65130 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65132 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  65141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  65145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  65149 */     GIR_RootConstrainSelectedInstOperands,
     /*  65150 */     // GIR_Coverage, 13901,
     /*  65150 */     GIR_EraseRootFromParent_Done,
     /*  65151 */   // Label 1086: @65151
     /*  65151 */   GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(65260), // Rule ID 13904 //
     /*  65156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65175 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65179 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65184 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65188 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65192 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65196 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65200 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65205 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  65209 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65215 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  65217 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  65221 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65225 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65229 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65234 */     // MIs[4] LHS
     /*  65234 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  65239 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65241 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  65250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  65254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  65258 */     GIR_RootConstrainSelectedInstOperands,
     /*  65259 */     // GIR_Coverage, 13904,
     /*  65259 */     GIR_EraseRootFromParent_Done,
     /*  65260 */   // Label 1087: @65260
     /*  65260 */   GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(65369), // Rule ID 13903 //
     /*  65265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65280 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65284 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65288 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65293 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65297 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65301 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65305 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65309 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65314 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  65318 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65324 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  65326 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  65330 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65334 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65338 */     // MIs[4] LHS
     /*  65338 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  65343 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65348 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65350 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65355 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  65359 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  65363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  65367 */     GIR_RootConstrainSelectedInstOperands,
     /*  65368 */     // GIR_Coverage, 13903,
     /*  65368 */     GIR_EraseRootFromParent_Done,
     /*  65369 */   // Label 1088: @65369
     /*  65369 */   GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(65478), // Rule ID 2477 //
     /*  65374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65385 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65389 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65393 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65397 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65402 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65407 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  65411 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65415 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65419 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65423 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  65427 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65431 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65435 */     // MIs[3] LHS
     /*  65435 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  65440 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  65444 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65450 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  65452 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65457 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65459 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  65468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  65472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  65476 */     GIR_RootConstrainSelectedInstOperands,
     /*  65477 */     // GIR_Coverage, 2477,
     /*  65477 */     GIR_EraseRootFromParent_Done,
     /*  65478 */   // Label 1089: @65478
     /*  65478 */   GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(65587), // Rule ID 13899 //
     /*  65483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65502 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65506 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  65520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65524 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65528 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65532 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  65536 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65540 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65544 */     // MIs[3] LHS
     /*  65544 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  65549 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  65553 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65559 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  65561 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65566 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65568 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65573 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  65577 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  65581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  65585 */     GIR_RootConstrainSelectedInstOperands,
     /*  65586 */     // GIR_Coverage, 13899,
     /*  65586 */     GIR_EraseRootFromParent_Done,
     /*  65587 */   // Label 1090: @65587
     /*  65587 */   GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(65696), // Rule ID 13898 //
     /*  65592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65611 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65615 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65620 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  65629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65633 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65637 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65641 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65646 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  65650 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65654 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65658 */     // MIs[3] LHS
     /*  65658 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  65663 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  65667 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65673 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  65675 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65677 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65682 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  65686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  65690 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  65694 */     GIR_RootConstrainSelectedInstOperands,
     /*  65695 */     // GIR_Coverage, 13898,
     /*  65695 */     GIR_EraseRootFromParent_Done,
     /*  65696 */   // Label 1091: @65696
     /*  65696 */   GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(65805), // Rule ID 13900 //
     /*  65701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65712 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65716 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65724 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65729 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65734 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  65738 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  65742 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65746 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65750 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65755 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  65759 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65763 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  65767 */     // MIs[3] LHS
     /*  65767 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  65772 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  65776 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  65782 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  65784 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  65786 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  65786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  65789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  65795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  65799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  65803 */     GIR_RootConstrainSelectedInstOperands,
     /*  65804 */     // GIR_Coverage, 13900,
     /*  65804 */     GIR_EraseRootFromParent_Done,
     /*  65805 */   // Label 1092: @65805
     /*  65805 */   GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(65872), // Rule ID 13865 //
     /*  65810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  65825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65829 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65834 */     // MIs[1] imm
     /*  65834 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65838 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  65842 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  65846 */     // MIs[2] Operand 1
     /*  65846 */     // No operand predicates
     /*  65846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65850 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  65854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65856 */     // (or:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  65856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  65859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  65863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  65867 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  65870 */     GIR_RootConstrainSelectedInstOperands,
     /*  65871 */     // GIR_Coverage, 13865,
     /*  65871 */     GIR_EraseRootFromParent_Done,
     /*  65872 */   // Label 1093: @65872
     /*  65872 */   GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(65939), // Rule ID 13886 //
     /*  65877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  65892 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65896 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65901 */     // MIs[1] imm
     /*  65901 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65905 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  65909 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  65913 */     // MIs[2] Operand 1
     /*  65913 */     // No operand predicates
     /*  65913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65917 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  65921 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65923 */     // (or:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  65923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  65926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  65930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  65934 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  65937 */     GIR_RootConstrainSelectedInstOperands,
     /*  65938 */     // GIR_Coverage, 13886,
     /*  65938 */     GIR_EraseRootFromParent_Done,
     /*  65939 */   // Label 1094: @65939
     /*  65939 */   GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(66006), // Rule ID 2243 //
     /*  65944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  65947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65951 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65955 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65959 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  65963 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  65967 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  65972 */     // MIs[1] imm
     /*  65972 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65976 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  65980 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  65984 */     // MIs[2] Operand 1
     /*  65984 */     // No operand predicates
     /*  65984 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  65988 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65990 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  65990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  65993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  65995 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  65997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  66001 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  66004 */     GIR_RootConstrainSelectedInstOperands,
     /*  66005 */     // GIR_Coverage, 2243,
     /*  66005 */     GIR_EraseRootFromParent_Done,
     /*  66006 */   // Label 1095: @66006
     /*  66006 */   GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(66073), // Rule ID 2302 //
     /*  66011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66022 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66026 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  66030 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  66034 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66039 */     // MIs[1] imm
     /*  66039 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66043 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  66047 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  66051 */     // MIs[2] Operand 1
     /*  66051 */     // No operand predicates
     /*  66051 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  66055 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66057 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  66057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  66060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66062 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  66064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  66068 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  66071 */     GIR_RootConstrainSelectedInstOperands,
     /*  66072 */     // GIR_Coverage, 2302,
     /*  66072 */     GIR_EraseRootFromParent_Done,
     /*  66073 */   // Label 1096: @66073
     /*  66073 */   GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(66137), // Rule ID 14204 //
     /*  66078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66093 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  66097 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  66101 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66106 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66110 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66116 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  66118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66122 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66124 */     // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS)  =>  (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  66124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  66127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66129 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  66131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  66135 */     GIR_RootConstrainSelectedInstOperands,
     /*  66136 */     // GIR_Coverage, 14204,
     /*  66136 */     GIR_EraseRootFromParent_Done,
     /*  66137 */   // Label 1097: @66137
     /*  66137 */   GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(66201), // Rule ID 5103 //
     /*  66142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66149 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66153 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66157 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66161 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  66165 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  66169 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66174 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66178 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66184 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  66186 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66188 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }))  =>  (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  66188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  66191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66193 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  66195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  66199 */     GIR_RootConstrainSelectedInstOperands,
     /*  66200 */     // GIR_Coverage, 5103,
     /*  66200 */     GIR_EraseRootFromParent_Done,
     /*  66201 */   // Label 1098: @66201
     /*  66201 */   GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(66228), // Rule ID 5109 //
     /*  66206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66213 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66217 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  66221 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  66221 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  66226 */     GIR_RootConstrainSelectedInstOperands,
     /*  66227 */     // GIR_Coverage, 5109,
     /*  66227 */     GIR_Done,
     /*  66228 */   // Label 1099: @66228
     /*  66228 */   GIM_Reject,
     /*  66229 */ // Label 1084: @66229
     /*  66229 */ GIM_Reject,
     /*  66230 */ // Label 1033: @66230
     /*  66230 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(67537),
     /*  66235 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66238 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66241 */   GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(66350), // Rule ID 13930 //
     /*  66246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66269 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66273 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66277 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66281 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66285 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66290 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  66294 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66300 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  66302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66307 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  66311 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66315 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66319 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66324 */     // MIs[4] LHS
     /*  66324 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  66329 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66331 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66336 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  66340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  66344 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  66348 */     GIR_RootConstrainSelectedInstOperands,
     /*  66349 */     // GIR_Coverage, 13930,
     /*  66349 */     GIR_EraseRootFromParent_Done,
     /*  66350 */   // Label 1101: @66350
     /*  66350 */   GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(66459), // Rule ID 13929 //
     /*  66355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66378 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66382 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66386 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66390 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66394 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66399 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  66403 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66409 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  66411 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66416 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  66420 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66424 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66428 */     // MIs[4] LHS
     /*  66428 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  66433 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66438 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66440 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  66449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  66453 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  66457 */     GIR_RootConstrainSelectedInstOperands,
     /*  66458 */     // GIR_Coverage, 13929,
     /*  66458 */     GIR_EraseRootFromParent_Done,
     /*  66459 */   // Label 1102: @66459
     /*  66459 */   GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(66568), // Rule ID 13932 //
     /*  66464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66471 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66475 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66479 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66483 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66487 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66492 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66496 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66500 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66504 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66508 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66513 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  66517 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66523 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  66525 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  66529 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66533 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66537 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66542 */     // MIs[4] LHS
     /*  66542 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  66547 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66549 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66554 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  66558 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  66562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  66566 */     GIR_RootConstrainSelectedInstOperands,
     /*  66567 */     // GIR_Coverage, 13932,
     /*  66567 */     GIR_EraseRootFromParent_Done,
     /*  66568 */   // Label 1103: @66568
     /*  66568 */   GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(66677), // Rule ID 13931 //
     /*  66573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66580 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66584 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66588 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66592 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66596 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66609 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66613 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66617 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66622 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  66626 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66632 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  66634 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  66638 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66642 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66646 */     // MIs[4] LHS
     /*  66646 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  66651 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66656 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66658 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  66667 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  66671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  66675 */     GIR_RootConstrainSelectedInstOperands,
     /*  66676 */     // GIR_Coverage, 13931,
     /*  66676 */     GIR_EraseRootFromParent_Done,
     /*  66677 */   // Label 1104: @66677
     /*  66677 */   GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(66786), // Rule ID 2481 //
     /*  66682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66689 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66693 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66697 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66701 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66705 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66710 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66715 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  66719 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66723 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66727 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66731 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  66735 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66739 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66743 */     // MIs[3] LHS
     /*  66743 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  66748 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  66752 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66758 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  66760 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66765 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66767 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66772 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  66776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  66780 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  66784 */     GIR_RootConstrainSelectedInstOperands,
     /*  66785 */     // GIR_Coverage, 2481,
     /*  66785 */     GIR_EraseRootFromParent_Done,
     /*  66786 */   // Label 1105: @66786
     /*  66786 */   GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(66895), // Rule ID 13927 //
     /*  66791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66802 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66806 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66810 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66814 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66819 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66824 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  66828 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66832 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66836 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66840 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  66844 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66848 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66852 */     // MIs[3] LHS
     /*  66852 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  66857 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  66861 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66867 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  66869 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66874 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66876 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  66885 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  66889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  66893 */     GIR_RootConstrainSelectedInstOperands,
     /*  66894 */     // GIR_Coverage, 13927,
     /*  66894 */     GIR_EraseRootFromParent_Done,
     /*  66895 */   // Label 1106: @66895
     /*  66895 */   GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(67004), // Rule ID 13926 //
     /*  66900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  66903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66911 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66915 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66919 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66923 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66928 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66933 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  66937 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  66941 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  66945 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66949 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  66954 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  66958 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66962 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  66966 */     // MIs[3] LHS
     /*  66966 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  66971 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  66975 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  66981 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  66983 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  66985 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  66985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  66988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  66990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  66994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  66998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  67002 */     GIR_RootConstrainSelectedInstOperands,
     /*  67003 */     // GIR_Coverage, 13926,
     /*  67003 */     GIR_EraseRootFromParent_Done,
     /*  67004 */   // Label 1107: @67004
     /*  67004 */   GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(67113), // Rule ID 13928 //
     /*  67009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67028 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  67032 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67037 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67042 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  67046 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67050 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67054 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  67058 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67063 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67067 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67071 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  67075 */     // MIs[3] LHS
     /*  67075 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  67080 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  67084 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67090 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  67092 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67094 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  67094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  67097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67099 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  67103 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  67107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  67111 */     GIR_RootConstrainSelectedInstOperands,
     /*  67112 */     // GIR_Coverage, 13928,
     /*  67112 */     GIR_EraseRootFromParent_Done,
     /*  67113 */   // Label 1108: @67113
     /*  67113 */   GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(67180), // Rule ID 13869 //
     /*  67118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67129 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  67133 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67137 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67142 */     // MIs[1] imm
     /*  67142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  67150 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  67154 */     // MIs[2] Operand 1
     /*  67154 */     // No operand predicates
     /*  67154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67158 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  67162 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67164 */     // (or:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  67164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  67167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  67171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  67175 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  67178 */     GIR_RootConstrainSelectedInstOperands,
     /*  67179 */     // GIR_Coverage, 13869,
     /*  67179 */     GIR_EraseRootFromParent_Done,
     /*  67180 */   // Label 1109: @67180
     /*  67180 */   GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(67247), // Rule ID 13890 //
     /*  67185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67192 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67196 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  67200 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67204 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67209 */     // MIs[1] imm
     /*  67209 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67213 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  67217 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  67221 */     // MIs[2] Operand 1
     /*  67221 */     // No operand predicates
     /*  67221 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67225 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  67229 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67231 */     // (or:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  67231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  67234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  67238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  67242 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  67245 */     GIR_RootConstrainSelectedInstOperands,
     /*  67246 */     // GIR_Coverage, 13890,
     /*  67246 */     GIR_EraseRootFromParent_Done,
     /*  67247 */   // Label 1110: @67247
     /*  67247 */   GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(67314), // Rule ID 2247 //
     /*  67252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67259 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  67267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  67271 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67280 */     // MIs[1] imm
     /*  67280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  67288 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  67292 */     // MIs[2] Operand 1
     /*  67292 */     // No operand predicates
     /*  67292 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  67296 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67298 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  67298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  67301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67303 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  67305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  67309 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  67312 */     GIR_RootConstrainSelectedInstOperands,
     /*  67313 */     // GIR_Coverage, 2247,
     /*  67313 */     GIR_EraseRootFromParent_Done,
     /*  67314 */   // Label 1111: @67314
     /*  67314 */   GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(67381), // Rule ID 2306 //
     /*  67319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67326 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  67334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  67338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67342 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67347 */     // MIs[1] imm
     /*  67347 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67351 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  67355 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  67359 */     // MIs[2] Operand 1
     /*  67359 */     // No operand predicates
     /*  67359 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  67363 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67365 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  67365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  67368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67370 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  67372 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  67376 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  67379 */     GIR_RootConstrainSelectedInstOperands,
     /*  67380 */     // GIR_Coverage, 2306,
     /*  67380 */     GIR_EraseRootFromParent_Done,
     /*  67381 */   // Label 1112: @67381
     /*  67381 */   GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(67445), // Rule ID 14208 //
     /*  67386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67393 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67397 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67401 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67405 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  67409 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67418 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67424 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  67426 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67430 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67432 */     // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS)  =>  (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  67432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  67435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67437 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  67439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67443 */     GIR_RootConstrainSelectedInstOperands,
     /*  67444 */     // GIR_Coverage, 14208,
     /*  67444 */     GIR_EraseRootFromParent_Done,
     /*  67445 */   // Label 1113: @67445
     /*  67445 */   GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(67509), // Rule ID 5107 //
     /*  67450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67457 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  67465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  67473 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  67477 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67482 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67486 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67492 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  67494 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  67496 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }))  =>  (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  67496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  67499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67501 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  67503 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67507 */     GIR_RootConstrainSelectedInstOperands,
     /*  67508 */     // GIR_Coverage, 5107,
     /*  67508 */     GIR_EraseRootFromParent_Done,
     /*  67509 */   // Label 1114: @67509
     /*  67509 */   GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(67536), // Rule ID 5113 //
     /*  67514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67521 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67525 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  67529 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  67529 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  67534 */     GIR_RootConstrainSelectedInstOperands,
     /*  67535 */     // GIR_Coverage, 5113,
     /*  67535 */     GIR_Done,
     /*  67536 */   // Label 1115: @67536
     /*  67536 */   GIM_Reject,
     /*  67537 */ // Label 1100: @67537
     /*  67537 */ GIM_Reject,
     /*  67538 */ // Label 1034: @67538
     /*  67538 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(68845),
     /*  67543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67546 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67549 */   GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(67658), // Rule ID 13895 //
     /*  67554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67569 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67573 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67577 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67581 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67585 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67589 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67593 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67598 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67602 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67608 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67615 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67619 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67623 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67627 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67632 */     // MIs[4] LHS
     /*  67632 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67637 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67639 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  67639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67648 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  67652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  67656 */     GIR_RootConstrainSelectedInstOperands,
     /*  67657 */     // GIR_Coverage, 13895,
     /*  67657 */     GIR_EraseRootFromParent_Done,
     /*  67658 */   // Label 1117: @67658
     /*  67658 */   GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(67767), // Rule ID 13894 //
     /*  67663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67686 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67690 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67694 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67698 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67702 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67707 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67711 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67717 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67719 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67724 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67728 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67732 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67736 */     // MIs[4] LHS
     /*  67736 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67741 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67746 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67748 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  67748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  67761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  67765 */     GIR_RootConstrainSelectedInstOperands,
     /*  67766 */     // GIR_Coverage, 13894,
     /*  67766 */     GIR_EraseRootFromParent_Done,
     /*  67767 */   // Label 1118: @67767
     /*  67767 */   GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(67876), // Rule ID 13897 //
     /*  67772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67787 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67791 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67795 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67800 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67804 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67808 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67812 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67821 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67825 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67831 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67833 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67837 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67841 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67845 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67850 */     // MIs[4] LHS
     /*  67850 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67855 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67857 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  67857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67862 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67866 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  67870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67874 */     GIR_RootConstrainSelectedInstOperands,
     /*  67875 */     // GIR_Coverage, 13897,
     /*  67875 */     GIR_EraseRootFromParent_Done,
     /*  67876 */   // Label 1119: @67876
     /*  67876 */   GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(67985), // Rule ID 13896 //
     /*  67881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67904 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67909 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67913 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67917 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  67921 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67925 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67930 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67934 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67940 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67942 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67946 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67950 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  67954 */     // MIs[4] LHS
     /*  67954 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67959 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67964 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67966 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  67966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  67979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67983 */     GIR_RootConstrainSelectedInstOperands,
     /*  67984 */     // GIR_Coverage, 13896,
     /*  67984 */     GIR_EraseRootFromParent_Done,
     /*  67985 */   // Label 1120: @67985
     /*  67985 */   GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(68094), // Rule ID 2476 //
     /*  67990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68005 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68009 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68013 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68018 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68031 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68035 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68039 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  68043 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68047 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68051 */     // MIs[3] LHS
     /*  68051 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  68056 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68060 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68066 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68068 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68073 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68075 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  68075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68080 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  68084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  68088 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  68092 */     GIR_RootConstrainSelectedInstOperands,
     /*  68093 */     // GIR_Coverage, 2476,
     /*  68093 */     GIR_EraseRootFromParent_Done,
     /*  68094 */   // Label 1121: @68094
     /*  68094 */   GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(68203), // Rule ID 13892 //
     /*  68099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68122 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68132 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68136 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68140 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68144 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68148 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  68152 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68156 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68160 */     // MIs[3] LHS
     /*  68160 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  68165 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68169 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68175 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68177 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68182 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68184 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  68184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  68193 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  68197 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  68201 */     GIR_RootConstrainSelectedInstOperands,
     /*  68202 */     // GIR_Coverage, 13892,
     /*  68202 */     GIR_EraseRootFromParent_Done,
     /*  68203 */   // Label 1122: @68203
     /*  68203 */   GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(68312), // Rule ID 13891 //
     /*  68208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68215 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68219 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68223 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68227 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68231 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68236 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68241 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68245 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68249 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68253 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68257 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68262 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68266 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68270 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68274 */     // MIs[3] LHS
     /*  68274 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  68279 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68283 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68289 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68291 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68293 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  68293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68298 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  68302 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  68306 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  68310 */     GIR_RootConstrainSelectedInstOperands,
     /*  68311 */     // GIR_Coverage, 13891,
     /*  68311 */     GIR_EraseRootFromParent_Done,
     /*  68312 */   // Label 1123: @68312
     /*  68312 */   GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(68421), // Rule ID 13893 //
     /*  68317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68328 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68332 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68336 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68340 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68345 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68350 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68354 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68358 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68362 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68366 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68371 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68375 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68379 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68383 */     // MIs[3] LHS
     /*  68383 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  68388 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68392 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68398 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68400 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68402 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  68402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  68411 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  68415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  68419 */     GIR_RootConstrainSelectedInstOperands,
     /*  68420 */     // GIR_Coverage, 13893,
     /*  68420 */     GIR_EraseRootFromParent_Done,
     /*  68421 */   // Label 1124: @68421
     /*  68421 */   GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(68488), // Rule ID 13861 //
     /*  68426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68437 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  68441 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68445 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68450 */     // MIs[1] imm
     /*  68450 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68454 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  68458 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  68462 */     // MIs[2] Operand 1
     /*  68462 */     // No operand predicates
     /*  68462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68466 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68470 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68472 */     // (or:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  68472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  68475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  68479 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68483 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  68486 */     GIR_RootConstrainSelectedInstOperands,
     /*  68487 */     // GIR_Coverage, 13861,
     /*  68487 */     GIR_EraseRootFromParent_Done,
     /*  68488 */   // Label 1125: @68488
     /*  68488 */   GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(68555), // Rule ID 13882 //
     /*  68493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68500 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68504 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  68508 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68512 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68517 */     // MIs[1] imm
     /*  68517 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68521 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  68525 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  68529 */     // MIs[2] Operand 1
     /*  68529 */     // No operand predicates
     /*  68529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68533 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68537 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68539 */     // (or:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  68539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  68542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  68546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68550 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  68553 */     GIR_RootConstrainSelectedInstOperands,
     /*  68554 */     // GIR_Coverage, 13882,
     /*  68554 */     GIR_EraseRootFromParent_Done,
     /*  68555 */   // Label 1126: @68555
     /*  68555 */   GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(68622), // Rule ID 2239 //
     /*  68560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  68579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68583 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68588 */     // MIs[1] imm
     /*  68588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  68596 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  68600 */     // MIs[2] Operand 1
     /*  68600 */     // No operand predicates
     /*  68600 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68604 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68606 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  68606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  68609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68611 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  68613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68617 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  68620 */     GIR_RootConstrainSelectedInstOperands,
     /*  68621 */     // GIR_Coverage, 2239,
     /*  68621 */     GIR_EraseRootFromParent_Done,
     /*  68622 */   // Label 1127: @68622
     /*  68622 */   GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(68689), // Rule ID 2298 //
     /*  68627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68634 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68642 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  68646 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68650 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68655 */     // MIs[1] imm
     /*  68655 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68659 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  68663 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  68667 */     // MIs[2] Operand 1
     /*  68667 */     // No operand predicates
     /*  68667 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68671 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68673 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  68673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  68676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68678 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  68680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68684 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  68687 */     GIR_RootConstrainSelectedInstOperands,
     /*  68688 */     // GIR_Coverage, 2298,
     /*  68688 */     GIR_EraseRootFromParent_Done,
     /*  68689 */   // Label 1128: @68689
     /*  68689 */   GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(68753), // Rule ID 14203 //
     /*  68694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68713 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68722 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68726 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68732 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  68734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68738 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68740 */     // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS)  =>  (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  68740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  68743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68745 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  68747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  68751 */     GIR_RootConstrainSelectedInstOperands,
     /*  68752 */     // GIR_Coverage, 14203,
     /*  68752 */     GIR_EraseRootFromParent_Done,
     /*  68753 */   // Label 1129: @68753
     /*  68753 */   GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(68817), // Rule ID 5102 //
     /*  68758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  68781 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  68785 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68794 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68800 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  68802 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68804 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }))  =>  (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  68804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  68807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68809 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  68811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  68815 */     GIR_RootConstrainSelectedInstOperands,
     /*  68816 */     // GIR_Coverage, 5102,
     /*  68816 */     GIR_EraseRootFromParent_Done,
     /*  68817 */   // Label 1130: @68817
     /*  68817 */   GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(68844), // Rule ID 5108 //
     /*  68822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68829 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68837 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  68837 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  68842 */     GIR_RootConstrainSelectedInstOperands,
     /*  68843 */     // GIR_Coverage, 5108,
     /*  68843 */     GIR_Done,
     /*  68844 */   // Label 1131: @68844
     /*  68844 */   GIM_Reject,
     /*  68845 */ // Label 1116: @68845
     /*  68845 */ GIM_Reject,
     /*  68846 */ // Label 1035: @68846
     /*  68846 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(70153),
     /*  68851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  68854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  68857 */   GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(68966), // Rule ID 13923 //
     /*  68862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  68869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  68881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  68885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  68889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  68897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  68901 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  68906 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68910 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68916 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  68918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  68923 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  68927 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68931 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  68935 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  68940 */     // MIs[4] LHS
     /*  68940 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  68945 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68947 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  68947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  68950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  68956 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  68960 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  68964 */     GIR_RootConstrainSelectedInstOperands,
     /*  68965 */     // GIR_Coverage, 13923,
     /*  68965 */     GIR_EraseRootFromParent_Done,
     /*  68966 */   // Label 1133: @68966
     /*  68966 */   GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(69075), // Rule ID 13922 //
     /*  68971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  68978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68986 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  68990 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  68994 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  68998 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69002 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69006 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69010 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69015 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69019 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69025 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69032 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69036 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69040 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69044 */     // MIs[4] LHS
     /*  69044 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69049 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69054 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69056 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  69069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  69073 */     GIR_RootConstrainSelectedInstOperands,
     /*  69074 */     // GIR_Coverage, 13922,
     /*  69074 */     GIR_EraseRootFromParent_Done,
     /*  69075 */   // Label 1134: @69075
     /*  69075 */   GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(69184), // Rule ID 13925 //
     /*  69080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69087 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69091 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69095 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69099 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69103 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69108 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69112 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69116 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69120 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69124 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69129 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69133 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69139 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69141 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69145 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69149 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69153 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69158 */     // MIs[4] LHS
     /*  69158 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69163 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69165 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69174 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  69178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  69182 */     GIR_RootConstrainSelectedInstOperands,
     /*  69183 */     // GIR_Coverage, 13925,
     /*  69183 */     GIR_EraseRootFromParent_Done,
     /*  69184 */   // Label 1135: @69184
     /*  69184 */   GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(69293), // Rule ID 13924 //
     /*  69189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69196 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69200 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69204 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69208 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69212 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69217 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69221 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69225 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69229 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69233 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69238 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69242 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69248 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69250 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69254 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69258 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69262 */     // MIs[4] LHS
     /*  69262 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69267 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69272 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69274 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69283 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  69287 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  69291 */     GIR_RootConstrainSelectedInstOperands,
     /*  69292 */     // GIR_Coverage, 13924,
     /*  69292 */     GIR_EraseRootFromParent_Done,
     /*  69293 */   // Label 1136: @69293
     /*  69293 */   GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(69402), // Rule ID 2480 //
     /*  69298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69305 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69309 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69313 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69317 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69321 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69326 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69339 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69343 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69347 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  69351 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69355 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69359 */     // MIs[3] LHS
     /*  69359 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  69364 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69368 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69374 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69376 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69381 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69383 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69388 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  69392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  69396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  69400 */     GIR_RootConstrainSelectedInstOperands,
     /*  69401 */     // GIR_Coverage, 2480,
     /*  69401 */     GIR_EraseRootFromParent_Done,
     /*  69402 */   // Label 1137: @69402
     /*  69402 */   GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(69511), // Rule ID 13920 //
     /*  69407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69426 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69435 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69440 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69444 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69448 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69452 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69456 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  69460 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69464 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69468 */     // MIs[3] LHS
     /*  69468 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  69473 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69477 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69483 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69485 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69490 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69492 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69497 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  69501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  69505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  69509 */     GIR_RootConstrainSelectedInstOperands,
     /*  69510 */     // GIR_Coverage, 13920,
     /*  69510 */     GIR_EraseRootFromParent_Done,
     /*  69511 */   // Label 1138: @69511
     /*  69511 */   GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(69620), // Rule ID 13919 //
     /*  69516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69531 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69535 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69539 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69544 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69549 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69553 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69557 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69561 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69565 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69570 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69574 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69578 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69582 */     // MIs[3] LHS
     /*  69582 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  69587 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69591 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69597 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69599 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69601 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  69610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  69614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  69618 */     GIR_RootConstrainSelectedInstOperands,
     /*  69619 */     // GIR_Coverage, 13919,
     /*  69619 */     GIR_EraseRootFromParent_Done,
     /*  69620 */   // Label 1139: @69620
     /*  69620 */   GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(69729), // Rule ID 13921 //
     /*  69625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69640 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69644 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69648 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69653 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69658 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69662 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69666 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69670 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69674 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69679 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69683 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69687 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  69691 */     // MIs[3] LHS
     /*  69691 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  69696 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69700 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69706 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69708 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69710 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  69710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  69713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69715 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  69719 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  69723 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  69727 */     GIR_RootConstrainSelectedInstOperands,
     /*  69728 */     // GIR_Coverage, 13921,
     /*  69728 */     GIR_EraseRootFromParent_Done,
     /*  69729 */   // Label 1140: @69729
     /*  69729 */   GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(69796), // Rule ID 13867 //
     /*  69734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69741 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69745 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  69749 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69758 */     // MIs[1] imm
     /*  69758 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69762 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  69766 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69770 */     // MIs[2] Operand 1
     /*  69770 */     // No operand predicates
     /*  69770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69774 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69778 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  69780 */     // (or:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  69780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  69783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  69787 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69791 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  69794 */     GIR_RootConstrainSelectedInstOperands,
     /*  69795 */     // GIR_Coverage, 13867,
     /*  69795 */     GIR_EraseRootFromParent_Done,
     /*  69796 */   // Label 1141: @69796
     /*  69796 */   GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(69863), // Rule ID 13888 //
     /*  69801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  69816 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69820 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69825 */     // MIs[1] imm
     /*  69825 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69829 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  69833 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69837 */     // MIs[2] Operand 1
     /*  69837 */     // No operand predicates
     /*  69837 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69841 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69845 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  69847 */     // (or:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  69847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  69850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  69854 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69858 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  69861 */     GIR_RootConstrainSelectedInstOperands,
     /*  69862 */     // GIR_Coverage, 13888,
     /*  69862 */     GIR_EraseRootFromParent_Done,
     /*  69863 */   // Label 1142: @69863
     /*  69863 */   GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(69930), // Rule ID 2245 //
     /*  69868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  69883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  69887 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69891 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69896 */     // MIs[1] imm
     /*  69896 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69900 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  69904 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69908 */     // MIs[2] Operand 1
     /*  69908 */     // No operand predicates
     /*  69908 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69912 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  69914 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  69914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  69917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69919 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  69921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69925 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  69928 */     GIR_RootConstrainSelectedInstOperands,
     /*  69929 */     // GIR_Coverage, 2245,
     /*  69929 */     GIR_EraseRootFromParent_Done,
     /*  69930 */   // Label 1143: @69930
     /*  69930 */   GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(69997), // Rule ID 2304 //
     /*  69935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69942 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69946 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  69950 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  69954 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  69958 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  69963 */     // MIs[1] imm
     /*  69963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  69971 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69975 */     // MIs[2] Operand 1
     /*  69975 */     // No operand predicates
     /*  69975 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69979 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  69981 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  69981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  69984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69986 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  69988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69992 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  69995 */     GIR_RootConstrainSelectedInstOperands,
     /*  69996 */     // GIR_Coverage, 2304,
     /*  69996 */     GIR_EraseRootFromParent_Done,
     /*  69997 */   // Label 1144: @69997
     /*  69997 */   GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(70061), // Rule ID 14207 //
     /*  70002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70009 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70013 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70017 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  70021 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  70025 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70030 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70034 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70040 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  70042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70046 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  70048 */     // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS)  =>  (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  70048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  70051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  70053 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  70055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70059 */     GIR_RootConstrainSelectedInstOperands,
     /*  70060 */     // GIR_Coverage, 14207,
     /*  70060 */     GIR_EraseRootFromParent_Done,
     /*  70061 */   // Label 1145: @70061
     /*  70061 */   GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(70125), // Rule ID 5106 //
     /*  70066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70073 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  70081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  70089 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  70093 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70098 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70102 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70108 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  70110 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  70112 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }))  =>  (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  70112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  70115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  70117 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  70119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70123 */     GIR_RootConstrainSelectedInstOperands,
     /*  70124 */     // GIR_Coverage, 5106,
     /*  70124 */     GIR_EraseRootFromParent_Done,
     /*  70125 */   // Label 1146: @70125
     /*  70125 */   GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(70152), // Rule ID 5112 //
     /*  70130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70137 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70141 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70145 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  70145 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  70150 */     GIR_RootConstrainSelectedInstOperands,
     /*  70151 */     // GIR_Coverage, 5112,
     /*  70151 */     GIR_Done,
     /*  70152 */   // Label 1147: @70152
     /*  70152 */   GIM_Reject,
     /*  70153 */ // Label 1132: @70153
     /*  70153 */ GIM_Reject,
     /*  70154 */ // Label 1036: @70154
     /*  70154 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(71461),
     /*  70159 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70162 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70165 */   GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(70274), // Rule ID 13673 //
     /*  70170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70193 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  70197 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70201 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70205 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70209 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70214 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70218 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70224 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70231 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70235 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70239 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70243 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70248 */     // MIs[4] Rd
     /*  70248 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70253 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70255 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70260 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  70264 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  70268 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  70272 */     GIR_RootConstrainSelectedInstOperands,
     /*  70273 */     // GIR_Coverage, 13673,
     /*  70273 */     GIR_EraseRootFromParent_Done,
     /*  70274 */   // Label 1149: @70274
     /*  70274 */   GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(70383), // Rule ID 13672 //
     /*  70279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70294 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70298 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70302 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  70306 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70310 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70314 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70318 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70323 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70327 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70333 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70335 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70340 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70344 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70348 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70352 */     // MIs[4] Rd
     /*  70352 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70357 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70362 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70364 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  70373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  70377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  70381 */     GIR_RootConstrainSelectedInstOperands,
     /*  70382 */     // GIR_Coverage, 13672,
     /*  70382 */     GIR_EraseRootFromParent_Done,
     /*  70383 */   // Label 1150: @70383
     /*  70383 */   GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(70492), // Rule ID 13675 //
     /*  70388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70395 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70399 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70403 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70407 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70411 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70424 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70428 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70432 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70437 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70441 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70447 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70449 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70453 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70457 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70461 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70466 */     // MIs[4] Rd
     /*  70466 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70471 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70473 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  70482 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  70486 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  70490 */     GIR_RootConstrainSelectedInstOperands,
     /*  70491 */     // GIR_Coverage, 13675,
     /*  70491 */     GIR_EraseRootFromParent_Done,
     /*  70492 */   // Label 1151: @70492
     /*  70492 */   GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(70601), // Rule ID 13674 //
     /*  70497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70520 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70525 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70529 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70533 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70537 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70541 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70546 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70550 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70556 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70558 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70562 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70566 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70570 */     // MIs[4] Rd
     /*  70570 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70575 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70580 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70582 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  70591 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  70595 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  70599 */     GIR_RootConstrainSelectedInstOperands,
     /*  70600 */     // GIR_Coverage, 13674,
     /*  70600 */     GIR_EraseRootFromParent_Done,
     /*  70601 */   // Label 1152: @70601
     /*  70601 */   GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(70710), // Rule ID 1609 //
     /*  70606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70613 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70617 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70621 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70625 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70629 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70634 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70639 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70643 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70647 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70651 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70655 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  70659 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70663 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70667 */     // MIs[3] Rd
     /*  70667 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  70672 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70676 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70682 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70684 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70689 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70691 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  70700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  70704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  70708 */     GIR_RootConstrainSelectedInstOperands,
     /*  70709 */     // GIR_Coverage, 1609,
     /*  70709 */     GIR_EraseRootFromParent_Done,
     /*  70710 */   // Label 1153: @70710
     /*  70710 */   GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(70819), // Rule ID 13670 //
     /*  70715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70730 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70734 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70738 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70743 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70748 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70752 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70756 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70760 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70764 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  70768 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70772 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70776 */     // MIs[3] Rd
     /*  70776 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  70781 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70785 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70791 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70793 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70798 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70800 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  70809 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  70813 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  70817 */     GIR_RootConstrainSelectedInstOperands,
     /*  70818 */     // GIR_Coverage, 13670,
     /*  70818 */     GIR_EraseRootFromParent_Done,
     /*  70819 */   // Label 1154: @70819
     /*  70819 */   GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(70928), // Rule ID 13669 //
     /*  70824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70831 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70835 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70839 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70843 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70847 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70852 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70857 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70861 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70865 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70869 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70873 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70878 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70882 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70886 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70890 */     // MIs[3] Rd
     /*  70890 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  70895 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70899 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70905 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70907 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70909 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  70909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  70912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  70918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  70922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  70926 */     GIR_RootConstrainSelectedInstOperands,
     /*  70927 */     // GIR_Coverage, 13669,
     /*  70927 */     GIR_EraseRootFromParent_Done,
     /*  70928 */   // Label 1155: @70928
     /*  70928 */   GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(71037), // Rule ID 13671 //
     /*  70933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70952 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70956 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70961 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70966 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70970 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70974 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  70978 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70982 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70987 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70991 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70995 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  70999 */     // MIs[3] Rd
     /*  70999 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  71004 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  71008 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71014 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  71016 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71018 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  71018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  71021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71023 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  71027 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71031 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  71035 */     GIR_RootConstrainSelectedInstOperands,
     /*  71036 */     // GIR_Coverage, 13671,
     /*  71036 */     GIR_EraseRootFromParent_Done,
     /*  71037 */   // Label 1156: @71037
     /*  71037 */   GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(71104), // Rule ID 13857 //
     /*  71042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71049 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71053 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  71057 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71061 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71066 */     // MIs[1] imm
     /*  71066 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71070 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  71074 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  71078 */     // MIs[2] Operand 1
     /*  71078 */     // No operand predicates
     /*  71078 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71082 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71086 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71088 */     // (or:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  71088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  71091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  71095 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71099 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  71102 */     GIR_RootConstrainSelectedInstOperands,
     /*  71103 */     // GIR_Coverage, 13857,
     /*  71103 */     GIR_EraseRootFromParent_Done,
     /*  71104 */   // Label 1157: @71104
     /*  71104 */   GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(71171), // Rule ID 13878 //
     /*  71109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  71124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71128 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71133 */     // MIs[1] imm
     /*  71133 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71137 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  71141 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  71145 */     // MIs[2] Operand 1
     /*  71145 */     // No operand predicates
     /*  71145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71149 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71153 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71155 */     // (or:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  71155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  71158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71160 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  71162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71166 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  71169 */     GIR_RootConstrainSelectedInstOperands,
     /*  71170 */     // GIR_Coverage, 13878,
     /*  71170 */     GIR_EraseRootFromParent_Done,
     /*  71171 */   // Label 1158: @71171
     /*  71171 */   GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(71238), // Rule ID 2235 //
     /*  71176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71183 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71187 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71191 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  71195 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71199 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71204 */     // MIs[1] imm
     /*  71204 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71208 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  71212 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  71216 */     // MIs[2] Operand 1
     /*  71216 */     // No operand predicates
     /*  71216 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71220 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71222 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  71222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  71225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71227 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  71229 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71233 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  71236 */     GIR_RootConstrainSelectedInstOperands,
     /*  71237 */     // GIR_Coverage, 2235,
     /*  71237 */     GIR_EraseRootFromParent_Done,
     /*  71238 */   // Label 1159: @71238
     /*  71238 */   GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(71305), // Rule ID 2294 //
     /*  71243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71250 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  71262 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71266 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71271 */     // MIs[1] imm
     /*  71271 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71275 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  71279 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  71283 */     // MIs[2] Operand 1
     /*  71283 */     // No operand predicates
     /*  71283 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71287 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71289 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  71289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  71292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71294 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  71296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71300 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  71303 */     GIR_RootConstrainSelectedInstOperands,
     /*  71304 */     // GIR_Coverage, 2294,
     /*  71304 */     GIR_EraseRootFromParent_Done,
     /*  71305 */   // Label 1160: @71305
     /*  71305 */   GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(71369), // Rule ID 13667 //
     /*  71310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71317 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71325 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71329 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  71333 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71338 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71342 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71348 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  71350 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71354 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71356 */     // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn)  =>  (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  71356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  71359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  71361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  71363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  71367 */     GIR_RootConstrainSelectedInstOperands,
     /*  71368 */     // GIR_Coverage, 13667,
     /*  71368 */     GIR_EraseRootFromParent_Done,
     /*  71369 */   // Label 1161: @71369
     /*  71369 */   GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(71433), // Rule ID 1605 //
     /*  71374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71381 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  71397 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  71401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71406 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71410 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71416 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  71418 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71420 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }))  =>  (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  71420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  71423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  71425 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  71427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  71431 */     GIR_RootConstrainSelectedInstOperands,
     /*  71432 */     // GIR_Coverage, 1605,
     /*  71432 */     GIR_EraseRootFromParent_Done,
     /*  71433 */   // Label 1162: @71433
     /*  71433 */   GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(71460), // Rule ID 1607 //
     /*  71438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71445 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71453 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  71453 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  71458 */     GIR_RootConstrainSelectedInstOperands,
     /*  71459 */     // GIR_Coverage, 1607,
     /*  71459 */     GIR_Done,
     /*  71460 */   // Label 1163: @71460
     /*  71460 */   GIM_Reject,
     /*  71461 */ // Label 1148: @71461
     /*  71461 */ GIM_Reject,
     /*  71462 */ // Label 1037: @71462
     /*  71462 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(72769),
     /*  71467 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71470 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71473 */   GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(71582), // Rule ID 13916 //
     /*  71478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71497 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71501 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  71505 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71509 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71513 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71517 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71522 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71526 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71532 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71534 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71539 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71543 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71547 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71551 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71556 */     // MIs[4] LHS
     /*  71556 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71561 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71563 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  71563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  71566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71568 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71572 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  71576 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  71580 */     GIR_RootConstrainSelectedInstOperands,
     /*  71581 */     // GIR_Coverage, 13916,
     /*  71581 */     GIR_EraseRootFromParent_Done,
     /*  71582 */   // Label 1165: @71582
     /*  71582 */   GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(71691), // Rule ID 13915 //
     /*  71587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71594 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71598 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71602 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71606 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71610 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  71614 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71618 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71622 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71626 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71631 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71635 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71641 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71643 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71648 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71652 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71656 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71660 */     // MIs[4] LHS
     /*  71660 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71665 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71670 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71672 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  71672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  71675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  71685 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  71689 */     GIR_RootConstrainSelectedInstOperands,
     /*  71690 */     // GIR_Coverage, 13915,
     /*  71690 */     GIR_EraseRootFromParent_Done,
     /*  71691 */   // Label 1166: @71691
     /*  71691 */   GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(71800), // Rule ID 13918 //
     /*  71696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71703 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71707 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71711 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71715 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71719 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71724 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71728 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71732 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71736 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71740 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71745 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71749 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71755 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71757 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71761 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71765 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71769 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71774 */     // MIs[4] LHS
     /*  71774 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71779 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71781 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  71781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  71784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71786 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  71794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71798 */     GIR_RootConstrainSelectedInstOperands,
     /*  71799 */     // GIR_Coverage, 13918,
     /*  71799 */     GIR_EraseRootFromParent_Done,
     /*  71800 */   // Label 1167: @71800
     /*  71800 */   GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(71909), // Rule ID 13917 //
     /*  71805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71812 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71816 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71820 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71824 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71828 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71833 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71837 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71841 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71845 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71849 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71854 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71858 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71864 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71866 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71870 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71874 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71878 */     // MIs[4] LHS
     /*  71878 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71883 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71888 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71890 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  71890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  71893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71899 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  71903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71907 */     GIR_RootConstrainSelectedInstOperands,
     /*  71908 */     // GIR_Coverage, 13917,
     /*  71908 */     GIR_EraseRootFromParent_Done,
     /*  71909 */   // Label 1168: @71909
     /*  71909 */   GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(72018), // Rule ID 2479 //
     /*  71914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71933 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71937 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71942 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71947 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  71951 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71955 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  71959 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71963 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  71967 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71971 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  71975 */     // MIs[3] LHS
     /*  71975 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  71980 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  71984 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71990 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  71992 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71997 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71999 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  71999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72004 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  72008 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  72012 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  72016 */     GIR_RootConstrainSelectedInstOperands,
     /*  72017 */     // GIR_Coverage, 2479,
     /*  72017 */     GIR_EraseRootFromParent_Done,
     /*  72018 */   // Label 1169: @72018
     /*  72018 */   GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(72127), // Rule ID 13913 //
     /*  72023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72030 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72034 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72038 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72042 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72046 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72051 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72056 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72060 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72064 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72068 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72072 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  72076 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72080 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72084 */     // MIs[3] LHS
     /*  72084 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  72089 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72093 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72099 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72101 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72106 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72108 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  72108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  72117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  72121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  72125 */     GIR_RootConstrainSelectedInstOperands,
     /*  72126 */     // GIR_Coverage, 13913,
     /*  72126 */     GIR_EraseRootFromParent_Done,
     /*  72127 */   // Label 1170: @72127
     /*  72127 */   GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(72236), // Rule ID 13912 //
     /*  72132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72151 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72155 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72160 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72173 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72177 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72181 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72186 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72190 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72194 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72198 */     // MIs[3] LHS
     /*  72198 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  72203 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72207 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72213 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72215 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72217 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  72217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72222 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  72226 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  72230 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  72234 */     GIR_RootConstrainSelectedInstOperands,
     /*  72235 */     // GIR_Coverage, 13912,
     /*  72235 */     GIR_EraseRootFromParent_Done,
     /*  72236 */   // Label 1171: @72236
     /*  72236 */   GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(72345), // Rule ID 13914 //
     /*  72241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72248 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72252 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72256 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72260 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72264 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72269 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72274 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72278 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72282 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72286 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72290 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72295 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72299 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72303 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72307 */     // MIs[3] LHS
     /*  72307 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  72312 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72316 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72322 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72324 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72326 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  72326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72331 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  72335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  72339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  72343 */     GIR_RootConstrainSelectedInstOperands,
     /*  72344 */     // GIR_Coverage, 13914,
     /*  72344 */     GIR_EraseRootFromParent_Done,
     /*  72345 */   // Label 1172: @72345
     /*  72345 */   GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(72412), // Rule ID 13863 //
     /*  72350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  72365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72369 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72374 */     // MIs[1] imm
     /*  72374 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72378 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  72382 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72386 */     // MIs[2] Operand 1
     /*  72386 */     // No operand predicates
     /*  72386 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72390 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72394 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72396 */     // (or:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  72396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  72399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  72403 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72407 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  72410 */     GIR_RootConstrainSelectedInstOperands,
     /*  72411 */     // GIR_Coverage, 13863,
     /*  72411 */     GIR_EraseRootFromParent_Done,
     /*  72412 */   // Label 1173: @72412
     /*  72412 */   GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(72479), // Rule ID 13884 //
     /*  72417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72428 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  72432 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72436 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72441 */     // MIs[1] imm
     /*  72441 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72445 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  72449 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72453 */     // MIs[2] Operand 1
     /*  72453 */     // No operand predicates
     /*  72453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72457 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72461 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72463 */     // (or:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  72463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  72466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  72470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72474 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  72477 */     GIR_RootConstrainSelectedInstOperands,
     /*  72478 */     // GIR_Coverage, 13884,
     /*  72478 */     GIR_EraseRootFromParent_Done,
     /*  72479 */   // Label 1174: @72479
     /*  72479 */   GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(72546), // Rule ID 2241 //
     /*  72484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72491 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  72503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72507 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72512 */     // MIs[1] imm
     /*  72512 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72516 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  72520 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72524 */     // MIs[2] Operand 1
     /*  72524 */     // No operand predicates
     /*  72524 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72528 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72530 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  72530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  72533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  72537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72541 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  72544 */     GIR_RootConstrainSelectedInstOperands,
     /*  72545 */     // GIR_Coverage, 2241,
     /*  72545 */     GIR_EraseRootFromParent_Done,
     /*  72546 */   // Label 1175: @72546
     /*  72546 */   GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(72613), // Rule ID 2300 //
     /*  72551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72558 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  72570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72574 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72579 */     // MIs[1] imm
     /*  72579 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72583 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  72587 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72591 */     // MIs[2] Operand 1
     /*  72591 */     // No operand predicates
     /*  72591 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72595 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72597 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  72597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  72600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72602 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  72604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72608 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  72611 */     GIR_RootConstrainSelectedInstOperands,
     /*  72612 */     // GIR_Coverage, 2300,
     /*  72612 */     GIR_EraseRootFromParent_Done,
     /*  72613 */   // Label 1176: @72613
     /*  72613 */   GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(72677), // Rule ID 14206 //
     /*  72618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72633 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72637 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72641 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72646 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72650 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72656 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  72658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72662 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72664 */     // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS)  =>  (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  72664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  72667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  72669 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  72671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  72675 */     GIR_RootConstrainSelectedInstOperands,
     /*  72676 */     // GIR_Coverage, 14206,
     /*  72676 */     GIR_EraseRootFromParent_Done,
     /*  72677 */   // Label 1177: @72677
     /*  72677 */   GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(72741), // Rule ID 5105 //
     /*  72682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72689 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72701 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  72705 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  72709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72718 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72724 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  72726 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72728 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }))  =>  (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  72728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  72731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  72733 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  72735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  72739 */     GIR_RootConstrainSelectedInstOperands,
     /*  72740 */     // GIR_Coverage, 5105,
     /*  72740 */     GIR_EraseRootFromParent_Done,
     /*  72741 */   // Label 1178: @72741
     /*  72741 */   GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(72768), // Rule ID 5111 //
     /*  72746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72753 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72757 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72761 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  72761 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  72766 */     GIR_RootConstrainSelectedInstOperands,
     /*  72767 */     // GIR_Coverage, 5111,
     /*  72767 */     GIR_Done,
     /*  72768 */   // Label 1179: @72768
     /*  72768 */   GIM_Reject,
     /*  72769 */ // Label 1164: @72769
     /*  72769 */ GIM_Reject,
     /*  72770 */ // Label 1038: @72770
     /*  72770 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(74077),
     /*  72775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72778 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72781 */   GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(72890), // Rule ID 13680 //
     /*  72786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72805 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72809 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  72813 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72817 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72821 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72825 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72830 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72834 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72840 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  72842 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72847 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  72851 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72855 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72859 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72864 */     // MIs[4] Rd
     /*  72864 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  72869 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72871 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  72871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72876 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  72880 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  72884 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  72888 */     GIR_RootConstrainSelectedInstOperands,
     /*  72889 */     // GIR_Coverage, 13680,
     /*  72889 */     GIR_EraseRootFromParent_Done,
     /*  72890 */   // Label 1181: @72890
     /*  72890 */   GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(72999), // Rule ID 13679 //
     /*  72895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72918 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  72922 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72926 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  72930 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72934 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72939 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72943 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72949 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  72951 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72956 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  72960 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72964 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  72968 */     // MIs[4] Rd
     /*  72968 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  72973 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72978 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72980 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  72980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  72989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  72993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  72997 */     GIR_RootConstrainSelectedInstOperands,
     /*  72998 */     // GIR_Coverage, 13679,
     /*  72998 */     GIR_EraseRootFromParent_Done,
     /*  72999 */   // Label 1182: @72999
     /*  72999 */   GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(73108), // Rule ID 13682 //
     /*  73004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73023 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73032 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73036 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73040 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73044 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73048 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73053 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73057 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73063 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  73065 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  73069 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73073 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73077 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73082 */     // MIs[4] Rd
     /*  73082 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  73087 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73089 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  73098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  73102 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  73106 */     GIR_RootConstrainSelectedInstOperands,
     /*  73107 */     // GIR_Coverage, 13682,
     /*  73107 */     GIR_EraseRootFromParent_Done,
     /*  73108 */   // Label 1183: @73108
     /*  73108 */   GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(73217), // Rule ID 13681 //
     /*  73113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73120 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73124 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73128 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73132 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73136 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73141 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73145 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73149 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73153 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73157 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73162 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73166 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73172 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  73174 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  73178 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73182 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73186 */     // MIs[4] Rd
     /*  73186 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  73191 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73196 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73198 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73203 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  73207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  73211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  73215 */     GIR_RootConstrainSelectedInstOperands,
     /*  73216 */     // GIR_Coverage, 13681,
     /*  73216 */     GIR_EraseRootFromParent_Done,
     /*  73217 */   // Label 1184: @73217
     /*  73217 */   GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(73326), // Rule ID 1610 //
     /*  73222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73241 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73245 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73250 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73255 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73259 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73263 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73267 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73271 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  73275 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73279 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73283 */     // MIs[3] Rd
     /*  73283 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  73288 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73292 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73298 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73300 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73305 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73307 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  73316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  73320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  73324 */     GIR_RootConstrainSelectedInstOperands,
     /*  73325 */     // GIR_Coverage, 1610,
     /*  73325 */     GIR_EraseRootFromParent_Done,
     /*  73326 */   // Label 1185: @73326
     /*  73326 */   GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(73435), // Rule ID 13677 //
     /*  73331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73346 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73350 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73354 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73359 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73364 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73368 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73372 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73376 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73380 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  73384 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73388 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73392 */     // MIs[3] Rd
     /*  73392 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  73397 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73401 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73407 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73409 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73414 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73416 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  73425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  73433 */     GIR_RootConstrainSelectedInstOperands,
     /*  73434 */     // GIR_Coverage, 13677,
     /*  73434 */     GIR_EraseRootFromParent_Done,
     /*  73435 */   // Label 1186: @73435
     /*  73435 */   GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(73544), // Rule ID 13676 //
     /*  73440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73447 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73451 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73455 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73459 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73463 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73468 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73473 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73477 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73481 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73485 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73489 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73494 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73498 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73502 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73506 */     // MIs[3] Rd
     /*  73506 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  73511 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73515 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73521 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73523 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73525 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73530 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  73534 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  73538 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  73542 */     GIR_RootConstrainSelectedInstOperands,
     /*  73543 */     // GIR_Coverage, 13676,
     /*  73543 */     GIR_EraseRootFromParent_Done,
     /*  73544 */   // Label 1187: @73544
     /*  73544 */   GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(73653), // Rule ID 13678 //
     /*  73549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73564 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73568 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73572 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73577 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73582 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73586 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73590 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73594 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73598 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73603 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73607 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73611 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73615 */     // MIs[3] Rd
     /*  73615 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  73620 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73624 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73630 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73632 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73634 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  73643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  73651 */     GIR_RootConstrainSelectedInstOperands,
     /*  73652 */     // GIR_Coverage, 13678,
     /*  73652 */     GIR_EraseRootFromParent_Done,
     /*  73653 */   // Label 1188: @73653
     /*  73653 */   GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(73720), // Rule ID 13859 //
     /*  73658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  73673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73677 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73682 */     // MIs[1] imm
     /*  73682 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73686 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  73690 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  73694 */     // MIs[2] Operand 1
     /*  73694 */     // No operand predicates
     /*  73694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73698 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73702 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73704 */     // (or:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  73704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  73707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  73711 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73715 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  73718 */     GIR_RootConstrainSelectedInstOperands,
     /*  73719 */     // GIR_Coverage, 13859,
     /*  73719 */     GIR_EraseRootFromParent_Done,
     /*  73720 */   // Label 1189: @73720
     /*  73720 */   GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(73787), // Rule ID 13880 //
     /*  73725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  73740 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73744 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73749 */     // MIs[1] imm
     /*  73749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  73757 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  73761 */     // MIs[2] Operand 1
     /*  73761 */     // No operand predicates
     /*  73761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73765 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73769 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73771 */     // (or:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  73771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  73774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  73778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  73785 */     GIR_RootConstrainSelectedInstOperands,
     /*  73786 */     // GIR_Coverage, 13880,
     /*  73786 */     GIR_EraseRootFromParent_Done,
     /*  73787 */   // Label 1190: @73787
     /*  73787 */   GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(73854), // Rule ID 2237 //
     /*  73792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73799 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73803 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  73807 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  73811 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73815 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73820 */     // MIs[1] imm
     /*  73820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  73828 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  73832 */     // MIs[2] Operand 1
     /*  73832 */     // No operand predicates
     /*  73832 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73836 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73838 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  73838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  73841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  73845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73849 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  73852 */     GIR_RootConstrainSelectedInstOperands,
     /*  73853 */     // GIR_Coverage, 2237,
     /*  73853 */     GIR_EraseRootFromParent_Done,
     /*  73854 */   // Label 1191: @73854
     /*  73854 */   GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(73921), // Rule ID 2296 //
     /*  73859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73866 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  73874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  73878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73887 */     // MIs[1] imm
     /*  73887 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73891 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  73895 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  73899 */     // MIs[2] Operand 1
     /*  73899 */     // No operand predicates
     /*  73899 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73903 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73905 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /*  73905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  73908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73910 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  73912 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73916 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /*  73919 */     GIR_RootConstrainSelectedInstOperands,
     /*  73920 */     // GIR_Coverage, 2296,
     /*  73920 */     GIR_EraseRootFromParent_Done,
     /*  73921 */   // Label 1192: @73921
     /*  73921 */   GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(73985), // Rule ID 13668 //
     /*  73926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  73945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  73949 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73958 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73964 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  73966 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73970 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73972 */     // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn)  =>  (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  73972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  73975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  73977 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  73979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  73983 */     GIR_RootConstrainSelectedInstOperands,
     /*  73984 */     // GIR_Coverage, 13668,
     /*  73984 */     GIR_EraseRootFromParent_Done,
     /*  73985 */   // Label 1193: @73985
     /*  73985 */   GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(74049), // Rule ID 1606 //
     /*  73990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  74005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  74013 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  74017 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  74026 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74032 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  74034 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  74036 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }))  =>  (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  74036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  74039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  74041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  74043 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  74047 */     GIR_RootConstrainSelectedInstOperands,
     /*  74048 */     // GIR_Coverage, 1606,
     /*  74048 */     GIR_EraseRootFromParent_Done,
     /*  74049 */   // Label 1194: @74049
     /*  74049 */   GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(74076), // Rule ID 1608 //
     /*  74054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74061 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74069 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  74069 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  74074 */     GIR_RootConstrainSelectedInstOperands,
     /*  74075 */     // GIR_Coverage, 1608,
     /*  74075 */     GIR_Done,
     /*  74076 */   // Label 1195: @74076
     /*  74076 */   GIM_Reject,
     /*  74077 */ // Label 1180: @74077
     /*  74077 */ GIM_Reject,
     /*  74078 */ // Label 1039: @74078
     /*  74078 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(74109), // Rule ID 8577 //
     /*  74083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  74086 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  74089 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  74092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  74096 */   // (or:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  74096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  74099 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  74101 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  74103 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  74105 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  74107 */   GIR_RootConstrainSelectedInstOperands,
     /*  74108 */   // GIR_Coverage, 8577,
     /*  74108 */   GIR_EraseRootFromParent_Done,
     /*  74109 */ // Label 1196: @74109
     /*  74109 */ GIM_Reject,
     /*  74110 */ // Label 1040: @74110
     /*  74110 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(74141), // Rule ID 8576 //
     /*  74115 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  74118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  74121 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  74124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  74128 */   // (or:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  74128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  74131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  74133 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  74135 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  74137 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  74139 */   GIR_RootConstrainSelectedInstOperands,
     /*  74140 */   // GIR_Coverage, 8576,
     /*  74140 */   GIR_EraseRootFromParent_Done,
     /*  74141 */ // Label 1197: @74141
     /*  74141 */ GIM_Reject,
     /*  74142 */ // Label 1041: @74142
     /*  74142 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(77607),
     /*  74147 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74150 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74153 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  74157 */   GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(74275), // Rule ID 16183 //
     /*  74162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74177 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74181 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74185 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74189 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74193 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74197 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74201 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74207 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74209 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  74213 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74217 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74221 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74225 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  74229 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74235 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  74237 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  74241 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74245 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74249 */     // MIs[6] Op3
     /*  74249 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  74254 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74256 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  74259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  74265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  74269 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  74273 */     GIR_RootConstrainSelectedInstOperands,
     /*  74274 */     // GIR_Coverage, 16183,
     /*  74274 */     GIR_EraseRootFromParent_Done,
     /*  74275 */   // Label 1199: @74275
     /*  74275 */   GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(74393), // Rule ID 16185 //
     /*  74280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74291 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74295 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74299 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74303 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74307 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74311 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74315 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74319 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74325 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74327 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  74331 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74335 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74339 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74343 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  74347 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74353 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  74355 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  74359 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74363 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74367 */     // MIs[6] Op3
     /*  74367 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74372 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74374 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  74377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  74383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  74387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  74391 */     GIR_RootConstrainSelectedInstOperands,
     /*  74392 */     // GIR_Coverage, 16185,
     /*  74392 */     GIR_EraseRootFromParent_Done,
     /*  74393 */   // Label 1200: @74393
     /*  74393 */   GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(74511), // Rule ID 16182 //
     /*  74398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74409 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74413 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74417 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74421 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74425 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74429 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74433 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74437 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74443 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74445 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  74449 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74453 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74457 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74461 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  74465 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74471 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  74473 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  74477 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74481 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74485 */     // MIs[6] Op3
     /*  74485 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  74490 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74492 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  74495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74497 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  74501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  74505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  74509 */     GIR_RootConstrainSelectedInstOperands,
     /*  74510 */     // GIR_Coverage, 16182,
     /*  74510 */     GIR_EraseRootFromParent_Done,
     /*  74511 */   // Label 1201: @74511
     /*  74511 */   GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(74629), // Rule ID 16184 //
     /*  74516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74519 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74523 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74527 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74531 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74535 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74539 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74543 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74547 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74551 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74555 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74561 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74563 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  74567 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74571 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74575 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74579 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  74583 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74589 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  74591 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  74595 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74599 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74603 */     // MIs[6] Op3
     /*  74603 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74608 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74610 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  74613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  74619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  74623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  74627 */     GIR_RootConstrainSelectedInstOperands,
     /*  74628 */     // GIR_Coverage, 16184,
     /*  74628 */     GIR_EraseRootFromParent_Done,
     /*  74629 */   // Label 1202: @74629
     /*  74629 */   GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(74747), // Rule ID 16074 //
     /*  74634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74649 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74661 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74665 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74669 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74673 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74679 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74681 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74685 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74689 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74693 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74697 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  74701 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74705 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74709 */     // MIs[5] Op3
     /*  74709 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  74714 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  74718 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74724 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  74726 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74728 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  74731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  74737 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  74741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  74745 */     GIR_RootConstrainSelectedInstOperands,
     /*  74746 */     // GIR_Coverage, 16074,
     /*  74746 */     GIR_EraseRootFromParent_Done,
     /*  74747 */   // Label 1203: @74747
     /*  74747 */   GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(74865), // Rule ID 16079 //
     /*  74752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74755 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74759 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74763 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74767 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74771 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74775 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74779 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74783 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74787 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74791 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74797 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74799 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74803 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74807 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74811 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  74815 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74819 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74823 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74827 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  74831 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74837 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  74839 */     // MIs[4] Op3
     /*  74839 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74844 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74846 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  74849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  74855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  74859 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  74863 */     GIR_RootConstrainSelectedInstOperands,
     /*  74864 */     // GIR_Coverage, 16079,
     /*  74864 */     GIR_EraseRootFromParent_Done,
     /*  74865 */   // Label 1204: @74865
     /*  74865 */   GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(74983), // Rule ID 16080 //
     /*  74870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74881 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74885 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74889 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74893 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74897 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74901 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74905 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74909 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74915 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74917 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74921 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74925 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74929 */     // MIs[4] Op3
     /*  74929 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74934 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  74938 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74942 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  74946 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  74950 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  74954 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74960 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  74962 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  74964 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  74964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  74967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  74969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  74973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  74977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  74981 */     GIR_RootConstrainSelectedInstOperands,
     /*  74982 */     // GIR_Coverage, 16080,
     /*  74982 */     GIR_EraseRootFromParent_Done,
     /*  74983 */   // Label 1205: @74983
     /*  74983 */   GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(75101), // Rule ID 12071 //
     /*  74988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  74991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  75011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75015 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75019 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75023 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75027 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75033 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75035 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75039 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75043 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75047 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75051 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  75055 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75059 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75063 */     // MIs[5] Op3
     /*  75063 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  75068 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75072 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75078 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75080 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75082 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  75085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75087 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  75091 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  75095 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  75099 */     GIR_RootConstrainSelectedInstOperands,
     /*  75100 */     // GIR_Coverage, 12071,
     /*  75100 */     GIR_EraseRootFromParent_Done,
     /*  75101 */   // Label 1206: @75101
     /*  75101 */   GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(75219), // Rule ID 16076 //
     /*  75106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75113 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75117 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75121 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75125 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75129 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75133 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75137 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75141 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75145 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75151 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75153 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75157 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75161 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75165 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75169 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  75173 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75177 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75181 */     // MIs[5] Op3
     /*  75181 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  75186 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75190 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75196 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75198 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75200 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  75203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  75209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  75213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  75217 */     GIR_RootConstrainSelectedInstOperands,
     /*  75218 */     // GIR_Coverage, 16076,
     /*  75218 */     GIR_EraseRootFromParent_Done,
     /*  75219 */   // Label 1207: @75219
     /*  75219 */   GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(75337), // Rule ID 16077 //
     /*  75224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75235 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75239 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75243 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75247 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75251 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75255 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75259 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75263 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75269 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75271 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75275 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75279 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75283 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  75287 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75291 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75295 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75299 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75303 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75309 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75311 */     // MIs[4] Op3
     /*  75311 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75316 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75318 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  75321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75323 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  75327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  75331 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  75335 */     GIR_RootConstrainSelectedInstOperands,
     /*  75336 */     // GIR_Coverage, 16077,
     /*  75336 */     GIR_EraseRootFromParent_Done,
     /*  75337 */   // Label 1208: @75337
     /*  75337 */   GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(75455), // Rule ID 16078 //
     /*  75342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75345 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75349 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75353 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75357 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75369 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75373 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75377 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75381 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75387 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75389 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75393 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75397 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75401 */     // MIs[4] Op3
     /*  75401 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75406 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  75410 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75414 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75418 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75422 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75426 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75432 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75434 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75436 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  75439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75441 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  75445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  75449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  75453 */     GIR_RootConstrainSelectedInstOperands,
     /*  75454 */     // GIR_Coverage, 16078,
     /*  75454 */     GIR_EraseRootFromParent_Done,
     /*  75455 */   // Label 1209: @75455
     /*  75455 */   GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(75573), // Rule ID 16075 //
     /*  75460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75463 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75467 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75471 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75475 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75479 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75483 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75487 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75491 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75495 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75499 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75505 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75507 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75511 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75515 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75519 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75523 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  75527 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75531 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75535 */     // MIs[5] Op3
     /*  75535 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  75540 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75544 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75550 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75552 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75554 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  75557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  75563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  75567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  75571 */     GIR_RootConstrainSelectedInstOperands,
     /*  75572 */     // GIR_Coverage, 16075,
     /*  75572 */     GIR_EraseRootFromParent_Done,
     /*  75573 */   // Label 1210: @75573
     /*  75573 */   GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(75691), // Rule ID 16179 //
     /*  75578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75597 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75605 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75609 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75613 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  75617 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75621 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75625 */     // MIs[3] Op3
     /*  75625 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  75630 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  75634 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75640 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  75642 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  75646 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75650 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75654 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75658 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75662 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75668 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75670 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75672 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  75675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  75681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  75685 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  75689 */     GIR_RootConstrainSelectedInstOperands,
     /*  75690 */     // GIR_Coverage, 16179,
     /*  75690 */     GIR_EraseRootFromParent_Done,
     /*  75691 */   // Label 1211: @75691
     /*  75691 */   GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(75809), // Rule ID 16181 //
     /*  75696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75707 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75711 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75715 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75719 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75723 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75727 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75731 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  75735 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75739 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75743 */     // MIs[3] Op3
     /*  75743 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  75748 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  75752 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75758 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  75760 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  75764 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75768 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75772 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75776 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75780 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75786 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75788 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75790 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  75793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  75799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  75803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  75807 */     GIR_RootConstrainSelectedInstOperands,
     /*  75808 */     // GIR_Coverage, 16181,
     /*  75808 */     GIR_EraseRootFromParent_Done,
     /*  75809 */   // Label 1212: @75809
     /*  75809 */   GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(75927), // Rule ID 12098 //
     /*  75814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75829 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75833 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75837 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75841 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75845 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75849 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  75853 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75857 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75861 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75865 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  75869 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75875 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  75877 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  75881 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75885 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75889 */     // MIs[5] Op3
     /*  75889 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  75894 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  75898 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75904 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  75906 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  75908 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  75908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  75911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  75913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  75917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  75921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  75925 */     GIR_RootConstrainSelectedInstOperands,
     /*  75926 */     // GIR_Coverage, 12098,
     /*  75926 */     GIR_EraseRootFromParent_Done,
     /*  75927 */   // Label 1213: @75927
     /*  75927 */   GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(76045), // Rule ID 16180 //
     /*  75932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  75935 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75939 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75943 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75947 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75951 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75955 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75959 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75963 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75967 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  75971 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75975 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  75979 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  75983 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  75987 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75993 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  75995 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  75999 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76003 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76007 */     // MIs[5] Op3
     /*  76007 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  76012 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  76016 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76022 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  76024 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  76026 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  76029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76031 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  76035 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  76039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  76043 */     GIR_RootConstrainSelectedInstOperands,
     /*  76044 */     // GIR_Coverage, 16180,
     /*  76044 */     GIR_EraseRootFromParent_Done,
     /*  76045 */   // Label 1214: @76045
     /*  76045 */   GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(76135), // Rule ID 15996 //
     /*  76050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  76073 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76077 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76081 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76085 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76089 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76095 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76097 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76101 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76105 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76109 */     // MIs[4] Op3
     /*  76109 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76114 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76116 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  76125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  76129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  76133 */     GIR_RootConstrainSelectedInstOperands,
     /*  76134 */     // GIR_Coverage, 15996,
     /*  76134 */     GIR_EraseRootFromParent_Done,
     /*  76135 */   // Label 1215: @76135
     /*  76135 */   GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(76225), // Rule ID 15995 //
     /*  76140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76151 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76155 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  76163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76167 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76171 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76175 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76179 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76185 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76187 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76191 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76195 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76199 */     // MIs[4] Op3
     /*  76199 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76204 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76206 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  76215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  76219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  76223 */     GIR_RootConstrainSelectedInstOperands,
     /*  76224 */     // GIR_Coverage, 15995,
     /*  76224 */     GIR_EraseRootFromParent_Done,
     /*  76225 */   // Label 1216: @76225
     /*  76225 */   GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(76315), // Rule ID 15994 //
     /*  76230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76245 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76249 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  76253 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76257 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76261 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76265 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76269 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76275 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76277 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76281 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76285 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76289 */     // MIs[4] Op3
     /*  76289 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76294 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76296 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  76305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  76309 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  76313 */     GIR_RootConstrainSelectedInstOperands,
     /*  76314 */     // GIR_Coverage, 15994,
     /*  76314 */     GIR_EraseRootFromParent_Done,
     /*  76315 */   // Label 1217: @76315
     /*  76315 */   GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(76405), // Rule ID 15993 //
     /*  76320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76323 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76327 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76331 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76335 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76339 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  76343 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76347 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76351 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76355 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76359 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76365 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76367 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76371 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76375 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76379 */     // MIs[4] Op3
     /*  76379 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76384 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76386 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76391 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  76395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  76399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  76403 */     GIR_RootConstrainSelectedInstOperands,
     /*  76404 */     // GIR_Coverage, 15993,
     /*  76404 */     GIR_EraseRootFromParent_Done,
     /*  76405 */   // Label 1218: @76405
     /*  76405 */   GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(76495), // Rule ID 15990 //
     /*  76410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76425 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76429 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76433 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76437 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76441 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76445 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76449 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76453 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76457 */     // MIs[3] Op3
     /*  76457 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  76462 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76466 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76472 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76474 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76476 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  76485 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  76489 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  76493 */     GIR_RootConstrainSelectedInstOperands,
     /*  76494 */     // GIR_Coverage, 15990,
     /*  76494 */     GIR_EraseRootFromParent_Done,
     /*  76495 */   // Label 1219: @76495
     /*  76495 */   GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(76585), // Rule ID 15992 //
     /*  76500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76507 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76511 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76515 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76519 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76523 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76527 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76531 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76535 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76539 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76543 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76547 */     // MIs[3] Op3
     /*  76547 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  76552 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76556 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76562 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76564 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76566 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  76575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  76579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  76583 */     GIR_RootConstrainSelectedInstOperands,
     /*  76584 */     // GIR_Coverage, 15992,
     /*  76584 */     GIR_EraseRootFromParent_Done,
     /*  76585 */   // Label 1220: @76585
     /*  76585 */   GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(76675), // Rule ID 12047 //
     /*  76590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76593 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76597 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76601 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76605 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76617 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76621 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76625 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76629 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76633 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76637 */     // MIs[3] Op3
     /*  76637 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  76642 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76646 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76652 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76654 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76656 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  76665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  76669 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  76673 */     GIR_RootConstrainSelectedInstOperands,
     /*  76674 */     // GIR_Coverage, 12047,
     /*  76674 */     GIR_EraseRootFromParent_Done,
     /*  76675 */   // Label 1221: @76675
     /*  76675 */   GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(76765), // Rule ID 15991 //
     /*  76680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76691 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76695 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76703 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76707 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76711 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76723 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76727 */     // MIs[3] Op3
     /*  76727 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  76732 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76736 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76742 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76744 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76746 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  76749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  76755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  76759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  76763 */     GIR_RootConstrainSelectedInstOperands,
     /*  76764 */     // GIR_Coverage, 15991,
     /*  76764 */     GIR_EraseRootFromParent_Done,
     /*  76765 */   // Label 1222: @76765
     /*  76765 */   GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(76855), // Rule ID 16186 //
     /*  76770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76781 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76785 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76789 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76793 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76797 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76801 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76805 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76809 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  76813 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76817 */     // MIs[3] Op3
     /*  76817 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  76822 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  76826 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76832 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76834 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76836 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  76839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76841 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  76845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  76849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  76853 */     GIR_RootConstrainSelectedInstOperands,
     /*  76854 */     // GIR_Coverage, 16186,
     /*  76854 */     GIR_EraseRootFromParent_Done,
     /*  76855 */   // Label 1223: @76855
     /*  76855 */   GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(76945), // Rule ID 16188 //
     /*  76860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76891 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76895 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76899 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  76903 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76907 */     // MIs[3] Op3
     /*  76907 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  76912 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  76916 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76922 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76924 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76926 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  76926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  76929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  76931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  76935 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  76939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  76943 */     GIR_RootConstrainSelectedInstOperands,
     /*  76944 */     // GIR_Coverage, 16188,
     /*  76944 */     GIR_EraseRootFromParent_Done,
     /*  76945 */   // Label 1224: @76945
     /*  76945 */   GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(77035), // Rule ID 12099 //
     /*  76950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  76953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76961 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76965 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76973 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76977 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76981 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  76985 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76989 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  76993 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  76997 */     // MIs[3] Op3
     /*  76997 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  77002 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  77006 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77012 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77014 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77016 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77021 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  77025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  77029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  77033 */     GIR_RootConstrainSelectedInstOperands,
     /*  77034 */     // GIR_Coverage, 12099,
     /*  77034 */     GIR_EraseRootFromParent_Done,
     /*  77035 */   // Label 1225: @77035
     /*  77035 */   GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(77125), // Rule ID 16187 //
     /*  77040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77043 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77047 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77051 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77055 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77059 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  77063 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77067 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77071 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77075 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  77079 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  77083 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77087 */     // MIs[3] Op3
     /*  77087 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  77092 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  77096 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77102 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77104 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77106 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  77115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  77119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  77123 */     GIR_RootConstrainSelectedInstOperands,
     /*  77124 */     // GIR_Coverage, 16187,
     /*  77124 */     GIR_EraseRootFromParent_Done,
     /*  77125 */   // Label 1226: @77125
     /*  77125 */   GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(77215), // Rule ID 16190 //
     /*  77130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77133 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77137 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77141 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77145 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  77157 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77161 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77165 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  77169 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77175 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77177 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  77181 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77185 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77189 */     // MIs[4] Op3
     /*  77189 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  77194 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77196 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  77205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  77209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  77213 */     GIR_RootConstrainSelectedInstOperands,
     /*  77214 */     // GIR_Coverage, 16190,
     /*  77214 */     GIR_EraseRootFromParent_Done,
     /*  77215 */   // Label 1227: @77215
     /*  77215 */   GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(77305), // Rule ID 16192 //
     /*  77220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  77247 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77251 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77255 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  77259 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77265 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77267 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  77271 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77275 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77279 */     // MIs[4] Op3
     /*  77279 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  77284 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77286 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77291 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  77295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  77299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  77303 */     GIR_RootConstrainSelectedInstOperands,
     /*  77304 */     // GIR_Coverage, 16192,
     /*  77304 */     GIR_EraseRootFromParent_Done,
     /*  77305 */   // Label 1228: @77305
     /*  77305 */   GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(77395), // Rule ID 16189 //
     /*  77310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77329 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77333 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  77337 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77341 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77345 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  77349 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77355 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77357 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  77361 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77365 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77369 */     // MIs[4] Op3
     /*  77369 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  77374 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77376 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  77385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  77389 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  77393 */     GIR_RootConstrainSelectedInstOperands,
     /*  77394 */     // GIR_Coverage, 16189,
     /*  77394 */     GIR_EraseRootFromParent_Done,
     /*  77395 */   // Label 1229: @77395
     /*  77395 */   GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(77485), // Rule ID 16191 //
     /*  77400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77403 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77407 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77411 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77415 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  77427 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77431 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77435 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  77439 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77445 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77447 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  77451 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77455 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77459 */     // MIs[4] Op3
     /*  77459 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  77464 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77466 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  77466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  77475 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  77479 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  77483 */     GIR_RootConstrainSelectedInstOperands,
     /*  77484 */     // GIR_Coverage, 16191,
     /*  77484 */     GIR_EraseRootFromParent_Done,
     /*  77485 */   // Label 1230: @77485
     /*  77485 */   GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(77538), // Rule ID 16422 //
     /*  77490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77493 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77497 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77501 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77505 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77509 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  77513 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77519 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  77521 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  77523 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1)
     /*  77523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77528 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  77530 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  77534 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  77536 */     GIR_RootConstrainSelectedInstOperands,
     /*  77537 */     // GIR_Coverage, 16422,
     /*  77537 */     GIR_EraseRootFromParent_Done,
     /*  77538 */   // Label 1231: @77538
     /*  77538 */   GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(77591), // Rule ID 12193 //
     /*  77543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  77550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  77558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  77562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  77566 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77572 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  77574 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  77576 */     // (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1)
     /*  77576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77581 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  77583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  77587 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  77589 */     GIR_RootConstrainSelectedInstOperands,
     /*  77590 */     // GIR_Coverage, 12193,
     /*  77590 */     GIR_EraseRootFromParent_Done,
     /*  77591 */   // Label 1232: @77591
     /*  77591 */   GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(77606), // Rule ID 7557 //
     /*  77596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  77599 */     // (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  77599 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  77604 */     GIR_RootConstrainSelectedInstOperands,
     /*  77605 */     // GIR_Coverage, 7557,
     /*  77605 */     GIR_Done,
     /*  77606 */   // Label 1233: @77606
     /*  77606 */   GIM_Reject,
     /*  77607 */ // Label 1198: @77607
     /*  77607 */ GIM_Reject,
     /*  77608 */ // Label 1042: @77608
     /*  77608 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(77639), // Rule ID 8575 //
     /*  77613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  77616 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  77619 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  77622 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  77626 */   // (or:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  77626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  77629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  77631 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  77633 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  77635 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  77637 */   GIR_RootConstrainSelectedInstOperands,
     /*  77638 */   // GIR_Coverage, 8575,
     /*  77638 */   GIR_EraseRootFromParent_Done,
     /*  77639 */ // Label 1234: @77639
     /*  77639 */ GIM_Reject,
     /*  77640 */ // Label 1043: @77640
     /*  77640 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(81105),
     /*  77645 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77648 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  77655 */   GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(77773), // Rule ID 16169 //
     /*  77660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77675 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77683 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77687 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77691 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77695 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77699 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77705 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77707 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  77711 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77715 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77719 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77723 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  77727 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77733 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  77735 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  77739 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77743 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77747 */     // MIs[6] Op3
     /*  77747 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  77752 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  77754 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  77754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  77763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  77767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  77771 */     GIR_RootConstrainSelectedInstOperands,
     /*  77772 */     // GIR_Coverage, 16169,
     /*  77772 */     GIR_EraseRootFromParent_Done,
     /*  77773 */   // Label 1236: @77773
     /*  77773 */   GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(77891), // Rule ID 16171 //
     /*  77778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77789 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77793 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77797 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77801 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77805 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77809 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77813 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77817 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77823 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77825 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  77829 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77833 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77837 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77841 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  77845 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77851 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  77853 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  77857 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77861 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77865 */     // MIs[6] Op3
     /*  77865 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  77870 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  77872 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  77872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  77881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  77885 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  77889 */     GIR_RootConstrainSelectedInstOperands,
     /*  77890 */     // GIR_Coverage, 16171,
     /*  77890 */     GIR_EraseRootFromParent_Done,
     /*  77891 */   // Label 1237: @77891
     /*  77891 */   GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(78009), // Rule ID 16168 //
     /*  77896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  77899 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77903 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77907 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77911 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77915 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  77919 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77923 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77927 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77931 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77935 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77941 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77943 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  77947 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77951 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77955 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  77959 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  77963 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77969 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  77971 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  77975 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77979 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  77983 */     // MIs[6] Op3
     /*  77983 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  77988 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  77990 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  77990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  77993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  77995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  77999 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  78003 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  78007 */     GIR_RootConstrainSelectedInstOperands,
     /*  78008 */     // GIR_Coverage, 16168,
     /*  78008 */     GIR_EraseRootFromParent_Done,
     /*  78009 */   // Label 1238: @78009
     /*  78009 */   GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(78127), // Rule ID 16170 //
     /*  78014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78033 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78037 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78041 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78045 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78049 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78053 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78059 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78061 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  78065 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78069 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78073 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78077 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78081 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78087 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  78089 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  78093 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78097 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78101 */     // MIs[6] Op3
     /*  78101 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78106 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78108 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  78111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  78117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  78121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78125 */     GIR_RootConstrainSelectedInstOperands,
     /*  78126 */     // GIR_Coverage, 16170,
     /*  78126 */     GIR_EraseRootFromParent_Done,
     /*  78127 */   // Label 1239: @78127
     /*  78127 */   GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(78245), // Rule ID 16067 //
     /*  78132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78135 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78139 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78143 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78147 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78151 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78155 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78159 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78163 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78167 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78171 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78177 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78179 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78183 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78187 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78191 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78195 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78199 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78203 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78207 */     // MIs[5] Op3
     /*  78207 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  78212 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78216 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78222 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78224 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78226 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  78235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  78239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  78243 */     GIR_RootConstrainSelectedInstOperands,
     /*  78244 */     // GIR_Coverage, 16067,
     /*  78244 */     GIR_EraseRootFromParent_Done,
     /*  78245 */   // Label 1240: @78245
     /*  78245 */   GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(78363), // Rule ID 16072 //
     /*  78250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78269 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78273 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78277 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78281 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78285 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78289 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78295 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78297 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78301 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78305 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78309 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78313 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78317 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78321 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78325 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78329 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78335 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78337 */     // MIs[4] Op3
     /*  78337 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78342 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78344 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  78357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78361 */     GIR_RootConstrainSelectedInstOperands,
     /*  78362 */     // GIR_Coverage, 16072,
     /*  78362 */     GIR_EraseRootFromParent_Done,
     /*  78363 */   // Label 1241: @78363
     /*  78363 */   GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(78481), // Rule ID 16073 //
     /*  78368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78371 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78375 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78379 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78383 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78387 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78391 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78395 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78399 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78403 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78407 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78413 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78415 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78419 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78423 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78427 */     // MIs[4] Op3
     /*  78427 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78432 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78436 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78440 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78444 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78448 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78452 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78458 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78460 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78462 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  78475 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78479 */     GIR_RootConstrainSelectedInstOperands,
     /*  78480 */     // GIR_Coverage, 16073,
     /*  78480 */     GIR_EraseRootFromParent_Done,
     /*  78481 */   // Label 1242: @78481
     /*  78481 */   GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(78599), // Rule ID 12069 //
     /*  78486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78505 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78509 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78513 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78517 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78521 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78525 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78531 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78533 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78537 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78541 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78545 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78549 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78553 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78557 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78561 */     // MIs[5] Op3
     /*  78561 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  78566 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78570 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78576 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78578 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78580 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  78589 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  78593 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  78597 */     GIR_RootConstrainSelectedInstOperands,
     /*  78598 */     // GIR_Coverage, 12069,
     /*  78598 */     GIR_EraseRootFromParent_Done,
     /*  78599 */   // Label 1243: @78599
     /*  78599 */   GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(78717), // Rule ID 16069 //
     /*  78604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78607 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78611 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78615 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78619 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78623 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  78627 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78631 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78635 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78639 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78643 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78649 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78651 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78655 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78659 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78663 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78667 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78671 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78675 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78679 */     // MIs[5] Op3
     /*  78679 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  78684 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78688 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78694 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78696 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78698 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  78707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  78711 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  78715 */     GIR_RootConstrainSelectedInstOperands,
     /*  78716 */     // GIR_Coverage, 16069,
     /*  78716 */     GIR_EraseRootFromParent_Done,
     /*  78717 */   // Label 1244: @78717
     /*  78717 */   GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(78835), // Rule ID 16070 //
     /*  78722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78725 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78729 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78733 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78737 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78741 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  78745 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78749 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78753 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78757 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78761 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78767 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78769 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78773 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78777 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78781 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78785 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78789 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78793 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78797 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78801 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78807 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78809 */     // MIs[4] Op3
     /*  78809 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78814 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78816 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  78829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78833 */     GIR_RootConstrainSelectedInstOperands,
     /*  78834 */     // GIR_Coverage, 16070,
     /*  78834 */     GIR_EraseRootFromParent_Done,
     /*  78835 */   // Label 1245: @78835
     /*  78835 */   GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(78953), // Rule ID 16071 //
     /*  78840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78843 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78847 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78851 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78855 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78859 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  78863 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78867 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78871 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78875 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78879 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78885 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78887 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78891 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78895 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78899 */     // MIs[4] Op3
     /*  78899 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78904 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78908 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78912 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78916 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78920 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78924 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78930 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78932 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78934 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  78934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  78947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78951 */     GIR_RootConstrainSelectedInstOperands,
     /*  78952 */     // GIR_Coverage, 16071,
     /*  78952 */     GIR_EraseRootFromParent_Done,
     /*  78953 */   // Label 1246: @78953
     /*  78953 */   GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(79071), // Rule ID 16068 //
     /*  78958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78961 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78965 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78969 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78973 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  78981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78985 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  78989 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  78993 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78997 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79003 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79005 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79009 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79013 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79017 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79021 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  79025 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79029 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79033 */     // MIs[5] Op3
     /*  79033 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79038 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79042 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79048 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79050 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79052 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  79055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  79061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  79065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79069 */     GIR_RootConstrainSelectedInstOperands,
     /*  79070 */     // GIR_Coverage, 16068,
     /*  79070 */     GIR_EraseRootFromParent_Done,
     /*  79071 */   // Label 1247: @79071
     /*  79071 */   GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(79189), // Rule ID 16165 //
     /*  79076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79091 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79095 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79099 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79103 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79107 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79111 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79115 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79119 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79123 */     // MIs[3] Op3
     /*  79123 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  79128 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79132 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79138 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79140 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79144 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79148 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79152 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79156 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79160 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79166 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79168 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79170 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  79179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  79183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79187 */     GIR_RootConstrainSelectedInstOperands,
     /*  79188 */     // GIR_Coverage, 16165,
     /*  79188 */     GIR_EraseRootFromParent_Done,
     /*  79189 */   // Label 1248: @79189
     /*  79189 */   GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(79307), // Rule ID 16167 //
     /*  79194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79201 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79205 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79209 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79213 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79217 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79221 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79225 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79229 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79233 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79237 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79241 */     // MIs[3] Op3
     /*  79241 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79246 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79250 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79256 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79258 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79262 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79266 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79270 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79274 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79278 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79284 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79286 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79288 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79293 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  79297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  79301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79305 */     GIR_RootConstrainSelectedInstOperands,
     /*  79306 */     // GIR_Coverage, 16167,
     /*  79306 */     GIR_EraseRootFromParent_Done,
     /*  79307 */   // Label 1249: @79307
     /*  79307 */   GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(79425), // Rule ID 12095 //
     /*  79312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79327 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79339 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79343 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79347 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79351 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79355 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79359 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79363 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79367 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79373 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79375 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79379 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79383 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79387 */     // MIs[5] Op3
     /*  79387 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  79392 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79396 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79402 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79404 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79406 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79411 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  79415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  79419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79423 */     GIR_RootConstrainSelectedInstOperands,
     /*  79424 */     // GIR_Coverage, 12095,
     /*  79424 */     GIR_EraseRootFromParent_Done,
     /*  79425 */   // Label 1250: @79425
     /*  79425 */   GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(79543), // Rule ID 16166 //
     /*  79430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79437 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79441 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79445 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79457 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79461 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79465 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79469 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79473 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79477 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79481 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79485 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79491 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79493 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79497 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79501 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79505 */     // MIs[5] Op3
     /*  79505 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79510 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79514 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79520 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79522 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79524 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79529 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  79533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  79537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79541 */     GIR_RootConstrainSelectedInstOperands,
     /*  79542 */     // GIR_Coverage, 16166,
     /*  79542 */     GIR_EraseRootFromParent_Done,
     /*  79543 */   // Label 1251: @79543
     /*  79543 */   GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(79633), // Rule ID 15989 //
     /*  79548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79563 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  79571 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79575 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79579 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79583 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79587 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79593 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79595 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79599 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79603 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79607 */     // MIs[4] Op3
     /*  79607 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79612 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  79614 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  79617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  79623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  79627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79631 */     GIR_RootConstrainSelectedInstOperands,
     /*  79632 */     // GIR_Coverage, 15989,
     /*  79632 */     GIR_EraseRootFromParent_Done,
     /*  79633 */   // Label 1252: @79633
     /*  79633 */   GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(79723), // Rule ID 15988 //
     /*  79638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79653 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79657 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  79661 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79665 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79669 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79673 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79677 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79683 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79685 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79689 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79693 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79697 */     // MIs[4] Op3
     /*  79697 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79702 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  79704 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  79707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  79713 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  79717 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79721 */     GIR_RootConstrainSelectedInstOperands,
     /*  79722 */     // GIR_Coverage, 15988,
     /*  79722 */     GIR_EraseRootFromParent_Done,
     /*  79723 */   // Label 1253: @79723
     /*  79723 */   GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(79813), // Rule ID 15987 //
     /*  79728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79731 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79735 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79739 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79743 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79755 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79759 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79763 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79767 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79773 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79775 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79779 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79783 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79787 */     // MIs[4] Op3
     /*  79787 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79792 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  79794 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  79797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  79803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  79807 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79811 */     GIR_RootConstrainSelectedInstOperands,
     /*  79812 */     // GIR_Coverage, 15987,
     /*  79812 */     GIR_EraseRootFromParent_Done,
     /*  79813 */   // Label 1254: @79813
     /*  79813 */   GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(79903), // Rule ID 15986 //
     /*  79818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79833 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79837 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79841 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79845 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79849 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79853 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79857 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79863 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79865 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79869 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79873 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79877 */     // MIs[4] Op3
     /*  79877 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79882 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  79884 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  79887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  79893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  79897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79901 */     GIR_RootConstrainSelectedInstOperands,
     /*  79902 */     // GIR_Coverage, 15986,
     /*  79902 */     GIR_EraseRootFromParent_Done,
     /*  79903 */   // Label 1255: @79903
     /*  79903 */   GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(79993), // Rule ID 15983 //
     /*  79908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79923 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79927 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79931 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79935 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  79939 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79943 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79947 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79951 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  79955 */     // MIs[3] Op3
     /*  79955 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  79960 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79964 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79970 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79972 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  79974 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  79974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  79977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  79983 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  79987 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79991 */     GIR_RootConstrainSelectedInstOperands,
     /*  79992 */     // GIR_Coverage, 15983,
     /*  79992 */     GIR_EraseRootFromParent_Done,
     /*  79993 */   // Label 1256: @79993
     /*  79993 */   GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(80083), // Rule ID 15985 //
     /*  79998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80013 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80017 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80021 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80025 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80029 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80033 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80037 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80041 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80045 */     // MIs[3] Op3
     /*  80045 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80050 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80054 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80060 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80062 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80064 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  80077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80081 */     GIR_RootConstrainSelectedInstOperands,
     /*  80082 */     // GIR_Coverage, 15985,
     /*  80082 */     GIR_EraseRootFromParent_Done,
     /*  80083 */   // Label 1257: @80083
     /*  80083 */   GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(80173), // Rule ID 12045 //
     /*  80088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80091 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80095 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80099 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80103 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80107 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80111 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80115 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80119 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80123 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80127 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80131 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80135 */     // MIs[3] Op3
     /*  80135 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80140 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80144 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80150 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80152 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80154 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80171 */     GIR_RootConstrainSelectedInstOperands,
     /*  80172 */     // GIR_Coverage, 12045,
     /*  80172 */     GIR_EraseRootFromParent_Done,
     /*  80173 */   // Label 1258: @80173
     /*  80173 */   GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(80263), // Rule ID 15984 //
     /*  80178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80193 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80205 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80209 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80213 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80217 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80221 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80225 */     // MIs[3] Op3
     /*  80225 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80230 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80234 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80240 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80242 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80244 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80261 */     GIR_RootConstrainSelectedInstOperands,
     /*  80262 */     // GIR_Coverage, 15984,
     /*  80262 */     GIR_EraseRootFromParent_Done,
     /*  80263 */   // Label 1259: @80263
     /*  80263 */   GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(80353), // Rule ID 16172 //
     /*  80268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80279 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80287 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80291 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80295 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80299 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80303 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80307 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80311 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80315 */     // MIs[3] Op3
     /*  80315 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80320 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80324 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80330 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80332 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80334 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  80347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80351 */     GIR_RootConstrainSelectedInstOperands,
     /*  80352 */     // GIR_Coverage, 16172,
     /*  80352 */     GIR_EraseRootFromParent_Done,
     /*  80353 */   // Label 1260: @80353
     /*  80353 */   GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(80443), // Rule ID 16174 //
     /*  80358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80369 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80373 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80377 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80381 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80385 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80389 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80393 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80397 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80401 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80405 */     // MIs[3] Op3
     /*  80405 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80410 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80414 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80420 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80422 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80424 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80433 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  80437 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80441 */     GIR_RootConstrainSelectedInstOperands,
     /*  80442 */     // GIR_Coverage, 16174,
     /*  80442 */     GIR_EraseRootFromParent_Done,
     /*  80443 */   // Label 1261: @80443
     /*  80443 */   GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(80533), // Rule ID 12096 //
     /*  80448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80451 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80455 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80459 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80463 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80467 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80471 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80475 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80479 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80483 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80487 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80491 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80495 */     // MIs[3] Op3
     /*  80495 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80500 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80504 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80510 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80512 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80514 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80519 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  80527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80531 */     GIR_RootConstrainSelectedInstOperands,
     /*  80532 */     // GIR_Coverage, 12096,
     /*  80532 */     GIR_EraseRootFromParent_Done,
     /*  80533 */   // Label 1262: @80533
     /*  80533 */   GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(80623), // Rule ID 16173 //
     /*  80538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80549 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80553 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80557 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80561 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80565 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80569 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80573 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80577 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80581 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80585 */     // MIs[3] Op3
     /*  80585 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80590 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80594 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80600 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80602 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80604 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  80617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80621 */     GIR_RootConstrainSelectedInstOperands,
     /*  80622 */     // GIR_Coverage, 16173,
     /*  80622 */     GIR_EraseRootFromParent_Done,
     /*  80623 */   // Label 1263: @80623
     /*  80623 */   GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(80713), // Rule ID 16176 //
     /*  80628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80639 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80643 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80647 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  80651 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80655 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80659 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80663 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  80667 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80673 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80675 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80679 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80683 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80687 */     // MIs[4] Op3
     /*  80687 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  80692 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80694 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80699 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  80703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  80711 */     GIR_RootConstrainSelectedInstOperands,
     /*  80712 */     // GIR_Coverage, 16176,
     /*  80712 */     GIR_EraseRootFromParent_Done,
     /*  80713 */   // Label 1264: @80713
     /*  80713 */   GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(80803), // Rule ID 16178 //
     /*  80718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80729 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80733 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  80741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80745 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80749 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80753 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  80757 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80763 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80765 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80769 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80773 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80777 */     // MIs[4] Op3
     /*  80777 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80782 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80784 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  80793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  80797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80801 */     GIR_RootConstrainSelectedInstOperands,
     /*  80802 */     // GIR_Coverage, 16178,
     /*  80802 */     GIR_EraseRootFromParent_Done,
     /*  80803 */   // Label 1265: @80803
     /*  80803 */   GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(80893), // Rule ID 16175 //
     /*  80808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80811 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80815 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80819 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80823 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  80831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80835 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80839 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80843 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  80847 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80853 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80855 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80859 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80863 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80867 */     // MIs[4] Op3
     /*  80867 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  80872 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80874 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  80883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80887 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  80891 */     GIR_RootConstrainSelectedInstOperands,
     /*  80892 */     // GIR_Coverage, 16175,
     /*  80892 */     GIR_EraseRootFromParent_Done,
     /*  80893 */   // Label 1266: @80893
     /*  80893 */   GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(80983), // Rule ID 16177 //
     /*  80898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80901 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80905 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80909 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80913 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80917 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  80921 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80925 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80929 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  80933 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  80937 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80943 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80945 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80949 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80953 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  80957 */     // MIs[4] Op3
     /*  80957 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80962 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80964 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  80964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  80973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  80977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80981 */     GIR_RootConstrainSelectedInstOperands,
     /*  80982 */     // GIR_Coverage, 16177,
     /*  80982 */     GIR_EraseRootFromParent_Done,
     /*  80983 */   // Label 1267: @80983
     /*  80983 */   GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(81036), // Rule ID 16413 //
     /*  80988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  81011 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81017 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  81019 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  81021 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1)
     /*  81021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81026 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  81028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  81032 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  81034 */     GIR_RootConstrainSelectedInstOperands,
     /*  81035 */     // GIR_Coverage, 16413,
     /*  81035 */     GIR_EraseRootFromParent_Done,
     /*  81036 */   // Label 1268: @81036
     /*  81036 */   GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(81089), // Rule ID 12181 //
     /*  81041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  81048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81056 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81060 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  81064 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81070 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  81072 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  81074 */     // (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1)
     /*  81074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81079 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  81081 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  81085 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  81087 */     GIR_RootConstrainSelectedInstOperands,
     /*  81088 */     // GIR_Coverage, 12181,
     /*  81088 */     GIR_EraseRootFromParent_Done,
     /*  81089 */   // Label 1269: @81089
     /*  81089 */   GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(81104), // Rule ID 7556 //
     /*  81094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  81097 */     // (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  81097 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  81102 */     GIR_RootConstrainSelectedInstOperands,
     /*  81103 */     // GIR_Coverage, 7556,
     /*  81103 */     GIR_Done,
     /*  81104 */   // Label 1270: @81104
     /*  81104 */   GIM_Reject,
     /*  81105 */ // Label 1235: @81105
     /*  81105 */ GIM_Reject,
     /*  81106 */ // Label 1044: @81106
     /*  81106 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(81137), // Rule ID 8574 //
     /*  81111 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  81114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  81117 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  81120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  81124 */   // (or:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  81124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  81127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  81129 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  81131 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  81133 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  81135 */   GIR_RootConstrainSelectedInstOperands,
     /*  81136 */   // GIR_Coverage, 8574,
     /*  81136 */   GIR_EraseRootFromParent_Done,
     /*  81137 */ // Label 1271: @81137
     /*  81137 */ GIM_Reject,
     /*  81138 */ // Label 1045: @81138
     /*  81138 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(84603),
     /*  81143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81146 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  81153 */   GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(81271), // Rule ID 16155 //
     /*  81158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81169 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81173 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81189 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81193 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81197 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81203 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81205 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81209 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81213 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81217 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81221 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81225 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81231 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81233 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81237 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81241 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81245 */     // MIs[6] Op3
     /*  81245 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  81250 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81252 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  81261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  81269 */     GIR_RootConstrainSelectedInstOperands,
     /*  81270 */     // GIR_Coverage, 16155,
     /*  81270 */     GIR_EraseRootFromParent_Done,
     /*  81271 */   // Label 1273: @81271
     /*  81271 */   GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(81389), // Rule ID 16157 //
     /*  81276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81295 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81299 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81303 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81307 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81311 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81315 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81321 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81323 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81327 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81331 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81335 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81339 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81343 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81349 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81351 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81355 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81359 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81363 */     // MIs[6] Op3
     /*  81363 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81368 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81370 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81375 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  81379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  81383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81387 */     GIR_RootConstrainSelectedInstOperands,
     /*  81388 */     // GIR_Coverage, 16157,
     /*  81388 */     GIR_EraseRootFromParent_Done,
     /*  81389 */   // Label 1274: @81389
     /*  81389 */   GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(81507), // Rule ID 16154 //
     /*  81394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81421 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81425 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81429 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81433 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81439 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81441 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81445 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81449 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81453 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81457 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81461 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81467 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81469 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81473 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81477 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81481 */     // MIs[6] Op3
     /*  81481 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  81486 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81488 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81493 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  81497 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  81505 */     GIR_RootConstrainSelectedInstOperands,
     /*  81506 */     // GIR_Coverage, 16154,
     /*  81506 */     GIR_EraseRootFromParent_Done,
     /*  81507 */   // Label 1275: @81507
     /*  81507 */   GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(81625), // Rule ID 16156 //
     /*  81512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81519 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81523 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81527 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81531 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81535 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81539 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81543 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81547 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81551 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81557 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81559 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81563 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81567 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81571 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81575 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81579 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81585 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81587 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81591 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81595 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81599 */     // MIs[6] Op3
     /*  81599 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81604 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81606 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  81615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  81619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81623 */     GIR_RootConstrainSelectedInstOperands,
     /*  81624 */     // GIR_Coverage, 16156,
     /*  81624 */     GIR_EraseRootFromParent_Done,
     /*  81625 */   // Label 1276: @81625
     /*  81625 */   GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(81743), // Rule ID 16060 //
     /*  81630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81633 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81637 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81641 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81645 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81649 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81653 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81657 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81661 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81665 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81669 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81675 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81677 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81681 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81685 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81689 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81693 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  81697 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81701 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81705 */     // MIs[5] Op3
     /*  81705 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  81710 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  81714 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81720 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  81722 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81724 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  81727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  81733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  81737 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  81741 */     GIR_RootConstrainSelectedInstOperands,
     /*  81742 */     // GIR_Coverage, 16060,
     /*  81742 */     GIR_EraseRootFromParent_Done,
     /*  81743 */   // Label 1277: @81743
     /*  81743 */   GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(81861), // Rule ID 16065 //
     /*  81748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81751 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81755 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81759 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81763 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81767 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81771 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81775 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81779 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81783 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81787 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81793 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81795 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81799 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81803 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81807 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  81811 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81815 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81819 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81823 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  81827 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81833 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  81835 */     // MIs[4] Op3
     /*  81835 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81840 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81842 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  81845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81847 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  81851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  81855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81859 */     GIR_RootConstrainSelectedInstOperands,
     /*  81860 */     // GIR_Coverage, 16065,
     /*  81860 */     GIR_EraseRootFromParent_Done,
     /*  81861 */   // Label 1278: @81861
     /*  81861 */   GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(81979), // Rule ID 16066 //
     /*  81866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81901 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81905 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81911 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81913 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81917 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81921 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81925 */     // MIs[4] Op3
     /*  81925 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81930 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81934 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81938 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81942 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  81946 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  81950 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81956 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  81958 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81960 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  81960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  81963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  81969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  81973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81977 */     GIR_RootConstrainSelectedInstOperands,
     /*  81978 */     // GIR_Coverage, 16066,
     /*  81978 */     GIR_EraseRootFromParent_Done,
     /*  81979 */   // Label 1279: @81979
     /*  81979 */   GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(82097), // Rule ID 12067 //
     /*  81984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81995 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  81999 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82003 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  82007 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82011 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82015 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82019 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82023 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82029 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82031 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82035 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82039 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82043 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82047 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82051 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82055 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82059 */     // MIs[5] Op3
     /*  82059 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  82064 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82068 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82074 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82076 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82078 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82083 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82087 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  82091 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  82095 */     GIR_RootConstrainSelectedInstOperands,
     /*  82096 */     // GIR_Coverage, 12067,
     /*  82096 */     GIR_EraseRootFromParent_Done,
     /*  82097 */   // Label 1280: @82097
     /*  82097 */   GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(82215), // Rule ID 16062 //
     /*  82102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82113 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82117 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82129 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82133 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82137 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82141 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82147 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82149 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82153 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82157 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82161 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82165 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82169 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82173 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82177 */     // MIs[5] Op3
     /*  82177 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  82182 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82186 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82192 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82194 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82196 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  82209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  82213 */     GIR_RootConstrainSelectedInstOperands,
     /*  82214 */     // GIR_Coverage, 16062,
     /*  82214 */     GIR_EraseRootFromParent_Done,
     /*  82215 */   // Label 1281: @82215
     /*  82215 */   GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(82333), // Rule ID 16063 //
     /*  82220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82247 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82251 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82255 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82259 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82265 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82267 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82271 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82275 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82279 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82283 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82287 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82291 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82295 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82299 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82305 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82307 */     // MIs[4] Op3
     /*  82307 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82312 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82314 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82319 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82323 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  82327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82331 */     GIR_RootConstrainSelectedInstOperands,
     /*  82332 */     // GIR_Coverage, 16063,
     /*  82332 */     GIR_EraseRootFromParent_Done,
     /*  82333 */   // Label 1282: @82333
     /*  82333 */   GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(82451), // Rule ID 16064 //
     /*  82338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82341 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82345 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82349 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82353 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82357 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82361 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82365 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82369 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82373 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82377 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82383 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82385 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82389 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82393 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82397 */     // MIs[4] Op3
     /*  82397 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82402 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82406 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82410 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82414 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82418 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82422 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82428 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82430 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82432 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82437 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82441 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  82445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82449 */     GIR_RootConstrainSelectedInstOperands,
     /*  82450 */     // GIR_Coverage, 16064,
     /*  82450 */     GIR_EraseRootFromParent_Done,
     /*  82451 */   // Label 1283: @82451
     /*  82451 */   GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(82569), // Rule ID 16061 //
     /*  82456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82463 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82467 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82471 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82483 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82487 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82491 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82495 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82501 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82503 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82507 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82511 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82515 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82519 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82523 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82527 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82531 */     // MIs[5] Op3
     /*  82531 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  82536 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82540 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82546 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82548 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82550 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82555 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  82563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  82567 */     GIR_RootConstrainSelectedInstOperands,
     /*  82568 */     // GIR_Coverage, 16061,
     /*  82568 */     GIR_EraseRootFromParent_Done,
     /*  82569 */   // Label 1284: @82569
     /*  82569 */   GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(82687), // Rule ID 16151 //
     /*  82574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82589 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82593 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  82597 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82601 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82605 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82609 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  82613 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82617 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82621 */     // MIs[3] Op3
     /*  82621 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  82626 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  82630 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82636 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  82638 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  82642 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82646 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82650 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82654 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82658 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82664 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82666 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82668 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  82671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82673 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  82677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  82681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  82685 */     GIR_RootConstrainSelectedInstOperands,
     /*  82686 */     // GIR_Coverage, 16151,
     /*  82686 */     GIR_EraseRootFromParent_Done,
     /*  82687 */   // Label 1285: @82687
     /*  82687 */   GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(82805), // Rule ID 16153 //
     /*  82692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82703 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82707 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82711 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  82715 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82719 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82723 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82727 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  82731 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82735 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82739 */     // MIs[3] Op3
     /*  82739 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  82744 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  82748 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82754 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  82756 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  82760 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82764 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82768 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82772 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82776 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82782 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82784 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82786 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  82789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  82795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  82799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  82803 */     GIR_RootConstrainSelectedInstOperands,
     /*  82804 */     // GIR_Coverage, 16153,
     /*  82804 */     GIR_EraseRootFromParent_Done,
     /*  82805 */   // Label 1286: @82805
     /*  82805 */   GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(82923), // Rule ID 12092 //
     /*  82810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82829 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  82833 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82837 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82841 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82845 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  82849 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82853 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82857 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82861 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  82865 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82871 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  82873 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  82877 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82881 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82885 */     // MIs[5] Op3
     /*  82885 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  82890 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82894 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82900 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82902 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82904 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  82904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  82907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  82913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  82917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  82921 */     GIR_RootConstrainSelectedInstOperands,
     /*  82922 */     // GIR_Coverage, 12092,
     /*  82922 */     GIR_EraseRootFromParent_Done,
     /*  82923 */   // Label 1287: @82923
     /*  82923 */   GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(83041), // Rule ID 16152 //
     /*  82928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82931 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82935 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82939 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82943 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82947 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  82951 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82955 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82959 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82963 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  82967 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82971 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  82975 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  82979 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  82983 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82989 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  82991 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  82995 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82999 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83003 */     // MIs[5] Op3
     /*  83003 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83008 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  83012 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83018 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  83020 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  83022 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83027 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83031 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  83035 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83039 */     GIR_RootConstrainSelectedInstOperands,
     /*  83040 */     // GIR_Coverage, 16152,
     /*  83040 */     GIR_EraseRootFromParent_Done,
     /*  83041 */   // Label 1288: @83041
     /*  83041 */   GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(83131), // Rule ID 15982 //
     /*  83046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83049 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83053 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83057 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83061 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  83069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83073 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83077 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83081 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83085 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83091 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83093 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83097 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83101 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83105 */     // MIs[4] Op3
     /*  83105 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83110 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83112 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  83121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  83125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83129 */     GIR_RootConstrainSelectedInstOperands,
     /*  83130 */     // GIR_Coverage, 15982,
     /*  83130 */     GIR_EraseRootFromParent_Done,
     /*  83131 */   // Label 1289: @83131
     /*  83131 */   GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(83221), // Rule ID 15981 //
     /*  83136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83151 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83155 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  83159 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83163 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83167 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83171 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83175 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83181 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83183 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83187 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83191 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83195 */     // MIs[4] Op3
     /*  83195 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83200 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83202 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  83211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  83215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83219 */     GIR_RootConstrainSelectedInstOperands,
     /*  83220 */     // GIR_Coverage, 15981,
     /*  83220 */     GIR_EraseRootFromParent_Done,
     /*  83221 */   // Label 1290: @83221
     /*  83221 */   GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(83311), // Rule ID 15980 //
     /*  83226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83241 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  83249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83257 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83261 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83265 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83271 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83273 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83277 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83281 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83285 */     // MIs[4] Op3
     /*  83285 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83290 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83292 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  83301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  83305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83309 */     GIR_RootConstrainSelectedInstOperands,
     /*  83310 */     // GIR_Coverage, 15980,
     /*  83310 */     GIR_EraseRootFromParent_Done,
     /*  83311 */   // Label 1291: @83311
     /*  83311 */   GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(83401), // Rule ID 15979 //
     /*  83316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83319 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83323 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83327 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83331 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83335 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  83339 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83343 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83347 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83351 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83355 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83361 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83363 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83367 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83371 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83375 */     // MIs[4] Op3
     /*  83375 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83380 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83382 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  83391 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  83395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83399 */     GIR_RootConstrainSelectedInstOperands,
     /*  83400 */     // GIR_Coverage, 15979,
     /*  83400 */     GIR_EraseRootFromParent_Done,
     /*  83401 */   // Label 1292: @83401
     /*  83401 */   GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(83491), // Rule ID 15976 //
     /*  83406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83409 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83413 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83417 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83421 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83425 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83429 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83433 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83437 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83441 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83445 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83449 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83453 */     // MIs[3] Op3
     /*  83453 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83458 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83462 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83468 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83470 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83472 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  83485 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83489 */     GIR_RootConstrainSelectedInstOperands,
     /*  83490 */     // GIR_Coverage, 15976,
     /*  83490 */     GIR_EraseRootFromParent_Done,
     /*  83491 */   // Label 1293: @83491
     /*  83491 */   GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(83581), // Rule ID 15978 //
     /*  83496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83511 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83515 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83519 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83523 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83527 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83531 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83535 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83539 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83543 */     // MIs[3] Op3
     /*  83543 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83548 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83552 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83558 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83560 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83562 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  83575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83579 */     GIR_RootConstrainSelectedInstOperands,
     /*  83580 */     // GIR_Coverage, 15978,
     /*  83580 */     GIR_EraseRootFromParent_Done,
     /*  83581 */   // Label 1294: @83581
     /*  83581 */   GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(83671), // Rule ID 12043 //
     /*  83586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83597 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83601 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83605 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83609 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83613 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83617 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83621 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83625 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83629 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83633 */     // MIs[3] Op3
     /*  83633 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83638 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83642 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83648 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83650 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83652 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83657 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  83665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83669 */     GIR_RootConstrainSelectedInstOperands,
     /*  83670 */     // GIR_Coverage, 12043,
     /*  83670 */     GIR_EraseRootFromParent_Done,
     /*  83671 */   // Label 1295: @83671
     /*  83671 */   GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(83761), // Rule ID 15977 //
     /*  83676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83679 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83683 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83687 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83691 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83695 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83699 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83703 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83707 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83711 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83715 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83719 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83723 */     // MIs[3] Op3
     /*  83723 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83728 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83732 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83738 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83740 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83742 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  83755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83759 */     GIR_RootConstrainSelectedInstOperands,
     /*  83760 */     // GIR_Coverage, 15977,
     /*  83760 */     GIR_EraseRootFromParent_Done,
     /*  83761 */   // Label 1296: @83761
     /*  83761 */   GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(83851), // Rule ID 16158 //
     /*  83766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83781 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83785 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83789 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83793 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83797 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83801 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83805 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  83809 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83813 */     // MIs[3] Op3
     /*  83813 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83818 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  83822 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83828 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83830 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83832 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83837 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83841 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  83845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83849 */     GIR_RootConstrainSelectedInstOperands,
     /*  83850 */     // GIR_Coverage, 16158,
     /*  83850 */     GIR_EraseRootFromParent_Done,
     /*  83851 */   // Label 1297: @83851
     /*  83851 */   GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(83941), // Rule ID 16160 //
     /*  83856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83859 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83863 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83867 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83871 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83883 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83887 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83891 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83895 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  83899 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83903 */     // MIs[3] Op3
     /*  83903 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83908 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  83912 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83918 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83920 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83922 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  83922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  83935 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83939 */     GIR_RootConstrainSelectedInstOperands,
     /*  83940 */     // GIR_Coverage, 16160,
     /*  83940 */     GIR_EraseRootFromParent_Done,
     /*  83941 */   // Label 1298: @83941
     /*  83941 */   GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(84031), // Rule ID 12093 //
     /*  83946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83949 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83953 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83957 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83965 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83969 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83973 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83977 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  83981 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83985 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  83989 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  83993 */     // MIs[3] Op3
     /*  83993 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83998 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84002 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84008 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84010 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84012 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84017 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  84021 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  84025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  84029 */     GIR_RootConstrainSelectedInstOperands,
     /*  84030 */     // GIR_Coverage, 12093,
     /*  84030 */     GIR_EraseRootFromParent_Done,
     /*  84031 */   // Label 1299: @84031
     /*  84031 */   GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(84121), // Rule ID 16159 //
     /*  84036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84039 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84043 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84047 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84051 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84055 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84059 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84063 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84067 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84071 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  84075 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84079 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84083 */     // MIs[3] Op3
     /*  84083 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  84088 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84092 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84098 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84100 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84102 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  84111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  84115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  84119 */     GIR_RootConstrainSelectedInstOperands,
     /*  84120 */     // GIR_Coverage, 16159,
     /*  84120 */     GIR_EraseRootFromParent_Done,
     /*  84121 */   // Label 1300: @84121
     /*  84121 */   GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(84211), // Rule ID 16162 //
     /*  84126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84137 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84141 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84145 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84149 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84153 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84157 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84161 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84165 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84171 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84173 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84177 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84181 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84185 */     // MIs[4] Op3
     /*  84185 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  84190 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84192 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84197 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  84201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  84209 */     GIR_RootConstrainSelectedInstOperands,
     /*  84210 */     // GIR_Coverage, 16162,
     /*  84210 */     GIR_EraseRootFromParent_Done,
     /*  84211 */   // Label 1301: @84211
     /*  84211 */   GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(84301), // Rule ID 16164 //
     /*  84216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84227 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84231 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84243 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84247 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84251 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84255 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84261 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84263 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84267 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84271 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84275 */     // MIs[4] Op3
     /*  84275 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  84280 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84282 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84287 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  84291 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  84295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  84299 */     GIR_RootConstrainSelectedInstOperands,
     /*  84300 */     // GIR_Coverage, 16164,
     /*  84300 */     GIR_EraseRootFromParent_Done,
     /*  84301 */   // Label 1302: @84301
     /*  84301 */   GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(84391), // Rule ID 16161 //
     /*  84306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84309 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84313 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84317 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84321 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84325 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84329 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84333 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84337 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84341 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84345 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84351 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84353 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84357 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84361 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84365 */     // MIs[4] Op3
     /*  84365 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  84370 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84372 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  84381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  84389 */     GIR_RootConstrainSelectedInstOperands,
     /*  84390 */     // GIR_Coverage, 16161,
     /*  84390 */     GIR_EraseRootFromParent_Done,
     /*  84391 */   // Label 1303: @84391
     /*  84391 */   GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(84481), // Rule ID 16163 //
     /*  84396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84399 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84403 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84407 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84411 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84415 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84419 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84423 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84427 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84431 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84435 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84441 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84443 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84447 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84451 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84455 */     // MIs[4] Op3
     /*  84455 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  84460 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84462 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  84462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  84471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  84475 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  84479 */     GIR_RootConstrainSelectedInstOperands,
     /*  84480 */     // GIR_Coverage, 16163,
     /*  84480 */     GIR_EraseRootFromParent_Done,
     /*  84481 */   // Label 1304: @84481
     /*  84481 */   GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(84534), // Rule ID 16404 //
     /*  84486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84505 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  84509 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84515 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  84517 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  84519 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1)
     /*  84519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84524 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  84526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  84530 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  84532 */     GIR_RootConstrainSelectedInstOperands,
     /*  84533 */     // GIR_Coverage, 16404,
     /*  84533 */     GIR_EraseRootFromParent_Done,
     /*  84534 */   // Label 1305: @84534
     /*  84534 */   GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(84587), // Rule ID 12169 //
     /*  84539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84542 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  84546 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84550 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  84554 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  84558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  84562 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84568 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  84570 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  84572 */     // (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1)
     /*  84572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84577 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  84579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  84583 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  84585 */     GIR_RootConstrainSelectedInstOperands,
     /*  84586 */     // GIR_Coverage, 12169,
     /*  84586 */     GIR_EraseRootFromParent_Done,
     /*  84587 */   // Label 1306: @84587
     /*  84587 */   GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(84602), // Rule ID 7555 //
     /*  84592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  84595 */     // (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  84595 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  84600 */     GIR_RootConstrainSelectedInstOperands,
     /*  84601 */     // GIR_Coverage, 7555,
     /*  84601 */     GIR_Done,
     /*  84602 */   // Label 1307: @84602
     /*  84602 */   GIM_Reject,
     /*  84603 */ // Label 1272: @84603
     /*  84603 */ GIM_Reject,
     /*  84604 */ // Label 1046: @84604
     /*  84604 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(84635), // Rule ID 8573 //
     /*  84609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  84612 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  84615 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  84618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  84622 */   // (or:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  84622 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  84625 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  84627 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  84629 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  84631 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  84633 */   GIR_RootConstrainSelectedInstOperands,
     /*  84634 */   // GIR_Coverage, 8573,
     /*  84634 */   GIR_EraseRootFromParent_Done,
     /*  84635 */ // Label 1308: @84635
     /*  84635 */ GIM_Reject,
     /*  84636 */ // Label 1047: @84636
     /*  84636 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(88101),
     /*  84641 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84644 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  84651 */   GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(84769), // Rule ID 16141 //
     /*  84656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84659 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84663 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84667 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84671 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84675 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84679 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84683 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84687 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84691 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  84695 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84701 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84703 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  84707 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84711 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84715 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84719 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  84723 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84729 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  84731 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  84735 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84739 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84743 */     // MIs[6] Op3
     /*  84743 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  84748 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  84750 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  84750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  84759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  84767 */     GIR_RootConstrainSelectedInstOperands,
     /*  84768 */     // GIR_Coverage, 16141,
     /*  84768 */     GIR_EraseRootFromParent_Done,
     /*  84769 */   // Label 1310: @84769
     /*  84769 */   GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(84887), // Rule ID 16143 //
     /*  84774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84777 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84781 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84785 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84789 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84793 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84797 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84801 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84805 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84809 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  84813 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84819 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84821 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  84825 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84829 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84833 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84837 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  84841 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84847 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  84849 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  84853 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84857 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84861 */     // MIs[6] Op3
     /*  84861 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  84866 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  84868 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  84868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84873 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  84877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  84881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  84885 */     GIR_RootConstrainSelectedInstOperands,
     /*  84886 */     // GIR_Coverage, 16143,
     /*  84886 */     GIR_EraseRootFromParent_Done,
     /*  84887 */   // Label 1311: @84887
     /*  84887 */   GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(85005), // Rule ID 16140 //
     /*  84892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84895 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84899 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84903 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84907 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84911 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84915 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84919 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84923 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84927 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  84931 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84937 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84939 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  84943 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84947 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84951 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  84955 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  84959 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84965 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  84967 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  84971 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84975 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  84979 */     // MIs[6] Op3
     /*  84979 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  84984 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  84986 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  84986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84991 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  84995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84999 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  85003 */     GIR_RootConstrainSelectedInstOperands,
     /*  85004 */     // GIR_Coverage, 16140,
     /*  85004 */     GIR_EraseRootFromParent_Done,
     /*  85005 */   // Label 1312: @85005
     /*  85005 */   GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(85123), // Rule ID 16142 //
     /*  85010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85013 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85017 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85021 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85025 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85029 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85033 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85037 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85041 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85045 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85049 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85055 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85057 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  85061 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85065 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85069 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85073 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85077 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85083 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  85085 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  85089 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85093 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85097 */     // MIs[6] Op3
     /*  85097 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85102 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85104 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  85107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  85113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  85117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85121 */     GIR_RootConstrainSelectedInstOperands,
     /*  85122 */     // GIR_Coverage, 16142,
     /*  85122 */     GIR_EraseRootFromParent_Done,
     /*  85123 */   // Label 1313: @85123
     /*  85123 */   GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(85241), // Rule ID 16053 //
     /*  85128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85143 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85155 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85159 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85163 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85167 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85173 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85175 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85179 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85183 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85187 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85191 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85195 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85199 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85203 */     // MIs[5] Op3
     /*  85203 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  85208 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85212 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85218 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85220 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85222 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  85231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  85235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  85239 */     GIR_RootConstrainSelectedInstOperands,
     /*  85240 */     // GIR_Coverage, 16053,
     /*  85240 */     GIR_EraseRootFromParent_Done,
     /*  85241 */   // Label 1314: @85241
     /*  85241 */   GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(85359), // Rule ID 16058 //
     /*  85246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85257 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85261 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85265 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85269 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85273 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85277 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85281 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85285 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85291 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85293 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85297 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85301 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85305 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85309 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85313 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85317 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85321 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85325 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85331 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85333 */     // MIs[4] Op3
     /*  85333 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85338 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85340 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85345 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  85353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85357 */     GIR_RootConstrainSelectedInstOperands,
     /*  85358 */     // GIR_Coverage, 16058,
     /*  85358 */     GIR_EraseRootFromParent_Done,
     /*  85359 */   // Label 1315: @85359
     /*  85359 */   GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(85477), // Rule ID 16059 //
     /*  85364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85379 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85387 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85391 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85395 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85399 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85403 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85409 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85411 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85415 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85419 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85423 */     // MIs[4] Op3
     /*  85423 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85428 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85432 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85436 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85440 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85444 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85448 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85454 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85456 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85458 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  85471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85475 */     GIR_RootConstrainSelectedInstOperands,
     /*  85476 */     // GIR_Coverage, 16059,
     /*  85476 */     GIR_EraseRootFromParent_Done,
     /*  85477 */   // Label 1316: @85477
     /*  85477 */   GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(85595), // Rule ID 12065 //
     /*  85482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85497 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85501 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85505 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85509 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85513 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85517 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85521 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85527 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85529 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85533 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85537 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85541 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85545 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85549 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85553 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85557 */     // MIs[5] Op3
     /*  85557 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  85562 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85566 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85572 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85574 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85576 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  85585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  85589 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  85593 */     GIR_RootConstrainSelectedInstOperands,
     /*  85594 */     // GIR_Coverage, 12065,
     /*  85594 */     GIR_EraseRootFromParent_Done,
     /*  85595 */   // Label 1317: @85595
     /*  85595 */   GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(85713), // Rule ID 16055 //
     /*  85600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85615 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85619 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  85623 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85627 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85631 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85635 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85639 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85645 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85647 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85651 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85655 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85659 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85663 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85667 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85671 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85675 */     // MIs[5] Op3
     /*  85675 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  85680 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85684 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85690 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85692 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85694 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85699 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  85703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  85707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  85711 */     GIR_RootConstrainSelectedInstOperands,
     /*  85712 */     // GIR_Coverage, 16055,
     /*  85712 */     GIR_EraseRootFromParent_Done,
     /*  85713 */   // Label 1318: @85713
     /*  85713 */   GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(85831), // Rule ID 16056 //
     /*  85718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85729 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85733 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  85741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85745 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85749 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85753 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85757 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85763 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85765 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85769 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85773 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85777 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85781 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85785 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85789 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85793 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85797 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85803 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85805 */     // MIs[4] Op3
     /*  85805 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85810 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85812 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85817 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  85825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85829 */     GIR_RootConstrainSelectedInstOperands,
     /*  85830 */     // GIR_Coverage, 16056,
     /*  85830 */     GIR_EraseRootFromParent_Done,
     /*  85831 */   // Label 1319: @85831
     /*  85831 */   GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(85949), // Rule ID 16057 //
     /*  85836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85839 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85843 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85847 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85851 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85855 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  85859 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85863 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85867 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85871 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85875 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85881 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85883 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85887 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85891 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85895 */     // MIs[4] Op3
     /*  85895 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85900 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85904 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85908 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85912 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85916 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85920 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85926 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85928 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85930 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  85930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85935 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  85943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85947 */     GIR_RootConstrainSelectedInstOperands,
     /*  85948 */     // GIR_Coverage, 16057,
     /*  85948 */     GIR_EraseRootFromParent_Done,
     /*  85949 */   // Label 1320: @85949
     /*  85949 */   GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(86067), // Rule ID 16054 //
     /*  85954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85969 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85973 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  85977 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85981 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  85985 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  85989 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85993 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85999 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86001 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86005 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86009 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86013 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86017 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  86021 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86025 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86029 */     // MIs[5] Op3
     /*  86029 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86034 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86038 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86044 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86046 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86048 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  86051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86053 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  86057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  86061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86065 */     GIR_RootConstrainSelectedInstOperands,
     /*  86066 */     // GIR_Coverage, 16054,
     /*  86066 */     GIR_EraseRootFromParent_Done,
     /*  86067 */   // Label 1321: @86067
     /*  86067 */   GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(86185), // Rule ID 16137 //
     /*  86072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86083 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86087 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86099 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86103 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86107 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86111 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86115 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86119 */     // MIs[3] Op3
     /*  86119 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  86124 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86128 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86134 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86136 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86140 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86144 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86148 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86152 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86156 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86162 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86164 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86166 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  86175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  86179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86183 */     GIR_RootConstrainSelectedInstOperands,
     /*  86184 */     // GIR_Coverage, 16137,
     /*  86184 */     GIR_EraseRootFromParent_Done,
     /*  86185 */   // Label 1322: @86185
     /*  86185 */   GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(86303), // Rule ID 16139 //
     /*  86190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86201 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86205 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86209 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86213 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86217 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86221 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86225 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86229 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86233 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86237 */     // MIs[3] Op3
     /*  86237 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86242 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86246 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86252 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86254 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86258 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86262 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86266 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86270 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86274 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86280 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86282 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86284 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86289 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  86293 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  86297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86301 */     GIR_RootConstrainSelectedInstOperands,
     /*  86302 */     // GIR_Coverage, 16139,
     /*  86302 */     GIR_EraseRootFromParent_Done,
     /*  86303 */   // Label 1323: @86303
     /*  86303 */   GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(86421), // Rule ID 12089 //
     /*  86308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86311 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86315 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86319 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86323 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86335 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86339 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86343 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86347 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86351 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86355 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86359 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86363 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86369 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86371 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86375 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86379 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86383 */     // MIs[5] Op3
     /*  86383 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  86388 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86392 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86398 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86400 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86402 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  86411 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  86415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86419 */     GIR_RootConstrainSelectedInstOperands,
     /*  86420 */     // GIR_Coverage, 12089,
     /*  86420 */     GIR_EraseRootFromParent_Done,
     /*  86421 */   // Label 1324: @86421
     /*  86421 */   GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(86539), // Rule ID 16138 //
     /*  86426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86429 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86433 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86437 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86441 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86453 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86457 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86461 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86465 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86469 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86473 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86477 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86481 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86487 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86489 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86493 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86497 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86501 */     // MIs[5] Op3
     /*  86501 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86506 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86510 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86516 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86518 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86520 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86525 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  86529 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  86533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86537 */     GIR_RootConstrainSelectedInstOperands,
     /*  86538 */     // GIR_Coverage, 16138,
     /*  86538 */     GIR_EraseRootFromParent_Done,
     /*  86539 */   // Label 1325: @86539
     /*  86539 */   GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(86629), // Rule ID 15975 //
     /*  86544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86547 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86551 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86555 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86559 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86563 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  86567 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86571 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86575 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86579 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86583 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86589 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86591 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86595 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86599 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86603 */     // MIs[4] Op3
     /*  86603 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86608 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  86610 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  86613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  86619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  86623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86627 */     GIR_RootConstrainSelectedInstOperands,
     /*  86628 */     // GIR_Coverage, 15975,
     /*  86628 */     GIR_EraseRootFromParent_Done,
     /*  86629 */   // Label 1326: @86629
     /*  86629 */   GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(86719), // Rule ID 15974 //
     /*  86634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86649 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  86657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86661 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86665 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86669 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86673 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86679 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86681 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86685 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86689 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86693 */     // MIs[4] Op3
     /*  86693 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86698 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  86700 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  86703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  86709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  86713 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86717 */     GIR_RootConstrainSelectedInstOperands,
     /*  86718 */     // GIR_Coverage, 15974,
     /*  86718 */     GIR_EraseRootFromParent_Done,
     /*  86719 */   // Label 1327: @86719
     /*  86719 */   GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(86809), // Rule ID 15973 //
     /*  86724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86739 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86743 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86747 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86751 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86755 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86759 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86763 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86769 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86771 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86775 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86779 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86783 */     // MIs[4] Op3
     /*  86783 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86788 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  86790 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  86793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  86799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  86803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86807 */     GIR_RootConstrainSelectedInstOperands,
     /*  86808 */     // GIR_Coverage, 15973,
     /*  86808 */     GIR_EraseRootFromParent_Done,
     /*  86809 */   // Label 1328: @86809
     /*  86809 */   GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(86899), // Rule ID 15972 //
     /*  86814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86829 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86833 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86837 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86841 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86845 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86849 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86853 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86859 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86861 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86865 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86869 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86873 */     // MIs[4] Op3
     /*  86873 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86878 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  86880 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  86883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86885 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  86889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  86893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86897 */     GIR_RootConstrainSelectedInstOperands,
     /*  86898 */     // GIR_Coverage, 15972,
     /*  86898 */     GIR_EraseRootFromParent_Done,
     /*  86899 */   // Label 1329: @86899
     /*  86899 */   GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(86989), // Rule ID 15969 //
     /*  86904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86911 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86915 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86919 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86931 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  86935 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86939 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86943 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86947 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  86951 */     // MIs[3] Op3
     /*  86951 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  86956 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86960 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86966 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86968 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  86970 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  86970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  86973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  86979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  86983 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86987 */     GIR_RootConstrainSelectedInstOperands,
     /*  86988 */     // GIR_Coverage, 15969,
     /*  86988 */     GIR_EraseRootFromParent_Done,
     /*  86989 */   // Label 1330: @86989
     /*  86989 */   GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(87079), // Rule ID 15971 //
     /*  86994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87005 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87009 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87021 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87025 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87029 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87033 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87037 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87041 */     // MIs[3] Op3
     /*  87041 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87046 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87050 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87056 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87058 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87060 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  87073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87077 */     GIR_RootConstrainSelectedInstOperands,
     /*  87078 */     // GIR_Coverage, 15971,
     /*  87078 */     GIR_EraseRootFromParent_Done,
     /*  87079 */   // Label 1331: @87079
     /*  87079 */   GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(87169), // Rule ID 12041 //
     /*  87084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87087 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87091 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87095 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87099 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87103 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87107 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87111 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87115 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87119 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87123 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87127 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87131 */     // MIs[3] Op3
     /*  87131 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87136 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87140 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87146 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87148 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87150 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87167 */     GIR_RootConstrainSelectedInstOperands,
     /*  87168 */     // GIR_Coverage, 12041,
     /*  87168 */     GIR_EraseRootFromParent_Done,
     /*  87169 */   // Label 1332: @87169
     /*  87169 */   GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(87259), // Rule ID 15970 //
     /*  87174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87193 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87197 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87201 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87205 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87209 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87213 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87217 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87221 */     // MIs[3] Op3
     /*  87221 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87226 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87230 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87236 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87238 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87240 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87245 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87257 */     GIR_RootConstrainSelectedInstOperands,
     /*  87258 */     // GIR_Coverage, 15970,
     /*  87258 */     GIR_EraseRootFromParent_Done,
     /*  87259 */   // Label 1333: @87259
     /*  87259 */   GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(87349), // Rule ID 16144 //
     /*  87264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87283 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87287 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87291 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87295 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87299 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87303 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87307 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87311 */     // MIs[3] Op3
     /*  87311 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87316 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87320 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87326 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87328 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87330 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  87343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87347 */     GIR_RootConstrainSelectedInstOperands,
     /*  87348 */     // GIR_Coverage, 16144,
     /*  87348 */     GIR_EraseRootFromParent_Done,
     /*  87349 */   // Label 1334: @87349
     /*  87349 */   GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(87439), // Rule ID 16146 //
     /*  87354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87369 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87373 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87377 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87381 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87385 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87389 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87393 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87397 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87401 */     // MIs[3] Op3
     /*  87401 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87406 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87410 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87416 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87418 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87420 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  87433 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87437 */     GIR_RootConstrainSelectedInstOperands,
     /*  87438 */     // GIR_Coverage, 16146,
     /*  87438 */     GIR_EraseRootFromParent_Done,
     /*  87439 */   // Label 1335: @87439
     /*  87439 */   GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(87529), // Rule ID 12090 //
     /*  87444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87447 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87451 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87455 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87459 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87463 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87467 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87471 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87475 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87479 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87483 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87487 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87491 */     // MIs[3] Op3
     /*  87491 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87496 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87500 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87506 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87508 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87510 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87515 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87519 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  87523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87527 */     GIR_RootConstrainSelectedInstOperands,
     /*  87528 */     // GIR_Coverage, 12090,
     /*  87528 */     GIR_EraseRootFromParent_Done,
     /*  87529 */   // Label 1336: @87529
     /*  87529 */   GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(87619), // Rule ID 16145 //
     /*  87534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87561 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87565 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87569 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87573 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87577 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87581 */     // MIs[3] Op3
     /*  87581 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87586 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87590 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87596 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87598 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87600 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  87613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87617 */     GIR_RootConstrainSelectedInstOperands,
     /*  87618 */     // GIR_Coverage, 16145,
     /*  87618 */     GIR_EraseRootFromParent_Done,
     /*  87619 */   // Label 1337: @87619
     /*  87619 */   GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(87709), // Rule ID 16148 //
     /*  87624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87627 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87631 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87635 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87639 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87643 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  87647 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87651 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87655 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87659 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  87663 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87669 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87671 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87675 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87679 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87683 */     // MIs[4] Op3
     /*  87683 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  87688 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87690 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87695 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  87699 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  87707 */     GIR_RootConstrainSelectedInstOperands,
     /*  87708 */     // GIR_Coverage, 16148,
     /*  87708 */     GIR_EraseRootFromParent_Done,
     /*  87709 */   // Label 1338: @87709
     /*  87709 */   GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(87799), // Rule ID 16150 //
     /*  87714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87717 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87721 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87725 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87729 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87733 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  87737 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87741 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87745 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87749 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  87753 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87759 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87761 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87765 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87769 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87773 */     // MIs[4] Op3
     /*  87773 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87778 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87780 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87785 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  87789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  87793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87797 */     GIR_RootConstrainSelectedInstOperands,
     /*  87798 */     // GIR_Coverage, 16150,
     /*  87798 */     GIR_EraseRootFromParent_Done,
     /*  87799 */   // Label 1339: @87799
     /*  87799 */   GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(87889), // Rule ID 16147 //
     /*  87804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87807 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87811 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87815 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87819 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87823 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  87827 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87831 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87835 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87839 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  87843 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87849 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87851 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87855 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87859 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87863 */     // MIs[4] Op3
     /*  87863 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  87868 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87870 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  87879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  87887 */     GIR_RootConstrainSelectedInstOperands,
     /*  87888 */     // GIR_Coverage, 16147,
     /*  87888 */     GIR_EraseRootFromParent_Done,
     /*  87889 */   // Label 1340: @87889
     /*  87889 */   GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(87979), // Rule ID 16149 //
     /*  87894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87909 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  87917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87925 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  87929 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  87933 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87939 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87941 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87945 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87949 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87953 */     // MIs[4] Op3
     /*  87953 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87958 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87960 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  87960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  87969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  87973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87977 */     GIR_RootConstrainSelectedInstOperands,
     /*  87978 */     // GIR_Coverage, 16149,
     /*  87978 */     GIR_EraseRootFromParent_Done,
     /*  87979 */   // Label 1341: @87979
     /*  87979 */   GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(88032), // Rule ID 16395 //
     /*  87984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87995 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  87999 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88003 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  88007 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88013 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  88015 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  88017 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1)
     /*  88017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88022 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  88024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  88028 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  88030 */     GIR_RootConstrainSelectedInstOperands,
     /*  88031 */     // GIR_Coverage, 16395,
     /*  88031 */     GIR_EraseRootFromParent_Done,
     /*  88032 */   // Label 1342: @88032
     /*  88032 */   GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(88085), // Rule ID 12157 //
     /*  88037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88052 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88056 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  88060 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88066 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  88068 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  88070 */     // (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1)
     /*  88070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88075 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  88077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  88081 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  88083 */     GIR_RootConstrainSelectedInstOperands,
     /*  88084 */     // GIR_Coverage, 12157,
     /*  88084 */     GIR_EraseRootFromParent_Done,
     /*  88085 */   // Label 1343: @88085
     /*  88085 */   GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(88100), // Rule ID 7554 //
     /*  88090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  88093 */     // (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  88093 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  88098 */     GIR_RootConstrainSelectedInstOperands,
     /*  88099 */     // GIR_Coverage, 7554,
     /*  88099 */     GIR_Done,
     /*  88100 */   // Label 1344: @88100
     /*  88100 */   GIM_Reject,
     /*  88101 */ // Label 1309: @88101
     /*  88101 */ GIM_Reject,
     /*  88102 */ // Label 1048: @88102
     /*  88102 */ GIM_Reject,
     /*  88103 */ // Label 7: @88103
     /*  88103 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1363*/ GIMT_Encode4(100562),
     /*  88114 */ /*GILLT_s32*//*Label 1345*/ GIMT_Encode4(88202),
     /*  88118 */ /*GILLT_s64*//*Label 1346*/ GIMT_Encode4(89066), GIMT_Encode4(0),
     /*  88126 */ /*GILLT_v2s32*//*Label 1347*/ GIMT_Encode4(90093),
     /*  88130 */ /*GILLT_v2s64*//*Label 1348*/ GIMT_Encode4(90328),
     /*  88134 */ /*GILLT_v4s16*//*Label 1349*/ GIMT_Encode4(91017),
     /*  88138 */ /*GILLT_v4s32*//*Label 1350*/ GIMT_Encode4(91252),
     /*  88142 */ /*GILLT_v8s8*//*Label 1351*/ GIMT_Encode4(91941),
     /*  88146 */ /*GILLT_v8s16*//*Label 1352*/ GIMT_Encode4(92179),
     /*  88150 */ /*GILLT_v16s8*//*Label 1353*/ GIMT_Encode4(92868),
     /*  88154 */ /*GILLT_nxv1s1*//*Label 1354*/ GIMT_Encode4(93560),
     /*  88158 */ /*GILLT_nxv2s1*//*Label 1355*/ GIMT_Encode4(93610), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  88170 */ /*GILLT_nxv2s64*//*Label 1356*/ GIMT_Encode4(93660),
     /*  88174 */ /*GILLT_nxv4s1*//*Label 1357*/ GIMT_Encode4(95348), GIMT_Encode4(0),
     /*  88182 */ /*GILLT_nxv4s32*//*Label 1358*/ GIMT_Encode4(95398),
     /*  88186 */ /*GILLT_nxv8s1*//*Label 1359*/ GIMT_Encode4(97086),
     /*  88190 */ /*GILLT_nxv8s16*//*Label 1360*/ GIMT_Encode4(97136),
     /*  88194 */ /*GILLT_nxv16s1*//*Label 1361*/ GIMT_Encode4(98824),
     /*  88198 */ /*GILLT_nxv16s8*//*Label 1362*/ GIMT_Encode4(98874),
     /*  88202 */ // Label 1345: @88202
     /*  88202 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(89065),
     /*  88207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  88210 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  88213 */   GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(88275), // Rule ID 13538 //
     /*  88218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88222 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88226 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88230 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88234 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88238 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88243 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  88247 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88251 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88253 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88260 */     // (xor:{ *:[i32] } (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  88269 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88273 */     GIR_RootConstrainSelectedInstOperands,
     /*  88274 */     // GIR_Coverage, 13538,
     /*  88274 */     GIR_EraseRootFromParent_Done,
     /*  88275 */   // Label 1365: @88275
     /*  88275 */   GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(88337), // Rule ID 169 //
     /*  88280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88296 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88300 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88305 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  88309 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88313 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88315 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88322 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88331 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88335 */     GIR_RootConstrainSelectedInstOperands,
     /*  88336 */     // GIR_Coverage, 169,
     /*  88336 */     GIR_EraseRootFromParent_Done,
     /*  88337 */   // Label 1366: @88337
     /*  88337 */   GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(88395), // Rule ID 13536 //
     /*  88342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88346 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88350 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88354 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88358 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88362 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88367 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88371 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88380 */     // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }))  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88389 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88393 */     GIR_RootConstrainSelectedInstOperands,
     /*  88394 */     // GIR_Coverage, 13536,
     /*  88394 */     GIR_EraseRootFromParent_Done,
     /*  88395 */   // Label 1367: @88395
     /*  88395 */   GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(88450), // Rule ID 13535 //
     /*  88400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88404 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88408 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88412 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88416 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88420 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88428 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88430 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88437 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  88444 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88448 */     GIR_RootConstrainSelectedInstOperands,
     /*  88449 */     // GIR_Coverage, 13535,
     /*  88449 */     GIR_EraseRootFromParent_Done,
     /*  88450 */   // Label 1368: @88450
     /*  88450 */   GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(88508), // Rule ID 13533 //
     /*  88455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88463 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88467 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88471 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88475 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88480 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88484 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88486 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88493 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88498 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  88502 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88506 */     GIR_RootConstrainSelectedInstOperands,
     /*  88507 */     // GIR_Coverage, 13533,
     /*  88507 */     GIR_EraseRootFromParent_Done,
     /*  88508 */   // Label 1369: @88508
     /*  88508 */   GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(88566), // Rule ID 168 //
     /*  88513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88533 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88538 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88542 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88544 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88551 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift), -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88556 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88560 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88564 */     GIR_RootConstrainSelectedInstOperands,
     /*  88565 */     // GIR_Coverage, 168,
     /*  88565 */     GIR_EraseRootFromParent_Done,
     /*  88566 */   // Label 1370: @88566
     /*  88566 */   GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(88624), // Rule ID 13534 //
     /*  88571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88575 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88579 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88583 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88587 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88591 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88596 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88600 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88609 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88618 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88622 */     GIR_RootConstrainSelectedInstOperands,
     /*  88623 */     // GIR_Coverage, 13534,
     /*  88623 */     GIR_EraseRootFromParent_Done,
     /*  88624 */   // Label 1371: @88624
     /*  88624 */   GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(88679), // Rule ID 13537 //
     /*  88629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88649 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88653 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88657 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88659 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88666 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  88669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88671 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  88673 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88677 */     GIR_RootConstrainSelectedInstOperands,
     /*  88678 */     // GIR_Coverage, 13537,
     /*  88678 */     GIR_EraseRootFromParent_Done,
     /*  88679 */   // Label 1372: @88679
     /*  88679 */   GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(88720), // Rule ID 144 //
     /*  88684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  88688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  88700 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  88704 */     // MIs[1] Operand 1
     /*  88704 */     // No operand predicates
     /*  88704 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88706 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  88706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
     /*  88709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88711 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  88713 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  88718 */     GIR_RootConstrainSelectedInstOperands,
     /*  88719 */     // GIR_Coverage, 144,
     /*  88719 */     GIR_EraseRootFromParent_Done,
     /*  88720 */   // Label 1373: @88720
     /*  88720 */   GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(88753), // Rule ID 13545 //
     /*  88725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88729 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88740 */     // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
     /*  88743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  88747 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88751 */     GIR_RootConstrainSelectedInstOperands,
     /*  88752 */     // GIR_Coverage, 13545,
     /*  88752 */     GIR_EraseRootFromParent_Done,
     /*  88753 */   // Label 1374: @88753
     /*  88753 */   GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(88813), // Rule ID 165 //
     /*  88758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88762 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88766 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88770 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88774 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88778 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88783 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88788 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  88792 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88796 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88798 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  88798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  88801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88807 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  88811 */     GIR_RootConstrainSelectedInstOperands,
     /*  88812 */     // GIR_Coverage, 165,
     /*  88812 */     GIR_EraseRootFromParent_Done,
     /*  88813 */   // Label 1375: @88813
     /*  88813 */   GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(88846), // Rule ID 174 //
     /*  88818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88822 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  88833 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  88833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
     /*  88836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88838 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  88840 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  88844 */     GIR_RootConstrainSelectedInstOperands,
     /*  88845 */     // GIR_Coverage, 174,
     /*  88845 */     GIR_EraseRootFromParent_Done,
     /*  88846 */   // Label 1376: @88846
     /*  88846 */   GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(88899), // Rule ID 13529 //
     /*  88851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88859 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88863 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88867 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88876 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88884 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88886 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm)  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  88886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  88889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88895 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  88897 */     GIR_RootConstrainSelectedInstOperands,
     /*  88898 */     // GIR_Coverage, 13529,
     /*  88898 */     GIR_EraseRootFromParent_Done,
     /*  88899 */   // Label 1377: @88899
     /*  88899 */   GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(88955), // Rule ID 164 //
     /*  88904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88912 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88916 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88920 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88924 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88929 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88934 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  88938 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88940 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] })  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  88940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  88943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  88945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  88949 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  88953 */     GIR_RootConstrainSelectedInstOperands,
     /*  88954 */     // GIR_Coverage, 164,
     /*  88954 */     GIR_EraseRootFromParent_Done,
     /*  88955 */   // Label 1378: @88955
     /*  88955 */   GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(89008), // Rule ID 13530 //
     /*  88960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88964 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88968 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88972 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88976 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  88980 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  88984 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  88989 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  88993 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  88995 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }))  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  88995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  88998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89000 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89004 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  89006 */     GIR_RootConstrainSelectedInstOperands,
     /*  89007 */     // GIR_Coverage, 13530,
     /*  89007 */     GIR_EraseRootFromParent_Done,
     /*  89008 */   // Label 1379: @89008
     /*  89008 */   GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(89040), // Rule ID 4035 //
     /*  89013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  89017 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  89021 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89025 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] })  =>  (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
     /*  89025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  89028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89030 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  89036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Wm
     /*  89038 */     GIR_RootConstrainSelectedInstOperands,
     /*  89039 */     // GIR_Coverage, 4035,
     /*  89039 */     GIR_EraseRootFromParent_Done,
     /*  89040 */   // Label 1380: @89040
     /*  89040 */   GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(89064), // Rule ID 172 //
     /*  89045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  89049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  89053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  89057 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  89057 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORWrr),
     /*  89062 */     GIR_RootConstrainSelectedInstOperands,
     /*  89063 */     // GIR_Coverage, 172,
     /*  89063 */     GIR_Done,
     /*  89064 */   // Label 1381: @89064
     /*  89064 */   GIM_Reject,
     /*  89065 */ // Label 1364: @89065
     /*  89065 */ GIM_Reject,
     /*  89066 */ // Label 1346: @89066
     /*  89066 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(90092),
     /*  89071 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  89074 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  89077 */   GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(89139), // Rule ID 13544 //
     /*  89082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89090 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  89094 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89098 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89102 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89107 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  89111 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89115 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89117 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89124 */     // (xor:{ *:[i64] } (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  89133 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89137 */     GIR_RootConstrainSelectedInstOperands,
     /*  89138 */     // GIR_Coverage, 13544,
     /*  89138 */     GIR_EraseRootFromParent_Done,
     /*  89139 */   // Label 1383: @89139
     /*  89139 */   GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(89201), // Rule ID 171 //
     /*  89144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  89156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89160 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89164 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89169 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  89173 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89177 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89179 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89186 */     // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89191 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89195 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89199 */     GIR_RootConstrainSelectedInstOperands,
     /*  89200 */     // GIR_Coverage, 171,
     /*  89200 */     GIR_EraseRootFromParent_Done,
     /*  89201 */   // Label 1384: @89201
     /*  89201 */   GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(89259), // Rule ID 13542 //
     /*  89206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89210 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  89214 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89218 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89222 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89231 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89244 */     // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }))  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89253 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89257 */     GIR_RootConstrainSelectedInstOperands,
     /*  89258 */     // GIR_Coverage, 13542,
     /*  89258 */     GIR_EraseRootFromParent_Done,
     /*  89259 */   // Label 1385: @89259
     /*  89259 */   GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(89314), // Rule ID 13541 //
     /*  89264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89284 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89294 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89301 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  89308 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89312 */     GIR_RootConstrainSelectedInstOperands,
     /*  89313 */     // GIR_Coverage, 13541,
     /*  89313 */     GIR_EraseRootFromParent_Done,
     /*  89314 */   // Label 1386: @89314
     /*  89314 */   GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(89372), // Rule ID 13539 //
     /*  89319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89323 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89327 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89331 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89335 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89339 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89344 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89348 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89350 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89357 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  89366 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89370 */     GIR_RootConstrainSelectedInstOperands,
     /*  89371 */     // GIR_Coverage, 13539,
     /*  89371 */     GIR_EraseRootFromParent_Done,
     /*  89372 */   // Label 1387: @89372
     /*  89372 */   GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(89430), // Rule ID 170 //
     /*  89377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89385 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89389 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89393 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89397 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89402 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89406 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89408 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89415 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift), -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89420 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89424 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89428 */     GIR_RootConstrainSelectedInstOperands,
     /*  89429 */     // GIR_Coverage, 170,
     /*  89429 */     GIR_EraseRootFromParent_Done,
     /*  89430 */   // Label 1388: @89430
     /*  89430 */   GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(89488), // Rule ID 13540 //
     /*  89435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89451 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89455 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89460 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89464 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89473 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89482 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89486 */     GIR_RootConstrainSelectedInstOperands,
     /*  89487 */     // GIR_Coverage, 13540,
     /*  89487 */     GIR_EraseRootFromParent_Done,
     /*  89488 */   // Label 1389: @89488
     /*  89488 */   GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(89543), // Rule ID 13543 //
     /*  89493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89497 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  89505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89513 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89517 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89521 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89523 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89530 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  89533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  89537 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89541 */     GIR_RootConstrainSelectedInstOperands,
     /*  89542 */     // GIR_Coverage, 13543,
     /*  89542 */     GIR_EraseRootFromParent_Done,
     /*  89543 */   // Label 1390: @89543
     /*  89543 */   GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(89643), // Rule ID 1617 //
     /*  89548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  89551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  89555 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89559 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  89563 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89567 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /*  89571 */     // MIs[1] Operand 1
     /*  89571 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  89576 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  89580 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89584 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  89588 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  89592 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  89597 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  89602 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  89606 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89612 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  89614 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89618 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89624 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  89626 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  89628 */     // (xor:{ *:[v1i64] } (setcc:{ *:[v1i64] } (and:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm), immAllZerosV:{ *:[v1i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v1i64] })  =>  (CMTSTv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  89628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv1i64),
     /*  89631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89633 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  89637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  89641 */     GIR_RootConstrainSelectedInstOperands,
     /*  89642 */     // GIR_Coverage, 1617,
     /*  89642 */     GIR_EraseRootFromParent_Done,
     /*  89643 */   // Label 1391: @89643
     /*  89643 */   GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(89684), // Rule ID 145 //
     /*  89648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  89652 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89656 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  89660 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  89664 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  89668 */     // MIs[1] Operand 1
     /*  89668 */     // No operand predicates
     /*  89668 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89670 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  89670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXri),
     /*  89673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89675 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  89677 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  89682 */     GIR_RootConstrainSelectedInstOperands,
     /*  89683 */     // GIR_Coverage, 145,
     /*  89683 */     GIR_EraseRootFromParent_Done,
     /*  89684 */   // Label 1392: @89684
     /*  89684 */   GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(89717), // Rule ID 13546 //
     /*  89689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89693 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89704 */     // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
     /*  89707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  89711 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89715 */     GIR_RootConstrainSelectedInstOperands,
     /*  89716 */     // GIR_Coverage, 13546,
     /*  89716 */     GIR_EraseRootFromParent_Done,
     /*  89717 */   // Label 1393: @89717
     /*  89717 */   GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(89777), // Rule ID 167 //
     /*  89722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  89734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89742 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89747 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89752 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  89756 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89760 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89762 */     // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  89762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  89765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89771 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  89775 */     GIR_RootConstrainSelectedInstOperands,
     /*  89776 */     // GIR_Coverage, 167,
     /*  89776 */     GIR_EraseRootFromParent_Done,
     /*  89777 */   // Label 1394: @89777
     /*  89777 */   GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(89810), // Rule ID 175 //
     /*  89782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  89797 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  89797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
     /*  89800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89802 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  89804 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  89808 */     GIR_RootConstrainSelectedInstOperands,
     /*  89809 */     // GIR_Coverage, 175,
     /*  89809 */     GIR_EraseRootFromParent_Done,
     /*  89810 */   // Label 1395: @89810
     /*  89810 */   GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(89863), // Rule ID 13531 //
     /*  89815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89840 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89848 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89850 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm)  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  89850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  89853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  89861 */     GIR_RootConstrainSelectedInstOperands,
     /*  89862 */     // GIR_Coverage, 13531,
     /*  89862 */     GIR_EraseRootFromParent_Done,
     /*  89863 */   // Label 1396: @89863
     /*  89863 */   GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(89919), // Rule ID 166 //
     /*  89868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89872 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89876 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89880 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89884 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89888 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89898 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89902 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89904 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] })  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  89904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  89907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  89917 */     GIR_RootConstrainSelectedInstOperands,
     /*  89918 */     // GIR_Coverage, 166,
     /*  89918 */     GIR_EraseRootFromParent_Done,
     /*  89919 */   // Label 1397: @89919
     /*  89919 */   GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(89972), // Rule ID 13532 //
     /*  89924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89928 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  89936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  89944 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  89948 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89953 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
     /*  89957 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  89959 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }))  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  89959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  89962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89964 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  89968 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  89970 */     GIR_RootConstrainSelectedInstOperands,
     /*  89971 */     // GIR_Coverage, 13532,
     /*  89971 */     GIR_EraseRootFromParent_Done,
     /*  89972 */   // Label 1398: @89972
     /*  89972 */   GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(90004), // Rule ID 4036 //
     /*  89977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89981 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  89985 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
     /*  89989 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] })  =>  (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm)
     /*  89989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  89992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  89994 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  90000 */     GIR_RootToRootCopy, /*OpIdx*/1, // Xm
     /*  90002 */     GIR_RootConstrainSelectedInstOperands,
     /*  90003 */     // GIR_Coverage, 4036,
     /*  90003 */     GIR_EraseRootFromParent_Done,
     /*  90004 */   // Label 1399: @90004
     /*  90004 */   GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(90040), // Rule ID 5020 //
     /*  90009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90013 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90021 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90027 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  90029 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  90031 */     // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] })  =>  (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
     /*  90031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  90034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  90038 */     GIR_RootConstrainSelectedInstOperands,
     /*  90039 */     // GIR_Coverage, 5020,
     /*  90039 */     GIR_EraseRootFromParent_Done,
     /*  90040 */   // Label 1400: @90040
     /*  90040 */   GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(90064), // Rule ID 173 //
     /*  90045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  90049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  90053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  90057 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  90057 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORXrr),
     /*  90062 */     GIR_RootConstrainSelectedInstOperands,
     /*  90063 */     // GIR_Coverage, 173,
     /*  90063 */     GIR_Done,
     /*  90064 */   // Label 1401: @90064
     /*  90064 */   GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(90091), // Rule ID 5098 //
     /*  90069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  90072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90076 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90084 */     // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  90084 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  90089 */     GIR_RootConstrainSelectedInstOperands,
     /*  90090 */     // GIR_Coverage, 5098,
     /*  90090 */     GIR_Done,
     /*  90091 */   // Label 1402: @90091
     /*  90091 */   GIM_Reject,
     /*  90092 */ // Label 1382: @90092
     /*  90092 */ GIM_Reject,
     /*  90093 */ // Label 1347: @90093
     /*  90093 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(90327),
     /*  90098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  90101 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  90104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90108 */   GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(90204), // Rule ID 1164 //
     /*  90113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  90116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  90124 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  90128 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  90132 */     // MIs[1] Operand 1
     /*  90132 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  90137 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90141 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90145 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  90149 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  90153 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90158 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90163 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  90167 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90173 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  90175 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90179 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90185 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90187 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90189 */     // (xor:{ *:[v2i32] } (setcc:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i32] })  =>  (CMTSTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  90189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i32),
     /*  90192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90194 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  90198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  90202 */     GIR_RootConstrainSelectedInstOperands,
     /*  90203 */     // GIR_Coverage, 1164,
     /*  90203 */     GIR_EraseRootFromParent_Done,
     /*  90204 */   // Label 1404: @90204
     /*  90204 */   GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(90271), // Rule ID 5067 //
     /*  90209 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90213 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  90217 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  90221 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  90225 */     // MIs[1] Operand 1
     /*  90225 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  90230 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  90234 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90240 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  90242 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  90246 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90252 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90254 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90256 */     // (xor:{ *:[v2i32] } (setcc:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i32] })  =>  (CMTSTv2i32:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$Rn, v2i32:{ *:[v2i32] }:$Rn)
     /*  90256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i32),
     /*  90259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  90265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  90269 */     GIR_RootConstrainSelectedInstOperands,
     /*  90270 */     // GIR_Coverage, 5067,
     /*  90270 */     GIR_EraseRootFromParent_Done,
     /*  90271 */   // Label 1405: @90271
     /*  90271 */   GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(90303), // Rule ID 5018 //
     /*  90276 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90284 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90290 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  90292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  90294 */     // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] })  =>  (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /*  90294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  90297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90299 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  90301 */     GIR_RootConstrainSelectedInstOperands,
     /*  90302 */     // GIR_Coverage, 5018,
     /*  90302 */     GIR_EraseRootFromParent_Done,
     /*  90303 */   // Label 1406: @90303
     /*  90303 */   GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(90326), // Rule ID 5097 //
     /*  90308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  90311 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  90319 */     // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  90319 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  90324 */     GIR_RootConstrainSelectedInstOperands,
     /*  90325 */     // GIR_Coverage, 5097,
     /*  90325 */     GIR_Done,
     /*  90326 */   // Label 1407: @90326
     /*  90326 */   GIM_Reject,
     /*  90327 */ // Label 1403: @90327
     /*  90327 */ GIM_Reject,
     /*  90328 */ // Label 1348: @90328
     /*  90328 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(91016),
     /*  90333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90336 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90343 */   GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(90439), // Rule ID 1166 //
     /*  90348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  90351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  90359 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90363 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /*  90367 */     // MIs[1] Operand 1
     /*  90367 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  90372 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90376 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90380 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90384 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90388 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90393 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90398 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  90402 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90408 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  90410 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90414 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90420 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90422 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90424 */     // (xor:{ *:[v2i64] } (setcc:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i64] })  =>  (CMTSTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  90424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i64),
     /*  90427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  90433 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  90437 */     GIR_RootConstrainSelectedInstOperands,
     /*  90438 */     // GIR_Coverage, 1166,
     /*  90438 */     GIR_EraseRootFromParent_Done,
     /*  90439 */   // Label 1409: @90439
     /*  90439 */   GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(90506), // Rule ID 5069 //
     /*  90444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  90452 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90456 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /*  90460 */     // MIs[1] Operand 1
     /*  90460 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  90465 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  90469 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90475 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  90477 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  90481 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90487 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90489 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90491 */     // (xor:{ *:[v2i64] } (setcc:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i64] })  =>  (CMTSTv2i64:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, v2i64:{ *:[v2i64] }:$Rn)
     /*  90491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i64),
     /*  90494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  90500 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  90504 */     GIR_RootConstrainSelectedInstOperands,
     /*  90505 */     // GIR_Coverage, 5069,
     /*  90505 */     GIR_EraseRootFromParent_Done,
     /*  90506 */   // Label 1410: @90506
     /*  90506 */   GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(90591), // Rule ID 14083 //
     /*  90511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90518 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90522 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90526 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90530 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  90534 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90538 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90542 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90546 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90551 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90555 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90561 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90572 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90574 */     // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Vn)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  90577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90579 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  90581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  90585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  90589 */     GIR_RootConstrainSelectedInstOperands,
     /*  90590 */     // GIR_Coverage, 14083,
     /*  90590 */     GIR_EraseRootFromParent_Done,
     /*  90591 */   // Label 1411: @90591
     /*  90591 */   GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(90676), // Rule ID 14082 //
     /*  90596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90611 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90615 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90620 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90624 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90628 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90632 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90636 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90641 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90645 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90651 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90657 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90659 */     // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })), V128:{ *:[v2i64] }:$Vn)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  90662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  90666 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  90670 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  90674 */     GIR_RootConstrainSelectedInstOperands,
     /*  90675 */     // GIR_Coverage, 14082,
     /*  90675 */     GIR_EraseRootFromParent_Done,
     /*  90676 */   // Label 1412: @90676
     /*  90676 */   GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(90761), // Rule ID 14081 //
     /*  90681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90684 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90700 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90704 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  90708 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90712 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90716 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90720 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90725 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90729 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90735 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90737 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90742 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90744 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm))  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  90747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90749 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  90751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  90755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  90759 */     GIR_RootConstrainSelectedInstOperands,
     /*  90760 */     // GIR_Coverage, 14081,
     /*  90760 */     GIR_EraseRootFromParent_Done,
     /*  90761 */   // Label 1413: @90761
     /*  90761 */   GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(90846), // Rule ID 3863 //
     /*  90766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90781 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90785 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90789 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90794 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90798 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90802 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90806 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90810 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90815 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90819 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90825 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90827 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  90829 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })))  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  90832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90834 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  90836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  90840 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  90844 */     GIR_RootConstrainSelectedInstOperands,
     /*  90845 */     // GIR_Coverage, 3863,
     /*  90845 */     GIR_EraseRootFromParent_Done,
     /*  90846 */   // Label 1414: @90846
     /*  90846 */   GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(90878), // Rule ID 5021 //
     /*  90851 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90859 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90865 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  90867 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  90869 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] })  =>  (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /*  90869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  90872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  90874 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  90876 */     GIR_RootConstrainSelectedInstOperands,
     /*  90877 */     // GIR_Coverage, 5021,
     /*  90877 */     GIR_EraseRootFromParent_Done,
     /*  90878 */   // Label 1415: @90878
     /*  90878 */   GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(90935), // Rule ID 3859 //
     /*  90883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90886 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90890 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90894 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90898 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90902 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90907 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90912 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90916 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  90918 */     // (xor:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Va)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  90921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  90927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  90931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  90933 */     GIR_RootConstrainSelectedInstOperands,
     /*  90934 */     // GIR_Coverage, 3859,
     /*  90934 */     GIR_EraseRootFromParent_Done,
     /*  90935 */   // Label 1416: @90935
     /*  90935 */   GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(90992), // Rule ID 14071 //
     /*  90940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  90943 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90947 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  90951 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90955 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  90959 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  90963 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90968 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  90973 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  90975 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm))  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  90975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  90978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  90980 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  90984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  90988 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  90990 */     GIR_RootConstrainSelectedInstOperands,
     /*  90991 */     // GIR_Coverage, 14071,
     /*  90991 */     GIR_EraseRootFromParent_Done,
     /*  90992 */   // Label 1417: @90992
     /*  90992 */   GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(91015), // Rule ID 5101 //
     /*  90997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91000 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91004 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91008 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  91008 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  91013 */     GIR_RootConstrainSelectedInstOperands,
     /*  91014 */     // GIR_Coverage, 5101,
     /*  91014 */     GIR_Done,
     /*  91015 */   // Label 1418: @91015
     /*  91015 */   GIM_Reject,
     /*  91016 */ // Label 1408: @91016
     /*  91016 */ GIM_Reject,
     /*  91017 */ // Label 1349: @91017
     /*  91017 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(91251),
     /*  91022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  91025 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  91028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91032 */   GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(91128), // Rule ID 1162 //
     /*  91037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  91048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  91052 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  91056 */     // MIs[1] Operand 1
     /*  91056 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  91061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91069 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  91073 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  91077 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91082 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91087 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  91091 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91097 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  91099 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91103 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91109 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91111 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91113 */     // (xor:{ *:[v4i16] } (setcc:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i16] })  =>  (CMTSTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  91113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i16),
     /*  91116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  91122 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  91126 */     GIR_RootConstrainSelectedInstOperands,
     /*  91127 */     // GIR_Coverage, 1162,
     /*  91127 */     GIR_EraseRootFromParent_Done,
     /*  91128 */   // Label 1420: @91128
     /*  91128 */   GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(91195), // Rule ID 5065 //
     /*  91133 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91137 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  91141 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  91145 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  91149 */     // MIs[1] Operand 1
     /*  91149 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  91154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  91158 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91164 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  91166 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  91170 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91176 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91178 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91180 */     // (xor:{ *:[v4i16] } (setcc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i16] })  =>  (CMTSTv4i16:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$Rn, v4i16:{ *:[v4i16] }:$Rn)
     /*  91180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i16),
     /*  91183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  91189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  91193 */     GIR_RootConstrainSelectedInstOperands,
     /*  91194 */     // GIR_Coverage, 5065,
     /*  91194 */     GIR_EraseRootFromParent_Done,
     /*  91195 */   // Label 1421: @91195
     /*  91195 */   GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(91227), // Rule ID 5016 //
     /*  91200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91208 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91214 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  91216 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  91218 */     // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] })  =>  (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /*  91218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  91221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91223 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  91225 */     GIR_RootConstrainSelectedInstOperands,
     /*  91226 */     // GIR_Coverage, 5016,
     /*  91226 */     GIR_EraseRootFromParent_Done,
     /*  91227 */   // Label 1422: @91227
     /*  91227 */   GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(91250), // Rule ID 5096 //
     /*  91232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91235 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91239 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91243 */     // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  91243 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  91248 */     GIR_RootConstrainSelectedInstOperands,
     /*  91249 */     // GIR_Coverage, 5096,
     /*  91249 */     GIR_Done,
     /*  91250 */   // Label 1423: @91250
     /*  91250 */   GIM_Reject,
     /*  91251 */ // Label 1419: @91251
     /*  91251 */ GIM_Reject,
     /*  91252 */ // Label 1350: @91252
     /*  91252 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(91940),
     /*  91257 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91260 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91267 */   GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(91363), // Rule ID 1165 //
     /*  91272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91275 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91279 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  91283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91287 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  91291 */     // MIs[1] Operand 1
     /*  91291 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  91296 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91300 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91304 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91308 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91312 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91317 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91322 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  91326 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91332 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  91334 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91338 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91344 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91346 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91348 */     // (xor:{ *:[v4i32] } (setcc:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i32] })  =>  (CMTSTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  91348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i32),
     /*  91351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  91357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  91361 */     GIR_RootConstrainSelectedInstOperands,
     /*  91362 */     // GIR_Coverage, 1165,
     /*  91362 */     GIR_EraseRootFromParent_Done,
     /*  91363 */   // Label 1425: @91363
     /*  91363 */   GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(91430), // Rule ID 5068 //
     /*  91368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  91376 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91380 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  91384 */     // MIs[1] Operand 1
     /*  91384 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  91389 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  91393 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91399 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  91401 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  91405 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91411 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91413 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91415 */     // (xor:{ *:[v4i32] } (setcc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i32] })  =>  (CMTSTv4i32:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, v4i32:{ *:[v4i32] }:$Rn)
     /*  91415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i32),
     /*  91418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91420 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  91424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  91428 */     GIR_RootConstrainSelectedInstOperands,
     /*  91429 */     // GIR_Coverage, 5068,
     /*  91429 */     GIR_EraseRootFromParent_Done,
     /*  91430 */   // Label 1426: @91430
     /*  91430 */   GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(91515), // Rule ID 14080 //
     /*  91435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91438 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91442 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91446 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91450 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91454 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91458 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91462 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91466 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91470 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91475 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91479 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91485 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91487 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91496 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91498 */     // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Vn)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  91501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  91505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  91509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  91513 */     GIR_RootConstrainSelectedInstOperands,
     /*  91514 */     // GIR_Coverage, 14080,
     /*  91514 */     GIR_EraseRootFromParent_Done,
     /*  91515 */   // Label 1427: @91515
     /*  91515 */   GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(91600), // Rule ID 14079 //
     /*  91520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91531 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91535 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91539 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91544 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91548 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91552 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91556 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91560 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91565 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91569 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91575 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91581 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91583 */     // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })), V128:{ *:[v4i32] }:$Vn)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  91586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  91590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  91594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  91598 */     GIR_RootConstrainSelectedInstOperands,
     /*  91599 */     // GIR_Coverage, 14079,
     /*  91599 */     GIR_EraseRootFromParent_Done,
     /*  91600 */   // Label 1428: @91600
     /*  91600 */   GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(91685), // Rule ID 14078 //
     /*  91605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91608 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91612 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91616 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91620 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91624 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91628 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91632 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91636 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91640 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91644 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91649 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91653 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91659 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91666 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91668 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm))  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  91671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91673 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  91675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  91679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  91683 */     GIR_RootConstrainSelectedInstOperands,
     /*  91684 */     // GIR_Coverage, 14078,
     /*  91684 */     GIR_EraseRootFromParent_Done,
     /*  91685 */   // Label 1429: @91685
     /*  91685 */   GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(91770), // Rule ID 3862 //
     /*  91690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91713 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91718 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91722 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91726 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91730 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91734 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91739 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91743 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91749 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91751 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  91753 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })))  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  91756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91758 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  91760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  91764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  91768 */     GIR_RootConstrainSelectedInstOperands,
     /*  91769 */     // GIR_Coverage, 3862,
     /*  91769 */     GIR_EraseRootFromParent_Done,
     /*  91770 */   // Label 1430: @91770
     /*  91770 */   GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(91802), // Rule ID 5019 //
     /*  91775 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91783 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91789 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  91791 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  91793 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] })  =>  (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /*  91793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  91796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  91798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  91800 */     GIR_RootConstrainSelectedInstOperands,
     /*  91801 */     // GIR_Coverage, 5019,
     /*  91801 */     GIR_EraseRootFromParent_Done,
     /*  91802 */   // Label 1431: @91802
     /*  91802 */   GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(91859), // Rule ID 3858 //
     /*  91807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91831 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91836 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91840 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  91842 */     // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Va)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  91845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91847 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  91851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  91855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  91857 */     GIR_RootConstrainSelectedInstOperands,
     /*  91858 */     // GIR_Coverage, 3858,
     /*  91858 */     GIR_EraseRootFromParent_Done,
     /*  91859 */   // Label 1432: @91859
     /*  91859 */   GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(91916), // Rule ID 14070 //
     /*  91864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  91867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  91883 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  91887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91892 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91897 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  91899 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm))  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  91899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  91902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  91904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  91908 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  91912 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  91914 */     GIR_RootConstrainSelectedInstOperands,
     /*  91915 */     // GIR_Coverage, 14070,
     /*  91915 */     GIR_EraseRootFromParent_Done,
     /*  91916 */   // Label 1433: @91916
     /*  91916 */   GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(91939), // Rule ID 5100 //
     /*  91921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91924 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  91932 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  91932 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  91937 */     GIR_RootConstrainSelectedInstOperands,
     /*  91938 */     // GIR_Coverage, 5100,
     /*  91938 */     GIR_Done,
     /*  91939 */   // Label 1434: @91939
     /*  91939 */   GIM_Reject,
     /*  91940 */ // Label 1424: @91940
     /*  91940 */ GIM_Reject,
     /*  91941 */ // Label 1351: @91941
     /*  91941 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(92178),
     /*  91946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  91949 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  91952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  91956 */   GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(92052), // Rule ID 1160 //
     /*  91961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  91964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  91972 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  91976 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  91980 */     // MIs[1] Operand 1
     /*  91980 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  91985 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91989 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91993 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  91997 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  92001 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  92006 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  92011 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  92015 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92021 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  92023 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  92027 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92033 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  92035 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  92037 */     // (xor:{ *:[v8i8] } (setcc:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i8] })  =>  (CMTSTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  92037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i8),
     /*  92040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92042 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  92046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  92050 */     GIR_RootConstrainSelectedInstOperands,
     /*  92051 */     // GIR_Coverage, 1160,
     /*  92051 */     GIR_EraseRootFromParent_Done,
     /*  92052 */   // Label 1436: @92052
     /*  92052 */   GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(92119), // Rule ID 5063 //
     /*  92057 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92061 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  92065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  92069 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  92073 */     // MIs[1] Operand 1
     /*  92073 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  92078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  92082 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92088 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  92090 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  92094 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92100 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92102 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92104 */     // (xor:{ *:[v8i8] } (setcc:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i8] })  =>  (CMTSTv8i8:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rn)
     /*  92104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i8),
     /*  92107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92117 */     GIR_RootConstrainSelectedInstOperands,
     /*  92118 */     // GIR_Coverage, 5063,
     /*  92118 */     GIR_EraseRootFromParent_Done,
     /*  92119 */   // Label 1437: @92119
     /*  92119 */   GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(92154), // Rule ID 976 //
     /*  92124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  92127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  92131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92135 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92141 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  92143 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92145 */     // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] })  =>  (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /*  92145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  92148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92150 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  92152 */     GIR_RootConstrainSelectedInstOperands,
     /*  92153 */     // GIR_Coverage, 976,
     /*  92153 */     GIR_EraseRootFromParent_Done,
     /*  92154 */   // Label 1438: @92154
     /*  92154 */   GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(92177), // Rule ID 1603 //
     /*  92159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  92162 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  92166 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  92170 */     // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  92170 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  92175 */     GIR_RootConstrainSelectedInstOperands,
     /*  92176 */     // GIR_Coverage, 1603,
     /*  92176 */     GIR_Done,
     /*  92177 */   // Label 1439: @92177
     /*  92177 */   GIM_Reject,
     /*  92178 */ // Label 1435: @92178
     /*  92178 */ GIM_Reject,
     /*  92179 */ // Label 1352: @92179
     /*  92179 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(92867),
     /*  92184 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92187 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92194 */   GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(92290), // Rule ID 1163 //
     /*  92199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  92202 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92206 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  92210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92214 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  92218 */     // MIs[1] Operand 1
     /*  92218 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  92223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  92227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92231 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92235 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92239 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92244 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92249 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  92253 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92259 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  92261 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  92265 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92271 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  92273 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  92275 */     // (xor:{ *:[v8i16] } (setcc:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i16] })  =>  (CMTSTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  92275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i16),
     /*  92278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  92284 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  92288 */     GIR_RootConstrainSelectedInstOperands,
     /*  92289 */     // GIR_Coverage, 1163,
     /*  92289 */     GIR_EraseRootFromParent_Done,
     /*  92290 */   // Label 1441: @92290
     /*  92290 */   GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(92357), // Rule ID 5066 //
     /*  92295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  92303 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92307 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  92311 */     // MIs[1] Operand 1
     /*  92311 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  92316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  92320 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92326 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  92328 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  92332 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92338 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92340 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92342 */     // (xor:{ *:[v8i16] } (setcc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i16] })  =>  (CMTSTv8i16:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, v8i16:{ *:[v8i16] }:$Rn)
     /*  92342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i16),
     /*  92345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92355 */     GIR_RootConstrainSelectedInstOperands,
     /*  92356 */     // GIR_Coverage, 5066,
     /*  92356 */     GIR_EraseRootFromParent_Done,
     /*  92357 */   // Label 1442: @92357
     /*  92357 */   GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(92442), // Rule ID 14077 //
     /*  92362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  92385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92389 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92393 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92397 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92402 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  92406 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92412 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92423 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92425 */     // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Vn)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  92428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92430 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  92432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  92436 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  92440 */     GIR_RootConstrainSelectedInstOperands,
     /*  92441 */     // GIR_Coverage, 14077,
     /*  92441 */     GIR_EraseRootFromParent_Done,
     /*  92442 */   // Label 1443: @92442
     /*  92442 */   GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(92527), // Rule ID 14076 //
     /*  92447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92462 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92471 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  92475 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92479 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92483 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92487 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92492 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  92496 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92502 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92508 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92510 */     // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })), V128:{ *:[v8i16] }:$Vn)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  92513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  92517 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  92521 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  92525 */     GIR_RootConstrainSelectedInstOperands,
     /*  92526 */     // GIR_Coverage, 14076,
     /*  92526 */     GIR_EraseRootFromParent_Done,
     /*  92527 */   // Label 1444: @92527
     /*  92527 */   GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(92612), // Rule ID 14075 //
     /*  92532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92535 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92551 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92555 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  92559 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92563 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92567 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92571 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92576 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  92580 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92586 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92588 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92593 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92595 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm))  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  92598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92600 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  92602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  92606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  92610 */     GIR_RootConstrainSelectedInstOperands,
     /*  92611 */     // GIR_Coverage, 14075,
     /*  92611 */     GIR_EraseRootFromParent_Done,
     /*  92612 */   // Label 1445: @92612
     /*  92612 */   GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(92697), // Rule ID 3861 //
     /*  92617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92620 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92636 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92640 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92645 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  92649 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92653 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92657 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92661 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92666 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  92670 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92676 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  92678 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  92680 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })))  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  92683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92685 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  92687 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  92691 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  92695 */     GIR_RootConstrainSelectedInstOperands,
     /*  92696 */     // GIR_Coverage, 3861,
     /*  92696 */     GIR_EraseRootFromParent_Done,
     /*  92697 */   // Label 1446: @92697
     /*  92697 */   GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(92729), // Rule ID 5017 //
     /*  92702 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92706 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92710 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92716 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  92718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92720 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] })  =>  (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /*  92720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  92723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92725 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  92727 */     GIR_RootConstrainSelectedInstOperands,
     /*  92728 */     // GIR_Coverage, 5017,
     /*  92728 */     GIR_EraseRootFromParent_Done,
     /*  92729 */   // Label 1447: @92729
     /*  92729 */   GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(92786), // Rule ID 3857 //
     /*  92734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92749 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92758 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92767 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92769 */     // (xor:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Va)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  92772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  92778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  92782 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  92784 */     GIR_RootConstrainSelectedInstOperands,
     /*  92785 */     // GIR_Coverage, 3857,
     /*  92785 */     GIR_EraseRootFromParent_Done,
     /*  92786 */   // Label 1448: @92786
     /*  92786 */   GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(92843), // Rule ID 14069 //
     /*  92791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  92794 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92802 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92806 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  92810 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  92814 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92819 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92824 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92826 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm))  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  92826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  92829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  92831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  92835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  92839 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  92841 */     GIR_RootConstrainSelectedInstOperands,
     /*  92842 */     // GIR_Coverage, 14069,
     /*  92842 */     GIR_EraseRootFromParent_Done,
     /*  92843 */   // Label 1449: @92843
     /*  92843 */   GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(92866), // Rule ID 5099 //
     /*  92848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  92851 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92855 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92859 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  92859 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  92864 */     GIR_RootConstrainSelectedInstOperands,
     /*  92865 */     // GIR_Coverage, 5099,
     /*  92865 */     GIR_Done,
     /*  92866 */   // Label 1450: @92866
     /*  92866 */   GIM_Reject,
     /*  92867 */ // Label 1440: @92867
     /*  92867 */ GIM_Reject,
     /*  92868 */ // Label 1353: @92868
     /*  92868 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(93559),
     /*  92873 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  92876 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  92879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92883 */   GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(92979), // Rule ID 1161 //
     /*  92888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  92891 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92895 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  92899 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  92903 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  92907 */     // MIs[1] Operand 1
     /*  92907 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  92912 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  92916 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  92920 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  92924 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  92928 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92933 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  92938 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  92942 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92948 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  92950 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  92954 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  92960 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  92962 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  92964 */     // (xor:{ *:[v16i8] } (setcc:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v16i8] })  =>  (CMTSTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  92964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv16i8),
     /*  92967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  92973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  92977 */     GIR_RootConstrainSelectedInstOperands,
     /*  92978 */     // GIR_Coverage, 1161,
     /*  92978 */     GIR_EraseRootFromParent_Done,
     /*  92979 */   // Label 1452: @92979
     /*  92979 */   GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(93046), // Rule ID 5064 //
     /*  92984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  92992 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  92996 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  93000 */     // MIs[1] Operand 1
     /*  93000 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  93005 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  93009 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93015 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  93017 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  93021 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93027 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  93029 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  93031 */     // (xor:{ *:[v16i8] } (setcc:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v16i8] })  =>  (CMTSTv16i8:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rn)
     /*  93031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv16i8),
     /*  93034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  93040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  93044 */     GIR_RootConstrainSelectedInstOperands,
     /*  93045 */     // GIR_Coverage, 5064,
     /*  93045 */     GIR_EraseRootFromParent_Done,
     /*  93046 */   // Label 1453: @93046
     /*  93046 */   GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(93131), // Rule ID 14074 //
     /*  93051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93070 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  93074 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93078 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93082 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93086 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93091 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  93095 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93101 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  93103 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93112 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  93114 */     // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Vn)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  93117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  93121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  93125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  93129 */     GIR_RootConstrainSelectedInstOperands,
     /*  93130 */     // GIR_Coverage, 14074,
     /*  93130 */     GIR_EraseRootFromParent_Done,
     /*  93131 */   // Label 1454: @93131
     /*  93131 */   GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(93216), // Rule ID 14073 //
     /*  93136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93151 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93155 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93160 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  93164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93168 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93172 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93176 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93181 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  93185 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93191 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  93193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93197 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  93199 */     // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })), V128:{ *:[v16i8] }:$Vn)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  93202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  93206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  93210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  93214 */     GIR_RootConstrainSelectedInstOperands,
     /*  93215 */     // GIR_Coverage, 14073,
     /*  93215 */     GIR_EraseRootFromParent_Done,
     /*  93216 */   // Label 1455: @93216
     /*  93216 */   GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(93301), // Rule ID 14072 //
     /*  93221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93224 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93244 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  93248 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93252 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93256 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93260 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93265 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  93269 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93275 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  93277 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93282 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  93284 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm))  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  93287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93289 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  93291 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  93295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  93299 */     GIR_RootConstrainSelectedInstOperands,
     /*  93300 */     // GIR_Coverage, 14072,
     /*  93300 */     GIR_EraseRootFromParent_Done,
     /*  93301 */   // Label 1456: @93301
     /*  93301 */   GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(93386), // Rule ID 3860 //
     /*  93306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93309 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93329 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  93338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93342 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93346 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93350 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93355 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  93359 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93365 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  93367 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  93369 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })))  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  93372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93374 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  93376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  93380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  93384 */     GIR_RootConstrainSelectedInstOperands,
     /*  93385 */     // GIR_Coverage, 3860,
     /*  93385 */     GIR_EraseRootFromParent_Done,
     /*  93386 */   // Label 1457: @93386
     /*  93386 */   GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(93421), // Rule ID 977 //
     /*  93391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  93394 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93402 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93408 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  93410 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93412 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] })  =>  (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /*  93412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  93415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93417 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  93419 */     GIR_RootConstrainSelectedInstOperands,
     /*  93420 */     // GIR_Coverage, 977,
     /*  93420 */     GIR_EraseRootFromParent_Done,
     /*  93421 */   // Label 1458: @93421
     /*  93421 */   GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(93478), // Rule ID 3856 //
     /*  93426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93429 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93433 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93437 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93441 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93445 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93450 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93459 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93461 */     // (xor:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Va)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  93464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93466 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  93470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  93474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  93476 */     GIR_RootConstrainSelectedInstOperands,
     /*  93477 */     // GIR_Coverage, 3856,
     /*  93477 */     GIR_EraseRootFromParent_Done,
     /*  93478 */   // Label 1459: @93478
     /*  93478 */   GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(93535), // Rule ID 14068 //
     /*  93483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  93486 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  93502 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  93506 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93516 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93518 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm))  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  93518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  93521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  93523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  93527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  93531 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  93533 */     GIR_RootConstrainSelectedInstOperands,
     /*  93534 */     // GIR_Coverage, 14068,
     /*  93534 */     GIR_EraseRootFromParent_Done,
     /*  93535 */   // Label 1460: @93535
     /*  93535 */   GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(93558), // Rule ID 1604 //
     /*  93540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  93543 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93547 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  93551 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  93551 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  93556 */     GIR_RootConstrainSelectedInstOperands,
     /*  93557 */     // GIR_Coverage, 1604,
     /*  93557 */     GIR_Done,
     /*  93558 */   // Label 1461: @93558
     /*  93558 */   GIM_Reject,
     /*  93559 */ // Label 1451: @93559
     /*  93559 */ GIM_Reject,
     /*  93560 */ // Label 1354: @93560
     /*  93560 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(93609), // Rule ID 8567 //
     /*  93565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  93568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  93571 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  93574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  93578 */   // (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  93578 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  93581 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  93585 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  93590 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  93593 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  93595 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  93598 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  93600 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  93603 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  93605 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  93607 */   GIR_RootConstrainSelectedInstOperands,
     /*  93608 */   // GIR_Coverage, 8567,
     /*  93608 */   GIR_EraseRootFromParent_Done,
     /*  93609 */ // Label 1462: @93609
     /*  93609 */ GIM_Reject,
     /*  93610 */ // Label 1355: @93610
     /*  93610 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(93659), // Rule ID 8566 //
     /*  93615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  93618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  93621 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  93624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  93628 */   // (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  93628 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  93631 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  93635 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  93640 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  93643 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  93645 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  93648 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  93650 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  93653 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  93655 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  93657 */   GIR_RootConstrainSelectedInstOperands,
     /*  93658 */   // GIR_Coverage, 8566,
     /*  93658 */   GIR_EraseRootFromParent_Done,
     /*  93659 */ // Label 1463: @93659
     /*  93659 */ GIM_Reject,
     /*  93660 */ // Label 1356: @93660
     /*  93660 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(95347),
     /*  93665 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93668 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  93675 */   GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(93793), // Rule ID 16332 //
     /*  93680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  93683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93691 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93695 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  93703 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93707 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93711 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  93719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93723 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93727 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93731 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  93735 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93741 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  93743 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  93747 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93751 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93755 */     // MIs[5] Op3
     /*  93755 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  93760 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  93764 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93770 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  93772 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  93774 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  93774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  93777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  93779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  93783 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  93787 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  93791 */     GIR_RootConstrainSelectedInstOperands,
     /*  93792 */     // GIR_Coverage, 16332,
     /*  93792 */     GIR_EraseRootFromParent_Done,
     /*  93793 */   // Label 1465: @93793
     /*  93793 */   GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(93911), // Rule ID 16331 //
     /*  93798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  93801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93809 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93813 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93817 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  93821 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93825 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93829 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93833 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  93837 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93841 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93845 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93849 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  93853 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93859 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  93861 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  93865 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93869 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93873 */     // MIs[5] Op3
     /*  93873 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  93878 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  93882 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93888 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  93890 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  93892 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  93892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  93895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  93897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  93901 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  93905 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  93909 */     GIR_RootConstrainSelectedInstOperands,
     /*  93910 */     // GIR_Coverage, 16331,
     /*  93910 */     GIR_EraseRootFromParent_Done,
     /*  93911 */   // Label 1466: @93911
     /*  93911 */   GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(94029), // Rule ID 16330 //
     /*  93916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  93919 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93923 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93927 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93931 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93935 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  93939 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93943 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93947 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93951 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  93955 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93959 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  93963 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93967 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  93971 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93977 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  93979 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  93983 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93987 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  93991 */     // MIs[5] Op3
     /*  93991 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  93996 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94000 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94006 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94008 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94010 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  94019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  94023 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  94027 */     GIR_RootConstrainSelectedInstOperands,
     /*  94028 */     // GIR_Coverage, 16330,
     /*  94028 */     GIR_EraseRootFromParent_Done,
     /*  94029 */   // Label 1467: @94029
     /*  94029 */   GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(94147), // Rule ID 16329 //
     /*  94034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94037 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94041 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  94045 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94049 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94053 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94057 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94061 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94065 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94069 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  94073 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94077 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94081 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94085 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  94089 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94095 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  94097 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  94101 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94105 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94109 */     // MIs[5] Op3
     /*  94109 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  94114 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94118 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94124 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94126 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94128 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94133 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  94137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  94141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  94145 */     GIR_RootConstrainSelectedInstOperands,
     /*  94146 */     // GIR_Coverage, 16329,
     /*  94146 */     GIR_EraseRootFromParent_Done,
     /*  94147 */   // Label 1468: @94147
     /*  94147 */   GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(94265), // Rule ID 16326 //
     /*  94152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  94163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94167 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94171 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94175 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94179 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94183 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94187 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  94191 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94195 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94199 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94203 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  94207 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94211 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94215 */     // MIs[4] Op3
     /*  94215 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  94220 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  94224 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94230 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  94232 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94236 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94242 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94244 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94246 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94251 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  94255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  94259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  94263 */     GIR_RootConstrainSelectedInstOperands,
     /*  94264 */     // GIR_Coverage, 16326,
     /*  94264 */     GIR_EraseRootFromParent_Done,
     /*  94265 */   // Label 1469: @94265
     /*  94265 */   GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(94383), // Rule ID 16328 //
     /*  94270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  94281 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94285 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94297 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94301 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94305 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  94309 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94313 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94317 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94321 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  94325 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94329 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94333 */     // MIs[4] Op3
     /*  94333 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  94338 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  94342 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94348 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  94350 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94354 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94360 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94362 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94364 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  94373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  94377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94381 */     GIR_RootConstrainSelectedInstOperands,
     /*  94382 */     // GIR_Coverage, 16328,
     /*  94382 */     GIR_EraseRootFromParent_Done,
     /*  94383 */   // Label 1470: @94383
     /*  94383 */   GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(94501), // Rule ID 12131 //
     /*  94388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  94399 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94403 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94407 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94411 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94415 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94419 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94423 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  94427 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94431 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94435 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94439 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  94443 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94447 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94451 */     // MIs[4] Op3
     /*  94451 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  94456 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  94460 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94466 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  94468 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94472 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94478 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94480 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94482 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }))), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  94491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  94495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  94499 */     GIR_RootConstrainSelectedInstOperands,
     /*  94500 */     // GIR_Coverage, 12131,
     /*  94500 */     GIR_EraseRootFromParent_Done,
     /*  94501 */   // Label 1471: @94501
     /*  94501 */   GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(94619), // Rule ID 16327 //
     /*  94506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94513 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  94517 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94521 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94525 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94529 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94533 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94537 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94541 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  94545 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94549 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94553 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94557 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  94561 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94565 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94569 */     // MIs[4] Op3
     /*  94569 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  94574 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  94578 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94584 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  94586 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  94590 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94596 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  94598 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  94600 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }))), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  94609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  94613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94617 */     GIR_RootConstrainSelectedInstOperands,
     /*  94618 */     // GIR_Coverage, 16327,
     /*  94618 */     GIR_EraseRootFromParent_Done,
     /*  94619 */   // Label 1472: @94619
     /*  94619 */   GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(94690), // Rule ID 15944 //
     /*  94624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94627 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94631 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94635 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94639 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94643 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94647 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94651 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94655 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94659 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  94663 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94669 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  94671 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  94673 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  94676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  94680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  94684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94688 */     GIR_RootConstrainSelectedInstOperands,
     /*  94689 */     // GIR_Coverage, 15944,
     /*  94689 */     GIR_EraseRootFromParent_Done,
     /*  94690 */   // Label 1473: @94690
     /*  94690 */   GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(94761), // Rule ID 15943 //
     /*  94695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94698 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94702 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94706 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94710 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  94718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94722 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94726 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94730 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  94734 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94740 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  94742 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  94744 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  94747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  94751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  94755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94759 */     GIR_RootConstrainSelectedInstOperands,
     /*  94760 */     // GIR_Coverage, 15943,
     /*  94760 */     GIR_EraseRootFromParent_Done,
     /*  94761 */   // Label 1474: @94761
     /*  94761 */   GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(94832), // Rule ID 15942 //
     /*  94766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  94773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94781 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94785 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  94789 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94793 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94797 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94801 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  94805 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94811 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  94813 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  94815 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  94818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94820 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  94822 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  94826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94830 */     GIR_RootConstrainSelectedInstOperands,
     /*  94831 */     // GIR_Coverage, 15942,
     /*  94831 */     GIR_EraseRootFromParent_Done,
     /*  94832 */   // Label 1475: @94832
     /*  94832 */   GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(94903), // Rule ID 12023 //
     /*  94837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94840 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  94844 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94848 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94852 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94856 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  94860 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94864 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94868 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94872 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  94876 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94882 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  94884 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  94886 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  94889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94891 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  94893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  94897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  94901 */     GIR_RootConstrainSelectedInstOperands,
     /*  94902 */     // GIR_Coverage, 12023,
     /*  94902 */     GIR_EraseRootFromParent_Done,
     /*  94903 */   // Label 1476: @94903
     /*  94903 */   GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(94964), // Rule ID 12130 //
     /*  94908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /*  94919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94923 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94927 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /*  94931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  94935 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94941 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  94943 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  94945 */     // (xor:{ *:[nxv2i64] } (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  94945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  94948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  94950 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  94954 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /*  94958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  94962 */     GIR_RootConstrainSelectedInstOperands,
     /*  94963 */     // GIR_Coverage, 12130,
     /*  94963 */     GIR_EraseRootFromParent_Done,
     /*  94964 */   // Label 1477: @94964
     /*  94964 */   GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(95021), // Rule ID 12187 //
     /*  94969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  94972 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94976 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94980 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  94984 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  94988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  94992 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94998 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  95000 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  95002 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1)
     /*  95002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  95011 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95019 */     GIR_RootConstrainSelectedInstOperands,
     /*  95020 */     // GIR_Coverage, 12187,
     /*  95020 */     GIR_EraseRootFromParent_Done,
     /*  95021 */   // Label 1478: @95021
     /*  95021 */   GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(95078), // Rule ID 12190 //
     /*  95026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  95049 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95055 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  95057 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  95059 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /*  95059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  95068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95072 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  95076 */     GIR_RootConstrainSelectedInstOperands,
     /*  95077 */     // GIR_Coverage, 12190,
     /*  95077 */     GIR_EraseRootFromParent_Done,
     /*  95078 */   // Label 1479: @95078
     /*  95078 */   GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(95133), // Rule ID 16416 //
     /*  95083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95090 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95094 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95098 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95102 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  95106 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95112 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  95114 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  95116 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /*  95116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  95119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95129 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /*  95131 */     GIR_RootConstrainSelectedInstOperands,
     /*  95132 */     // GIR_Coverage, 16416,
     /*  95132 */     GIR_EraseRootFromParent_Done,
     /*  95133 */   // Label 1480: @95133
     /*  95133 */   GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(95190), // Rule ID 12184 //
     /*  95138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95153 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95157 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  95161 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95167 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  95169 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  95171 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /*  95171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  95174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95180 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95184 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  95188 */     GIR_RootConstrainSelectedInstOperands,
     /*  95189 */     // GIR_Coverage, 12184,
     /*  95189 */     GIR_EraseRootFromParent_Done,
     /*  95190 */   // Label 1481: @95190
     /*  95190 */   GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(95245), // Rule ID 16417 //
     /*  95195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  95218 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95224 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  95226 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  95228 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /*  95228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  95231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95233 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  95241 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /*  95243 */     GIR_RootConstrainSelectedInstOperands,
     /*  95244 */     // GIR_Coverage, 16417,
     /*  95244 */     GIR_EraseRootFromParent_Done,
     /*  95245 */   // Label 1482: @95245
     /*  95245 */   GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(95288), // Rule ID 14033 //
     /*  95250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95269 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95271 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  95271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  95274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  95280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  95284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /*  95286 */     GIR_RootConstrainSelectedInstOperands,
     /*  95287 */     // GIR_Coverage, 14033,
     /*  95287 */     GIR_EraseRootFromParent_Done,
     /*  95288 */   // Label 1483: @95288
     /*  95288 */   GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(95331), // Rule ID 3169 //
     /*  95293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95304 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  95308 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  95312 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95314 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  95314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  95317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95319 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  95321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  95325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  95329 */     GIR_RootConstrainSelectedInstOperands,
     /*  95330 */     // GIR_Coverage, 3169,
     /*  95330 */     GIR_EraseRootFromParent_Done,
     /*  95331 */   // Label 1484: @95331
     /*  95331 */   GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(95346), // Rule ID 7561 //
     /*  95336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  95339 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  95339 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /*  95344 */     GIR_RootConstrainSelectedInstOperands,
     /*  95345 */     // GIR_Coverage, 7561,
     /*  95345 */     GIR_Done,
     /*  95346 */   // Label 1485: @95346
     /*  95346 */   GIM_Reject,
     /*  95347 */ // Label 1464: @95347
     /*  95347 */ GIM_Reject,
     /*  95348 */ // Label 1357: @95348
     /*  95348 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(95397), // Rule ID 8565 //
     /*  95353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  95356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  95359 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  95362 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  95366 */   // (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  95366 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  95369 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /*  95373 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95378 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  95381 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  95383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  95386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  95388 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  95391 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  95393 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  95395 */   GIR_RootConstrainSelectedInstOperands,
     /*  95396 */   // GIR_Coverage, 8565,
     /*  95396 */   GIR_EraseRootFromParent_Done,
     /*  95397 */ // Label 1486: @95397
     /*  95397 */ GIM_Reject,
     /*  95398 */ // Label 1358: @95398
     /*  95398 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(97085),
     /*  95403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95406 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  95413 */   GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(95531), // Rule ID 16325 //
     /*  95418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95437 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95441 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95445 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95449 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95453 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  95457 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95461 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95465 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95469 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  95473 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95479 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  95481 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  95485 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95489 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95493 */     // MIs[5] Op3
     /*  95493 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  95498 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  95502 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95508 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  95510 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  95512 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  95512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95517 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  95521 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  95525 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  95529 */     GIR_RootConstrainSelectedInstOperands,
     /*  95530 */     // GIR_Coverage, 16325,
     /*  95530 */     GIR_EraseRootFromParent_Done,
     /*  95531 */   // Label 1488: @95531
     /*  95531 */   GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(95649), // Rule ID 16324 //
     /*  95536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95551 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95555 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95559 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95563 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95567 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95571 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  95575 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95579 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95583 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95587 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  95591 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95597 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  95599 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  95603 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95607 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95611 */     // MIs[5] Op3
     /*  95611 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  95616 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  95620 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95626 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  95628 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  95630 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  95630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95635 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  95639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  95643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  95647 */     GIR_RootConstrainSelectedInstOperands,
     /*  95648 */     // GIR_Coverage, 16324,
     /*  95648 */     GIR_EraseRootFromParent_Done,
     /*  95649 */   // Label 1489: @95649
     /*  95649 */   GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(95767), // Rule ID 16323 //
     /*  95654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95673 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95677 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95681 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95685 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95689 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95693 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95697 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95701 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95705 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  95709 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95715 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  95717 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  95721 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95725 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95729 */     // MIs[5] Op3
     /*  95729 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  95734 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  95738 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95744 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  95746 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  95748 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  95748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  95757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  95761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  95765 */     GIR_RootConstrainSelectedInstOperands,
     /*  95766 */     // GIR_Coverage, 16323,
     /*  95766 */     GIR_EraseRootFromParent_Done,
     /*  95767 */   // Label 1490: @95767
     /*  95767 */   GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(95885), // Rule ID 16322 //
     /*  95772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95783 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95787 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95791 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95795 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95799 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95803 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95807 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95811 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95815 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95819 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95823 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  95827 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95833 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  95835 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  95839 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95843 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95847 */     // MIs[5] Op3
     /*  95847 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  95852 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  95856 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95862 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  95864 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  95866 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  95866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95871 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  95875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  95879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  95883 */     GIR_RootConstrainSelectedInstOperands,
     /*  95884 */     // GIR_Coverage, 16322,
     /*  95884 */     GIR_EraseRootFromParent_Done,
     /*  95885 */   // Label 1491: @95885
     /*  95885 */   GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(96003), // Rule ID 16319 //
     /*  95890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  95893 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95897 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  95901 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95905 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95909 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95913 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95917 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95921 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95925 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  95929 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95933 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  95937 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95941 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  95945 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95949 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  95953 */     // MIs[4] Op3
     /*  95953 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  95958 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  95962 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95968 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  95970 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  95974 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95980 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  95982 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  95984 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  95984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  95987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  95989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  95993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  95997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  96001 */     GIR_RootConstrainSelectedInstOperands,
     /*  96002 */     // GIR_Coverage, 16319,
     /*  96002 */     GIR_EraseRootFromParent_Done,
     /*  96003 */   // Label 1492: @96003
     /*  96003 */   GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(96121), // Rule ID 16321 //
     /*  96008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  96019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96023 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96035 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96039 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96043 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  96047 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96051 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96055 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96059 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  96063 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96067 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96071 */     // MIs[4] Op3
     /*  96071 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  96076 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  96080 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96086 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  96088 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  96092 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96098 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  96100 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  96102 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  96111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  96115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96119 */     GIR_RootConstrainSelectedInstOperands,
     /*  96120 */     // GIR_Coverage, 16321,
     /*  96120 */     GIR_EraseRootFromParent_Done,
     /*  96121 */   // Label 1493: @96121
     /*  96121 */   GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(96239), // Rule ID 12129 //
     /*  96126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  96137 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96141 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96145 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96149 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96153 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96157 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96161 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  96165 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96169 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96173 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96177 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  96181 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96185 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96189 */     // MIs[4] Op3
     /*  96189 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  96194 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  96198 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96204 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  96206 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  96210 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96216 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  96218 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  96220 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }))), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96225 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  96229 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  96233 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  96237 */     GIR_RootConstrainSelectedInstOperands,
     /*  96238 */     // GIR_Coverage, 12129,
     /*  96238 */     GIR_EraseRootFromParent_Done,
     /*  96239 */   // Label 1494: @96239
     /*  96239 */   GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(96357), // Rule ID 16320 //
     /*  96244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96247 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96251 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  96255 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96259 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96263 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96267 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96271 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96275 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96279 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  96283 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96287 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96291 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96295 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  96299 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96303 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96307 */     // MIs[4] Op3
     /*  96307 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  96312 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  96316 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96322 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  96324 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  96328 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96334 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  96336 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  96338 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }))), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  96347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  96351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96355 */     GIR_RootConstrainSelectedInstOperands,
     /*  96356 */     // GIR_Coverage, 16320,
     /*  96356 */     GIR_EraseRootFromParent_Done,
     /*  96357 */   // Label 1495: @96357
     /*  96357 */   GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(96428), // Rule ID 15941 //
     /*  96362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96389 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96393 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96397 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96401 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96407 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96409 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96411 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  96414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  96418 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  96422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96426 */     GIR_RootConstrainSelectedInstOperands,
     /*  96427 */     // GIR_Coverage, 15941,
     /*  96427 */     GIR_EraseRootFromParent_Done,
     /*  96428 */   // Label 1496: @96428
     /*  96428 */   GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(96499), // Rule ID 15940 //
     /*  96433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96448 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96452 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96456 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96460 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96464 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96468 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96472 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96478 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96480 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96482 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  96485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  96489 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  96493 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96497 */     GIR_RootConstrainSelectedInstOperands,
     /*  96498 */     // GIR_Coverage, 15940,
     /*  96498 */     GIR_EraseRootFromParent_Done,
     /*  96499 */   // Label 1497: @96499
     /*  96499 */   GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(96570), // Rule ID 15939 //
     /*  96504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96507 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  96511 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96515 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96519 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96523 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96527 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96531 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96535 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96539 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96543 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96549 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96551 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96553 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  96556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96558 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  96560 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  96564 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96568 */     GIR_RootConstrainSelectedInstOperands,
     /*  96569 */     // GIR_Coverage, 15939,
     /*  96569 */     GIR_EraseRootFromParent_Done,
     /*  96570 */   // Label 1498: @96570
     /*  96570 */   GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(96641), // Rule ID 12021 //
     /*  96575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  96582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96594 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96598 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96602 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96606 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96610 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96614 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96620 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96622 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96624 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  96627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96629 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  96631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  96635 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  96639 */     GIR_RootConstrainSelectedInstOperands,
     /*  96640 */     // GIR_Coverage, 12021,
     /*  96640 */     GIR_EraseRootFromParent_Done,
     /*  96641 */   // Label 1499: @96641
     /*  96641 */   GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(96702), // Rule ID 12128 //
     /*  96646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96649 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96653 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /*  96657 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96661 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96665 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /*  96669 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  96673 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96679 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96681 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96683 */     // (xor:{ *:[nxv4i32] } (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  96683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96688 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  96692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /*  96696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  96700 */     GIR_RootConstrainSelectedInstOperands,
     /*  96701 */     // GIR_Coverage, 12128,
     /*  96701 */     GIR_EraseRootFromParent_Done,
     /*  96702 */   // Label 1500: @96702
     /*  96702 */   GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(96759), // Rule ID 12175 //
     /*  96707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96714 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96718 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96722 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96726 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  96730 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96736 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96738 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96740 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1)
     /*  96740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96745 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  96749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96757 */     GIR_RootConstrainSelectedInstOperands,
     /*  96758 */     // GIR_Coverage, 12175,
     /*  96758 */     GIR_EraseRootFromParent_Done,
     /*  96759 */   // Label 1501: @96759
     /*  96759 */   GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(96816), // Rule ID 12178 //
     /*  96764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96767 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96771 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  96775 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96779 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96783 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  96787 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96793 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96795 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96797 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /*  96797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  96800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  96806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96810 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  96814 */     GIR_RootConstrainSelectedInstOperands,
     /*  96815 */     // GIR_Coverage, 12178,
     /*  96815 */     GIR_EraseRootFromParent_Done,
     /*  96816 */   // Label 1502: @96816
     /*  96816 */   GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(96871), // Rule ID 16407 //
     /*  96821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96836 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96844 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96850 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96852 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96854 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /*  96854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  96857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96859 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96867 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /*  96869 */     GIR_RootConstrainSelectedInstOperands,
     /*  96870 */     // GIR_Coverage, 16407,
     /*  96870 */     GIR_EraseRootFromParent_Done,
     /*  96871 */   // Label 1503: @96871
     /*  96871 */   GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(96928), // Rule ID 12172 //
     /*  96876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96887 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96891 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96895 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  96899 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96905 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96907 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96909 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /*  96909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  96912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  96926 */     GIR_RootConstrainSelectedInstOperands,
     /*  96927 */     // GIR_Coverage, 12172,
     /*  96927 */     GIR_EraseRootFromParent_Done,
     /*  96928 */   // Label 1504: @96928
     /*  96928 */   GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(96983), // Rule ID 16408 //
     /*  96933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96936 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  96940 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96944 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  96948 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  96952 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96956 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96962 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  96964 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  96966 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /*  96966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  96969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  96971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  96979 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /*  96981 */     GIR_RootConstrainSelectedInstOperands,
     /*  96982 */     // GIR_Coverage, 16408,
     /*  96982 */     GIR_EraseRootFromParent_Done,
     /*  96983 */   // Label 1505: @96983
     /*  96983 */   GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(97026), // Rule ID 14032 //
     /*  96988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  96991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  97003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  97007 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97009 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  97009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  97012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  97018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  97022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /*  97024 */     GIR_RootConstrainSelectedInstOperands,
     /*  97025 */     // GIR_Coverage, 14032,
     /*  97025 */     GIR_EraseRootFromParent_Done,
     /*  97026 */   // Label 1506: @97026
     /*  97026 */   GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(97069), // Rule ID 3167 //
     /*  97031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97034 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97038 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97042 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  97046 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  97050 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97052 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  97052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  97055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97057 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  97059 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  97063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  97067 */     GIR_RootConstrainSelectedInstOperands,
     /*  97068 */     // GIR_Coverage, 3167,
     /*  97068 */     GIR_EraseRootFromParent_Done,
     /*  97069 */   // Label 1507: @97069
     /*  97069 */   GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(97084), // Rule ID 7560 //
     /*  97074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  97077 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  97077 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /*  97082 */     GIR_RootConstrainSelectedInstOperands,
     /*  97083 */     // GIR_Coverage, 7560,
     /*  97083 */     GIR_Done,
     /*  97084 */   // Label 1508: @97084
     /*  97084 */   GIM_Reject,
     /*  97085 */ // Label 1487: @97085
     /*  97085 */ GIM_Reject,
     /*  97086 */ // Label 1359: @97086
     /*  97086 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(97135), // Rule ID 8564 //
     /*  97091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  97094 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  97097 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  97100 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  97104 */   // (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  97104 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  97107 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /*  97111 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97116 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  97119 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  97121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  97124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  97126 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  97129 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  97131 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  97133 */   GIR_RootConstrainSelectedInstOperands,
     /*  97134 */   // GIR_Coverage, 8564,
     /*  97134 */   GIR_EraseRootFromParent_Done,
     /*  97135 */ // Label 1509: @97135
     /*  97135 */ GIM_Reject,
     /*  97136 */ // Label 1360: @97136
     /*  97136 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(98823),
     /*  97141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97144 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  97151 */   GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(97269), // Rule ID 16318 //
     /*  97156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97159 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97163 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97167 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97171 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97175 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97179 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97183 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97187 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97191 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  97195 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97199 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97203 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97207 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  97211 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97217 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  97219 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  97223 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97227 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97231 */     // MIs[5] Op3
     /*  97231 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  97236 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97240 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97246 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97248 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97250 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  97259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  97263 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  97267 */     GIR_RootConstrainSelectedInstOperands,
     /*  97268 */     // GIR_Coverage, 16318,
     /*  97268 */     GIR_EraseRootFromParent_Done,
     /*  97269 */   // Label 1511: @97269
     /*  97269 */   GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(97387), // Rule ID 16317 //
     /*  97274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97285 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97289 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97293 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97297 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97301 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97305 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97309 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  97313 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97317 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97321 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97325 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  97329 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97335 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  97337 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  97341 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97345 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97349 */     // MIs[5] Op3
     /*  97349 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  97354 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97358 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97364 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97366 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97368 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  97377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  97381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  97385 */     GIR_RootConstrainSelectedInstOperands,
     /*  97386 */     // GIR_Coverage, 16317,
     /*  97386 */     GIR_EraseRootFromParent_Done,
     /*  97387 */   // Label 1512: @97387
     /*  97387 */   GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(97505), // Rule ID 16316 //
     /*  97392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97395 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97399 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97403 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97407 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97411 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97415 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97419 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97423 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97427 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  97431 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97435 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97439 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97443 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  97447 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97453 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  97455 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  97459 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97463 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97467 */     // MIs[5] Op3
     /*  97467 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  97472 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97476 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97482 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97484 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97486 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  97495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  97499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  97503 */     GIR_RootConstrainSelectedInstOperands,
     /*  97504 */     // GIR_Coverage, 16316,
     /*  97504 */     GIR_EraseRootFromParent_Done,
     /*  97505 */   // Label 1513: @97505
     /*  97505 */   GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(97623), // Rule ID 16315 //
     /*  97510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97521 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97525 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97537 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97541 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97545 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  97549 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97553 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97557 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97561 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  97565 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97571 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  97573 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  97577 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97581 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97585 */     // MIs[5] Op3
     /*  97585 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  97590 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97594 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97600 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97602 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97604 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  97613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  97617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  97621 */     GIR_RootConstrainSelectedInstOperands,
     /*  97622 */     // GIR_Coverage, 16315,
     /*  97622 */     GIR_EraseRootFromParent_Done,
     /*  97623 */   // Label 1514: @97623
     /*  97623 */   GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(97741), // Rule ID 16312 //
     /*  97628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97639 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97643 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97647 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97651 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97655 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97659 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97663 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  97667 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97671 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97675 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97679 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  97683 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97687 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97691 */     // MIs[4] Op3
     /*  97691 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  97696 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  97700 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97706 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  97708 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97712 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97718 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97720 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97722 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  97731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  97735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  97739 */     GIR_RootConstrainSelectedInstOperands,
     /*  97740 */     // GIR_Coverage, 16312,
     /*  97740 */     GIR_EraseRootFromParent_Done,
     /*  97741 */   // Label 1515: @97741
     /*  97741 */   GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(97859), // Rule ID 16314 //
     /*  97746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97761 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97773 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97777 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97781 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  97785 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97789 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97793 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97797 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  97801 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97805 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97809 */     // MIs[4] Op3
     /*  97809 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  97814 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  97818 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97824 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  97826 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97830 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97836 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97838 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97840 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  97849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  97853 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  97857 */     GIR_RootConstrainSelectedInstOperands,
     /*  97858 */     // GIR_Coverage, 16314,
     /*  97858 */     GIR_EraseRootFromParent_Done,
     /*  97859 */   // Label 1516: @97859
     /*  97859 */   GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(97977), // Rule ID 12127 //
     /*  97864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97875 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97879 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97883 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97887 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97891 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97895 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97899 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  97903 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97907 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97911 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97915 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  97919 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97923 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  97927 */     // MIs[4] Op3
     /*  97927 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  97932 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  97936 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97942 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  97944 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  97948 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97954 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  97956 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  97958 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }))), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  97958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  97961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  97963 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  97967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  97971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  97975 */     GIR_RootConstrainSelectedInstOperands,
     /*  97976 */     // GIR_Coverage, 12127,
     /*  97976 */     GIR_EraseRootFromParent_Done,
     /*  97977 */   // Label 1517: @97977
     /*  97977 */   GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(98095), // Rule ID 16313 //
     /*  97982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  97985 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97989 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  97993 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  97997 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98009 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98013 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98017 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  98021 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98025 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98029 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98033 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  98037 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98041 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98045 */     // MIs[4] Op3
     /*  98045 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  98050 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  98054 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98060 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  98062 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  98066 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98072 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  98074 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  98076 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }))), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  98079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98081 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  98085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  98089 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  98093 */     GIR_RootConstrainSelectedInstOperands,
     /*  98094 */     // GIR_Coverage, 16313,
     /*  98094 */     GIR_EraseRootFromParent_Done,
     /*  98095 */   // Label 1518: @98095
     /*  98095 */   GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(98166), // Rule ID 15938 //
     /*  98100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98103 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98107 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98111 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98115 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98119 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98123 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98127 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98131 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98135 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98139 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98145 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98147 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98149 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  98152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  98156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  98160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  98164 */     GIR_RootConstrainSelectedInstOperands,
     /*  98165 */     // GIR_Coverage, 15938,
     /*  98165 */     GIR_EraseRootFromParent_Done,
     /*  98166 */   // Label 1519: @98166
     /*  98166 */   GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(98237), // Rule ID 15937 //
     /*  98171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98186 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98190 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98194 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98198 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98202 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98206 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98210 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98216 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98218 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98220 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  98223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98225 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  98227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  98231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  98235 */     GIR_RootConstrainSelectedInstOperands,
     /*  98236 */     // GIR_Coverage, 15937,
     /*  98236 */     GIR_EraseRootFromParent_Done,
     /*  98237 */   // Label 1520: @98237
     /*  98237 */   GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(98308), // Rule ID 15936 //
     /*  98242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98245 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98249 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98253 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98257 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98261 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98265 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98269 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98273 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98277 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98281 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98287 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98289 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98291 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  98294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98296 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  98298 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  98302 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  98306 */     GIR_RootConstrainSelectedInstOperands,
     /*  98307 */     // GIR_Coverage, 15936,
     /*  98307 */     GIR_EraseRootFromParent_Done,
     /*  98308 */   // Label 1521: @98308
     /*  98308 */   GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(98379), // Rule ID 12019 //
     /*  98313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98316 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98320 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98324 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98328 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98332 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98336 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98340 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98344 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98348 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98352 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98358 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98360 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98362 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  98365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98367 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  98369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  98373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  98377 */     GIR_RootConstrainSelectedInstOperands,
     /*  98378 */     // GIR_Coverage, 12019,
     /*  98378 */     GIR_EraseRootFromParent_Done,
     /*  98379 */   // Label 1522: @98379
     /*  98379 */   GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(98440), // Rule ID 12126 //
     /*  98384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /*  98395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98399 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98403 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /*  98407 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  98411 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98417 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98419 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98421 */     // (xor:{ *:[nxv8i16] } (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  98424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98426 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  98430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /*  98434 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  98438 */     GIR_RootConstrainSelectedInstOperands,
     /*  98439 */     // GIR_Coverage, 12126,
     /*  98439 */     GIR_EraseRootFromParent_Done,
     /*  98440 */   // Label 1523: @98440
     /*  98440 */   GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(98497), // Rule ID 12163 //
     /*  98445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98456 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98460 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98464 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  98468 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98474 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98476 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98478 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1)
     /*  98478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  98481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  98487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98495 */     GIR_RootConstrainSelectedInstOperands,
     /*  98496 */     // GIR_Coverage, 12163,
     /*  98496 */     GIR_EraseRootFromParent_Done,
     /*  98497 */   // Label 1524: @98497
     /*  98497 */   GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(98554), // Rule ID 12166 //
     /*  98502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  98513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98517 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  98525 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98531 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98533 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98535 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /*  98535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  98538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98540 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  98544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  98552 */     GIR_RootConstrainSelectedInstOperands,
     /*  98553 */     // GIR_Coverage, 12166,
     /*  98553 */     GIR_EraseRootFromParent_Done,
     /*  98554 */   // Label 1525: @98554
     /*  98554 */   GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(98609), // Rule ID 16398 //
     /*  98559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98574 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98578 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98582 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98588 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98590 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98592 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /*  98592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  98595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98597 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98601 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98605 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /*  98607 */     GIR_RootConstrainSelectedInstOperands,
     /*  98608 */     // GIR_Coverage, 16398,
     /*  98608 */     GIR_EraseRootFromParent_Done,
     /*  98609 */   // Label 1526: @98609
     /*  98609 */   GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(98666), // Rule ID 12160 //
     /*  98614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98625 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98629 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98633 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  98637 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98643 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98645 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98647 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /*  98647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  98650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /*  98664 */     GIR_RootConstrainSelectedInstOperands,
     /*  98665 */     // GIR_Coverage, 12160,
     /*  98665 */     GIR_EraseRootFromParent_Done,
     /*  98666 */   // Label 1527: @98666
     /*  98666 */   GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(98721), // Rule ID 16399 //
     /*  98671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98674 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98678 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98682 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98686 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98694 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98700 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  98702 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  98704 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /*  98704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  98707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98713 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /*  98717 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /*  98719 */     GIR_RootConstrainSelectedInstOperands,
     /*  98720 */     // GIR_Coverage, 16399,
     /*  98720 */     GIR_EraseRootFromParent_Done,
     /*  98721 */   // Label 1528: @98721
     /*  98721 */   GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(98764), // Rule ID 14031 //
     /*  98726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98729 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98733 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98737 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98741 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98745 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  98747 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  98750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  98756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  98760 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /*  98762 */     GIR_RootConstrainSelectedInstOperands,
     /*  98763 */     // GIR_Coverage, 14031,
     /*  98763 */     GIR_EraseRootFromParent_Done,
     /*  98764 */   // Label 1529: @98764
     /*  98764 */   GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(98807), // Rule ID 3165 //
     /*  98769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98776 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98780 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  98784 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  98788 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  98790 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  98790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /*  98793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98795 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  98797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  98801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  98805 */     GIR_RootConstrainSelectedInstOperands,
     /*  98806 */     // GIR_Coverage, 3165,
     /*  98806 */     GIR_EraseRootFromParent_Done,
     /*  98807 */   // Label 1530: @98807
     /*  98807 */   GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(98822), // Rule ID 7559 //
     /*  98812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  98815 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  98815 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /*  98820 */     GIR_RootConstrainSelectedInstOperands,
     /*  98821 */     // GIR_Coverage, 7559,
     /*  98821 */     GIR_Done,
     /*  98822 */   // Label 1531: @98822
     /*  98822 */   GIM_Reject,
     /*  98823 */ // Label 1510: @98823
     /*  98823 */ GIM_Reject,
     /*  98824 */ // Label 1361: @98824
     /*  98824 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(98873), // Rule ID 8563 //
     /*  98829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  98832 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  98835 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  98838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  98842 */   // (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  98842 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  98845 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /*  98849 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  98854 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  98857 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  98859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  98862 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  98864 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  98867 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  98869 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  98871 */   GIR_RootConstrainSelectedInstOperands,
     /*  98872 */   // GIR_Coverage, 8563,
     /*  98872 */   GIR_EraseRootFromParent_Done,
     /*  98873 */ // Label 1532: @98873
     /*  98873 */ GIM_Reject,
     /*  98874 */ // Label 1362: @98874
     /*  98874 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(100561),
     /*  98879 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  98882 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  98885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  98889 */   GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(99007), // Rule ID 16311 //
     /*  98894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  98897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  98905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  98909 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  98913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  98925 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  98929 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  98933 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98937 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  98941 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  98945 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  98949 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98955 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  98957 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  98961 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98965 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  98969 */     // MIs[5] Op3
     /*  98969 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  98974 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  98978 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98984 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  98986 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  98988 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  98988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  98991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  98993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  98997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  99001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99005 */     GIR_RootConstrainSelectedInstOperands,
     /*  99006 */     // GIR_Coverage, 16311,
     /*  99006 */     GIR_EraseRootFromParent_Done,
     /*  99007 */   // Label 1534: @99007
     /*  99007 */   GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(99125), // Rule ID 16310 //
     /*  99012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99015 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99019 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99023 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99027 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99031 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99035 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99039 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99043 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99047 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  99051 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99055 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99059 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99063 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99067 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99073 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99075 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99079 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99083 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99087 */     // MIs[5] Op3
     /*  99087 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99092 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99096 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99102 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99104 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99106 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  99115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  99119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99123 */     GIR_RootConstrainSelectedInstOperands,
     /*  99124 */     // GIR_Coverage, 16310,
     /*  99124 */     GIR_EraseRootFromParent_Done,
     /*  99125 */   // Label 1535: @99125
     /*  99125 */   GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(99243), // Rule ID 16309 //
     /*  99130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99133 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99137 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99141 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99145 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99157 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99161 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99165 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99169 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99173 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99177 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99181 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99185 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99191 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99193 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99197 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99201 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99205 */     // MIs[5] Op3
     /*  99205 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99210 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99214 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99220 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99222 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99224 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99229 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  99233 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  99237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99241 */     GIR_RootConstrainSelectedInstOperands,
     /*  99242 */     // GIR_Coverage, 16309,
     /*  99242 */     GIR_EraseRootFromParent_Done,
     /*  99243 */   // Label 1536: @99243
     /*  99243 */   GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(99361), // Rule ID 16308 //
     /*  99248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99251 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99255 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99259 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99263 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99267 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99271 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99275 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99279 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99283 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99287 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99291 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99295 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99299 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99303 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99309 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99311 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99315 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99319 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99323 */     // MIs[5] Op3
     /*  99323 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99328 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99332 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99338 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99340 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99342 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  99351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  99355 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99359 */     GIR_RootConstrainSelectedInstOperands,
     /*  99360 */     // GIR_Coverage, 16308,
     /*  99360 */     GIR_EraseRootFromParent_Done,
     /*  99361 */   // Label 1537: @99361
     /*  99361 */   GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(99479), // Rule ID 16305 //
     /*  99366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99381 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99385 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99389 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99393 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99397 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99401 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  99405 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99409 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99413 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99417 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  99421 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99425 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99429 */     // MIs[4] Op3
     /*  99429 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  99434 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  99438 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99444 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  99446 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99450 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99456 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99458 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99460 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  99469 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  99473 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  99477 */     GIR_RootConstrainSelectedInstOperands,
     /*  99478 */     // GIR_Coverage, 16305,
     /*  99478 */     GIR_EraseRootFromParent_Done,
     /*  99479 */   // Label 1538: @99479
     /*  99479 */   GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(99597), // Rule ID 16307 //
     /*  99484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99503 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99507 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99511 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99515 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99519 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  99523 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99527 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99531 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99535 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  99539 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99543 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99547 */     // MIs[4] Op3
     /*  99547 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  99552 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  99556 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99562 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  99564 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99568 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99574 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99576 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99578 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  99587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  99591 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  99595 */     GIR_RootConstrainSelectedInstOperands,
     /*  99596 */     // GIR_Coverage, 16307,
     /*  99596 */     GIR_EraseRootFromParent_Done,
     /*  99597 */   // Label 1539: @99597
     /*  99597 */   GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(99715), // Rule ID 12125 //
     /*  99602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99617 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99621 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99625 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99629 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99633 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99637 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  99641 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99645 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99649 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99653 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99657 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99661 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99665 */     // MIs[4] Op3
     /*  99665 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  99670 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  99674 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99680 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  99682 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99686 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99692 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99694 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99696 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }))), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99701 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  99705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  99709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  99713 */     GIR_RootConstrainSelectedInstOperands,
     /*  99714 */     // GIR_Coverage, 12125,
     /*  99714 */     GIR_EraseRootFromParent_Done,
     /*  99715 */   // Label 1540: @99715
     /*  99715 */   GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(99833), // Rule ID 16306 //
     /*  99720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99731 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99735 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99747 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99751 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99755 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  99759 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99763 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99767 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99771 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99775 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99779 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99783 */     // MIs[4] Op3
     /*  99783 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  99788 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  99792 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99798 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  99800 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99804 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99810 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99812 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99814 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }))), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99819 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /*  99823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  99827 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  99831 */     GIR_RootConstrainSelectedInstOperands,
     /*  99832 */     // GIR_Coverage, 16306,
     /*  99832 */     GIR_EraseRootFromParent_Done,
     /*  99833 */   // Label 1541: @99833
     /*  99833 */   GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(99904), // Rule ID 15935 //
     /*  99838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99841 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99845 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99849 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99853 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99857 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99861 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99865 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99869 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99873 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99877 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99883 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99885 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99887 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  99890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  99894 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  99898 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  99902 */     GIR_RootConstrainSelectedInstOperands,
     /*  99903 */     // GIR_Coverage, 15935,
     /*  99903 */     GIR_EraseRootFromParent_Done,
     /*  99904 */   // Label 1542: @99904
     /*  99904 */   GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(99975), // Rule ID 15934 //
     /*  99909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99912 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99916 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99920 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99924 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99928 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  99932 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99936 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99940 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99944 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99948 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99954 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99956 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99958 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  99958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /*  99961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  99965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  99969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  99973 */     GIR_RootConstrainSelectedInstOperands,
     /*  99974 */     // GIR_Coverage, 15934,
     /*  99974 */     GIR_EraseRootFromParent_Done,
     /*  99975 */   // Label 1543: @99975
     /*  99975 */   GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(100046), // Rule ID 15933 //
     /*  99980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99983 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  99987 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99991 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  99995 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  99999 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100003 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100007 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100011 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100015 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100019 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100025 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100027 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100029 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 100029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100034 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 100036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 100040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100044 */     GIR_RootConstrainSelectedInstOperands,
     /* 100045 */     // GIR_Coverage, 15933,
     /* 100045 */     GIR_EraseRootFromParent_Done,
     /* 100046 */   // Label 1544: @100046
     /* 100046 */   GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(100117), // Rule ID 12017 //
     /* 100051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100070 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 100074 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100078 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100082 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100086 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100090 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100096 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100098 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100100 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 100100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100105 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 100107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 100111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100115 */     GIR_RootConstrainSelectedInstOperands,
     /* 100116 */     // GIR_Coverage, 12017,
     /* 100116 */     GIR_EraseRootFromParent_Done,
     /* 100117 */   // Label 1545: @100117
     /* 100117 */   GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(100178), // Rule ID 12124 //
     /* 100122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100129 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /* 100133 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100137 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100141 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 100145 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100149 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100155 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100157 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100159 */     // (xor:{ *:[nxv16i8] } (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 100159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /* 100168 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /* 100172 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 100176 */     GIR_RootConstrainSelectedInstOperands,
     /* 100177 */     // GIR_Coverage, 12124,
     /* 100177 */     GIR_EraseRootFromParent_Done,
     /* 100178 */   // Label 1546: @100178
     /* 100178 */   GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(100235), // Rule ID 12151 //
     /* 100183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100198 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100202 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100206 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100212 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100214 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100216 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1)
     /* 100216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100221 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100225 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100229 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100233 */     GIR_RootConstrainSelectedInstOperands,
     /* 100234 */     // GIR_Coverage, 12151,
     /* 100234 */     GIR_EraseRootFromParent_Done,
     /* 100235 */   // Label 1547: @100235
     /* 100235 */   GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(100292), // Rule ID 12154 //
     /* 100240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100243 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100247 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100251 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100255 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100259 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100263 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100269 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100271 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100273 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 100273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100290 */     GIR_RootConstrainSelectedInstOperands,
     /* 100291 */     // GIR_Coverage, 12154,
     /* 100291 */     GIR_EraseRootFromParent_Done,
     /* 100292 */   // Label 1548: @100292
     /* 100292 */   GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(100347), // Rule ID 16389 //
     /* 100297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100308 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100312 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 100320 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100326 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100328 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100330 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 100330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 100333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100343 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /* 100345 */     GIR_RootConstrainSelectedInstOperands,
     /* 100346 */     // GIR_Coverage, 16389,
     /* 100346 */     GIR_EraseRootFromParent_Done,
     /* 100347 */   // Label 1549: @100347
     /* 100347 */   GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(100404), // Rule ID 12148 //
     /* 100352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100363 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100367 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100371 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100375 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100381 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100383 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100385 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 100385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 100388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100402 */     GIR_RootConstrainSelectedInstOperands,
     /* 100403 */     // GIR_Coverage, 12148,
     /* 100403 */     GIR_EraseRootFromParent_Done,
     /* 100404 */   // Label 1550: @100404
     /* 100404 */   GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(100459), // Rule ID 16390 //
     /* 100409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100412 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100416 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100420 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100424 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 100432 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100438 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100440 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100442 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 100442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 100445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100455 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /* 100457 */     GIR_RootConstrainSelectedInstOperands,
     /* 100458 */     // GIR_Coverage, 16390,
     /* 100458 */     GIR_EraseRootFromParent_Done,
     /* 100459 */   // Label 1551: @100459
     /* 100459 */   GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(100502), // Rule ID 14030 //
     /* 100464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100475 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100479 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100483 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100485 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 100485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 100488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 100494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 100498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 100500 */     GIR_RootConstrainSelectedInstOperands,
     /* 100501 */     // GIR_Coverage, 14030,
     /* 100501 */     GIR_EraseRootFromParent_Done,
     /* 100502 */   // Label 1552: @100502
     /* 100502 */   GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(100545), // Rule ID 3163 //
     /* 100507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 100522 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 100526 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100528 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 100528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 100531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100533 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 100535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 100539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /* 100543 */     GIR_RootConstrainSelectedInstOperands,
     /* 100544 */     // GIR_Coverage, 3163,
     /* 100544 */     GIR_EraseRootFromParent_Done,
     /* 100545 */   // Label 1553: @100545
     /* 100545 */   GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(100560), // Rule ID 7558 //
     /* 100550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 100553 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 100553 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /* 100558 */     GIR_RootConstrainSelectedInstOperands,
     /* 100559 */     // GIR_Coverage, 7558,
     /* 100559 */     GIR_Done,
     /* 100560 */   // Label 1554: @100560
     /* 100560 */   GIM_Reject,
     /* 100561 */ // Label 1533: @100561
     /* 100561 */ GIM_Reject,
     /* 100562 */ // Label 1363: @100562
     /* 100562 */ GIM_Reject,
     /* 100563 */ // Label 8: @100563
     /* 100563 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(108086),
     /* 100568 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 100571 */   GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(23), /*)*//*default:*//*Label 1567*/ GIMT_Encode4(108085),
     /* 100582 */   /*GILLT_v2s64*//*Label 1556*/ GIMT_Encode4(100650), GIMT_Encode4(0),
     /* 100590 */   /*GILLT_v4s32*//*Label 1557*/ GIMT_Encode4(101171), GIMT_Encode4(0),
     /* 100598 */   /*GILLT_v8s16*//*Label 1558*/ GIMT_Encode4(103583),
     /* 100602 */   /*GILLT_v16s8*//*Label 1559*/ GIMT_Encode4(105992), GIMT_Encode4(0),
     /* 100610 */   /*GILLT_nxv2s1*//*Label 1560*/ GIMT_Encode4(107903), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 100626 */   /*GILLT_nxv4s1*//*Label 1561*/ GIMT_Encode4(107929),
     /* 100630 */   /*GILLT_nxv4s16*//*Label 1562*/ GIMT_Encode4(107955),
     /* 100634 */   /*GILLT_nxv4s32*//*Label 1563*/ GIMT_Encode4(107981),
     /* 100638 */   /*GILLT_nxv8s1*//*Label 1564*/ GIMT_Encode4(108007),
     /* 100642 */   /*GILLT_nxv8s16*//*Label 1565*/ GIMT_Encode4(108033),
     /* 100646 */   /*GILLT_nxv16s1*//*Label 1566*/ GIMT_Encode4(108059),
     /* 100650 */   // Label 1556: @100650
     /* 100650 */   GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(101170),
     /* 100655 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 100658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 100661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100665 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100669 */     GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(100731), // Rule ID 5856 //
     /* 100674 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100678 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100684 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 100686 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100688 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1i64] }:$Rn), dsub:{ *:[i32] })
     /* 100688 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 100691 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 100695 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100700 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 100704 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 100706 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 100709 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 100711 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 100714 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 100717 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 100720 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100725 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100730 */       // GIR_Coverage, 5856,
     /* 100730 */       GIR_EraseRootFromParent_Done,
     /* 100731 */     // Label 1569: @100731
     /* 100731 */     GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(100793), // Rule ID 5860 //
     /* 100736 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100740 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100746 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 100748 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100750 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1f64] }:$Rn), dsub:{ *:[i32] })
     /* 100750 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 100753 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 100757 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100762 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 100766 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 100768 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 100771 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 100773 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 100776 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 100779 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 100782 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100787 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100792 */       // GIR_Coverage, 5860,
     /* 100792 */       GIR_EraseRootFromParent_Done,
     /* 100793 */     // Label 1570: @100793
     /* 100793 */     GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(100851), // Rule ID 5857 //
     /* 100798 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100802 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 100806 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100808 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] }))  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] })
     /* 100808 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 100811 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 100815 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100820 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 100822 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 100825 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 100827 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 100830 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 100832 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 100835 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100840 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100845 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100850 */       // GIR_Coverage, 5857,
     /* 100850 */       GIR_EraseRootFromParent_Done,
     /* 100851 */     // Label 1571: @100851
     /* 100851 */     GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(100909), // Rule ID 5861 //
     /* 100856 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100860 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 100864 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 100866 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] }))  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] })
     /* 100866 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 100869 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 100873 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100878 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 100880 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 100883 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 100885 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 100888 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 100890 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 100893 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100898 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100903 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100908 */       // GIR_Coverage, 5861,
     /* 100908 */       GIR_EraseRootFromParent_Done,
     /* 100909 */     // Label 1572: @100909
     /* 100909 */     GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(101039), // Rule ID 5855 //
     /* 100914 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100918 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn)  =>  (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 100918 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 100921 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 100925 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100930 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 100932 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 100935 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 100939 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100944 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 100947 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 100951 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 100954 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100959 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 100964 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 100969 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 100972 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 100976 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100981 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 100983 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 100986 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 100990 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 100995 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 100998 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101002 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101005 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101010 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101015 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101020 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 101023 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101025 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101028 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 101031 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 101034 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 101037 */       GIR_RootConstrainSelectedInstOperands,
     /* 101038 */       // GIR_Coverage, 5855,
     /* 101038 */       GIR_EraseRootFromParent_Done,
     /* 101039 */     // Label 1573: @101039
     /* 101039 */     GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(101169), // Rule ID 5859 //
     /* 101044 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101048 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn)  =>  (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 101048 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 101051 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 101055 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101060 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 101062 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 101065 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 101069 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101074 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 101077 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 101081 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 101084 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101089 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101094 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101099 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 101102 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 101106 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101111 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 101113 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101116 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 101120 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101125 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 101128 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101132 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101135 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101140 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101145 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101150 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 101153 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101155 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101158 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 101161 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 101164 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 101167 */       GIR_RootConstrainSelectedInstOperands,
     /* 101168 */       // GIR_Coverage, 5859,
     /* 101168 */       GIR_EraseRootFromParent_Done,
     /* 101169 */     // Label 1574: @101169
     /* 101169 */     GIM_Reject,
     /* 101170 */   // Label 1568: @101170
     /* 101170 */   GIM_Reject,
     /* 101171 */   // Label 1557: @101171
     /* 101171 */   GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(103582),
     /* 101176 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 101179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 101182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101186 */     GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(101315), // Rule ID 5479 //
     /* 101191 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101195 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101199 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 101203 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101207 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101211 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 101215 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101219 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 101223 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101227 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101231 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 101235 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101240 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 101244 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101250 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 101252 */       // MIs[2] Operand 2
     /* 101252 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 101263 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 101265 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 101265 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101268 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 101272 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101277 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 101280 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101284 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101287 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101292 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101297 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 101300 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101302 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101305 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 101309 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 101313 */       GIR_RootConstrainSelectedInstOperands,
     /* 101314 */       // GIR_Coverage, 5479,
     /* 101314 */       GIR_EraseRootFromParent_Done,
     /* 101315 */     // Label 1576: @101315
     /* 101315 */     GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(101437), // Rule ID 5475 //
     /* 101320 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101324 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101328 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 101332 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101336 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101340 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 101344 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101348 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 101352 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 101356 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101360 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 101364 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101369 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101374 */       // MIs[2] Operand 2
     /* 101374 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 101385 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 101387 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (ADDHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 101387 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101390 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 101394 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101399 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 101402 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101406 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101409 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101414 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101419 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
     /* 101422 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101424 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101427 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 101431 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 101435 */       GIR_RootConstrainSelectedInstOperands,
     /* 101436 */       // GIR_Coverage, 5475,
     /* 101436 */       GIR_EraseRootFromParent_Done,
     /* 101437 */     // Label 1577: @101437
     /* 101437 */     GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(101559), // Rule ID 5477 //
     /* 101442 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101446 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101450 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 101454 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101458 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101462 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 101466 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101470 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 101474 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 101478 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101482 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 101486 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101491 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101496 */       // MIs[2] Operand 2
     /* 101496 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 101507 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 101509 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 101509 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101512 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 101516 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101521 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 101524 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101528 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101531 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101536 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101541 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 101544 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101546 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101549 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 101553 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 101557 */       GIR_RootConstrainSelectedInstOperands,
     /* 101558 */       // GIR_Coverage, 5477,
     /* 101558 */       GIR_EraseRootFromParent_Done,
     /* 101559 */     // Label 1578: @101559
     /* 101559 */     GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(101661), // Rule ID 5625 //
     /* 101564 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101568 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 101572 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101576 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101580 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 101584 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101588 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101593 */       // MIs[2] Operand 2
     /* 101593 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 101604 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 101608 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 101612 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101616 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 101620 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 101624 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 101628 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101633 */       // MIs[4] Operand 2
     /* 101633 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(32),
     /* 101644 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 101646 */       // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })), (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, 32:{ *:[i32] })))  =>  (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 101646 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 101649 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 101651 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 101655 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 101659 */       GIR_RootConstrainSelectedInstOperands,
     /* 101660 */       // GIR_Coverage, 5625,
     /* 101660 */       GIR_EraseRootFromParent_Done,
     /* 101661 */     // Label 1579: @101661
     /* 101661 */     GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(101790), // Rule ID 6411 //
     /* 101666 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101670 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101674 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 101678 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 101681 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 101686 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 101690 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 101694 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101699 */       GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 32,
     /* 101703 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 101705 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vd, (intrinsic_wo_chain:{ *:[v2i32] } 667:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] }))  =>  (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
     /* 101705 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /* 101708 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 101712 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101717 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 101720 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 101722 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 101725 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 101729 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101734 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 101736 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101739 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 101743 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101748 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 101751 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 101755 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101758 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101763 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101768 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101773 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
     /* 101776 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101778 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101781 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 101785 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 101788 */       GIR_RootConstrainSelectedInstOperands,
     /* 101789 */       // GIR_Coverage, 6411,
     /* 101789 */       GIR_EraseRootFromParent_Done,
     /* 101790 */     // Label 1580: @101790
     /* 101790 */     GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(101832), // Rule ID 5866 //
     /* 101795 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 101802 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 101809 */       // (concat_vectors:{ *:[v4i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (INSvi64lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] })
     /* 101809 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 101812 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101814 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 101819 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 101822 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 101827 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 101830 */       GIR_RootConstrainSelectedInstOperands,
     /* 101831 */       // GIR_Coverage, 5866,
     /* 101831 */       GIR_EraseRootFromParent_Done,
     /* 101832 */     // Label 1581: @101832
     /* 101832 */     GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(101874), // Rule ID 5870 //
     /* 101837 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 101844 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 101851 */       // (concat_vectors:{ *:[v4f32] } (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn), (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm))  =>  (INSvi64lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })
     /* 101851 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 101854 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101856 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 101861 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 101864 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 101869 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 101872 */       GIR_RootConstrainSelectedInstOperands,
     /* 101873 */       // GIR_Coverage, 5870,
     /* 101873 */       GIR_EraseRootFromParent_Done,
     /* 101874 */     // Label 1582: @101874
     /* 101874 */     GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(101997), // Rule ID 2578 //
     /* 101879 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 101882 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101886 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101890 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 101894 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 101897 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 101902 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 101906 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 101910 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101915 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 101919 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 101923 */       GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 101927 */       // MIs[2] Operand 1
     /* 101927 */       // No operand predicates
     /* 101927 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 101929 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 667:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 101929 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 101932 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 101936 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101941 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 101943 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 101946 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 101950 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101955 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 101958 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 101962 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 101965 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101970 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 101975 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 101980 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i32_shift),
     /* 101983 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 101985 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101988 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 101992 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 101995 */       GIR_RootConstrainSelectedInstOperands,
     /* 101996 */       // GIR_Coverage, 2578,
     /* 101996 */       GIR_EraseRootFromParent_Done,
     /* 101997 */     // Label 1583: @101997
     /* 101997 */     GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(102120), // Rule ID 6381 //
     /* 102002 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102005 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102009 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102013 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 102017 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102021 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102025 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 102029 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102033 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102038 */       // MIs[2] imm
     /* 102038 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102042 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 102046 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 102050 */       // MIs[3] Operand 1
     /* 102050 */       // No operand predicates
     /* 102050 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102052 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 102052 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102055 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102059 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102064 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102066 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102069 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102073 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102078 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102081 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102085 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102088 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102093 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102098 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102103 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
     /* 102106 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102108 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102111 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 102115 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 102118 */       GIR_RootConstrainSelectedInstOperands,
     /* 102119 */       // GIR_Coverage, 6381,
     /* 102119 */       GIR_EraseRootFromParent_Done,
     /* 102120 */     // Label 1584: @102120
     /* 102120 */     GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(102240), // Rule ID 6417 //
     /* 102125 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102129 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102133 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 102137 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102141 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102145 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 102149 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102153 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102158 */       // MIs[2] imm
     /* 102158 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102162 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 102166 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 102170 */       // MIs[3] Operand 1
     /* 102170 */       // No operand predicates
     /* 102170 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102172 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 102172 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102175 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102179 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102184 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102186 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102189 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102193 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102198 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102201 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102205 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102208 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102213 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102218 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102223 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
     /* 102226 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102228 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102231 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 102235 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 102238 */       GIR_RootConstrainSelectedInstOperands,
     /* 102239 */       // GIR_Coverage, 6417,
     /* 102239 */       GIR_EraseRootFromParent_Done,
     /* 102240 */     // Label 1585: @102240
     /* 102240 */     GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(102357), // Rule ID 2501 //
     /* 102245 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102248 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102252 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102256 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 102260 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 102263 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 102268 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 102272 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 102276 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102281 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102286 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102288 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 579:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 102288 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102291 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102295 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102300 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102302 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102305 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102309 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102314 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102317 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102321 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102324 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102329 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102334 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102339 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
     /* 102342 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102344 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102347 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 102351 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 102355 */       GIR_RootConstrainSelectedInstOperands,
     /* 102356 */       // GIR_Coverage, 2501,
     /* 102356 */       GIR_EraseRootFromParent_Done,
     /* 102357 */     // Label 1586: @102357
     /* 102357 */     GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(102474), // Rule ID 5395 //
     /* 102362 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102365 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102369 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102373 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 102377 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 102380 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 102385 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 102389 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 102393 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102398 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102403 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102405 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 724:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 102405 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102408 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102412 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102417 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102419 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102422 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102426 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102431 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102434 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102438 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102441 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102446 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102451 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102456 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 102459 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102461 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102464 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 102468 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 102472 */       GIR_RootConstrainSelectedInstOperands,
     /* 102473 */       // GIR_Coverage, 5395,
     /* 102473 */       GIR_EraseRootFromParent_Done,
     /* 102474 */     // Label 1587: @102474
     /* 102474 */     GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(102591), // Rule ID 5398 //
     /* 102479 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102482 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102486 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102490 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 102494 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 102497 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 102502 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 102506 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 102510 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102515 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102520 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102522 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 666:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 102522 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102525 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102529 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102534 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102536 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102539 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102543 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102548 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102551 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102555 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102558 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102563 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102568 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102573 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
     /* 102576 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102578 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102581 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 102585 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 102589 */       GIR_RootConstrainSelectedInstOperands,
     /* 102590 */       // GIR_Coverage, 5398,
     /* 102590 */       GIR_EraseRootFromParent_Done,
     /* 102591 */     // Label 1588: @102591
     /* 102591 */     GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(102708), // Rule ID 5401 //
     /* 102596 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102599 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102603 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102607 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 102611 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 102614 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 102619 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 102623 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 102627 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102632 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102637 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102639 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 668:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 102639 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102642 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102646 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102651 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102653 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102656 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102660 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102665 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102668 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102672 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102675 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102680 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102685 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102690 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v4i32),
     /* 102693 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102695 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102698 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 102702 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 102706 */       GIR_RootConstrainSelectedInstOperands,
     /* 102707 */       // GIR_Coverage, 5401,
     /* 102707 */       GIR_EraseRootFromParent_Done,
     /* 102708 */     // Label 1589: @102708
     /* 102708 */     GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(102812), // Rule ID 2497 //
     /* 102713 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 102716 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102720 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102724 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 102728 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 102731 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
     /* 102736 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 102740 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102745 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102747 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 601:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn))  =>  (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
     /* 102747 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 102750 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 102754 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102759 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 102761 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 102764 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 102768 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102773 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 102776 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 102780 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 102783 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102788 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102793 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102798 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv4f32),
     /* 102801 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102803 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102806 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 102810 */       GIR_RootConstrainSelectedInstOperands,
     /* 102811 */       // GIR_Coverage, 2497,
     /* 102811 */       GIR_EraseRootFromParent_Done,
     /* 102812 */     // Label 1590: @102812
     /* 102812 */     GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(102868), // Rule ID 5558 //
     /* 102817 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102821 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 102825 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102829 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102834 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 102838 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 102842 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 102846 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102851 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102853 */       // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm))  =>  (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 102853 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 102856 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 102858 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 102862 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 102866 */       GIR_RootConstrainSelectedInstOperands,
     /* 102867 */       // GIR_Coverage, 5558,
     /* 102867 */       GIR_EraseRootFromParent_Done,
     /* 102868 */     // Label 1591: @102868
     /* 102868 */     GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(102934), // Rule ID 5864 //
     /* 102873 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102877 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102881 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102887 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 102889 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102891 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 102891 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 102894 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 102898 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102903 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 102907 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 102909 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 102912 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102914 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 102917 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102920 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 102923 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102928 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102933 */       // GIR_Coverage, 5864,
     /* 102933 */       GIR_EraseRootFromParent_Done,
     /* 102934 */     // Label 1592: @102934
     /* 102934 */     GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(103000), // Rule ID 5868 //
     /* 102939 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102943 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102947 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102953 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 102955 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102957 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2f32] }:$Rn), dsub:{ *:[i32] })
     /* 102957 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 102960 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 102964 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 102969 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 102973 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 102975 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 102978 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 102980 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 102983 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 102986 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 102989 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 102994 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 102999 */       // GIR_Coverage, 5868,
     /* 102999 */       GIR_EraseRootFromParent_Done,
     /* 103000 */     // Label 1593: @103000
     /* 103000 */     GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(103093), // Rule ID 4983 //
     /* 103005 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103009 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103013 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /* 103017 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 103021 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103026 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 103028 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn))  =>  (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
     /* 103028 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 103031 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103035 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103040 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 103042 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103045 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103049 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103054 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 103057 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103061 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103064 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103069 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103074 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103079 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i32),
     /* 103082 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103084 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103087 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 103091 */       GIR_RootConstrainSelectedInstOperands,
     /* 103092 */       // GIR_Coverage, 4983,
     /* 103092 */       GIR_EraseRootFromParent_Done,
     /* 103093 */     // Label 1594: @103093
     /* 103093 */     GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(103189), // Rule ID 5030 //
     /* 103098 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 103101 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103105 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103109 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 103113 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 103117 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103122 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 103124 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn))  =>  (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
     /* 103124 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 103127 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103131 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103136 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 103138 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103141 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103145 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103150 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 103153 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103157 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103160 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103165 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103170 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103175 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i32),
     /* 103178 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103180 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103183 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 103187 */       GIR_RootConstrainSelectedInstOperands,
     /* 103188 */       // GIR_Coverage, 5030,
     /* 103188 */       GIR_EraseRootFromParent_Done,
     /* 103189 */     // Label 1595: @103189
     /* 103189 */     GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(103251), // Rule ID 5865 //
     /* 103194 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103198 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103202 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 103206 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 103208 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] }))  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] })
     /* 103208 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 103211 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103215 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103220 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 103222 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103225 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103227 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103230 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 103232 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 103235 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103240 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103245 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103250 */       // GIR_Coverage, 5865,
     /* 103250 */       GIR_EraseRootFromParent_Done,
     /* 103251 */     // Label 1596: @103251
     /* 103251 */     GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(103313), // Rule ID 5869 //
     /* 103256 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103260 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103264 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 103268 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 103270 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] }))  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] })
     /* 103270 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 103273 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103277 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103282 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 103284 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103287 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103289 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103292 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 103294 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 103297 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103302 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103307 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103312 */       // GIR_Coverage, 5869,
     /* 103312 */       GIR_EraseRootFromParent_Done,
     /* 103313 */     // Label 1597: @103313
     /* 103313 */     GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(103447), // Rule ID 5863 //
     /* 103318 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103322 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103326 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 103326 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 103329 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103333 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103338 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 103340 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 103343 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103347 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103352 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 103355 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 103359 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 103362 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103367 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103372 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103377 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 103380 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103384 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103389 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 103391 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103394 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103398 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103403 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 103406 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103410 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103413 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103418 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103423 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103428 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 103431 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103433 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103436 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 103439 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 103442 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 103445 */       GIR_RootConstrainSelectedInstOperands,
     /* 103446 */       // GIR_Coverage, 5863,
     /* 103446 */       GIR_EraseRootFromParent_Done,
     /* 103447 */     // Label 1598: @103447
     /* 103447 */     GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(103581), // Rule ID 5867 //
     /* 103452 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103456 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103460 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn)  =>  (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 103460 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 103463 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103467 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103472 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 103474 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 103477 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103481 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103486 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 103489 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 103493 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 103496 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103501 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103506 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103511 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 103514 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 103518 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103523 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 103525 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103528 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 103532 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103537 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 103540 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103544 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103547 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103552 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103557 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103562 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 103565 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103567 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103570 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 103573 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 103576 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 103579 */       GIR_RootConstrainSelectedInstOperands,
     /* 103580 */       // GIR_Coverage, 5867,
     /* 103580 */       GIR_EraseRootFromParent_Done,
     /* 103581 */     // Label 1599: @103581
     /* 103581 */     GIM_Reject,
     /* 103582 */   // Label 1575: @103582
     /* 103582 */   GIM_Reject,
     /* 103583 */   // Label 1558: @103583
     /* 103583 */   GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(105991),
     /* 103588 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 103591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 103594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103598 */     GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(103727), // Rule ID 5473 //
     /* 103603 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103607 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103611 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 103615 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103619 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103623 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 103627 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103631 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 103635 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103639 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103643 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 103647 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103652 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103656 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103662 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 103664 */       // MIs[2] Operand 2
     /* 103664 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 103675 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 103677 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 103677 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103680 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 103684 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103689 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 103692 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103696 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103699 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103704 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103709 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 103712 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103714 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103717 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 103721 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 103725 */       GIR_RootConstrainSelectedInstOperands,
     /* 103726 */       // GIR_Coverage, 5473,
     /* 103726 */       GIR_EraseRootFromParent_Done,
     /* 103727 */     // Label 1601: @103727
     /* 103727 */     GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(103849), // Rule ID 5469 //
     /* 103732 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103736 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103740 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 103744 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103748 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103752 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 103756 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103760 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 103764 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 103768 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103772 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 103776 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103781 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103786 */       // MIs[2] Operand 2
     /* 103786 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 103797 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 103799 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (ADDHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 103799 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103802 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 103806 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103811 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 103814 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103818 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103821 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103826 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103831 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
     /* 103834 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103836 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103839 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 103843 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 103847 */       GIR_RootConstrainSelectedInstOperands,
     /* 103848 */       // GIR_Coverage, 5469,
     /* 103848 */       GIR_EraseRootFromParent_Done,
     /* 103849 */     // Label 1602: @103849
     /* 103849 */     GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(103971), // Rule ID 5471 //
     /* 103854 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103858 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 103862 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 103866 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103870 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103874 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 103878 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103882 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 103886 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 103890 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103894 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 103898 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103903 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103908 */       // MIs[2] Operand 2
     /* 103908 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 103919 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 103921 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 103921 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 103924 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 103928 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103933 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 103936 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 103940 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 103943 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 103948 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 103953 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 103956 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 103958 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103961 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 103965 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 103969 */       GIR_RootConstrainSelectedInstOperands,
     /* 103970 */       // GIR_Coverage, 5471,
     /* 103970 */       GIR_EraseRootFromParent_Done,
     /* 103971 */     // Label 1603: @103971
     /* 103971 */     GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(104073), // Rule ID 5624 //
     /* 103976 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103980 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 103984 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 103988 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103992 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 103996 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104000 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104005 */       // MIs[2] Operand 2
     /* 104005 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 104016 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 104020 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 104024 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104028 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 104032 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 104036 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104040 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104045 */       // MIs[4] Operand 2
     /* 104045 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(16),
     /* 104056 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 104058 */       // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })), (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, 16:{ *:[i32] })))  =>  (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 104058 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 104061 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 104063 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 104067 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 104071 */       GIR_RootConstrainSelectedInstOperands,
     /* 104072 */       // GIR_Coverage, 5624,
     /* 104072 */       GIR_EraseRootFromParent_Done,
     /* 104073 */     // Label 1604: @104073
     /* 104073 */     GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(104202), // Rule ID 6410 //
     /* 104078 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104082 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104086 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 104090 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 104093 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 104098 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 104102 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 104106 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104111 */       GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 16,
     /* 104115 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104117 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vd, (intrinsic_wo_chain:{ *:[v4i16] } 667:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] }))  =>  (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
     /* 104117 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 104120 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 104124 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104129 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 104132 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 104134 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104137 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104141 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104146 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104148 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104151 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104155 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104160 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104163 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 104167 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104170 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104175 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104180 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104185 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
     /* 104188 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104190 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104193 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 104197 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 104200 */       GIR_RootConstrainSelectedInstOperands,
     /* 104201 */       // GIR_Coverage, 6410,
     /* 104201 */       GIR_EraseRootFromParent_Done,
     /* 104202 */     // Label 1605: @104202
     /* 104202 */     GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(104244), // Rule ID 5874 //
     /* 104207 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 104214 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 104221 */       // (concat_vectors:{ *:[v8i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (INSvi64lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] })
     /* 104221 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 104224 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104226 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 104231 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 104234 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 104239 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 104242 */       GIR_RootConstrainSelectedInstOperands,
     /* 104243 */       // GIR_Coverage, 5874,
     /* 104243 */       GIR_EraseRootFromParent_Done,
     /* 104244 */     // Label 1606: @104244
     /* 104244 */     GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(104286), // Rule ID 5878 //
     /* 104249 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 104256 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 104263 */       // (concat_vectors:{ *:[v8f16] } (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn), (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm))  =>  (INSvi64lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })
     /* 104263 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 104266 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104268 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 104273 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 104276 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 104281 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 104284 */       GIR_RootConstrainSelectedInstOperands,
     /* 104285 */       // GIR_Coverage, 5878,
     /* 104285 */       GIR_EraseRootFromParent_Done,
     /* 104286 */     // Label 1607: @104286
     /* 104286 */     GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(104409), // Rule ID 2576 //
     /* 104291 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 104294 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104298 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104302 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 104306 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 104309 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 104314 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 104318 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 104322 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104327 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 104331 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 104335 */       GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 104339 */       // MIs[2] Operand 1
     /* 104339 */       // No operand predicates
     /* 104339 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104341 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 667:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (RSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 104341 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104344 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104348 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104353 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104355 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104358 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104362 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104367 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104370 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104374 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104377 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104382 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104387 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104392 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i16_shift),
     /* 104395 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104397 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104400 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 104404 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 104407 */       GIR_RootConstrainSelectedInstOperands,
     /* 104408 */       // GIR_Coverage, 2576,
     /* 104408 */       GIR_EraseRootFromParent_Done,
     /* 104409 */     // Label 1608: @104409
     /* 104409 */     GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(104532), // Rule ID 6380 //
     /* 104414 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 104417 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104421 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104425 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 104429 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104433 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104437 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 104441 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104445 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104450 */       // MIs[2] imm
     /* 104450 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104454 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 104458 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 104462 */       // MIs[3] Operand 1
     /* 104462 */       // No operand predicates
     /* 104462 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104464 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 104464 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104467 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104471 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104476 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104478 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104481 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104485 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104490 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104493 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104497 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104500 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104505 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104510 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104515 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
     /* 104518 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104520 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104523 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 104527 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 104530 */       GIR_RootConstrainSelectedInstOperands,
     /* 104531 */       // GIR_Coverage, 6380,
     /* 104531 */       GIR_EraseRootFromParent_Done,
     /* 104532 */     // Label 1609: @104532
     /* 104532 */     GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(104652), // Rule ID 6416 //
     /* 104537 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104541 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104545 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 104549 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104553 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104557 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 104561 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 104565 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104570 */       // MIs[2] imm
     /* 104570 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104574 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 104578 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 104582 */       // MIs[3] Operand 1
     /* 104582 */       // No operand predicates
     /* 104582 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104584 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 104584 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104587 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104591 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104596 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104598 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104601 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104605 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104610 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104613 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104617 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104620 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104625 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104630 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104635 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
     /* 104638 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104640 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104643 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 104647 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 104650 */       GIR_RootConstrainSelectedInstOperands,
     /* 104651 */       // GIR_Coverage, 6416,
     /* 104651 */       GIR_EraseRootFromParent_Done,
     /* 104652 */     // Label 1610: @104652
     /* 104652 */     GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(104769), // Rule ID 2500 //
     /* 104657 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 104660 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104664 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104668 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 104672 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 104675 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 104680 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 104684 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 104688 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104693 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104698 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104700 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 579:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 104700 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104703 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104707 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104712 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104714 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104717 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104721 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104726 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104729 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104733 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104736 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104741 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104746 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104751 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
     /* 104754 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104756 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104759 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 104763 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 104767 */       GIR_RootConstrainSelectedInstOperands,
     /* 104768 */       // GIR_Coverage, 2500,
     /* 104768 */       GIR_EraseRootFromParent_Done,
     /* 104769 */     // Label 1611: @104769
     /* 104769 */     GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(104886), // Rule ID 5394 //
     /* 104774 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 104777 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104781 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104785 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 104789 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 104792 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 104797 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 104801 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 104805 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104810 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104815 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104817 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 724:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 104817 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104820 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104824 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104829 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104831 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104834 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104838 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104843 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104846 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104850 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104853 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104858 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104863 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104868 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 104871 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104873 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104876 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 104880 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 104884 */       GIR_RootConstrainSelectedInstOperands,
     /* 104885 */       // GIR_Coverage, 5394,
     /* 104885 */       GIR_EraseRootFromParent_Done,
     /* 104886 */     // Label 1612: @104886
     /* 104886 */     GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(105003), // Rule ID 5397 //
     /* 104891 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 104894 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104898 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104902 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 104906 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 104909 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 104914 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 104918 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 104922 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104927 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104932 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104934 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 666:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 104934 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 104937 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 104941 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104946 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 104948 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 104951 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 104955 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104960 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 104963 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 104967 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 104970 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104975 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 104980 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 104985 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
     /* 104988 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 104990 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104993 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 104997 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 105001 */       GIR_RootConstrainSelectedInstOperands,
     /* 105002 */       // GIR_Coverage, 5397,
     /* 105002 */       GIR_EraseRootFromParent_Done,
     /* 105003 */     // Label 1613: @105003
     /* 105003 */     GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(105120), // Rule ID 5400 //
     /* 105008 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 105011 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105015 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105019 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 105023 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 105026 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 105031 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 105035 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 105039 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105044 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105049 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105051 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 668:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 105051 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105054 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105058 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105063 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105065 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105068 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105072 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105077 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105080 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105084 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105087 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105092 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105097 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105102 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v8i16),
     /* 105105 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105107 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105110 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 105114 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 105118 */       GIR_RootConstrainSelectedInstOperands,
     /* 105119 */       // GIR_Coverage, 5400,
     /* 105119 */       GIR_EraseRootFromParent_Done,
     /* 105120 */     // Label 1614: @105120
     /* 105120 */     GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(105221), // Rule ID 4977 //
     /* 105125 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105129 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105133 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 105137 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 105140 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
     /* 105145 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 105149 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105154 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105156 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 774:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn))  =>  (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
     /* 105156 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105159 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105163 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105168 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105170 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105173 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105177 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105182 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105185 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105189 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105192 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105197 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105202 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105207 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 105210 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105212 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105215 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 105219 */       GIR_RootConstrainSelectedInstOperands,
     /* 105220 */       // GIR_Coverage, 4977,
     /* 105220 */       GIR_EraseRootFromParent_Done,
     /* 105221 */     // Label 1615: @105221
     /* 105221 */     GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(105277), // Rule ID 5549 //
     /* 105226 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105230 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 105234 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 105238 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105243 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 105247 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 105251 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 105255 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105260 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 105262 */       // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm))  =>  (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 105262 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 105265 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 105267 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 105271 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 105275 */       GIR_RootConstrainSelectedInstOperands,
     /* 105276 */       // GIR_Coverage, 5549,
     /* 105276 */       GIR_EraseRootFromParent_Done,
     /* 105277 */     // Label 1616: @105277
     /* 105277 */     GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(105343), // Rule ID 5872 //
     /* 105282 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105286 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105290 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105296 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 105298 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105300 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4i16] }:$Rn), dsub:{ *:[i32] })
     /* 105300 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 105303 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 105307 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105312 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 105316 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 105318 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 105321 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105323 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 105326 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105329 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 105332 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105337 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105342 */       // GIR_Coverage, 5872,
     /* 105342 */       GIR_EraseRootFromParent_Done,
     /* 105343 */     // Label 1617: @105343
     /* 105343 */     GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(105409), // Rule ID 5876 //
     /* 105348 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105352 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105356 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105362 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 105364 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105366 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4f16] }:$Rn), dsub:{ *:[i32] })
     /* 105366 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 105369 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 105373 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105378 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 105382 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 105384 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 105387 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105389 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 105392 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105395 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 105398 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105403 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105408 */       // GIR_Coverage, 5876,
     /* 105408 */       GIR_EraseRootFromParent_Done,
     /* 105409 */     // Label 1618: @105409
     /* 105409 */     GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(105502), // Rule ID 4985 //
     /* 105414 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105418 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105422 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /* 105426 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 105430 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105435 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105437 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn))  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
     /* 105437 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105440 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105444 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105449 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105451 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105454 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105458 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105463 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105466 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105470 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105473 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105478 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105483 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105488 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 105491 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105493 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105496 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 105500 */       GIR_RootConstrainSelectedInstOperands,
     /* 105501 */       // GIR_Coverage, 4985,
     /* 105501 */       GIR_EraseRootFromParent_Done,
     /* 105502 */     // Label 1619: @105502
     /* 105502 */     GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(105598), // Rule ID 5029 //
     /* 105507 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 105510 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105514 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105518 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 105522 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 105526 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105531 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105533 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn))  =>  (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
     /* 105533 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105536 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105540 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105545 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105547 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105550 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105554 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105559 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105562 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105566 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105569 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105574 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105579 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105584 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i16),
     /* 105587 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105589 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105592 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 105596 */       GIR_RootConstrainSelectedInstOperands,
     /* 105597 */       // GIR_Coverage, 5029,
     /* 105597 */       GIR_EraseRootFromParent_Done,
     /* 105598 */     // Label 1620: @105598
     /* 105598 */     GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(105660), // Rule ID 5873 //
     /* 105603 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105607 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105611 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 105615 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105617 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] }))  =>  (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] })
     /* 105617 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 105620 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105624 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105629 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 105631 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105634 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105636 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105639 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 105641 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 105644 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105649 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105654 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105659 */       // GIR_Coverage, 5873,
     /* 105659 */       GIR_EraseRootFromParent_Done,
     /* 105660 */     // Label 1621: @105660
     /* 105660 */     GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(105722), // Rule ID 5877 //
     /* 105665 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105669 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105673 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 105677 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 105679 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, (undef:{ *:[v4f16] }))  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] })
     /* 105679 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 105682 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105686 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105691 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 105693 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105696 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105698 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105701 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 105703 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 105706 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105711 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105716 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105721 */       // GIR_Coverage, 5877,
     /* 105721 */       GIR_EraseRootFromParent_Done,
     /* 105722 */     // Label 1622: @105722
     /* 105722 */     GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(105856), // Rule ID 5871 //
     /* 105727 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105731 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105735 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 105735 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 105738 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105742 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105747 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 105749 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 105752 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105756 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105761 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 105764 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 105768 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 105771 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105776 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105781 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105786 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105789 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105793 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105798 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105800 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105803 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105807 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105812 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105815 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105819 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105822 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105827 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105832 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105837 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 105840 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105842 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105845 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 105848 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 105851 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 105854 */       GIR_RootConstrainSelectedInstOperands,
     /* 105855 */       // GIR_Coverage, 5871,
     /* 105855 */       GIR_EraseRootFromParent_Done,
     /* 105856 */     // Label 1623: @105856
     /* 105856 */     GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(105990), // Rule ID 5875 //
     /* 105861 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105865 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105869 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn)  =>  (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 105869 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 105872 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105876 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105881 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 105883 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 105886 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105890 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105895 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 105898 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 105902 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 105905 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105910 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105915 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105920 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 105923 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 105927 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105932 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 105934 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 105937 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 105941 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 105946 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 105949 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 105953 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 105956 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105961 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 105966 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 105971 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 105974 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 105976 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 105979 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 105982 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 105985 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 105988 */       GIR_RootConstrainSelectedInstOperands,
     /* 105989 */       // GIR_Coverage, 5875,
     /* 105989 */       GIR_EraseRootFromParent_Done,
     /* 105990 */     // Label 1624: @105990
     /* 105990 */     GIM_Reject,
     /* 105991 */   // Label 1600: @105991
     /* 105991 */   GIM_Reject,
     /* 105992 */   // Label 1559: @105992
     /* 105992 */   GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(107902),
     /* 105997 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 106000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 106003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106007 */     GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(106136), // Rule ID 5467 //
     /* 106012 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106016 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106020 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106024 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106028 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106032 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106036 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106040 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 106044 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106048 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106052 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106056 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106061 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 106065 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106071 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 106073 */       // MIs[2] Operand 2
     /* 106073 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 106084 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 106086 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 106086 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106089 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 106093 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106098 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 106101 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106105 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106108 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106113 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106118 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 106121 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106123 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106126 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 106130 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 106134 */       GIR_RootConstrainSelectedInstOperands,
     /* 106135 */       // GIR_Coverage, 5467,
     /* 106135 */       GIR_EraseRootFromParent_Done,
     /* 106136 */     // Label 1626: @106136
     /* 106136 */     GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(106258), // Rule ID 5463 //
     /* 106141 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106145 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106149 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106153 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106157 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106161 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106165 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106169 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 106173 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 106177 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106181 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106185 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106190 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106195 */       // MIs[2] Operand 2
     /* 106195 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 106206 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 106208 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (ADDHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 106208 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106211 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 106215 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106220 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 106223 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106227 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106230 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106235 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106240 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
     /* 106243 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106245 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106248 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 106252 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 106256 */       GIR_RootConstrainSelectedInstOperands,
     /* 106257 */       // GIR_Coverage, 5463,
     /* 106257 */       GIR_EraseRootFromParent_Done,
     /* 106258 */     // Label 1627: @106258
     /* 106258 */     GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(106380), // Rule ID 5465 //
     /* 106263 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106267 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106271 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106275 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106279 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106283 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106287 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106291 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 106295 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 106299 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106303 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106307 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106312 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106317 */       // MIs[2] Operand 2
     /* 106317 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 106328 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 106330 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 106330 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106333 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 106337 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106342 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 106345 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106349 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106352 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106357 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106362 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 106365 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106367 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106370 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 106374 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 106378 */       GIR_RootConstrainSelectedInstOperands,
     /* 106379 */       // GIR_Coverage, 5465,
     /* 106379 */       GIR_EraseRootFromParent_Done,
     /* 106380 */     // Label 1628: @106380
     /* 106380 */     GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(106482), // Rule ID 5623 //
     /* 106385 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106389 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106393 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106397 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106401 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106405 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106409 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106414 */       // MIs[2] Operand 2
     /* 106414 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 106425 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 106429 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106433 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106437 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 106441 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106445 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106449 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106454 */       // MIs[4] Operand 2
     /* 106454 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(8),
     /* 106465 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 106467 */       // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })), (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, 8:{ *:[i32] })))  =>  (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 106467 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 106470 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 106472 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 106476 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 106480 */       GIR_RootConstrainSelectedInstOperands,
     /* 106481 */       // GIR_Coverage, 5623,
     /* 106481 */       GIR_EraseRootFromParent_Done,
     /* 106482 */     // Label 1629: @106482
     /* 106482 */     GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(106611), // Rule ID 6409 //
     /* 106487 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106491 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106495 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 106499 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 106502 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 106507 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106511 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 106515 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106520 */       GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 8,
     /* 106524 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 106526 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Vd, (intrinsic_wo_chain:{ *:[v8i8] } 667:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] }))  =>  (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
     /* 106526 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 106529 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 106533 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106538 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 106541 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 106543 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 106546 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 106550 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106555 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 106557 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106560 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 106564 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106569 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 106572 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 106576 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106579 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106584 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106589 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106594 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
     /* 106597 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106599 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106602 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 106606 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 106609 */       GIR_RootConstrainSelectedInstOperands,
     /* 106610 */       // GIR_Coverage, 6409,
     /* 106610 */       GIR_EraseRootFromParent_Done,
     /* 106611 */     // Label 1630: @106611
     /* 106611 */     GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(106653), // Rule ID 5882 //
     /* 106616 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 106623 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 106630 */       // (concat_vectors:{ *:[v16i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (INSvi64lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] })
     /* 106630 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 106633 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106635 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 106640 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 106643 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 106648 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 106651 */       GIR_RootConstrainSelectedInstOperands,
     /* 106652 */       // GIR_Coverage, 5882,
     /* 106652 */       GIR_EraseRootFromParent_Done,
     /* 106653 */     // Label 1631: @106653
     /* 106653 */     GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(106776), // Rule ID 2574 //
     /* 106658 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106661 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106665 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106669 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 106673 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 106676 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 106681 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106685 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 106689 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106694 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 106698 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 106702 */       GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 106706 */       // MIs[2] Operand 1
     /* 106706 */       // No operand predicates
     /* 106706 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106708 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 667:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (RSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 106708 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 106711 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 106715 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106720 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 106722 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106725 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 106729 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106734 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 106737 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106741 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106744 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106749 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106754 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106759 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv16i8_shift),
     /* 106762 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106764 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106767 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 106771 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 106774 */       GIR_RootConstrainSelectedInstOperands,
     /* 106775 */       // GIR_Coverage, 2574,
     /* 106775 */       GIR_EraseRootFromParent_Done,
     /* 106776 */     // Label 1632: @106776
     /* 106776 */     GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(106899), // Rule ID 6379 //
     /* 106781 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106784 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106788 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106792 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106796 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106800 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106804 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 106808 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106812 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106817 */       // MIs[2] imm
     /* 106817 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 106821 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 106825 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 106829 */       // MIs[3] Operand 1
     /* 106829 */       // No operand predicates
     /* 106829 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 106831 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 106831 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 106834 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 106838 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106843 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 106845 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106848 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 106852 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106857 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 106860 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106864 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106867 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106872 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106877 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106882 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
     /* 106885 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 106887 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 106890 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 106894 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 106897 */       GIR_RootConstrainSelectedInstOperands,
     /* 106898 */       // GIR_Coverage, 6379,
     /* 106898 */       GIR_EraseRootFromParent_Done,
     /* 106899 */     // Label 1633: @106899
     /* 106899 */     GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(107019), // Rule ID 6415 //
     /* 106904 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106908 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106912 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 106916 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106920 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 106924 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 106928 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106932 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106937 */       // MIs[2] imm
     /* 106937 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 106941 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 106945 */       GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 106949 */       // MIs[3] Operand 1
     /* 106949 */       // No operand predicates
     /* 106949 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 106951 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 106951 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 106954 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 106958 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106963 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 106965 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 106968 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 106972 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 106977 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 106980 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 106984 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 106987 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106992 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106997 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107002 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
     /* 107005 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107007 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107010 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 107014 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 107017 */       GIR_RootConstrainSelectedInstOperands,
     /* 107018 */       // GIR_Coverage, 6415,
     /* 107018 */       GIR_EraseRootFromParent_Done,
     /* 107019 */     // Label 1634: @107019
     /* 107019 */     GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(107136), // Rule ID 2499 //
     /* 107024 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107027 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107031 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107035 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 107039 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 107042 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 107047 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107051 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 107055 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107060 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107065 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107067 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 579:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107067 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107070 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107074 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107079 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107081 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107084 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107088 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107093 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107096 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107100 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107103 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107108 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107113 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107118 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
     /* 107121 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107123 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107126 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 107130 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 107134 */       GIR_RootConstrainSelectedInstOperands,
     /* 107135 */       // GIR_Coverage, 2499,
     /* 107135 */       GIR_EraseRootFromParent_Done,
     /* 107136 */     // Label 1635: @107136
     /* 107136 */     GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(107253), // Rule ID 5393 //
     /* 107141 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107144 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107148 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107152 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 107156 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 107159 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 107164 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107168 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 107172 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107177 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107182 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107184 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 724:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107184 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107187 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107191 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107196 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107198 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107201 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107205 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107210 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107213 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107217 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107220 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107225 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107230 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107235 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 107238 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107240 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107243 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 107247 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 107251 */       GIR_RootConstrainSelectedInstOperands,
     /* 107252 */       // GIR_Coverage, 5393,
     /* 107252 */       GIR_EraseRootFromParent_Done,
     /* 107253 */     // Label 1636: @107253
     /* 107253 */     GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(107370), // Rule ID 5396 //
     /* 107258 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107261 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107265 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107269 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 107273 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 107276 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 107281 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107285 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 107289 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107294 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107299 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107301 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 666:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107301 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107304 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107308 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107313 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107315 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107318 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107322 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107327 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107330 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107334 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107337 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107342 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107347 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107352 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
     /* 107355 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107357 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107360 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 107364 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 107368 */       GIR_RootConstrainSelectedInstOperands,
     /* 107369 */       // GIR_Coverage, 5396,
     /* 107369 */       GIR_EraseRootFromParent_Done,
     /* 107370 */     // Label 1637: @107370
     /* 107370 */     GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(107487), // Rule ID 5399 //
     /* 107375 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107378 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107382 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107386 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 107390 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 107393 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 107398 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107402 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 107406 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107411 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107416 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107418 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 668:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107418 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107421 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107425 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107430 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107432 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107435 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107439 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107444 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107447 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107451 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107454 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107459 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107464 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107469 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v16i8),
     /* 107472 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107474 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107477 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 107481 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 107485 */       GIR_RootConstrainSelectedInstOperands,
     /* 107486 */       // GIR_Coverage, 5399,
     /* 107486 */       GIR_EraseRootFromParent_Done,
     /* 107487 */     // Label 1638: @107487
     /* 107487 */     GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(107543), // Rule ID 5540 //
     /* 107492 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 107496 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 107500 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107504 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107509 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 107513 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 107517 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107521 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107526 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 107528 */       // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn), (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vm))  =>  (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 107528 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
     /* 107531 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 107533 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 107537 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 107541 */       GIR_RootConstrainSelectedInstOperands,
     /* 107542 */       // GIR_Coverage, 5540,
     /* 107542 */       GIR_EraseRootFromParent_Done,
     /* 107543 */     // Label 1639: @107543
     /* 107543 */     GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(107609), // Rule ID 5880 //
     /* 107548 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107552 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107556 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 107562 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 107564 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107566 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v8i8] }:$Rn), dsub:{ *:[i32] })
     /* 107566 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 107569 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 107573 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107578 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 107582 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 107584 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 107587 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107589 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 107592 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107595 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 107598 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107603 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107608 */       // GIR_Coverage, 5880,
     /* 107608 */       GIR_EraseRootFromParent_Done,
     /* 107609 */     // Label 1640: @107609
     /* 107609 */     GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(107705), // Rule ID 5028 //
     /* 107614 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107617 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107621 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107625 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 107629 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107633 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107638 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107640 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn))  =>  (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
     /* 107640 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107643 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107647 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107652 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107654 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107657 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107661 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107666 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107669 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107673 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107676 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107681 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107686 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107691 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv16i8),
     /* 107694 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107696 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107699 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 107703 */       GIR_RootConstrainSelectedInstOperands,
     /* 107704 */       // GIR_Coverage, 5028,
     /* 107704 */       GIR_EraseRootFromParent_Done,
     /* 107705 */     // Label 1641: @107705
     /* 107705 */     GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(107767), // Rule ID 5881 //
     /* 107710 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107714 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 107718 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 107722 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 107724 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] }))  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] })
     /* 107724 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 107727 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107731 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107736 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 107738 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107741 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107743 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107746 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 107748 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 107751 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107756 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107761 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107766 */       // GIR_Coverage, 5881,
     /* 107766 */       GIR_EraseRootFromParent_Done,
     /* 107767 */     // Label 1642: @107767
     /* 107767 */     GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(107901), // Rule ID 5879 //
     /* 107772 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107776 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107780 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 107780 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 107783 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107787 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107792 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 107794 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 107797 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107801 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107806 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 107809 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 107813 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 107816 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107821 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107826 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107831 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 107834 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 107838 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107843 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 107845 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 107848 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 107852 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 107857 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 107860 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 107864 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 107867 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107872 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107877 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107882 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 107885 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 107887 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 107890 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 107893 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 107896 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 107899 */       GIR_RootConstrainSelectedInstOperands,
     /* 107900 */       // GIR_Coverage, 5879,
     /* 107900 */       GIR_EraseRootFromParent_Done,
     /* 107901 */     // Label 1643: @107901
     /* 107901 */     GIM_Reject,
     /* 107902 */   // Label 1625: @107902
     /* 107902 */   GIM_Reject,
     /* 107903 */   // Label 1560: @107903
     /* 107903 */   GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(107928), // Rule ID 9194 //
     /* 107908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 107911 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /* 107914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 107917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 107921 */     // (concat_vectors:{ *:[nxv2i1] } nxv1i1:{ *:[nxv1i1] }:$p1, nxv1i1:{ *:[nxv1i1] }:$p2)  =>  (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv1i1] }:$p1, ?:{ *:[nxv1i1] }:$p2)
     /* 107921 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 107926 */     GIR_RootConstrainSelectedInstOperands,
     /* 107927 */     // GIR_Coverage, 9194,
     /* 107927 */     GIR_Done,
     /* 107928 */   // Label 1644: @107928
     /* 107928 */   GIM_Reject,
     /* 107929 */   // Label 1561: @107929
     /* 107929 */   GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(107954), // Rule ID 9195 //
     /* 107934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 107937 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 107940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 107943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 107947 */     // (concat_vectors:{ *:[nxv4i1] } nxv2i1:{ *:[nxv2i1] }:$p1, nxv2i1:{ *:[nxv2i1] }:$p2)  =>  (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv2i1] }:$p1, ?:{ *:[nxv2i1] }:$p2)
     /* 107947 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 107952 */     GIR_RootConstrainSelectedInstOperands,
     /* 107953 */     // GIR_Coverage, 9195,
     /* 107953 */     GIR_Done,
     /* 107954 */   // Label 1645: @107954
     /* 107954 */   GIM_Reject,
     /* 107955 */   // Label 1562: @107955
     /* 107955 */   GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(107980), // Rule ID 9198 //
     /* 107960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 107963 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 107966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 107969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 107973 */     // (concat_vectors:{ *:[nxv4f16] } nxv2f16:{ *:[nxv2f16] }:$v1, nxv2f16:{ *:[nxv2f16] }:$v2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv2f16] }:$v1, ?:{ *:[nxv2f16] }:$v2)
     /* 107973 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 107978 */     GIR_RootConstrainSelectedInstOperands,
     /* 107979 */     // GIR_Coverage, 9198,
     /* 107979 */     GIR_Done,
     /* 107980 */   // Label 1646: @107980
     /* 107980 */   GIM_Reject,
     /* 107981 */   // Label 1563: @107981
     /* 107981 */   GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(108006), // Rule ID 9200 //
     /* 107986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 107989 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 107992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 107995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 107999 */     // (concat_vectors:{ *:[nxv4f32] } nxv2f32:{ *:[nxv2f32] }:$v1, nxv2f32:{ *:[nxv2f32] }:$v2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv2f32] }:$v1, ?:{ *:[nxv2f32] }:$v2)
     /* 107999 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 108004 */     GIR_RootConstrainSelectedInstOperands,
     /* 108005 */     // GIR_Coverage, 9200,
     /* 108005 */     GIR_Done,
     /* 108006 */   // Label 1647: @108006
     /* 108006 */   GIM_Reject,
     /* 108007 */   // Label 1564: @108007
     /* 108007 */   GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(108032), // Rule ID 9196 //
     /* 108012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 108015 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 108018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 108021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 108025 */     // (concat_vectors:{ *:[nxv8i1] } nxv4i1:{ *:[nxv4i1] }:$p1, nxv4i1:{ *:[nxv4i1] }:$p2)  =>  (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv4i1] }:$p1, ?:{ *:[nxv4i1] }:$p2)
     /* 108025 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 108030 */     GIR_RootConstrainSelectedInstOperands,
     /* 108031 */     // GIR_Coverage, 9196,
     /* 108031 */     GIR_Done,
     /* 108032 */   // Label 1648: @108032
     /* 108032 */   GIM_Reject,
     /* 108033 */   // Label 1565: @108033
     /* 108033 */   GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(108058), // Rule ID 9199 //
     /* 108038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 108041 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 108044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 108047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 108051 */     // (concat_vectors:{ *:[nxv8f16] } nxv4f16:{ *:[nxv4f16] }:$v1, nxv4f16:{ *:[nxv4f16] }:$v2)  =>  (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv4f16] }:$v1, ?:{ *:[nxv4f16] }:$v2)
     /* 108051 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 108056 */     GIR_RootConstrainSelectedInstOperands,
     /* 108057 */     // GIR_Coverage, 9199,
     /* 108057 */     GIR_Done,
     /* 108058 */   // Label 1649: @108058
     /* 108058 */   GIM_Reject,
     /* 108059 */   // Label 1566: @108059
     /* 108059 */   GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(108084), // Rule ID 9197 //
     /* 108064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 108067 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 108070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 108073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 108077 */     // (concat_vectors:{ *:[nxv16i1] } nxv8i1:{ *:[nxv8i1] }:$p1, nxv8i1:{ *:[nxv8i1] }:$p2)  =>  (UZP1_PPP_B:{ *:[nxv16i1] } ?:{ *:[nxv8i1] }:$p1, ?:{ *:[nxv8i1] }:$p2)
     /* 108077 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
     /* 108082 */     GIR_RootConstrainSelectedInstOperands,
     /* 108083 */     // GIR_Coverage, 9197,
     /* 108083 */     GIR_Done,
     /* 108084 */   // Label 1650: @108084
     /* 108084 */   GIM_Reject,
     /* 108085 */   // Label 1567: @108085
     /* 108085 */   GIM_Reject,
     /* 108086 */ // Label 1555: @108086
     /* 108086 */ GIM_Reject,
     /* 108087 */ // Label 9: @108087
     /* 108087 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1665*/ GIMT_Encode4(118168),
     /* 108098 */ /*GILLT_s32*//*Label 1651*/ GIMT_Encode4(108186),
     /* 108102 */ /*GILLT_s64*//*Label 1652*/ GIMT_Encode4(108689),
     /* 108106 */ /*GILLT_s128*//*Label 1653*/ GIMT_Encode4(110680),
     /* 108110 */ /*GILLT_v2s32*//*Label 1654*/ GIMT_Encode4(111326),
     /* 108114 */ /*GILLT_v2s64*//*Label 1655*/ GIMT_Encode4(112241),
     /* 108118 */ /*GILLT_v4s16*//*Label 1656*/ GIMT_Encode4(113010),
     /* 108122 */ /*GILLT_v4s32*//*Label 1657*/ GIMT_Encode4(113925),
     /* 108126 */ /*GILLT_v8s8*//*Label 1658*/ GIMT_Encode4(114770),
     /* 108130 */ /*GILLT_v8s16*//*Label 1659*/ GIMT_Encode4(115331),
     /* 108134 */ /*GILLT_v16s8*//*Label 1660*/ GIMT_Encode4(116176), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 108154 */ /*GILLT_nxv2s64*//*Label 1661*/ GIMT_Encode4(116628), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 108166 */ /*GILLT_nxv4s32*//*Label 1662*/ GIMT_Encode4(117077), GIMT_Encode4(0),
     /* 108174 */ /*GILLT_nxv8s16*//*Label 1663*/ GIMT_Encode4(117526), GIMT_Encode4(0),
     /* 108182 */ /*GILLT_nxv16s8*//*Label 1664*/ GIMT_Encode4(117975),
     /* 108186 */ // Label 1651: @108186
     /* 108186 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(108688),
     /* 108191 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 108194 */   GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(108268), // Rule ID 7146 //
     /* 108199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108211 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108214 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108218 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 108225 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108228 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108232 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108234 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 108241 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>)  =>  (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 108241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 108244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 108256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 108261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108266 */     GIR_RootConstrainSelectedInstOperands,
     /* 108267 */     // GIR_Coverage, 7146,
     /* 108267 */     GIR_EraseRootFromParent_Done,
     /* 108268 */   // Label 1667: @108268
     /* 108268 */   GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(108342), // Rule ID 7147 //
     /* 108273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108285 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108288 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108292 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 108299 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108302 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108306 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108308 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 108315 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>)  =>  (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 108315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 108318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 108330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 108335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108340 */     GIR_RootConstrainSelectedInstOperands,
     /* 108341 */     // GIR_Coverage, 7147,
     /* 108341 */     GIR_EraseRootFromParent_Done,
     /* 108342 */   // Label 1668: @108342
     /* 108342 */   GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(108411), // Rule ID 7148 //
     /* 108347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108359 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108362 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108366 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 108373 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108376 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108380 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108382 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 108389 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>)  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 108389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 108392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 108404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108409 */     GIR_RootConstrainSelectedInstOperands,
     /* 108410 */     // GIR_Coverage, 7148,
     /* 108410 */     GIR_EraseRootFromParent_Done,
     /* 108411 */   // Label 1669: @108411
     /* 108411 */   GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(108480), // Rule ID 7149 //
     /* 108416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108424 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108428 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108431 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108435 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 108442 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108445 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108449 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108451 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 108458 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>)  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 108458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 108461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 108473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108478 */     GIR_RootConstrainSelectedInstOperands,
     /* 108479 */     // GIR_Coverage, 7149,
     /* 108479 */     GIR_EraseRootFromParent_Done,
     /* 108480 */   // Label 1670: @108480
     /* 108480 */   GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(108533), // Rule ID 5841 //
     /* 108485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 108489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 108497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 108501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 108505 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 108509 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108511 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v16i8:{ *:[v16i8] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v16i8] }:$src, bsub:{ *:[i32] })
     /* 108511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 108514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108516 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
     /* 108522 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 108527 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108532 */     // GIR_Coverage, 5841,
     /* 108532 */     GIR_EraseRootFromParent_Done,
     /* 108533 */   // Label 1671: @108533
     /* 108533 */   GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(108586), // Rule ID 5842 //
     /* 108538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 108542 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108546 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 108550 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 108554 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 108558 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 108562 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108564 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v8i16:{ *:[v8i16] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v8i16] }:$src, hsub:{ *:[i32] })
     /* 108564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 108567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108569 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // src
     /* 108575 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 108580 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108585 */     // GIR_Coverage, 5842,
     /* 108585 */     GIR_EraseRootFromParent_Done,
     /* 108586 */   // Label 1672: @108586
     /* 108586 */   GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(108639), // Rule ID 5843 //
     /* 108591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108595 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108599 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 108603 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 108607 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 108611 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 108615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108617 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v4i32:{ *:[v4i32] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4i32] }:$src, ssub:{ *:[i32] })
     /* 108617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 108620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108622 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // src
     /* 108628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108633 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108638 */     // GIR_Coverage, 5843,
     /* 108638 */     GIR_EraseRootFromParent_Done,
     /* 108639 */   // Label 1673: @108639
     /* 108639 */   GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(108663), // Rule ID 6751 //
     /* 108644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 108652 */     // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] })
     /* 108652 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 108657 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108662 */     // GIR_Coverage, 6751,
     /* 108662 */     GIR_Done,
     /* 108663 */   // Label 1674: @108663
     /* 108663 */   GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(108687), // Rule ID 6752 //
     /* 108668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 108672 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 108676 */     // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] })
     /* 108676 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 108681 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 108686 */     // GIR_Coverage, 6752,
     /* 108686 */     GIR_Done,
     /* 108687 */   // Label 1675: @108687
     /* 108687 */   GIM_Reject,
     /* 108688 */ // Label 1666: @108688
     /* 108688 */ GIM_Reject,
     /* 108689 */ // Label 1652: @108689
     /* 108689 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(108766), // Rule ID 7150 //
     /* 108694 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108701 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108705 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108709 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108712 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108716 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 108723 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108726 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108730 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108732 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 108739 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>)  =>  (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 108739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 108742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 108754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 108759 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108764 */   GIR_RootConstrainSelectedInstOperands,
     /* 108765 */   // GIR_Coverage, 7150,
     /* 108765 */   GIR_EraseRootFromParent_Done,
     /* 108766 */ // Label 1676: @108766
     /* 108766 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(108843), // Rule ID 7151 //
     /* 108771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108778 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108782 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108786 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108789 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108793 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 108800 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108803 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108807 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108809 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 108816 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>)  =>  (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 108816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 108819 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 108831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 108836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108841 */   GIR_RootConstrainSelectedInstOperands,
     /* 108842 */   // GIR_Coverage, 7151,
     /* 108842 */   GIR_EraseRootFromParent_Done,
     /* 108843 */ // Label 1677: @108843
     /* 108843 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(108915), // Rule ID 7152 //
     /* 108848 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108855 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108859 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108863 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108866 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108870 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 108877 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108880 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108884 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108886 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 108893 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>)  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 108893 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 108896 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 108908 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108913 */   GIR_RootConstrainSelectedInstOperands,
     /* 108914 */   // GIR_Coverage, 7152,
     /* 108914 */   GIR_EraseRootFromParent_Done,
     /* 108915 */ // Label 1678: @108915
     /* 108915 */ GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(108987), // Rule ID 7153 //
     /* 108920 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108923 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108927 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108931 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 108935 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 108938 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 108942 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 108949 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 108952 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 108956 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108958 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 108965 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>)  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 108965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 108968 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 108970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 108975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 108980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 108985 */   GIR_RootConstrainSelectedInstOperands,
     /* 108986 */   // GIR_Coverage, 7153,
     /* 108986 */   GIR_EraseRootFromParent_Done,
     /* 108987 */ // Label 1679: @108987
     /* 108987 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(109043), // Rule ID 5844 //
     /* 108992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108999 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 109003 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 109007 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109011 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 109015 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 109019 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 109021 */   // (bitconvert:{ *:[f64] } (vector_extract:{ *:[i64] } v2i64:{ *:[v2i64] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2i64] }:$src, dsub:{ *:[i32] })
     /* 109021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109026 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src
     /* 109032 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109037 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109042 */   // GIR_Coverage, 5844,
     /* 109042 */   GIR_EraseRootFromParent_Done,
     /* 109043 */ // Label 1680: @109043
     /* 109043 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(109073), // Rule ID 6726 //
     /* 109048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109051 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 109054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109058 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109062 */   // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })
     /* 109062 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109067 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109072 */   // GIR_Coverage, 6726,
     /* 109072 */   GIR_Done,
     /* 109073 */ // Label 1681: @109073
     /* 109073 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(109103), // Rule ID 6727 //
     /* 109078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109088 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109092 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })
     /* 109092 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109097 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109102 */   // GIR_Coverage, 6727,
     /* 109102 */   GIR_Done,
     /* 109103 */ // Label 1682: @109103
     /* 109103 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(109133), // Rule ID 6728 //
     /* 109108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109111 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109118 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109122 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })
     /* 109122 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109127 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109132 */   // GIR_Coverage, 6728,
     /* 109132 */   GIR_Done,
     /* 109133 */ // Label 1683: @109133
     /* 109133 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(109163), // Rule ID 6729 //
     /* 109138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109148 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109152 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })
     /* 109152 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109157 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109162 */   // GIR_Coverage, 6729,
     /* 109162 */   GIR_Done,
     /* 109163 */ // Label 1684: @109163
     /* 109163 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(109193), // Rule ID 6730 //
     /* 109168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109171 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109178 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109182 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })
     /* 109182 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109187 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109192 */   // GIR_Coverage, 6730,
     /* 109192 */   GIR_Done,
     /* 109193 */ // Label 1685: @109193
     /* 109193 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(109223), // Rule ID 6731 //
     /* 109198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109208 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109212 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
     /* 109212 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109217 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109222 */   // GIR_Coverage, 6731,
     /* 109222 */   GIR_Done,
     /* 109223 */ // Label 1686: @109223
     /* 109223 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(109273), // Rule ID 6737 //
     /* 109228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109231 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 109234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109238 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109242 */   // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn)  =>  (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }))
     /* 109242 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 109245 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109249 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109254 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 109258 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 109266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109268 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109271 */   GIR_RootConstrainSelectedInstOperands,
     /* 109272 */   // GIR_Coverage, 6737,
     /* 109272 */   GIR_EraseRootFromParent_Done,
     /* 109273 */ // Label 1687: @109273
     /* 109273 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(109323), // Rule ID 6738 //
     /* 109278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109281 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109288 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109292 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn)  =>  (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }))
     /* 109292 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 109295 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109299 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109304 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 109308 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 109316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109318 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109321 */   GIR_RootConstrainSelectedInstOperands,
     /* 109322 */   // GIR_Coverage, 6738,
     /* 109322 */   GIR_EraseRootFromParent_Done,
     /* 109323 */ // Label 1688: @109323
     /* 109323 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(109373), // Rule ID 6739 //
     /* 109328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109338 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109342 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn)  =>  (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }))
     /* 109342 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 109345 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109349 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109354 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 109358 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 109366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109368 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109371 */   GIR_RootConstrainSelectedInstOperands,
     /* 109372 */   // GIR_Coverage, 6739,
     /* 109372 */   GIR_EraseRootFromParent_Done,
     /* 109373 */ // Label 1689: @109373
     /* 109373 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(109423), // Rule ID 6740 //
     /* 109378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109381 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109388 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109392 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn)  =>  (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }))
     /* 109392 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 109395 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109399 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109404 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 109408 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 109416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109418 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109421 */   GIR_RootConstrainSelectedInstOperands,
     /* 109422 */   // GIR_Coverage, 6740,
     /* 109422 */   GIR_EraseRootFromParent_Done,
     /* 109423 */ // Label 1690: @109423
     /* 109423 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(109473), // Rule ID 6741 //
     /* 109428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109431 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109434 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109438 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109442 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn)  =>  (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }))
     /* 109442 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 109445 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109449 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109454 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 109458 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 109466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109468 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109471 */   GIR_RootConstrainSelectedInstOperands,
     /* 109472 */   // GIR_Coverage, 6741,
     /* 109472 */   GIR_EraseRootFromParent_Done,
     /* 109473 */ // Label 1691: @109473
     /* 109473 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(109500), // Rule ID 6742 //
     /* 109478 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109481 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109485 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109489 */   // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 109489 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109494 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109499 */   // GIR_Coverage, 6742,
     /* 109499 */   GIR_Done,
     /* 109500 */ // Label 1692: @109500
     /* 109500 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(109527), // Rule ID 6743 //
     /* 109505 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109512 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109516 */   // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 109516 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109521 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109526 */   // GIR_Coverage, 6743,
     /* 109526 */   GIR_Done,
     /* 109527 */ // Label 1693: @109527
     /* 109527 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(109554), // Rule ID 6744 //
     /* 109532 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109539 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109543 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] })
     /* 109543 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109548 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109553 */   // GIR_Coverage, 6744,
     /* 109553 */   GIR_Done,
     /* 109554 */ // Label 1694: @109554
     /* 109554 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(109581), // Rule ID 6753 //
     /* 109559 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109562 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109566 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109570 */   // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 109570 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109575 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109580 */   // GIR_Coverage, 6753,
     /* 109580 */   GIR_Done,
     /* 109581 */ // Label 1695: @109581
     /* 109581 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(109608), // Rule ID 6754 //
     /* 109586 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109593 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109597 */   // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] })
     /* 109597 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109602 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109607 */   // GIR_Coverage, 6754,
     /* 109607 */   GIR_Done,
     /* 109608 */ // Label 1696: @109608
     /* 109608 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(109635), // Rule ID 6755 //
     /* 109613 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109620 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109624 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
     /* 109624 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109629 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 109634 */   // GIR_Coverage, 6755,
     /* 109634 */   GIR_Done,
     /* 109635 */ // Label 1697: @109635
     /* 109635 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(109667), // Rule ID 6756 //
     /* 109640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109650 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109654 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109657 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109659 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109661 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109666 */   // GIR_Coverage, 6756,
     /* 109666 */   GIR_EraseRootFromParent_Done,
     /* 109667 */ // Label 1698: @109667
     /* 109667 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(109699), // Rule ID 6757 //
     /* 109672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109675 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109682 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109686 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109686 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109689 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109691 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109693 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109698 */   // GIR_Coverage, 6757,
     /* 109698 */   GIR_EraseRootFromParent_Done,
     /* 109699 */ // Label 1699: @109699
     /* 109699 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(109731), // Rule ID 6758 //
     /* 109704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 109710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109714 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109718 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109721 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109723 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109725 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109730 */   // GIR_Coverage, 6758,
     /* 109730 */   GIR_EraseRootFromParent_Done,
     /* 109731 */ // Label 1700: @109731
     /* 109731 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(109763), // Rule ID 6759 //
     /* 109736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109746 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109750 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109753 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109755 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109757 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109762 */   // GIR_Coverage, 6759,
     /* 109762 */   GIR_EraseRootFromParent_Done,
     /* 109763 */ // Label 1701: @109763
     /* 109763 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(109795), // Rule ID 6760 //
     /* 109768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109778 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109782 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109785 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109787 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109789 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109794 */   // GIR_Coverage, 6760,
     /* 109794 */   GIR_EraseRootFromParent_Done,
     /* 109795 */ // Label 1702: @109795
     /* 109795 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(109821), // Rule ID 6761 //
     /* 109800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109803 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109810 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109814 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)
     /* 109814 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 109819 */   GIR_RootConstrainSelectedInstOperands,
     /* 109820 */   // GIR_Coverage, 6761,
     /* 109820 */   GIR_Done,
     /* 109821 */ // Label 1703: @109821
     /* 109821 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(109847), // Rule ID 6762 //
     /* 109826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109829 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109832 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109836 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109840 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)
     /* 109840 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 109845 */   GIR_RootConstrainSelectedInstOperands,
     /* 109846 */   // GIR_Coverage, 6762,
     /* 109846 */   GIR_Done,
     /* 109847 */ // Label 1704: @109847
     /* 109847 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(109873), // Rule ID 6763 //
     /* 109852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 109858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109862 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109866 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)
     /* 109866 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 109871 */   GIR_RootConstrainSelectedInstOperands,
     /* 109872 */   // GIR_Coverage, 6763,
     /* 109872 */   GIR_Done,
     /* 109873 */ // Label 1705: @109873
     /* 109873 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(109899), // Rule ID 6764 //
     /* 109878 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109881 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 109884 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109888 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109892 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)
     /* 109892 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 109897 */   GIR_RootConstrainSelectedInstOperands,
     /* 109898 */   // GIR_Coverage, 6764,
     /* 109898 */   GIR_Done,
     /* 109899 */ // Label 1706: @109899
     /* 109899 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(109925), // Rule ID 6765 //
     /* 109904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 109907 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109910 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109914 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109918 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)
     /* 109918 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 109923 */   GIR_RootConstrainSelectedInstOperands,
     /* 109924 */   // GIR_Coverage, 6765,
     /* 109924 */   GIR_Done,
     /* 109925 */ // Label 1707: @109925
     /* 109925 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(109954), // Rule ID 6766 //
     /* 109930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109937 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109941 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109944 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109946 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109948 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109953 */   // GIR_Coverage, 6766,
     /* 109953 */   GIR_EraseRootFromParent_Done,
     /* 109954 */ // Label 1708: @109954
     /* 109954 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(109983), // Rule ID 6767 //
     /* 109959 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 109962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109966 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109970 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 109970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 109973 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 109975 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 109977 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109982 */   // GIR_Coverage, 6767,
     /* 109982 */   GIR_EraseRootFromParent_Done,
     /* 109983 */ // Label 1709: @109983
     /* 109983 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(110015), // Rule ID 6821 //
     /* 109988 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 109991 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 109994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109998 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110002 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110005 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110007 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110009 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110014 */   // GIR_Coverage, 6821,
     /* 110014 */   GIR_EraseRootFromParent_Done,
     /* 110015 */ // Label 1710: @110015
     /* 110015 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(110047), // Rule ID 6822 //
     /* 110020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110023 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110030 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110034 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110037 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110039 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110041 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110046 */   // GIR_Coverage, 6822,
     /* 110046 */   GIR_EraseRootFromParent_Done,
     /* 110047 */ // Label 1711: @110047
     /* 110047 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(110079), // Rule ID 6823 //
     /* 110052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110055 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110058 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110062 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110066 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110069 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110071 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110073 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110078 */   // GIR_Coverage, 6823,
     /* 110078 */   GIR_EraseRootFromParent_Done,
     /* 110079 */ // Label 1712: @110079
     /* 110079 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(110111), // Rule ID 6824 //
     /* 110084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 110090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110094 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110098 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110101 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110103 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110105 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110110 */   // GIR_Coverage, 6824,
     /* 110110 */   GIR_EraseRootFromParent_Done,
     /* 110111 */ // Label 1713: @110111
     /* 110111 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(110143), // Rule ID 6825 //
     /* 110116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110126 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110130 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110133 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110135 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110137 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110142 */   // GIR_Coverage, 6825,
     /* 110142 */   GIR_EraseRootFromParent_Done,
     /* 110143 */ // Label 1714: @110143
     /* 110143 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(110169), // Rule ID 6826 //
     /* 110148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110162 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)
     /* 110162 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 110167 */   GIR_RootConstrainSelectedInstOperands,
     /* 110168 */   // GIR_Coverage, 6826,
     /* 110168 */   GIR_Done,
     /* 110169 */ // Label 1715: @110169
     /* 110169 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(110195), // Rule ID 6827 //
     /* 110174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110184 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110188 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)
     /* 110188 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 110193 */   GIR_RootConstrainSelectedInstOperands,
     /* 110194 */   // GIR_Coverage, 6827,
     /* 110194 */   GIR_Done,
     /* 110195 */ // Label 1716: @110195
     /* 110195 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(110221), // Rule ID 6828 //
     /* 110200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110203 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110210 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110214 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)
     /* 110214 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 110219 */   GIR_RootConstrainSelectedInstOperands,
     /* 110220 */   // GIR_Coverage, 6828,
     /* 110220 */   GIR_Done,
     /* 110221 */ // Label 1717: @110221
     /* 110221 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(110247), // Rule ID 6829 //
     /* 110226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110229 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 110232 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110236 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110240 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)
     /* 110240 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 110245 */   GIR_RootConstrainSelectedInstOperands,
     /* 110246 */   // GIR_Coverage, 6829,
     /* 110246 */   GIR_Done,
     /* 110247 */ // Label 1718: @110247
     /* 110247 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(110273), // Rule ID 6830 //
     /* 110252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110255 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110262 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110266 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)
     /* 110266 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 110271 */   GIR_RootConstrainSelectedInstOperands,
     /* 110272 */   // GIR_Coverage, 6830,
     /* 110272 */   GIR_Done,
     /* 110273 */ // Label 1719: @110273
     /* 110273 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(110302), // Rule ID 6831 //
     /* 110278 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 110281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110285 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110289 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110289 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110292 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110294 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110296 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110301 */   // GIR_Coverage, 6831,
     /* 110301 */   GIR_EraseRootFromParent_Done,
     /* 110302 */ // Label 1720: @110302
     /* 110302 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(110331), // Rule ID 6832 //
     /* 110307 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 110310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110314 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110318 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 110318 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110321 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110323 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110325 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110330 */   // GIR_Coverage, 6832,
     /* 110330 */   GIR_EraseRootFromParent_Done,
     /* 110331 */ // Label 1721: @110331
     /* 110331 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(110363), // Rule ID 6833 //
     /* 110336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110346 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110350 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110353 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110355 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110357 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110362 */   // GIR_Coverage, 6833,
     /* 110362 */   GIR_EraseRootFromParent_Done,
     /* 110363 */ // Label 1722: @110363
     /* 110363 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(110395), // Rule ID 6834 //
     /* 110368 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110382 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110385 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110387 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110389 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110394 */   // GIR_Coverage, 6834,
     /* 110394 */   GIR_EraseRootFromParent_Done,
     /* 110395 */ // Label 1723: @110395
     /* 110395 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(110427), // Rule ID 6835 //
     /* 110400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 110406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110410 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110414 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110417 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110419 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110421 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110426 */   // GIR_Coverage, 6835,
     /* 110426 */   GIR_EraseRootFromParent_Done,
     /* 110427 */ // Label 1724: @110427
     /* 110427 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(110459), // Rule ID 6836 //
     /* 110432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110435 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110442 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110446 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110446 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110449 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110451 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110453 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110458 */   // GIR_Coverage, 6836,
     /* 110458 */   GIR_EraseRootFromParent_Done,
     /* 110459 */ // Label 1725: @110459
     /* 110459 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(110491), // Rule ID 6837 //
     /* 110464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110467 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110470 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110474 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110478 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110481 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110483 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110485 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110490 */   // GIR_Coverage, 6837,
     /* 110490 */   GIR_EraseRootFromParent_Done,
     /* 110491 */ // Label 1726: @110491
     /* 110491 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(110517), // Rule ID 6838 //
     /* 110496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110506 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110510 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)
     /* 110510 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 110515 */   GIR_RootConstrainSelectedInstOperands,
     /* 110516 */   // GIR_Coverage, 6838,
     /* 110516 */   GIR_Done,
     /* 110517 */ // Label 1727: @110517
     /* 110517 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(110543), // Rule ID 6839 //
     /* 110522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110532 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110536 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)
     /* 110536 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 110541 */   GIR_RootConstrainSelectedInstOperands,
     /* 110542 */   // GIR_Coverage, 6839,
     /* 110542 */   GIR_Done,
     /* 110543 */ // Label 1728: @110543
     /* 110543 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(110569), // Rule ID 6840 //
     /* 110548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110551 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 110554 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110558 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110562 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)
     /* 110562 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 110567 */   GIR_RootConstrainSelectedInstOperands,
     /* 110568 */   // GIR_Coverage, 6840,
     /* 110568 */   GIR_Done,
     /* 110569 */ // Label 1729: @110569
     /* 110569 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(110595), // Rule ID 6841 //
     /* 110574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110577 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 110580 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110584 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110588 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)
     /* 110588 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 110593 */   GIR_RootConstrainSelectedInstOperands,
     /* 110594 */   // GIR_Coverage, 6841,
     /* 110594 */   GIR_Done,
     /* 110595 */ // Label 1730: @110595
     /* 110595 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(110621), // Rule ID 6842 //
     /* 110600 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110603 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 110606 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110610 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110614 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)
     /* 110614 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 110619 */   GIR_RootConstrainSelectedInstOperands,
     /* 110620 */   // GIR_Coverage, 6842,
     /* 110620 */   GIR_Done,
     /* 110621 */ // Label 1731: @110621
     /* 110621 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(110650), // Rule ID 6843 //
     /* 110626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 110629 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110633 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110637 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110640 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110642 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110644 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110649 */   // GIR_Coverage, 6843,
     /* 110649 */   GIR_EraseRootFromParent_Done,
     /* 110650 */ // Label 1732: @110650
     /* 110650 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(110679), // Rule ID 6844 //
     /* 110655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 110658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110662 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110666 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 110666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110669 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110671 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110673 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110678 */   // GIR_Coverage, 6844,
     /* 110678 */   GIR_EraseRootFromParent_Done,
     /* 110679 */ // Label 1733: @110679
     /* 110679 */ GIM_Reject,
     /* 110680 */ // Label 1653: @110680
     /* 110680 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(110712), // Rule ID 6858 //
     /* 110685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110688 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110695 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110699 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110702 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110704 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110706 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110711 */   // GIR_Coverage, 6858,
     /* 110711 */   GIR_EraseRootFromParent_Done,
     /* 110712 */ // Label 1734: @110712
     /* 110712 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(110744), // Rule ID 6859 //
     /* 110717 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110720 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 110723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110727 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110731 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110734 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110736 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110743 */   // GIR_Coverage, 6859,
     /* 110743 */   GIR_EraseRootFromParent_Done,
     /* 110744 */ // Label 1735: @110744
     /* 110744 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(110776), // Rule ID 6860 //
     /* 110749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110752 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 110755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110759 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110763 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110766 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110768 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110770 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110775 */   // GIR_Coverage, 6860,
     /* 110775 */   GIR_EraseRootFromParent_Done,
     /* 110776 */ // Label 1736: @110776
     /* 110776 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(110808), // Rule ID 6861 //
     /* 110781 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110784 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110791 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110795 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110798 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110800 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110802 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110807 */   // GIR_Coverage, 6861,
     /* 110807 */   GIR_EraseRootFromParent_Done,
     /* 110808 */ // Label 1737: @110808
     /* 110808 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(110840), // Rule ID 6862 //
     /* 110813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 110819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110823 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110827 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110830 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110832 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110834 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110839 */   // GIR_Coverage, 6862,
     /* 110839 */   GIR_EraseRootFromParent_Done,
     /* 110840 */ // Label 1738: @110840
     /* 110840 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(110872), // Rule ID 6863 //
     /* 110845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110848 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 110851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110855 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110859 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110862 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110864 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110866 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110871 */   // GIR_Coverage, 6863,
     /* 110871 */   GIR_EraseRootFromParent_Done,
     /* 110872 */ // Label 1739: @110872
     /* 110872 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(110904), // Rule ID 6864 //
     /* 110877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 110880 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 110883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110887 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110891 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 110891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 110894 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 110896 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110898 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110903 */   // GIR_Coverage, 6864,
     /* 110903 */   GIR_EraseRootFromParent_Done,
     /* 110904 */ // Label 1740: @110904
     /* 110904 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(110937), // Rule ID 6865 //
     /* 110909 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110912 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110919 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110923 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src)  =>  (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] })
     /* 110923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 110926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 110928 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110930 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 110932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 110935 */   GIR_RootConstrainSelectedInstOperands,
     /* 110936 */   // GIR_Coverage, 6865,
     /* 110936 */   GIR_EraseRootFromParent_Done,
     /* 110937 */ // Label 1741: @110937
     /* 110937 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(111008), // Rule ID 6866 //
     /* 110942 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 110945 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 110948 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110952 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110956 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] })
     /* 110956 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110959 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 110963 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110968 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 110972 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110974 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110977 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 110981 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110986 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 110990 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 110992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 110995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 110997 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111000 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 111003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111006 */   GIR_RootConstrainSelectedInstOperands,
     /* 111007 */   // GIR_Coverage, 6866,
     /* 111007 */   GIR_EraseRootFromParent_Done,
     /* 111008 */ // Label 1742: @111008
     /* 111008 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(111079), // Rule ID 6867 //
     /* 111013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111016 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 111019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111023 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111027 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] })
     /* 111027 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111030 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 111034 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111039 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111043 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111045 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111048 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 111052 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111057 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111061 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 111066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111068 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111071 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 111074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111077 */   GIR_RootConstrainSelectedInstOperands,
     /* 111078 */   // GIR_Coverage, 6867,
     /* 111078 */   GIR_EraseRootFromParent_Done,
     /* 111079 */ // Label 1743: @111079
     /* 111079 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(111150), // Rule ID 6868 //
     /* 111084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 111090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111094 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111098 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] })
     /* 111098 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111101 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 111105 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111110 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111114 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111116 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111119 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 111123 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111128 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111132 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 111137 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111139 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111142 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 111145 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111148 */   GIR_RootConstrainSelectedInstOperands,
     /* 111149 */   // GIR_Coverage, 6868,
     /* 111149 */   GIR_EraseRootFromParent_Done,
     /* 111150 */ // Label 1744: @111150
     /* 111150 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(111183), // Rule ID 6869 //
     /* 111155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111158 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111165 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111169 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src)  =>  (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] })
     /* 111169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 111172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111174 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111176 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111178 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111181 */   GIR_RootConstrainSelectedInstOperands,
     /* 111182 */   // GIR_Coverage, 6869,
     /* 111182 */   GIR_EraseRootFromParent_Done,
     /* 111183 */ // Label 1745: @111183
     /* 111183 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(111254), // Rule ID 6870 //
     /* 111188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111191 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 111194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111198 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111202 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] })
     /* 111202 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111205 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 111209 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111214 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111218 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111220 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111223 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 111227 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111232 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111236 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 111241 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111243 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111246 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 111249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111252 */   GIR_RootConstrainSelectedInstOperands,
     /* 111253 */   // GIR_Coverage, 6870,
     /* 111253 */   GIR_EraseRootFromParent_Done,
     /* 111254 */ // Label 1746: @111254
     /* 111254 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(111325), // Rule ID 6871 //
     /* 111259 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111262 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 111265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111269 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111273 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] })
     /* 111273 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111276 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 111280 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111285 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111289 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111291 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111294 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 111298 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111303 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 111307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 111312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111314 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111317 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 111320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 111323 */   GIR_RootConstrainSelectedInstOperands,
     /* 111324 */   // GIR_Coverage, 6871,
     /* 111324 */   GIR_EraseRootFromParent_Done,
     /* 111325 */ // Label 1747: @111325
     /* 111325 */ GIM_Reject,
     /* 111326 */ // Label 1654: @111326
     /* 111326 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(111356), // Rule ID 6723 //
     /* 111331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111341 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 111345 */   // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 111345 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111350 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111355 */   // GIR_Coverage, 6723,
     /* 111355 */   GIR_Done,
     /* 111356 */ // Label 1748: @111356
     /* 111356 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(111386), // Rule ID 6725 //
     /* 111361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111371 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 111375 */   // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 111375 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111380 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111385 */   // GIR_Coverage, 6725,
     /* 111385 */   GIR_Done,
     /* 111386 */ // Label 1749: @111386
     /* 111386 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(111436), // Rule ID 6734 //
     /* 111391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111394 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111397 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111401 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 111405 */   // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 111405 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 111408 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111412 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111417 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 111421 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 111429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111431 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111434 */   GIR_RootConstrainSelectedInstOperands,
     /* 111435 */   // GIR_Coverage, 6734,
     /* 111435 */   GIR_EraseRootFromParent_Done,
     /* 111436 */ // Label 1750: @111436
     /* 111436 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(111486), // Rule ID 6736 //
     /* 111441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111444 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111447 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111451 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 111455 */   // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 111455 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 111458 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111462 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111467 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 111471 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 111479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 111481 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111484 */   GIR_RootConstrainSelectedInstOperands,
     /* 111485 */   // GIR_Coverage, 6736,
     /* 111485 */   GIR_EraseRootFromParent_Done,
     /* 111486 */ // Label 1751: @111486
     /* 111486 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(111518), // Rule ID 6768 //
     /* 111491 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111494 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111501 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111505 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111508 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111510 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111512 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111517 */   // GIR_Coverage, 6768,
     /* 111517 */   GIR_EraseRootFromParent_Done,
     /* 111518 */ // Label 1752: @111518
     /* 111518 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(111550), // Rule ID 6769 //
     /* 111523 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111526 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 111529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111533 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111537 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111540 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111542 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111544 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111549 */   // GIR_Coverage, 6769,
     /* 111549 */   GIR_EraseRootFromParent_Done,
     /* 111550 */ // Label 1753: @111550
     /* 111550 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(111582), // Rule ID 6770 //
     /* 111555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111558 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 111561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111565 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111569 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111572 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111574 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111576 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111581 */   // GIR_Coverage, 6770,
     /* 111581 */   GIR_EraseRootFromParent_Done,
     /* 111582 */ // Label 1754: @111582
     /* 111582 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(111614), // Rule ID 6771 //
     /* 111587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111597 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111601 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111604 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111606 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111608 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111613 */   // GIR_Coverage, 6771,
     /* 111613 */   GIR_EraseRootFromParent_Done,
     /* 111614 */ // Label 1755: @111614
     /* 111614 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(111646), // Rule ID 6772 //
     /* 111619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111622 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111629 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111633 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111633 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111636 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111638 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111640 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111645 */   // GIR_Coverage, 6772,
     /* 111645 */   GIR_EraseRootFromParent_Done,
     /* 111646 */ // Label 1756: @111646
     /* 111646 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(111678), // Rule ID 6773 //
     /* 111651 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111654 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 111657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111661 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111665 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111668 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111670 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111672 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111677 */   // GIR_Coverage, 6773,
     /* 111677 */   GIR_EraseRootFromParent_Done,
     /* 111678 */ // Label 1757: @111678
     /* 111678 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(111704), // Rule ID 6774 //
     /* 111683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111686 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111693 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111697 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)
     /* 111697 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 111702 */   GIR_RootConstrainSelectedInstOperands,
     /* 111703 */   // GIR_Coverage, 6774,
     /* 111703 */   GIR_Done,
     /* 111704 */ // Label 1758: @111704
     /* 111704 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(111730), // Rule ID 6775 //
     /* 111709 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111712 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 111715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111719 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111723 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)  =>  (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)
     /* 111723 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 111728 */   GIR_RootConstrainSelectedInstOperands,
     /* 111729 */   // GIR_Coverage, 6775,
     /* 111729 */   GIR_Done,
     /* 111730 */ // Label 1759: @111730
     /* 111730 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(111756), // Rule ID 6776 //
     /* 111735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111738 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 111741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111745 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111749 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)  =>  (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)
     /* 111749 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 111754 */   GIR_RootConstrainSelectedInstOperands,
     /* 111755 */   // GIR_Coverage, 6776,
     /* 111755 */   GIR_Done,
     /* 111756 */ // Label 1760: @111756
     /* 111756 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(111782), // Rule ID 6777 //
     /* 111761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111764 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111771 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111775 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)
     /* 111775 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 111780 */   GIR_RootConstrainSelectedInstOperands,
     /* 111781 */   // GIR_Coverage, 6777,
     /* 111781 */   GIR_Done,
     /* 111782 */ // Label 1761: @111782
     /* 111782 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(111808), // Rule ID 6778 //
     /* 111787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111790 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111797 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111801 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)
     /* 111801 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 111806 */   GIR_RootConstrainSelectedInstOperands,
     /* 111807 */   // GIR_Coverage, 6778,
     /* 111807 */   GIR_Done,
     /* 111808 */ // Label 1762: @111808
     /* 111808 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(111834), // Rule ID 6779 //
     /* 111813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 111816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 111819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111823 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111827 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)  =>  (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)
     /* 111827 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 111832 */   GIR_RootConstrainSelectedInstOperands,
     /* 111833 */   // GIR_Coverage, 6779,
     /* 111833 */   GIR_Done,
     /* 111834 */ // Label 1763: @111834
     /* 111834 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(111863), // Rule ID 6780 //
     /* 111839 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 111842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111846 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111850 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 111850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111853 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111855 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111857 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111862 */   // GIR_Coverage, 6780,
     /* 111862 */   GIR_EraseRootFromParent_Done,
     /* 111863 */ // Label 1764: @111863
     /* 111863 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(111895), // Rule ID 6845 //
     /* 111868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111871 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111878 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111882 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 111882 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111885 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111887 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111889 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111894 */   // GIR_Coverage, 6845,
     /* 111894 */   GIR_EraseRootFromParent_Done,
     /* 111895 */ // Label 1765: @111895
     /* 111895 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(111927), // Rule ID 6846 //
     /* 111900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111903 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 111906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111910 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111914 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 111914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111917 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111919 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111921 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111926 */   // GIR_Coverage, 6846,
     /* 111926 */   GIR_EraseRootFromParent_Done,
     /* 111927 */ // Label 1766: @111927
     /* 111927 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(111959), // Rule ID 6847 //
     /* 111932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111935 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 111938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111942 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111946 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 111946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111949 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111951 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111953 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111958 */   // GIR_Coverage, 6847,
     /* 111958 */   GIR_EraseRootFromParent_Done,
     /* 111959 */ // Label 1767: @111959
     /* 111959 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(111991), // Rule ID 6848 //
     /* 111964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111967 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 111970 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111974 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111978 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 111978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 111981 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 111983 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 111985 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111990 */   // GIR_Coverage, 6848,
     /* 111990 */   GIR_EraseRootFromParent_Done,
     /* 111991 */ // Label 1768: @111991
     /* 111991 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(112023), // Rule ID 6849 //
     /* 111996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 111999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 112002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112006 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112010 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 112010 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112013 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112015 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112017 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112022 */   // GIR_Coverage, 6849,
     /* 112022 */   GIR_EraseRootFromParent_Done,
     /* 112023 */ // Label 1769: @112023
     /* 112023 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(112055), // Rule ID 6850 //
     /* 112028 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112031 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 112034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112038 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112042 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 112042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112045 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112047 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112049 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112054 */   // GIR_Coverage, 6850,
     /* 112054 */   GIR_EraseRootFromParent_Done,
     /* 112055 */ // Label 1770: @112055
     /* 112055 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(112081), // Rule ID 6851 //
     /* 112060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112063 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 112066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112070 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112074 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)
     /* 112074 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 112079 */   GIR_RootConstrainSelectedInstOperands,
     /* 112080 */   // GIR_Coverage, 6851,
     /* 112080 */   GIR_Done,
     /* 112081 */ // Label 1771: @112081
     /* 112081 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(112107), // Rule ID 6852 //
     /* 112086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112089 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 112092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112096 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112100 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)  =>  (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)
     /* 112100 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 112105 */   GIR_RootConstrainSelectedInstOperands,
     /* 112106 */   // GIR_Coverage, 6852,
     /* 112106 */   GIR_Done,
     /* 112107 */ // Label 1772: @112107
     /* 112107 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(112133), // Rule ID 6853 //
     /* 112112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 112118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112122 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112126 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)  =>  (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)
     /* 112126 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 112131 */   GIR_RootConstrainSelectedInstOperands,
     /* 112132 */   // GIR_Coverage, 6853,
     /* 112132 */   GIR_Done,
     /* 112133 */ // Label 1773: @112133
     /* 112133 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(112159), // Rule ID 6854 //
     /* 112138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 112144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112148 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112152 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)
     /* 112152 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 112157 */   GIR_RootConstrainSelectedInstOperands,
     /* 112158 */   // GIR_Coverage, 6854,
     /* 112158 */   GIR_Done,
     /* 112159 */ // Label 1774: @112159
     /* 112159 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(112185), // Rule ID 6855 //
     /* 112164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 112170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112174 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112178 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)
     /* 112178 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 112183 */   GIR_RootConstrainSelectedInstOperands,
     /* 112184 */   // GIR_Coverage, 6855,
     /* 112184 */   GIR_Done,
     /* 112185 */ // Label 1775: @112185
     /* 112185 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(112211), // Rule ID 6856 //
     /* 112190 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112193 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 112196 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112200 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112204 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)  =>  (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)
     /* 112204 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 112209 */   GIR_RootConstrainSelectedInstOperands,
     /* 112210 */   // GIR_Coverage, 6856,
     /* 112210 */   GIR_Done,
     /* 112211 */ // Label 1776: @112211
     /* 112211 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(112240), // Rule ID 6857 //
     /* 112216 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 112219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112223 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112227 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 112227 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112230 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112232 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112234 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112239 */   // GIR_Coverage, 6857,
     /* 112239 */   GIR_EraseRootFromParent_Done,
     /* 112240 */ // Label 1777: @112240
     /* 112240 */ GIM_Reject,
     /* 112241 */ // Label 1655: @112241
     /* 112241 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(112273), // Rule ID 6872 //
     /* 112246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112249 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 112252 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112256 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112260 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112263 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112265 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112267 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112272 */   // GIR_Coverage, 6872,
     /* 112272 */   GIR_EraseRootFromParent_Done,
     /* 112273 */ // Label 1778: @112273
     /* 112273 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(112305), // Rule ID 6873 //
     /* 112278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112281 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112288 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112292 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112295 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112297 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112299 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112304 */   // GIR_Coverage, 6873,
     /* 112304 */   GIR_EraseRootFromParent_Done,
     /* 112305 */ // Label 1779: @112305
     /* 112305 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(112337), // Rule ID 6874 //
     /* 112310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112320 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112324 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112327 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112329 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112331 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112336 */   // GIR_Coverage, 6874,
     /* 112336 */   GIR_EraseRootFromParent_Done,
     /* 112337 */ // Label 1780: @112337
     /* 112337 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(112369), // Rule ID 6875 //
     /* 112342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112345 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112352 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112356 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112356 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112359 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112361 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112363 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112368 */   // GIR_Coverage, 6875,
     /* 112368 */   GIR_EraseRootFromParent_Done,
     /* 112369 */ // Label 1781: @112369
     /* 112369 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(112401), // Rule ID 6876 //
     /* 112374 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112377 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 112380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112384 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112388 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112391 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112393 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112395 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112400 */   // GIR_Coverage, 6876,
     /* 112400 */   GIR_EraseRootFromParent_Done,
     /* 112401 */ // Label 1782: @112401
     /* 112401 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(112433), // Rule ID 6877 //
     /* 112406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112409 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112416 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112420 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112420 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112423 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112425 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112427 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112432 */   // GIR_Coverage, 6877,
     /* 112432 */   GIR_EraseRootFromParent_Done,
     /* 112433 */ // Label 1783: @112433
     /* 112433 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(112466), // Rule ID 6878 //
     /* 112438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112441 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 112444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112448 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112452 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
     /* 112452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 112455 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 112457 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112459 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112461 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 112464 */   GIR_RootConstrainSelectedInstOperands,
     /* 112465 */   // GIR_Coverage, 6878,
     /* 112465 */   GIR_EraseRootFromParent_Done,
     /* 112466 */ // Label 1784: @112466
     /* 112466 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(112492), // Rule ID 6879 //
     /* 112471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112481 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112485 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)  =>  (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)
     /* 112485 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 112490 */   GIR_RootConstrainSelectedInstOperands,
     /* 112491 */   // GIR_Coverage, 6879,
     /* 112491 */   GIR_Done,
     /* 112492 */ // Label 1785: @112492
     /* 112492 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(112518), // Rule ID 6880 //
     /* 112497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112500 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112507 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112511 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)  =>  (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)
     /* 112511 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 112516 */   GIR_RootConstrainSelectedInstOperands,
     /* 112517 */   // GIR_Coverage, 6880,
     /* 112517 */   GIR_Done,
     /* 112518 */ // Label 1786: @112518
     /* 112518 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(112544), // Rule ID 6881 //
     /* 112523 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112526 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112533 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112537 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)  =>  (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)
     /* 112537 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 112542 */   GIR_RootConstrainSelectedInstOperands,
     /* 112543 */   // GIR_Coverage, 6881,
     /* 112543 */   GIR_Done,
     /* 112544 */ // Label 1787: @112544
     /* 112544 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(112570), // Rule ID 6882 //
     /* 112549 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112552 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 112555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112559 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112563 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)  =>  (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)
     /* 112563 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 112568 */   GIR_RootConstrainSelectedInstOperands,
     /* 112569 */   // GIR_Coverage, 6882,
     /* 112569 */   GIR_Done,
     /* 112570 */ // Label 1788: @112570
     /* 112570 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(112596), // Rule ID 6883 //
     /* 112575 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112578 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112581 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112585 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112589 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)  =>  (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)
     /* 112589 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 112594 */   GIR_RootConstrainSelectedInstOperands,
     /* 112595 */   // GIR_Coverage, 6883,
     /* 112595 */   GIR_Done,
     /* 112596 */ // Label 1789: @112596
     /* 112596 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(112625), // Rule ID 6884 //
     /* 112601 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 112604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112608 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112612 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 112612 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112615 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112617 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112619 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112624 */   // GIR_Coverage, 6884,
     /* 112624 */   GIR_EraseRootFromParent_Done,
     /* 112625 */ // Label 1790: @112625
     /* 112625 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(112657), // Rule ID 6898 //
     /* 112630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 112636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112640 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112644 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112647 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112649 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112651 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112656 */   // GIR_Coverage, 6898,
     /* 112656 */   GIR_EraseRootFromParent_Done,
     /* 112657 */ // Label 1791: @112657
     /* 112657 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(112689), // Rule ID 6899 //
     /* 112662 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112665 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112668 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112672 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112676 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112676 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112679 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112681 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112683 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112688 */   // GIR_Coverage, 6899,
     /* 112688 */   GIR_EraseRootFromParent_Done,
     /* 112689 */ // Label 1792: @112689
     /* 112689 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(112721), // Rule ID 6900 //
     /* 112694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112697 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112700 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112704 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112708 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112711 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112713 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112715 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112720 */   // GIR_Coverage, 6900,
     /* 112720 */   GIR_EraseRootFromParent_Done,
     /* 112721 */ // Label 1793: @112721
     /* 112721 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(112753), // Rule ID 6901 //
     /* 112726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112729 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 112732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112736 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112740 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112743 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112745 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112747 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112752 */   // GIR_Coverage, 6901,
     /* 112752 */   GIR_EraseRootFromParent_Done,
     /* 112753 */ // Label 1794: @112753
     /* 112753 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(112785), // Rule ID 6902 //
     /* 112758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112768 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112772 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112775 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112777 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112779 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112784 */   // GIR_Coverage, 6902,
     /* 112784 */   GIR_EraseRootFromParent_Done,
     /* 112785 */ // Label 1795: @112785
     /* 112785 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(112817), // Rule ID 6903 //
     /* 112790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 112793 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112800 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112804 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112807 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 112809 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112811 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112816 */   // GIR_Coverage, 6903,
     /* 112816 */   GIR_EraseRootFromParent_Done,
     /* 112817 */ // Label 1796: @112817
     /* 112817 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(112850), // Rule ID 6904 //
     /* 112822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 112828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112832 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112836 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
     /* 112836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 112839 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 112841 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112843 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 112845 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 112848 */   GIR_RootConstrainSelectedInstOperands,
     /* 112849 */   // GIR_Coverage, 6904,
     /* 112849 */   GIR_EraseRootFromParent_Done,
     /* 112850 */ // Label 1797: @112850
     /* 112850 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(112876), // Rule ID 6905 //
     /* 112855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112858 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112865 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112869 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)  =>  (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)
     /* 112869 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 112874 */   GIR_RootConstrainSelectedInstOperands,
     /* 112875 */   // GIR_Coverage, 6905,
     /* 112875 */   GIR_Done,
     /* 112876 */ // Label 1798: @112876
     /* 112876 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(112902), // Rule ID 6906 //
     /* 112881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112891 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112895 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)  =>  (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)
     /* 112895 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 112900 */   GIR_RootConstrainSelectedInstOperands,
     /* 112901 */   // GIR_Coverage, 6906,
     /* 112901 */   GIR_Done,
     /* 112902 */ // Label 1799: @112902
     /* 112902 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(112928), // Rule ID 6907 //
     /* 112907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112910 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 112913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112917 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112921 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)  =>  (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)
     /* 112921 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 112926 */   GIR_RootConstrainSelectedInstOperands,
     /* 112927 */   // GIR_Coverage, 6907,
     /* 112927 */   GIR_Done,
     /* 112928 */ // Label 1800: @112928
     /* 112928 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(112954), // Rule ID 6908 //
     /* 112933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112936 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112939 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112943 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112947 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)  =>  (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)
     /* 112947 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 112952 */   GIR_RootConstrainSelectedInstOperands,
     /* 112953 */   // GIR_Coverage, 6908,
     /* 112953 */   GIR_Done,
     /* 112954 */ // Label 1801: @112954
     /* 112954 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(112980), // Rule ID 6909 //
     /* 112959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 112962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 112965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112973 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)  =>  (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)
     /* 112973 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 112978 */   GIR_RootConstrainSelectedInstOperands,
     /* 112979 */   // GIR_Coverage, 6909,
     /* 112979 */   GIR_Done,
     /* 112980 */ // Label 1802: @112980
     /* 112980 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(113009), // Rule ID 6910 //
     /* 112985 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 112988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112992 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112996 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 112996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 112999 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113001 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113003 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113008 */   // GIR_Coverage, 6910,
     /* 113008 */   GIR_EraseRootFromParent_Done,
     /* 113009 */ // Label 1803: @113009
     /* 113009 */ GIM_Reject,
     /* 113010 */ // Label 1656: @113010
     /* 113010 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(113040), // Rule ID 6722 //
     /* 113015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113025 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 113029 */   // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 113029 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113034 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113039 */   // GIR_Coverage, 6722,
     /* 113039 */   GIR_Done,
     /* 113040 */ // Label 1804: @113040
     /* 113040 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(113070), // Rule ID 6724 //
     /* 113045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113048 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113055 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 113059 */   // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 113059 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113064 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113069 */   // GIR_Coverage, 6724,
     /* 113069 */   GIR_Done,
     /* 113070 */ // Label 1805: @113070
     /* 113070 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(113120), // Rule ID 6733 //
     /* 113075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113085 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 113089 */   // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 113089 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 113092 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113096 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113101 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 113105 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113110 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113113 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 113115 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113118 */   GIR_RootConstrainSelectedInstOperands,
     /* 113119 */   // GIR_Coverage, 6733,
     /* 113119 */   GIR_EraseRootFromParent_Done,
     /* 113120 */ // Label 1806: @113120
     /* 113120 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(113170), // Rule ID 6735 //
     /* 113125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113135 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 113139 */   // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 113139 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 113142 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113146 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113151 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 113155 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113163 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 113165 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113168 */   GIR_RootConstrainSelectedInstOperands,
     /* 113169 */   // GIR_Coverage, 6735,
     /* 113169 */   GIR_EraseRootFromParent_Done,
     /* 113170 */ // Label 1807: @113170
     /* 113170 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(113202), // Rule ID 6781 //
     /* 113175 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113178 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113185 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113189 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113192 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113194 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113196 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113201 */   // GIR_Coverage, 6781,
     /* 113201 */   GIR_EraseRootFromParent_Done,
     /* 113202 */ // Label 1808: @113202
     /* 113202 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(113234), // Rule ID 6782 //
     /* 113207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113210 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113217 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113221 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113224 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113226 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113228 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113233 */   // GIR_Coverage, 6782,
     /* 113233 */   GIR_EraseRootFromParent_Done,
     /* 113234 */ // Label 1809: @113234
     /* 113234 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(113266), // Rule ID 6783 //
     /* 113239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113242 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 113245 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113249 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113253 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113256 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113258 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113260 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113265 */   // GIR_Coverage, 6783,
     /* 113265 */   GIR_EraseRootFromParent_Done,
     /* 113266 */ // Label 1810: @113266
     /* 113266 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(113298), // Rule ID 6784 //
     /* 113271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113274 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113281 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113285 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113288 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113290 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113292 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113297 */   // GIR_Coverage, 6784,
     /* 113297 */   GIR_EraseRootFromParent_Done,
     /* 113298 */ // Label 1811: @113298
     /* 113298 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(113330), // Rule ID 6785 //
     /* 113303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113306 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113313 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113317 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113320 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113322 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113324 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113329 */   // GIR_Coverage, 6785,
     /* 113329 */   GIR_EraseRootFromParent_Done,
     /* 113330 */ // Label 1812: @113330
     /* 113330 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(113362), // Rule ID 6786 //
     /* 113335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113345 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113349 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113352 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113354 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113356 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113361 */   // GIR_Coverage, 6786,
     /* 113361 */   GIR_EraseRootFromParent_Done,
     /* 113362 */ // Label 1813: @113362
     /* 113362 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(113388), // Rule ID 6787 //
     /* 113367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113377 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113381 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)
     /* 113381 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113386 */   GIR_RootConstrainSelectedInstOperands,
     /* 113387 */   // GIR_Coverage, 6787,
     /* 113387 */   GIR_Done,
     /* 113388 */ // Label 1814: @113388
     /* 113388 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(113414), // Rule ID 6788 //
     /* 113393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113403 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113407 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)
     /* 113407 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 113412 */   GIR_RootConstrainSelectedInstOperands,
     /* 113413 */   // GIR_Coverage, 6788,
     /* 113413 */   GIR_Done,
     /* 113414 */ // Label 1815: @113414
     /* 113414 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(113440), // Rule ID 6789 //
     /* 113419 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113422 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 113425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113429 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113433 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)  =>  (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)
     /* 113433 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 113438 */   GIR_RootConstrainSelectedInstOperands,
     /* 113439 */   // GIR_Coverage, 6789,
     /* 113439 */   GIR_Done,
     /* 113440 */ // Label 1816: @113440
     /* 113440 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(113466), // Rule ID 6790 //
     /* 113445 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113448 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113455 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113459 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)
     /* 113459 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113464 */   GIR_RootConstrainSelectedInstOperands,
     /* 113465 */   // GIR_Coverage, 6790,
     /* 113465 */   GIR_Done,
     /* 113466 */ // Label 1817: @113466
     /* 113466 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(113492), // Rule ID 6791 //
     /* 113471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113481 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113485 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)
     /* 113485 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 113490 */   GIR_RootConstrainSelectedInstOperands,
     /* 113491 */   // GIR_Coverage, 6791,
     /* 113491 */   GIR_Done,
     /* 113492 */ // Label 1818: @113492
     /* 113492 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(113518), // Rule ID 6792 //
     /* 113497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113500 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113507 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113511 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)
     /* 113511 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113516 */   GIR_RootConstrainSelectedInstOperands,
     /* 113517 */   // GIR_Coverage, 6792,
     /* 113517 */   GIR_Done,
     /* 113518 */ // Label 1819: @113518
     /* 113518 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(113547), // Rule ID 6793 //
     /* 113523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 113526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113534 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 113534 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113537 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113539 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113541 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113546 */   // GIR_Coverage, 6793,
     /* 113546 */   GIR_EraseRootFromParent_Done,
     /* 113547 */ // Label 1820: @113547
     /* 113547 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(113579), // Rule ID 6794 //
     /* 113552 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113562 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113566 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113569 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113571 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113573 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113578 */   // GIR_Coverage, 6794,
     /* 113578 */   GIR_EraseRootFromParent_Done,
     /* 113579 */ // Label 1821: @113579
     /* 113579 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(113611), // Rule ID 6795 //
     /* 113584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113587 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113594 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113598 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113598 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113601 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113603 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113605 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113610 */   // GIR_Coverage, 6795,
     /* 113610 */   GIR_EraseRootFromParent_Done,
     /* 113611 */ // Label 1822: @113611
     /* 113611 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(113643), // Rule ID 6796 //
     /* 113616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113619 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 113622 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113626 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113630 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113633 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113635 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113637 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113642 */   // GIR_Coverage, 6796,
     /* 113642 */   GIR_EraseRootFromParent_Done,
     /* 113643 */ // Label 1823: @113643
     /* 113643 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(113675), // Rule ID 6797 //
     /* 113648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113658 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113662 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113665 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113667 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113669 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113674 */   // GIR_Coverage, 6797,
     /* 113674 */   GIR_EraseRootFromParent_Done,
     /* 113675 */ // Label 1824: @113675
     /* 113675 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(113707), // Rule ID 6798 //
     /* 113680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113683 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113686 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113690 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113694 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113697 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113699 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113701 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113706 */   // GIR_Coverage, 6798,
     /* 113706 */   GIR_EraseRootFromParent_Done,
     /* 113707 */ // Label 1825: @113707
     /* 113707 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(113739), // Rule ID 6799 //
     /* 113712 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113715 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113718 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113722 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113726 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113729 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113731 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113733 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113738 */   // GIR_Coverage, 6799,
     /* 113738 */   GIR_EraseRootFromParent_Done,
     /* 113739 */ // Label 1826: @113739
     /* 113739 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(113765), // Rule ID 6800 //
     /* 113744 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113747 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113754 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113758 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)
     /* 113758 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113763 */   GIR_RootConstrainSelectedInstOperands,
     /* 113764 */   // GIR_Coverage, 6800,
     /* 113764 */   GIR_Done,
     /* 113765 */ // Label 1827: @113765
     /* 113765 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(113791), // Rule ID 6801 //
     /* 113770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113773 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113784 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)
     /* 113784 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 113789 */   GIR_RootConstrainSelectedInstOperands,
     /* 113790 */   // GIR_Coverage, 6801,
     /* 113790 */   GIR_Done,
     /* 113791 */ // Label 1828: @113791
     /* 113791 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(113817), // Rule ID 6802 //
     /* 113796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 113802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113806 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113810 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)  =>  (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)
     /* 113810 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 113815 */   GIR_RootConstrainSelectedInstOperands,
     /* 113816 */   // GIR_Coverage, 6802,
     /* 113816 */   GIR_Done,
     /* 113817 */ // Label 1829: @113817
     /* 113817 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(113843), // Rule ID 6803 //
     /* 113822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113832 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113836 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)
     /* 113836 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113841 */   GIR_RootConstrainSelectedInstOperands,
     /* 113842 */   // GIR_Coverage, 6803,
     /* 113842 */   GIR_Done,
     /* 113843 */ // Label 1830: @113843
     /* 113843 */ GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(113869), // Rule ID 6804 //
     /* 113848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 113854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113858 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113862 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)
     /* 113862 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 113867 */   GIR_RootConstrainSelectedInstOperands,
     /* 113868 */   // GIR_Coverage, 6804,
     /* 113868 */   GIR_Done,
     /* 113869 */ // Label 1831: @113869
     /* 113869 */ GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(113895), // Rule ID 6805 //
     /* 113874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 113877 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 113880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113884 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113888 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)
     /* 113888 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 113893 */   GIR_RootConstrainSelectedInstOperands,
     /* 113894 */   // GIR_Coverage, 6805,
     /* 113894 */   GIR_Done,
     /* 113895 */ // Label 1832: @113895
     /* 113895 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(113924), // Rule ID 6806 //
     /* 113900 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 113903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113907 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113911 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 113911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113914 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113916 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113918 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113923 */   // GIR_Coverage, 6806,
     /* 113923 */   GIR_EraseRootFromParent_Done,
     /* 113924 */ // Label 1833: @113924
     /* 113924 */ GIM_Reject,
     /* 113925 */ // Label 1657: @113925
     /* 113925 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(113957), // Rule ID 6885 //
     /* 113930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113933 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 113936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113944 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 113944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113947 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113949 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113951 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113956 */   // GIR_Coverage, 6885,
     /* 113956 */   GIR_EraseRootFromParent_Done,
     /* 113957 */ // Label 1834: @113957
     /* 113957 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(113989), // Rule ID 6886 //
     /* 113962 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113965 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 113968 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113972 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113976 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 113976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 113979 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 113981 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 113983 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113988 */   // GIR_Coverage, 6886,
     /* 113988 */   GIR_EraseRootFromParent_Done,
     /* 113989 */ // Label 1835: @113989
     /* 113989 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(114021), // Rule ID 6887 //
     /* 113994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 113997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114004 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114008 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 114008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114011 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114013 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114015 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114020 */   // GIR_Coverage, 6887,
     /* 114020 */   GIR_EraseRootFromParent_Done,
     /* 114021 */ // Label 1836: @114021
     /* 114021 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(114053), // Rule ID 6888 //
     /* 114026 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114029 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 114032 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114036 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114040 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 114040 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114043 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114045 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114047 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114052 */   // GIR_Coverage, 6888,
     /* 114052 */   GIR_EraseRootFromParent_Done,
     /* 114053 */ // Label 1837: @114053
     /* 114053 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(114085), // Rule ID 6889 //
     /* 114058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114061 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114068 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114072 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 114072 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114075 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114077 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114079 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114084 */   // GIR_Coverage, 6889,
     /* 114084 */   GIR_EraseRootFromParent_Done,
     /* 114085 */ // Label 1838: @114085
     /* 114085 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(114117), // Rule ID 6890 //
     /* 114090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114100 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114104 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 114104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114107 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114109 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114111 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114116 */   // GIR_Coverage, 6890,
     /* 114116 */   GIR_EraseRootFromParent_Done,
     /* 114117 */ // Label 1839: @114117
     /* 114117 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(114188), // Rule ID 6891 //
     /* 114122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 114128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114132 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114136 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 114136 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114139 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114143 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114148 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 114152 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114154 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114157 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114161 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114166 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 114170 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 114172 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 114175 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 114177 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114180 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 114183 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 114186 */   GIR_RootConstrainSelectedInstOperands,
     /* 114187 */   // GIR_Coverage, 6891,
     /* 114187 */   GIR_EraseRootFromParent_Done,
     /* 114188 */ // Label 1840: @114188
     /* 114188 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(114214), // Rule ID 6892 //
     /* 114193 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114196 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114199 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114203 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114207 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)  =>  (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)
     /* 114207 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 114212 */   GIR_RootConstrainSelectedInstOperands,
     /* 114213 */   // GIR_Coverage, 6892,
     /* 114213 */   GIR_Done,
     /* 114214 */ // Label 1841: @114214
     /* 114214 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(114240), // Rule ID 6893 //
     /* 114219 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114222 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114229 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114233 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)  =>  (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)
     /* 114233 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 114238 */   GIR_RootConstrainSelectedInstOperands,
     /* 114239 */   // GIR_Coverage, 6893,
     /* 114239 */   GIR_Done,
     /* 114240 */ // Label 1842: @114240
     /* 114240 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(114266), // Rule ID 6894 //
     /* 114245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114248 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 114251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114255 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114259 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)  =>  (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)
     /* 114259 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 114264 */   GIR_RootConstrainSelectedInstOperands,
     /* 114265 */   // GIR_Coverage, 6894,
     /* 114265 */   GIR_Done,
     /* 114266 */ // Label 1843: @114266
     /* 114266 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(114292), // Rule ID 6895 //
     /* 114271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114274 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114281 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114285 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)
     /* 114285 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114290 */   GIR_RootConstrainSelectedInstOperands,
     /* 114291 */   // GIR_Coverage, 6895,
     /* 114291 */   GIR_Done,
     /* 114292 */ // Label 1844: @114292
     /* 114292 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(114318), // Rule ID 6896 //
     /* 114297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114300 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114307 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114311 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)
     /* 114311 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114316 */   GIR_RootConstrainSelectedInstOperands,
     /* 114317 */   // GIR_Coverage, 6896,
     /* 114317 */   GIR_Done,
     /* 114318 */ // Label 1845: @114318
     /* 114318 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(114347), // Rule ID 6897 //
     /* 114323 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114330 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114334 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 114334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114337 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114339 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114341 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114346 */   // GIR_Coverage, 6897,
     /* 114346 */   GIR_EraseRootFromParent_Done,
     /* 114347 */ // Label 1846: @114347
     /* 114347 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(114379), // Rule ID 6911 //
     /* 114352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 114358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114362 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114366 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114369 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114371 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114373 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114378 */   // GIR_Coverage, 6911,
     /* 114378 */   GIR_EraseRootFromParent_Done,
     /* 114379 */ // Label 1847: @114379
     /* 114379 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(114411), // Rule ID 6912 //
     /* 114384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114394 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114398 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114398 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114401 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114403 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114405 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114410 */   // GIR_Coverage, 6912,
     /* 114410 */   GIR_EraseRootFromParent_Done,
     /* 114411 */ // Label 1848: @114411
     /* 114411 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(114443), // Rule ID 6913 //
     /* 114416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114419 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114426 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114430 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114433 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114435 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114437 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114442 */   // GIR_Coverage, 6913,
     /* 114442 */   GIR_EraseRootFromParent_Done,
     /* 114443 */ // Label 1849: @114443
     /* 114443 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(114475), // Rule ID 6914 //
     /* 114448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 114454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114458 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114462 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114465 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114467 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114469 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114474 */   // GIR_Coverage, 6914,
     /* 114474 */   GIR_EraseRootFromParent_Done,
     /* 114475 */ // Label 1850: @114475
     /* 114475 */ GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(114507), // Rule ID 6915 //
     /* 114480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114490 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114494 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114494 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114497 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114499 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114501 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114506 */   // GIR_Coverage, 6915,
     /* 114506 */   GIR_EraseRootFromParent_Done,
     /* 114507 */ // Label 1851: @114507
     /* 114507 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(114539), // Rule ID 6916 //
     /* 114512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114515 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114522 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114526 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114526 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114529 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114531 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114533 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114538 */   // GIR_Coverage, 6916,
     /* 114538 */   GIR_EraseRootFromParent_Done,
     /* 114539 */ // Label 1852: @114539
     /* 114539 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(114610), // Rule ID 6917 //
     /* 114544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114547 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 114550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114554 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114558 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 114558 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114561 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114565 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114570 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 114574 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114576 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114579 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114583 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114588 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 114592 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 114594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 114597 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 114599 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114602 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 114605 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 114608 */   GIR_RootConstrainSelectedInstOperands,
     /* 114609 */   // GIR_Coverage, 6917,
     /* 114609 */   GIR_EraseRootFromParent_Done,
     /* 114610 */ // Label 1853: @114610
     /* 114610 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(114636), // Rule ID 6918 //
     /* 114615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114625 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114629 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)
     /* 114629 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114634 */   GIR_RootConstrainSelectedInstOperands,
     /* 114635 */   // GIR_Coverage, 6918,
     /* 114635 */   GIR_Done,
     /* 114636 */ // Label 1854: @114636
     /* 114636 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(114662), // Rule ID 6919 //
     /* 114641 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114644 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114651 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114655 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)  =>  (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)
     /* 114655 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 114660 */   GIR_RootConstrainSelectedInstOperands,
     /* 114661 */   // GIR_Coverage, 6919,
     /* 114661 */   GIR_Done,
     /* 114662 */ // Label 1855: @114662
     /* 114662 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(114688), // Rule ID 6920 //
     /* 114667 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114670 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 114673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114677 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114681 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)  =>  (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)
     /* 114681 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 114686 */   GIR_RootConstrainSelectedInstOperands,
     /* 114687 */   // GIR_Coverage, 6920,
     /* 114687 */   GIR_Done,
     /* 114688 */ // Label 1856: @114688
     /* 114688 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(114714), // Rule ID 6921 //
     /* 114693 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114696 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 114699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114703 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114707 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)
     /* 114707 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 114712 */   GIR_RootConstrainSelectedInstOperands,
     /* 114713 */   // GIR_Coverage, 6921,
     /* 114713 */   GIR_Done,
     /* 114714 */ // Label 1857: @114714
     /* 114714 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(114740), // Rule ID 6922 //
     /* 114719 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114722 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 114725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114729 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114733 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)  =>  (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)
     /* 114733 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 114738 */   GIR_RootConstrainSelectedInstOperands,
     /* 114739 */   // GIR_Coverage, 6922,
     /* 114739 */   GIR_Done,
     /* 114740 */ // Label 1858: @114740
     /* 114740 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(114769), // Rule ID 6923 //
     /* 114745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114752 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114756 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 114756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114759 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114761 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114768 */   // GIR_Coverage, 6923,
     /* 114768 */   GIR_EraseRootFromParent_Done,
     /* 114769 */ // Label 1859: @114769
     /* 114769 */ GIM_Reject,
     /* 114770 */ // Label 1658: @114770
     /* 114770 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(114844), // Rule ID 5718 //
     /* 114775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 114778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114782 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 114786 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 114790 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 114794 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 114799 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114801 */   // (bitconvert:{ *:[v8i8] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn))  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (FMOVWSr:{ *:[f32] } GPR32:{ *:[i32] }:$Rn), ssub:{ *:[i32] })
     /* 114801 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 114804 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVWSr),
     /* 114808 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114813 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 114817 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 114819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 114822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 114827 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114830 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 114833 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114838 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 114843 */   // GIR_Coverage, 5718,
     /* 114843 */   GIR_EraseRootFromParent_Done,
     /* 114844 */ // Label 1860: @114844
     /* 114844 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(114874), // Rule ID 6721 //
     /* 114849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 114855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114859 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 114863 */   // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 114863 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114868 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114873 */   // GIR_Coverage, 6721,
     /* 114873 */   GIR_Done,
     /* 114874 */ // Label 1861: @114874
     /* 114874 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(114924), // Rule ID 6732 //
     /* 114879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 114882 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 114885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114889 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 114893 */   // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 114893 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 114896 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114900 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114905 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 114909 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 114917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 114919 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114922 */   GIR_RootConstrainSelectedInstOperands,
     /* 114923 */   // GIR_Coverage, 6732,
     /* 114923 */   GIR_EraseRootFromParent_Done,
     /* 114924 */ // Label 1862: @114924
     /* 114924 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(114956), // Rule ID 6807 //
     /* 114929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114932 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 114935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114939 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114943 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 114943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114946 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114948 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114950 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114955 */   // GIR_Coverage, 6807,
     /* 114955 */   GIR_EraseRootFromParent_Done,
     /* 114956 */ // Label 1863: @114956
     /* 114956 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(114988), // Rule ID 6808 //
     /* 114961 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114964 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 114967 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114971 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114975 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 114975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 114978 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 114980 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 114982 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114987 */   // GIR_Coverage, 6808,
     /* 114987 */   GIR_EraseRootFromParent_Done,
     /* 114988 */ // Label 1864: @114988
     /* 114988 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(115020), // Rule ID 6809 //
     /* 114993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 114996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 114999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115003 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115007 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 115007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115010 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115012 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115014 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115019 */   // GIR_Coverage, 6809,
     /* 115019 */   GIR_EraseRootFromParent_Done,
     /* 115020 */ // Label 1865: @115020
     /* 115020 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(115052), // Rule ID 6810 //
     /* 115025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 115031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115035 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115039 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 115039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115042 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115044 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115046 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115051 */   // GIR_Coverage, 6810,
     /* 115051 */   GIR_EraseRootFromParent_Done,
     /* 115052 */ // Label 1866: @115052
     /* 115052 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(115084), // Rule ID 6811 //
     /* 115057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 115063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115067 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115071 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 115071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115074 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115076 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115078 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115083 */   // GIR_Coverage, 6811,
     /* 115083 */   GIR_EraseRootFromParent_Done,
     /* 115084 */ // Label 1867: @115084
     /* 115084 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(115116), // Rule ID 6812 //
     /* 115089 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115092 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 115095 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115099 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115103 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 115103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115106 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115108 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115110 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115115 */   // GIR_Coverage, 6812,
     /* 115115 */   GIR_EraseRootFromParent_Done,
     /* 115116 */ // Label 1868: @115116
     /* 115116 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(115148), // Rule ID 6813 //
     /* 115121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115124 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 115127 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115131 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115135 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 115135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115138 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115140 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115142 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115147 */   // GIR_Coverage, 6813,
     /* 115147 */   GIR_EraseRootFromParent_Done,
     /* 115148 */ // Label 1869: @115148
     /* 115148 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(115174), // Rule ID 6814 //
     /* 115153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 115159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115163 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115167 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)
     /* 115167 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 115172 */   GIR_RootConstrainSelectedInstOperands,
     /* 115173 */   // GIR_Coverage, 6814,
     /* 115173 */   GIR_Done,
     /* 115174 */ // Label 1870: @115174
     /* 115174 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(115200), // Rule ID 6815 //
     /* 115179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115182 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 115185 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115189 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115193 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)
     /* 115193 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 115198 */   GIR_RootConstrainSelectedInstOperands,
     /* 115199 */   // GIR_Coverage, 6815,
     /* 115199 */   GIR_Done,
     /* 115200 */ // Label 1871: @115200
     /* 115200 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(115226), // Rule ID 6816 //
     /* 115205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115208 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 115211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115215 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115219 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)  =>  (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)
     /* 115219 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 115224 */   GIR_RootConstrainSelectedInstOperands,
     /* 115225 */   // GIR_Coverage, 6816,
     /* 115225 */   GIR_Done,
     /* 115226 */ // Label 1872: @115226
     /* 115226 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(115252), // Rule ID 6817 //
     /* 115231 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 115237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115241 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115245 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)
     /* 115245 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 115250 */   GIR_RootConstrainSelectedInstOperands,
     /* 115251 */   // GIR_Coverage, 6817,
     /* 115251 */   GIR_Done,
     /* 115252 */ // Label 1873: @115252
     /* 115252 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(115278), // Rule ID 6818 //
     /* 115257 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115260 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 115263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115267 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115271 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)
     /* 115271 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 115276 */   GIR_RootConstrainSelectedInstOperands,
     /* 115277 */   // GIR_Coverage, 6818,
     /* 115277 */   GIR_Done,
     /* 115278 */ // Label 1874: @115278
     /* 115278 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(115304), // Rule ID 6819 //
     /* 115283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 115289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115293 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115297 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)
     /* 115297 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 115302 */   GIR_RootConstrainSelectedInstOperands,
     /* 115303 */   // GIR_Coverage, 6819,
     /* 115303 */   GIR_Done,
     /* 115304 */ // Label 1875: @115304
     /* 115304 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(115330), // Rule ID 6820 //
     /* 115309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 115315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115319 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115323 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)  =>  (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)
     /* 115323 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 115328 */   GIR_RootConstrainSelectedInstOperands,
     /* 115329 */   // GIR_Coverage, 6820,
     /* 115329 */   GIR_Done,
     /* 115330 */ // Label 1876: @115330
     /* 115330 */ GIM_Reject,
     /* 115331 */ // Label 1659: @115331
     /* 115331 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(115363), // Rule ID 6924 //
     /* 115336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 115342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115346 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115350 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115353 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115355 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115357 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115362 */   // GIR_Coverage, 6924,
     /* 115362 */   GIR_EraseRootFromParent_Done,
     /* 115363 */ // Label 1877: @115363
     /* 115363 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(115395), // Rule ID 6925 //
     /* 115368 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115382 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115385 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115387 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115389 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115394 */   // GIR_Coverage, 6925,
     /* 115394 */   GIR_EraseRootFromParent_Done,
     /* 115395 */ // Label 1878: @115395
     /* 115395 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(115427), // Rule ID 6926 //
     /* 115400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115410 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115414 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115417 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115419 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115421 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115426 */   // GIR_Coverage, 6926,
     /* 115426 */   GIR_EraseRootFromParent_Done,
     /* 115427 */ // Label 1879: @115427
     /* 115427 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(115459), // Rule ID 6927 //
     /* 115432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115435 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 115438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115442 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115446 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115446 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115449 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115451 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115453 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115458 */   // GIR_Coverage, 6927,
     /* 115458 */   GIR_EraseRootFromParent_Done,
     /* 115459 */ // Label 1880: @115459
     /* 115459 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(115491), // Rule ID 6928 //
     /* 115464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115467 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115470 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115474 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115478 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115481 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115483 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115485 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115490 */   // GIR_Coverage, 6928,
     /* 115490 */   GIR_EraseRootFromParent_Done,
     /* 115491 */ // Label 1881: @115491
     /* 115491 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(115523), // Rule ID 6929 //
     /* 115496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115506 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115510 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115513 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115515 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115517 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115522 */   // GIR_Coverage, 6929,
     /* 115522 */   GIR_EraseRootFromParent_Done,
     /* 115523 */ // Label 1882: @115523
     /* 115523 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(115594), // Rule ID 6930 //
     /* 115528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115531 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 115534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115538 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115542 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 115542 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 115545 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115549 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115554 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 115558 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 115560 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115563 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115567 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115572 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 115576 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 115578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 115581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 115583 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115586 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 115589 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 115592 */   GIR_RootConstrainSelectedInstOperands,
     /* 115593 */   // GIR_Coverage, 6930,
     /* 115593 */   GIR_EraseRootFromParent_Done,
     /* 115594 */ // Label 1883: @115594
     /* 115594 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(115620), // Rule ID 6931 //
     /* 115599 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115602 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115609 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115613 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)
     /* 115613 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115618 */   GIR_RootConstrainSelectedInstOperands,
     /* 115619 */   // GIR_Coverage, 6931,
     /* 115619 */   GIR_Done,
     /* 115620 */ // Label 1884: @115620
     /* 115620 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(115646), // Rule ID 6932 //
     /* 115625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115639 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)
     /* 115639 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 115644 */   GIR_RootConstrainSelectedInstOperands,
     /* 115645 */   // GIR_Coverage, 6932,
     /* 115645 */   GIR_Done,
     /* 115646 */ // Label 1885: @115646
     /* 115646 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(115672), // Rule ID 6933 //
     /* 115651 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115654 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 115657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115661 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115665 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)  =>  (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)
     /* 115665 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 115670 */   GIR_RootConstrainSelectedInstOperands,
     /* 115671 */   // GIR_Coverage, 6933,
     /* 115671 */   GIR_Done,
     /* 115672 */ // Label 1886: @115672
     /* 115672 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(115698), // Rule ID 6934 //
     /* 115677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115680 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115687 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115691 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)
     /* 115691 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115696 */   GIR_RootConstrainSelectedInstOperands,
     /* 115697 */   // GIR_Coverage, 6934,
     /* 115697 */   GIR_Done,
     /* 115698 */ // Label 1887: @115698
     /* 115698 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(115724), // Rule ID 6935 //
     /* 115703 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115706 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115709 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115713 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115717 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)
     /* 115717 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 115722 */   GIR_RootConstrainSelectedInstOperands,
     /* 115723 */   // GIR_Coverage, 6935,
     /* 115723 */   GIR_Done,
     /* 115724 */ // Label 1888: @115724
     /* 115724 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(115753), // Rule ID 6936 //
     /* 115729 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115736 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115740 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 115740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115743 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115745 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115747 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115752 */   // GIR_Coverage, 6936,
     /* 115752 */   GIR_EraseRootFromParent_Done,
     /* 115753 */ // Label 1889: @115753
     /* 115753 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(115785), // Rule ID 6937 //
     /* 115758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 115764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115768 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115772 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115775 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115777 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115779 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115784 */   // GIR_Coverage, 6937,
     /* 115784 */   GIR_EraseRootFromParent_Done,
     /* 115785 */ // Label 1890: @115785
     /* 115785 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(115817), // Rule ID 6938 //
     /* 115790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115793 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115800 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115804 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115807 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115809 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115811 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115816 */   // GIR_Coverage, 6938,
     /* 115816 */   GIR_EraseRootFromParent_Done,
     /* 115817 */ // Label 1891: @115817
     /* 115817 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(115849), // Rule ID 6939 //
     /* 115822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115832 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115836 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115839 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115841 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115843 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115848 */   // GIR_Coverage, 6939,
     /* 115848 */   GIR_EraseRootFromParent_Done,
     /* 115849 */ // Label 1892: @115849
     /* 115849 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(115881), // Rule ID 6940 //
     /* 115854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115857 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 115860 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115864 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115868 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115868 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115871 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115873 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115875 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115880 */   // GIR_Coverage, 6940,
     /* 115880 */   GIR_EraseRootFromParent_Done,
     /* 115881 */ // Label 1893: @115881
     /* 115881 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(115913), // Rule ID 6941 //
     /* 115886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 115892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115896 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115900 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115903 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115905 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115907 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115912 */   // GIR_Coverage, 6941,
     /* 115912 */   GIR_EraseRootFromParent_Done,
     /* 115913 */ // Label 1894: @115913
     /* 115913 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(115945), // Rule ID 6942 //
     /* 115918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 115921 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 115924 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115928 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115932 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 115932 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 115935 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 115937 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 115939 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115944 */   // GIR_Coverage, 6942,
     /* 115944 */   GIR_EraseRootFromParent_Done,
     /* 115945 */ // Label 1895: @115945
     /* 115945 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(116016), // Rule ID 6943 //
     /* 115950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 115953 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 115956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115960 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115964 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 115964 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 115967 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115971 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115976 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 115980 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 115982 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115985 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 115989 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115994 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 115998 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 116000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 116003 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 116005 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116008 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 116011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 116014 */   GIR_RootConstrainSelectedInstOperands,
     /* 116015 */   // GIR_Coverage, 6943,
     /* 116015 */   GIR_EraseRootFromParent_Done,
     /* 116016 */ // Label 1896: @116016
     /* 116016 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(116042), // Rule ID 6944 //
     /* 116021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116024 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116027 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116031 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116035 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)
     /* 116035 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 116040 */   GIR_RootConstrainSelectedInstOperands,
     /* 116041 */   // GIR_Coverage, 6944,
     /* 116041 */   GIR_Done,
     /* 116042 */ // Label 1897: @116042
     /* 116042 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(116068), // Rule ID 6945 //
     /* 116047 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116050 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116057 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116061 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)
     /* 116061 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 116066 */   GIR_RootConstrainSelectedInstOperands,
     /* 116067 */   // GIR_Coverage, 6945,
     /* 116067 */   GIR_Done,
     /* 116068 */ // Label 1898: @116068
     /* 116068 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(116094), // Rule ID 6946 //
     /* 116073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116076 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 116079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116083 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116087 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)  =>  (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)
     /* 116087 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 116092 */   GIR_RootConstrainSelectedInstOperands,
     /* 116093 */   // GIR_Coverage, 6946,
     /* 116093 */   GIR_Done,
     /* 116094 */ // Label 1899: @116094
     /* 116094 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(116120), // Rule ID 6947 //
     /* 116099 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116102 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116105 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116109 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116113 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)
     /* 116113 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 116118 */   GIR_RootConstrainSelectedInstOperands,
     /* 116119 */   // GIR_Coverage, 6947,
     /* 116119 */   GIR_Done,
     /* 116120 */ // Label 1900: @116120
     /* 116120 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(116146), // Rule ID 6948 //
     /* 116125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116135 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116139 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)
     /* 116139 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 116144 */   GIR_RootConstrainSelectedInstOperands,
     /* 116145 */   // GIR_Coverage, 6948,
     /* 116145 */   GIR_Done,
     /* 116146 */ // Label 1901: @116146
     /* 116146 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(116175), // Rule ID 6949 //
     /* 116151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116162 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 116162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116165 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116167 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116169 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116174 */   // GIR_Coverage, 6949,
     /* 116174 */   GIR_EraseRootFromParent_Done,
     /* 116175 */ // Label 1902: @116175
     /* 116175 */ GIM_Reject,
     /* 116176 */ // Label 1660: @116176
     /* 116176 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(116208), // Rule ID 6950 //
     /* 116181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116184 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 116187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116191 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116195 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116198 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116200 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116202 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116207 */   // GIR_Coverage, 6950,
     /* 116207 */   GIR_EraseRootFromParent_Done,
     /* 116208 */ // Label 1903: @116208
     /* 116208 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(116240), // Rule ID 6951 //
     /* 116213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116216 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116223 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116227 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116227 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116230 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116232 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116234 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116239 */   // GIR_Coverage, 6951,
     /* 116239 */   GIR_EraseRootFromParent_Done,
     /* 116240 */ // Label 1904: @116240
     /* 116240 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(116272), // Rule ID 6952 //
     /* 116245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116248 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116255 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116259 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116262 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116264 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116266 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116271 */   // GIR_Coverage, 6952,
     /* 116271 */   GIR_EraseRootFromParent_Done,
     /* 116272 */ // Label 1905: @116272
     /* 116272 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(116304), // Rule ID 6953 //
     /* 116277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116287 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116291 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116294 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116296 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116298 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116303 */   // GIR_Coverage, 6953,
     /* 116303 */   GIR_EraseRootFromParent_Done,
     /* 116304 */ // Label 1906: @116304
     /* 116304 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(116336), // Rule ID 6954 //
     /* 116309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116319 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116323 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116323 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116326 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116328 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116330 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116335 */   // GIR_Coverage, 6954,
     /* 116335 */   GIR_EraseRootFromParent_Done,
     /* 116336 */ // Label 1907: @116336
     /* 116336 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(116368), // Rule ID 6955 //
     /* 116341 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116344 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116351 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116355 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116358 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116360 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116362 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116367 */   // GIR_Coverage, 6955,
     /* 116367 */   GIR_EraseRootFromParent_Done,
     /* 116368 */ // Label 1908: @116368
     /* 116368 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(116400), // Rule ID 6956 //
     /* 116373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 116376 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116383 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116387 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 116387 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116390 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116392 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116394 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116399 */   // GIR_Coverage, 6956,
     /* 116399 */   GIR_EraseRootFromParent_Done,
     /* 116400 */ // Label 1909: @116400
     /* 116400 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(116471), // Rule ID 6957 //
     /* 116405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116408 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 116411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116415 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116419 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 116419 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116422 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 116426 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116431 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 116435 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116437 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116440 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 116444 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116449 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 116453 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 116455 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 116458 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 116460 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116463 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 116466 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 116469 */   GIR_RootConstrainSelectedInstOperands,
     /* 116470 */   // GIR_Coverage, 6957,
     /* 116470 */   GIR_EraseRootFromParent_Done,
     /* 116471 */ // Label 1910: @116471
     /* 116471 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(116497), // Rule ID 6958 //
     /* 116476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116486 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116490 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)
     /* 116490 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 116495 */   GIR_RootConstrainSelectedInstOperands,
     /* 116496 */   // GIR_Coverage, 6958,
     /* 116496 */   GIR_Done,
     /* 116497 */ // Label 1911: @116497
     /* 116497 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(116523), // Rule ID 6959 //
     /* 116502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116505 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116512 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116516 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)
     /* 116516 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 116521 */   GIR_RootConstrainSelectedInstOperands,
     /* 116522 */   // GIR_Coverage, 6959,
     /* 116522 */   GIR_Done,
     /* 116523 */ // Label 1912: @116523
     /* 116523 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(116549), // Rule ID 6960 //
     /* 116528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116531 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116538 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116542 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)  =>  (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)
     /* 116542 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 116547 */   GIR_RootConstrainSelectedInstOperands,
     /* 116548 */   // GIR_Coverage, 6960,
     /* 116548 */   GIR_Done,
     /* 116549 */ // Label 1913: @116549
     /* 116549 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(116575), // Rule ID 6961 //
     /* 116554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116557 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 116560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116564 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116568 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)
     /* 116568 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 116573 */   GIR_RootConstrainSelectedInstOperands,
     /* 116574 */   // GIR_Coverage, 6961,
     /* 116574 */   GIR_Done,
     /* 116575 */ // Label 1914: @116575
     /* 116575 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(116601), // Rule ID 6962 //
     /* 116580 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 116586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116590 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116594 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)
     /* 116594 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 116599 */   GIR_RootConstrainSelectedInstOperands,
     /* 116600 */   // GIR_Coverage, 6962,
     /* 116600 */   GIR_Done,
     /* 116601 */ // Label 1915: @116601
     /* 116601 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(116627), // Rule ID 6963 //
     /* 116606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 116609 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116612 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116616 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116620 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)  =>  (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)
     /* 116620 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 116625 */   GIR_RootConstrainSelectedInstOperands,
     /* 116626 */   // GIR_Coverage, 6963,
     /* 116626 */   GIR_Done,
     /* 116627 */ // Label 1916: @116627
     /* 116627 */ GIM_Reject,
     /* 116628 */ // Label 1661: @116628
     /* 116628 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(116660), // Rule ID 10697 //
     /* 116633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116636 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 116639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116643 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116647 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116650 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116652 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116654 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116659 */   // GIR_Coverage, 10697,
     /* 116659 */   GIR_EraseRootFromParent_Done,
     /* 116660 */ // Label 1917: @116660
     /* 116660 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(116692), // Rule ID 10698 //
     /* 116665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116668 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 116671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116675 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116679 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116682 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116684 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116686 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116691 */   // GIR_Coverage, 10698,
     /* 116691 */   GIR_EraseRootFromParent_Done,
     /* 116692 */ // Label 1918: @116692
     /* 116692 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(116724), // Rule ID 10699 //
     /* 116697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 116703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116707 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116711 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116711 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116714 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116716 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116718 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116723 */   // GIR_Coverage, 10699,
     /* 116723 */   GIR_EraseRootFromParent_Done,
     /* 116724 */ // Label 1919: @116724
     /* 116724 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(116756), // Rule ID 10700 //
     /* 116729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116732 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 116735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116739 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116743 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116746 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116748 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116750 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116755 */   // GIR_Coverage, 10700,
     /* 116755 */   GIR_EraseRootFromParent_Done,
     /* 116756 */ // Label 1920: @116756
     /* 116756 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(116788), // Rule ID 10701 //
     /* 116761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116764 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 116767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116771 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116775 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116778 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116780 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116782 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116787 */   // GIR_Coverage, 10701,
     /* 116787 */   GIR_EraseRootFromParent_Done,
     /* 116788 */ // Label 1921: @116788
     /* 116788 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(116820), // Rule ID 10702 //
     /* 116793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116796 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 116799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116803 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116807 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 116807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116810 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116812 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116814 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116819 */   // GIR_Coverage, 10702,
     /* 116819 */   GIR_EraseRootFromParent_Done,
     /* 116820 */ // Label 1922: @116820
     /* 116820 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(116852), // Rule ID 10715 //
     /* 116825 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116828 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 116831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116835 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116839 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116839 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116842 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116844 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116846 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116851 */   // GIR_Coverage, 10715,
     /* 116851 */   GIR_EraseRootFromParent_Done,
     /* 116852 */ // Label 1923: @116852
     /* 116852 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(116884), // Rule ID 10716 //
     /* 116857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 116863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116871 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116871 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116874 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116876 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116878 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116883 */   // GIR_Coverage, 10716,
     /* 116883 */   GIR_EraseRootFromParent_Done,
     /* 116884 */ // Label 1924: @116884
     /* 116884 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(116916), // Rule ID 10717 //
     /* 116889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116892 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 116895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116899 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116903 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116906 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116908 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116910 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116915 */   // GIR_Coverage, 10717,
     /* 116915 */   GIR_EraseRootFromParent_Done,
     /* 116916 */ // Label 1925: @116916
     /* 116916 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(116948), // Rule ID 10718 //
     /* 116921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116924 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 116927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116931 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116935 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116935 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116938 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116940 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116942 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116947 */   // GIR_Coverage, 10718,
     /* 116947 */   GIR_EraseRootFromParent_Done,
     /* 116948 */ // Label 1926: @116948
     /* 116948 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(116980), // Rule ID 10719 //
     /* 116953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 116959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116963 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116967 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 116970 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 116972 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 116974 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116979 */   // GIR_Coverage, 10719,
     /* 116979 */   GIR_EraseRootFromParent_Done,
     /* 116980 */ // Label 1927: @116980
     /* 116980 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(117012), // Rule ID 10720 //
     /* 116985 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 116988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 116991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116995 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 116999 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 116999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117002 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117004 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117011 */   // GIR_Coverage, 10720,
     /* 117011 */   GIR_EraseRootFromParent_Done,
     /* 117012 */ // Label 1928: @117012
     /* 117012 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(117044), // Rule ID 10725 //
     /* 117017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117027 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117031 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 117031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117034 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117036 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117038 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117043 */   // GIR_Coverage, 10725,
     /* 117043 */   GIR_EraseRootFromParent_Done,
     /* 117044 */ // Label 1929: @117044
     /* 117044 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(117076), // Rule ID 10726 //
     /* 117049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117059 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117063 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 117063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117066 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117068 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117070 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117075 */   // GIR_Coverage, 10726,
     /* 117075 */   GIR_EraseRootFromParent_Done,
     /* 117076 */ // Label 1930: @117076
     /* 117076 */ GIM_Reject,
     /* 117077 */ // Label 1662: @117077
     /* 117077 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(117109), // Rule ID 10691 //
     /* 117082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117085 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 117088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117092 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117096 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117099 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117101 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117103 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117108 */   // GIR_Coverage, 10691,
     /* 117108 */   GIR_EraseRootFromParent_Done,
     /* 117109 */ // Label 1931: @117109
     /* 117109 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(117141), // Rule ID 10692 //
     /* 117114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117117 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117124 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117128 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117131 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117133 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117135 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117140 */   // GIR_Coverage, 10692,
     /* 117140 */   GIR_EraseRootFromParent_Done,
     /* 117141 */ // Label 1932: @117141
     /* 117141 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(117173), // Rule ID 10693 //
     /* 117146 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117149 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117156 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117160 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117163 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117165 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117167 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117172 */   // GIR_Coverage, 10693,
     /* 117172 */   GIR_EraseRootFromParent_Done,
     /* 117173 */ // Label 1933: @117173
     /* 117173 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(117205), // Rule ID 10694 //
     /* 117178 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117181 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117188 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117192 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117195 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117197 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117199 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117204 */   // GIR_Coverage, 10694,
     /* 117204 */   GIR_EraseRootFromParent_Done,
     /* 117205 */ // Label 1934: @117205
     /* 117205 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(117237), // Rule ID 10695 //
     /* 117210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117213 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117220 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117224 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117227 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117229 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117231 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117236 */   // GIR_Coverage, 10695,
     /* 117236 */   GIR_EraseRootFromParent_Done,
     /* 117237 */ // Label 1935: @117237
     /* 117237 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(117269), // Rule ID 10696 //
     /* 117242 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117245 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117252 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117256 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117259 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117261 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117263 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117268 */   // GIR_Coverage, 10696,
     /* 117268 */   GIR_EraseRootFromParent_Done,
     /* 117269 */ // Label 1936: @117269
     /* 117269 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(117301), // Rule ID 10709 //
     /* 117274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 117280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117284 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117288 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117291 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117293 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117295 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117300 */   // GIR_Coverage, 10709,
     /* 117300 */   GIR_EraseRootFromParent_Done,
     /* 117301 */ // Label 1937: @117301
     /* 117301 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(117333), // Rule ID 10710 //
     /* 117306 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117309 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117316 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117320 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117323 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117325 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117327 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117332 */   // GIR_Coverage, 10710,
     /* 117332 */   GIR_EraseRootFromParent_Done,
     /* 117333 */ // Label 1938: @117333
     /* 117333 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(117365), // Rule ID 10711 //
     /* 117338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117341 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117348 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117352 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117352 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117355 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117357 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117359 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117364 */   // GIR_Coverage, 10711,
     /* 117364 */   GIR_EraseRootFromParent_Done,
     /* 117365 */ // Label 1939: @117365
     /* 117365 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(117397), // Rule ID 10712 //
     /* 117370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117373 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117376 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117380 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117384 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117387 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117389 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117391 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117396 */   // GIR_Coverage, 10712,
     /* 117396 */   GIR_EraseRootFromParent_Done,
     /* 117397 */ // Label 1940: @117397
     /* 117397 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(117429), // Rule ID 10713 //
     /* 117402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117405 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117412 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117416 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117419 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117421 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117423 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117428 */   // GIR_Coverage, 10713,
     /* 117428 */   GIR_EraseRootFromParent_Done,
     /* 117429 */ // Label 1941: @117429
     /* 117429 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(117461), // Rule ID 10714 //
     /* 117434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117444 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117448 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117451 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117453 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117455 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117460 */   // GIR_Coverage, 10714,
     /* 117460 */   GIR_EraseRootFromParent_Done,
     /* 117461 */ // Label 1942: @117461
     /* 117461 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(117493), // Rule ID 10723 //
     /* 117466 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117476 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117480 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 117480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117483 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117485 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117487 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117492 */   // GIR_Coverage, 10723,
     /* 117492 */   GIR_EraseRootFromParent_Done,
     /* 117493 */ // Label 1943: @117493
     /* 117493 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(117525), // Rule ID 10724 //
     /* 117498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117501 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117508 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117512 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 117512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117515 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117517 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117519 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117524 */   // GIR_Coverage, 10724,
     /* 117524 */   GIR_EraseRootFromParent_Done,
     /* 117525 */ // Label 1944: @117525
     /* 117525 */ GIM_Reject,
     /* 117526 */ // Label 1663: @117526
     /* 117526 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(117558), // Rule ID 10685 //
     /* 117531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117534 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 117537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117541 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117545 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117548 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117550 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117552 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117557 */   // GIR_Coverage, 10685,
     /* 117557 */   GIR_EraseRootFromParent_Done,
     /* 117558 */ // Label 1945: @117558
     /* 117558 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(117590), // Rule ID 10686 //
     /* 117563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117573 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117577 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117580 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117582 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117584 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117589 */   // GIR_Coverage, 10686,
     /* 117589 */   GIR_EraseRootFromParent_Done,
     /* 117590 */ // Label 1946: @117590
     /* 117590 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(117622), // Rule ID 10687 //
     /* 117595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117605 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117609 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117612 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117614 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117616 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117621 */   // GIR_Coverage, 10687,
     /* 117621 */   GIR_EraseRootFromParent_Done,
     /* 117622 */ // Label 1947: @117622
     /* 117622 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(117654), // Rule ID 10688 //
     /* 117627 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117630 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117637 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117641 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117644 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117646 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117648 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117653 */   // GIR_Coverage, 10688,
     /* 117653 */   GIR_EraseRootFromParent_Done,
     /* 117654 */ // Label 1948: @117654
     /* 117654 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(117686), // Rule ID 10689 //
     /* 117659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117662 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117669 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117673 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117673 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117676 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117678 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117680 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117685 */   // GIR_Coverage, 10689,
     /* 117685 */   GIR_EraseRootFromParent_Done,
     /* 117686 */ // Label 1949: @117686
     /* 117686 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(117718), // Rule ID 10690 //
     /* 117691 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117694 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117701 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117705 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117708 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117710 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117712 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117717 */   // GIR_Coverage, 10690,
     /* 117717 */   GIR_EraseRootFromParent_Done,
     /* 117718 */ // Label 1950: @117718
     /* 117718 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(117750), // Rule ID 10703 //
     /* 117723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 117729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117733 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117737 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117737 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117740 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117742 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117744 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117749 */   // GIR_Coverage, 10703,
     /* 117749 */   GIR_EraseRootFromParent_Done,
     /* 117750 */ // Label 1951: @117750
     /* 117750 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(117782), // Rule ID 10704 //
     /* 117755 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117758 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117765 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117769 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117772 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117774 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117776 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117781 */   // GIR_Coverage, 10704,
     /* 117781 */   GIR_EraseRootFromParent_Done,
     /* 117782 */ // Label 1952: @117782
     /* 117782 */ GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(117814), // Rule ID 10705 //
     /* 117787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117790 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117797 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117801 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117804 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117806 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117808 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117813 */   // GIR_Coverage, 10705,
     /* 117813 */   GIR_EraseRootFromParent_Done,
     /* 117814 */ // Label 1953: @117814
     /* 117814 */ GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(117846), // Rule ID 10706 //
     /* 117819 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117822 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117825 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117829 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117833 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117836 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117838 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117840 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117845 */   // GIR_Coverage, 10706,
     /* 117845 */   GIR_EraseRootFromParent_Done,
     /* 117846 */ // Label 1954: @117846
     /* 117846 */ GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(117878), // Rule ID 10707 //
     /* 117851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117854 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 117857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117865 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117865 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117868 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117870 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117872 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117877 */   // GIR_Coverage, 10707,
     /* 117877 */   GIR_EraseRootFromParent_Done,
     /* 117878 */ // Label 1955: @117878
     /* 117878 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(117910), // Rule ID 10708 //
     /* 117883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117886 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 117889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117893 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117897 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117897 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117900 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117902 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117904 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117909 */   // GIR_Coverage, 10708,
     /* 117909 */   GIR_EraseRootFromParent_Done,
     /* 117910 */ // Label 1956: @117910
     /* 117910 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(117942), // Rule ID 10721 //
     /* 117915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117918 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117925 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117929 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 117929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117932 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117934 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117936 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117941 */   // GIR_Coverage, 10721,
     /* 117941 */   GIR_EraseRootFromParent_Done,
     /* 117942 */ // Label 1957: @117942
     /* 117942 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(117974), // Rule ID 10722 //
     /* 117947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 117950 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117953 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117957 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117961 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 117961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117964 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117966 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 117968 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117973 */   // GIR_Coverage, 10722,
     /* 117973 */   GIR_EraseRootFromParent_Done,
     /* 117974 */ // Label 1958: @117974
     /* 117974 */ GIM_Reject,
     /* 117975 */ // Label 1664: @117975
     /* 117975 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(118007), // Rule ID 10679 //
     /* 117980 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 117983 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 117986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117990 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 117994 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 117994 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 117997 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 117999 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118001 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118006 */   // GIR_Coverage, 10679,
     /* 118006 */   GIR_EraseRootFromParent_Done,
     /* 118007 */ // Label 1959: @118007
     /* 118007 */ GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(118039), // Rule ID 10680 //
     /* 118012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 118015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 118018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118026 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 118026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118029 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 118031 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118033 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118038 */   // GIR_Coverage, 10680,
     /* 118038 */   GIR_EraseRootFromParent_Done,
     /* 118039 */ // Label 1960: @118039
     /* 118039 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(118071), // Rule ID 10681 //
     /* 118044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 118047 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 118050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118054 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118058 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 118058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118061 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 118063 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118065 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118070 */   // GIR_Coverage, 10681,
     /* 118070 */   GIR_EraseRootFromParent_Done,
     /* 118071 */ // Label 1961: @118071
     /* 118071 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(118103), // Rule ID 10682 //
     /* 118076 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 118079 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 118082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118086 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118090 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 118090 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118093 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 118095 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118097 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118102 */   // GIR_Coverage, 10682,
     /* 118102 */   GIR_EraseRootFromParent_Done,
     /* 118103 */ // Label 1962: @118103
     /* 118103 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(118135), // Rule ID 10683 //
     /* 118108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 118111 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 118114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118118 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118122 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 118122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118125 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 118127 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118129 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118134 */   // GIR_Coverage, 10683,
     /* 118134 */   GIR_EraseRootFromParent_Done,
     /* 118135 */ // Label 1963: @118135
     /* 118135 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(118167), // Rule ID 10684 //
     /* 118140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 118143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 118146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118150 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118154 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 118154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118157 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 118159 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 118161 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118166 */   // GIR_Coverage, 10684,
     /* 118166 */   GIR_EraseRootFromParent_Done,
     /* 118167 */ // Label 1964: @118167
     /* 118167 */ GIM_Reject,
     /* 118168 */ // Label 1665: @118168
     /* 118168 */ GIM_Reject,
     /* 118169 */ // Label 10: @118169
     /* 118169 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 1973*/ GIMT_Encode4(118659),
     /* 118180 */ /*GILLT_s16*//*Label 1965*/ GIMT_Encode4(118220),
     /* 118184 */ /*GILLT_s32*//*Label 1966*/ GIMT_Encode4(118251),
     /* 118188 */ /*GILLT_s64*//*Label 1967*/ GIMT_Encode4(118282), GIMT_Encode4(0),
     /* 118196 */ /*GILLT_v2s32*//*Label 1968*/ GIMT_Encode4(118313),
     /* 118200 */ /*GILLT_v2s64*//*Label 1969*/ GIMT_Encode4(118344),
     /* 118204 */ /*GILLT_v4s16*//*Label 1970*/ GIMT_Encode4(118375),
     /* 118208 */ /*GILLT_v4s32*//*Label 1971*/ GIMT_Encode4(118406), GIMT_Encode4(0),
     /* 118216 */ /*GILLT_v8s16*//*Label 1972*/ GIMT_Encode4(118437),
     /* 118220 */ // Label 1965: @118220
     /* 118220 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(118250), // Rule ID 568 //
     /* 118225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 118228 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 118231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 118235 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 118239 */   // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 118239 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZHr),
     /* 118244 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118248 */   GIR_RootConstrainSelectedInstOperands,
     /* 118249 */   // GIR_Coverage, 568,
     /* 118249 */   GIR_Done,
     /* 118250 */ // Label 1974: @118250
     /* 118250 */ GIM_Reject,
     /* 118251 */ // Label 1966: @118251
     /* 118251 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(118281), // Rule ID 570 //
     /* 118256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 118259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 118262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118266 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118270 */   // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 118270 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZSr),
     /* 118275 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118279 */   GIR_RootConstrainSelectedInstOperands,
     /* 118280 */   // GIR_Coverage, 570,
     /* 118280 */   GIR_Done,
     /* 118281 */ // Label 1975: @118281
     /* 118281 */ GIM_Reject,
     /* 118282 */ // Label 1967: @118282
     /* 118282 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(118312), // Rule ID 572 //
     /* 118287 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 118290 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 118293 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118297 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118301 */   // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 118301 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZDr),
     /* 118306 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118310 */   GIR_RootConstrainSelectedInstOperands,
     /* 118311 */   // GIR_Coverage, 572,
     /* 118311 */   GIR_Done,
     /* 118312 */ // Label 1976: @118312
     /* 118312 */ GIM_Reject,
     /* 118313 */ // Label 1968: @118313
     /* 118313 */ GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(118343), // Rule ID 937 //
     /* 118318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118321 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 118324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118328 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118332 */   // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 118332 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f32),
     /* 118337 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118341 */   GIR_RootConstrainSelectedInstOperands,
     /* 118342 */   // GIR_Coverage, 937,
     /* 118342 */   GIR_Done,
     /* 118343 */ // Label 1977: @118343
     /* 118343 */ GIM_Reject,
     /* 118344 */ // Label 1969: @118344
     /* 118344 */ GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(118374), // Rule ID 941 //
     /* 118349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118352 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 118355 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118359 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118363 */   // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 118363 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f64),
     /* 118368 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118372 */   GIR_RootConstrainSelectedInstOperands,
     /* 118373 */   // GIR_Coverage, 941,
     /* 118373 */   GIR_Done,
     /* 118374 */ // Label 1978: @118374
     /* 118374 */ GIM_Reject,
     /* 118375 */ // Label 1970: @118375
     /* 118375 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(118405), // Rule ID 933 //
     /* 118380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 118383 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 118386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118390 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118394 */   // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 118394 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f16),
     /* 118399 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118403 */   GIR_RootConstrainSelectedInstOperands,
     /* 118404 */   // GIR_Coverage, 933,
     /* 118404 */   GIR_Done,
     /* 118405 */ // Label 1979: @118405
     /* 118405 */ GIM_Reject,
     /* 118406 */ // Label 1971: @118406
     /* 118406 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(118436), // Rule ID 939 //
     /* 118411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118414 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 118417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118421 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118425 */   // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 118425 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 118430 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118434 */   GIR_RootConstrainSelectedInstOperands,
     /* 118435 */   // GIR_Coverage, 939,
     /* 118435 */   GIR_Done,
     /* 118436 */ // Label 1980: @118436
     /* 118436 */ GIM_Reject,
     /* 118437 */ // Label 1972: @118437
     /* 118437 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(118658),
     /* 118442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 118445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118449 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118453 */   GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(118472), // Rule ID 935 //
     /* 118458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 118461 */     // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 118461 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv8f16),
     /* 118466 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118470 */     GIR_RootConstrainSelectedInstOperands,
     /* 118471 */     // GIR_Coverage, 935,
     /* 118471 */     GIR_Done,
     /* 118472 */   // Label 1982: @118472
     /* 118472 */   GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(118657), // Rule ID 7088 //
     /* 118477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 118480 */     // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTZv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTZv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 118480 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 118483 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 118487 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118492 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 118496 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 118498 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 118501 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 118505 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118510 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 118513 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 118515 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 118518 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 118522 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118527 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 118533 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118538 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118543 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 118546 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 118550 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118555 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 118558 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 118560 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 118563 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 118567 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118572 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 118575 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 118577 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 118580 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 118584 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118589 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 118592 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 118594 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 118597 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118601 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118606 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 118608 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 118611 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118615 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118620 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 118623 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 118626 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 118629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118634 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118639 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 118647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118649 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118652 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 118655 */     GIR_RootConstrainSelectedInstOperands,
     /* 118656 */     // GIR_Coverage, 7088,
     /* 118656 */     GIR_EraseRootFromParent_Done,
     /* 118657 */   // Label 1983: @118657
     /* 118657 */   GIM_Reject,
     /* 118658 */ // Label 1981: @118658
     /* 118658 */ GIM_Reject,
     /* 118659 */ // Label 1973: @118659
     /* 118659 */ GIM_Reject,
     /* 118660 */ // Label 11: @118660
     /* 118660 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 1992*/ GIMT_Encode4(119150),
     /* 118671 */ /*GILLT_s16*//*Label 1984*/ GIMT_Encode4(118711),
     /* 118675 */ /*GILLT_s32*//*Label 1985*/ GIMT_Encode4(118742),
     /* 118679 */ /*GILLT_s64*//*Label 1986*/ GIMT_Encode4(118773), GIMT_Encode4(0),
     /* 118687 */ /*GILLT_v2s32*//*Label 1987*/ GIMT_Encode4(118804),
     /* 118691 */ /*GILLT_v2s64*//*Label 1988*/ GIMT_Encode4(118835),
     /* 118695 */ /*GILLT_v4s16*//*Label 1989*/ GIMT_Encode4(118866),
     /* 118699 */ /*GILLT_v4s32*//*Label 1990*/ GIMT_Encode4(118897), GIMT_Encode4(0),
     /* 118707 */ /*GILLT_v8s16*//*Label 1991*/ GIMT_Encode4(118928),
     /* 118711 */ // Label 1984: @118711
     /* 118711 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(118741), // Rule ID 532 //
     /* 118716 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 118719 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 118722 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 118726 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 118730 */   // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 118730 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAHr),
     /* 118735 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118739 */   GIR_RootConstrainSelectedInstOperands,
     /* 118740 */   // GIR_Coverage, 532,
     /* 118740 */   GIR_Done,
     /* 118741 */ // Label 1993: @118741
     /* 118741 */ GIM_Reject,
     /* 118742 */ // Label 1985: @118742
     /* 118742 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(118772), // Rule ID 534 //
     /* 118747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 118750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 118753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118757 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118761 */   // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 118761 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTASr),
     /* 118766 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118770 */   GIR_RootConstrainSelectedInstOperands,
     /* 118771 */   // GIR_Coverage, 534,
     /* 118771 */   GIR_Done,
     /* 118772 */ // Label 1994: @118772
     /* 118772 */ GIM_Reject,
     /* 118773 */ // Label 1986: @118773
     /* 118773 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(118803), // Rule ID 536 //
     /* 118778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 118781 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 118784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118788 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118792 */   // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 118792 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTADr),
     /* 118797 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118801 */   GIR_RootConstrainSelectedInstOperands,
     /* 118802 */   // GIR_Coverage, 536,
     /* 118802 */   GIR_Done,
     /* 118803 */ // Label 1995: @118803
     /* 118803 */ GIM_Reject,
     /* 118804 */ // Label 1987: @118804
     /* 118804 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(118834), // Rule ID 877 //
     /* 118809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118812 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 118815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118819 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118823 */   // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 118823 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f32),
     /* 118828 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118832 */   GIR_RootConstrainSelectedInstOperands,
     /* 118833 */   // GIR_Coverage, 877,
     /* 118833 */   GIR_Done,
     /* 118834 */ // Label 1996: @118834
     /* 118834 */ GIM_Reject,
     /* 118835 */ // Label 1988: @118835
     /* 118835 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(118865), // Rule ID 881 //
     /* 118840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118843 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 118846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118850 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118854 */   // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 118854 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f64),
     /* 118859 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118863 */   GIR_RootConstrainSelectedInstOperands,
     /* 118864 */   // GIR_Coverage, 881,
     /* 118864 */   GIR_Done,
     /* 118865 */ // Label 1997: @118865
     /* 118865 */ GIM_Reject,
     /* 118866 */ // Label 1989: @118866
     /* 118866 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(118896), // Rule ID 873 //
     /* 118871 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 118874 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 118877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118881 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118885 */   // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 118885 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f16),
     /* 118890 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118894 */   GIR_RootConstrainSelectedInstOperands,
     /* 118895 */   // GIR_Coverage, 873,
     /* 118895 */   GIR_Done,
     /* 118896 */ // Label 1998: @118896
     /* 118896 */ GIM_Reject,
     /* 118897 */ // Label 1990: @118897
     /* 118897 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(118927), // Rule ID 879 //
     /* 118902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 118908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118912 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118916 */   // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 118916 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 118921 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118925 */   GIR_RootConstrainSelectedInstOperands,
     /* 118926 */   // GIR_Coverage, 879,
     /* 118926 */   GIR_Done,
     /* 118927 */ // Label 1999: @118927
     /* 118927 */ GIM_Reject,
     /* 118928 */ // Label 1991: @118928
     /* 118928 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(119149),
     /* 118933 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 118936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118944 */   GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(118963), // Rule ID 875 //
     /* 118949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 118952 */     // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 118952 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv8f16),
     /* 118957 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 118961 */     GIR_RootConstrainSelectedInstOperands,
     /* 118962 */     // GIR_Coverage, 875,
     /* 118962 */     GIR_Done,
     /* 118963 */   // Label 2001: @118963
     /* 118963 */   GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(119148), // Rule ID 7082 //
     /* 118968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 118971 */     // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTAv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTAv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 118971 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 118974 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 118978 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118983 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 118987 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 118989 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 118992 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 118996 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119001 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 119004 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 119006 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 119009 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 119013 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119018 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 119024 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119029 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119034 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 119037 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 119041 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119046 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 119049 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 119051 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 119054 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 119058 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119063 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 119066 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 119068 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 119071 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 119075 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119080 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 119083 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 119085 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 119088 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 119092 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 119099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 119102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 119106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119111 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 119114 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 119117 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 119120 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119125 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119130 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 119138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119140 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119143 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 119146 */     GIR_RootConstrainSelectedInstOperands,
     /* 119147 */     // GIR_Coverage, 7082,
     /* 119147 */     GIR_EraseRootFromParent_Done,
     /* 119148 */   // Label 2002: @119148
     /* 119148 */   GIM_Reject,
     /* 119149 */ // Label 2000: @119149
     /* 119149 */ GIM_Reject,
     /* 119150 */ // Label 1992: @119150
     /* 119150 */ GIM_Reject,
     /* 119151 */ // Label 12: @119151
     /* 119151 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2005*/ GIMT_Encode4(119418),
     /* 119162 */ /*GILLT_s32*//*Label 2003*/ GIMT_Encode4(119170),
     /* 119166 */ /*GILLT_s64*//*Label 2004*/ GIMT_Encode4(119294),
     /* 119170 */ // Label 2003: @119170
     /* 119170 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(119213), // Rule ID 4854 //
     /* 119175 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 119178 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 119181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 119185 */   // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 119185 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119188 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 119192 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119197 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119201 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 119206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119208 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119211 */   GIR_RootConstrainSelectedInstOperands,
     /* 119212 */   // GIR_Coverage, 4854,
     /* 119212 */   GIR_EraseRootFromParent_Done,
     /* 119213 */ // Label 2006: @119213
     /* 119213 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(119253), // Rule ID 4860 //
     /* 119218 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 119221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 119225 */   // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 119225 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 119228 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 119232 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119237 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119241 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 119246 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119248 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119251 */   GIR_RootConstrainSelectedInstOperands,
     /* 119252 */   // GIR_Coverage, 4860,
     /* 119252 */   GIR_EraseRootFromParent_Done,
     /* 119253 */ // Label 2007: @119253
     /* 119253 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(119293), // Rule ID 4862 //
     /* 119258 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 119261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 119265 */   // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 119265 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 119268 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 119272 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119277 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119281 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119283 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 119286 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119288 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119291 */   GIR_RootConstrainSelectedInstOperands,
     /* 119292 */   // GIR_Coverage, 4862,
     /* 119292 */   GIR_EraseRootFromParent_Done,
     /* 119293 */ // Label 2008: @119293
     /* 119293 */ GIM_Reject,
     /* 119294 */ // Label 2004: @119294
     /* 119294 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(119337), // Rule ID 4856 //
     /* 119299 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 119302 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 119305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119309 */   // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 119309 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119312 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 119316 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119321 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119325 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119327 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 119330 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119332 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119335 */   GIR_RootConstrainSelectedInstOperands,
     /* 119336 */   // GIR_Coverage, 4856,
     /* 119336 */   GIR_EraseRootFromParent_Done,
     /* 119337 */ // Label 2009: @119337
     /* 119337 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(119377), // Rule ID 4864 //
     /* 119342 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 119345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119349 */   // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 119349 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 119352 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 119356 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119361 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119365 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119367 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 119370 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119372 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119375 */   GIR_RootConstrainSelectedInstOperands,
     /* 119376 */   // GIR_Coverage, 4864,
     /* 119376 */   GIR_EraseRootFromParent_Done,
     /* 119377 */ // Label 2010: @119377
     /* 119377 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(119417), // Rule ID 4866 //
     /* 119382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 119385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119389 */   // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 119389 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 119392 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 119396 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119401 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119405 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 119410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119412 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119415 */   GIR_RootConstrainSelectedInstOperands,
     /* 119416 */   // GIR_Coverage, 4866,
     /* 119416 */   GIR_EraseRootFromParent_Done,
     /* 119417 */ // Label 2011: @119417
     /* 119417 */ GIM_Reject,
     /* 119418 */ // Label 2005: @119418
     /* 119418 */ GIM_Reject,
     /* 119419 */ // Label 13: @119419
     /* 119419 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(119568),
     /* 119424 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 119427 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2016*/ GIMT_Encode4(119567),
     /* 119438 */   /*GILLT_s16*//*Label 2013*/ GIMT_Encode4(119450),
     /* 119442 */   /*GILLT_s32*//*Label 2014*/ GIMT_Encode4(119491),
     /* 119446 */   /*GILLT_s64*//*Label 2015*/ GIMT_Encode4(119529),
     /* 119450 */   // Label 2013: @119450
     /* 119450 */   GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(119490), // Rule ID 4858 //
     /* 119455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 119458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119462 */     // (llrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 119462 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119465 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 119469 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119474 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119478 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 119483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119485 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119488 */     GIR_RootConstrainSelectedInstOperands,
     /* 119489 */     // GIR_Coverage, 4858,
     /* 119489 */     GIR_EraseRootFromParent_Done,
     /* 119490 */   // Label 2017: @119490
     /* 119490 */   GIM_Reject,
     /* 119491 */   // Label 2014: @119491
     /* 119491 */   GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(119528), // Rule ID 4868 //
     /* 119496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119500 */     // (llrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 119500 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 119503 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 119507 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119512 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119516 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 119521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119523 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119526 */     GIR_RootConstrainSelectedInstOperands,
     /* 119527 */     // GIR_Coverage, 4868,
     /* 119527 */     GIR_EraseRootFromParent_Done,
     /* 119528 */   // Label 2018: @119528
     /* 119528 */   GIM_Reject,
     /* 119529 */   // Label 2015: @119529
     /* 119529 */   GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(119566), // Rule ID 4870 //
     /* 119534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 119538 */     // (llrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 119538 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 119541 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 119545 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119550 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119554 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 119559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119561 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119564 */     GIR_RootConstrainSelectedInstOperands,
     /* 119565 */     // GIR_Coverage, 4870,
     /* 119565 */     GIR_EraseRootFromParent_Done,
     /* 119566 */   // Label 2019: @119566
     /* 119566 */   GIM_Reject,
     /* 119567 */   // Label 2016: @119567
     /* 119567 */   GIM_Reject,
     /* 119568 */ // Label 2012: @119568
     /* 119568 */ GIM_Reject,
     /* 119569 */ // Label 14: @119569
     /* 119569 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 2028*/ GIMT_Encode4(120059),
     /* 119580 */ /*GILLT_s16*//*Label 2020*/ GIMT_Encode4(119620),
     /* 119584 */ /*GILLT_s32*//*Label 2021*/ GIMT_Encode4(119651),
     /* 119588 */ /*GILLT_s64*//*Label 2022*/ GIMT_Encode4(119682), GIMT_Encode4(0),
     /* 119596 */ /*GILLT_v2s32*//*Label 2023*/ GIMT_Encode4(119713),
     /* 119600 */ /*GILLT_v2s64*//*Label 2024*/ GIMT_Encode4(119744),
     /* 119604 */ /*GILLT_v4s16*//*Label 2025*/ GIMT_Encode4(119775),
     /* 119608 */ /*GILLT_v4s32*//*Label 2026*/ GIMT_Encode4(119806), GIMT_Encode4(0),
     /* 119616 */ /*GILLT_v8s16*//*Label 2027*/ GIMT_Encode4(119837),
     /* 119620 */ // Label 2020: @119620
     /* 119620 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(119650), // Rule ID 550 //
     /* 119625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 119628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 119631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119639 */   // (froundeven:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 119639 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNHr),
     /* 119644 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119648 */   GIR_RootConstrainSelectedInstOperands,
     /* 119649 */   // GIR_Coverage, 550,
     /* 119649 */   GIR_Done,
     /* 119650 */ // Label 2029: @119650
     /* 119650 */ GIM_Reject,
     /* 119651 */ // Label 2021: @119651
     /* 119651 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(119681), // Rule ID 552 //
     /* 119656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 119659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 119662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119666 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119670 */   // (froundeven:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 119670 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNSr),
     /* 119675 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119679 */   GIR_RootConstrainSelectedInstOperands,
     /* 119680 */   // GIR_Coverage, 552,
     /* 119680 */   GIR_Done,
     /* 119681 */ // Label 2030: @119681
     /* 119681 */ GIM_Reject,
     /* 119682 */ // Label 2022: @119682
     /* 119682 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(119712), // Rule ID 554 //
     /* 119687 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 119690 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 119693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119697 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119701 */   // (froundeven:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 119701 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNDr),
     /* 119706 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119710 */   GIR_RootConstrainSelectedInstOperands,
     /* 119711 */   // GIR_Coverage, 554,
     /* 119711 */   GIR_Done,
     /* 119712 */ // Label 2031: @119712
     /* 119712 */ GIM_Reject,
     /* 119713 */ // Label 2023: @119713
     /* 119713 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(119743), // Rule ID 907 //
     /* 119718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 119721 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 119724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119728 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119732 */   // (froundeven:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 119732 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f32),
     /* 119737 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119741 */   GIR_RootConstrainSelectedInstOperands,
     /* 119742 */   // GIR_Coverage, 907,
     /* 119742 */   GIR_Done,
     /* 119743 */ // Label 2032: @119743
     /* 119743 */ GIM_Reject,
     /* 119744 */ // Label 2024: @119744
     /* 119744 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(119774), // Rule ID 911 //
     /* 119749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 119752 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 119755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119759 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119763 */   // (froundeven:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 119763 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f64),
     /* 119768 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119772 */   GIR_RootConstrainSelectedInstOperands,
     /* 119773 */   // GIR_Coverage, 911,
     /* 119773 */   GIR_Done,
     /* 119774 */ // Label 2033: @119774
     /* 119774 */ GIM_Reject,
     /* 119775 */ // Label 2025: @119775
     /* 119775 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(119805), // Rule ID 903 //
     /* 119780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 119783 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 119786 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119790 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119794 */   // (froundeven:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 119794 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f16),
     /* 119799 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119803 */   GIR_RootConstrainSelectedInstOperands,
     /* 119804 */   // GIR_Coverage, 903,
     /* 119804 */   GIR_Done,
     /* 119805 */ // Label 2034: @119805
     /* 119805 */ GIM_Reject,
     /* 119806 */ // Label 2026: @119806
     /* 119806 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(119836), // Rule ID 909 //
     /* 119811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 119814 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 119817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119821 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119825 */   // (froundeven:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 119825 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 119830 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119834 */   GIR_RootConstrainSelectedInstOperands,
     /* 119835 */   // GIR_Coverage, 909,
     /* 119835 */   GIR_Done,
     /* 119836 */ // Label 2035: @119836
     /* 119836 */ GIM_Reject,
     /* 119837 */ // Label 2027: @119837
     /* 119837 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(120058),
     /* 119842 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 119845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119849 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119853 */   GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(119872), // Rule ID 905 //
     /* 119858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 119861 */     // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 119861 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv8f16),
     /* 119866 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 119870 */     GIR_RootConstrainSelectedInstOperands,
     /* 119871 */     // GIR_Coverage, 905,
     /* 119871 */     GIR_Done,
     /* 119872 */   // Label 2037: @119872
     /* 119872 */   GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(120057), // Rule ID 7084 //
     /* 119877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 119880 */     // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTNv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTNv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 119880 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 119883 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 119887 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119892 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 119896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 119898 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 119901 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 119905 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119910 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 119913 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 119915 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 119918 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 119922 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119927 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 119933 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119938 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119943 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 119946 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 119950 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119955 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 119958 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 119960 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 119963 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 119967 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119972 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 119975 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 119977 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 119980 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 119984 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119989 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 119992 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 119994 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 119997 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 120001 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 120006 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 120008 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 120011 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 120015 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 120020 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 120023 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 120026 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 120029 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 120034 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 120039 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 120047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 120049 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 120052 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 120055 */     GIR_RootConstrainSelectedInstOperands,
     /* 120056 */     // GIR_Coverage, 7084,
     /* 120056 */     GIR_EraseRootFromParent_Done,
     /* 120057 */   // Label 2038: @120057
     /* 120057 */   GIM_Reject,
     /* 120058 */ // Label 2036: @120058
     /* 120058 */ GIM_Reject,
     /* 120059 */ // Label 2028: @120059
     /* 120059 */ GIM_Reject,
     /* 120060 */ // Label 15: @120060
     /* 120060 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(120092), // Rule ID 3937 //
     /* 120065 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 120068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 120072 */   // (readcyclecounter:{ *:[i64] })  =>  (MRS:{ *:[i64] }:{ *:[i32] } 57090:{ *:[i32] })
     /* 120072 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
     /* 120075 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120077 */   GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(57090),
     /* 120087 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 120090 */   GIR_RootConstrainSelectedInstOperands,
     /* 120091 */   // GIR_Coverage, 3937,
     /* 120091 */   GIR_EraseRootFromParent_Done,
     /* 120092 */ // Label 2039: @120092
     /* 120092 */ GIM_Reject,
     /* 120093 */ // Label 16: @120093
     /* 120093 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 2060*/ GIMT_Encode4(129030),
     /* 120104 */ /*GILLT_s8*//*Label 2040*/ GIMT_Encode4(120200),
     /* 120108 */ /*GILLT_s16*//*Label 2041*/ GIMT_Encode4(120376),
     /* 120112 */ /*GILLT_s32*//*Label 2042*/ GIMT_Encode4(120552),
     /* 120116 */ /*GILLT_s64*//*Label 2043*/ GIMT_Encode4(122946),
     /* 120120 */ /*GILLT_s128*//*Label 2044*/ GIMT_Encode4(125659),
     /* 120124 */ /*GILLT_v2s32*//*Label 2045*/ GIMT_Encode4(125868),
     /* 120128 */ /*GILLT_v2s64*//*Label 2046*/ GIMT_Encode4(126246),
     /* 120132 */ /*GILLT_v4s16*//*Label 2047*/ GIMT_Encode4(126624),
     /* 120136 */ /*GILLT_v4s32*//*Label 2048*/ GIMT_Encode4(127002),
     /* 120140 */ /*GILLT_v8s8*//*Label 2049*/ GIMT_Encode4(127380),
     /* 120144 */ /*GILLT_v8s16*//*Label 2050*/ GIMT_Encode4(127588),
     /* 120148 */ /*GILLT_v16s8*//*Label 2051*/ GIMT_Encode4(127966), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 120160 */ /*GILLT_nxv2s16*//*Label 2052*/ GIMT_Encode4(128174),
     /* 120164 */ /*GILLT_nxv2s32*//*Label 2053*/ GIMT_Encode4(128238),
     /* 120168 */ /*GILLT_nxv2s64*//*Label 2054*/ GIMT_Encode4(128302), GIMT_Encode4(0),
     /* 120176 */ /*GILLT_nxv4s16*//*Label 2055*/ GIMT_Encode4(128476),
     /* 120180 */ /*GILLT_nxv4s32*//*Label 2056*/ GIMT_Encode4(128540), GIMT_Encode4(0),
     /* 120188 */ /*GILLT_nxv8s16*//*Label 2057*/ GIMT_Encode4(128714),
     /* 120192 */ /*GILLT_nxv16s1*//*Label 2058*/ GIMT_Encode4(128888),
     /* 120196 */ /*GILLT_nxv16s8*//*Label 2059*/ GIMT_Encode4(128932),
     /* 120200 */ // Label 2040: @120200
     /* 120200 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(120375),
     /* 120205 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120208 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 120216 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120220 */   GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(120261), // Rule ID 241 //
     /* 120225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 120235 */     // (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 120235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 120238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120259 */     GIR_RootConstrainSelectedInstOperands,
     /* 120260 */     // GIR_Coverage, 241,
     /* 120260 */     GIR_EraseRootFromParent_Done,
     /* 120261 */   // Label 2062: @120261
     /* 120261 */   GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(120302), // Rule ID 242 //
     /* 120266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 120276 */     // (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 120276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 120279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120300 */     GIR_RootConstrainSelectedInstOperands,
     /* 120301 */     // GIR_Coverage, 242,
     /* 120301 */     GIR_EraseRootFromParent_Done,
     /* 120302 */   // Label 2063: @120302
     /* 120302 */   GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(120338), // Rule ID 265 //
     /* 120307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120310 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 120317 */     // (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 120317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 120320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 120332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120336 */     GIR_RootConstrainSelectedInstOperands,
     /* 120337 */     // GIR_Coverage, 265,
     /* 120337 */     GIR_EraseRootFromParent_Done,
     /* 120338 */   // Label 2064: @120338
     /* 120338 */   GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(120374), // Rule ID 286 //
     /* 120343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 120353 */     // (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 120353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 120356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 120368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120372 */     GIR_RootConstrainSelectedInstOperands,
     /* 120373 */     // GIR_Coverage, 286,
     /* 120373 */     GIR_EraseRootFromParent_Done,
     /* 120374 */   // Label 2065: @120374
     /* 120374 */   GIM_Reject,
     /* 120375 */ // Label 2061: @120375
     /* 120375 */ GIM_Reject,
     /* 120376 */ // Label 2041: @120376
     /* 120376 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(120551),
     /* 120381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120384 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120396 */   GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(120437), // Rule ID 243 //
     /* 120401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 120411 */     // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 120411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 120414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120435 */     GIR_RootConstrainSelectedInstOperands,
     /* 120436 */     // GIR_Coverage, 243,
     /* 120436 */     GIR_EraseRootFromParent_Done,
     /* 120437 */   // Label 2067: @120437
     /* 120437 */   GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(120478), // Rule ID 244 //
     /* 120442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 120452 */     // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 120452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 120455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120476 */     GIR_RootConstrainSelectedInstOperands,
     /* 120477 */     // GIR_Coverage, 244,
     /* 120477 */     GIR_EraseRootFromParent_Done,
     /* 120478 */   // Label 2068: @120478
     /* 120478 */   GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(120514), // Rule ID 266 //
     /* 120483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 120493 */     // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 120493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 120496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 120508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120512 */     GIR_RootConstrainSelectedInstOperands,
     /* 120513 */     // GIR_Coverage, 266,
     /* 120513 */     GIR_EraseRootFromParent_Done,
     /* 120514 */   // Label 2069: @120514
     /* 120514 */   GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(120550), // Rule ID 287 //
     /* 120519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 120529 */     // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 120529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 120532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 120544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120548 */     GIR_RootConstrainSelectedInstOperands,
     /* 120549 */     // GIR_Coverage, 287,
     /* 120549 */     GIR_EraseRootFromParent_Done,
     /* 120550 */   // Label 2070: @120550
     /* 120550 */   GIM_Reject,
     /* 120551 */ // Label 2066: @120551
     /* 120551 */ GIM_Reject,
     /* 120552 */ // Label 2042: @120552
     /* 120552 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(120605), // Rule ID 237 //
     /* 120557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120560 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120564 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120568 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120572 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 120579 */   // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 120579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 120582 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120603 */   GIR_RootConstrainSelectedInstOperands,
     /* 120604 */   // GIR_Coverage, 237,
     /* 120604 */   GIR_EraseRootFromParent_Done,
     /* 120605 */ // Label 2071: @120605
     /* 120605 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(120658), // Rule ID 238 //
     /* 120610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120613 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120617 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120621 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120625 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 120632 */   // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 120632 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 120635 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120656 */   GIR_RootConstrainSelectedInstOperands,
     /* 120657 */   // GIR_Coverage, 238,
     /* 120657 */   GIR_EraseRootFromParent_Done,
     /* 120658 */ // Label 2072: @120658
     /* 120658 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(120714), // Rule ID 245 //
     /* 120663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120669 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120677 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120681 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 120688 */   // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 120688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 120691 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120708 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120712 */   GIR_RootConstrainSelectedInstOperands,
     /* 120713 */   // GIR_Coverage, 245,
     /* 120713 */   GIR_EraseRootFromParent_Done,
     /* 120714 */ // Label 2073: @120714
     /* 120714 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(120770), // Rule ID 246 //
     /* 120719 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 120722 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120725 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 120744 */   // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 120744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 120747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120764 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120768 */   GIR_RootConstrainSelectedInstOperands,
     /* 120769 */   // GIR_Coverage, 246,
     /* 120769 */   GIR_EraseRootFromParent_Done,
     /* 120770 */ // Label 2074: @120770
     /* 120770 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(120830), // Rule ID 4153 //
     /* 120775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120778 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 120789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 120804 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 120804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 120807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120824 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120828 */   GIR_RootConstrainSelectedInstOperands,
     /* 120829 */   // GIR_Coverage, 4153,
     /* 120829 */   GIR_EraseRootFromParent_Done,
     /* 120830 */ // Label 2075: @120830
     /* 120830 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(120890), // Rule ID 4154 //
     /* 120835 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120838 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120842 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 120849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120857 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 120864 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 120864 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 120867 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120884 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120888 */   GIR_RootConstrainSelectedInstOperands,
     /* 120889 */   // GIR_Coverage, 4154,
     /* 120889 */   GIR_EraseRootFromParent_Done,
     /* 120890 */ // Label 2076: @120890
     /* 120890 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(120950), // Rule ID 4155 //
     /* 120895 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120898 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120902 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 120909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 120924 */   // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 120924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 120927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 120944 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 120948 */   GIR_RootConstrainSelectedInstOperands,
     /* 120949 */   // GIR_Coverage, 4155,
     /* 120949 */   GIR_EraseRootFromParent_Done,
     /* 120950 */ // Label 2077: @120950
     /* 120950 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(121010), // Rule ID 4156 //
     /* 120955 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 120958 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 120962 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 120969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 120973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 120977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 120984 */   // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 120984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 120987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 120989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 120994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 120999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121008 */   GIR_RootConstrainSelectedInstOperands,
     /* 121009 */   // GIR_Coverage, 4156,
     /* 121009 */   GIR_EraseRootFromParent_Done,
     /* 121010 */ // Label 2078: @121010
     /* 121010 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(121070), // Rule ID 4157 //
     /* 121015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121018 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121022 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 121029 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121033 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121037 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 121044 */   // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 121044 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 121047 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121064 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121068 */   GIR_RootConstrainSelectedInstOperands,
     /* 121069 */   // GIR_Coverage, 4157,
     /* 121069 */   GIR_EraseRootFromParent_Done,
     /* 121070 */ // Label 2079: @121070
     /* 121070 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(121130), // Rule ID 4158 //
     /* 121075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121078 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121082 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 121089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121093 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121097 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 121104 */   // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 121104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 121107 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121124 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121128 */   GIR_RootConstrainSelectedInstOperands,
     /* 121129 */   // GIR_Coverage, 4158,
     /* 121129 */   GIR_EraseRootFromParent_Done,
     /* 121130 */ // Label 2080: @121130
     /* 121130 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(121178), // Rule ID 264 //
     /* 121135 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121138 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121142 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121146 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121150 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 121157 */   // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 121157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 121160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121172 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121176 */   GIR_RootConstrainSelectedInstOperands,
     /* 121177 */   // GIR_Coverage, 264,
     /* 121177 */   GIR_EraseRootFromParent_Done,
     /* 121178 */ // Label 2081: @121178
     /* 121178 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(121229), // Rule ID 267 //
     /* 121183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 121186 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121189 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121193 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121197 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121201 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 121208 */   // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 121208 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 121211 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121223 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121227 */   GIR_RootConstrainSelectedInstOperands,
     /* 121228 */   // GIR_Coverage, 267,
     /* 121228 */   GIR_EraseRootFromParent_Done,
     /* 121229 */ // Label 2082: @121229
     /* 121229 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(121292), // Rule ID 7114 //
     /* 121234 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121237 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121241 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 121248 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121255 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121259 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 121266 */   // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
     /* 121266 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 121269 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 121286 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121290 */   GIR_RootConstrainSelectedInstOperands,
     /* 121291 */   // GIR_Coverage, 7114,
     /* 121291 */   GIR_EraseRootFromParent_Done,
     /* 121292 */ // Label 2083: @121292
     /* 121292 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(121355), // Rule ID 7116 //
     /* 121297 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121300 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121304 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 121311 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121318 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121322 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 121329 */   // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
     /* 121329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 121332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 121349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121353 */   GIR_RootConstrainSelectedInstOperands,
     /* 121354 */   // GIR_Coverage, 7116,
     /* 121354 */   GIR_EraseRootFromParent_Done,
     /* 121355 */ // Label 2084: @121355
     /* 121355 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(121418), // Rule ID 7126 //
     /* 121360 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121363 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121367 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 121374 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121377 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121381 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121385 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 121392 */   // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 121392 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 121395 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121412 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121416 */   GIR_RootConstrainSelectedInstOperands,
     /* 121417 */   // GIR_Coverage, 7126,
     /* 121417 */   GIR_EraseRootFromParent_Done,
     /* 121418 */ // Label 2085: @121418
     /* 121418 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(121481), // Rule ID 7128 //
     /* 121423 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121426 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 121437 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121444 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121448 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 121455 */   // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 121455 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 121458 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121479 */   GIR_RootConstrainSelectedInstOperands,
     /* 121480 */   // GIR_Coverage, 7128,
     /* 121480 */   GIR_EraseRootFromParent_Done,
     /* 121481 */ // Label 2086: @121481
     /* 121481 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(121544), // Rule ID 7136 //
     /* 121486 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121489 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121493 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 121500 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121507 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121511 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 121518 */   // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>  =>  (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 121518 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 121521 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121538 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121542 */   GIR_RootConstrainSelectedInstOperands,
     /* 121543 */   // GIR_Coverage, 7136,
     /* 121543 */   GIR_EraseRootFromParent_Done,
     /* 121544 */ // Label 2087: @121544
     /* 121544 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(121607), // Rule ID 7137 //
     /* 121549 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 121552 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121556 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 121563 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 121566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 121581 */   // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>  =>  (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 121581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 121584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 121596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 121601 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121605 */   GIR_RootConstrainSelectedInstOperands,
     /* 121606 */   // GIR_Coverage, 7137,
     /* 121606 */   GIR_EraseRootFromParent_Done,
     /* 121607 */ // Label 2088: @121607
     /* 121607 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(121655), // Rule ID 285 //
     /* 121612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121615 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 121634 */   // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 121634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 121637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121653 */   GIR_RootConstrainSelectedInstOperands,
     /* 121654 */   // GIR_Coverage, 285,
     /* 121654 */   GIR_EraseRootFromParent_Done,
     /* 121655 */ // Label 2089: @121655
     /* 121655 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(121706), // Rule ID 288 //
     /* 121660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 121663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121666 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121674 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121678 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 121685 */   // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 121685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 121688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121700 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121704 */   GIR_RootConstrainSelectedInstOperands,
     /* 121705 */   // GIR_Coverage, 288,
     /* 121705 */   GIR_EraseRootFromParent_Done,
     /* 121706 */ // Label 2090: @121706
     /* 121706 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(121761), // Rule ID 4180 //
     /* 121711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121714 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121718 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 121725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 121740 */   // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 121740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 121743 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121759 */   GIR_RootConstrainSelectedInstOperands,
     /* 121760 */   // GIR_Coverage, 4180,
     /* 121760 */   GIR_EraseRootFromParent_Done,
     /* 121761 */ // Label 2091: @121761
     /* 121761 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(121816), // Rule ID 4181 //
     /* 121766 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121769 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121773 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 121780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121784 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121788 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 121795 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 121795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 121798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121814 */   GIR_RootConstrainSelectedInstOperands,
     /* 121815 */   // GIR_Coverage, 4181,
     /* 121815 */   GIR_EraseRootFromParent_Done,
     /* 121816 */ // Label 2092: @121816
     /* 121816 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(121871), // Rule ID 4182 //
     /* 121821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121824 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121828 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 121835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 121850 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 121850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 121853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121865 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121869 */   GIR_RootConstrainSelectedInstOperands,
     /* 121870 */   // GIR_Coverage, 4182,
     /* 121870 */   GIR_EraseRootFromParent_Done,
     /* 121871 */ // Label 2093: @121871
     /* 121871 */ GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(121926), // Rule ID 4203 //
     /* 121876 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121879 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121883 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 121890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 121905 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 121905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 121908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121920 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121924 */   GIR_RootConstrainSelectedInstOperands,
     /* 121925 */   // GIR_Coverage, 4203,
     /* 121925 */   GIR_EraseRootFromParent_Done,
     /* 121926 */ // Label 2094: @121926
     /* 121926 */ GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(121981), // Rule ID 4204 //
     /* 121931 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121934 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121938 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 121945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 121949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 121953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 121960 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 121960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 121963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 121965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 121970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 121975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 121979 */   GIR_RootConstrainSelectedInstOperands,
     /* 121980 */   // GIR_Coverage, 4204,
     /* 121980 */   GIR_EraseRootFromParent_Done,
     /* 121981 */ // Label 2095: @121981
     /* 121981 */ GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(122036), // Rule ID 4205 //
     /* 121986 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 121989 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 121993 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122004 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122008 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 122015 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 122018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122030 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122034 */   GIR_RootConstrainSelectedInstOperands,
     /* 122035 */   // GIR_Coverage, 4205,
     /* 122035 */   GIR_EraseRootFromParent_Done,
     /* 122036 */ // Label 2096: @122036
     /* 122036 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(122094), // Rule ID 7118 //
     /* 122041 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122044 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122048 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122055 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122058 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122062 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122066 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 122073 */   // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 122073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 122076 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122088 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122092 */   GIR_RootConstrainSelectedInstOperands,
     /* 122093 */   // GIR_Coverage, 7118,
     /* 122093 */   GIR_EraseRootFromParent_Done,
     /* 122094 */ // Label 2097: @122094
     /* 122094 */ GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(122152), // Rule ID 7120 //
     /* 122099 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122102 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122106 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122113 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122120 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122124 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 122131 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15879>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 122134 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122150 */   GIR_RootConstrainSelectedInstOperands,
     /* 122151 */   // GIR_Coverage, 7120,
     /* 122151 */   GIR_EraseRootFromParent_Done,
     /* 122152 */ // Label 2098: @122152
     /* 122152 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(122210), // Rule ID 7130 //
     /* 122157 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122160 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122164 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122171 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122178 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122182 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 122189 */   // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 122189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 122192 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122204 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122208 */   GIR_RootConstrainSelectedInstOperands,
     /* 122209 */   // GIR_Coverage, 7130,
     /* 122209 */   GIR_EraseRootFromParent_Done,
     /* 122210 */ // Label 2099: @122210
     /* 122210 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(122268), // Rule ID 7132 //
     /* 122215 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122218 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122222 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122229 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122232 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122236 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122240 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 122247 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15887>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122247 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 122250 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122266 */   GIR_RootConstrainSelectedInstOperands,
     /* 122267 */   // GIR_Coverage, 7132,
     /* 122267 */   GIR_EraseRootFromParent_Done,
     /* 122268 */ // Label 2100: @122268
     /* 122268 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(122326), // Rule ID 7138 //
     /* 122273 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122276 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122287 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 122305 */   // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 122305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 122308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122320 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122324 */   GIR_RootConstrainSelectedInstOperands,
     /* 122325 */   // GIR_Coverage, 7138,
     /* 122325 */   GIR_EraseRootFromParent_Done,
     /* 122326 */ // Label 2101: @122326
     /* 122326 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(122384), // Rule ID 7139 //
     /* 122331 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122334 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122338 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122345 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 122363 */   // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15895>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 122366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122382 */   GIR_RootConstrainSelectedInstOperands,
     /* 122383 */   // GIR_Coverage, 7139,
     /* 122383 */   GIR_EraseRootFromParent_Done,
     /* 122384 */ // Label 2102: @122384
     /* 122384 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(122445), // Rule ID 7524 //
     /* 122389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 122392 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122395 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122399 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122406 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122413 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122417 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 122424 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15868>>  =>  (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
     /* 122427 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122439 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122443 */   GIR_RootConstrainSelectedInstOperands,
     /* 122444 */   // GIR_Coverage, 7524,
     /* 122444 */   GIR_EraseRootFromParent_Done,
     /* 122445 */ // Label 2103: @122445
     /* 122445 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(122506), // Rule ID 7526 //
     /* 122450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 122453 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122456 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122460 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122467 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122470 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122474 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122478 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 122485 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15870>>  =>  (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
     /* 122488 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122500 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122504 */   GIR_RootConstrainSelectedInstOperands,
     /* 122505 */   // GIR_Coverage, 7526,
     /* 122505 */   GIR_EraseRootFromParent_Done,
     /* 122506 */ // Label 2104: @122506
     /* 122506 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(122567), // Rule ID 7528 //
     /* 122511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 122514 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122517 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122521 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122528 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122535 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 122546 */   // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15872>>  =>  (LDAPURi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 122546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURi),
     /* 122549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 122561 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122565 */   GIR_RootConstrainSelectedInstOperands,
     /* 122566 */   // GIR_Coverage, 7528,
     /* 122566 */   GIR_EraseRootFromParent_Done,
     /* 122567 */ // Label 2105: @122567
     /* 122567 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(122611), // Rule ID 7104 //
     /* 122572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 122575 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122578 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122582 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122596 */   // MIs[0] ptr
     /* 122596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122600 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122604 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15868>>  =>  (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122604 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRB),
     /* 122609 */   GIR_RootConstrainSelectedInstOperands,
     /* 122610 */   // GIR_Coverage, 7104,
     /* 122610 */   GIR_Done,
     /* 122611 */ // Label 2106: @122611
     /* 122611 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(122655), // Rule ID 7106 //
     /* 122616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 122619 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122622 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122633 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122640 */   // MIs[0] ptr
     /* 122640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122644 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122648 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15870>>  =>  (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122648 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRH),
     /* 122653 */   GIR_RootConstrainSelectedInstOperands,
     /* 122654 */   // GIR_Coverage, 7106,
     /* 122654 */   GIR_Done,
     /* 122655 */ // Label 2107: @122655
     /* 122655 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(122699), // Rule ID 7108 //
     /* 122660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 122663 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122666 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122670 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122684 */   // MIs[0] ptr
     /* 122684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122688 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122692 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15872>>  =>  (LDAPRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122692 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRW),
     /* 122697 */   GIR_RootConstrainSelectedInstOperands,
     /* 122698 */   // GIR_Coverage, 7108,
     /* 122698 */   GIR_Done,
     /* 122699 */ // Label 2108: @122699
     /* 122699 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(122740), // Rule ID 7110 //
     /* 122704 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122707 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122711 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122718 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 122721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122725 */   // MIs[0] ptr
     /* 122725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122729 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122733 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15876>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122733 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 122738 */   GIR_RootConstrainSelectedInstOperands,
     /* 122739 */   // GIR_Coverage, 7110,
     /* 122739 */   GIR_Done,
     /* 122740 */ // Label 2109: @122740
     /* 122740 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(122781), // Rule ID 7112 //
     /* 122745 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122748 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 122759 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122762 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122766 */   // MIs[0] ptr
     /* 122766 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122770 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122774 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_15868>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122774 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 122779 */   GIR_RootConstrainSelectedInstOperands,
     /* 122780 */   // GIR_Coverage, 7112,
     /* 122780 */   GIR_Done,
     /* 122781 */ // Label 2110: @122781
     /* 122781 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(122822), // Rule ID 7122 //
     /* 122786 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122789 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122793 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122800 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 122803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122807 */   // MIs[0] ptr
     /* 122807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122811 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122815 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15884>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122815 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 122820 */   GIR_RootConstrainSelectedInstOperands,
     /* 122821 */   // GIR_Coverage, 7122,
     /* 122821 */   GIR_Done,
     /* 122822 */ // Label 2111: @122822
     /* 122822 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(122863), // Rule ID 7124 //
     /* 122827 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122830 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 122841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122848 */   // MIs[0] ptr
     /* 122848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122852 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122856 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_15870>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122856 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 122861 */   GIR_RootConstrainSelectedInstOperands,
     /* 122862 */   // GIR_Coverage, 7124,
     /* 122862 */   GIR_Done,
     /* 122863 */ // Label 2112: @122863
     /* 122863 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(122904), // Rule ID 7134 //
     /* 122868 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122871 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122875 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122882 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 122885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122889 */   // MIs[0] ptr
     /* 122889 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122893 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122897 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15892>>  =>  (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122897 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
     /* 122902 */   GIR_RootConstrainSelectedInstOperands,
     /* 122903 */   // GIR_Coverage, 7134,
     /* 122903 */   GIR_Done,
     /* 122904 */ // Label 2113: @122904
     /* 122904 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(122945), // Rule ID 7135 //
     /* 122909 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122912 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122923 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122930 */   // MIs[0] ptr
     /* 122930 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 122934 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 122938 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_15872>>  =>  (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 122938 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
     /* 122943 */   GIR_RootConstrainSelectedInstOperands,
     /* 122944 */   // GIR_Coverage, 7135,
     /* 122944 */   GIR_Done,
     /* 122945 */ // Label 2114: @122945
     /* 122945 */ GIM_Reject,
     /* 122946 */ // Label 2043: @122946
     /* 122946 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(122999), // Rule ID 239 //
     /* 122951 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 122954 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 122958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 122962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 122966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 122973 */   // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 122973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
     /* 122976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 122988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 122993 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 122997 */   GIR_RootConstrainSelectedInstOperands,
     /* 122998 */   // GIR_Coverage, 239,
     /* 122998 */   GIR_EraseRootFromParent_Done,
     /* 122999 */ // Label 2115: @122999
     /* 122999 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(123052), // Rule ID 240 //
     /* 123004 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123007 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 123015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 123026 */   // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 123026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
     /* 123029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123050 */   GIR_RootConstrainSelectedInstOperands,
     /* 123051 */   // GIR_Coverage, 240,
     /* 123051 */   GIR_EraseRootFromParent_Done,
     /* 123052 */ // Label 2116: @123052
     /* 123052 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(123108), // Rule ID 247 //
     /* 123057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 123060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123063 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 123082 */   // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 123082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 123085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123102 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123106 */   GIR_RootConstrainSelectedInstOperands,
     /* 123107 */   // GIR_Coverage, 247,
     /* 123107 */   GIR_EraseRootFromParent_Done,
     /* 123108 */ // Label 2117: @123108
     /* 123108 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(123164), // Rule ID 248 //
     /* 123113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 123116 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123119 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123127 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123131 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 123138 */   // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 123138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 123141 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123162 */   GIR_RootConstrainSelectedInstOperands,
     /* 123163 */   // GIR_Coverage, 248,
     /* 123163 */   GIR_EraseRootFromParent_Done,
     /* 123164 */ // Label 2118: @123164
     /* 123164 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(123217), // Rule ID 4119 //
     /* 123169 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123172 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 123191 */   // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 123191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 123194 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123215 */   GIR_RootConstrainSelectedInstOperands,
     /* 123216 */   // GIR_Coverage, 4119,
     /* 123216 */   GIR_EraseRootFromParent_Done,
     /* 123217 */ // Label 2119: @123217
     /* 123217 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(123270), // Rule ID 4120 //
     /* 123222 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123225 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 123244 */   // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 123244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 123247 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123264 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123268 */   GIR_RootConstrainSelectedInstOperands,
     /* 123269 */   // GIR_Coverage, 4120,
     /* 123269 */   GIR_EraseRootFromParent_Done,
     /* 123270 */ // Label 2120: @123270
     /* 123270 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(123323), // Rule ID 4121 //
     /* 123275 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123278 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123290 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 123297 */   // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 123297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 123300 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123317 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123321 */   GIR_RootConstrainSelectedInstOperands,
     /* 123322 */   // GIR_Coverage, 4121,
     /* 123322 */   GIR_EraseRootFromParent_Done,
     /* 123323 */ // Label 2121: @123323
     /* 123323 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(123376), // Rule ID 4122 //
     /* 123328 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123331 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123343 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 123350 */   // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 123350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 123353 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123370 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123374 */   GIR_RootConstrainSelectedInstOperands,
     /* 123375 */   // GIR_Coverage, 4122,
     /* 123375 */   GIR_EraseRootFromParent_Done,
     /* 123376 */ // Label 2122: @123376
     /* 123376 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(123468), // Rule ID 4145 //
     /* 123381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123384 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 123410 */   // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123410 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123413 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 123417 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123437 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123441 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123446 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123448 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123451 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123457 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123462 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123467 */   // GIR_Coverage, 4145,
     /* 123467 */   GIR_EraseRootFromParent_Done,
     /* 123468 */ // Label 2123: @123468
     /* 123468 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(123560), // Rule ID 4146 //
     /* 123473 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123476 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123480 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123491 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123495 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 123502 */   // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123502 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123505 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 123509 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123529 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123533 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123538 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123543 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123546 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123549 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123554 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123559 */   // GIR_Coverage, 4146,
     /* 123559 */   GIR_EraseRootFromParent_Done,
     /* 123560 */ // Label 2124: @123560
     /* 123560 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(123652), // Rule ID 4147 //
     /* 123565 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123568 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123572 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 123579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123587 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 123594 */   // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123594 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123597 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 123601 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123621 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123625 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123627 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123630 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123635 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123641 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123646 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123651 */   // GIR_Coverage, 4147,
     /* 123651 */   GIR_EraseRootFromParent_Done,
     /* 123652 */ // Label 2125: @123652
     /* 123652 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(123744), // Rule ID 4148 //
     /* 123657 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123660 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123664 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 123671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123675 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123679 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 123686 */   // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123686 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123689 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 123693 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123713 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123717 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123727 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123730 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123733 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123743 */   // GIR_Coverage, 4148,
     /* 123743 */   GIR_EraseRootFromParent_Done,
     /* 123744 */ // Label 2126: @123744
     /* 123744 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(123836), // Rule ID 4149 //
     /* 123749 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123752 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123756 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 123763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 123778 */   // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123778 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123781 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 123785 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123805 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123809 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123816 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123819 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123822 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123825 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123830 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123835 */   // GIR_Coverage, 4149,
     /* 123835 */   GIR_EraseRootFromParent_Done,
     /* 123836 */ // Label 2127: @123836
     /* 123836 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(123928), // Rule ID 4150 //
     /* 123841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123844 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123848 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 123855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123859 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123863 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 123870 */   // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123870 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123873 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 123877 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123897 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123901 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123908 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123911 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 123917 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123922 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 123927 */   // GIR_Coverage, 4150,
     /* 123927 */   GIR_EraseRootFromParent_Done,
     /* 123928 */ // Label 2128: @123928
     /* 123928 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(124020), // Rule ID 4151 //
     /* 123933 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123936 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 123940 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 123951 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 123955 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 123962 */   // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 123962 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123965 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 123969 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123989 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 123993 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123995 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123998 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124003 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124009 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124014 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124019 */   // GIR_Coverage, 4151,
     /* 124019 */   GIR_EraseRootFromParent_Done,
     /* 124020 */ // Label 2129: @124020
     /* 124020 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(124112), // Rule ID 4152 //
     /* 124025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124028 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124032 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 124039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124043 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124047 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 124054 */   // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 124054 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 124057 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 124061 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 124076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 124081 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124085 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124090 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124095 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124098 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124101 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124106 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124111 */   // GIR_Coverage, 4152,
     /* 124111 */   GIR_EraseRootFromParent_Done,
     /* 124112 */ // Label 2130: @124112
     /* 124112 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(124160), // Rule ID 263 //
     /* 124117 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124120 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 124128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 124139 */   // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 124139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
     /* 124142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124154 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124158 */   GIR_RootConstrainSelectedInstOperands,
     /* 124159 */   // GIR_Coverage, 263,
     /* 124159 */   GIR_EraseRootFromParent_Done,
     /* 124160 */ // Label 2131: @124160
     /* 124160 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(124211), // Rule ID 268 //
     /* 124165 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 124168 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124171 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124175 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124179 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124183 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 124190 */   // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 124190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 124193 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124205 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124209 */   GIR_RootConstrainSelectedInstOperands,
     /* 124210 */   // GIR_Coverage, 268,
     /* 124210 */   GIR_EraseRootFromParent_Done,
     /* 124211 */ // Label 2132: @124211
     /* 124211 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(124274), // Rule ID 7142 //
     /* 124216 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 124219 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124223 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 124230 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 124233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 124237 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124241 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 124248 */   // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>  =>  (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 124248 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
     /* 124251 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 124263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 124268 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124272 */   GIR_RootConstrainSelectedInstOperands,
     /* 124273 */   // GIR_Coverage, 7142,
     /* 124273 */   GIR_EraseRootFromParent_Done,
     /* 124274 */ // Label 2133: @124274
     /* 124274 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(124337), // Rule ID 7143 //
     /* 124279 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 124282 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124286 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 124293 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 124296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 124300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 124311 */   // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>  =>  (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 124311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
     /* 124314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 124326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 124331 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124335 */   GIR_RootConstrainSelectedInstOperands,
     /* 124336 */   // GIR_Coverage, 7143,
     /* 124336 */   GIR_EraseRootFromParent_Done,
     /* 124337 */ // Label 2134: @124337
     /* 124337 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(124385), // Rule ID 284 //
     /* 124342 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124345 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 124353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124357 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 124364 */   // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 124364 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
     /* 124367 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124383 */   GIR_RootConstrainSelectedInstOperands,
     /* 124384 */   // GIR_Coverage, 284,
     /* 124384 */   GIR_EraseRootFromParent_Done,
     /* 124385 */ // Label 2135: @124385
     /* 124385 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(124436), // Rule ID 289 //
     /* 124390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 124393 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124396 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 124415 */   // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 124415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 124418 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124434 */   GIR_RootConstrainSelectedInstOperands,
     /* 124435 */   // GIR_Coverage, 289,
     /* 124435 */   GIR_EraseRootFromParent_Done,
     /* 124436 */ // Label 2136: @124436
     /* 124436 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(124484), // Rule ID 4166 //
     /* 124441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124444 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124456 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 124463 */   // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 124463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 124466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124478 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124482 */   GIR_RootConstrainSelectedInstOperands,
     /* 124483 */   // GIR_Coverage, 4166,
     /* 124483 */   GIR_EraseRootFromParent_Done,
     /* 124484 */ // Label 2137: @124484
     /* 124484 */ GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(124532), // Rule ID 4167 //
     /* 124489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124492 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124496 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124500 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124504 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 124511 */   // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 124511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 124514 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124526 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124530 */   GIR_RootConstrainSelectedInstOperands,
     /* 124531 */   // GIR_Coverage, 4167,
     /* 124531 */   GIR_EraseRootFromParent_Done,
     /* 124532 */ // Label 2138: @124532
     /* 124532 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(124619), // Rule ID 4183 //
     /* 124537 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124540 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124544 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 124551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 124566 */   // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 124566 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 124569 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 124573 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124588 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124592 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124597 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124602 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124605 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124608 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124613 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124618 */   // GIR_Coverage, 4183,
     /* 124618 */   GIR_EraseRootFromParent_Done,
     /* 124619 */ // Label 2139: @124619
     /* 124619 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(124706), // Rule ID 4184 //
     /* 124624 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124627 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124631 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 124638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 124653 */   // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 124653 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 124656 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 124660 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124675 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124679 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124686 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124689 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124692 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124695 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124700 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124705 */   // GIR_Coverage, 4184,
     /* 124705 */   GIR_EraseRootFromParent_Done,
     /* 124706 */ // Label 2140: @124706
     /* 124706 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(124793), // Rule ID 4185 //
     /* 124711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124714 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124718 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 124725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 124740 */   // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 124740 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 124743 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 124747 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124762 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124766 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124776 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124782 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124787 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124792 */   // GIR_Coverage, 4185,
     /* 124792 */   GIR_EraseRootFromParent_Done,
     /* 124793 */ // Label 2141: @124793
     /* 124793 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(124880), // Rule ID 4186 //
     /* 124798 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124801 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 124812 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124816 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124820 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 124827 */   // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 124827 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 124830 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 124834 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124849 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124853 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124858 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124863 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 124869 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124874 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 124879 */   // GIR_Coverage, 4186,
     /* 124879 */   GIR_EraseRootFromParent_Done,
     /* 124880 */ // Label 2142: @124880
     /* 124880 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(124928), // Rule ID 4194 //
     /* 124885 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124888 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 124907 */   // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 124907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 124910 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124922 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124926 */   GIR_RootConstrainSelectedInstOperands,
     /* 124927 */   // GIR_Coverage, 4194,
     /* 124927 */   GIR_EraseRootFromParent_Done,
     /* 124928 */ // Label 2143: @124928
     /* 124928 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(124976), // Rule ID 4195 //
     /* 124933 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124936 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124940 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124944 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 124948 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 124955 */   // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 124955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 124958 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 124960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124970 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 124974 */   GIR_RootConstrainSelectedInstOperands,
     /* 124975 */   // GIR_Coverage, 4195,
     /* 124975 */   GIR_EraseRootFromParent_Done,
     /* 124976 */ // Label 2144: @124976
     /* 124976 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(125063), // Rule ID 4206 //
     /* 124981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124984 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 124988 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 124995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 124999 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125003 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 125010 */   // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 125010 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 125013 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 125017 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 125022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125032 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125036 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 125038 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 125041 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 125043 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 125046 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 125049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 125052 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125057 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 125062 */   // GIR_Coverage, 4206,
     /* 125062 */   GIR_EraseRootFromParent_Done,
     /* 125063 */ // Label 2145: @125063
     /* 125063 */ GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(125150), // Rule ID 4207 //
     /* 125068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125071 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125075 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 125082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125086 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125090 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 125097 */   // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 125097 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 125100 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 125104 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 125109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125119 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125123 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 125125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 125128 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 125130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 125133 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 125136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 125139 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125144 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 125149 */   // GIR_Coverage, 4207,
     /* 125149 */   GIR_EraseRootFromParent_Done,
     /* 125150 */ // Label 2146: @125150
     /* 125150 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(125237), // Rule ID 4208 //
     /* 125155 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125158 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125162 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 125169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125177 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 125184 */   // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 125184 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 125187 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 125191 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 125196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125206 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125210 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 125212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 125215 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 125217 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 125220 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 125223 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 125226 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125231 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 125236 */   // GIR_Coverage, 4208,
     /* 125236 */   GIR_EraseRootFromParent_Done,
     /* 125237 */ // Label 2147: @125237
     /* 125237 */ GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(125324), // Rule ID 4209 //
     /* 125242 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125245 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125249 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 125256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 125271 */   // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 125271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 125274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 125278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 125283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125293 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125297 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 125299 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 125302 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 125304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 125307 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 125310 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 125313 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 125318 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 125323 */   // GIR_Coverage, 4209,
     /* 125323 */   GIR_EraseRootFromParent_Done,
     /* 125324 */ // Label 2148: @125324
     /* 125324 */ GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(125382), // Rule ID 7144 //
     /* 125329 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125332 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125343 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 125346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125350 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 125361 */   // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 125361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
     /* 125364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125376 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125380 */   GIR_RootConstrainSelectedInstOperands,
     /* 125381 */   // GIR_Coverage, 7144,
     /* 125381 */   GIR_EraseRootFromParent_Done,
     /* 125382 */ // Label 2149: @125382
     /* 125382 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(125440), // Rule ID 7145 //
     /* 125387 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125390 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125394 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125401 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 125404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 125419 */   // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15903>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 125419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
     /* 125422 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125434 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125438 */   GIR_RootConstrainSelectedInstOperands,
     /* 125439 */   // GIR_Coverage, 7145,
     /* 125439 */   GIR_EraseRootFromParent_Done,
     /* 125440 */ // Label 2150: @125440
     /* 125440 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(125501), // Rule ID 7529 //
     /* 125445 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 125448 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125451 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125455 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125462 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 125465 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125469 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125473 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 125480 */   // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15874>>  =>  (LDAPURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 125480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURXi),
     /* 125483 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125495 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125499 */   GIR_RootConstrainSelectedInstOperands,
     /* 125500 */   // GIR_Coverage, 7529,
     /* 125500 */   GIR_EraseRootFromParent_Done,
     /* 125501 */ // Label 2151: @125501
     /* 125501 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(125532), // Rule ID 6471 //
     /* 125506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125509 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125517 */   // MIs[0] Rn
     /* 125517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 125521 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 125525 */   // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 125525 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev1d),
     /* 125530 */   GIR_RootConstrainSelectedInstOperands,
     /* 125531 */   // GIR_Coverage, 6471,
     /* 125531 */   GIR_Done,
     /* 125532 */ // Label 2152: @125532
     /* 125532 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(125576), // Rule ID 7109 //
     /* 125537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 125540 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125543 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125547 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 125557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125561 */   // MIs[0] ptr
     /* 125561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 125565 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 125569 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15874>>  =>  (LDAPRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 125569 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRX),
     /* 125574 */   GIR_RootConstrainSelectedInstOperands,
     /* 125575 */   // GIR_Coverage, 7109,
     /* 125575 */   GIR_Done,
     /* 125576 */ // Label 2153: @125576
     /* 125576 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(125617), // Rule ID 7140 //
     /* 125581 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125584 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125588 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 125598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125602 */   // MIs[0] ptr
     /* 125602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 125606 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 125610 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15900>>  =>  (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 125610 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
     /* 125615 */   GIR_RootConstrainSelectedInstOperands,
     /* 125616 */   // GIR_Coverage, 7140,
     /* 125616 */   GIR_Done,
     /* 125617 */ // Label 2154: @125617
     /* 125617 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(125658), // Rule ID 7141 //
     /* 125622 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 125625 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125629 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 125636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 125639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 125643 */   // MIs[0] ptr
     /* 125643 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 125647 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 125651 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15874>>  =>  (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 125651 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
     /* 125656 */   GIR_RootConstrainSelectedInstOperands,
     /* 125657 */   // GIR_Coverage, 7141,
     /* 125657 */   GIR_Done,
     /* 125658 */ // Label 2155: @125658
     /* 125658 */ GIM_Reject,
     /* 125659 */ // Label 2044: @125659
     /* 125659 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(125867),
     /* 125664 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125667 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 125675 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125679 */   GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(125720), // Rule ID 249 //
     /* 125684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 125687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 125694 */     // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 125694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 125697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 125709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 125714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125718 */     GIR_RootConstrainSelectedInstOperands,
     /* 125719 */     // GIR_Coverage, 249,
     /* 125719 */     GIR_EraseRootFromParent_Done,
     /* 125720 */   // Label 2157: @125720
     /* 125720 */   GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(125761), // Rule ID 250 //
     /* 125725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 125728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 125735 */     // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 125735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 125738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 125750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 125755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125759 */     GIR_RootConstrainSelectedInstOperands,
     /* 125760 */     // GIR_Coverage, 250,
     /* 125760 */     GIR_EraseRootFromParent_Done,
     /* 125761 */   // Label 2158: @125761
     /* 125761 */   GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(125797), // Rule ID 269 //
     /* 125766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 125769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 125776 */     // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 125776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 125779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125795 */     GIR_RootConstrainSelectedInstOperands,
     /* 125796 */     // GIR_Coverage, 269,
     /* 125796 */     GIR_EraseRootFromParent_Done,
     /* 125797 */   // Label 2159: @125797
     /* 125797 */   GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(125833), // Rule ID 290 //
     /* 125802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 125805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 125812 */     // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 125812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 125815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125831 */     GIR_RootConstrainSelectedInstOperands,
     /* 125832 */     // GIR_Coverage, 290,
     /* 125832 */     GIR_EraseRootFromParent_Done,
     /* 125833 */   // Label 2160: @125833
     /* 125833 */   GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(125866), // Rule ID 4175 //
     /* 125838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 125845 */     // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 125845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 125848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 125860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125864 */     GIR_RootConstrainSelectedInstOperands,
     /* 125865 */     // GIR_Coverage, 4175,
     /* 125865 */     GIR_EraseRootFromParent_Done,
     /* 125866 */   // Label 2161: @125866
     /* 125866 */   GIM_Reject,
     /* 125867 */ // Label 2156: @125867
     /* 125867 */ GIM_Reject,
     /* 125868 */ // Label 2045: @125868
     /* 125868 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(126245),
     /* 125873 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 125876 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 125880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125884 */   GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(125929), // Rule ID 4109 //
     /* 125889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 125892 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 125903 */     // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 125903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 125906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 125918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 125923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125927 */     GIR_RootConstrainSelectedInstOperands,
     /* 125928 */     // GIR_Coverage, 4109,
     /* 125928 */     GIR_EraseRootFromParent_Done,
     /* 125929 */   // Label 2163: @125929
     /* 125929 */   GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(125974), // Rule ID 4110 //
     /* 125934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 125937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 125948 */     // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 125948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 125951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 125958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 125963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 125968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 125972 */     GIR_RootConstrainSelectedInstOperands,
     /* 125973 */     // GIR_Coverage, 4110,
     /* 125973 */     GIR_EraseRootFromParent_Done,
     /* 125974 */   // Label 2164: @125974
     /* 125974 */   GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(126019), // Rule ID 4111 //
     /* 125979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 125982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 125986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 125993 */     // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 125993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 125996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 125998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126017 */     GIR_RootConstrainSelectedInstOperands,
     /* 126018 */     // GIR_Coverage, 4111,
     /* 126018 */     GIR_EraseRootFromParent_Done,
     /* 126019 */   // Label 2165: @126019
     /* 126019 */   GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(126064), // Rule ID 4112 //
     /* 126024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 126038 */     // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 126038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 126041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126062 */     GIR_RootConstrainSelectedInstOperands,
     /* 126063 */     // GIR_Coverage, 4112,
     /* 126063 */     GIR_EraseRootFromParent_Done,
     /* 126064 */   // Label 2166: @126064
     /* 126064 */   GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(126104), // Rule ID 4161 //
     /* 126069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 126083 */     // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 126083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 126086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126102 */     GIR_RootConstrainSelectedInstOperands,
     /* 126103 */     // GIR_Coverage, 4161,
     /* 126103 */     GIR_EraseRootFromParent_Done,
     /* 126104 */   // Label 2167: @126104
     /* 126104 */   GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(126144), // Rule ID 4164 //
     /* 126109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126112 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126116 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 126123 */     // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 126123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 126126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126142 */     GIR_RootConstrainSelectedInstOperands,
     /* 126143 */     // GIR_Coverage, 4164,
     /* 126143 */     GIR_EraseRootFromParent_Done,
     /* 126144 */   // Label 2168: @126144
     /* 126144 */   GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(126184), // Rule ID 4189 //
     /* 126149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126156 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 126163 */     // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 126166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126182 */     GIR_RootConstrainSelectedInstOperands,
     /* 126183 */     // GIR_Coverage, 4189,
     /* 126183 */     GIR_EraseRootFromParent_Done,
     /* 126184 */   // Label 2169: @126184
     /* 126184 */   GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(126224), // Rule ID 4190 //
     /* 126189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 126203 */     // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 126206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126222 */     GIR_RootConstrainSelectedInstOperands,
     /* 126223 */     // GIR_Coverage, 4190,
     /* 126223 */     GIR_EraseRootFromParent_Done,
     /* 126224 */   // Label 2170: @126224
     /* 126224 */   GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(126244), // Rule ID 6470 //
     /* 126229 */     // MIs[0] Rn
     /* 126229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 126233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 126237 */     // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 126237 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2s),
     /* 126242 */     GIR_RootConstrainSelectedInstOperands,
     /* 126243 */     // GIR_Coverage, 6470,
     /* 126243 */     GIR_Done,
     /* 126244 */   // Label 2171: @126244
     /* 126244 */   GIM_Reject,
     /* 126245 */ // Label 2162: @126245
     /* 126245 */ GIM_Reject,
     /* 126246 */ // Label 2046: @126246
     /* 126246 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(126623),
     /* 126251 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 126254 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 126258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 126262 */   GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(126307), // Rule ID 4123 //
     /* 126267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126270 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126274 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 126281 */     // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 126281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 126284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126305 */     GIR_RootConstrainSelectedInstOperands,
     /* 126306 */     // GIR_Coverage, 4123,
     /* 126306 */     GIR_EraseRootFromParent_Done,
     /* 126307 */   // Label 2173: @126307
     /* 126307 */   GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(126352), // Rule ID 4124 //
     /* 126312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 126326 */     // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 126326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 126329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126350 */     GIR_RootConstrainSelectedInstOperands,
     /* 126351 */     // GIR_Coverage, 4124,
     /* 126351 */     GIR_EraseRootFromParent_Done,
     /* 126352 */   // Label 2174: @126352
     /* 126352 */   GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(126397), // Rule ID 4125 //
     /* 126357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 126371 */     // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 126371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 126374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126395 */     GIR_RootConstrainSelectedInstOperands,
     /* 126396 */     // GIR_Coverage, 4125,
     /* 126396 */     GIR_EraseRootFromParent_Done,
     /* 126397 */   // Label 2175: @126397
     /* 126397 */   GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(126442), // Rule ID 4126 //
     /* 126402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 126416 */     // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 126416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 126419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126440 */     GIR_RootConstrainSelectedInstOperands,
     /* 126441 */     // GIR_Coverage, 4126,
     /* 126441 */     GIR_EraseRootFromParent_Done,
     /* 126442 */   // Label 2176: @126442
     /* 126442 */   GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(126482), // Rule ID 4169 //
     /* 126447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 126461 */     // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 126461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 126464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126480 */     GIR_RootConstrainSelectedInstOperands,
     /* 126481 */     // GIR_Coverage, 4169,
     /* 126481 */     GIR_EraseRootFromParent_Done,
     /* 126482 */   // Label 2177: @126482
     /* 126482 */   GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(126522), // Rule ID 4173 //
     /* 126487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 126501 */     // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 126501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 126504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126516 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126520 */     GIR_RootConstrainSelectedInstOperands,
     /* 126521 */     // GIR_Coverage, 4173,
     /* 126521 */     GIR_EraseRootFromParent_Done,
     /* 126522 */   // Label 2178: @126522
     /* 126522 */   GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(126562), // Rule ID 4196 //
     /* 126527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 126541 */     // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 126544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126560 */     GIR_RootConstrainSelectedInstOperands,
     /* 126561 */     // GIR_Coverage, 4196,
     /* 126561 */     GIR_EraseRootFromParent_Done,
     /* 126562 */   // Label 2179: @126562
     /* 126562 */   GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(126602), // Rule ID 4197 //
     /* 126567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 126581 */     // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 126584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126600 */     GIR_RootConstrainSelectedInstOperands,
     /* 126601 */     // GIR_Coverage, 4197,
     /* 126601 */     GIR_EraseRootFromParent_Done,
     /* 126602 */   // Label 2180: @126602
     /* 126602 */   GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(126622), // Rule ID 6467 //
     /* 126607 */     // MIs[0] Rn
     /* 126607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 126611 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 126615 */     // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 126615 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2d),
     /* 126620 */     GIR_RootConstrainSelectedInstOperands,
     /* 126621 */     // GIR_Coverage, 6467,
     /* 126621 */     GIR_Done,
     /* 126622 */   // Label 2181: @126622
     /* 126622 */   GIM_Reject,
     /* 126623 */ // Label 2172: @126623
     /* 126623 */ GIM_Reject,
     /* 126624 */ // Label 2047: @126624
     /* 126624 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(127001),
     /* 126629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 126632 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 126636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126640 */   GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(126685), // Rule ID 4115 //
     /* 126645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 126659 */     // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 126659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 126662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126683 */     GIR_RootConstrainSelectedInstOperands,
     /* 126684 */     // GIR_Coverage, 4115,
     /* 126684 */     GIR_EraseRootFromParent_Done,
     /* 126685 */   // Label 2183: @126685
     /* 126685 */   GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(126730), // Rule ID 4116 //
     /* 126690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 126704 */     // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 126704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 126707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126728 */     GIR_RootConstrainSelectedInstOperands,
     /* 126729 */     // GIR_Coverage, 4116,
     /* 126729 */     GIR_EraseRootFromParent_Done,
     /* 126730 */   // Label 2184: @126730
     /* 126730 */   GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(126775), // Rule ID 4117 //
     /* 126735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 126749 */     // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 126749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 126752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126773 */     GIR_RootConstrainSelectedInstOperands,
     /* 126774 */     // GIR_Coverage, 4117,
     /* 126774 */     GIR_EraseRootFromParent_Done,
     /* 126775 */   // Label 2185: @126775
     /* 126775 */   GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(126820), // Rule ID 4118 //
     /* 126780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 126794 */     // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 126794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 126797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 126809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 126814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126818 */     GIR_RootConstrainSelectedInstOperands,
     /* 126819 */     // GIR_Coverage, 4118,
     /* 126819 */     GIR_EraseRootFromParent_Done,
     /* 126820 */   // Label 2186: @126820
     /* 126820 */   GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(126860), // Rule ID 4163 //
     /* 126825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 126839 */     // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 126839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 126842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126858 */     GIR_RootConstrainSelectedInstOperands,
     /* 126859 */     // GIR_Coverage, 4163,
     /* 126859 */     GIR_EraseRootFromParent_Done,
     /* 126860 */   // Label 2187: @126860
     /* 126860 */   GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(126900), // Rule ID 4165 //
     /* 126865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 126879 */     // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 126879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 126882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126898 */     GIR_RootConstrainSelectedInstOperands,
     /* 126899 */     // GIR_Coverage, 4165,
     /* 126899 */     GIR_EraseRootFromParent_Done,
     /* 126900 */   // Label 2188: @126900
     /* 126900 */   GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(126940), // Rule ID 4191 //
     /* 126905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 126919 */     // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 126922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126938 */     GIR_RootConstrainSelectedInstOperands,
     /* 126939 */     // GIR_Coverage, 4191,
     /* 126939 */     GIR_EraseRootFromParent_Done,
     /* 126940 */   // Label 2189: @126940
     /* 126940 */   GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(126980), // Rule ID 4193 //
     /* 126945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 126948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 126952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 126959 */     // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 126959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 126962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 126964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 126969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 126974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 126978 */     GIR_RootConstrainSelectedInstOperands,
     /* 126979 */     // GIR_Coverage, 4193,
     /* 126979 */     GIR_EraseRootFromParent_Done,
     /* 126980 */   // Label 2190: @126980
     /* 126980 */   GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(127000), // Rule ID 6469 //
     /* 126985 */     // MIs[0] Rn
     /* 126985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 126989 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 126993 */     // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 126993 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4h),
     /* 126998 */     GIR_RootConstrainSelectedInstOperands,
     /* 126999 */     // GIR_Coverage, 6469,
     /* 126999 */     GIR_Done,
     /* 127000 */   // Label 2191: @127000
     /* 127000 */   GIM_Reject,
     /* 127001 */ // Label 2182: @127001
     /* 127001 */ GIM_Reject,
     /* 127002 */ // Label 2048: @127002
     /* 127002 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(127379),
     /* 127007 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 127010 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 127014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 127018 */   GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(127063), // Rule ID 4127 //
     /* 127023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127026 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 127037 */     // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 127037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 127040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127061 */     GIR_RootConstrainSelectedInstOperands,
     /* 127062 */     // GIR_Coverage, 4127,
     /* 127062 */     GIR_EraseRootFromParent_Done,
     /* 127063 */   // Label 2193: @127063
     /* 127063 */   GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(127108), // Rule ID 4128 //
     /* 127068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 127082 */     // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 127082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 127085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127106 */     GIR_RootConstrainSelectedInstOperands,
     /* 127107 */     // GIR_Coverage, 4128,
     /* 127107 */     GIR_EraseRootFromParent_Done,
     /* 127108 */   // Label 2194: @127108
     /* 127108 */   GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(127153), // Rule ID 4129 //
     /* 127113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 127127 */     // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 127127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 127130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127151 */     GIR_RootConstrainSelectedInstOperands,
     /* 127152 */     // GIR_Coverage, 4129,
     /* 127152 */     GIR_EraseRootFromParent_Done,
     /* 127153 */   // Label 2195: @127153
     /* 127153 */   GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(127198), // Rule ID 4130 //
     /* 127158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 127172 */     // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 127172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 127175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127196 */     GIR_RootConstrainSelectedInstOperands,
     /* 127197 */     // GIR_Coverage, 4130,
     /* 127197 */     GIR_EraseRootFromParent_Done,
     /* 127198 */   // Label 2196: @127198
     /* 127198 */   GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(127238), // Rule ID 4168 //
     /* 127203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 127217 */     // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 127217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 127220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127236 */     GIR_RootConstrainSelectedInstOperands,
     /* 127237 */     // GIR_Coverage, 4168,
     /* 127237 */     GIR_EraseRootFromParent_Done,
     /* 127238 */   // Label 2197: @127238
     /* 127238 */   GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(127278), // Rule ID 4172 //
     /* 127243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 127257 */     // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 127257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 127260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127276 */     GIR_RootConstrainSelectedInstOperands,
     /* 127277 */     // GIR_Coverage, 4172,
     /* 127277 */     GIR_EraseRootFromParent_Done,
     /* 127278 */   // Label 2198: @127278
     /* 127278 */   GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(127318), // Rule ID 4198 //
     /* 127283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127290 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 127297 */     // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 127297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 127300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127316 */     GIR_RootConstrainSelectedInstOperands,
     /* 127317 */     // GIR_Coverage, 4198,
     /* 127317 */     GIR_EraseRootFromParent_Done,
     /* 127318 */   // Label 2199: @127318
     /* 127318 */   GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(127358), // Rule ID 4199 //
     /* 127323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 127337 */     // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 127337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 127340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127356 */     GIR_RootConstrainSelectedInstOperands,
     /* 127357 */     // GIR_Coverage, 4199,
     /* 127357 */     GIR_EraseRootFromParent_Done,
     /* 127358 */   // Label 2200: @127358
     /* 127358 */   GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(127378), // Rule ID 6466 //
     /* 127363 */     // MIs[0] Rn
     /* 127363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 127367 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 127371 */     // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 127371 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4s),
     /* 127376 */     GIR_RootConstrainSelectedInstOperands,
     /* 127377 */     // GIR_Coverage, 6466,
     /* 127377 */     GIR_Done,
     /* 127378 */   // Label 2201: @127378
     /* 127378 */   GIM_Reject,
     /* 127379 */ // Label 2192: @127379
     /* 127379 */ GIM_Reject,
     /* 127380 */ // Label 2049: @127380
     /* 127380 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(127587),
     /* 127385 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 127388 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 127392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127396 */   GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(127441), // Rule ID 4113 //
     /* 127401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 127415 */     // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 127415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 127418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127439 */     GIR_RootConstrainSelectedInstOperands,
     /* 127440 */     // GIR_Coverage, 4113,
     /* 127440 */     GIR_EraseRootFromParent_Done,
     /* 127441 */   // Label 2203: @127441
     /* 127441 */   GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(127486), // Rule ID 4114 //
     /* 127446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 127460 */     // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 127460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 127463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127484 */     GIR_RootConstrainSelectedInstOperands,
     /* 127485 */     // GIR_Coverage, 4114,
     /* 127485 */     GIR_EraseRootFromParent_Done,
     /* 127486 */   // Label 2204: @127486
     /* 127486 */   GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(127526), // Rule ID 4162 //
     /* 127491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127494 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127498 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 127505 */     // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 127505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 127508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127524 */     GIR_RootConstrainSelectedInstOperands,
     /* 127525 */     // GIR_Coverage, 4162,
     /* 127525 */     GIR_EraseRootFromParent_Done,
     /* 127526 */   // Label 2205: @127526
     /* 127526 */   GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(127566), // Rule ID 4192 //
     /* 127531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 127545 */     // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 127545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 127548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127564 */     GIR_RootConstrainSelectedInstOperands,
     /* 127565 */     // GIR_Coverage, 4192,
     /* 127565 */     GIR_EraseRootFromParent_Done,
     /* 127566 */   // Label 2206: @127566
     /* 127566 */   GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(127586), // Rule ID 6468 //
     /* 127571 */     // MIs[0] Rn
     /* 127571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 127575 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 127579 */     // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 127579 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8b),
     /* 127584 */     GIR_RootConstrainSelectedInstOperands,
     /* 127585 */     // GIR_Coverage, 6468,
     /* 127585 */     GIR_Done,
     /* 127586 */   // Label 2207: @127586
     /* 127586 */   GIM_Reject,
     /* 127587 */ // Label 2202: @127587
     /* 127587 */ GIM_Reject,
     /* 127588 */ // Label 2050: @127588
     /* 127588 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(127965),
     /* 127593 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 127596 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 127600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 127604 */   GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(127649), // Rule ID 4131 //
     /* 127609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 127623 */     // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 127623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 127626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127647 */     GIR_RootConstrainSelectedInstOperands,
     /* 127648 */     // GIR_Coverage, 4131,
     /* 127648 */     GIR_EraseRootFromParent_Done,
     /* 127649 */   // Label 2209: @127649
     /* 127649 */   GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(127694), // Rule ID 4132 //
     /* 127654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 127668 */     // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 127668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 127671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127692 */     GIR_RootConstrainSelectedInstOperands,
     /* 127693 */     // GIR_Coverage, 4132,
     /* 127693 */     GIR_EraseRootFromParent_Done,
     /* 127694 */   // Label 2210: @127694
     /* 127694 */   GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(127739), // Rule ID 4133 //
     /* 127699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127706 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 127713 */     // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 127713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 127716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127737 */     GIR_RootConstrainSelectedInstOperands,
     /* 127738 */     // GIR_Coverage, 4133,
     /* 127738 */     GIR_EraseRootFromParent_Done,
     /* 127739 */   // Label 2211: @127739
     /* 127739 */   GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(127784), // Rule ID 4134 //
     /* 127744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 127758 */     // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 127758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 127761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 127773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 127778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127782 */     GIR_RootConstrainSelectedInstOperands,
     /* 127783 */     // GIR_Coverage, 4134,
     /* 127783 */     GIR_EraseRootFromParent_Done,
     /* 127784 */   // Label 2212: @127784
     /* 127784 */   GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(127824), // Rule ID 4171 //
     /* 127789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 127803 */     // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 127803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 127806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127822 */     GIR_RootConstrainSelectedInstOperands,
     /* 127823 */     // GIR_Coverage, 4171,
     /* 127823 */     GIR_EraseRootFromParent_Done,
     /* 127824 */   // Label 2213: @127824
     /* 127824 */   GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(127864), // Rule ID 4174 //
     /* 127829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 127843 */     // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 127843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 127846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127862 */     GIR_RootConstrainSelectedInstOperands,
     /* 127863 */     // GIR_Coverage, 4174,
     /* 127863 */     GIR_EraseRootFromParent_Done,
     /* 127864 */   // Label 2214: @127864
     /* 127864 */   GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(127904), // Rule ID 4200 //
     /* 127869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 127883 */     // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 127883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 127886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127902 */     GIR_RootConstrainSelectedInstOperands,
     /* 127903 */     // GIR_Coverage, 4200,
     /* 127903 */     GIR_EraseRootFromParent_Done,
     /* 127904 */   // Label 2215: @127904
     /* 127904 */   GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(127944), // Rule ID 4202 //
     /* 127909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 127923 */     // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 127923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 127926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 127928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 127933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 127938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 127942 */     GIR_RootConstrainSelectedInstOperands,
     /* 127943 */     // GIR_Coverage, 4202,
     /* 127943 */     GIR_EraseRootFromParent_Done,
     /* 127944 */   // Label 2216: @127944
     /* 127944 */   GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(127964), // Rule ID 6465 //
     /* 127949 */     // MIs[0] Rn
     /* 127949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 127953 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 127957 */     // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 127957 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8h),
     /* 127962 */     GIR_RootConstrainSelectedInstOperands,
     /* 127963 */     // GIR_Coverage, 6465,
     /* 127963 */     GIR_Done,
     /* 127964 */   // Label 2217: @127964
     /* 127964 */   GIM_Reject,
     /* 127965 */ // Label 2208: @127965
     /* 127965 */ GIM_Reject,
     /* 127966 */ // Label 2051: @127966
     /* 127966 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(128173),
     /* 127971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 127974 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 127978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 127982 */   GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(128027), // Rule ID 4135 //
     /* 127987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 127994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 128001 */     // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 128001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 128004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 128006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 128011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 128016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 128021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128025 */     GIR_RootConstrainSelectedInstOperands,
     /* 128026 */     // GIR_Coverage, 4135,
     /* 128026 */     GIR_EraseRootFromParent_Done,
     /* 128027 */   // Label 2219: @128027
     /* 128027 */   GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(128072), // Rule ID 4136 //
     /* 128032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 128039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 128046 */     // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 128046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 128049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 128051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 128056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 128061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 128066 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128070 */     GIR_RootConstrainSelectedInstOperands,
     /* 128071 */     // GIR_Coverage, 4136,
     /* 128071 */     GIR_EraseRootFromParent_Done,
     /* 128072 */   // Label 2220: @128072
     /* 128072 */   GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(128112), // Rule ID 4170 //
     /* 128077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 128084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 128091 */     // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 128091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 128094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 128096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 128101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 128106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128110 */     GIR_RootConstrainSelectedInstOperands,
     /* 128111 */     // GIR_Coverage, 4170,
     /* 128111 */     GIR_EraseRootFromParent_Done,
     /* 128112 */   // Label 2221: @128112
     /* 128112 */   GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(128152), // Rule ID 4201 //
     /* 128117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 128124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 128131 */     // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 128131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 128134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 128136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 128141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 128146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128150 */     GIR_RootConstrainSelectedInstOperands,
     /* 128151 */     // GIR_Coverage, 4201,
     /* 128151 */     GIR_EraseRootFromParent_Done,
     /* 128152 */   // Label 2222: @128152
     /* 128152 */   GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(128172), // Rule ID 6464 //
     /* 128157 */     // MIs[0] Rn
     /* 128157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128161 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128165 */     // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 128165 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev16b),
     /* 128170 */     GIR_RootConstrainSelectedInstOperands,
     /* 128171 */     // GIR_Coverage, 6464,
     /* 128171 */     GIR_Done,
     /* 128172 */   // Label 2223: @128172
     /* 128172 */   GIM_Reject,
     /* 128173 */ // Label 2218: @128173
     /* 128173 */ GIM_Reject,
     /* 128174 */ // Label 2052: @128174
     /* 128174 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(128237), // Rule ID 11081 //
     /* 128179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128182 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128185 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128193 */   // MIs[0] base
     /* 128193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128197 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128201 */   // (ld:{ *:[nxv2f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_D_IMM:{ *:[nxv2f16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128201 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128204 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 128208 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128213 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128216 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_D_IMM),
     /* 128221 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128223 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128226 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128228 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128231 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128235 */   GIR_RootConstrainSelectedInstOperands,
     /* 128236 */   // GIR_Coverage, 11081,
     /* 128236 */   GIR_EraseRootFromParent_Done,
     /* 128237 */ // Label 2224: @128237
     /* 128237 */ GIM_Reject,
     /* 128238 */ // Label 2053: @128238
     /* 128238 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(128301), // Rule ID 11087 //
     /* 128243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128246 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128249 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128257 */   // MIs[0] base
     /* 128257 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128261 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128265 */   // (ld:{ *:[nxv2f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_D_IMM:{ *:[nxv2f32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128265 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128268 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 128272 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128277 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128280 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128282 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_D_IMM),
     /* 128285 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128287 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128290 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128292 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128295 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128299 */   GIR_RootConstrainSelectedInstOperands,
     /* 128300 */   // GIR_Coverage, 11087,
     /* 128300 */   GIR_EraseRootFromParent_Done,
     /* 128301 */ // Label 2225: @128301
     /* 128301 */ GIM_Reject,
     /* 128302 */ // Label 2054: @128302
     /* 128302 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(128475),
     /* 128307 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128310 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128318 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128322 */   GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(128370), // Rule ID 11072 //
     /* 128327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128330 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128334 */     // (ld:{ *:[nxv2i64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1D_IMM:{ *:[nxv2i64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128334 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128337 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 128341 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128346 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128349 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
     /* 128354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128356 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128359 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128368 */     GIR_RootConstrainSelectedInstOperands,
     /* 128369 */     // GIR_Coverage, 11072,
     /* 128369 */     GIR_EraseRootFromParent_Done,
     /* 128370 */   // Label 2227: @128370
     /* 128370 */   GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(128418), // Rule ID 11090 //
     /* 128375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128378 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128382 */     // (ld:{ *:[nxv2f64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1D_IMM:{ *:[nxv2f64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128382 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128385 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 128389 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128394 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128397 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
     /* 128402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128404 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128407 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128416 */     GIR_RootConstrainSelectedInstOperands,
     /* 128417 */     // GIR_Coverage, 11090,
     /* 128417 */     GIR_EraseRootFromParent_Done,
     /* 128418 */   // Label 2228: @128418
     /* 128418 */   GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(128446), // Rule ID 11117 //
     /* 128423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128430 */     // (ld:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128435 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128444 */     GIR_RootConstrainSelectedInstOperands,
     /* 128445 */     // GIR_Coverage, 11117,
     /* 128445 */     GIR_EraseRootFromParent_Done,
     /* 128446 */   // Label 2229: @128446
     /* 128446 */   GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(128474), // Rule ID 11129 //
     /* 128451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128454 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128458 */     // (ld:{ *:[nxv2f64] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv2f64] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128463 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128472 */     GIR_RootConstrainSelectedInstOperands,
     /* 128473 */     // GIR_Coverage, 11129,
     /* 128473 */     GIR_EraseRootFromParent_Done,
     /* 128474 */   // Label 2230: @128474
     /* 128474 */   GIM_Reject,
     /* 128475 */ // Label 2226: @128475
     /* 128475 */ GIM_Reject,
     /* 128476 */ // Label 2055: @128476
     /* 128476 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(128539), // Rule ID 11078 //
     /* 128481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128487 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128491 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128495 */   // MIs[0] base
     /* 128495 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128499 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128503 */   // (ld:{ *:[nxv4f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_S_IMM:{ *:[nxv4f16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128503 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128506 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 128510 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128515 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128518 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_S_IMM),
     /* 128523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128525 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128528 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128537 */   GIR_RootConstrainSelectedInstOperands,
     /* 128538 */   // GIR_Coverage, 11078,
     /* 128538 */   GIR_EraseRootFromParent_Done,
     /* 128539 */ // Label 2231: @128539
     /* 128539 */ GIM_Reject,
     /* 128540 */ // Label 2056: @128540
     /* 128540 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(128713),
     /* 128545 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128548 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128556 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128560 */   GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(128608), // Rule ID 11060 //
     /* 128565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128568 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128572 */     // (ld:{ *:[nxv4i32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_IMM:{ *:[nxv4i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128572 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128575 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 128579 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128584 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128587 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
     /* 128592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128594 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128597 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128606 */     GIR_RootConstrainSelectedInstOperands,
     /* 128607 */     // GIR_Coverage, 11060,
     /* 128607 */     GIR_EraseRootFromParent_Done,
     /* 128608 */   // Label 2233: @128608
     /* 128608 */   GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(128656), // Rule ID 11084 //
     /* 128613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128616 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128620 */     // (ld:{ *:[nxv4f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_IMM:{ *:[nxv4f32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128620 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128623 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 128627 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128632 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128635 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
     /* 128640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128642 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128645 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128654 */     GIR_RootConstrainSelectedInstOperands,
     /* 128655 */     // GIR_Coverage, 11084,
     /* 128655 */     GIR_EraseRootFromParent_Done,
     /* 128656 */   // Label 2234: @128656
     /* 128656 */   GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(128684), // Rule ID 11113 //
     /* 128661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128664 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128668 */     // (ld:{ *:[nxv4i32] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv4i32] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128673 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128682 */     GIR_RootConstrainSelectedInstOperands,
     /* 128683 */     // GIR_Coverage, 11113,
     /* 128683 */     GIR_EraseRootFromParent_Done,
     /* 128684 */   // Label 2235: @128684
     /* 128684 */   GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(128712), // Rule ID 11125 //
     /* 128689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128692 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128696 */     // (ld:{ *:[nxv4f32] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv4f32] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128701 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128710 */     GIR_RootConstrainSelectedInstOperands,
     /* 128711 */     // GIR_Coverage, 11125,
     /* 128711 */     GIR_EraseRootFromParent_Done,
     /* 128712 */   // Label 2236: @128712
     /* 128712 */   GIM_Reject,
     /* 128713 */ // Label 2232: @128713
     /* 128713 */ GIM_Reject,
     /* 128714 */ // Label 2057: @128714
     /* 128714 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(128887),
     /* 128719 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128722 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128730 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128734 */   GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(128782), // Rule ID 11039 //
     /* 128739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128742 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128746 */     // (ld:{ *:[nxv8i16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_IMM:{ *:[nxv8i16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128746 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128749 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 128753 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128758 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128761 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
     /* 128766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128768 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128771 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128780 */     GIR_RootConstrainSelectedInstOperands,
     /* 128781 */     // GIR_Coverage, 11039,
     /* 128781 */     GIR_EraseRootFromParent_Done,
     /* 128782 */   // Label 2238: @128782
     /* 128782 */   GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(128830), // Rule ID 11075 //
     /* 128787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128790 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128794 */     // (ld:{ *:[nxv8f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_IMM:{ *:[nxv8f16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128794 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128797 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 128801 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128806 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128809 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
     /* 128814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128816 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128819 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128828 */     GIR_RootConstrainSelectedInstOperands,
     /* 128829 */     // GIR_Coverage, 11075,
     /* 128829 */     GIR_EraseRootFromParent_Done,
     /* 128830 */   // Label 2239: @128830
     /* 128830 */   GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(128858), // Rule ID 11109 //
     /* 128835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128842 */     // (ld:{ *:[nxv8i16] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv8i16] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128847 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128856 */     GIR_RootConstrainSelectedInstOperands,
     /* 128857 */     // GIR_Coverage, 11109,
     /* 128857 */     GIR_EraseRootFromParent_Done,
     /* 128858 */   // Label 2240: @128858
     /* 128858 */   GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(128886), // Rule ID 11121 //
     /* 128863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 128866 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 128870 */     // (ld:{ *:[nxv8f16] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv8f16] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 128873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128875 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128884 */     GIR_RootConstrainSelectedInstOperands,
     /* 128885 */     // GIR_Coverage, 11121,
     /* 128885 */     GIR_EraseRootFromParent_Done,
     /* 128886 */   // Label 2241: @128886
     /* 128886 */   GIM_Reject,
     /* 128887 */ // Label 2237: @128887
     /* 128887 */ GIM_Reject,
     /* 128888 */ // Label 2058: @128888
     /* 128888 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(128931), // Rule ID 2435 //
     /* 128893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128899 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 128907 */   // MIs[0] base
     /* 128907 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128911 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128915 */   // (ld:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_PXI:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128915 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_PXI),
     /* 128918 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pt]
     /* 128920 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128929 */   GIR_RootConstrainSelectedInstOperands,
     /* 128930 */   // GIR_Coverage, 2435,
     /* 128930 */   GIR_EraseRootFromParent_Done,
     /* 128931 */ // Label 2242: @128931
     /* 128931 */ GIM_Reject,
     /* 128932 */ // Label 2059: @128932
     /* 128932 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(129029),
     /* 128937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 128940 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 128944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 128948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 128952 */   GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(129000), // Rule ID 11007 //
     /* 128957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 128960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 128964 */     // (ld:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1B_IMM:{ *:[nxv16i8] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 128964 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 128967 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 128971 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 128976 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 128979 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 128981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1B_IMM),
     /* 128984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 128986 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 128989 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 128991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 128994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 128998 */     GIR_RootConstrainSelectedInstOperands,
     /* 128999 */     // GIR_Coverage, 11007,
     /* 128999 */     GIR_EraseRootFromParent_Done,
     /* 129000 */   // Label 2244: @129000
     /* 129000 */   GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(129028), // Rule ID 11105 //
     /* 129005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 129008 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 129012 */     // (ld:{ *:[nxv16i8] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv16i8] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 129012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 129015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 129017 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 129019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 129022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129026 */     GIR_RootConstrainSelectedInstOperands,
     /* 129027 */     // GIR_Coverage, 11105,
     /* 129027 */     GIR_EraseRootFromParent_Done,
     /* 129028 */   // Label 2245: @129028
     /* 129028 */   GIM_Reject,
     /* 129029 */ // Label 2243: @129029
     /* 129029 */ GIM_Reject,
     /* 129030 */ // Label 2060: @129030
     /* 129030 */ GIM_Reject,
     /* 129031 */ // Label 17: @129031
     /* 129031 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2248*/ GIMT_Encode4(130080),
     /* 129042 */ /*GILLT_s32*//*Label 2246*/ GIMT_Encode4(129050),
     /* 129046 */ /*GILLT_s64*//*Label 2247*/ GIMT_Encode4(129464),
     /* 129050 */ // Label 2246: @129050
     /* 129050 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(129463),
     /* 129055 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 129058 */   GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(129111), // Rule ID 251 //
     /* 129063 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129074 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 129085 */     // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 129085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroW),
     /* 129088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129109 */     GIR_RootConstrainSelectedInstOperands,
     /* 129110 */     // GIR_Coverage, 251,
     /* 129110 */     GIR_EraseRootFromParent_Done,
     /* 129111 */   // Label 2250: @129111
     /* 129111 */   GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(129164), // Rule ID 252 //
     /* 129116 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 129138 */     // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 129138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroX),
     /* 129141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129162 */     GIR_RootConstrainSelectedInstOperands,
     /* 129163 */     // GIR_Coverage, 252,
     /* 129163 */     GIR_EraseRootFromParent_Done,
     /* 129164 */   // Label 2251: @129164
     /* 129164 */   GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(129217), // Rule ID 255 //
     /* 129169 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 129191 */     // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 129191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroW),
     /* 129194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129215 */     GIR_RootConstrainSelectedInstOperands,
     /* 129216 */     // GIR_Coverage, 255,
     /* 129216 */     GIR_EraseRootFromParent_Done,
     /* 129217 */   // Label 2252: @129217
     /* 129217 */   GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(129270), // Rule ID 256 //
     /* 129222 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 129244 */     // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 129244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroX),
     /* 129247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129268 */     GIR_RootConstrainSelectedInstOperands,
     /* 129269 */     // GIR_Coverage, 256,
     /* 129269 */     GIR_EraseRootFromParent_Done,
     /* 129270 */   // Label 2253: @129270
     /* 129270 */   GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(129318), // Rule ID 272 //
     /* 129275 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129290 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 129297 */     // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 129297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWui),
     /* 129300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129316 */     GIR_RootConstrainSelectedInstOperands,
     /* 129317 */     // GIR_Coverage, 272,
     /* 129317 */     GIR_EraseRootFromParent_Done,
     /* 129318 */   // Label 2254: @129318
     /* 129318 */   GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(129366), // Rule ID 274 //
     /* 129323 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 129345 */     // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 129345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWui),
     /* 129348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129360 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129364 */     GIR_RootConstrainSelectedInstOperands,
     /* 129365 */     // GIR_Coverage, 274,
     /* 129365 */     GIR_EraseRootFromParent_Done,
     /* 129366 */   // Label 2255: @129366
     /* 129366 */   GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(129414), // Rule ID 293 //
     /* 129371 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 129393 */     // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 129393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHWi),
     /* 129396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129412 */     GIR_RootConstrainSelectedInstOperands,
     /* 129413 */     // GIR_Coverage, 293,
     /* 129413 */     GIR_EraseRootFromParent_Done,
     /* 129414 */   // Label 2256: @129414
     /* 129414 */   GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(129462), // Rule ID 295 //
     /* 129419 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 129430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 129441 */     // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 129441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBWi),
     /* 129444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129460 */     GIR_RootConstrainSelectedInstOperands,
     /* 129461 */     // GIR_Coverage, 295,
     /* 129461 */     GIR_EraseRootFromParent_Done,
     /* 129462 */   // Label 2257: @129462
     /* 129462 */   GIM_Reject,
     /* 129463 */ // Label 2249: @129463
     /* 129463 */ GIM_Reject,
     /* 129464 */ // Label 2247: @129464
     /* 129464 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(130079),
     /* 129469 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 129472 */   GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(129525), // Rule ID 253 //
     /* 129477 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 129499 */     // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 129499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroW),
     /* 129502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129523 */     GIR_RootConstrainSelectedInstOperands,
     /* 129524 */     // GIR_Coverage, 253,
     /* 129524 */     GIR_EraseRootFromParent_Done,
     /* 129525 */   // Label 2259: @129525
     /* 129525 */   GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(129578), // Rule ID 254 //
     /* 129530 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 129552 */     // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 129552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroX),
     /* 129555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129576 */     GIR_RootConstrainSelectedInstOperands,
     /* 129577 */     // GIR_Coverage, 254,
     /* 129577 */     GIR_EraseRootFromParent_Done,
     /* 129578 */   // Label 2260: @129578
     /* 129578 */   GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(129631), // Rule ID 257 //
     /* 129583 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 129605 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 129605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroW),
     /* 129608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129629 */     GIR_RootConstrainSelectedInstOperands,
     /* 129630 */     // GIR_Coverage, 257,
     /* 129630 */     GIR_EraseRootFromParent_Done,
     /* 129631 */   // Label 2261: @129631
     /* 129631 */   GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(129684), // Rule ID 258 //
     /* 129636 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 129658 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 129658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroX),
     /* 129661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129682 */     GIR_RootConstrainSelectedInstOperands,
     /* 129683 */     // GIR_Coverage, 258,
     /* 129683 */     GIR_EraseRootFromParent_Done,
     /* 129684 */   // Label 2262: @129684
     /* 129684 */   GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(129737), // Rule ID 259 //
     /* 129689 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 129696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 129711 */     // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 129711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroW),
     /* 129714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129735 */     GIR_RootConstrainSelectedInstOperands,
     /* 129736 */     // GIR_Coverage, 259,
     /* 129736 */     GIR_EraseRootFromParent_Done,
     /* 129737 */   // Label 2263: @129737
     /* 129737 */   GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(129790), // Rule ID 260 //
     /* 129742 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 129749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 129764 */     // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 129764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroX),
     /* 129767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 129779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 129784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129788 */     GIR_RootConstrainSelectedInstOperands,
     /* 129789 */     // GIR_Coverage, 260,
     /* 129789 */     GIR_EraseRootFromParent_Done,
     /* 129790 */   // Label 2264: @129790
     /* 129790 */   GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(129838), // Rule ID 273 //
     /* 129795 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 129817 */     // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 129817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXui),
     /* 129820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129836 */     GIR_RootConstrainSelectedInstOperands,
     /* 129837 */     // GIR_Coverage, 273,
     /* 129837 */     GIR_EraseRootFromParent_Done,
     /* 129838 */   // Label 2265: @129838
     /* 129838 */   GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(129886), // Rule ID 275 //
     /* 129843 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129854 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129858 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 129865 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 129865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXui),
     /* 129868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129884 */     GIR_RootConstrainSelectedInstOperands,
     /* 129885 */     // GIR_Coverage, 275,
     /* 129885 */     GIR_EraseRootFromParent_Done,
     /* 129886 */   // Label 2266: @129886
     /* 129886 */   GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(129934), // Rule ID 276 //
     /* 129891 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 129898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129902 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129906 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 129913 */     // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 129913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWui),
     /* 129916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129932 */     GIR_RootConstrainSelectedInstOperands,
     /* 129933 */     // GIR_Coverage, 276,
     /* 129933 */     GIR_EraseRootFromParent_Done,
     /* 129934 */   // Label 2267: @129934
     /* 129934 */   GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(129982), // Rule ID 294 //
     /* 129939 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 129946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129950 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 129954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 129961 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 129961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHXi),
     /* 129964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 129966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 129971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 129976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 129980 */     GIR_RootConstrainSelectedInstOperands,
     /* 129981 */     // GIR_Coverage, 294,
     /* 129981 */     GIR_EraseRootFromParent_Done,
     /* 129982 */   // Label 2268: @129982
     /* 129982 */   GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(130030), // Rule ID 296 //
     /* 129987 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 129994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 130009 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 130009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBXi),
     /* 130012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130028 */     GIR_RootConstrainSelectedInstOperands,
     /* 130029 */     // GIR_Coverage, 296,
     /* 130029 */     GIR_EraseRootFromParent_Done,
     /* 130030 */   // Label 2269: @130030
     /* 130030 */   GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(130078), // Rule ID 297 //
     /* 130035 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 130042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 130046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 130057 */     // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 130057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSWi),
     /* 130060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130076 */     GIR_RootConstrainSelectedInstOperands,
     /* 130077 */     // GIR_Coverage, 297,
     /* 130077 */     GIR_EraseRootFromParent_Done,
     /* 130078 */   // Label 2270: @130078
     /* 130078 */   GIM_Reject,
     /* 130079 */ // Label 2258: @130079
     /* 130079 */ GIM_Reject,
     /* 130080 */ // Label 2248: @130080
     /* 130080 */ GIM_Reject,
     /* 130081 */ // Label 18: @130081
     /* 130081 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2273*/ GIMT_Encode4(133129),
     /* 130092 */ /*GILLT_s32*//*Label 2271*/ GIMT_Encode4(130100),
     /* 130096 */ /*GILLT_s64*//*Label 2272*/ GIMT_Encode4(131639),
     /* 130100 */ // Label 2271: @130100
     /* 130100 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(130156), // Rule ID 233 //
     /* 130105 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130108 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 130130 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 130130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 130133 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130150 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130154 */   GIR_RootConstrainSelectedInstOperands,
     /* 130155 */   // GIR_Coverage, 233,
     /* 130155 */   GIR_EraseRootFromParent_Done,
     /* 130156 */ // Label 2274: @130156
     /* 130156 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(130212), // Rule ID 234 //
     /* 130161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130164 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130175 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130179 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 130186 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 130186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 130189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130206 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130210 */   GIR_RootConstrainSelectedInstOperands,
     /* 130211 */   // GIR_Coverage, 234,
     /* 130211 */   GIR_EraseRootFromParent_Done,
     /* 130212 */ // Label 2275: @130212
     /* 130212 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(130268), // Rule ID 235 //
     /* 130217 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130220 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130227 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130231 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130235 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 130242 */   // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 130242 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 130245 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130266 */   GIR_RootConstrainSelectedInstOperands,
     /* 130267 */   // GIR_Coverage, 235,
     /* 130267 */   GIR_EraseRootFromParent_Done,
     /* 130268 */ // Label 2276: @130268
     /* 130268 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(130324), // Rule ID 236 //
     /* 130273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 130298 */   // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 130298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 130301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130322 */   GIR_RootConstrainSelectedInstOperands,
     /* 130323 */   // GIR_Coverage, 236,
     /* 130323 */   GIR_EraseRootFromParent_Done,
     /* 130324 */ // Label 2277: @130324
     /* 130324 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(130380), // Rule ID 4159 //
     /* 130329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130332 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 130354 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 130354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 130357 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130378 */   GIR_RootConstrainSelectedInstOperands,
     /* 130379 */   // GIR_Coverage, 4159,
     /* 130379 */   GIR_EraseRootFromParent_Done,
     /* 130380 */ // Label 2278: @130380
     /* 130380 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(130436), // Rule ID 4160 //
     /* 130385 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 130410 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 130410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 130413 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130434 */   GIR_RootConstrainSelectedInstOperands,
     /* 130435 */   // GIR_Coverage, 4160,
     /* 130435 */   GIR_EraseRootFromParent_Done,
     /* 130436 */ // Label 2279: @130436
     /* 130436 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(130487), // Rule ID 270 //
     /* 130441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130444 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 130466 */   // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 130466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 130469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130481 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130485 */   GIR_RootConstrainSelectedInstOperands,
     /* 130486 */   // GIR_Coverage, 270,
     /* 130486 */   GIR_EraseRootFromParent_Done,
     /* 130487 */ // Label 2280: @130487
     /* 130487 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(130538), // Rule ID 271 //
     /* 130492 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130495 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130506 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130510 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 130517 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 130517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 130520 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130536 */   GIR_RootConstrainSelectedInstOperands,
     /* 130537 */   // GIR_Coverage, 271,
     /* 130537 */   GIR_EraseRootFromParent_Done,
     /* 130538 */ // Label 2281: @130538
     /* 130538 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(130597), // Rule ID 7115 //
     /* 130543 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 130546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130553 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 130556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 130571 */   // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
     /* 130571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 130574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 130591 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130595 */   GIR_RootConstrainSelectedInstOperands,
     /* 130596 */   // GIR_Coverage, 7115,
     /* 130596 */   GIR_EraseRootFromParent_Done,
     /* 130597 */ // Label 2282: @130597
     /* 130597 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(130656), // Rule ID 7117 //
     /* 130602 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 130605 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130612 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 130615 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130619 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130623 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 130630 */   // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
     /* 130630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 130633 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 130650 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130654 */   GIR_RootConstrainSelectedInstOperands,
     /* 130655 */   // GIR_Coverage, 7117,
     /* 130655 */   GIR_EraseRootFromParent_Done,
     /* 130656 */ // Label 2283: @130656
     /* 130656 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(130715), // Rule ID 7127 //
     /* 130661 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 130664 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130671 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 130674 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130678 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130682 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 130689 */   // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 130689 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 130692 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130713 */   GIR_RootConstrainSelectedInstOperands,
     /* 130714 */   // GIR_Coverage, 7127,
     /* 130714 */   GIR_EraseRootFromParent_Done,
     /* 130715 */ // Label 2284: @130715
     /* 130715 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(130774), // Rule ID 7129 //
     /* 130720 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 130723 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130730 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 130733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130737 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130741 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 130748 */   // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 130748 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 130751 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 130763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 130768 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130772 */   GIR_RootConstrainSelectedInstOperands,
     /* 130773 */   // GIR_Coverage, 7129,
     /* 130773 */   GIR_EraseRootFromParent_Done,
     /* 130774 */ // Label 2285: @130774
     /* 130774 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(130825), // Rule ID 291 //
     /* 130779 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 130804 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 130804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 130807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130823 */   GIR_RootConstrainSelectedInstOperands,
     /* 130824 */   // GIR_Coverage, 291,
     /* 130824 */   GIR_EraseRootFromParent_Done,
     /* 130825 */ // Label 2286: @130825
     /* 130825 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(130876), // Rule ID 292 //
     /* 130830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130833 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130844 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130848 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 130855 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 130855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 130858 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130870 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130874 */   GIR_RootConstrainSelectedInstOperands,
     /* 130875 */   // GIR_Coverage, 292,
     /* 130875 */   GIR_EraseRootFromParent_Done,
     /* 130876 */ // Label 2287: @130876
     /* 130876 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(130927), // Rule ID 4178 //
     /* 130881 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130884 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130891 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130895 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130899 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 130906 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 130906 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 130909 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130925 */   GIR_RootConstrainSelectedInstOperands,
     /* 130926 */   // GIR_Coverage, 4178,
     /* 130926 */   GIR_EraseRootFromParent_Done,
     /* 130927 */ // Label 2288: @130927
     /* 130927 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(130978), // Rule ID 4210 //
     /* 130932 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130935 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 130942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130946 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 130950 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 130957 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 130957 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 130960 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 130962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 130967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 130972 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 130976 */   GIR_RootConstrainSelectedInstOperands,
     /* 130977 */   // GIR_Coverage, 4210,
     /* 130977 */   GIR_EraseRootFromParent_Done,
     /* 130978 */ // Label 2289: @130978
     /* 130978 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(131029), // Rule ID 4211 //
     /* 130983 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 130986 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 130993 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 130997 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131001 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 131008 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 131011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131027 */   GIR_RootConstrainSelectedInstOperands,
     /* 131028 */   // GIR_Coverage, 4211,
     /* 131028 */   GIR_EraseRootFromParent_Done,
     /* 131029 */ // Label 2290: @131029
     /* 131029 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(131080), // Rule ID 4212 //
     /* 131034 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 131037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 131059 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 131062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131074 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131078 */   GIR_RootConstrainSelectedInstOperands,
     /* 131079 */   // GIR_Coverage, 4212,
     /* 131079 */   GIR_EraseRootFromParent_Done,
     /* 131080 */ // Label 2291: @131080
     /* 131080 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(131134), // Rule ID 7119 //
     /* 131085 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131088 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131095 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131102 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131106 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 131113 */   // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15879>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 131113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 131116 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131128 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131132 */   GIR_RootConstrainSelectedInstOperands,
     /* 131133 */   // GIR_Coverage, 7119,
     /* 131133 */   GIR_EraseRootFromParent_Done,
     /* 131134 */ // Label 2292: @131134
     /* 131134 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(131188), // Rule ID 7121 //
     /* 131139 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131142 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131149 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 131167 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15879>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 131170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131182 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131186 */   GIR_RootConstrainSelectedInstOperands,
     /* 131187 */   // GIR_Coverage, 7121,
     /* 131187 */   GIR_EraseRootFromParent_Done,
     /* 131188 */ // Label 2293: @131188
     /* 131188 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(131242), // Rule ID 7131 //
     /* 131193 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131196 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131203 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131210 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131214 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 131221 */   // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15887>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 131221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 131224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131240 */   GIR_RootConstrainSelectedInstOperands,
     /* 131241 */   // GIR_Coverage, 7131,
     /* 131241 */   GIR_EraseRootFromParent_Done,
     /* 131242 */ // Label 2294: @131242
     /* 131242 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(131296), // Rule ID 7133 //
     /* 131247 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131250 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131257 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131260 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131264 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131268 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 131275 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15887>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 131278 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131290 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131294 */   GIR_RootConstrainSelectedInstOperands,
     /* 131295 */   // GIR_Coverage, 7133,
     /* 131295 */   GIR_EraseRootFromParent_Done,
     /* 131296 */ // Label 2295: @131296
     /* 131296 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(131353), // Rule ID 7525 //
     /* 131301 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 131304 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131307 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131314 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131317 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131321 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131325 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 131332 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15868>>  =>  (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
     /* 131335 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131351 */   GIR_RootConstrainSelectedInstOperands,
     /* 131352 */   // GIR_Coverage, 7525,
     /* 131352 */   GIR_EraseRootFromParent_Done,
     /* 131353 */ // Label 2296: @131353
     /* 131353 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(131410), // Rule ID 7527 //
     /* 131358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 131361 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131364 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131371 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 131389 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15870>>  =>  (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 131389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
     /* 131392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 131394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 131404 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131408 */   GIR_RootConstrainSelectedInstOperands,
     /* 131409 */   // GIR_Coverage, 7527,
     /* 131409 */   GIR_EraseRootFromParent_Done,
     /* 131410 */ // Label 2297: @131410
     /* 131410 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(131450), // Rule ID 7105 //
     /* 131415 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 131418 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131421 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131428 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131435 */   // MIs[0] ptr
     /* 131435 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131439 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131443 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15868>>  =>  (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131443 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRB),
     /* 131448 */   GIR_RootConstrainSelectedInstOperands,
     /* 131449 */   // GIR_Coverage, 7105,
     /* 131449 */   GIR_Done,
     /* 131450 */ // Label 2298: @131450
     /* 131450 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(131490), // Rule ID 7107 //
     /* 131455 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 131458 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131461 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131468 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131475 */   // MIs[0] ptr
     /* 131475 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131479 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131483 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15870>>  =>  (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131483 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRH),
     /* 131488 */   GIR_RootConstrainSelectedInstOperands,
     /* 131489 */   // GIR_Coverage, 7107,
     /* 131489 */   GIR_Done,
     /* 131490 */ // Label 2299: @131490
     /* 131490 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(131527), // Rule ID 7111 //
     /* 131495 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131498 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131505 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 131508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131512 */   // MIs[0] ptr
     /* 131512 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131516 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131520 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15876>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131520 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 131525 */   GIR_RootConstrainSelectedInstOperands,
     /* 131526 */   // GIR_Coverage, 7111,
     /* 131526 */   GIR_Done,
     /* 131527 */ // Label 2300: @131527
     /* 131527 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(131564), // Rule ID 7113 //
     /* 131532 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131535 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131549 */   // MIs[0] ptr
     /* 131549 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131553 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131557 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_15868>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131557 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 131562 */   GIR_RootConstrainSelectedInstOperands,
     /* 131563 */   // GIR_Coverage, 7113,
     /* 131563 */   GIR_Done,
     /* 131564 */ // Label 2301: @131564
     /* 131564 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(131601), // Rule ID 7123 //
     /* 131569 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131572 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131579 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 131582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131586 */   // MIs[0] ptr
     /* 131586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131590 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131594 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15884>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131594 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 131599 */   GIR_RootConstrainSelectedInstOperands,
     /* 131600 */   // GIR_Coverage, 7123,
     /* 131600 */   GIR_Done,
     /* 131601 */ // Label 2302: @131601
     /* 131601 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(131638), // Rule ID 7125 //
     /* 131606 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 131609 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 131619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131623 */   // MIs[0] ptr
     /* 131623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 131627 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 131631 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_15870>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 131631 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 131636 */   GIR_RootConstrainSelectedInstOperands,
     /* 131637 */   // GIR_Coverage, 7125,
     /* 131637 */   GIR_Done,
     /* 131638 */ // Label 2303: @131638
     /* 131638 */ GIM_Reject,
     /* 131639 */ // Label 2272: @131639
     /* 131639 */ GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(133128),
     /* 131644 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 131647 */   GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(131732), // Rule ID 4137 //
     /* 131652 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 131674 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 131674 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 131677 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 131681 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 131696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 131701 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131705 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 131707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 131710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 131712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 131715 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 131721 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131726 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131731 */     // GIR_Coverage, 4137,
     /* 131731 */     GIR_EraseRootFromParent_Done,
     /* 131732 */   // Label 2305: @131732
     /* 131732 */   GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(131817), // Rule ID 4138 //
     /* 131737 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 131744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 131759 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 131759 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 131762 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 131766 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 131781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 131786 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131790 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 131792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 131795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 131797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 131800 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 131806 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131811 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131816 */     // GIR_Coverage, 4138,
     /* 131816 */     GIR_EraseRootFromParent_Done,
     /* 131817 */   // Label 2306: @131817
     /* 131817 */   GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(131902), // Rule ID 4139 //
     /* 131822 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131833 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 131844 */     // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 131844 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 131847 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 131851 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 131866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 131871 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131875 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 131877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 131880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 131882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 131885 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 131891 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131896 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131901 */     // GIR_Coverage, 4139,
     /* 131901 */     GIR_EraseRootFromParent_Done,
     /* 131902 */   // Label 2307: @131902
     /* 131902 */   GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(131987), // Rule ID 4140 //
     /* 131907 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 131914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 131922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 131929 */     // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 131929 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 131932 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 131936 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 131946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 131951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 131956 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 131960 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 131962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 131965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 131967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 131970 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 131976 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 131981 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 131986 */     // GIR_Coverage, 4140,
     /* 131986 */     GIR_EraseRootFromParent_Done,
     /* 131987 */   // Label 2308: @131987
     /* 131987 */   GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(132072), // Rule ID 4141 //
     /* 131992 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 131999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 132014 */     // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 132014 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132017 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 132021 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 132036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 132041 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132045 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132055 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132061 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132066 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132071 */     // GIR_Coverage, 4141,
     /* 132071 */     GIR_EraseRootFromParent_Done,
     /* 132072 */   // Label 2309: @132072
     /* 132072 */   GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(132157), // Rule ID 4142 //
     /* 132077 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 132084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132088 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132092 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 132099 */     // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 132099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 132106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 132121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 132126 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132130 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132140 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132146 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132151 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132156 */     // GIR_Coverage, 4142,
     /* 132156 */     GIR_EraseRootFromParent_Done,
     /* 132157 */   // Label 2310: @132157
     /* 132157 */   GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(132242), // Rule ID 4143 //
     /* 132162 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 132184 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 132184 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132187 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 132191 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 132206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 132211 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132215 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132225 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132231 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132236 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132241 */     // GIR_Coverage, 4143,
     /* 132241 */     GIR_EraseRootFromParent_Done,
     /* 132242 */   // Label 2311: @132242
     /* 132242 */   GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(132327), // Rule ID 4144 //
     /* 132247 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 132269 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 132269 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132272 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 132276 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 132291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 132296 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132300 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132310 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132316 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132321 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132326 */     // GIR_Coverage, 4144,
     /* 132326 */     GIR_EraseRootFromParent_Done,
     /* 132327 */   // Label 2312: @132327
     /* 132327 */   GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(132407), // Rule ID 4176 //
     /* 132332 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 132354 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 132354 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132357 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 132361 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132376 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132380 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132390 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132396 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132401 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132406 */     // GIR_Coverage, 4176,
     /* 132406 */     GIR_EraseRootFromParent_Done,
     /* 132407 */   // Label 2313: @132407
     /* 132407 */   GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(132487), // Rule ID 4177 //
     /* 132412 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 132419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 132434 */     // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 132434 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132437 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 132441 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132456 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132460 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132470 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132486 */     // GIR_Coverage, 4177,
     /* 132486 */     GIR_EraseRootFromParent_Done,
     /* 132487 */   // Label 2314: @132487
     /* 132487 */   GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(132567), // Rule ID 4179 //
     /* 132492 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 132514 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 132514 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132517 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 132521 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132536 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132540 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132550 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132561 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132566 */     // GIR_Coverage, 4179,
     /* 132566 */     GIR_EraseRootFromParent_Done,
     /* 132567 */   // Label 2315: @132567
     /* 132567 */   GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(132647), // Rule ID 4187 //
     /* 132572 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 132579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 132594 */     // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 132594 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132597 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 132601 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132616 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132620 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132630 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132636 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132641 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132646 */     // GIR_Coverage, 4187,
     /* 132646 */     GIR_EraseRootFromParent_Done,
     /* 132647 */   // Label 2316: @132647
     /* 132647 */   GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(132727), // Rule ID 4213 //
     /* 132652 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 132659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 132674 */     // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 132674 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132677 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 132681 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132696 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132700 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132710 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132716 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132721 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132726 */     // GIR_Coverage, 4213,
     /* 132726 */     GIR_EraseRootFromParent_Done,
     /* 132727 */   // Label 2317: @132727
     /* 132727 */   GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(132807), // Rule ID 4214 //
     /* 132732 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 132739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 132754 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 132754 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132757 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 132761 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132776 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132780 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132790 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132796 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132801 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132806 */     // GIR_Coverage, 4214,
     /* 132806 */     GIR_EraseRootFromParent_Done,
     /* 132807 */   // Label 2318: @132807
     /* 132807 */   GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(132887), // Rule ID 4215 //
     /* 132812 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 132834 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 132834 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132837 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 132841 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132856 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132860 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132870 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132876 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132881 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132886 */     // GIR_Coverage, 4215,
     /* 132886 */     GIR_EraseRootFromParent_Done,
     /* 132887 */   // Label 2319: @132887
     /* 132887 */   GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(132967), // Rule ID 4216 //
     /* 132892 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132903 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 132914 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 132914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 132921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 132931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 132936 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 132940 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 132945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 132947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 132950 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 132956 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132961 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 132966 */     // GIR_Coverage, 4216,
     /* 132966 */     GIR_EraseRootFromParent_Done,
     /* 132967 */   // Label 2320: @132967
     /* 132967 */   GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(133047), // Rule ID 4217 //
     /* 132972 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 132979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 132983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 132987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 132994 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 132994 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 132997 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 133001 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 133016 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133020 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 133022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 133025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 133027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 133030 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 133036 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 133041 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 133046 */     // GIR_Coverage, 4217,
     /* 133046 */     GIR_EraseRootFromParent_Done,
     /* 133047 */   // Label 2321: @133047
     /* 133047 */   GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(133127), // Rule ID 4218 //
     /* 133052 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 133059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 133063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 133074 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 133074 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 133077 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 133081 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 133096 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133100 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 133102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 133105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 133107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 133110 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 133116 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 133121 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 133126 */     // GIR_Coverage, 4218,
     /* 133126 */     GIR_EraseRootFromParent_Done,
     /* 133127 */   // Label 2322: @133127
     /* 133127 */   GIM_Reject,
     /* 133128 */ // Label 2304: @133128
     /* 133128 */ GIM_Reject,
     /* 133129 */ // Label 2273: @133129
     /* 133129 */ GIM_Reject,
     /* 133130 */ // Label 19: @133130
     /* 133130 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 2343*/ GIMT_Encode4(146655),
     /* 133141 */ /*GILLT_s8*//*Label 2323*/ GIMT_Encode4(133237),
     /* 133145 */ /*GILLT_s16*//*Label 2324*/ GIMT_Encode4(133604),
     /* 133149 */ /*GILLT_s32*//*Label 2325*/ GIMT_Encode4(134743),
     /* 133153 */ /*GILLT_s64*//*Label 2326*/ GIMT_Encode4(139338),
     /* 133157 */ /*GILLT_s128*//*Label 2327*/ GIMT_Encode4(143107),
     /* 133161 */ /*GILLT_v2s32*//*Label 2328*/ GIMT_Encode4(143313),
     /* 133165 */ /*GILLT_v2s64*//*Label 2329*/ GIMT_Encode4(143719),
     /* 133169 */ /*GILLT_v4s16*//*Label 2330*/ GIMT_Encode4(144169),
     /* 133173 */ /*GILLT_v4s32*//*Label 2331*/ GIMT_Encode4(144575),
     /* 133177 */ /*GILLT_v8s8*//*Label 2332*/ GIMT_Encode4(144981),
     /* 133181 */ /*GILLT_v8s16*//*Label 2333*/ GIMT_Encode4(145201),
     /* 133185 */ /*GILLT_v16s8*//*Label 2334*/ GIMT_Encode4(145607), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 133197 */ /*GILLT_nxv2s16*//*Label 2335*/ GIMT_Encode4(145827),
     /* 133201 */ /*GILLT_nxv2s32*//*Label 2336*/ GIMT_Encode4(145887),
     /* 133205 */ /*GILLT_nxv2s64*//*Label 2337*/ GIMT_Encode4(145947), GIMT_Encode4(0),
     /* 133213 */ /*GILLT_nxv4s16*//*Label 2338*/ GIMT_Encode4(146117),
     /* 133217 */ /*GILLT_nxv4s32*//*Label 2339*/ GIMT_Encode4(146177), GIMT_Encode4(0),
     /* 133225 */ /*GILLT_nxv8s16*//*Label 2340*/ GIMT_Encode4(146347),
     /* 133229 */ /*GILLT_nxv16s1*//*Label 2341*/ GIMT_Encode4(146517),
     /* 133233 */ /*GILLT_nxv16s8*//*Label 2342*/ GIMT_Encode4(146561),
     /* 133237 */ // Label 2323: @133237
     /* 133237 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(133603),
     /* 133242 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 133245 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 133249 */   GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(133317), // Rule ID 13488 //
     /* 133254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133262 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 133266 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133270 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133275 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 133279 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 133283 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 133287 */     // MIs[2] Operand 1
     /* 133287 */     // No operand predicates
     /* 133287 */     // MIs[0] Rn
     /* 133287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 133291 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 133295 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 133297 */     // (st (vector_extract:{ *:[i8] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 133297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 133300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 133304 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 133307 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 133309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 133315 */     GIR_RootConstrainSelectedInstOperands,
     /* 133316 */     // GIR_Coverage, 13488,
     /* 133316 */     GIR_EraseRootFromParent_Done,
     /* 133317 */   // Label 2345: @133317
     /* 133317 */   GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(133416), // Rule ID 13489 //
     /* 133322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 133334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133338 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133343 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 133347 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 133351 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 133355 */     // MIs[2] Operand 1
     /* 133355 */     // No operand predicates
     /* 133355 */     // MIs[0] Rn
     /* 133355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 133359 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 133363 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 133365 */     // (st (vector_extract:{ *:[i8] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 133365 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 133368 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 133372 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133377 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 133380 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 133384 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 133387 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133392 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 133400 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133403 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 133406 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 133408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 133414 */     GIR_RootConstrainSelectedInstOperands,
     /* 133415 */     // GIR_Coverage, 13489,
     /* 133415 */     GIR_EraseRootFromParent_Done,
     /* 133416 */   // Label 2346: @133416
     /* 133416 */   GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(133465), // Rule ID 307 //
     /* 133421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 133424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 133428 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133432 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 133439 */     // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBroW FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 133439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroW),
     /* 133442 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 133444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 133454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 133459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133463 */     GIR_RootConstrainSelectedInstOperands,
     /* 133464 */     // GIR_Coverage, 307,
     /* 133464 */     GIR_EraseRootFromParent_Done,
     /* 133465 */   // Label 2347: @133465
     /* 133465 */   GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(133514), // Rule ID 308 //
     /* 133470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 133473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 133477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 133488 */     // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBroX FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 133488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroX),
     /* 133491 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 133493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 133503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 133508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133512 */     GIR_RootConstrainSelectedInstOperands,
     /* 133513 */     // GIR_Coverage, 308,
     /* 133513 */     GIR_EraseRootFromParent_Done,
     /* 133514 */   // Label 2348: @133514
     /* 133514 */   GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(133558), // Rule ID 317 //
     /* 133519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 133522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 133526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 133537 */     // (st FPR8Op:{ *:[i8] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBui FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 133537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBui),
     /* 133540 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 133542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 133552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133556 */     GIR_RootConstrainSelectedInstOperands,
     /* 133557 */     // GIR_Coverage, 317,
     /* 133557 */     GIR_EraseRootFromParent_Done,
     /* 133558 */   // Label 2349: @133558
     /* 133558 */   GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(133602), // Rule ID 325 //
     /* 133563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 133566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 133570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 133581 */     // (st FPR8Op:{ *:[i8] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURBi FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 133581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBi),
     /* 133584 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 133586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 133596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 133600 */     GIR_RootConstrainSelectedInstOperands,
     /* 133601 */     // GIR_Coverage, 325,
     /* 133601 */     GIR_EraseRootFromParent_Done,
     /* 133602 */   // Label 2350: @133602
     /* 133602 */   GIM_Reject,
     /* 133603 */ // Label 2344: @133603
     /* 133603 */ GIM_Reject,
     /* 133604 */ // Label 2324: @133604
     /* 133604 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(134742),
     /* 133609 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 133612 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 133616 */   GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(133715), // Rule ID 4551 //
     /* 133621 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133625 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133629 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 133633 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133637 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133642 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 133646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 133652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 133659 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 133659 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 133662 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133666 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133671 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 133677 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 133682 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 133690 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 133703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 133708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 133713 */     GIR_RootConstrainSelectedInstOperands,
     /* 133714 */     // GIR_Coverage, 4551,
     /* 133714 */     GIR_EraseRootFromParent_Done,
     /* 133715 */   // Label 2352: @133715
     /* 133715 */   GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(133814), // Rule ID 4552 //
     /* 133720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 133732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133736 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133741 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 133745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133749 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 133751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 133758 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 133758 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 133761 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133765 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133770 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 133776 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 133781 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 133789 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 133802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 133807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 133812 */     GIR_RootConstrainSelectedInstOperands,
     /* 133813 */     // GIR_Coverage, 4552,
     /* 133813 */     GIR_EraseRootFromParent_Done,
     /* 133814 */   // Label 2353: @133814
     /* 133814 */   GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(133913), // Rule ID 13486 //
     /* 133819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133840 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 133844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133848 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 133850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 133857 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 133857 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 133860 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133864 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133869 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 133875 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 133880 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 133888 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 133901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 133906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 133911 */     GIR_RootConstrainSelectedInstOperands,
     /* 133912 */     // GIR_Coverage, 13486,
     /* 133912 */     GIR_EraseRootFromParent_Done,
     /* 133913 */   // Label 2354: @133913
     /* 133913 */   GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(134012), // Rule ID 13487 //
     /* 133918 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 133922 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 133926 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133930 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 133934 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133939 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 133943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 133947 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 133949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 133956 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 133956 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 133959 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133963 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133968 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 133974 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 133979 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 133987 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 133995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 134000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 134005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134010 */     GIR_RootConstrainSelectedInstOperands,
     /* 134011 */     // GIR_Coverage, 13487,
     /* 134011 */     GIR_EraseRootFromParent_Done,
     /* 134012 */   // Label 2355: @134012
     /* 134012 */   GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(134106), // Rule ID 4580 //
     /* 134017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134038 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134046 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 134055 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 134055 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134058 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134062 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134067 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134073 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134078 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 134086 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134104 */     GIR_RootConstrainSelectedInstOperands,
     /* 134105 */     // GIR_Coverage, 4580,
     /* 134105 */     GIR_EraseRootFromParent_Done,
     /* 134106 */   // Label 2356: @134106
     /* 134106 */   GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(134200), // Rule ID 4607 //
     /* 134111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134119 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134123 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134132 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134140 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 134149 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 134149 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134152 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134156 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134161 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134167 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134172 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 134180 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134198 */     GIR_RootConstrainSelectedInstOperands,
     /* 134199 */     // GIR_Coverage, 4607,
     /* 134199 */     GIR_EraseRootFromParent_Done,
     /* 134200 */   // Label 2357: @134200
     /* 134200 */   GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(134294), // Rule ID 13485 //
     /* 134205 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134209 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134213 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 134217 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134221 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134226 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134234 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 134243 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 134243 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134246 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134250 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134255 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134261 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134266 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 134274 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134287 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134292 */     GIR_RootConstrainSelectedInstOperands,
     /* 134293 */     // GIR_Coverage, 13485,
     /* 134293 */     GIR_EraseRootFromParent_Done,
     /* 134294 */   // Label 2358: @134294
     /* 134294 */   GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(134388), // Rule ID 13491 //
     /* 134299 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134303 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134307 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 134311 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134315 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134320 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134328 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 134337 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 134337 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134340 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134344 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134349 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134355 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134360 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 134368 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134381 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134386 */     GIR_RootConstrainSelectedInstOperands,
     /* 134387 */     // GIR_Coverage, 13491,
     /* 134387 */     GIR_EraseRootFromParent_Done,
     /* 134388 */   // Label 2359: @134388
     /* 134388 */   GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(134456), // Rule ID 6541 //
     /* 134393 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134397 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134401 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134405 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134409 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 134418 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 134422 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 134426 */     // MIs[2] Operand 1
     /* 134426 */     // No operand predicates
     /* 134426 */     // MIs[0] Rn
     /* 134426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 134430 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 134434 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 134436 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 134436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 134439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 134443 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 134446 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 134448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 134454 */     GIR_RootConstrainSelectedInstOperands,
     /* 134455 */     // GIR_Coverage, 6541,
     /* 134455 */     GIR_EraseRootFromParent_Done,
     /* 134456 */   // Label 2360: @134456
     /* 134456 */   GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(134555), // Rule ID 6546 //
     /* 134461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 134473 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134477 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134482 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 134486 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 134490 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 134494 */     // MIs[2] Operand 1
     /* 134494 */     // No operand predicates
     /* 134494 */     // MIs[0] Rn
     /* 134494 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 134498 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 134502 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 134504 */     // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 134504 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 134507 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 134511 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134516 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 134519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 134523 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 134526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134531 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 134536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 134539 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134542 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 134545 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 134547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 134553 */     GIR_RootConstrainSelectedInstOperands,
     /* 134554 */     // GIR_Coverage, 6546,
     /* 134554 */     GIR_EraseRootFromParent_Done,
     /* 134555 */   // Label 2361: @134555
     /* 134555 */   GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(134604), // Rule ID 309 //
     /* 134560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 134563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 134578 */     // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 134578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 134581 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 134583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 134593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 134598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 134602 */     GIR_RootConstrainSelectedInstOperands,
     /* 134603 */     // GIR_Coverage, 309,
     /* 134603 */     GIR_EraseRootFromParent_Done,
     /* 134604 */   // Label 2362: @134604
     /* 134604 */   GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(134653), // Rule ID 310 //
     /* 134609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 134612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 134627 */     // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 134627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 134630 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 134632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 134642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 134647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 134651 */     GIR_RootConstrainSelectedInstOperands,
     /* 134652 */     // GIR_Coverage, 310,
     /* 134652 */     GIR_EraseRootFromParent_Done,
     /* 134653 */   // Label 2363: @134653
     /* 134653 */   GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(134697), // Rule ID 318 //
     /* 134658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 134661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 134676 */     // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 134676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 134679 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 134681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 134695 */     GIR_RootConstrainSelectedInstOperands,
     /* 134696 */     // GIR_Coverage, 318,
     /* 134696 */     GIR_EraseRootFromParent_Done,
     /* 134697 */   // Label 2364: @134697
     /* 134697 */   GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(134741), // Rule ID 326 //
     /* 134702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 134705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 134720 */     // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 134720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 134723 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 134725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 134735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 134739 */     GIR_RootConstrainSelectedInstOperands,
     /* 134740 */     // GIR_Coverage, 326,
     /* 134740 */     GIR_EraseRootFromParent_Done,
     /* 134741 */   // Label 2365: @134741
     /* 134741 */   GIM_Reject,
     /* 134742 */ // Label 2351: @134742
     /* 134742 */ GIM_Reject,
     /* 134743 */ // Label 2325: @134743
     /* 134743 */ GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(134856), // Rule ID 4549 //
     /* 134748 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 134751 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 134755 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 134762 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134766 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134770 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134774 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134778 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134783 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134787 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134791 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134793 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 134800 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 134800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134812 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134818 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134823 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 134831 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 134844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 134849 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134854 */   GIR_RootConstrainSelectedInstOperands,
     /* 134855 */   // GIR_Coverage, 4549,
     /* 134855 */   GIR_EraseRootFromParent_Done,
     /* 134856 */ // Label 2366: @134856
     /* 134856 */ GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(134969), // Rule ID 4550 //
     /* 134861 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 134864 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 134868 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 134875 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134879 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134883 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134887 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134891 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134896 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 134900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 134904 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 134906 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 134913 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 134913 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 134916 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134920 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134925 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 134931 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 134936 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 134944 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 134952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 134957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 134962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 134967 */   GIR_RootConstrainSelectedInstOperands,
     /* 134968 */   // GIR_Coverage, 4550,
     /* 134968 */   GIR_EraseRootFromParent_Done,
     /* 134969 */ // Label 2367: @134969
     /* 134969 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(135075), // Rule ID 4553 //
     /* 134974 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 134977 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 134981 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 134985 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 134989 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134993 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 134997 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135002 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135010 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135012 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 135019 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 135019 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135022 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135026 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135031 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135037 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135042 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135047 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 135050 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135068 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135073 */   GIR_RootConstrainSelectedInstOperands,
     /* 135074 */   // GIR_Coverage, 4553,
     /* 135074 */   GIR_EraseRootFromParent_Done,
     /* 135075 */ // Label 2368: @135075
     /* 135075 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(135181), // Rule ID 4554 //
     /* 135080 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135083 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135087 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135091 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135095 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 135099 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135103 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135108 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135112 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135116 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135118 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 135125 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 135125 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135128 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135132 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135137 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135143 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135148 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 135156 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135179 */   GIR_RootConstrainSelectedInstOperands,
     /* 135180 */   // GIR_Coverage, 4554,
     /* 135180 */   GIR_EraseRootFromParent_Done,
     /* 135181 */ // Label 2369: @135181
     /* 135181 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(135287), // Rule ID 4555 //
     /* 135186 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135189 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135193 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135197 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135201 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 135205 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135209 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135214 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135222 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135224 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 135231 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 135231 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135234 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135238 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135243 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135249 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135254 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 135262 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135280 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135285 */   GIR_RootConstrainSelectedInstOperands,
     /* 135286 */   // GIR_Coverage, 4555,
     /* 135286 */   GIR_EraseRootFromParent_Done,
     /* 135287 */ // Label 2370: @135287
     /* 135287 */ GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(135393), // Rule ID 4556 //
     /* 135292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135295 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135299 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135303 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135307 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 135311 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135315 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135320 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135328 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135330 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 135337 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 135337 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135340 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135344 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135349 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135355 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135360 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 135368 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135386 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135391 */   GIR_RootConstrainSelectedInstOperands,
     /* 135392 */   // GIR_Coverage, 4556,
     /* 135392 */   GIR_EraseRootFromParent_Done,
     /* 135393 */ // Label 2371: @135393
     /* 135393 */ GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(135499), // Rule ID 13493 //
     /* 135398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135401 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135405 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135409 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135413 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 135417 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135421 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 135426 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135430 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135434 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135436 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 135443 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 135443 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135446 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135450 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135455 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135461 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135466 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 135471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 135474 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135492 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135497 */   GIR_RootConstrainSelectedInstOperands,
     /* 135498 */   // GIR_Coverage, 13493,
     /* 135498 */   GIR_EraseRootFromParent_Done,
     /* 135499 */ // Label 2372: @135499
     /* 135499 */ GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(135605), // Rule ID 13494 //
     /* 135504 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135507 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135511 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135515 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135519 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 135523 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135527 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 135532 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135536 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135540 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135542 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 135549 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 135549 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135552 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135556 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135561 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135567 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135572 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 135577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 135580 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 135593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 135598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135603 */   GIR_RootConstrainSelectedInstOperands,
     /* 135604 */   // GIR_Coverage, 13494,
     /* 135604 */   GIR_EraseRootFromParent_Done,
     /* 135605 */ // Label 2373: @135605
     /* 135605 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(135713), // Rule ID 4579 //
     /* 135610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135613 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135617 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 135624 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135628 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135632 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 135636 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135640 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135645 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135653 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135655 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 135662 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 135662 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 135665 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135669 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135674 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 135680 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 135685 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 135693 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 135706 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135711 */   GIR_RootConstrainSelectedInstOperands,
     /* 135712 */   // GIR_Coverage, 4579,
     /* 135712 */   GIR_EraseRootFromParent_Done,
     /* 135713 */ // Label 2374: @135713
     /* 135713 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(135814), // Rule ID 4581 //
     /* 135718 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135721 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135725 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135729 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135733 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 135737 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135741 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135746 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135754 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135756 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 135763 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 135763 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135766 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135770 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135775 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135781 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135786 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 135794 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 135807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135812 */   GIR_RootConstrainSelectedInstOperands,
     /* 135813 */   // GIR_Coverage, 4581,
     /* 135813 */   GIR_EraseRootFromParent_Done,
     /* 135814 */ // Label 2375: @135814
     /* 135814 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(135915), // Rule ID 4582 //
     /* 135819 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135822 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135826 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135830 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135834 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 135838 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135842 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135847 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135855 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135857 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 135864 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 135864 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 135867 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135871 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135876 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 135882 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 135887 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 135895 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 135898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 135903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 135908 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 135913 */   GIR_RootConstrainSelectedInstOperands,
     /* 135914 */   // GIR_Coverage, 4582,
     /* 135914 */   GIR_EraseRootFromParent_Done,
     /* 135915 */ // Label 2376: @135915
     /* 135915 */ GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(136023), // Rule ID 4606 //
     /* 135920 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 135923 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 135927 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 135934 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 135938 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 135942 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 135946 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 135950 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 135955 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 135959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 135963 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 135965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 135972 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 135972 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 135975 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135979 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 135984 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 135990 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 135995 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 136003 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 136011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 136016 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 136021 */   GIR_RootConstrainSelectedInstOperands,
     /* 136022 */   // GIR_Coverage, 4606,
     /* 136022 */   GIR_EraseRootFromParent_Done,
     /* 136023 */ // Label 2377: @136023
     /* 136023 */ GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(136124), // Rule ID 4608 //
     /* 136028 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136031 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136035 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136039 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136043 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 136047 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136051 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136056 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 136060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 136064 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 136066 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 136073 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 136073 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 136076 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136080 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136085 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 136091 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136096 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 136104 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 136112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 136117 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 136122 */   GIR_RootConstrainSelectedInstOperands,
     /* 136123 */   // GIR_Coverage, 4608,
     /* 136123 */   GIR_EraseRootFromParent_Done,
     /* 136124 */ // Label 2378: @136124
     /* 136124 */ GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(136225), // Rule ID 4609 //
     /* 136129 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136132 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136136 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136140 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136144 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 136148 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136152 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136157 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 136161 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 136165 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 136167 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 136174 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 136174 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 136177 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136181 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136186 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 136192 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136197 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136202 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 136205 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 136213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 136218 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 136223 */   GIR_RootConstrainSelectedInstOperands,
     /* 136224 */   // GIR_Coverage, 4609,
     /* 136224 */   GIR_EraseRootFromParent_Done,
     /* 136225 */ // Label 2379: @136225
     /* 136225 */ GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(136326), // Rule ID 13490 //
     /* 136230 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136233 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136237 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136241 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136245 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 136249 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136253 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136258 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 136262 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 136266 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 136268 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 136275 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 136275 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 136278 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136282 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136287 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 136293 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136298 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 136306 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 136314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 136319 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 136324 */   GIR_RootConstrainSelectedInstOperands,
     /* 136325 */   // GIR_Coverage, 13490,
     /* 136325 */   GIR_EraseRootFromParent_Done,
     /* 136326 */ // Label 2380: @136326
     /* 136326 */ GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(136427), // Rule ID 13492 //
     /* 136331 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136334 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136338 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136342 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136346 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 136350 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136354 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136359 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 136363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 136367 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 136369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 136376 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 136376 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 136379 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136383 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136388 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 136394 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136399 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 136407 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 136415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 136420 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 136425 */   GIR_RootConstrainSelectedInstOperands,
     /* 136426 */   // GIR_Coverage, 13492,
     /* 136426 */   GIR_EraseRootFromParent_Done,
     /* 136427 */ // Label 2381: @136427
     /* 136427 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(136509), // Rule ID 6535 //
     /* 136432 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136435 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136439 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 136446 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136450 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136454 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 136458 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136462 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136467 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136471 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136475 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 136479 */   // MIs[2] Operand 1
     /* 136479 */   // No operand predicates
     /* 136479 */   // MIs[0] Rn
     /* 136479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136483 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136487 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136489 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 136492 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136496 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136499 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136507 */   GIR_RootConstrainSelectedInstOperands,
     /* 136508 */   // GIR_Coverage, 6535,
     /* 136508 */   GIR_EraseRootFromParent_Done,
     /* 136509 */ // Label 2382: @136509
     /* 136509 */ GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(136591), // Rule ID 6536 //
     /* 136514 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136517 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136521 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 136528 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136532 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136536 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 136540 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136544 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136549 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136553 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136557 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 136561 */   // MIs[2] Operand 1
     /* 136561 */   // No operand predicates
     /* 136561 */   // MIs[0] Rn
     /* 136561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136565 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136569 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136571 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (ST1i16 VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 136574 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136578 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136581 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136589 */   GIR_RootConstrainSelectedInstOperands,
     /* 136590 */   // GIR_Coverage, 6536,
     /* 136590 */   GIR_EraseRootFromParent_Done,
     /* 136591 */ // Label 2383: @136591
     /* 136591 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(136666), // Rule ID 6537 //
     /* 136596 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136599 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136603 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136607 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136611 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 136615 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136619 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136624 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136628 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136632 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 136636 */   // MIs[2] Operand 1
     /* 136636 */   // No operand predicates
     /* 136636 */   // MIs[0] Rn
     /* 136636 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136640 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136644 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136646 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 136649 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136653 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136656 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136664 */   GIR_RootConstrainSelectedInstOperands,
     /* 136665 */   // GIR_Coverage, 6537,
     /* 136665 */   GIR_EraseRootFromParent_Done,
     /* 136666 */ // Label 2384: @136666
     /* 136666 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(136741), // Rule ID 6538 //
     /* 136671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136674 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136678 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136682 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136686 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 136690 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136694 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136699 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136703 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136707 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 136711 */   // MIs[2] Operand 1
     /* 136711 */   // No operand predicates
     /* 136711 */   // MIs[0] Rn
     /* 136711 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136715 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136719 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136721 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 136724 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136728 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136731 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136733 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136739 */   GIR_RootConstrainSelectedInstOperands,
     /* 136740 */   // GIR_Coverage, 6538,
     /* 136740 */   GIR_EraseRootFromParent_Done,
     /* 136741 */ // Label 2385: @136741
     /* 136741 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(136854), // Rule ID 6542 //
     /* 136746 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136749 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136753 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 136760 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136764 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136768 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 136772 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136776 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136781 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136785 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136789 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 136793 */   // MIs[2] Operand 1
     /* 136793 */   // No operand predicates
     /* 136793 */   // MIs[0] Rn
     /* 136793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136797 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136801 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136803 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136803 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 136806 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 136810 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136815 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 136818 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136822 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 136825 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136830 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136835 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 136838 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136841 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136844 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136846 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136852 */   GIR_RootConstrainSelectedInstOperands,
     /* 136853 */   // GIR_Coverage, 6542,
     /* 136853 */   GIR_EraseRootFromParent_Done,
     /* 136854 */ // Label 2386: @136854
     /* 136854 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(136967), // Rule ID 6543 //
     /* 136859 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136862 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136866 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 136873 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136877 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136881 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 136885 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136889 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136894 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 136898 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 136902 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 136906 */   // MIs[2] Operand 1
     /* 136906 */   // No operand predicates
     /* 136906 */   // MIs[0] Rn
     /* 136906 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 136910 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 136914 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 136916 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v4i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 136916 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 136919 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 136923 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136928 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 136931 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 136935 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 136938 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136943 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 136951 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136954 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 136957 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 136959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 136965 */   GIR_RootConstrainSelectedInstOperands,
     /* 136966 */   // GIR_Coverage, 6543,
     /* 136966 */   GIR_EraseRootFromParent_Done,
     /* 136967 */ // Label 2387: @136967
     /* 136967 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(137073), // Rule ID 6544 //
     /* 136972 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 136975 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 136979 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 136983 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 136987 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 136991 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 136995 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137000 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 137004 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 137008 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 137012 */   // MIs[2] Operand 1
     /* 137012 */   // No operand predicates
     /* 137012 */   // MIs[0] Rn
     /* 137012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 137016 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 137020 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 137022 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 137022 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 137025 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 137029 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137034 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 137037 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 137041 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 137044 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137049 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 137057 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137060 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 137063 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 137065 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 137071 */   GIR_RootConstrainSelectedInstOperands,
     /* 137072 */   // GIR_Coverage, 6544,
     /* 137072 */   GIR_EraseRootFromParent_Done,
     /* 137073 */ // Label 2388: @137073
     /* 137073 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(137179), // Rule ID 6545 //
     /* 137078 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137081 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137085 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 137089 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 137093 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 137097 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 137101 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137106 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 137110 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 137114 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 137118 */   // MIs[2] Operand 1
     /* 137118 */   // No operand predicates
     /* 137118 */   // MIs[0] Rn
     /* 137118 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 137122 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 137126 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 137128 */   // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 137128 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 137131 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 137135 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137140 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 137143 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 137147 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 137150 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137155 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 137163 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137166 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 137169 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 137171 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 137177 */   GIR_RootConstrainSelectedInstOperands,
     /* 137178 */   // GIR_Coverage, 6545,
     /* 137178 */   GIR_EraseRootFromParent_Done,
     /* 137179 */ // Label 2389: @137179
     /* 137179 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(137239), // Rule ID 299 //
     /* 137184 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137187 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137191 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 137198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 137213 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 137213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 137216 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137233 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137237 */   GIR_RootConstrainSelectedInstOperands,
     /* 137238 */   // GIR_Coverage, 299,
     /* 137238 */   GIR_EraseRootFromParent_Done,
     /* 137239 */ // Label 2390: @137239
     /* 137239 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(137299), // Rule ID 300 //
     /* 137244 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137247 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 137258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137262 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137266 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 137273 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 137273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 137276 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137297 */   GIR_RootConstrainSelectedInstOperands,
     /* 137298 */   // GIR_Coverage, 300,
     /* 137298 */   GIR_EraseRootFromParent_Done,
     /* 137299 */ // Label 2391: @137299
     /* 137299 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(137359), // Rule ID 301 //
     /* 137304 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137307 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137311 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 137318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 137333 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 137333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 137336 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137353 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137357 */   GIR_RootConstrainSelectedInstOperands,
     /* 137358 */   // GIR_Coverage, 301,
     /* 137358 */   GIR_EraseRootFromParent_Done,
     /* 137359 */ // Label 2392: @137359
     /* 137359 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(137419), // Rule ID 302 //
     /* 137364 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137367 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137371 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 137378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 137393 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 137393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 137396 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137417 */   GIR_RootConstrainSelectedInstOperands,
     /* 137418 */   // GIR_Coverage, 302,
     /* 137418 */   GIR_EraseRootFromParent_Done,
     /* 137419 */ // Label 2393: @137419
     /* 137419 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(137472), // Rule ID 303 //
     /* 137424 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137427 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137435 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137439 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 137446 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 137446 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 137449 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137456 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137470 */   GIR_RootConstrainSelectedInstOperands,
     /* 137471 */   // GIR_Coverage, 303,
     /* 137471 */   GIR_EraseRootFromParent_Done,
     /* 137472 */ // Label 2394: @137472
     /* 137472 */ GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(137525), // Rule ID 304 //
     /* 137477 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137480 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 137499 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 137499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 137502 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137519 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137523 */   GIR_RootConstrainSelectedInstOperands,
     /* 137524 */   // GIR_Coverage, 304,
     /* 137524 */   GIR_EraseRootFromParent_Done,
     /* 137525 */ // Label 2395: @137525
     /* 137525 */ GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(137581), // Rule ID 311 //
     /* 137530 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 137533 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137536 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137544 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137548 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 137555 */   // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 137555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 137558 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137575 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137579 */   GIR_RootConstrainSelectedInstOperands,
     /* 137580 */   // GIR_Coverage, 311,
     /* 137580 */   GIR_EraseRootFromParent_Done,
     /* 137581 */ // Label 2396: @137581
     /* 137581 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(137637), // Rule ID 312 //
     /* 137586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 137589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137592 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137600 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 137611 */   // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 137611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 137614 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137635 */   GIR_RootConstrainSelectedInstOperands,
     /* 137636 */   // GIR_Coverage, 312,
     /* 137636 */   GIR_EraseRootFromParent_Done,
     /* 137637 */ // Label 2397: @137637
     /* 137637 */ GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(137689), // Rule ID 316 //
     /* 137642 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137645 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137657 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 137664 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 137664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 137667 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 137673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 137683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137687 */   GIR_RootConstrainSelectedInstOperands,
     /* 137688 */   // GIR_Coverage, 316,
     /* 137688 */   GIR_EraseRootFromParent_Done,
     /* 137689 */ // Label 2398: @137689
     /* 137689 */ GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(137740), // Rule ID 319 //
     /* 137694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 137697 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137700 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 137719 */   // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 137719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 137722 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 137724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 137734 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137738 */   GIR_RootConstrainSelectedInstOperands,
     /* 137739 */   // GIR_Coverage, 319,
     /* 137739 */   GIR_EraseRootFromParent_Done,
     /* 137740 */ // Label 2399: @137740
     /* 137740 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(137799), // Rule ID 321 //
     /* 137745 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137748 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 137759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 137774 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 137774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 137777 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 137783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 137793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137797 */   GIR_RootConstrainSelectedInstOperands,
     /* 137798 */   // GIR_Coverage, 321,
     /* 137798 */   GIR_EraseRootFromParent_Done,
     /* 137799 */ // Label 2400: @137799
     /* 137799 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(137858), // Rule ID 322 //
     /* 137804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 137807 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 137811 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 137818 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 137833 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 137833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 137836 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 137842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 137852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 137856 */   GIR_RootConstrainSelectedInstOperands,
     /* 137857 */   // GIR_Coverage, 322,
     /* 137857 */   GIR_EraseRootFromParent_Done,
     /* 137858 */ // Label 2401: @137858
     /* 137858 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(137935), // Rule ID 7174 //
     /* 137863 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 137866 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 137873 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 137876 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 137880 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 137884 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 137888 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137897 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 137899 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 137906 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRSroW FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 137906 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 137909 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 137913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 137923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 137928 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 137933 */   GIR_RootConstrainSelectedInstOperands,
     /* 137934 */   // GIR_Coverage, 7174,
     /* 137934 */   GIR_EraseRootFromParent_Done,
     /* 137935 */ // Label 2402: @137935
     /* 137935 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(138012), // Rule ID 7175 //
     /* 137940 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 137943 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 137950 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 137953 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 137957 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 137961 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 137965 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 137974 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 137976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 137983 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRSroX FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 137983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 137986 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 137990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 137995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138005 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 138010 */   GIR_RootConstrainSelectedInstOperands,
     /* 138011 */   // GIR_Coverage, 7175,
     /* 138011 */   GIR_EraseRootFromParent_Done,
     /* 138012 */ // Label 2403: @138012
     /* 138012 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(138071), // Rule ID 7155 //
     /* 138017 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138020 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 138027 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 138045 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15918>>  =>  (STRBBroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 138045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 138048 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138065 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138069 */   GIR_RootConstrainSelectedInstOperands,
     /* 138070 */   // GIR_Coverage, 7155,
     /* 138070 */   GIR_EraseRootFromParent_Done,
     /* 138071 */ // Label 2404: @138071
     /* 138071 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(138130), // Rule ID 7156 //
     /* 138076 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138079 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 138086 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138093 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138097 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 138104 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15918>>  =>  (STRBBroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 138104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 138107 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138124 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138128 */   GIR_RootConstrainSelectedInstOperands,
     /* 138129 */   // GIR_Coverage, 7156,
     /* 138129 */   GIR_EraseRootFromParent_Done,
     /* 138130 */ // Label 2405: @138130
     /* 138130 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(138189), // Rule ID 7160 //
     /* 138135 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138138 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 138145 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138152 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138156 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 138163 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15925>>  =>  (STRHHroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 138163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 138166 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138187 */   GIR_RootConstrainSelectedInstOperands,
     /* 138188 */   // GIR_Coverage, 7160,
     /* 138188 */   GIR_EraseRootFromParent_Done,
     /* 138189 */ // Label 2406: @138189
     /* 138189 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(138248), // Rule ID 7161 //
     /* 138194 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138197 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 138204 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138215 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 138222 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15925>>  =>  (STRHHroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 138222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 138225 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138246 */   GIR_RootConstrainSelectedInstOperands,
     /* 138247 */   // GIR_Coverage, 7161,
     /* 138247 */   GIR_EraseRootFromParent_Done,
     /* 138248 */ // Label 2407: @138248
     /* 138248 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(138307), // Rule ID 7165 //
     /* 138253 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 138263 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 138281 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRWroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 138281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 138284 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138301 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138305 */   GIR_RootConstrainSelectedInstOperands,
     /* 138306 */   // GIR_Coverage, 7165,
     /* 138306 */   GIR_EraseRootFromParent_Done,
     /* 138307 */ // Label 2408: @138307
     /* 138307 */ GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(138366), // Rule ID 7166 //
     /* 138312 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138315 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 138322 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138325 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138329 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138333 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 138340 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRWroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 138340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 138343 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138360 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138364 */   GIR_RootConstrainSelectedInstOperands,
     /* 138365 */   // GIR_Coverage, 7166,
     /* 138365 */   GIR_EraseRootFromParent_Done,
     /* 138366 */ // Label 2409: @138366
     /* 138366 */ GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(138438), // Rule ID 7176 //
     /* 138371 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138374 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 138381 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138384 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 138388 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 138392 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 138396 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 138401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138405 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 138407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 138414 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRSui FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 138414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 138417 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 138421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 138436 */   GIR_RootConstrainSelectedInstOperands,
     /* 138437 */   // GIR_Coverage, 7176,
     /* 138437 */   GIR_EraseRootFromParent_Done,
     /* 138438 */ // Label 2410: @138438
     /* 138438 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(138510), // Rule ID 7177 //
     /* 138443 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138446 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 138453 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138456 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 138460 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 138464 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 138468 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 138473 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138477 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 138479 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 138486 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STURSi FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 138486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 138489 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 138493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 138508 */   GIR_RootConstrainSelectedInstOperands,
     /* 138509 */   // GIR_Coverage, 7177,
     /* 138509 */   GIR_EraseRootFromParent_Done,
     /* 138510 */ // Label 2411: @138510
     /* 138510 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(138562), // Rule ID 324 //
     /* 138515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 138518 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 138522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138526 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138530 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 138537 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 138537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 138540 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 138546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138556 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138560 */   GIR_RootConstrainSelectedInstOperands,
     /* 138561 */   // GIR_Coverage, 324,
     /* 138561 */   GIR_EraseRootFromParent_Done,
     /* 138562 */ // Label 2412: @138562
     /* 138562 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(138613), // Rule ID 327 //
     /* 138567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 138570 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 138573 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 138577 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 138581 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138585 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 138592 */   // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 138592 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 138595 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 138597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138611 */   GIR_RootConstrainSelectedInstOperands,
     /* 138612 */   // GIR_Coverage, 327,
     /* 138612 */   GIR_EraseRootFromParent_Done,
     /* 138613 */ // Label 2413: @138613
     /* 138613 */ GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(138672), // Rule ID 330 //
     /* 138618 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 138621 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 138625 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 138632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138636 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138640 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 138647 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHHi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 138647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 138650 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 138656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138666 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138670 */   GIR_RootConstrainSelectedInstOperands,
     /* 138671 */   // GIR_Coverage, 330,
     /* 138671 */   GIR_EraseRootFromParent_Done,
     /* 138672 */ // Label 2414: @138672
     /* 138672 */ GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(138731), // Rule ID 331 //
     /* 138677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 138680 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 138684 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 138691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 138706 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STURBBi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 138706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 138709 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 138715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138729 */   GIR_RootConstrainSelectedInstOperands,
     /* 138730 */   // GIR_Coverage, 331,
     /* 138730 */   GIR_EraseRootFromParent_Done,
     /* 138731 */ // Label 2415: @138731
     /* 138731 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(138785), // Rule ID 7157 //
     /* 138736 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 138746 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138749 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138753 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138757 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 138764 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15918>>  =>  (STRBBui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 138764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 138767 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138783 */   GIR_RootConstrainSelectedInstOperands,
     /* 138784 */   // GIR_Coverage, 7157,
     /* 138784 */   GIR_EraseRootFromParent_Done,
     /* 138785 */ // Label 2416: @138785
     /* 138785 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(138839), // Rule ID 7158 //
     /* 138790 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138793 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 138800 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 138818 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15918>>  =>  (STURBBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 138818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 138821 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138833 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138837 */   GIR_RootConstrainSelectedInstOperands,
     /* 138838 */   // GIR_Coverage, 7158,
     /* 138838 */   GIR_EraseRootFromParent_Done,
     /* 138839 */ // Label 2417: @138839
     /* 138839 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(138893), // Rule ID 7162 //
     /* 138844 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138847 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 138854 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138861 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 138872 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15925>>  =>  (STRHHui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 138872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 138875 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138891 */   GIR_RootConstrainSelectedInstOperands,
     /* 138892 */   // GIR_Coverage, 7162,
     /* 138892 */   GIR_EraseRootFromParent_Done,
     /* 138893 */ // Label 2418: @138893
     /* 138893 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(138947), // Rule ID 7163 //
     /* 138898 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138901 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 138908 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138919 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 138926 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15925>>  =>  (STURHHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 138926 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 138929 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138941 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138945 */   GIR_RootConstrainSelectedInstOperands,
     /* 138946 */   // GIR_Coverage, 7163,
     /* 138946 */   GIR_EraseRootFromParent_Done,
     /* 138947 */ // Label 2419: @138947
     /* 138947 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(139001), // Rule ID 7167 //
     /* 138952 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 138955 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 138962 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 138965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 138969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 138980 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STRWui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 138980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 138983 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 138985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 138995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138999 */   GIR_RootConstrainSelectedInstOperands,
     /* 139000 */   // GIR_Coverage, 7167,
     /* 139000 */   GIR_EraseRootFromParent_Done,
     /* 139001 */ // Label 2420: @139001
     /* 139001 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(139055), // Rule ID 7168 //
     /* 139006 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139009 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 139016 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139023 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139027 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 139034 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15932>>  =>  (STURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 139034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 139037 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 139039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139053 */   GIR_RootConstrainSelectedInstOperands,
     /* 139054 */   // GIR_Coverage, 7168,
     /* 139054 */   GIR_EraseRootFromParent_Done,
     /* 139055 */ // Label 2421: @139055
     /* 139055 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(139112), // Rule ID 7530 //
     /* 139060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 139063 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139073 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139080 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139084 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 139091 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15916>>  =>  (STLURBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 139091 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURBi),
     /* 139094 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 139096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139106 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139110 */   GIR_RootConstrainSelectedInstOperands,
     /* 139111 */   // GIR_Coverage, 7530,
     /* 139111 */   GIR_EraseRootFromParent_Done,
     /* 139112 */ // Label 2422: @139112
     /* 139112 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(139169), // Rule ID 7531 //
     /* 139117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 139120 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139123 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 139130 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139133 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139137 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139141 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 139148 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15923>>  =>  (STLURHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 139148 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURHi),
     /* 139151 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 139153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139167 */   GIR_RootConstrainSelectedInstOperands,
     /* 139168 */   // GIR_Coverage, 7531,
     /* 139168 */   GIR_EraseRootFromParent_Done,
     /* 139169 */ // Label 2423: @139169
     /* 139169 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(139226), // Rule ID 7532 //
     /* 139174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 139177 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139180 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 139187 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139194 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 139205 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15930>>  =>  (STLURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 139205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURWi),
     /* 139208 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 139210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139220 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139224 */   GIR_RootConstrainSelectedInstOperands,
     /* 139225 */   // GIR_Coverage, 7532,
     /* 139225 */   GIR_EraseRootFromParent_Done,
     /* 139226 */ // Label 2424: @139226
     /* 139226 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(139263), // Rule ID 7154 //
     /* 139231 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139241 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139248 */   // MIs[0] ptr
     /* 139248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 139252 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 139256 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_15916>>  =>  (STLRB GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 139256 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRB),
     /* 139261 */   GIR_RootConstrainSelectedInstOperands,
     /* 139262 */   // GIR_Coverage, 7154,
     /* 139262 */   GIR_Done,
     /* 139263 */ // Label 2425: @139263
     /* 139263 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(139300), // Rule ID 7159 //
     /* 139268 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139271 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 139278 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139285 */   // MIs[0] ptr
     /* 139285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 139289 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 139293 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_15923>>  =>  (STLRH GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 139293 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRH),
     /* 139298 */   GIR_RootConstrainSelectedInstOperands,
     /* 139299 */   // GIR_Coverage, 7159,
     /* 139299 */   GIR_Done,
     /* 139300 */ // Label 2426: @139300
     /* 139300 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(139337), // Rule ID 7164 //
     /* 139305 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139308 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 139315 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 139318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139322 */   // MIs[0] ptr
     /* 139322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 139326 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 139330 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_15930>>  =>  (STLRW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 139330 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRW),
     /* 139335 */   GIR_RootConstrainSelectedInstOperands,
     /* 139336 */   // GIR_Coverage, 7164,
     /* 139336 */   GIR_Done,
     /* 139337 */ // Label 2427: @139337
     /* 139337 */ GIM_Reject,
     /* 139338 */ // Label 2326: @139338
     /* 139338 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(139444), // Rule ID 4557 //
     /* 139343 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139346 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139350 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139354 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139358 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139362 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139366 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139371 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139375 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139379 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 139388 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 139388 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139391 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139395 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139400 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139406 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139411 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 139419 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139442 */   GIR_RootConstrainSelectedInstOperands,
     /* 139443 */   // GIR_Coverage, 4557,
     /* 139443 */   GIR_EraseRootFromParent_Done,
     /* 139444 */ // Label 2428: @139444
     /* 139444 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(139550), // Rule ID 4558 //
     /* 139449 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139452 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139456 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139460 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139464 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139468 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139472 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139477 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139481 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139485 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139487 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 139494 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 139494 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139497 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139501 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139506 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139512 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139517 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 139525 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139548 */   GIR_RootConstrainSelectedInstOperands,
     /* 139549 */   // GIR_Coverage, 4558,
     /* 139549 */   GIR_EraseRootFromParent_Done,
     /* 139550 */ // Label 2429: @139550
     /* 139550 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(139656), // Rule ID 4559 //
     /* 139555 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139558 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139562 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139566 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139570 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139574 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139578 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139583 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139587 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139591 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139593 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 139600 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 139600 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139603 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139607 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139612 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139618 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139623 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139628 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 139631 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139654 */   GIR_RootConstrainSelectedInstOperands,
     /* 139655 */   // GIR_Coverage, 4559,
     /* 139655 */   GIR_EraseRootFromParent_Done,
     /* 139656 */ // Label 2430: @139656
     /* 139656 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(139762), // Rule ID 4560 //
     /* 139661 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139664 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139668 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139672 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139676 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139680 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139684 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139689 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139697 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 139706 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 139706 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139709 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139713 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139718 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139724 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139729 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 139737 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139760 */   GIR_RootConstrainSelectedInstOperands,
     /* 139761 */   // GIR_Coverage, 4560,
     /* 139761 */   GIR_EraseRootFromParent_Done,
     /* 139762 */ // Label 2431: @139762
     /* 139762 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(139863), // Rule ID 4583 //
     /* 139767 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139770 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139774 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139778 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139782 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139786 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139790 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139795 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139803 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 139812 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 139812 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139815 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139819 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139824 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139830 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139835 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139840 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 139843 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139856 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139861 */   GIR_RootConstrainSelectedInstOperands,
     /* 139862 */   // GIR_Coverage, 4583,
     /* 139862 */   GIR_EraseRootFromParent_Done,
     /* 139863 */ // Label 2432: @139863
     /* 139863 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(139964), // Rule ID 4584 //
     /* 139868 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139871 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139875 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139879 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139883 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139887 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139891 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139896 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 139900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139904 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 139906 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 139913 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 139913 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 139916 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 139920 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 139925 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 139931 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 139936 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 139944 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 139947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 139962 */   GIR_RootConstrainSelectedInstOperands,
     /* 139963 */   // GIR_Coverage, 4584,
     /* 139963 */   GIR_EraseRootFromParent_Done,
     /* 139964 */ // Label 2433: @139964
     /* 139964 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(140065), // Rule ID 4610 //
     /* 139969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139972 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139976 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 139980 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 139984 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 139988 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 139992 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 139997 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 140001 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140005 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 140007 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 140014 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140014 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 140017 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140021 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140026 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 140032 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 140037 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 140042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 140045 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140058 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 140063 */   GIR_RootConstrainSelectedInstOperands,
     /* 140064 */   // GIR_Coverage, 4610,
     /* 140064 */   GIR_EraseRootFromParent_Done,
     /* 140065 */ // Label 2434: @140065
     /* 140065 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(140166), // Rule ID 4611 //
     /* 140070 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140073 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140077 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 140081 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 140085 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 140089 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 140093 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 140098 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 140102 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140106 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 140108 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 140115 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140115 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 140118 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140122 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140127 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 140133 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 140138 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 140143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 140146 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140159 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 140164 */   GIR_RootConstrainSelectedInstOperands,
     /* 140165 */   // GIR_Coverage, 4611,
     /* 140165 */   GIR_EraseRootFromParent_Done,
     /* 140166 */ // Label 2435: @140166
     /* 140166 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(140241), // Rule ID 6539 //
     /* 140171 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140174 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140178 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 140182 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 140186 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 140190 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 140194 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 140199 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 140203 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 140207 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 140211 */   // MIs[2] Operand 1
     /* 140211 */   // No operand predicates
     /* 140211 */   // MIs[0] Rn
     /* 140211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 140215 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 140219 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 140221 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 140221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
     /* 140224 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 140228 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 140231 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 140233 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 140239 */   GIR_RootConstrainSelectedInstOperands,
     /* 140240 */   // GIR_Coverage, 6539,
     /* 140240 */   GIR_EraseRootFromParent_Done,
     /* 140241 */ // Label 2436: @140241
     /* 140241 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(140316), // Rule ID 6540 //
     /* 140246 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140249 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140253 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 140257 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 140261 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 140265 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 140269 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 140274 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 140278 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 140282 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 140286 */   // MIs[2] Operand 1
     /* 140286 */   // No operand predicates
     /* 140286 */   // MIs[0] Rn
     /* 140286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 140290 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 140294 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 140296 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 140296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
     /* 140299 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 140303 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 140306 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 140308 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 140314 */   GIR_RootConstrainSelectedInstOperands,
     /* 140315 */   // GIR_Coverage, 6540,
     /* 140315 */   GIR_EraseRootFromParent_Done,
     /* 140316 */ // Label 2437: @140316
     /* 140316 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(140369), // Rule ID 305 //
     /* 140321 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140324 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 140343 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 140343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
     /* 140346 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 140348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140363 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140367 */   GIR_RootConstrainSelectedInstOperands,
     /* 140368 */   // GIR_Coverage, 305,
     /* 140368 */   GIR_EraseRootFromParent_Done,
     /* 140369 */ // Label 2438: @140369
     /* 140369 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(140422), // Rule ID 306 //
     /* 140374 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140377 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 140396 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 140396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
     /* 140399 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 140401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140416 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140420 */   GIR_RootConstrainSelectedInstOperands,
     /* 140421 */   // GIR_Coverage, 306,
     /* 140421 */   GIR_EraseRootFromParent_Done,
     /* 140422 */ // Label 2439: @140422
     /* 140422 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(140478), // Rule ID 313 //
     /* 140427 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 140430 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140433 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 140441 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 140452 */   // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 140452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 140455 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 140457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140472 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140476 */   GIR_RootConstrainSelectedInstOperands,
     /* 140477 */   // GIR_Coverage, 313,
     /* 140477 */   GIR_EraseRootFromParent_Done,
     /* 140478 */ // Label 2440: @140478
     /* 140478 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(140534), // Rule ID 314 //
     /* 140483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 140486 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140489 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 140497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 140508 */   // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 140508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 140511 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 140513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140532 */   GIR_RootConstrainSelectedInstOperands,
     /* 140533 */   // GIR_Coverage, 314,
     /* 140533 */   GIR_EraseRootFromParent_Done,
     /* 140534 */ // Label 2441: @140534
     /* 140534 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(140623), // Rule ID 4515 //
     /* 140539 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140542 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140557 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140561 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 140568 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 140568 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 140571 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140575 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140580 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 140586 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140591 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 140599 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140617 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140621 */   GIR_RootConstrainSelectedInstOperands,
     /* 140622 */   // GIR_Coverage, 4515,
     /* 140622 */   GIR_EraseRootFromParent_Done,
     /* 140623 */ // Label 2442: @140623
     /* 140623 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(140712), // Rule ID 4516 //
     /* 140628 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140631 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140635 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140650 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 140657 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 140657 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 140660 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140664 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140669 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 140675 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140680 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 140688 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140706 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140710 */   GIR_RootConstrainSelectedInstOperands,
     /* 140711 */   // GIR_Coverage, 4516,
     /* 140711 */   GIR_EraseRootFromParent_Done,
     /* 140712 */ // Label 2443: @140712
     /* 140712 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(140801), // Rule ID 4517 //
     /* 140717 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140720 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140724 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140735 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 140746 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 140746 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 140749 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140753 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140758 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 140764 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140769 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 140777 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140795 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140799 */   GIR_RootConstrainSelectedInstOperands,
     /* 140800 */   // GIR_Coverage, 4517,
     /* 140800 */   GIR_EraseRootFromParent_Done,
     /* 140801 */ // Label 2444: @140801
     /* 140801 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(140890), // Rule ID 4518 //
     /* 140806 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140809 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140813 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140824 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140828 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 140835 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 140835 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 140838 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140842 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140847 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 140853 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140858 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 140866 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140884 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140888 */   GIR_RootConstrainSelectedInstOperands,
     /* 140889 */   // GIR_Coverage, 4518,
     /* 140889 */   GIR_EraseRootFromParent_Done,
     /* 140890 */ // Label 2445: @140890
     /* 140890 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(140979), // Rule ID 4519 //
     /* 140895 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140898 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140902 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 140924 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 140924 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 140927 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 140931 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 140936 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 140942 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140947 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 140952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 140955 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 140958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140973 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140977 */   GIR_RootConstrainSelectedInstOperands,
     /* 140978 */   // GIR_Coverage, 4519,
     /* 140978 */   GIR_EraseRootFromParent_Done,
     /* 140979 */ // Label 2446: @140979
     /* 140979 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(141068), // Rule ID 4520 //
     /* 140984 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140987 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140991 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140998 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141002 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141006 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 141013 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 141013 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 141016 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 141020 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 141025 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 141031 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141036 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 141044 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 141047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141062 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141066 */   GIR_RootConstrainSelectedInstOperands,
     /* 141067 */   // GIR_Coverage, 4520,
     /* 141067 */   GIR_EraseRootFromParent_Done,
     /* 141068 */ // Label 2447: @141068
     /* 141068 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(141121), // Rule ID 4531 //
     /* 141073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141076 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141095 */   // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 141098 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141115 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141119 */   GIR_RootConstrainSelectedInstOperands,
     /* 141120 */   // GIR_Coverage, 4531,
     /* 141120 */   GIR_EraseRootFromParent_Done,
     /* 141121 */ // Label 2448: @141121
     /* 141121 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(141174), // Rule ID 4532 //
     /* 141126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141129 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141133 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141137 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141141 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141148 */   // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141148 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 141151 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141168 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141172 */   GIR_RootConstrainSelectedInstOperands,
     /* 141173 */   // GIR_Coverage, 4532,
     /* 141173 */   GIR_EraseRootFromParent_Done,
     /* 141174 */ // Label 2449: @141174
     /* 141174 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(141227), // Rule ID 4533 //
     /* 141179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141182 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141194 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141201 */   // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 141204 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141221 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141225 */   GIR_RootConstrainSelectedInstOperands,
     /* 141226 */   // GIR_Coverage, 4533,
     /* 141226 */   GIR_EraseRootFromParent_Done,
     /* 141227 */ // Label 2450: @141227
     /* 141227 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(141280), // Rule ID 4534 //
     /* 141232 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141235 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141254 */   // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 141257 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141278 */   GIR_RootConstrainSelectedInstOperands,
     /* 141279 */   // GIR_Coverage, 4534,
     /* 141279 */   GIR_EraseRootFromParent_Done,
     /* 141280 */ // Label 2451: @141280
     /* 141280 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(141332), // Rule ID 315 //
     /* 141285 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141288 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141292 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 141307 */   // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 141307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
     /* 141310 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
     /* 141316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141326 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141330 */   GIR_RootConstrainSelectedInstOperands,
     /* 141331 */   // GIR_Coverage, 315,
     /* 141331 */   GIR_EraseRootFromParent_Done,
     /* 141332 */ // Label 2452: @141332
     /* 141332 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(141383), // Rule ID 320 //
     /* 141337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 141340 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141343 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 141362 */   // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 141362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 141365 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141381 */   GIR_RootConstrainSelectedInstOperands,
     /* 141382 */   // GIR_Coverage, 320,
     /* 141382 */   GIR_EraseRootFromParent_Done,
     /* 141383 */ // Label 2453: @141383
     /* 141383 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(141431), // Rule ID 4561 //
     /* 141388 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141391 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 141410 */   // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 141410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 141413 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141429 */   GIR_RootConstrainSelectedInstOperands,
     /* 141430 */   // GIR_Coverage, 4561,
     /* 141430 */   GIR_EraseRootFromParent_Done,
     /* 141431 */ // Label 2454: @141431
     /* 141431 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(141479), // Rule ID 4562 //
     /* 141436 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141439 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141447 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141451 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 141458 */   // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 141458 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 141461 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 141463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141477 */   GIR_RootConstrainSelectedInstOperands,
     /* 141478 */   // GIR_Coverage, 4562,
     /* 141478 */   GIR_EraseRootFromParent_Done,
     /* 141479 */ // Label 2455: @141479
     /* 141479 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(141563), // Rule ID 4576 //
     /* 141484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141487 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141491 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 141498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141502 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141506 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 141513 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 141513 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 141516 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 141520 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 141525 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 141531 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141536 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 141544 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 141547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141557 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141561 */   GIR_RootConstrainSelectedInstOperands,
     /* 141562 */   // GIR_Coverage, 4576,
     /* 141562 */   GIR_EraseRootFromParent_Done,
     /* 141563 */ // Label 2456: @141563
     /* 141563 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(141647), // Rule ID 4577 //
     /* 141568 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141571 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141575 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 141582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 141597 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 141597 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 141600 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 141604 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 141609 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 141615 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141620 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 141628 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 141631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141641 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141645 */   GIR_RootConstrainSelectedInstOperands,
     /* 141646 */   // GIR_Coverage, 4577,
     /* 141646 */   GIR_EraseRootFromParent_Done,
     /* 141647 */ // Label 2457: @141647
     /* 141647 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(141731), // Rule ID 4578 //
     /* 141652 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141655 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141659 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 141666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141670 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141674 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 141681 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 141681 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 141684 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 141688 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 141693 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 141699 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141704 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 141712 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 141715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141729 */   GIR_RootConstrainSelectedInstOperands,
     /* 141730 */   // GIR_Coverage, 4578,
     /* 141730 */   GIR_EraseRootFromParent_Done,
     /* 141731 */ // Label 2458: @141731
     /* 141731 */ GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(141808), // Rule ID 7178 //
     /* 141736 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 141746 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 141749 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 141753 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 141757 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 141761 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141766 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141770 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 141772 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141779 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRDroW FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 141782 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 141786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 141806 */   GIR_RootConstrainSelectedInstOperands,
     /* 141807 */   // GIR_Coverage, 7178,
     /* 141807 */   GIR_EraseRootFromParent_Done,
     /* 141808 */ // Label 2459: @141808
     /* 141808 */ GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(141885), // Rule ID 7179 //
     /* 141813 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141816 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 141823 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 141826 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 141830 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 141834 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 141838 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141847 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 141849 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141856 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRDroX FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141856 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 141859 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 141863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 141883 */   GIR_RootConstrainSelectedInstOperands,
     /* 141884 */   // GIR_Coverage, 7179,
     /* 141884 */   GIR_EraseRootFromParent_Done,
     /* 141885 */ // Label 2460: @141885
     /* 141885 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(141944), // Rule ID 7170 //
     /* 141890 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141893 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 141900 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 141903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141907 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141911 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141918 */   // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRXroW GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141918 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
     /* 141921 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 141923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141938 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141942 */   GIR_RootConstrainSelectedInstOperands,
     /* 141943 */   // GIR_Coverage, 7170,
     /* 141943 */   GIR_EraseRootFromParent_Done,
     /* 141944 */ // Label 2461: @141944
     /* 141944 */ GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(142003), // Rule ID 7171 //
     /* 141949 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141952 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 141959 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 141962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141966 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141970 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141977 */   // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRXroX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
     /* 141980 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 141982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141997 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142001 */   GIR_RootConstrainSelectedInstOperands,
     /* 142002 */   // GIR_Coverage, 7171,
     /* 142002 */   GIR_EraseRootFromParent_Done,
     /* 142003 */ // Label 2462: @142003
     /* 142003 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(142075), // Rule ID 7180 //
     /* 142008 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142011 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142018 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142021 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 142025 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 142029 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 142033 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142042 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 142044 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 142051 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRDui FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 142051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 142054 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 142058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142068 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 142073 */   GIR_RootConstrainSelectedInstOperands,
     /* 142074 */   // GIR_Coverage, 7180,
     /* 142074 */   GIR_EraseRootFromParent_Done,
     /* 142075 */ // Label 2463: @142075
     /* 142075 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(142147), // Rule ID 7181 //
     /* 142080 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142083 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142090 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142093 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 142097 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 142101 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 142105 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142110 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142114 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 142116 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142123 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STURDi FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142123 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 142126 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 142130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 142145 */   GIR_RootConstrainSelectedInstOperands,
     /* 142146 */   // GIR_Coverage, 7181,
     /* 142146 */   GIR_EraseRootFromParent_Done,
     /* 142147 */ // Label 2464: @142147
     /* 142147 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(142244), // Rule ID 7522 //
     /* 142152 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 142155 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142158 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142165 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142168 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 142172 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 142176 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 142180 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 142184 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 142188 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 142192 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 142196 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 142201 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 142205 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 142209 */   GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 142213 */   // MIs[3] Operand 1
     /* 142213 */   // No operand predicates
     /* 142213 */   // MIs[0] Rn
     /* 142213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 142217 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 142221 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 142223 */   // (atomic_store (bitconvert:{ *:[i64] } (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15937>>  =>  (STL1 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 142223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 142226 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vt
     /* 142230 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 142233 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 142235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
     /* 142242 */   GIR_RootConstrainSelectedInstOperands,
     /* 142243 */   // GIR_Coverage, 7522,
     /* 142243 */   GIR_EraseRootFromParent_Done,
     /* 142244 */ // Label 2465: @142244
     /* 142244 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(142296), // Rule ID 323 //
     /* 142249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142252 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142271 */   // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 142271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
     /* 142274 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
     /* 142280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142290 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142294 */   GIR_RootConstrainSelectedInstOperands,
     /* 142295 */   // GIR_Coverage, 323,
     /* 142295 */   GIR_EraseRootFromParent_Done,
     /* 142296 */ // Label 2466: @142296
     /* 142296 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(142347), // Rule ID 328 //
     /* 142301 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 142304 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142307 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142326 */   // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 142326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 142329 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 142331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142345 */   GIR_RootConstrainSelectedInstOperands,
     /* 142346 */   // GIR_Coverage, 328,
     /* 142346 */   GIR_EraseRootFromParent_Done,
     /* 142347 */ // Label 2467: @142347
     /* 142347 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(142401), // Rule ID 7172 //
     /* 142352 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142355 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142362 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142369 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142373 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 142380 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STRXui GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 142380 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
     /* 142383 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 142385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142395 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142399 */   GIR_RootConstrainSelectedInstOperands,
     /* 142400 */   // GIR_Coverage, 7172,
     /* 142400 */   GIR_EraseRootFromParent_Done,
     /* 142401 */ // Label 2468: @142401
     /* 142401 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(142455), // Rule ID 7173 //
     /* 142406 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142409 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142416 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142434 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15939>>  =>  (STURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
     /* 142437 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 142439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142449 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142453 */   GIR_RootConstrainSelectedInstOperands,
     /* 142454 */   // GIR_Coverage, 7173,
     /* 142454 */   GIR_EraseRootFromParent_Done,
     /* 142455 */ // Label 2469: @142455
     /* 142455 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(142512), // Rule ID 7533 //
     /* 142460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 142463 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142466 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142473 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142480 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142484 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142491 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15937>>  =>  (STLURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURXi),
     /* 142494 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 142496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142510 */   GIR_RootConstrainSelectedInstOperands,
     /* 142511 */   // GIR_Coverage, 7533,
     /* 142511 */   GIR_EraseRootFromParent_Done,
     /* 142512 */ // Label 2470: @142512
     /* 142512 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(142560), // Rule ID 4585 //
     /* 142517 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142520 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142532 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142539 */   // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 142542 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 142544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142554 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142558 */   GIR_RootConstrainSelectedInstOperands,
     /* 142559 */   // GIR_Coverage, 4585,
     /* 142559 */   GIR_EraseRootFromParent_Done,
     /* 142560 */ // Label 2471: @142560
     /* 142560 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(142608), // Rule ID 4586 //
     /* 142565 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142568 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142580 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142587 */   // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 142590 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 142592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142606 */   GIR_RootConstrainSelectedInstOperands,
     /* 142607 */   // GIR_Coverage, 4586,
     /* 142607 */   GIR_EraseRootFromParent_Done,
     /* 142608 */ // Label 2472: @142608
     /* 142608 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(142692), // Rule ID 4601 //
     /* 142613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142616 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 142627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 142642 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STURWi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142642 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142645 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 142649 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142654 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 142660 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142665 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 142673 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142690 */   GIR_RootConstrainSelectedInstOperands,
     /* 142691 */   // GIR_Coverage, 4601,
     /* 142691 */   GIR_EraseRootFromParent_Done,
     /* 142692 */ // Label 2473: @142692
     /* 142692 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(142776), // Rule ID 4602 //
     /* 142697 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142700 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142704 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 142711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142715 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142719 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 142726 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHHi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142726 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142729 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 142733 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142738 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 142744 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142749 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 142757 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142770 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142774 */   GIR_RootConstrainSelectedInstOperands,
     /* 142775 */   // GIR_Coverage, 4602,
     /* 142775 */   GIR_EraseRootFromParent_Done,
     /* 142776 */ // Label 2474: @142776
     /* 142776 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(142860), // Rule ID 4603 //
     /* 142781 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142784 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142788 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 142795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 142810 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STURBBi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 142810 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142813 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 142817 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142822 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 142828 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142833 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 142841 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142854 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142858 */   GIR_RootConstrainSelectedInstOperands,
     /* 142859 */   // GIR_Coverage, 4603,
     /* 142859 */   GIR_EraseRootFromParent_Done,
     /* 142860 */ // Label 2475: @142860
     /* 142860 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(142944), // Rule ID 7521 //
     /* 142865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 142868 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142871 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142878 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142881 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 142885 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 142889 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 142893 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 142897 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 142902 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 142906 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 142910 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 142914 */   // MIs[2] Operand 1
     /* 142914 */   // No operand predicates
     /* 142914 */   // MIs[0] Rn
     /* 142914 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 142918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 142922 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 142924 */   // (atomic_store (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15937>>  =>  (STL1 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 142924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 142927 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 142931 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 142934 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 142936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 142942 */   GIR_RootConstrainSelectedInstOperands,
     /* 142943 */   // GIR_Coverage, 7521,
     /* 142943 */   GIR_EraseRootFromParent_Done,
     /* 142944 */ // Label 2476: @142944
     /* 142944 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(143042), // Rule ID 7523 //
     /* 142949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 142952 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142955 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142962 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 142965 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 142969 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 142973 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 142977 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142982 */   // MIs[0] Rn
     /* 142982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 142986 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 142990 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 142992 */   // (atomic_store (bitconvert:{ *:[i64] } VecListOne64:{ *:[v1f64] }:$Vt), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15937>>  =>  (STL1 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, VecListOne64:{ *:[v1f64] }:$Vt, dsub:{ *:[i32] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn)
     /* 142992 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 142995 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142999 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143004 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 143007 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 143011 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 143014 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143019 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 143027 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143030 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143033 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 143035 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 143040 */   GIR_RootConstrainSelectedInstOperands,
     /* 143041 */   // GIR_Coverage, 7523,
     /* 143041 */   GIR_EraseRootFromParent_Done,
     /* 143042 */ // Label 2477: @143042
     /* 143042 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(143079), // Rule ID 7169 //
     /* 143047 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 143050 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 143057 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 143060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 143064 */   // MIs[0] ptr
     /* 143064 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 143068 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 143072 */   // (atomic_store GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_15937>>  =>  (STLRX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 143072 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRX),
     /* 143077 */   GIR_RootConstrainSelectedInstOperands,
     /* 143078 */   // GIR_Coverage, 7169,
     /* 143078 */   GIR_Done,
     /* 143079 */ // Label 2478: @143079
     /* 143079 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(143106), // Rule ID 6479 //
     /* 143084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143087 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143091 */   // MIs[0] Rn
     /* 143091 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 143095 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 143099 */   // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 143099 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev1d),
     /* 143104 */   GIR_RootConstrainSelectedInstOperands,
     /* 143105 */   // GIR_Coverage, 6479,
     /* 143105 */   GIR_Done,
     /* 143106 */ // Label 2479: @143106
     /* 143106 */ GIM_Reject,
     /* 143107 */ // Label 2327: @143107
     /* 143107 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(143312),
     /* 143112 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143115 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143119 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143127 */   GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(143168), // Rule ID 4513 //
     /* 143132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
     /* 143135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 143142 */     // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 143142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 143145 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143162 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143166 */     GIR_RootConstrainSelectedInstOperands,
     /* 143167 */     // GIR_Coverage, 4513,
     /* 143167 */     GIR_EraseRootFromParent_Done,
     /* 143168 */   // Label 2481: @143168
     /* 143168 */   GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(143209), // Rule ID 4514 //
     /* 143173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
     /* 143176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 143183 */     // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 143183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 143186 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143207 */     GIR_RootConstrainSelectedInstOperands,
     /* 143208 */     // GIR_Coverage, 4514,
     /* 143208 */     GIR_EraseRootFromParent_Done,
     /* 143209 */   // Label 2482: @143209
     /* 143209 */   GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(143242), // Rule ID 4568 //
     /* 143214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 143221 */     // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 143221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 143224 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143240 */     GIR_RootConstrainSelectedInstOperands,
     /* 143241 */     // GIR_Coverage, 4568,
     /* 143241 */     GIR_EraseRootFromParent_Done,
     /* 143242 */   // Label 2483: @143242
     /* 143242 */   GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(143275), // Rule ID 4592 //
     /* 143247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 143254 */     // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 143254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 143257 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143273 */     GIR_RootConstrainSelectedInstOperands,
     /* 143274 */     // GIR_Coverage, 4592,
     /* 143274 */     GIR_EraseRootFromParent_Done,
     /* 143275 */   // Label 2484: @143275
     /* 143275 */   GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(143311), // Rule ID 329 //
     /* 143280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 143283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 143290 */     // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 143290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 143293 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143309 */     GIR_RootConstrainSelectedInstOperands,
     /* 143310 */     // GIR_Coverage, 329,
     /* 143310 */     GIR_EraseRootFromParent_Done,
     /* 143311 */   // Label 2485: @143311
     /* 143311 */   GIM_Reject,
     /* 143312 */ // Label 2480: @143312
     /* 143312 */ GIM_Reject,
     /* 143313 */ // Label 2328: @143313
     /* 143313 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(143718),
     /* 143318 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143321 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143325 */   GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(143374), // Rule ID 4521 //
     /* 143330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 143348 */     // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 143348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 143351 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143372 */     GIR_RootConstrainSelectedInstOperands,
     /* 143373 */     // GIR_Coverage, 4521,
     /* 143373 */     GIR_EraseRootFromParent_Done,
     /* 143374 */   // Label 2487: @143374
     /* 143374 */   GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(143423), // Rule ID 4522 //
     /* 143379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 143397 */     // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 143397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 143400 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143421 */     GIR_RootConstrainSelectedInstOperands,
     /* 143422 */     // GIR_Coverage, 4522,
     /* 143422 */     GIR_EraseRootFromParent_Done,
     /* 143423 */   // Label 2488: @143423
     /* 143423 */   GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(143472), // Rule ID 4523 //
     /* 143428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 143446 */     // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 143446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 143449 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143470 */     GIR_RootConstrainSelectedInstOperands,
     /* 143471 */     // GIR_Coverage, 4523,
     /* 143471 */     GIR_EraseRootFromParent_Done,
     /* 143472 */   // Label 2489: @143472
     /* 143472 */   GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(143521), // Rule ID 4524 //
     /* 143477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 143495 */     // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 143495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 143498 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143515 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143519 */     GIR_RootConstrainSelectedInstOperands,
     /* 143520 */     // GIR_Coverage, 4524,
     /* 143520 */     GIR_EraseRootFromParent_Done,
     /* 143521 */   // Label 2490: @143521
     /* 143521 */   GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(143565), // Rule ID 4563 //
     /* 143526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 143544 */     // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 143544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 143547 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143563 */     GIR_RootConstrainSelectedInstOperands,
     /* 143564 */     // GIR_Coverage, 4563,
     /* 143564 */     GIR_EraseRootFromParent_Done,
     /* 143565 */   // Label 2491: @143565
     /* 143565 */   GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(143609), // Rule ID 4566 //
     /* 143570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 143588 */     // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 143588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 143591 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143607 */     GIR_RootConstrainSelectedInstOperands,
     /* 143608 */     // GIR_Coverage, 4566,
     /* 143608 */     GIR_EraseRootFromParent_Done,
     /* 143609 */   // Label 2492: @143609
     /* 143609 */   GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(143653), // Rule ID 4587 //
     /* 143614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 143632 */     // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 143632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 143635 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143651 */     GIR_RootConstrainSelectedInstOperands,
     /* 143652 */     // GIR_Coverage, 4587,
     /* 143652 */     GIR_EraseRootFromParent_Done,
     /* 143653 */   // Label 2493: @143653
     /* 143653 */   GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(143697), // Rule ID 4590 //
     /* 143658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 143676 */     // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 143676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 143679 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143695 */     GIR_RootConstrainSelectedInstOperands,
     /* 143696 */     // GIR_Coverage, 4590,
     /* 143696 */     GIR_EraseRootFromParent_Done,
     /* 143697 */   // Label 2494: @143697
     /* 143697 */   GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(143717), // Rule ID 6478 //
     /* 143702 */     // MIs[0] Rn
     /* 143702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 143706 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 143710 */     // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 143710 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2s),
     /* 143715 */     GIR_RootConstrainSelectedInstOperands,
     /* 143716 */     // GIR_Coverage, 6478,
     /* 143716 */     GIR_Done,
     /* 143717 */   // Label 2495: @143717
     /* 143717 */   GIM_Reject,
     /* 143718 */ // Label 2486: @143718
     /* 143718 */ GIM_Reject,
     /* 143719 */ // Label 2329: @143719
     /* 143719 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(144168),
     /* 143724 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143727 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143731 */   GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(143780), // Rule ID 4535 //
     /* 143736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 143739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 143754 */     // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 143754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 143757 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143774 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143778 */     GIR_RootConstrainSelectedInstOperands,
     /* 143779 */     // GIR_Coverage, 4535,
     /* 143779 */     GIR_EraseRootFromParent_Done,
     /* 143780 */   // Label 2497: @143780
     /* 143780 */   GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(143829), // Rule ID 4536 //
     /* 143785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 143788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 143803 */     // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 143803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 143806 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143823 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143827 */     GIR_RootConstrainSelectedInstOperands,
     /* 143828 */     // GIR_Coverage, 4536,
     /* 143828 */     GIR_EraseRootFromParent_Done,
     /* 143829 */   // Label 2498: @143829
     /* 143829 */   GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(143878), // Rule ID 4537 //
     /* 143834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 143837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 143852 */     // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 143852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 143855 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143876 */     GIR_RootConstrainSelectedInstOperands,
     /* 143877 */     // GIR_Coverage, 4537,
     /* 143877 */     GIR_EraseRootFromParent_Done,
     /* 143878 */   // Label 2499: @143878
     /* 143878 */   GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(143927), // Rule ID 4538 //
     /* 143883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 143886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 143901 */     // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 143901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 143904 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 143916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 143921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143925 */     GIR_RootConstrainSelectedInstOperands,
     /* 143926 */     // GIR_Coverage, 4538,
     /* 143926 */     GIR_EraseRootFromParent_Done,
     /* 143927 */   // Label 2500: @143927
     /* 143927 */   GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(143971), // Rule ID 4570 //
     /* 143932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 143950 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 143950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 143953 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143969 */     GIR_RootConstrainSelectedInstOperands,
     /* 143970 */     // GIR_Coverage, 4570,
     /* 143970 */     GIR_EraseRootFromParent_Done,
     /* 143971 */   // Label 2501: @143971
     /* 143971 */   GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(144015), // Rule ID 4574 //
     /* 143976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 143979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 143983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 143994 */     // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 143994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 143997 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 143999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144013 */     GIR_RootConstrainSelectedInstOperands,
     /* 144014 */     // GIR_Coverage, 4574,
     /* 144014 */     GIR_EraseRootFromParent_Done,
     /* 144015 */   // Label 2502: @144015
     /* 144015 */   GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(144059), // Rule ID 4594 //
     /* 144020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144038 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 144041 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144057 */     GIR_RootConstrainSelectedInstOperands,
     /* 144058 */     // GIR_Coverage, 4594,
     /* 144058 */     GIR_EraseRootFromParent_Done,
     /* 144059 */   // Label 2503: @144059
     /* 144059 */   GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(144103), // Rule ID 4598 //
     /* 144064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144082 */     // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 144085 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144101 */     GIR_RootConstrainSelectedInstOperands,
     /* 144102 */     // GIR_Coverage, 4598,
     /* 144102 */     GIR_EraseRootFromParent_Done,
     /* 144103 */   // Label 2504: @144103
     /* 144103 */   GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(144147), // Rule ID 4599 //
     /* 144108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144126 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 144129 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144145 */     GIR_RootConstrainSelectedInstOperands,
     /* 144146 */     // GIR_Coverage, 4599,
     /* 144146 */     GIR_EraseRootFromParent_Done,
     /* 144147 */   // Label 2505: @144147
     /* 144147 */   GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(144167), // Rule ID 6475 //
     /* 144152 */     // MIs[0] Rn
     /* 144152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144156 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144160 */     // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 144160 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2d),
     /* 144165 */     GIR_RootConstrainSelectedInstOperands,
     /* 144166 */     // GIR_Coverage, 6475,
     /* 144166 */     GIR_Done,
     /* 144167 */   // Label 2506: @144167
     /* 144167 */   GIM_Reject,
     /* 144168 */ // Label 2496: @144168
     /* 144168 */ GIM_Reject,
     /* 144169 */ // Label 2330: @144169
     /* 144169 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(144574),
     /* 144174 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144177 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144181 */   GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(144230), // Rule ID 4525 //
     /* 144186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 144204 */     // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 144204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 144207 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144228 */     GIR_RootConstrainSelectedInstOperands,
     /* 144229 */     // GIR_Coverage, 4525,
     /* 144229 */     GIR_EraseRootFromParent_Done,
     /* 144230 */   // Label 2508: @144230
     /* 144230 */   GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(144279), // Rule ID 4526 //
     /* 144235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144246 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 144253 */     // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 144253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 144256 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144277 */     GIR_RootConstrainSelectedInstOperands,
     /* 144278 */     // GIR_Coverage, 4526,
     /* 144278 */     GIR_EraseRootFromParent_Done,
     /* 144279 */   // Label 2509: @144279
     /* 144279 */   GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(144328), // Rule ID 4529 //
     /* 144284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 144302 */     // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 144302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 144305 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144326 */     GIR_RootConstrainSelectedInstOperands,
     /* 144327 */     // GIR_Coverage, 4529,
     /* 144327 */     GIR_EraseRootFromParent_Done,
     /* 144328 */   // Label 2510: @144328
     /* 144328 */   GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(144377), // Rule ID 4530 //
     /* 144333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 144351 */     // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 144351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 144354 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144375 */     GIR_RootConstrainSelectedInstOperands,
     /* 144376 */     // GIR_Coverage, 4530,
     /* 144376 */     GIR_EraseRootFromParent_Done,
     /* 144377 */   // Label 2511: @144377
     /* 144377 */   GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(144421), // Rule ID 4565 //
     /* 144382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 144400 */     // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 144400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 144403 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144419 */     GIR_RootConstrainSelectedInstOperands,
     /* 144420 */     // GIR_Coverage, 4565,
     /* 144420 */     GIR_EraseRootFromParent_Done,
     /* 144421 */   // Label 2512: @144421
     /* 144421 */   GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(144465), // Rule ID 4567 //
     /* 144426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 144444 */     // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 144444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 144447 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144463 */     GIR_RootConstrainSelectedInstOperands,
     /* 144464 */     // GIR_Coverage, 4567,
     /* 144464 */     GIR_EraseRootFromParent_Done,
     /* 144465 */   // Label 2513: @144465
     /* 144465 */   GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(144509), // Rule ID 4589 //
     /* 144470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144488 */     // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 144491 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144507 */     GIR_RootConstrainSelectedInstOperands,
     /* 144508 */     // GIR_Coverage, 4589,
     /* 144508 */     GIR_EraseRootFromParent_Done,
     /* 144509 */   // Label 2514: @144509
     /* 144509 */   GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(144553), // Rule ID 4591 //
     /* 144514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144532 */     // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 144535 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144551 */     GIR_RootConstrainSelectedInstOperands,
     /* 144552 */     // GIR_Coverage, 4591,
     /* 144552 */     GIR_EraseRootFromParent_Done,
     /* 144553 */   // Label 2515: @144553
     /* 144553 */   GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(144573), // Rule ID 6477 //
     /* 144558 */     // MIs[0] Rn
     /* 144558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144566 */     // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 144566 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4h),
     /* 144571 */     GIR_RootConstrainSelectedInstOperands,
     /* 144572 */     // GIR_Coverage, 6477,
     /* 144572 */     GIR_Done,
     /* 144573 */   // Label 2516: @144573
     /* 144573 */   GIM_Reject,
     /* 144574 */ // Label 2507: @144574
     /* 144574 */ GIM_Reject,
     /* 144575 */ // Label 2331: @144575
     /* 144575 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(144980),
     /* 144580 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144583 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144587 */   GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(144636), // Rule ID 4539 //
     /* 144592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 144595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 144610 */     // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 144610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 144613 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144634 */     GIR_RootConstrainSelectedInstOperands,
     /* 144635 */     // GIR_Coverage, 4539,
     /* 144635 */     GIR_EraseRootFromParent_Done,
     /* 144636 */   // Label 2518: @144636
     /* 144636 */   GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(144685), // Rule ID 4540 //
     /* 144641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 144644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 144659 */     // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 144659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 144662 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144683 */     GIR_RootConstrainSelectedInstOperands,
     /* 144684 */     // GIR_Coverage, 4540,
     /* 144684 */     GIR_EraseRootFromParent_Done,
     /* 144685 */   // Label 2519: @144685
     /* 144685 */   GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(144734), // Rule ID 4541 //
     /* 144690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 144693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 144708 */     // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 144708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 144711 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144732 */     GIR_RootConstrainSelectedInstOperands,
     /* 144733 */     // GIR_Coverage, 4541,
     /* 144733 */     GIR_EraseRootFromParent_Done,
     /* 144734 */   // Label 2520: @144734
     /* 144734 */   GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(144783), // Rule ID 4542 //
     /* 144739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 144742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 144757 */     // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 144757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 144760 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144777 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144781 */     GIR_RootConstrainSelectedInstOperands,
     /* 144782 */     // GIR_Coverage, 4542,
     /* 144782 */     GIR_EraseRootFromParent_Done,
     /* 144783 */   // Label 2521: @144783
     /* 144783 */   GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(144827), // Rule ID 4569 //
     /* 144788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 144806 */     // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 144806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 144809 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144825 */     GIR_RootConstrainSelectedInstOperands,
     /* 144826 */     // GIR_Coverage, 4569,
     /* 144826 */     GIR_EraseRootFromParent_Done,
     /* 144827 */   // Label 2522: @144827
     /* 144827 */   GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(144871), // Rule ID 4573 //
     /* 144832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144839 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 144850 */     // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 144850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 144853 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144865 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144869 */     GIR_RootConstrainSelectedInstOperands,
     /* 144870 */     // GIR_Coverage, 4573,
     /* 144870 */     GIR_EraseRootFromParent_Done,
     /* 144871 */   // Label 2523: @144871
     /* 144871 */   GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(144915), // Rule ID 4593 //
     /* 144876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144894 */     // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 144897 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144913 */     GIR_RootConstrainSelectedInstOperands,
     /* 144914 */     // GIR_Coverage, 4593,
     /* 144914 */     GIR_EraseRootFromParent_Done,
     /* 144915 */   // Label 2524: @144915
     /* 144915 */   GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(144959), // Rule ID 4597 //
     /* 144920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144938 */     // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 144941 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 144943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144957 */     GIR_RootConstrainSelectedInstOperands,
     /* 144958 */     // GIR_Coverage, 4597,
     /* 144958 */     GIR_EraseRootFromParent_Done,
     /* 144959 */   // Label 2525: @144959
     /* 144959 */   GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(144979), // Rule ID 6474 //
     /* 144964 */     // MIs[0] Rn
     /* 144964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144968 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144972 */     // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 144972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4s),
     /* 144977 */     GIR_RootConstrainSelectedInstOperands,
     /* 144978 */     // GIR_Coverage, 6474,
     /* 144978 */     GIR_Done,
     /* 144979 */   // Label 2526: @144979
     /* 144979 */   GIM_Reject,
     /* 144980 */ // Label 2517: @144980
     /* 144980 */ GIM_Reject,
     /* 144981 */ // Label 2332: @144981
     /* 144981 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(145200),
     /* 144986 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144989 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144993 */   GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(145042), // Rule ID 4527 //
     /* 144998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 145016 */     // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 145016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 145019 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145040 */     GIR_RootConstrainSelectedInstOperands,
     /* 145041 */     // GIR_Coverage, 4527,
     /* 145041 */     GIR_EraseRootFromParent_Done,
     /* 145042 */   // Label 2528: @145042
     /* 145042 */   GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(145091), // Rule ID 4528 //
     /* 145047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 145065 */     // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 145065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 145068 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145089 */     GIR_RootConstrainSelectedInstOperands,
     /* 145090 */     // GIR_Coverage, 4528,
     /* 145090 */     GIR_EraseRootFromParent_Done,
     /* 145091 */   // Label 2529: @145091
     /* 145091 */   GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(145135), // Rule ID 4564 //
     /* 145096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 145114 */     // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 145114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 145117 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145133 */     GIR_RootConstrainSelectedInstOperands,
     /* 145134 */     // GIR_Coverage, 4564,
     /* 145134 */     GIR_EraseRootFromParent_Done,
     /* 145135 */   // Label 2530: @145135
     /* 145135 */   GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(145179), // Rule ID 4588 //
     /* 145140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 145158 */     // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 145161 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145177 */     GIR_RootConstrainSelectedInstOperands,
     /* 145178 */     // GIR_Coverage, 4588,
     /* 145178 */     GIR_EraseRootFromParent_Done,
     /* 145179 */   // Label 2531: @145179
     /* 145179 */   GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(145199), // Rule ID 6476 //
     /* 145184 */     // MIs[0] Rn
     /* 145184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145188 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145192 */     // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 145192 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8b),
     /* 145197 */     GIR_RootConstrainSelectedInstOperands,
     /* 145198 */     // GIR_Coverage, 6476,
     /* 145198 */     GIR_Done,
     /* 145199 */   // Label 2532: @145199
     /* 145199 */   GIM_Reject,
     /* 145200 */ // Label 2527: @145200
     /* 145200 */ GIM_Reject,
     /* 145201 */ // Label 2333: @145201
     /* 145201 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(145606),
     /* 145206 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145209 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145213 */   GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(145262), // Rule ID 4543 //
     /* 145218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 145236 */     // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 145236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 145239 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145260 */     GIR_RootConstrainSelectedInstOperands,
     /* 145261 */     // GIR_Coverage, 4543,
     /* 145261 */     GIR_EraseRootFromParent_Done,
     /* 145262 */   // Label 2534: @145262
     /* 145262 */   GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(145311), // Rule ID 4544 //
     /* 145267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 145285 */     // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 145285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 145288 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145309 */     GIR_RootConstrainSelectedInstOperands,
     /* 145310 */     // GIR_Coverage, 4544,
     /* 145310 */     GIR_EraseRootFromParent_Done,
     /* 145311 */   // Label 2535: @145311
     /* 145311 */   GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(145360), // Rule ID 4547 //
     /* 145316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 145334 */     // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 145334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 145337 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145358 */     GIR_RootConstrainSelectedInstOperands,
     /* 145359 */     // GIR_Coverage, 4547,
     /* 145359 */     GIR_EraseRootFromParent_Done,
     /* 145360 */   // Label 2536: @145360
     /* 145360 */   GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(145409), // Rule ID 4548 //
     /* 145365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 145383 */     // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 145383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 145386 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145407 */     GIR_RootConstrainSelectedInstOperands,
     /* 145408 */     // GIR_Coverage, 4548,
     /* 145408 */     GIR_EraseRootFromParent_Done,
     /* 145409 */   // Label 2537: @145409
     /* 145409 */   GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(145453), // Rule ID 4572 //
     /* 145414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145432 */     // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 145435 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145451 */     GIR_RootConstrainSelectedInstOperands,
     /* 145452 */     // GIR_Coverage, 4572,
     /* 145452 */     GIR_EraseRootFromParent_Done,
     /* 145453 */   // Label 2538: @145453
     /* 145453 */   GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(145497), // Rule ID 4575 //
     /* 145458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145476 */     // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 145479 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145495 */     GIR_RootConstrainSelectedInstOperands,
     /* 145496 */     // GIR_Coverage, 4575,
     /* 145496 */     GIR_EraseRootFromParent_Done,
     /* 145497 */   // Label 2539: @145497
     /* 145497 */   GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(145541), // Rule ID 4596 //
     /* 145502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145520 */     // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 145523 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145539 */     GIR_RootConstrainSelectedInstOperands,
     /* 145540 */     // GIR_Coverage, 4596,
     /* 145540 */     GIR_EraseRootFromParent_Done,
     /* 145541 */   // Label 2540: @145541
     /* 145541 */   GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(145585), // Rule ID 4600 //
     /* 145546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145564 */     // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 145567 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145583 */     GIR_RootConstrainSelectedInstOperands,
     /* 145584 */     // GIR_Coverage, 4600,
     /* 145584 */     GIR_EraseRootFromParent_Done,
     /* 145585 */   // Label 2541: @145585
     /* 145585 */   GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(145605), // Rule ID 6473 //
     /* 145590 */     // MIs[0] Rn
     /* 145590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145598 */     // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 145598 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8h),
     /* 145603 */     GIR_RootConstrainSelectedInstOperands,
     /* 145604 */     // GIR_Coverage, 6473,
     /* 145604 */     GIR_Done,
     /* 145605 */   // Label 2542: @145605
     /* 145605 */   GIM_Reject,
     /* 145606 */ // Label 2533: @145606
     /* 145606 */ GIM_Reject,
     /* 145607 */ // Label 2334: @145607
     /* 145607 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(145826),
     /* 145612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145615 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145619 */   GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(145668), // Rule ID 4545 //
     /* 145624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 145642 */     // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 145642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 145645 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145662 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145666 */     GIR_RootConstrainSelectedInstOperands,
     /* 145667 */     // GIR_Coverage, 4545,
     /* 145667 */     GIR_EraseRootFromParent_Done,
     /* 145668 */   // Label 2544: @145668
     /* 145668 */   GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(145717), // Rule ID 4546 //
     /* 145673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 145676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 145691 */     // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 145691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 145694 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145715 */     GIR_RootConstrainSelectedInstOperands,
     /* 145716 */     // GIR_Coverage, 4546,
     /* 145716 */     GIR_EraseRootFromParent_Done,
     /* 145717 */   // Label 2545: @145717
     /* 145717 */   GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(145761), // Rule ID 4571 //
     /* 145722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145740 */     // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 145743 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145759 */     GIR_RootConstrainSelectedInstOperands,
     /* 145760 */     // GIR_Coverage, 4571,
     /* 145760 */     GIR_EraseRootFromParent_Done,
     /* 145761 */   // Label 2546: @145761
     /* 145761 */   GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(145805), // Rule ID 4595 //
     /* 145766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145784 */     // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 145787 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 145789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145803 */     GIR_RootConstrainSelectedInstOperands,
     /* 145804 */     // GIR_Coverage, 4595,
     /* 145804 */     GIR_EraseRootFromParent_Done,
     /* 145805 */   // Label 2547: @145805
     /* 145805 */   GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(145825), // Rule ID 6472 //
     /* 145810 */     // MIs[0] Rn
     /* 145810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145814 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145818 */     // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 145818 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev16b),
     /* 145823 */     GIR_RootConstrainSelectedInstOperands,
     /* 145824 */     // GIR_Coverage, 6472,
     /* 145824 */     GIR_Done,
     /* 145825 */   // Label 2548: @145825
     /* 145825 */   GIM_Reject,
     /* 145826 */ // Label 2543: @145826
     /* 145826 */ GIM_Reject,
     /* 145827 */ // Label 2335: @145827
     /* 145827 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(145886), // Rule ID 10997 //
     /* 145832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 145835 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145838 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145842 */   // MIs[0] base
     /* 145842 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145846 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 145850 */   // (st nxv2f16:{ *:[nxv2f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_D_IMM ZPR:{ *:[nxv2f16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 145850 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 145853 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 145857 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 145862 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 145865 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 145867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_D_IMM),
     /* 145870 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 145872 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 145875 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 145877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 145880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145884 */   GIR_RootConstrainSelectedInstOperands,
     /* 145885 */   // GIR_Coverage, 10997,
     /* 145885 */   GIR_EraseRootFromParent_Done,
     /* 145886 */ // Label 2549: @145886
     /* 145886 */ GIM_Reject,
     /* 145887 */ // Label 2336: @145887
     /* 145887 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(145946), // Rule ID 11003 //
     /* 145892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 145895 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145898 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145902 */   // MIs[0] base
     /* 145902 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145906 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 145910 */   // (st nxv2f32:{ *:[nxv2f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_D_IMM ZPR:{ *:[nxv2f32] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 145910 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 145913 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 145917 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 145922 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 145925 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 145927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_D_IMM),
     /* 145930 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 145932 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 145935 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 145937 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 145940 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145944 */   GIR_RootConstrainSelectedInstOperands,
     /* 145945 */   // GIR_Coverage, 11003,
     /* 145945 */   GIR_EraseRootFromParent_Done,
     /* 145946 */ // Label 2550: @145946
     /* 145946 */ GIM_Reject,
     /* 145947 */ // Label 2337: @145947
     /* 145947 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(146116),
     /* 145952 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145955 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145963 */   GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(146011), // Rule ID 10988 //
     /* 145968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 145971 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 145975 */     // (st nxv2i64:{ *:[nxv2i64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1D_IMM ZPR:{ *:[nxv2i64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 145975 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 145978 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 145982 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 145987 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 145990 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 145992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
     /* 145995 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 145997 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146000 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146009 */     GIR_RootConstrainSelectedInstOperands,
     /* 146010 */     // GIR_Coverage, 10988,
     /* 146010 */     GIR_EraseRootFromParent_Done,
     /* 146011 */   // Label 2552: @146011
     /* 146011 */   GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(146059), // Rule ID 11006 //
     /* 146016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146019 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146023 */     // (st nxv2f64:{ *:[nxv2f64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1D_IMM ZPR:{ *:[nxv2f64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 146030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146035 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146038 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
     /* 146043 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146045 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146048 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146057 */     GIR_RootConstrainSelectedInstOperands,
     /* 146058 */     // GIR_Coverage, 11006,
     /* 146058 */     GIR_EraseRootFromParent_Done,
     /* 146059 */   // Label 2553: @146059
     /* 146059 */   GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(146087), // Rule ID 11118 //
     /* 146064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146071 */     // (st nxv2i64:{ *:[nxv2i64] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv2i64] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146074 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146076 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146085 */     GIR_RootConstrainSelectedInstOperands,
     /* 146086 */     // GIR_Coverage, 11118,
     /* 146086 */     GIR_EraseRootFromParent_Done,
     /* 146087 */   // Label 2554: @146087
     /* 146087 */   GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(146115), // Rule ID 11130 //
     /* 146092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146095 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146099 */     // (st nxv2f64:{ *:[nxv2f64] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv2f64] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146102 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146104 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146113 */     GIR_RootConstrainSelectedInstOperands,
     /* 146114 */     // GIR_Coverage, 11130,
     /* 146114 */     GIR_EraseRootFromParent_Done,
     /* 146115 */   // Label 2555: @146115
     /* 146115 */   GIM_Reject,
     /* 146116 */ // Label 2551: @146116
     /* 146116 */ GIM_Reject,
     /* 146117 */ // Label 2338: @146117
     /* 146117 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(146176), // Rule ID 10994 //
     /* 146122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146128 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146132 */   // MIs[0] base
     /* 146132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146136 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146140 */   // (st nxv4f16:{ *:[nxv4f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_S_IMM ZPR:{ *:[nxv4f16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146140 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146143 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 146147 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146152 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146155 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_S_IMM),
     /* 146160 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146162 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146165 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146170 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146174 */   GIR_RootConstrainSelectedInstOperands,
     /* 146175 */   // GIR_Coverage, 10994,
     /* 146175 */   GIR_EraseRootFromParent_Done,
     /* 146176 */ // Label 2556: @146176
     /* 146176 */ GIM_Reject,
     /* 146177 */ // Label 2339: @146177
     /* 146177 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(146346),
     /* 146182 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146185 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146189 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146193 */   GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(146241), // Rule ID 10982 //
     /* 146198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146201 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146205 */     // (st nxv4i32:{ *:[nxv4i32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_IMM ZPR:{ *:[nxv4i32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146205 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146208 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 146212 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146217 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146220 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
     /* 146225 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146227 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146230 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146235 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146239 */     GIR_RootConstrainSelectedInstOperands,
     /* 146240 */     // GIR_Coverage, 10982,
     /* 146240 */     GIR_EraseRootFromParent_Done,
     /* 146241 */   // Label 2558: @146241
     /* 146241 */   GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(146289), // Rule ID 11000 //
     /* 146246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146249 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146253 */     // (st nxv4f32:{ *:[nxv4f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_IMM ZPR:{ *:[nxv4f32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146253 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146256 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 146260 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146265 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
     /* 146273 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146275 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146278 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146287 */     GIR_RootConstrainSelectedInstOperands,
     /* 146288 */     // GIR_Coverage, 11000,
     /* 146288 */     GIR_EraseRootFromParent_Done,
     /* 146289 */   // Label 2559: @146289
     /* 146289 */   GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(146317), // Rule ID 11114 //
     /* 146294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146301 */     // (st nxv4i32:{ *:[nxv4i32] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv4i32] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146304 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146306 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146315 */     GIR_RootConstrainSelectedInstOperands,
     /* 146316 */     // GIR_Coverage, 11114,
     /* 146316 */     GIR_EraseRootFromParent_Done,
     /* 146317 */   // Label 2560: @146317
     /* 146317 */   GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(146345), // Rule ID 11126 //
     /* 146322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146325 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146329 */     // (st nxv4f32:{ *:[nxv4f32] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv4f32] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146332 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146334 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146343 */     GIR_RootConstrainSelectedInstOperands,
     /* 146344 */     // GIR_Coverage, 11126,
     /* 146344 */     GIR_EraseRootFromParent_Done,
     /* 146345 */   // Label 2561: @146345
     /* 146345 */   GIM_Reject,
     /* 146346 */ // Label 2557: @146346
     /* 146346 */ GIM_Reject,
     /* 146347 */ // Label 2340: @146347
     /* 146347 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(146516),
     /* 146352 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146355 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146359 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146363 */   GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(146411), // Rule ID 10973 //
     /* 146368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146371 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146375 */     // (st nxv8i16:{ *:[nxv8i16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_IMM ZPR:{ *:[nxv8i16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146375 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146378 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 146382 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146387 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146390 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
     /* 146395 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146397 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146400 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146409 */     GIR_RootConstrainSelectedInstOperands,
     /* 146410 */     // GIR_Coverage, 10973,
     /* 146410 */     GIR_EraseRootFromParent_Done,
     /* 146411 */   // Label 2563: @146411
     /* 146411 */   GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(146459), // Rule ID 10991 //
     /* 146416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146423 */     // (st nxv8f16:{ *:[nxv8f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_IMM ZPR:{ *:[nxv8f16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146423 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146426 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 146430 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146435 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146438 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
     /* 146443 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146445 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146448 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146457 */     GIR_RootConstrainSelectedInstOperands,
     /* 146458 */     // GIR_Coverage, 10991,
     /* 146458 */     GIR_EraseRootFromParent_Done,
     /* 146459 */   // Label 2564: @146459
     /* 146459 */   GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(146487), // Rule ID 11110 //
     /* 146464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146467 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146471 */     // (st nxv8i16:{ *:[nxv8i16] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv8i16] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146474 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146476 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146485 */     GIR_RootConstrainSelectedInstOperands,
     /* 146486 */     // GIR_Coverage, 11110,
     /* 146486 */     GIR_EraseRootFromParent_Done,
     /* 146487 */   // Label 2565: @146487
     /* 146487 */   GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(146515), // Rule ID 11122 //
     /* 146492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146495 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146499 */     // (st nxv8f16:{ *:[nxv8f16] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv8f16] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146502 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146504 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146513 */     GIR_RootConstrainSelectedInstOperands,
     /* 146514 */     // GIR_Coverage, 11122,
     /* 146514 */     GIR_EraseRootFromParent_Done,
     /* 146515 */   // Label 2566: @146515
     /* 146515 */   GIM_Reject,
     /* 146516 */ // Label 2562: @146516
     /* 146516 */ GIM_Reject,
     /* 146517 */ // Label 2341: @146517
     /* 146517 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(146560), // Rule ID 2437 //
     /* 146522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146525 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146528 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146532 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 146536 */   // MIs[0] base
     /* 146536 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146540 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146544 */   // (st PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_PXI PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_PXI),
     /* 146547 */   GIR_RootToRootCopy, /*OpIdx*/0, // Val
     /* 146549 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146551 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146554 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146558 */   GIR_RootConstrainSelectedInstOperands,
     /* 146559 */   // GIR_Coverage, 2437,
     /* 146559 */   GIR_EraseRootFromParent_Done,
     /* 146560 */ // Label 2567: @146560
     /* 146560 */ GIM_Reject,
     /* 146561 */ // Label 2342: @146561
     /* 146561 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(146654),
     /* 146566 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146569 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146577 */   GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(146625), // Rule ID 10959 //
     /* 146582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146585 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146589 */     // (st nxv16i8:{ *:[nxv16i8] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1B_IMM ZPR:{ *:[nxv16i8] }:$val, (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146589 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146592 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 146596 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146601 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146604 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1B_IMM),
     /* 146609 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146611 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146614 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146623 */     GIR_RootConstrainSelectedInstOperands,
     /* 146624 */     // GIR_Coverage, 10959,
     /* 146624 */     GIR_EraseRootFromParent_Done,
     /* 146625 */   // Label 2569: @146625
     /* 146625 */   GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(146653), // Rule ID 11106 //
     /* 146630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_HasSVE_or_SME_IsLE),
     /* 146633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146637 */     // (st nxv16i8:{ *:[nxv16i8] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv16i8] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 146640 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 146642 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146651 */     GIR_RootConstrainSelectedInstOperands,
     /* 146652 */     // GIR_Coverage, 11106,
     /* 146652 */     GIR_EraseRootFromParent_Done,
     /* 146653 */   // Label 2570: @146653
     /* 146653 */   GIM_Reject,
     /* 146654 */ // Label 2568: @146654
     /* 146654 */ GIM_Reject,
     /* 146655 */ // Label 2343: @146655
     /* 146655 */ GIM_Reject,
     /* 146656 */ // Label 20: @146656
     /* 146656 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2573*/ GIMT_Encode4(148006),
     /* 146667 */ /*GILLT_s32*//*Label 2571*/ GIMT_Encode4(146675),
     /* 146671 */ /*GILLT_s64*//*Label 2572*/ GIMT_Encode4(147693),
     /* 146675 */ // Label 2571: @146675
     /* 146675 */ GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(147692),
     /* 146680 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 146683 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 146686 */   GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(146741), // Rule ID 7392 //
     /* 146691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146694 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 146701 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 146704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146708 */     // MIs[0] Rn
     /* 146708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146712 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146716 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146720 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146724 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>>  =>  (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASW),
     /* 146727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 146729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 146731 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 146733 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 146735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146739 */     GIR_RootConstrainSelectedInstOperands,
     /* 146740 */     // GIR_Coverage, 7392,
     /* 146740 */     GIR_EraseRootFromParent_Done,
     /* 146741 */   // Label 2575: @146741
     /* 146741 */   GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(146796), // Rule ID 7393 //
     /* 146746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146749 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 146756 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 146759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146763 */     // MIs[0] Rn
     /* 146763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146767 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146771 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146775 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146779 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>>  =>  (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAW),
     /* 146782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 146784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 146786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 146788 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 146790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146794 */     GIR_RootConstrainSelectedInstOperands,
     /* 146795 */     // GIR_Coverage, 7393,
     /* 146795 */     GIR_EraseRootFromParent_Done,
     /* 146796 */   // Label 2576: @146796
     /* 146796 */   GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(146851), // Rule ID 7394 //
     /* 146801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146804 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 146811 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 146814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146818 */     // MIs[0] Rn
     /* 146818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146822 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146826 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146830 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146834 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>>  =>  (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLW),
     /* 146837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 146839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 146841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 146843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 146845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146849 */     GIR_RootConstrainSelectedInstOperands,
     /* 146850 */     // GIR_Coverage, 7394,
     /* 146850 */     GIR_EraseRootFromParent_Done,
     /* 146851 */   // Label 2577: @146851
     /* 146851 */   GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(146906), // Rule ID 7395 //
     /* 146856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146859 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 146866 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 146869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146873 */     // MIs[0] Rn
     /* 146873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146877 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146881 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146885 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146889 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>>  =>  (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
     /* 146892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 146894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 146896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 146898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 146900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146904 */     GIR_RootConstrainSelectedInstOperands,
     /* 146905 */     // GIR_Coverage, 7395,
     /* 146905 */     GIR_EraseRootFromParent_Done,
     /* 146906 */   // Label 2578: @146906
     /* 146906 */   GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(146961), // Rule ID 7396 //
     /* 146911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146914 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 146921 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 146924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146928 */     // MIs[0] Rn
     /* 146928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146940 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146944 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>>  =>  (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
     /* 146947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 146949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 146951 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 146953 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 146955 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146959 */     GIR_RootConstrainSelectedInstOperands,
     /* 146960 */     // GIR_Coverage, 7396,
     /* 146960 */     GIR_EraseRootFromParent_Done,
     /* 146961 */   // Label 2579: @146961
     /* 146961 */   GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(147016), // Rule ID 7397 //
     /* 146966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 146969 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 146976 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 146979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146983 */     // MIs[0] Rn
     /* 146983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146987 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146991 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146995 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 146999 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>>  =>  (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 146999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASH),
     /* 147002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147004 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147006 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147014 */     GIR_RootConstrainSelectedInstOperands,
     /* 147015 */     // GIR_Coverage, 7397,
     /* 147015 */     GIR_EraseRootFromParent_Done,
     /* 147016 */   // Label 2580: @147016
     /* 147016 */   GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(147071), // Rule ID 7398 //
     /* 147021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147024 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147031 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 147034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147038 */     // MIs[0] Rn
     /* 147038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147046 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147050 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147054 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>>  =>  (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAH),
     /* 147057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147061 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147063 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147069 */     GIR_RootConstrainSelectedInstOperands,
     /* 147070 */     // GIR_Coverage, 7398,
     /* 147070 */     GIR_EraseRootFromParent_Done,
     /* 147071 */   // Label 2581: @147071
     /* 147071 */   GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(147126), // Rule ID 7399 //
     /* 147076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147079 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147086 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 147089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147093 */     // MIs[0] Rn
     /* 147093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147097 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147101 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147105 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147109 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>>  =>  (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLH),
     /* 147112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147116 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147118 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147120 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147124 */     GIR_RootConstrainSelectedInstOperands,
     /* 147125 */     // GIR_Coverage, 7399,
     /* 147125 */     GIR_EraseRootFromParent_Done,
     /* 147126 */   // Label 2582: @147126
     /* 147126 */   GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(147181), // Rule ID 7400 //
     /* 147131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147134 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147141 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 147144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147148 */     // MIs[0] Rn
     /* 147148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147160 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147164 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>>  =>  (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
     /* 147167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147173 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147175 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147179 */     GIR_RootConstrainSelectedInstOperands,
     /* 147180 */     // GIR_Coverage, 7400,
     /* 147180 */     GIR_EraseRootFromParent_Done,
     /* 147181 */   // Label 2583: @147181
     /* 147181 */   GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(147236), // Rule ID 7401 //
     /* 147186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147189 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147196 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 147199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147203 */     // MIs[0] Rn
     /* 147203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147207 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147215 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147219 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>>  =>  (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
     /* 147222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147226 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147228 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147234 */     GIR_RootConstrainSelectedInstOperands,
     /* 147235 */     // GIR_Coverage, 7401,
     /* 147235 */     GIR_EraseRootFromParent_Done,
     /* 147236 */   // Label 2584: @147236
     /* 147236 */   GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(147291), // Rule ID 7402 //
     /* 147241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147244 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147251 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 147254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147258 */     // MIs[0] Rn
     /* 147258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147262 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147266 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147270 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147274 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>>  =>  (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASB),
     /* 147277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147281 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147283 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147285 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147289 */     GIR_RootConstrainSelectedInstOperands,
     /* 147290 */     // GIR_Coverage, 7402,
     /* 147290 */     GIR_EraseRootFromParent_Done,
     /* 147291 */   // Label 2585: @147291
     /* 147291 */   GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(147346), // Rule ID 7403 //
     /* 147296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147299 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147306 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 147309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147313 */     // MIs[0] Rn
     /* 147313 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147329 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>>  =>  (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAB),
     /* 147332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147338 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147344 */     GIR_RootConstrainSelectedInstOperands,
     /* 147345 */     // GIR_Coverage, 7403,
     /* 147345 */     GIR_EraseRootFromParent_Done,
     /* 147346 */   // Label 2586: @147346
     /* 147346 */   GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(147401), // Rule ID 7404 //
     /* 147351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147354 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147361 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 147364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147368 */     // MIs[0] Rn
     /* 147368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147372 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147380 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147384 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>>  =>  (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLB),
     /* 147387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147391 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147393 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147399 */     GIR_RootConstrainSelectedInstOperands,
     /* 147400 */     // GIR_Coverage, 7404,
     /* 147400 */     GIR_EraseRootFromParent_Done,
     /* 147401 */   // Label 2587: @147401
     /* 147401 */   GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(147456), // Rule ID 7405 //
     /* 147406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147409 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147416 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 147419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147423 */     // MIs[0] Rn
     /* 147423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147427 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147431 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147435 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147439 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>>  =>  (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
     /* 147442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147446 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147448 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147454 */     GIR_RootConstrainSelectedInstOperands,
     /* 147455 */     // GIR_Coverage, 7405,
     /* 147455 */     GIR_EraseRootFromParent_Done,
     /* 147456 */   // Label 2588: @147456
     /* 147456 */   GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(147511), // Rule ID 7406 //
     /* 147461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147464 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147471 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 147474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147478 */     // MIs[0] Rn
     /* 147478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147482 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147486 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147490 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147494 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>>  =>  (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
     /* 147497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147499 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147501 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147503 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147509 */     GIR_RootConstrainSelectedInstOperands,
     /* 147510 */     // GIR_Coverage, 7406,
     /* 147510 */     GIR_EraseRootFromParent_Done,
     /* 147511 */   // Label 2589: @147511
     /* 147511 */   GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(147571), // Rule ID 13417 //
     /* 147516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 147519 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147530 */     // MIs[0] addr
     /* 147530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147534 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147538 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147542 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147546 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>>  =>  (CMP_SWAP_8:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 147546 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 147549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_8),
     /* 147552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 147554 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 147559 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 147561 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 147563 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 147565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147569 */     GIR_RootConstrainSelectedInstOperands,
     /* 147570 */     // GIR_Coverage, 13417,
     /* 147570 */     GIR_EraseRootFromParent_Done,
     /* 147571 */   // Label 2590: @147571
     /* 147571 */   GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(147631), // Rule ID 13418 //
     /* 147576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 147579 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147590 */     // MIs[0] addr
     /* 147590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147602 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147606 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>>  =>  (CMP_SWAP_16:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 147606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 147609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_16),
     /* 147612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 147614 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 147619 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 147621 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 147623 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 147625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147629 */     GIR_RootConstrainSelectedInstOperands,
     /* 147630 */     // GIR_Coverage, 13418,
     /* 147630 */     GIR_EraseRootFromParent_Done,
     /* 147631 */   // Label 2591: @147631
     /* 147631 */   GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(147691), // Rule ID 13419 //
     /* 147636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 147639 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 147646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147650 */     // MIs[0] addr
     /* 147650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147654 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147662 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147666 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>>  =>  (CMP_SWAP_32:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 147666 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 147669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_32),
     /* 147672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 147674 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 147679 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 147681 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 147683 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 147685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147689 */     GIR_RootConstrainSelectedInstOperands,
     /* 147690 */     // GIR_Coverage, 13419,
     /* 147690 */     GIR_EraseRootFromParent_Done,
     /* 147691 */   // Label 2592: @147691
     /* 147691 */   GIM_Reject,
     /* 147692 */ // Label 2574: @147692
     /* 147692 */ GIM_Reject,
     /* 147693 */ // Label 2572: @147693
     /* 147693 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(148005),
     /* 147698 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 147701 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 147704 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 147711 */   GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(147759), // Rule ID 2589 //
     /* 147716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147719 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 147722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147726 */     // MIs[0] Rn
     /* 147726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147730 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147738 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147742 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_monotonic>>  =>  (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASX),
     /* 147745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147751 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147757 */     GIR_RootConstrainSelectedInstOperands,
     /* 147758 */     // GIR_Coverage, 2589,
     /* 147758 */     GIR_EraseRootFromParent_Done,
     /* 147759 */   // Label 2594: @147759
     /* 147759 */   GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(147807), // Rule ID 2590 //
     /* 147764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147767 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 147770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147774 */     // MIs[0] Rn
     /* 147774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147778 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147786 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147790 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acquire>>  =>  (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAX),
     /* 147793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147797 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147799 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147805 */     GIR_RootConstrainSelectedInstOperands,
     /* 147806 */     // GIR_Coverage, 2590,
     /* 147806 */     GIR_EraseRootFromParent_Done,
     /* 147807 */   // Label 2595: @147807
     /* 147807 */   GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(147855), // Rule ID 2591 //
     /* 147812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147815 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 147818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147822 */     // MIs[0] Rn
     /* 147822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147826 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147830 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147834 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147838 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_release>>  =>  (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLX),
     /* 147841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147847 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147853 */     GIR_RootConstrainSelectedInstOperands,
     /* 147854 */     // GIR_Coverage, 2591,
     /* 147854 */     GIR_EraseRootFromParent_Done,
     /* 147855 */   // Label 2596: @147855
     /* 147855 */   GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(147903), // Rule ID 2592 //
     /* 147860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147863 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 147866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147870 */     // MIs[0] Rn
     /* 147870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147874 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147882 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147886 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acq_rel>>  =>  (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
     /* 147889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147893 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147895 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147901 */     GIR_RootConstrainSelectedInstOperands,
     /* 147902 */     // GIR_Coverage, 2592,
     /* 147902 */     GIR_EraseRootFromParent_Done,
     /* 147903 */   // Label 2597: @147903
     /* 147903 */   GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(147951), // Rule ID 2593 //
     /* 147908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 147911 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 147914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147918 */     // MIs[0] Rn
     /* 147918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147922 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147926 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147930 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147934 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_seq_cst>>  =>  (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 147934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
     /* 147937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 147939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 147941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 147943 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 147945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147949 */     GIR_RootConstrainSelectedInstOperands,
     /* 147950 */     // GIR_Coverage, 2593,
     /* 147950 */     GIR_EraseRootFromParent_Done,
     /* 147951 */   // Label 2598: @147951
     /* 147951 */   GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(148004), // Rule ID 13420 //
     /* 147956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 147959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147963 */     // MIs[0] addr
     /* 147963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147967 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147971 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147975 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147979 */     // (atomic_cmp_swap:{ *:[i64] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>>  =>  (CMP_SWAP_64:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)
     /* 147979 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 147982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_64),
     /* 147985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 147987 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 147992 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 147994 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 147996 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 147998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148002 */     GIR_RootConstrainSelectedInstOperands,
     /* 148003 */     // GIR_Coverage, 13420,
     /* 148003 */     GIR_EraseRootFromParent_Done,
     /* 148004 */   // Label 2599: @148004
     /* 148004 */   GIM_Reject,
     /* 148005 */ // Label 2593: @148005
     /* 148005 */ GIM_Reject,
     /* 148006 */ // Label 2573: @148006
     /* 148006 */ GIM_Reject,
     /* 148007 */ // Label 21: @148007
     /* 148007 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2602*/ GIMT_Encode4(148998),
     /* 148018 */ /*GILLT_s32*//*Label 2600*/ GIMT_Encode4(148026),
     /* 148022 */ /*GILLT_s64*//*Label 2601*/ GIMT_Encode4(148771),
     /* 148026 */ // Label 2600: @148026
     /* 148026 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(148770),
     /* 148031 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 148034 */   GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(148083), // Rule ID 7377 //
     /* 148039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148042 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148049 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 148052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148056 */     // MIs[0] Rn
     /* 148056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148060 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148064 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148068 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>>  =>  (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPW),
     /* 148071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148075 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148081 */     GIR_RootConstrainSelectedInstOperands,
     /* 148082 */     // GIR_Coverage, 7377,
     /* 148082 */     GIR_EraseRootFromParent_Done,
     /* 148083 */   // Label 2604: @148083
     /* 148083 */   GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(148132), // Rule ID 7378 //
     /* 148088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148091 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148098 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 148101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148105 */     // MIs[0] Rn
     /* 148105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148109 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148113 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148117 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>>  =>  (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAW),
     /* 148120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148124 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148130 */     GIR_RootConstrainSelectedInstOperands,
     /* 148131 */     // GIR_Coverage, 7378,
     /* 148131 */     GIR_EraseRootFromParent_Done,
     /* 148132 */   // Label 2605: @148132
     /* 148132 */   GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(148181), // Rule ID 7379 //
     /* 148137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148140 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148147 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 148150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148154 */     // MIs[0] Rn
     /* 148154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148158 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148166 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>>  =>  (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLW),
     /* 148169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148173 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148175 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148179 */     GIR_RootConstrainSelectedInstOperands,
     /* 148180 */     // GIR_Coverage, 7379,
     /* 148180 */     GIR_EraseRootFromParent_Done,
     /* 148181 */   // Label 2606: @148181
     /* 148181 */   GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(148230), // Rule ID 7380 //
     /* 148186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148189 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148196 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 148199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148203 */     // MIs[0] Rn
     /* 148203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148207 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148215 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>>  =>  (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
     /* 148218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148222 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148228 */     GIR_RootConstrainSelectedInstOperands,
     /* 148229 */     // GIR_Coverage, 7380,
     /* 148229 */     GIR_EraseRootFromParent_Done,
     /* 148230 */   // Label 2607: @148230
     /* 148230 */   GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(148279), // Rule ID 7381 //
     /* 148235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148238 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148245 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 148248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148252 */     // MIs[0] Rn
     /* 148252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148256 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148264 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>>  =>  (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
     /* 148267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148271 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148277 */     GIR_RootConstrainSelectedInstOperands,
     /* 148278 */     // GIR_Coverage, 7381,
     /* 148278 */     GIR_EraseRootFromParent_Done,
     /* 148279 */   // Label 2608: @148279
     /* 148279 */   GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(148328), // Rule ID 7382 //
     /* 148284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148287 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148294 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 148297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148301 */     // MIs[0] Rn
     /* 148301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148305 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148313 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>>  =>  (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPH),
     /* 148316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148326 */     GIR_RootConstrainSelectedInstOperands,
     /* 148327 */     // GIR_Coverage, 7382,
     /* 148327 */     GIR_EraseRootFromParent_Done,
     /* 148328 */   // Label 2609: @148328
     /* 148328 */   GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(148377), // Rule ID 7383 //
     /* 148333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148336 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148343 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 148346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148350 */     // MIs[0] Rn
     /* 148350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148354 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148362 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>>  =>  (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAH),
     /* 148365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148369 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148375 */     GIR_RootConstrainSelectedInstOperands,
     /* 148376 */     // GIR_Coverage, 7383,
     /* 148376 */     GIR_EraseRootFromParent_Done,
     /* 148377 */   // Label 2610: @148377
     /* 148377 */   GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(148426), // Rule ID 7384 //
     /* 148382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148385 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148392 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 148395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148399 */     // MIs[0] Rn
     /* 148399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148403 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148411 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>>  =>  (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLH),
     /* 148414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148418 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148424 */     GIR_RootConstrainSelectedInstOperands,
     /* 148425 */     // GIR_Coverage, 7384,
     /* 148425 */     GIR_EraseRootFromParent_Done,
     /* 148426 */   // Label 2611: @148426
     /* 148426 */   GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(148475), // Rule ID 7385 //
     /* 148431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148434 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148441 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 148444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148448 */     // MIs[0] Rn
     /* 148448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148452 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148460 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>>  =>  (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
     /* 148463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148465 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148467 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148473 */     GIR_RootConstrainSelectedInstOperands,
     /* 148474 */     // GIR_Coverage, 7385,
     /* 148474 */     GIR_EraseRootFromParent_Done,
     /* 148475 */   // Label 2612: @148475
     /* 148475 */   GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(148524), // Rule ID 7386 //
     /* 148480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148483 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148490 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 148493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148497 */     // MIs[0] Rn
     /* 148497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148509 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>>  =>  (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
     /* 148512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148516 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148522 */     GIR_RootConstrainSelectedInstOperands,
     /* 148523 */     // GIR_Coverage, 7386,
     /* 148523 */     GIR_EraseRootFromParent_Done,
     /* 148524 */   // Label 2613: @148524
     /* 148524 */   GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(148573), // Rule ID 7387 //
     /* 148529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148532 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148539 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 148542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148546 */     // MIs[0] Rn
     /* 148546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148550 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148558 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>>  =>  (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPB),
     /* 148561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148565 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148567 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148571 */     GIR_RootConstrainSelectedInstOperands,
     /* 148572 */     // GIR_Coverage, 7387,
     /* 148572 */     GIR_EraseRootFromParent_Done,
     /* 148573 */   // Label 2614: @148573
     /* 148573 */   GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(148622), // Rule ID 7388 //
     /* 148578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148581 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148588 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 148591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148595 */     // MIs[0] Rn
     /* 148595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148599 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148603 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148607 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>>  =>  (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAB),
     /* 148610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148614 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148620 */     GIR_RootConstrainSelectedInstOperands,
     /* 148621 */     // GIR_Coverage, 7388,
     /* 148621 */     GIR_EraseRootFromParent_Done,
     /* 148622 */   // Label 2615: @148622
     /* 148622 */   GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(148671), // Rule ID 7389 //
     /* 148627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148630 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148637 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 148640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148644 */     // MIs[0] Rn
     /* 148644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148652 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148656 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>>  =>  (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLB),
     /* 148659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148663 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148669 */     GIR_RootConstrainSelectedInstOperands,
     /* 148670 */     // GIR_Coverage, 7389,
     /* 148670 */     GIR_EraseRootFromParent_Done,
     /* 148671 */   // Label 2616: @148671
     /* 148671 */   GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(148720), // Rule ID 7390 //
     /* 148676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148679 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148686 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 148689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148693 */     // MIs[0] Rn
     /* 148693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148701 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148705 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>>  =>  (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
     /* 148708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148712 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148718 */     GIR_RootConstrainSelectedInstOperands,
     /* 148719 */     // GIR_Coverage, 7390,
     /* 148719 */     GIR_EraseRootFromParent_Done,
     /* 148720 */   // Label 2617: @148720
     /* 148720 */   GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(148769), // Rule ID 7391 //
     /* 148725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148728 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148735 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 148738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148742 */     // MIs[0] Rn
     /* 148742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148746 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148754 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>>  =>  (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
     /* 148757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148759 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148761 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148767 */     GIR_RootConstrainSelectedInstOperands,
     /* 148768 */     // GIR_Coverage, 7391,
     /* 148768 */     GIR_EraseRootFromParent_Done,
     /* 148769 */   // Label 2618: @148769
     /* 148769 */   GIM_Reject,
     /* 148770 */ // Label 2603: @148770
     /* 148770 */ GIM_Reject,
     /* 148771 */ // Label 2601: @148771
     /* 148771 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(148997),
     /* 148776 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 148779 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 148786 */   GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(148828), // Rule ID 7372 //
     /* 148791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148794 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 148797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148801 */     // MIs[0] Rn
     /* 148801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148805 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148813 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_monotonic>>  =>  (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPX),
     /* 148816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148820 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148826 */     GIR_RootConstrainSelectedInstOperands,
     /* 148827 */     // GIR_Coverage, 7372,
     /* 148827 */     GIR_EraseRootFromParent_Done,
     /* 148828 */   // Label 2620: @148828
     /* 148828 */   GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(148870), // Rule ID 7373 //
     /* 148833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148836 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 148839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148843 */     // MIs[0] Rn
     /* 148843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148847 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148851 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148855 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acquire>>  =>  (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAX),
     /* 148858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148860 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148862 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148868 */     GIR_RootConstrainSelectedInstOperands,
     /* 148869 */     // GIR_Coverage, 7373,
     /* 148869 */     GIR_EraseRootFromParent_Done,
     /* 148870 */   // Label 2621: @148870
     /* 148870 */   GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(148912), // Rule ID 7374 //
     /* 148875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148878 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 148881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148885 */     // MIs[0] Rn
     /* 148885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148889 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148897 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_release>>  =>  (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLX),
     /* 148900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148904 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148910 */     GIR_RootConstrainSelectedInstOperands,
     /* 148911 */     // GIR_Coverage, 7374,
     /* 148911 */     GIR_EraseRootFromParent_Done,
     /* 148912 */   // Label 2622: @148912
     /* 148912 */   GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(148954), // Rule ID 7375 //
     /* 148917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148920 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 148923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148927 */     // MIs[0] Rn
     /* 148927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148931 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148935 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148939 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acq_rel>>  =>  (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
     /* 148942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148952 */     GIR_RootConstrainSelectedInstOperands,
     /* 148953 */     // GIR_Coverage, 7375,
     /* 148953 */     GIR_EraseRootFromParent_Done,
     /* 148954 */   // Label 2623: @148954
     /* 148954 */   GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(148996), // Rule ID 7376 //
     /* 148959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 148962 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 148965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148969 */     // MIs[0] Rn
     /* 148969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 148973 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 148977 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148981 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_seq_cst>>  =>  (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 148981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
     /* 148984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 148988 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 148990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148994 */     GIR_RootConstrainSelectedInstOperands,
     /* 148995 */     // GIR_Coverage, 7376,
     /* 148995 */     GIR_EraseRootFromParent_Done,
     /* 148996 */   // Label 2624: @148996
     /* 148996 */   GIM_Reject,
     /* 148997 */ // Label 2619: @148997
     /* 148997 */ GIM_Reject,
     /* 148998 */ // Label 2602: @148998
     /* 148998 */ GIM_Reject,
     /* 148999 */ // Label 22: @148999
     /* 148999 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2627*/ GIMT_Encode4(149990),
     /* 149010 */ /*GILLT_s32*//*Label 2625*/ GIMT_Encode4(149018),
     /* 149014 */ /*GILLT_s64*//*Label 2626*/ GIMT_Encode4(149763),
     /* 149018 */ // Label 2625: @149018
     /* 149018 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(149762),
     /* 149023 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 149026 */   GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(149075), // Rule ID 7217 //
     /* 149031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149034 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 149041 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 149044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149048 */     // MIs[0] Rn
     /* 149048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149052 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149056 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149060 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>>  =>  (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
     /* 149063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149067 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149069 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149073 */     GIR_RootConstrainSelectedInstOperands,
     /* 149074 */     // GIR_Coverage, 7217,
     /* 149074 */     GIR_EraseRootFromParent_Done,
     /* 149075 */   // Label 2629: @149075
     /* 149075 */   GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(149124), // Rule ID 7218 //
     /* 149080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149083 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 149090 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149097 */     // MIs[0] Rn
     /* 149097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149101 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149105 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149109 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>>  =>  (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
     /* 149112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149116 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149122 */     GIR_RootConstrainSelectedInstOperands,
     /* 149123 */     // GIR_Coverage, 7218,
     /* 149123 */     GIR_EraseRootFromParent_Done,
     /* 149124 */   // Label 2630: @149124
     /* 149124 */   GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(149173), // Rule ID 7219 //
     /* 149129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149132 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 149139 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 149142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149146 */     // MIs[0] Rn
     /* 149146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149150 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149158 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>>  =>  (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
     /* 149161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149165 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149171 */     GIR_RootConstrainSelectedInstOperands,
     /* 149172 */     // GIR_Coverage, 7219,
     /* 149172 */     GIR_EraseRootFromParent_Done,
     /* 149173 */   // Label 2631: @149173
     /* 149173 */   GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(149222), // Rule ID 7220 //
     /* 149178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149181 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 149188 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 149191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149195 */     // MIs[0] Rn
     /* 149195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149199 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149207 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>>  =>  (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 149210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149214 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149220 */     GIR_RootConstrainSelectedInstOperands,
     /* 149221 */     // GIR_Coverage, 7220,
     /* 149221 */     GIR_EraseRootFromParent_Done,
     /* 149222 */   // Label 2632: @149222
     /* 149222 */   GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(149271), // Rule ID 7221 //
     /* 149227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149230 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 149237 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 149240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149244 */     // MIs[0] Rn
     /* 149244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149248 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149252 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149256 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>>  =>  (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 149259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149263 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149269 */     GIR_RootConstrainSelectedInstOperands,
     /* 149270 */     // GIR_Coverage, 7221,
     /* 149270 */     GIR_EraseRootFromParent_Done,
     /* 149271 */   // Label 2633: @149271
     /* 149271 */   GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(149320), // Rule ID 7222 //
     /* 149276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149279 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149286 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 149289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149293 */     // MIs[0] Rn
     /* 149293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149301 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149305 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>>  =>  (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
     /* 149308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149312 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149318 */     GIR_RootConstrainSelectedInstOperands,
     /* 149319 */     // GIR_Coverage, 7222,
     /* 149319 */     GIR_EraseRootFromParent_Done,
     /* 149320 */   // Label 2634: @149320
     /* 149320 */   GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(149369), // Rule ID 7223 //
     /* 149325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149328 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149335 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149342 */     // MIs[0] Rn
     /* 149342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149346 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149350 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149354 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>>  =>  (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
     /* 149357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149361 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149367 */     GIR_RootConstrainSelectedInstOperands,
     /* 149368 */     // GIR_Coverage, 7223,
     /* 149368 */     GIR_EraseRootFromParent_Done,
     /* 149369 */   // Label 2635: @149369
     /* 149369 */   GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(149418), // Rule ID 7224 //
     /* 149374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149377 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149384 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 149387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149391 */     // MIs[0] Rn
     /* 149391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149395 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149403 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>>  =>  (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
     /* 149406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149410 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149416 */     GIR_RootConstrainSelectedInstOperands,
     /* 149417 */     // GIR_Coverage, 7224,
     /* 149417 */     GIR_EraseRootFromParent_Done,
     /* 149418 */   // Label 2636: @149418
     /* 149418 */   GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(149467), // Rule ID 7225 //
     /* 149423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149426 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149433 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 149436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149440 */     // MIs[0] Rn
     /* 149440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149444 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149448 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149452 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>>  =>  (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 149455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149459 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149465 */     GIR_RootConstrainSelectedInstOperands,
     /* 149466 */     // GIR_Coverage, 7225,
     /* 149466 */     GIR_EraseRootFromParent_Done,
     /* 149467 */   // Label 2637: @149467
     /* 149467 */   GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(149516), // Rule ID 7226 //
     /* 149472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149475 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149482 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 149485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149489 */     // MIs[0] Rn
     /* 149489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149493 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149497 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149501 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>>  =>  (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 149504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149508 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149514 */     GIR_RootConstrainSelectedInstOperands,
     /* 149515 */     // GIR_Coverage, 7226,
     /* 149515 */     GIR_EraseRootFromParent_Done,
     /* 149516 */   // Label 2638: @149516
     /* 149516 */   GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(149565), // Rule ID 7227 //
     /* 149521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149524 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149531 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 149534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149538 */     // MIs[0] Rn
     /* 149538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149542 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149546 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149550 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>>  =>  (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
     /* 149553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149563 */     GIR_RootConstrainSelectedInstOperands,
     /* 149564 */     // GIR_Coverage, 7227,
     /* 149564 */     GIR_EraseRootFromParent_Done,
     /* 149565 */   // Label 2639: @149565
     /* 149565 */   GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(149614), // Rule ID 7228 //
     /* 149570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149573 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149580 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149587 */     // MIs[0] Rn
     /* 149587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149591 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149599 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>>  =>  (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
     /* 149602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149606 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149608 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149612 */     GIR_RootConstrainSelectedInstOperands,
     /* 149613 */     // GIR_Coverage, 7228,
     /* 149613 */     GIR_EraseRootFromParent_Done,
     /* 149614 */   // Label 2640: @149614
     /* 149614 */   GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(149663), // Rule ID 7229 //
     /* 149619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149622 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149629 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 149632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149636 */     // MIs[0] Rn
     /* 149636 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149640 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149648 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>>  =>  (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
     /* 149651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149655 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149661 */     GIR_RootConstrainSelectedInstOperands,
     /* 149662 */     // GIR_Coverage, 7229,
     /* 149662 */     GIR_EraseRootFromParent_Done,
     /* 149663 */   // Label 2641: @149663
     /* 149663 */   GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(149712), // Rule ID 7230 //
     /* 149668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149671 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149678 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 149681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149685 */     // MIs[0] Rn
     /* 149685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149689 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149693 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149697 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>>  =>  (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 149700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149704 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149710 */     GIR_RootConstrainSelectedInstOperands,
     /* 149711 */     // GIR_Coverage, 7230,
     /* 149711 */     GIR_EraseRootFromParent_Done,
     /* 149712 */   // Label 2642: @149712
     /* 149712 */   GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(149761), // Rule ID 7231 //
     /* 149717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149720 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149727 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 149730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149734 */     // MIs[0] Rn
     /* 149734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149738 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149742 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149746 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>>  =>  (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 149749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149753 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149759 */     GIR_RootConstrainSelectedInstOperands,
     /* 149760 */     // GIR_Coverage, 7231,
     /* 149760 */     GIR_EraseRootFromParent_Done,
     /* 149761 */   // Label 2643: @149761
     /* 149761 */   GIM_Reject,
     /* 149762 */ // Label 2628: @149762
     /* 149762 */ GIM_Reject,
     /* 149763 */ // Label 2626: @149763
     /* 149763 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(149989),
     /* 149768 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 149771 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 149778 */   GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(149820), // Rule ID 2579 //
     /* 149783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149786 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 149789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149793 */     // MIs[0] Rn
     /* 149793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149797 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149801 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149805 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_monotonic>>  =>  (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
     /* 149808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149810 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149812 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149818 */     GIR_RootConstrainSelectedInstOperands,
     /* 149819 */     // GIR_Coverage, 2579,
     /* 149819 */     GIR_EraseRootFromParent_Done,
     /* 149820 */   // Label 2645: @149820
     /* 149820 */   GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(149862), // Rule ID 2580 //
     /* 149825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149828 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149835 */     // MIs[0] Rn
     /* 149835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149839 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149847 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acquire>>  =>  (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
     /* 149850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149854 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149860 */     GIR_RootConstrainSelectedInstOperands,
     /* 149861 */     // GIR_Coverage, 2580,
     /* 149861 */     GIR_EraseRootFromParent_Done,
     /* 149862 */   // Label 2646: @149862
     /* 149862 */   GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(149904), // Rule ID 2581 //
     /* 149867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149870 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 149873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149877 */     // MIs[0] Rn
     /* 149877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149881 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149889 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_release>>  =>  (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
     /* 149892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149896 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149902 */     GIR_RootConstrainSelectedInstOperands,
     /* 149903 */     // GIR_Coverage, 2581,
     /* 149903 */     GIR_EraseRootFromParent_Done,
     /* 149904 */   // Label 2647: @149904
     /* 149904 */   GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(149946), // Rule ID 2582 //
     /* 149909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149912 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 149915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149919 */     // MIs[0] Rn
     /* 149919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149923 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149927 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149931 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acq_rel>>  =>  (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 149934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149938 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149944 */     GIR_RootConstrainSelectedInstOperands,
     /* 149945 */     // GIR_Coverage, 2582,
     /* 149945 */     GIR_EraseRootFromParent_Done,
     /* 149946 */   // Label 2648: @149946
     /* 149946 */   GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(149988), // Rule ID 2583 //
     /* 149951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 149954 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 149957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149961 */     // MIs[0] Rn
     /* 149961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 149965 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 149969 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 149973 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_seq_cst>>  =>  (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 149973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 149976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 149980 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 149982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149986 */     GIR_RootConstrainSelectedInstOperands,
     /* 149987 */     // GIR_Coverage, 2583,
     /* 149987 */     GIR_EraseRootFromParent_Done,
     /* 149988 */   // Label 2649: @149988
     /* 149988 */   GIM_Reject,
     /* 149989 */ // Label 2644: @149989
     /* 149989 */ GIM_Reject,
     /* 149990 */ // Label 2627: @149990
     /* 149990 */ GIM_Reject,
     /* 149991 */ // Label 23: @149991
     /* 149991 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2652*/ GIMT_Encode4(151482),
     /* 150002 */ /*GILLT_s32*//*Label 2650*/ GIMT_Encode4(150010),
     /* 150006 */ /*GILLT_s64*//*Label 2651*/ GIMT_Encode4(151130),
     /* 150010 */ // Label 2650: @150010
     /* 150010 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(151129),
     /* 150015 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 150018 */   GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(150092), // Rule ID 7412 //
     /* 150023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150026 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150033 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 150036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150040 */     // MIs[0] Rn
     /* 150040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150044 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150048 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150052 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_monotonic>>  =>  (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150052 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150055 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150059 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150064 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150070 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150074 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
     /* 150079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150081 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150084 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150090 */     GIR_RootConstrainSelectedInstOperands,
     /* 150091 */     // GIR_Coverage, 7412,
     /* 150091 */     GIR_EraseRootFromParent_Done,
     /* 150092 */   // Label 2654: @150092
     /* 150092 */   GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(150166), // Rule ID 7413 //
     /* 150097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150100 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150107 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150114 */     // MIs[0] Rn
     /* 150114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150122 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150126 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acquire>>  =>  (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150126 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150129 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150133 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150138 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150144 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150148 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
     /* 150153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150155 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150158 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150164 */     GIR_RootConstrainSelectedInstOperands,
     /* 150165 */     // GIR_Coverage, 7413,
     /* 150165 */     GIR_EraseRootFromParent_Done,
     /* 150166 */   // Label 2655: @150166
     /* 150166 */   GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(150240), // Rule ID 7414 //
     /* 150171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150174 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150181 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 150184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150188 */     // MIs[0] Rn
     /* 150188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150192 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150196 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150200 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_release>>  =>  (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150200 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150203 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150207 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150212 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150218 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150222 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
     /* 150227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150229 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150232 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150238 */     GIR_RootConstrainSelectedInstOperands,
     /* 150239 */     // GIR_Coverage, 7414,
     /* 150239 */     GIR_EraseRootFromParent_Done,
     /* 150240 */   // Label 2656: @150240
     /* 150240 */   GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(150314), // Rule ID 7415 //
     /* 150245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150248 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150255 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 150258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150262 */     // MIs[0] Rn
     /* 150262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150266 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150274 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acq_rel>>  =>  (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150274 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150277 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150281 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150286 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150292 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150296 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 150301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150303 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150306 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150312 */     GIR_RootConstrainSelectedInstOperands,
     /* 150313 */     // GIR_Coverage, 7415,
     /* 150313 */     GIR_EraseRootFromParent_Done,
     /* 150314 */   // Label 2657: @150314
     /* 150314 */   GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(150388), // Rule ID 7416 //
     /* 150319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150322 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150329 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 150332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150336 */     // MIs[0] Rn
     /* 150336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150340 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150344 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150348 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_seq_cst>>  =>  (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150348 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150351 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150355 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150360 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150366 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150370 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 150375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150377 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150380 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150386 */     GIR_RootConstrainSelectedInstOperands,
     /* 150387 */     // GIR_Coverage, 7416,
     /* 150387 */     GIR_EraseRootFromParent_Done,
     /* 150388 */   // Label 2658: @150388
     /* 150388 */   GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(150462), // Rule ID 7417 //
     /* 150393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150396 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150403 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 150406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150410 */     // MIs[0] Rn
     /* 150410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150414 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150418 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150422 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_monotonic>>  =>  (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150422 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150425 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150429 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150434 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150440 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150444 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
     /* 150449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150451 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150454 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150460 */     GIR_RootConstrainSelectedInstOperands,
     /* 150461 */     // GIR_Coverage, 7417,
     /* 150461 */     GIR_EraseRootFromParent_Done,
     /* 150462 */   // Label 2659: @150462
     /* 150462 */   GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(150536), // Rule ID 7418 //
     /* 150467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150470 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150477 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150484 */     // MIs[0] Rn
     /* 150484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150488 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150496 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acquire>>  =>  (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150496 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150499 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150503 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150508 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150514 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150518 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
     /* 150523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150525 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150528 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150534 */     GIR_RootConstrainSelectedInstOperands,
     /* 150535 */     // GIR_Coverage, 7418,
     /* 150535 */     GIR_EraseRootFromParent_Done,
     /* 150536 */   // Label 2660: @150536
     /* 150536 */   GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(150610), // Rule ID 7419 //
     /* 150541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150544 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150551 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 150554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150558 */     // MIs[0] Rn
     /* 150558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150566 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150570 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_release>>  =>  (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150570 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150573 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150577 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150582 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150588 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150592 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
     /* 150597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150599 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150602 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150608 */     GIR_RootConstrainSelectedInstOperands,
     /* 150609 */     // GIR_Coverage, 7419,
     /* 150609 */     GIR_EraseRootFromParent_Done,
     /* 150610 */   // Label 2661: @150610
     /* 150610 */   GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(150684), // Rule ID 7420 //
     /* 150615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150618 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150625 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 150628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150632 */     // MIs[0] Rn
     /* 150632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150636 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150644 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acq_rel>>  =>  (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150644 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150647 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150651 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150656 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150662 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150666 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 150671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150676 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150682 */     GIR_RootConstrainSelectedInstOperands,
     /* 150683 */     // GIR_Coverage, 7420,
     /* 150683 */     GIR_EraseRootFromParent_Done,
     /* 150684 */   // Label 2662: @150684
     /* 150684 */   GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(150758), // Rule ID 7421 //
     /* 150689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150692 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150699 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 150702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150706 */     // MIs[0] Rn
     /* 150706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150710 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150718 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_seq_cst>>  =>  (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150718 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150721 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150725 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150730 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150736 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150740 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 150745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150747 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150750 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150756 */     GIR_RootConstrainSelectedInstOperands,
     /* 150757 */     // GIR_Coverage, 7421,
     /* 150757 */     GIR_EraseRootFromParent_Done,
     /* 150758 */   // Label 2663: @150758
     /* 150758 */   GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(150832), // Rule ID 7422 //
     /* 150763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150766 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150773 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 150776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150780 */     // MIs[0] Rn
     /* 150780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150784 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150792 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_monotonic>>  =>  (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150792 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150795 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150799 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150804 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150810 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150814 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
     /* 150819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150821 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150824 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150830 */     GIR_RootConstrainSelectedInstOperands,
     /* 150831 */     // GIR_Coverage, 7422,
     /* 150831 */     GIR_EraseRootFromParent_Done,
     /* 150832 */   // Label 2664: @150832
     /* 150832 */   GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(150906), // Rule ID 7423 //
     /* 150837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150840 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150847 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150854 */     // MIs[0] Rn
     /* 150854 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150858 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150862 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150866 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acquire>>  =>  (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150866 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150869 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150873 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150878 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150884 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150888 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
     /* 150893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150895 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150904 */     GIR_RootConstrainSelectedInstOperands,
     /* 150905 */     // GIR_Coverage, 7423,
     /* 150905 */     GIR_EraseRootFromParent_Done,
     /* 150906 */   // Label 2665: @150906
     /* 150906 */   GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(150980), // Rule ID 7424 //
     /* 150911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150914 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150921 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 150924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150928 */     // MIs[0] Rn
     /* 150928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150940 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_release>>  =>  (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 150940 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150943 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 150947 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150952 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 150958 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 150962 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
     /* 150967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 150969 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150972 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 150974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150978 */     GIR_RootConstrainSelectedInstOperands,
     /* 150979 */     // GIR_Coverage, 7424,
     /* 150979 */     GIR_EraseRootFromParent_Done,
     /* 150980 */   // Label 2666: @150980
     /* 150980 */   GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(151054), // Rule ID 7425 //
     /* 150985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 150988 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150995 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 150998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151002 */     // MIs[0] Rn
     /* 151002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151006 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151014 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acq_rel>>  =>  (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151014 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151017 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 151021 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151026 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151032 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151036 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 151041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151043 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151046 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151052 */     GIR_RootConstrainSelectedInstOperands,
     /* 151053 */     // GIR_Coverage, 7425,
     /* 151053 */     GIR_EraseRootFromParent_Done,
     /* 151054 */   // Label 2667: @151054
     /* 151054 */   GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(151128), // Rule ID 7426 //
     /* 151059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151062 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 151069 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 151072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151076 */     // MIs[0] Rn
     /* 151076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151080 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151088 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_seq_cst>>  =>  (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151088 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151091 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 151095 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151100 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151106 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151110 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 151115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151117 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151120 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151126 */     GIR_RootConstrainSelectedInstOperands,
     /* 151127 */     // GIR_Coverage, 7426,
     /* 151127 */     GIR_EraseRootFromParent_Done,
     /* 151128 */   // Label 2668: @151128
     /* 151128 */   GIM_Reject,
     /* 151129 */ // Label 2653: @151129
     /* 151129 */ GIM_Reject,
     /* 151130 */ // Label 2651: @151130
     /* 151130 */ GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(151481),
     /* 151135 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 151138 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 151145 */   GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(151212), // Rule ID 7407 //
     /* 151150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151153 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 151156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151160 */     // MIs[0] Rn
     /* 151160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151164 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151168 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151172 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_monotonic>>  =>  (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151172 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 151175 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 151179 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151184 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151190 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151194 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
     /* 151199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151201 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151204 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151210 */     GIR_RootConstrainSelectedInstOperands,
     /* 151211 */     // GIR_Coverage, 7407,
     /* 151211 */     GIR_EraseRootFromParent_Done,
     /* 151212 */   // Label 2670: @151212
     /* 151212 */   GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(151279), // Rule ID 7408 //
     /* 151217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151220 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 151223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151227 */     // MIs[0] Rn
     /* 151227 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151231 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151239 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acquire>>  =>  (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151239 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 151242 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 151246 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151251 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151257 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151261 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
     /* 151266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151268 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151271 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151277 */     GIR_RootConstrainSelectedInstOperands,
     /* 151278 */     // GIR_Coverage, 7408,
     /* 151278 */     GIR_EraseRootFromParent_Done,
     /* 151279 */   // Label 2671: @151279
     /* 151279 */   GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(151346), // Rule ID 7409 //
     /* 151284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151287 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 151290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151294 */     // MIs[0] Rn
     /* 151294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151298 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151306 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_release>>  =>  (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151306 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 151309 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 151313 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151318 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151324 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151328 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
     /* 151333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151335 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151338 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151344 */     GIR_RootConstrainSelectedInstOperands,
     /* 151345 */     // GIR_Coverage, 7409,
     /* 151345 */     GIR_EraseRootFromParent_Done,
     /* 151346 */   // Label 2672: @151346
     /* 151346 */   GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(151413), // Rule ID 7410 //
     /* 151351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151354 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 151357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151361 */     // MIs[0] Rn
     /* 151361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151373 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acq_rel>>  =>  (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151373 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 151376 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 151380 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151385 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151391 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 151400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151402 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151405 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151411 */     GIR_RootConstrainSelectedInstOperands,
     /* 151412 */     // GIR_Coverage, 7410,
     /* 151412 */     GIR_EraseRootFromParent_Done,
     /* 151413 */   // Label 2673: @151413
     /* 151413 */   GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(151480), // Rule ID 7411 //
     /* 151418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151421 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 151424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151428 */     // MIs[0] Rn
     /* 151428 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151432 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151436 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 151440 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_seq_cst>>  =>  (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 151443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 151447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151452 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151458 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 151467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151469 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151472 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151478 */     GIR_RootConstrainSelectedInstOperands,
     /* 151479 */     // GIR_Coverage, 7411,
     /* 151479 */     GIR_EraseRootFromParent_Done,
     /* 151480 */   // Label 2674: @151480
     /* 151480 */   GIM_Reject,
     /* 151481 */ // Label 2669: @151481
     /* 151481 */ GIM_Reject,
     /* 151482 */ // Label 2652: @151482
     /* 151482 */ GIM_Reject,
     /* 151483 */ // Label 24: @151483
     /* 151483 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2677*/ GIMT_Encode4(152974),
     /* 151494 */ /*GILLT_s32*//*Label 2675*/ GIMT_Encode4(151502),
     /* 151498 */ /*GILLT_s64*//*Label 2676*/ GIMT_Encode4(152622),
     /* 151502 */ // Label 2675: @151502
     /* 151502 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(152621),
     /* 151507 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 151510 */   GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(151584), // Rule ID 7432 //
     /* 151515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151518 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151525 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 151528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151532 */     // MIs[0] Rn
     /* 151532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151536 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151544 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>>  =>  (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151544 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151547 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151551 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151556 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151562 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRW),
     /* 151571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151573 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151576 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151582 */     GIR_RootConstrainSelectedInstOperands,
     /* 151583 */     // GIR_Coverage, 7432,
     /* 151583 */     GIR_EraseRootFromParent_Done,
     /* 151584 */   // Label 2679: @151584
     /* 151584 */   GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(151658), // Rule ID 7433 //
     /* 151589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151592 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151599 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 151602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151606 */     // MIs[0] Rn
     /* 151606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151610 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151618 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>>  =>  (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151618 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151621 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151625 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151630 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151636 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151640 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAW),
     /* 151645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151647 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151650 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151656 */     GIR_RootConstrainSelectedInstOperands,
     /* 151657 */     // GIR_Coverage, 7433,
     /* 151657 */     GIR_EraseRootFromParent_Done,
     /* 151658 */   // Label 2680: @151658
     /* 151658 */   GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(151732), // Rule ID 7434 //
     /* 151663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151666 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151673 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 151676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151680 */     // MIs[0] Rn
     /* 151680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151684 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151692 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>>  =>  (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151692 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151695 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151699 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151704 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151710 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151714 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLW),
     /* 151719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151721 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151724 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151730 */     GIR_RootConstrainSelectedInstOperands,
     /* 151731 */     // GIR_Coverage, 7434,
     /* 151731 */     GIR_EraseRootFromParent_Done,
     /* 151732 */   // Label 2681: @151732
     /* 151732 */   GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(151806), // Rule ID 7435 //
     /* 151737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151740 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151747 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 151750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151754 */     // MIs[0] Rn
     /* 151754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151758 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151766 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>>  =>  (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151766 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151769 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151773 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151778 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151784 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151788 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
     /* 151793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151795 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151804 */     GIR_RootConstrainSelectedInstOperands,
     /* 151805 */     // GIR_Coverage, 7435,
     /* 151805 */     GIR_EraseRootFromParent_Done,
     /* 151806 */   // Label 2682: @151806
     /* 151806 */   GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(151880), // Rule ID 7436 //
     /* 151811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151814 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151821 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 151824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151828 */     // MIs[0] Rn
     /* 151828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151832 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151836 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151840 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>>  =>  (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151840 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151843 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151847 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151852 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151858 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151862 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
     /* 151867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151869 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151872 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151878 */     GIR_RootConstrainSelectedInstOperands,
     /* 151879 */     // GIR_Coverage, 7436,
     /* 151879 */     GIR_EraseRootFromParent_Done,
     /* 151880 */   // Label 2683: @151880
     /* 151880 */   GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(151954), // Rule ID 7437 //
     /* 151885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151888 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 151895 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 151898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151902 */     // MIs[0] Rn
     /* 151902 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151906 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151910 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151914 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>>  =>  (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151926 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 151932 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 151936 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRH),
     /* 151941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 151943 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151952 */     GIR_RootConstrainSelectedInstOperands,
     /* 151953 */     // GIR_Coverage, 7437,
     /* 151953 */     GIR_EraseRootFromParent_Done,
     /* 151954 */   // Label 2684: @151954
     /* 151954 */   GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(152028), // Rule ID 7438 //
     /* 151959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 151962 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 151969 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 151972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151976 */     // MIs[0] Rn
     /* 151976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151980 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151988 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>>  =>  (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 151988 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151991 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 151995 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152000 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152006 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152010 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAH),
     /* 152015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152017 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152020 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152026 */     GIR_RootConstrainSelectedInstOperands,
     /* 152027 */     // GIR_Coverage, 7438,
     /* 152027 */     GIR_EraseRootFromParent_Done,
     /* 152028 */   // Label 2685: @152028
     /* 152028 */   GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(152102), // Rule ID 7439 //
     /* 152033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152036 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 152043 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 152046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152050 */     // MIs[0] Rn
     /* 152050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152054 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152062 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>>  =>  (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152062 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152065 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152069 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152074 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152080 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152084 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLH),
     /* 152089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152091 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152094 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152100 */     GIR_RootConstrainSelectedInstOperands,
     /* 152101 */     // GIR_Coverage, 7439,
     /* 152101 */     GIR_EraseRootFromParent_Done,
     /* 152102 */   // Label 2686: @152102
     /* 152102 */   GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(152176), // Rule ID 7440 //
     /* 152107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152110 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 152117 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 152120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152124 */     // MIs[0] Rn
     /* 152124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152128 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152136 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>>  =>  (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152136 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152139 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152143 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152148 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152154 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152158 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
     /* 152163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152165 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152168 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152174 */     GIR_RootConstrainSelectedInstOperands,
     /* 152175 */     // GIR_Coverage, 7440,
     /* 152175 */     GIR_EraseRootFromParent_Done,
     /* 152176 */   // Label 2687: @152176
     /* 152176 */   GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(152250), // Rule ID 7441 //
     /* 152181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152184 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 152191 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 152194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152198 */     // MIs[0] Rn
     /* 152198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152206 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152210 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>>  =>  (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152210 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152213 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152217 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152222 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152228 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152232 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
     /* 152237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152239 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152248 */     GIR_RootConstrainSelectedInstOperands,
     /* 152249 */     // GIR_Coverage, 7441,
     /* 152249 */     GIR_EraseRootFromParent_Done,
     /* 152250 */   // Label 2688: @152250
     /* 152250 */   GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(152324), // Rule ID 7442 //
     /* 152255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152258 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 152265 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 152268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152272 */     // MIs[0] Rn
     /* 152272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152276 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152284 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>>  =>  (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152284 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152287 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152291 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152296 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152302 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152306 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRB),
     /* 152311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152313 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152316 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152322 */     GIR_RootConstrainSelectedInstOperands,
     /* 152323 */     // GIR_Coverage, 7442,
     /* 152323 */     GIR_EraseRootFromParent_Done,
     /* 152324 */   // Label 2689: @152324
     /* 152324 */   GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(152398), // Rule ID 7443 //
     /* 152329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152332 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 152339 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 152342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152346 */     // MIs[0] Rn
     /* 152346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152350 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152358 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>>  =>  (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152358 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152361 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152365 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152370 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152376 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152380 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAB),
     /* 152385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152387 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152390 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152396 */     GIR_RootConstrainSelectedInstOperands,
     /* 152397 */     // GIR_Coverage, 7443,
     /* 152397 */     GIR_EraseRootFromParent_Done,
     /* 152398 */   // Label 2690: @152398
     /* 152398 */   GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(152472), // Rule ID 7444 //
     /* 152403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152406 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 152413 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 152416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152420 */     // MIs[0] Rn
     /* 152420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152424 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152428 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152432 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>>  =>  (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152432 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152435 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152439 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152444 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152450 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152454 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLB),
     /* 152459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152461 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152464 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152470 */     GIR_RootConstrainSelectedInstOperands,
     /* 152471 */     // GIR_Coverage, 7444,
     /* 152471 */     GIR_EraseRootFromParent_Done,
     /* 152472 */   // Label 2691: @152472
     /* 152472 */   GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(152546), // Rule ID 7445 //
     /* 152477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152480 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 152487 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 152490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152494 */     // MIs[0] Rn
     /* 152494 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152498 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152506 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>>  =>  (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152506 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152509 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152518 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152524 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152528 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
     /* 152533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152535 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152538 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152544 */     GIR_RootConstrainSelectedInstOperands,
     /* 152545 */     // GIR_Coverage, 7445,
     /* 152545 */     GIR_EraseRootFromParent_Done,
     /* 152546 */   // Label 2692: @152546
     /* 152546 */   GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(152620), // Rule ID 7446 //
     /* 152551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152554 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 152561 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 152564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152568 */     // MIs[0] Rn
     /* 152568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 152580 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>>  =>  (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152580 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 152583 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 152587 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152592 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152598 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152602 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
     /* 152607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152609 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152612 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152618 */     GIR_RootConstrainSelectedInstOperands,
     /* 152619 */     // GIR_Coverage, 7446,
     /* 152619 */     GIR_EraseRootFromParent_Done,
     /* 152620 */   // Label 2693: @152620
     /* 152620 */   GIM_Reject,
     /* 152621 */ // Label 2678: @152621
     /* 152621 */ GIM_Reject,
     /* 152622 */ // Label 2676: @152622
     /* 152622 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(152973),
     /* 152627 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 152630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 152637 */   GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(152704), // Rule ID 7427 //
     /* 152642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152645 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 152648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152652 */     // MIs[0] Rn
     /* 152652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152656 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152664 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_monotonic>>  =>  (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152664 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 152667 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 152671 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152676 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152682 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152686 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRX),
     /* 152691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152693 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152696 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152702 */     GIR_RootConstrainSelectedInstOperands,
     /* 152703 */     // GIR_Coverage, 7427,
     /* 152703 */     GIR_EraseRootFromParent_Done,
     /* 152704 */   // Label 2695: @152704
     /* 152704 */   GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(152771), // Rule ID 7428 //
     /* 152709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152712 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 152715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152719 */     // MIs[0] Rn
     /* 152719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152723 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152731 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acquire>>  =>  (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152731 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 152734 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 152738 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152743 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152749 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152753 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAX),
     /* 152758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152760 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152763 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152769 */     GIR_RootConstrainSelectedInstOperands,
     /* 152770 */     // GIR_Coverage, 7428,
     /* 152770 */     GIR_EraseRootFromParent_Done,
     /* 152771 */   // Label 2696: @152771
     /* 152771 */   GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(152838), // Rule ID 7429 //
     /* 152776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152779 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 152782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152786 */     // MIs[0] Rn
     /* 152786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152790 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152794 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152798 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_release>>  =>  (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152798 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 152801 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 152805 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152810 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152816 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152820 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLX),
     /* 152825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152827 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152830 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152836 */     GIR_RootConstrainSelectedInstOperands,
     /* 152837 */     // GIR_Coverage, 7429,
     /* 152837 */     GIR_EraseRootFromParent_Done,
     /* 152838 */   // Label 2697: @152838
     /* 152838 */   GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(152905), // Rule ID 7430 //
     /* 152843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152846 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 152849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152853 */     // MIs[0] Rn
     /* 152853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152865 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acq_rel>>  =>  (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152865 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 152868 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 152872 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152877 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152883 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152887 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
     /* 152892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152897 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152903 */     GIR_RootConstrainSelectedInstOperands,
     /* 152904 */     // GIR_Coverage, 7430,
     /* 152904 */     GIR_EraseRootFromParent_Done,
     /* 152905 */   // Label 2698: @152905
     /* 152905 */   GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(152972), // Rule ID 7431 //
     /* 152910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 152913 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 152916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152920 */     // MIs[0] Rn
     /* 152920 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 152924 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 152928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 152932 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_seq_cst>>  =>  (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 152932 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 152935 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 152939 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152944 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 152950 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 152954 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 152956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
     /* 152959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 152961 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152964 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 152966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152970 */     GIR_RootConstrainSelectedInstOperands,
     /* 152971 */     // GIR_Coverage, 7431,
     /* 152971 */     GIR_EraseRootFromParent_Done,
     /* 152972 */   // Label 2699: @152972
     /* 152972 */   GIM_Reject,
     /* 152973 */ // Label 2694: @152973
     /* 152973 */ GIM_Reject,
     /* 152974 */ // Label 2677: @152974
     /* 152974 */ GIM_Reject,
     /* 152975 */ // Label 25: @152975
     /* 152975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2702*/ GIMT_Encode4(153966),
     /* 152986 */ /*GILLT_s32*//*Label 2700*/ GIMT_Encode4(152994),
     /* 152990 */ /*GILLT_s64*//*Label 2701*/ GIMT_Encode4(153739),
     /* 152994 */ // Label 2700: @152994
     /* 152994 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(153738),
     /* 152999 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 153002 */   GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(153051), // Rule ID 7237 //
     /* 153007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153010 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 153017 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 153020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153024 */     // MIs[0] Rn
     /* 153024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153028 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153036 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>>  =>  (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETW),
     /* 153039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153041 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153049 */     GIR_RootConstrainSelectedInstOperands,
     /* 153050 */     // GIR_Coverage, 7237,
     /* 153050 */     GIR_EraseRootFromParent_Done,
     /* 153051 */   // Label 2704: @153051
     /* 153051 */   GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(153100), // Rule ID 7238 //
     /* 153056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153059 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 153066 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 153069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153073 */     // MIs[0] Rn
     /* 153073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153077 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153081 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153085 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>>  =>  (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAW),
     /* 153088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153090 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153092 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153098 */     GIR_RootConstrainSelectedInstOperands,
     /* 153099 */     // GIR_Coverage, 7238,
     /* 153099 */     GIR_EraseRootFromParent_Done,
     /* 153100 */   // Label 2705: @153100
     /* 153100 */   GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(153149), // Rule ID 7239 //
     /* 153105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153108 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 153115 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 153118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153122 */     // MIs[0] Rn
     /* 153122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153126 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153134 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>>  =>  (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLW),
     /* 153137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153139 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153141 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153147 */     GIR_RootConstrainSelectedInstOperands,
     /* 153148 */     // GIR_Coverage, 7239,
     /* 153148 */     GIR_EraseRootFromParent_Done,
     /* 153149 */   // Label 2706: @153149
     /* 153149 */   GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(153198), // Rule ID 7240 //
     /* 153154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153157 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 153164 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 153167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153171 */     // MIs[0] Rn
     /* 153171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153175 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153179 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153183 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>>  =>  (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
     /* 153186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153190 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153196 */     GIR_RootConstrainSelectedInstOperands,
     /* 153197 */     // GIR_Coverage, 7240,
     /* 153197 */     GIR_EraseRootFromParent_Done,
     /* 153198 */   // Label 2707: @153198
     /* 153198 */   GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(153247), // Rule ID 7241 //
     /* 153203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153206 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 153213 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 153216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153220 */     // MIs[0] Rn
     /* 153220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153224 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153232 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>>  =>  (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
     /* 153235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153239 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153245 */     GIR_RootConstrainSelectedInstOperands,
     /* 153246 */     // GIR_Coverage, 7241,
     /* 153246 */     GIR_EraseRootFromParent_Done,
     /* 153247 */   // Label 2708: @153247
     /* 153247 */   GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(153296), // Rule ID 7242 //
     /* 153252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153255 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153262 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 153265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153269 */     // MIs[0] Rn
     /* 153269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153273 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153277 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153281 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>>  =>  (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETH),
     /* 153284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153286 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153288 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153294 */     GIR_RootConstrainSelectedInstOperands,
     /* 153295 */     // GIR_Coverage, 7242,
     /* 153295 */     GIR_EraseRootFromParent_Done,
     /* 153296 */   // Label 2709: @153296
     /* 153296 */   GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(153345), // Rule ID 7243 //
     /* 153301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153304 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153311 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 153314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153318 */     // MIs[0] Rn
     /* 153318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153326 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153330 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>>  =>  (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAH),
     /* 153333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153337 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153343 */     GIR_RootConstrainSelectedInstOperands,
     /* 153344 */     // GIR_Coverage, 7243,
     /* 153344 */     GIR_EraseRootFromParent_Done,
     /* 153345 */   // Label 2710: @153345
     /* 153345 */   GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(153394), // Rule ID 7244 //
     /* 153350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153353 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153360 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 153363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153367 */     // MIs[0] Rn
     /* 153367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153371 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153379 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>>  =>  (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLH),
     /* 153382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153386 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153392 */     GIR_RootConstrainSelectedInstOperands,
     /* 153393 */     // GIR_Coverage, 7244,
     /* 153393 */     GIR_EraseRootFromParent_Done,
     /* 153394 */   // Label 2711: @153394
     /* 153394 */   GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(153443), // Rule ID 7245 //
     /* 153399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153402 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153409 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 153412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153416 */     // MIs[0] Rn
     /* 153416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153428 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>>  =>  (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
     /* 153431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153433 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153435 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153441 */     GIR_RootConstrainSelectedInstOperands,
     /* 153442 */     // GIR_Coverage, 7245,
     /* 153442 */     GIR_EraseRootFromParent_Done,
     /* 153443 */   // Label 2712: @153443
     /* 153443 */   GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(153492), // Rule ID 7246 //
     /* 153448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153451 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153458 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 153461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153465 */     // MIs[0] Rn
     /* 153465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153469 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153477 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>>  =>  (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
     /* 153480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153482 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153484 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153490 */     GIR_RootConstrainSelectedInstOperands,
     /* 153491 */     // GIR_Coverage, 7246,
     /* 153491 */     GIR_EraseRootFromParent_Done,
     /* 153492 */   // Label 2713: @153492
     /* 153492 */   GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(153541), // Rule ID 7247 //
     /* 153497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153500 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 153507 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 153510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153514 */     // MIs[0] Rn
     /* 153514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153518 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153526 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>>  =>  (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETB),
     /* 153529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153533 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153539 */     GIR_RootConstrainSelectedInstOperands,
     /* 153540 */     // GIR_Coverage, 7247,
     /* 153540 */     GIR_EraseRootFromParent_Done,
     /* 153541 */   // Label 2714: @153541
     /* 153541 */   GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(153590), // Rule ID 7248 //
     /* 153546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153549 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 153556 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 153559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153563 */     // MIs[0] Rn
     /* 153563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153571 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153575 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>>  =>  (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAB),
     /* 153578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153580 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153582 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153588 */     GIR_RootConstrainSelectedInstOperands,
     /* 153589 */     // GIR_Coverage, 7248,
     /* 153589 */     GIR_EraseRootFromParent_Done,
     /* 153590 */   // Label 2715: @153590
     /* 153590 */   GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(153639), // Rule ID 7249 //
     /* 153595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153598 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 153605 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 153608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153612 */     // MIs[0] Rn
     /* 153612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153616 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153624 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>>  =>  (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLB),
     /* 153627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153631 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153637 */     GIR_RootConstrainSelectedInstOperands,
     /* 153638 */     // GIR_Coverage, 7249,
     /* 153638 */     GIR_EraseRootFromParent_Done,
     /* 153639 */   // Label 2716: @153639
     /* 153639 */   GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(153688), // Rule ID 7250 //
     /* 153644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153647 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 153654 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 153657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153661 */     // MIs[0] Rn
     /* 153661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153665 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153673 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>>  =>  (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
     /* 153676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153680 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153686 */     GIR_RootConstrainSelectedInstOperands,
     /* 153687 */     // GIR_Coverage, 7250,
     /* 153687 */     GIR_EraseRootFromParent_Done,
     /* 153688 */   // Label 2717: @153688
     /* 153688 */   GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(153737), // Rule ID 7251 //
     /* 153693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153696 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 153703 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 153706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153710 */     // MIs[0] Rn
     /* 153710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153714 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 153722 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>>  =>  (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
     /* 153725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153729 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153735 */     GIR_RootConstrainSelectedInstOperands,
     /* 153736 */     // GIR_Coverage, 7251,
     /* 153736 */     GIR_EraseRootFromParent_Done,
     /* 153737 */   // Label 2718: @153737
     /* 153737 */   GIM_Reject,
     /* 153738 */ // Label 2703: @153738
     /* 153738 */ GIM_Reject,
     /* 153739 */ // Label 2701: @153739
     /* 153739 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(153965),
     /* 153744 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 153747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 153754 */   GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(153796), // Rule ID 7232 //
     /* 153759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153762 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 153765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153769 */     // MIs[0] Rn
     /* 153769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153773 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153781 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_monotonic>>  =>  (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETX),
     /* 153784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153788 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153794 */     GIR_RootConstrainSelectedInstOperands,
     /* 153795 */     // GIR_Coverage, 7232,
     /* 153795 */     GIR_EraseRootFromParent_Done,
     /* 153796 */   // Label 2720: @153796
     /* 153796 */   GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(153838), // Rule ID 7233 //
     /* 153801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153804 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 153807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153811 */     // MIs[0] Rn
     /* 153811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153823 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acquire>>  =>  (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAX),
     /* 153826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153830 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153836 */     GIR_RootConstrainSelectedInstOperands,
     /* 153837 */     // GIR_Coverage, 7233,
     /* 153837 */     GIR_EraseRootFromParent_Done,
     /* 153838 */   // Label 2721: @153838
     /* 153838 */   GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(153880), // Rule ID 7234 //
     /* 153843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153846 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 153849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153853 */     // MIs[0] Rn
     /* 153853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153865 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_release>>  =>  (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLX),
     /* 153868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153872 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153878 */     GIR_RootConstrainSelectedInstOperands,
     /* 153879 */     // GIR_Coverage, 7234,
     /* 153879 */     GIR_EraseRootFromParent_Done,
     /* 153880 */   // Label 2722: @153880
     /* 153880 */   GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(153922), // Rule ID 7235 //
     /* 153885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153888 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 153891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153895 */     // MIs[0] Rn
     /* 153895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153899 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153907 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acq_rel>>  =>  (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
     /* 153910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153914 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153920 */     GIR_RootConstrainSelectedInstOperands,
     /* 153921 */     // GIR_Coverage, 7235,
     /* 153921 */     GIR_EraseRootFromParent_Done,
     /* 153922 */   // Label 2723: @153922
     /* 153922 */   GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(153964), // Rule ID 7236 //
     /* 153927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 153930 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 153933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153937 */     // MIs[0] Rn
     /* 153937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153941 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153945 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 153949 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_seq_cst>>  =>  (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 153949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
     /* 153952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 153954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 153956 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153962 */     GIR_RootConstrainSelectedInstOperands,
     /* 153963 */     // GIR_Coverage, 7236,
     /* 153963 */     GIR_EraseRootFromParent_Done,
     /* 153964 */   // Label 2724: @153964
     /* 153964 */   GIM_Reject,
     /* 153965 */ // Label 2719: @153965
     /* 153965 */ GIM_Reject,
     /* 153966 */ // Label 2702: @153966
     /* 153966 */ GIM_Reject,
     /* 153967 */ // Label 26: @153967
     /* 153967 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2727*/ GIMT_Encode4(154958),
     /* 153978 */ /*GILLT_s32*//*Label 2725*/ GIMT_Encode4(153986),
     /* 153982 */ /*GILLT_s64*//*Label 2726*/ GIMT_Encode4(154731),
     /* 153986 */ // Label 2725: @153986
     /* 153986 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(154730),
     /* 153991 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 153994 */   GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(154043), // Rule ID 7257 //
     /* 153999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154002 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 154009 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 154012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154016 */     // MIs[0] Rn
     /* 154016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154020 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154028 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>>  =>  (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORW),
     /* 154031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154035 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154041 */     GIR_RootConstrainSelectedInstOperands,
     /* 154042 */     // GIR_Coverage, 7257,
     /* 154042 */     GIR_EraseRootFromParent_Done,
     /* 154043 */   // Label 2729: @154043
     /* 154043 */   GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(154092), // Rule ID 7258 //
     /* 154048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154051 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 154058 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 154061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154065 */     // MIs[0] Rn
     /* 154065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154069 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154077 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>>  =>  (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAW),
     /* 154080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154082 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154084 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154090 */     GIR_RootConstrainSelectedInstOperands,
     /* 154091 */     // GIR_Coverage, 7258,
     /* 154091 */     GIR_EraseRootFromParent_Done,
     /* 154092 */   // Label 2730: @154092
     /* 154092 */   GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(154141), // Rule ID 7259 //
     /* 154097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154100 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 154107 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 154110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154114 */     // MIs[0] Rn
     /* 154114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154122 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154126 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>>  =>  (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLW),
     /* 154129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154131 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154133 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154139 */     GIR_RootConstrainSelectedInstOperands,
     /* 154140 */     // GIR_Coverage, 7259,
     /* 154140 */     GIR_EraseRootFromParent_Done,
     /* 154141 */   // Label 2731: @154141
     /* 154141 */   GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(154190), // Rule ID 7260 //
     /* 154146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154149 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 154156 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 154159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154163 */     // MIs[0] Rn
     /* 154163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154167 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154175 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>>  =>  (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
     /* 154178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154182 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154188 */     GIR_RootConstrainSelectedInstOperands,
     /* 154189 */     // GIR_Coverage, 7260,
     /* 154189 */     GIR_EraseRootFromParent_Done,
     /* 154190 */   // Label 2732: @154190
     /* 154190 */   GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(154239), // Rule ID 7261 //
     /* 154195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154198 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 154205 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 154208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154212 */     // MIs[0] Rn
     /* 154212 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154216 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154224 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>>  =>  (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
     /* 154227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154231 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154237 */     GIR_RootConstrainSelectedInstOperands,
     /* 154238 */     // GIR_Coverage, 7261,
     /* 154238 */     GIR_EraseRootFromParent_Done,
     /* 154239 */   // Label 2733: @154239
     /* 154239 */   GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(154288), // Rule ID 7262 //
     /* 154244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154247 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154254 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 154257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154261 */     // MIs[0] Rn
     /* 154261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154265 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154273 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>>  =>  (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORH),
     /* 154276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154280 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154286 */     GIR_RootConstrainSelectedInstOperands,
     /* 154287 */     // GIR_Coverage, 7262,
     /* 154287 */     GIR_EraseRootFromParent_Done,
     /* 154288 */   // Label 2734: @154288
     /* 154288 */   GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(154337), // Rule ID 7263 //
     /* 154293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154296 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154303 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 154306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154310 */     // MIs[0] Rn
     /* 154310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154314 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154318 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154322 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>>  =>  (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAH),
     /* 154325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154329 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154335 */     GIR_RootConstrainSelectedInstOperands,
     /* 154336 */     // GIR_Coverage, 7263,
     /* 154336 */     GIR_EraseRootFromParent_Done,
     /* 154337 */   // Label 2735: @154337
     /* 154337 */   GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(154386), // Rule ID 7264 //
     /* 154342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154345 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154352 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 154355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154359 */     // MIs[0] Rn
     /* 154359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154363 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154371 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>>  =>  (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLH),
     /* 154374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154384 */     GIR_RootConstrainSelectedInstOperands,
     /* 154385 */     // GIR_Coverage, 7264,
     /* 154385 */     GIR_EraseRootFromParent_Done,
     /* 154386 */   // Label 2736: @154386
     /* 154386 */   GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(154435), // Rule ID 7265 //
     /* 154391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154394 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154401 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 154404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154408 */     // MIs[0] Rn
     /* 154408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154412 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154416 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154420 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>>  =>  (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
     /* 154423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154425 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154427 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154433 */     GIR_RootConstrainSelectedInstOperands,
     /* 154434 */     // GIR_Coverage, 7265,
     /* 154434 */     GIR_EraseRootFromParent_Done,
     /* 154435 */   // Label 2737: @154435
     /* 154435 */   GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(154484), // Rule ID 7266 //
     /* 154440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154443 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154450 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 154453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154457 */     // MIs[0] Rn
     /* 154457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154461 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154469 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>>  =>  (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
     /* 154472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154476 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154482 */     GIR_RootConstrainSelectedInstOperands,
     /* 154483 */     // GIR_Coverage, 7266,
     /* 154483 */     GIR_EraseRootFromParent_Done,
     /* 154484 */   // Label 2738: @154484
     /* 154484 */   GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(154533), // Rule ID 7267 //
     /* 154489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154492 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 154499 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 154502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154506 */     // MIs[0] Rn
     /* 154506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154510 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154514 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154518 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>>  =>  (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORB),
     /* 154521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154523 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154525 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154531 */     GIR_RootConstrainSelectedInstOperands,
     /* 154532 */     // GIR_Coverage, 7267,
     /* 154532 */     GIR_EraseRootFromParent_Done,
     /* 154533 */   // Label 2739: @154533
     /* 154533 */   GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(154582), // Rule ID 7268 //
     /* 154538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154541 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 154548 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 154551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154555 */     // MIs[0] Rn
     /* 154555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154559 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154563 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154567 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>>  =>  (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAB),
     /* 154570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154574 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154576 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154580 */     GIR_RootConstrainSelectedInstOperands,
     /* 154581 */     // GIR_Coverage, 7268,
     /* 154581 */     GIR_EraseRootFromParent_Done,
     /* 154582 */   // Label 2740: @154582
     /* 154582 */   GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(154631), // Rule ID 7269 //
     /* 154587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154590 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 154597 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 154600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154604 */     // MIs[0] Rn
     /* 154604 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154608 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154612 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154616 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>>  =>  (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLB),
     /* 154619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154621 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154623 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154629 */     GIR_RootConstrainSelectedInstOperands,
     /* 154630 */     // GIR_Coverage, 7269,
     /* 154630 */     GIR_EraseRootFromParent_Done,
     /* 154631 */   // Label 2741: @154631
     /* 154631 */   GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(154680), // Rule ID 7270 //
     /* 154636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154639 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 154646 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 154649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154653 */     // MIs[0] Rn
     /* 154653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154657 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154661 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154665 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>>  =>  (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
     /* 154668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154672 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154678 */     GIR_RootConstrainSelectedInstOperands,
     /* 154679 */     // GIR_Coverage, 7270,
     /* 154679 */     GIR_EraseRootFromParent_Done,
     /* 154680 */   // Label 2742: @154680
     /* 154680 */   GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(154729), // Rule ID 7271 //
     /* 154685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154688 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 154695 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 154698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154702 */     // MIs[0] Rn
     /* 154702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154706 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154710 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 154714 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>>  =>  (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
     /* 154717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154721 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154727 */     GIR_RootConstrainSelectedInstOperands,
     /* 154728 */     // GIR_Coverage, 7271,
     /* 154728 */     GIR_EraseRootFromParent_Done,
     /* 154729 */   // Label 2743: @154729
     /* 154729 */   GIM_Reject,
     /* 154730 */ // Label 2728: @154730
     /* 154730 */ GIM_Reject,
     /* 154731 */ // Label 2726: @154731
     /* 154731 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(154957),
     /* 154736 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 154739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 154746 */   GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(154788), // Rule ID 7252 //
     /* 154751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154754 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 154757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154761 */     // MIs[0] Rn
     /* 154761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154773 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_monotonic>>  =>  (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORX),
     /* 154776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154778 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154780 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154786 */     GIR_RootConstrainSelectedInstOperands,
     /* 154787 */     // GIR_Coverage, 7252,
     /* 154787 */     GIR_EraseRootFromParent_Done,
     /* 154788 */   // Label 2745: @154788
     /* 154788 */   GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(154830), // Rule ID 7253 //
     /* 154793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154796 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 154799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154803 */     // MIs[0] Rn
     /* 154803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154807 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154811 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154815 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acquire>>  =>  (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAX),
     /* 154818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154822 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154828 */     GIR_RootConstrainSelectedInstOperands,
     /* 154829 */     // GIR_Coverage, 7253,
     /* 154829 */     GIR_EraseRootFromParent_Done,
     /* 154830 */   // Label 2746: @154830
     /* 154830 */   GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(154872), // Rule ID 7254 //
     /* 154835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154838 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 154841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154845 */     // MIs[0] Rn
     /* 154845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154849 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154853 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154857 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_release>>  =>  (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLX),
     /* 154860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154862 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154864 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154870 */     GIR_RootConstrainSelectedInstOperands,
     /* 154871 */     // GIR_Coverage, 7254,
     /* 154871 */     GIR_EraseRootFromParent_Done,
     /* 154872 */   // Label 2747: @154872
     /* 154872 */   GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(154914), // Rule ID 7255 //
     /* 154877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154880 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 154883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154887 */     // MIs[0] Rn
     /* 154887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154891 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154899 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acq_rel>>  =>  (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
     /* 154902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154906 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154912 */     GIR_RootConstrainSelectedInstOperands,
     /* 154913 */     // GIR_Coverage, 7255,
     /* 154913 */     GIR_EraseRootFromParent_Done,
     /* 154914 */   // Label 2748: @154914
     /* 154914 */   GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(154956), // Rule ID 7256 //
     /* 154919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154922 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 154925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154929 */     // MIs[0] Rn
     /* 154929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 154933 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 154937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 154941 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_seq_cst>>  =>  (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 154941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
     /* 154944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 154946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 154948 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 154950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 154954 */     GIR_RootConstrainSelectedInstOperands,
     /* 154955 */     // GIR_Coverage, 7256,
     /* 154955 */     GIR_EraseRootFromParent_Done,
     /* 154956 */   // Label 2749: @154956
     /* 154956 */   GIM_Reject,
     /* 154957 */ // Label 2744: @154957
     /* 154957 */ GIM_Reject,
     /* 154958 */ // Label 2727: @154958
     /* 154958 */ GIM_Reject,
     /* 154959 */ // Label 27: @154959
     /* 154959 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2752*/ GIMT_Encode4(155950),
     /* 154970 */ /*GILLT_s32*//*Label 2750*/ GIMT_Encode4(154978),
     /* 154974 */ /*GILLT_s64*//*Label 2751*/ GIMT_Encode4(155723),
     /* 154978 */ // Label 2750: @154978
     /* 154978 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(155722),
     /* 154983 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 154986 */   GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(155035), // Rule ID 7297 //
     /* 154991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 154994 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155001 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 155004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155008 */     // MIs[0] Rn
     /* 155008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155016 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155020 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>>  =>  (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXW),
     /* 155023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155027 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155033 */     GIR_RootConstrainSelectedInstOperands,
     /* 155034 */     // GIR_Coverage, 7297,
     /* 155034 */     GIR_EraseRootFromParent_Done,
     /* 155035 */   // Label 2754: @155035
     /* 155035 */   GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(155084), // Rule ID 7298 //
     /* 155040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155043 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155050 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 155053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155057 */     // MIs[0] Rn
     /* 155057 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155061 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155069 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>>  =>  (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAW),
     /* 155072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155074 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155076 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155082 */     GIR_RootConstrainSelectedInstOperands,
     /* 155083 */     // GIR_Coverage, 7298,
     /* 155083 */     GIR_EraseRootFromParent_Done,
     /* 155084 */   // Label 2755: @155084
     /* 155084 */   GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(155133), // Rule ID 7299 //
     /* 155089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155092 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155099 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 155102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155106 */     // MIs[0] Rn
     /* 155106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155110 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155114 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155118 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>>  =>  (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLW),
     /* 155121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155125 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155131 */     GIR_RootConstrainSelectedInstOperands,
     /* 155132 */     // GIR_Coverage, 7299,
     /* 155132 */     GIR_EraseRootFromParent_Done,
     /* 155133 */   // Label 2756: @155133
     /* 155133 */   GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(155182), // Rule ID 7300 //
     /* 155138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155141 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155148 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 155151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155155 */     // MIs[0] Rn
     /* 155155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155163 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155167 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>>  =>  (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
     /* 155170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155174 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155176 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155180 */     GIR_RootConstrainSelectedInstOperands,
     /* 155181 */     // GIR_Coverage, 7300,
     /* 155181 */     GIR_EraseRootFromParent_Done,
     /* 155182 */   // Label 2757: @155182
     /* 155182 */   GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(155231), // Rule ID 7301 //
     /* 155187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155190 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155197 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 155200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155204 */     // MIs[0] Rn
     /* 155204 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155208 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155216 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>>  =>  (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
     /* 155219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155223 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155225 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155229 */     GIR_RootConstrainSelectedInstOperands,
     /* 155230 */     // GIR_Coverage, 7301,
     /* 155230 */     GIR_EraseRootFromParent_Done,
     /* 155231 */   // Label 2758: @155231
     /* 155231 */   GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(155280), // Rule ID 7302 //
     /* 155236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155239 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155246 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 155249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155253 */     // MIs[0] Rn
     /* 155253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155257 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155265 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>>  =>  (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXH),
     /* 155268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155272 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155278 */     GIR_RootConstrainSelectedInstOperands,
     /* 155279 */     // GIR_Coverage, 7302,
     /* 155279 */     GIR_EraseRootFromParent_Done,
     /* 155280 */   // Label 2759: @155280
     /* 155280 */   GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(155329), // Rule ID 7303 //
     /* 155285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155288 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155295 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 155298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155302 */     // MIs[0] Rn
     /* 155302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155314 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>>  =>  (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAH),
     /* 155317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155321 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155327 */     GIR_RootConstrainSelectedInstOperands,
     /* 155328 */     // GIR_Coverage, 7303,
     /* 155328 */     GIR_EraseRootFromParent_Done,
     /* 155329 */   // Label 2760: @155329
     /* 155329 */   GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(155378), // Rule ID 7304 //
     /* 155334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155337 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155344 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 155347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155351 */     // MIs[0] Rn
     /* 155351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155355 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155359 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155363 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>>  =>  (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLH),
     /* 155366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155370 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155376 */     GIR_RootConstrainSelectedInstOperands,
     /* 155377 */     // GIR_Coverage, 7304,
     /* 155377 */     GIR_EraseRootFromParent_Done,
     /* 155378 */   // Label 2761: @155378
     /* 155378 */   GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(155427), // Rule ID 7305 //
     /* 155383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155386 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155393 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 155396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155400 */     // MIs[0] Rn
     /* 155400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155404 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155412 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>>  =>  (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
     /* 155415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155419 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155425 */     GIR_RootConstrainSelectedInstOperands,
     /* 155426 */     // GIR_Coverage, 7305,
     /* 155426 */     GIR_EraseRootFromParent_Done,
     /* 155427 */   // Label 2762: @155427
     /* 155427 */   GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(155476), // Rule ID 7306 //
     /* 155432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155435 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155442 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 155445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155449 */     // MIs[0] Rn
     /* 155449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155453 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155457 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155461 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>>  =>  (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
     /* 155464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155466 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155468 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155474 */     GIR_RootConstrainSelectedInstOperands,
     /* 155475 */     // GIR_Coverage, 7306,
     /* 155475 */     GIR_EraseRootFromParent_Done,
     /* 155476 */   // Label 2763: @155476
     /* 155476 */   GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(155525), // Rule ID 7307 //
     /* 155481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155484 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155491 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 155494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155498 */     // MIs[0] Rn
     /* 155498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155502 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155506 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155510 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>>  =>  (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXB),
     /* 155513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155517 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155523 */     GIR_RootConstrainSelectedInstOperands,
     /* 155524 */     // GIR_Coverage, 7307,
     /* 155524 */     GIR_EraseRootFromParent_Done,
     /* 155525 */   // Label 2764: @155525
     /* 155525 */   GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(155574), // Rule ID 7308 //
     /* 155530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155533 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155540 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 155543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155547 */     // MIs[0] Rn
     /* 155547 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155551 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155555 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155559 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>>  =>  (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAB),
     /* 155562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155566 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155572 */     GIR_RootConstrainSelectedInstOperands,
     /* 155573 */     // GIR_Coverage, 7308,
     /* 155573 */     GIR_EraseRootFromParent_Done,
     /* 155574 */   // Label 2765: @155574
     /* 155574 */   GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(155623), // Rule ID 7309 //
     /* 155579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155582 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155589 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 155592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155596 */     // MIs[0] Rn
     /* 155596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155600 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155608 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>>  =>  (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLB),
     /* 155611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155615 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155621 */     GIR_RootConstrainSelectedInstOperands,
     /* 155622 */     // GIR_Coverage, 7309,
     /* 155622 */     GIR_EraseRootFromParent_Done,
     /* 155623 */   // Label 2766: @155623
     /* 155623 */   GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(155672), // Rule ID 7310 //
     /* 155628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155631 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155638 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 155641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155645 */     // MIs[0] Rn
     /* 155645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155649 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155657 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>>  =>  (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
     /* 155660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155664 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155670 */     GIR_RootConstrainSelectedInstOperands,
     /* 155671 */     // GIR_Coverage, 7310,
     /* 155671 */     GIR_EraseRootFromParent_Done,
     /* 155672 */   // Label 2767: @155672
     /* 155672 */   GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(155721), // Rule ID 7311 //
     /* 155677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155680 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155687 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 155690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155694 */     // MIs[0] Rn
     /* 155694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155698 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155706 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>>  =>  (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
     /* 155709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155713 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155719 */     GIR_RootConstrainSelectedInstOperands,
     /* 155720 */     // GIR_Coverage, 7311,
     /* 155720 */     GIR_EraseRootFromParent_Done,
     /* 155721 */   // Label 2768: @155721
     /* 155721 */   GIM_Reject,
     /* 155722 */ // Label 2753: @155722
     /* 155722 */ GIM_Reject,
     /* 155723 */ // Label 2751: @155723
     /* 155723 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(155949),
     /* 155728 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 155731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 155738 */   GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(155780), // Rule ID 7292 //
     /* 155743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155746 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 155749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155753 */     // MIs[0] Rn
     /* 155753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155757 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155765 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_monotonic>>  =>  (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXX),
     /* 155768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155772 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155774 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155778 */     GIR_RootConstrainSelectedInstOperands,
     /* 155779 */     // GIR_Coverage, 7292,
     /* 155779 */     GIR_EraseRootFromParent_Done,
     /* 155780 */   // Label 2770: @155780
     /* 155780 */   GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(155822), // Rule ID 7293 //
     /* 155785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155788 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 155791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155795 */     // MIs[0] Rn
     /* 155795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155799 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155803 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155807 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acquire>>  =>  (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAX),
     /* 155810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155814 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155820 */     GIR_RootConstrainSelectedInstOperands,
     /* 155821 */     // GIR_Coverage, 7293,
     /* 155821 */     GIR_EraseRootFromParent_Done,
     /* 155822 */   // Label 2771: @155822
     /* 155822 */   GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(155864), // Rule ID 7294 //
     /* 155827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155830 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 155833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155837 */     // MIs[0] Rn
     /* 155837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155841 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155845 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155849 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_release>>  =>  (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLX),
     /* 155852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155856 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155862 */     GIR_RootConstrainSelectedInstOperands,
     /* 155863 */     // GIR_Coverage, 7294,
     /* 155863 */     GIR_EraseRootFromParent_Done,
     /* 155864 */   // Label 2772: @155864
     /* 155864 */   GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(155906), // Rule ID 7295 //
     /* 155869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155872 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 155875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155879 */     // MIs[0] Rn
     /* 155879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155883 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155891 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acq_rel>>  =>  (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
     /* 155894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155904 */     GIR_RootConstrainSelectedInstOperands,
     /* 155905 */     // GIR_Coverage, 7295,
     /* 155905 */     GIR_EraseRootFromParent_Done,
     /* 155906 */   // Label 2773: @155906
     /* 155906 */   GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(155948), // Rule ID 7296 //
     /* 155911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155914 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 155917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155921 */     // MIs[0] Rn
     /* 155921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155925 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 155933 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_seq_cst>>  =>  (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 155933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
     /* 155936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 155938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 155940 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155946 */     GIR_RootConstrainSelectedInstOperands,
     /* 155947 */     // GIR_Coverage, 7296,
     /* 155947 */     GIR_EraseRootFromParent_Done,
     /* 155948 */   // Label 2774: @155948
     /* 155948 */   GIM_Reject,
     /* 155949 */ // Label 2769: @155949
     /* 155949 */ GIM_Reject,
     /* 155950 */ // Label 2752: @155950
     /* 155950 */ GIM_Reject,
     /* 155951 */ // Label 28: @155951
     /* 155951 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2777*/ GIMT_Encode4(156942),
     /* 155962 */ /*GILLT_s32*//*Label 2775*/ GIMT_Encode4(155970),
     /* 155966 */ /*GILLT_s64*//*Label 2776*/ GIMT_Encode4(156715),
     /* 155970 */ // Label 2775: @155970
     /* 155970 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(156714),
     /* 155975 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 155978 */   GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(156027), // Rule ID 7317 //
     /* 155983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 155986 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 155993 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 155996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156000 */     // MIs[0] Rn
     /* 156000 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156004 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156012 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>>  =>  (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINW),
     /* 156015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156019 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156025 */     GIR_RootConstrainSelectedInstOperands,
     /* 156026 */     // GIR_Coverage, 7317,
     /* 156026 */     GIR_EraseRootFromParent_Done,
     /* 156027 */   // Label 2779: @156027
     /* 156027 */   GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(156076), // Rule ID 7318 //
     /* 156032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156035 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156042 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 156045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156049 */     // MIs[0] Rn
     /* 156049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156053 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156057 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156061 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>>  =>  (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAW),
     /* 156064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156068 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156074 */     GIR_RootConstrainSelectedInstOperands,
     /* 156075 */     // GIR_Coverage, 7318,
     /* 156075 */     GIR_EraseRootFromParent_Done,
     /* 156076 */   // Label 2780: @156076
     /* 156076 */   GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(156125), // Rule ID 7319 //
     /* 156081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156084 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156091 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156098 */     // MIs[0] Rn
     /* 156098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156102 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156106 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156110 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>>  =>  (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLW),
     /* 156113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156117 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156123 */     GIR_RootConstrainSelectedInstOperands,
     /* 156124 */     // GIR_Coverage, 7319,
     /* 156124 */     GIR_EraseRootFromParent_Done,
     /* 156125 */   // Label 2781: @156125
     /* 156125 */   GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(156174), // Rule ID 7320 //
     /* 156130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156133 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156140 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 156143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156147 */     // MIs[0] Rn
     /* 156147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156151 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156159 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>>  =>  (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
     /* 156162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156164 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156166 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156172 */     GIR_RootConstrainSelectedInstOperands,
     /* 156173 */     // GIR_Coverage, 7320,
     /* 156173 */     GIR_EraseRootFromParent_Done,
     /* 156174 */   // Label 2782: @156174
     /* 156174 */   GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(156223), // Rule ID 7321 //
     /* 156179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156182 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156189 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 156192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156196 */     // MIs[0] Rn
     /* 156196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156208 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>>  =>  (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
     /* 156211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156215 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156221 */     GIR_RootConstrainSelectedInstOperands,
     /* 156222 */     // GIR_Coverage, 7321,
     /* 156222 */     GIR_EraseRootFromParent_Done,
     /* 156223 */   // Label 2783: @156223
     /* 156223 */   GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(156272), // Rule ID 7322 //
     /* 156228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156231 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156238 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 156241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156245 */     // MIs[0] Rn
     /* 156245 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156249 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156257 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>>  =>  (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINH),
     /* 156260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156264 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156270 */     GIR_RootConstrainSelectedInstOperands,
     /* 156271 */     // GIR_Coverage, 7322,
     /* 156271 */     GIR_EraseRootFromParent_Done,
     /* 156272 */   // Label 2784: @156272
     /* 156272 */   GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(156321), // Rule ID 7323 //
     /* 156277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156280 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156287 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 156290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156294 */     // MIs[0] Rn
     /* 156294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156298 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156306 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>>  =>  (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAH),
     /* 156309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156313 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156319 */     GIR_RootConstrainSelectedInstOperands,
     /* 156320 */     // GIR_Coverage, 7323,
     /* 156320 */     GIR_EraseRootFromParent_Done,
     /* 156321 */   // Label 2785: @156321
     /* 156321 */   GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(156370), // Rule ID 7324 //
     /* 156326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156329 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156336 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156343 */     // MIs[0] Rn
     /* 156343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156355 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>>  =>  (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLH),
     /* 156358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156362 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156368 */     GIR_RootConstrainSelectedInstOperands,
     /* 156369 */     // GIR_Coverage, 7324,
     /* 156369 */     GIR_EraseRootFromParent_Done,
     /* 156370 */   // Label 2786: @156370
     /* 156370 */   GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(156419), // Rule ID 7325 //
     /* 156375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156378 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156385 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 156388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156392 */     // MIs[0] Rn
     /* 156392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156396 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156400 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156404 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>>  =>  (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
     /* 156407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156409 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156411 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156417 */     GIR_RootConstrainSelectedInstOperands,
     /* 156418 */     // GIR_Coverage, 7325,
     /* 156418 */     GIR_EraseRootFromParent_Done,
     /* 156419 */   // Label 2787: @156419
     /* 156419 */   GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(156468), // Rule ID 7326 //
     /* 156424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156427 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156434 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 156437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156441 */     // MIs[0] Rn
     /* 156441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156445 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156453 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>>  =>  (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
     /* 156456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156460 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156466 */     GIR_RootConstrainSelectedInstOperands,
     /* 156467 */     // GIR_Coverage, 7326,
     /* 156467 */     GIR_EraseRootFromParent_Done,
     /* 156468 */   // Label 2788: @156468
     /* 156468 */   GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(156517), // Rule ID 7327 //
     /* 156473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156476 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156483 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 156486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156490 */     // MIs[0] Rn
     /* 156490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156494 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156502 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>>  =>  (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINB),
     /* 156505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156509 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156515 */     GIR_RootConstrainSelectedInstOperands,
     /* 156516 */     // GIR_Coverage, 7327,
     /* 156516 */     GIR_EraseRootFromParent_Done,
     /* 156517 */   // Label 2789: @156517
     /* 156517 */   GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(156566), // Rule ID 7328 //
     /* 156522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156525 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156532 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 156535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156539 */     // MIs[0] Rn
     /* 156539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156543 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156547 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156551 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>>  =>  (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAB),
     /* 156554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156558 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156564 */     GIR_RootConstrainSelectedInstOperands,
     /* 156565 */     // GIR_Coverage, 7328,
     /* 156565 */     GIR_EraseRootFromParent_Done,
     /* 156566 */   // Label 2790: @156566
     /* 156566 */   GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(156615), // Rule ID 7329 //
     /* 156571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156574 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156581 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156588 */     // MIs[0] Rn
     /* 156588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156592 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156600 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>>  =>  (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLB),
     /* 156603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156607 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156613 */     GIR_RootConstrainSelectedInstOperands,
     /* 156614 */     // GIR_Coverage, 7329,
     /* 156614 */     GIR_EraseRootFromParent_Done,
     /* 156615 */   // Label 2791: @156615
     /* 156615 */   GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(156664), // Rule ID 7330 //
     /* 156620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156623 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156630 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 156633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156637 */     // MIs[0] Rn
     /* 156637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156641 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156649 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>>  =>  (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
     /* 156652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156654 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156656 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156662 */     GIR_RootConstrainSelectedInstOperands,
     /* 156663 */     // GIR_Coverage, 7330,
     /* 156663 */     GIR_EraseRootFromParent_Done,
     /* 156664 */   // Label 2792: @156664
     /* 156664 */   GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(156713), // Rule ID 7331 //
     /* 156669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156672 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156679 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 156682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156686 */     // MIs[0] Rn
     /* 156686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156690 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156698 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>>  =>  (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
     /* 156701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156705 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156711 */     GIR_RootConstrainSelectedInstOperands,
     /* 156712 */     // GIR_Coverage, 7331,
     /* 156712 */     GIR_EraseRootFromParent_Done,
     /* 156713 */   // Label 2793: @156713
     /* 156713 */   GIM_Reject,
     /* 156714 */ // Label 2778: @156714
     /* 156714 */ GIM_Reject,
     /* 156715 */ // Label 2776: @156715
     /* 156715 */ GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(156941),
     /* 156720 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 156723 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 156730 */   GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(156772), // Rule ID 7312 //
     /* 156735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156738 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 156741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156745 */     // MIs[0] Rn
     /* 156745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156753 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156757 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_monotonic>>  =>  (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINX),
     /* 156760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156762 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156764 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156770 */     GIR_RootConstrainSelectedInstOperands,
     /* 156771 */     // GIR_Coverage, 7312,
     /* 156771 */     GIR_EraseRootFromParent_Done,
     /* 156772 */   // Label 2795: @156772
     /* 156772 */   GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(156814), // Rule ID 7313 //
     /* 156777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156780 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 156783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156787 */     // MIs[0] Rn
     /* 156787 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156791 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156799 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acquire>>  =>  (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAX),
     /* 156802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156804 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156806 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156812 */     GIR_RootConstrainSelectedInstOperands,
     /* 156813 */     // GIR_Coverage, 7313,
     /* 156813 */     GIR_EraseRootFromParent_Done,
     /* 156814 */   // Label 2796: @156814
     /* 156814 */   GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(156856), // Rule ID 7314 //
     /* 156819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156822 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156829 */     // MIs[0] Rn
     /* 156829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156833 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156837 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156841 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_release>>  =>  (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLX),
     /* 156844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156846 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156848 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156854 */     GIR_RootConstrainSelectedInstOperands,
     /* 156855 */     // GIR_Coverage, 7314,
     /* 156855 */     GIR_EraseRootFromParent_Done,
     /* 156856 */   // Label 2797: @156856
     /* 156856 */   GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(156898), // Rule ID 7315 //
     /* 156861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156864 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 156867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156871 */     // MIs[0] Rn
     /* 156871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156883 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acq_rel>>  =>  (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
     /* 156886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156890 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156896 */     GIR_RootConstrainSelectedInstOperands,
     /* 156897 */     // GIR_Coverage, 7315,
     /* 156897 */     GIR_EraseRootFromParent_Done,
     /* 156898 */   // Label 2798: @156898
     /* 156898 */   GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(156940), // Rule ID 7316 //
     /* 156903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156906 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 156909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156913 */     // MIs[0] Rn
     /* 156913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 156921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 156925 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_seq_cst>>  =>  (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 156925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
     /* 156928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 156930 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 156932 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 156934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156938 */     GIR_RootConstrainSelectedInstOperands,
     /* 156939 */     // GIR_Coverage, 7316,
     /* 156939 */     GIR_EraseRootFromParent_Done,
     /* 156940 */   // Label 2799: @156940
     /* 156940 */   GIM_Reject,
     /* 156941 */ // Label 2794: @156941
     /* 156941 */ GIM_Reject,
     /* 156942 */ // Label 2777: @156942
     /* 156942 */ GIM_Reject,
     /* 156943 */ // Label 29: @156943
     /* 156943 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2802*/ GIMT_Encode4(157934),
     /* 156954 */ /*GILLT_s32*//*Label 2800*/ GIMT_Encode4(156962),
     /* 156958 */ /*GILLT_s64*//*Label 2801*/ GIMT_Encode4(157707),
     /* 156962 */ // Label 2800: @156962
     /* 156962 */ GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(157706),
     /* 156967 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 156970 */   GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(157019), // Rule ID 7337 //
     /* 156975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 156978 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156985 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 156988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156992 */     // MIs[0] Rn
     /* 156992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 156996 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157004 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>>  =>  (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXW),
     /* 157007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157011 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157017 */     GIR_RootConstrainSelectedInstOperands,
     /* 157018 */     // GIR_Coverage, 7337,
     /* 157018 */     GIR_EraseRootFromParent_Done,
     /* 157019 */   // Label 2804: @157019
     /* 157019 */   GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(157068), // Rule ID 7338 //
     /* 157024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157027 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157034 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 157037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157041 */     // MIs[0] Rn
     /* 157041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157045 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157049 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157053 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>>  =>  (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAW),
     /* 157056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157058 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157060 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157066 */     GIR_RootConstrainSelectedInstOperands,
     /* 157067 */     // GIR_Coverage, 7338,
     /* 157067 */     GIR_EraseRootFromParent_Done,
     /* 157068 */   // Label 2805: @157068
     /* 157068 */   GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(157117), // Rule ID 7339 //
     /* 157073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157076 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157083 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157090 */     // MIs[0] Rn
     /* 157090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157102 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>>  =>  (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLW),
     /* 157105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157109 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157115 */     GIR_RootConstrainSelectedInstOperands,
     /* 157116 */     // GIR_Coverage, 7339,
     /* 157116 */     GIR_EraseRootFromParent_Done,
     /* 157117 */   // Label 2806: @157117
     /* 157117 */   GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(157166), // Rule ID 7340 //
     /* 157122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157125 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157132 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 157135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157139 */     // MIs[0] Rn
     /* 157139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157151 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>>  =>  (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
     /* 157154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157158 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157164 */     GIR_RootConstrainSelectedInstOperands,
     /* 157165 */     // GIR_Coverage, 7340,
     /* 157165 */     GIR_EraseRootFromParent_Done,
     /* 157166 */   // Label 2807: @157166
     /* 157166 */   GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(157215), // Rule ID 7341 //
     /* 157171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157174 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157181 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 157184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157188 */     // MIs[0] Rn
     /* 157188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157192 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157196 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157200 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>>  =>  (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
     /* 157203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157207 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157213 */     GIR_RootConstrainSelectedInstOperands,
     /* 157214 */     // GIR_Coverage, 7341,
     /* 157214 */     GIR_EraseRootFromParent_Done,
     /* 157215 */   // Label 2808: @157215
     /* 157215 */   GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(157264), // Rule ID 7342 //
     /* 157220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157223 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157230 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 157233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157237 */     // MIs[0] Rn
     /* 157237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157241 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157249 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>>  =>  (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXH),
     /* 157252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157256 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157262 */     GIR_RootConstrainSelectedInstOperands,
     /* 157263 */     // GIR_Coverage, 7342,
     /* 157263 */     GIR_EraseRootFromParent_Done,
     /* 157264 */   // Label 2809: @157264
     /* 157264 */   GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(157313), // Rule ID 7343 //
     /* 157269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157272 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157279 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 157282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157286 */     // MIs[0] Rn
     /* 157286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157290 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157298 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>>  =>  (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAH),
     /* 157301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157305 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157311 */     GIR_RootConstrainSelectedInstOperands,
     /* 157312 */     // GIR_Coverage, 7343,
     /* 157312 */     GIR_EraseRootFromParent_Done,
     /* 157313 */   // Label 2810: @157313
     /* 157313 */   GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(157362), // Rule ID 7344 //
     /* 157318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157321 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157328 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157335 */     // MIs[0] Rn
     /* 157335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157339 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157347 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>>  =>  (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLH),
     /* 157350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157352 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157354 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157360 */     GIR_RootConstrainSelectedInstOperands,
     /* 157361 */     // GIR_Coverage, 7344,
     /* 157361 */     GIR_EraseRootFromParent_Done,
     /* 157362 */   // Label 2811: @157362
     /* 157362 */   GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(157411), // Rule ID 7345 //
     /* 157367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157370 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157377 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 157380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157384 */     // MIs[0] Rn
     /* 157384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157388 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157396 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>>  =>  (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
     /* 157399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157403 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157409 */     GIR_RootConstrainSelectedInstOperands,
     /* 157410 */     // GIR_Coverage, 7345,
     /* 157410 */     GIR_EraseRootFromParent_Done,
     /* 157411 */   // Label 2812: @157411
     /* 157411 */   GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(157460), // Rule ID 7346 //
     /* 157416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157419 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157426 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 157429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157433 */     // MIs[0] Rn
     /* 157433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157437 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157441 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157445 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>>  =>  (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
     /* 157448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157452 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157458 */     GIR_RootConstrainSelectedInstOperands,
     /* 157459 */     // GIR_Coverage, 7346,
     /* 157459 */     GIR_EraseRootFromParent_Done,
     /* 157460 */   // Label 2813: @157460
     /* 157460 */   GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(157509), // Rule ID 7347 //
     /* 157465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157468 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157475 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 157478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157482 */     // MIs[0] Rn
     /* 157482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157486 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157490 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157494 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>>  =>  (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXB),
     /* 157497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157499 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157501 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157507 */     GIR_RootConstrainSelectedInstOperands,
     /* 157508 */     // GIR_Coverage, 7347,
     /* 157508 */     GIR_EraseRootFromParent_Done,
     /* 157509 */   // Label 2814: @157509
     /* 157509 */   GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(157558), // Rule ID 7348 //
     /* 157514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157517 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157524 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 157527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157531 */     // MIs[0] Rn
     /* 157531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157535 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157543 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>>  =>  (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAB),
     /* 157546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157550 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157556 */     GIR_RootConstrainSelectedInstOperands,
     /* 157557 */     // GIR_Coverage, 7348,
     /* 157557 */     GIR_EraseRootFromParent_Done,
     /* 157558 */   // Label 2815: @157558
     /* 157558 */   GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(157607), // Rule ID 7349 //
     /* 157563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157566 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157573 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157580 */     // MIs[0] Rn
     /* 157580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157584 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157592 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>>  =>  (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLB),
     /* 157595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157599 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157605 */     GIR_RootConstrainSelectedInstOperands,
     /* 157606 */     // GIR_Coverage, 7349,
     /* 157606 */     GIR_EraseRootFromParent_Done,
     /* 157607 */   // Label 2816: @157607
     /* 157607 */   GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(157656), // Rule ID 7350 //
     /* 157612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157615 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157622 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 157625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157629 */     // MIs[0] Rn
     /* 157629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157641 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>>  =>  (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
     /* 157644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157646 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157648 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157654 */     GIR_RootConstrainSelectedInstOperands,
     /* 157655 */     // GIR_Coverage, 7350,
     /* 157655 */     GIR_EraseRootFromParent_Done,
     /* 157656 */   // Label 2817: @157656
     /* 157656 */   GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(157705), // Rule ID 7351 //
     /* 157661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157664 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157671 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 157674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157678 */     // MIs[0] Rn
     /* 157678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157682 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157690 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>>  =>  (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
     /* 157693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157697 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157703 */     GIR_RootConstrainSelectedInstOperands,
     /* 157704 */     // GIR_Coverage, 7351,
     /* 157704 */     GIR_EraseRootFromParent_Done,
     /* 157705 */   // Label 2818: @157705
     /* 157705 */   GIM_Reject,
     /* 157706 */ // Label 2803: @157706
     /* 157706 */ GIM_Reject,
     /* 157707 */ // Label 2801: @157707
     /* 157707 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(157933),
     /* 157712 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 157715 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 157722 */   GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(157764), // Rule ID 7332 //
     /* 157727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157730 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 157733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157737 */     // MIs[0] Rn
     /* 157737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157741 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157749 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_monotonic>>  =>  (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXX),
     /* 157752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157754 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157756 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157762 */     GIR_RootConstrainSelectedInstOperands,
     /* 157763 */     // GIR_Coverage, 7332,
     /* 157763 */     GIR_EraseRootFromParent_Done,
     /* 157764 */   // Label 2820: @157764
     /* 157764 */   GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(157806), // Rule ID 7333 //
     /* 157769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157772 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 157775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157779 */     // MIs[0] Rn
     /* 157779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157783 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157787 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157791 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acquire>>  =>  (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAX),
     /* 157794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157796 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157804 */     GIR_RootConstrainSelectedInstOperands,
     /* 157805 */     // GIR_Coverage, 7333,
     /* 157805 */     GIR_EraseRootFromParent_Done,
     /* 157806 */   // Label 2821: @157806
     /* 157806 */   GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(157848), // Rule ID 7334 //
     /* 157811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157814 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157821 */     // MIs[0] Rn
     /* 157821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157825 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157829 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157833 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_release>>  =>  (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLX),
     /* 157836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157840 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157842 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157846 */     GIR_RootConstrainSelectedInstOperands,
     /* 157847 */     // GIR_Coverage, 7334,
     /* 157847 */     GIR_EraseRootFromParent_Done,
     /* 157848 */   // Label 2822: @157848
     /* 157848 */   GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(157890), // Rule ID 7335 //
     /* 157853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157856 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 157859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157863 */     // MIs[0] Rn
     /* 157863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157875 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acq_rel>>  =>  (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
     /* 157878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157882 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157888 */     GIR_RootConstrainSelectedInstOperands,
     /* 157889 */     // GIR_Coverage, 7335,
     /* 157889 */     GIR_EraseRootFromParent_Done,
     /* 157890 */   // Label 2823: @157890
     /* 157890 */   GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(157932), // Rule ID 7336 //
     /* 157895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157898 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 157901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157905 */     // MIs[0] Rn
     /* 157905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157909 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 157917 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_seq_cst>>  =>  (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
     /* 157920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 157922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 157924 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 157926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157930 */     GIR_RootConstrainSelectedInstOperands,
     /* 157931 */     // GIR_Coverage, 7336,
     /* 157931 */     GIR_EraseRootFromParent_Done,
     /* 157932 */   // Label 2824: @157932
     /* 157932 */   GIM_Reject,
     /* 157933 */ // Label 2819: @157933
     /* 157933 */ GIM_Reject,
     /* 157934 */ // Label 2802: @157934
     /* 157934 */ GIM_Reject,
     /* 157935 */ // Label 30: @157935
     /* 157935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2827*/ GIMT_Encode4(158926),
     /* 157946 */ /*GILLT_s32*//*Label 2825*/ GIMT_Encode4(157954),
     /* 157950 */ /*GILLT_s64*//*Label 2826*/ GIMT_Encode4(158699),
     /* 157954 */ // Label 2825: @157954
     /* 157954 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(158698),
     /* 157959 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 157962 */   GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(158011), // Rule ID 7357 //
     /* 157967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 157970 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157977 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 157980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157984 */     // MIs[0] Rn
     /* 157984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157988 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157996 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>>  =>  (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 157996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINW),
     /* 157999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158003 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158009 */     GIR_RootConstrainSelectedInstOperands,
     /* 158010 */     // GIR_Coverage, 7357,
     /* 158010 */     GIR_EraseRootFromParent_Done,
     /* 158011 */   // Label 2829: @158011
     /* 158011 */   GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(158060), // Rule ID 7358 //
     /* 158016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158019 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 158026 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 158029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158033 */     // MIs[0] Rn
     /* 158033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158037 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158041 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158045 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>>  =>  (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAW),
     /* 158048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158050 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158052 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158058 */     GIR_RootConstrainSelectedInstOperands,
     /* 158059 */     // GIR_Coverage, 7358,
     /* 158059 */     GIR_EraseRootFromParent_Done,
     /* 158060 */   // Label 2830: @158060
     /* 158060 */   GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(158109), // Rule ID 7359 //
     /* 158065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158068 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 158075 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 158078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158082 */     // MIs[0] Rn
     /* 158082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158086 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158094 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>>  =>  (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLW),
     /* 158097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158099 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158101 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158107 */     GIR_RootConstrainSelectedInstOperands,
     /* 158108 */     // GIR_Coverage, 7359,
     /* 158108 */     GIR_EraseRootFromParent_Done,
     /* 158109 */   // Label 2831: @158109
     /* 158109 */   GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(158158), // Rule ID 7360 //
     /* 158114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158117 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 158124 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 158127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158131 */     // MIs[0] Rn
     /* 158131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158135 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158143 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>>  =>  (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
     /* 158146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158150 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158156 */     GIR_RootConstrainSelectedInstOperands,
     /* 158157 */     // GIR_Coverage, 7360,
     /* 158157 */     GIR_EraseRootFromParent_Done,
     /* 158158 */   // Label 2832: @158158
     /* 158158 */   GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(158207), // Rule ID 7361 //
     /* 158163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158166 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 158173 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 158176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158180 */     // MIs[0] Rn
     /* 158180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158184 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158192 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>>  =>  (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
     /* 158195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158199 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158205 */     GIR_RootConstrainSelectedInstOperands,
     /* 158206 */     // GIR_Coverage, 7361,
     /* 158206 */     GIR_EraseRootFromParent_Done,
     /* 158207 */   // Label 2833: @158207
     /* 158207 */   GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(158256), // Rule ID 7362 //
     /* 158212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158215 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158222 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 158225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158229 */     // MIs[0] Rn
     /* 158229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158241 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>>  =>  (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINH),
     /* 158244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158248 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158254 */     GIR_RootConstrainSelectedInstOperands,
     /* 158255 */     // GIR_Coverage, 7362,
     /* 158255 */     GIR_EraseRootFromParent_Done,
     /* 158256 */   // Label 2834: @158256
     /* 158256 */   GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(158305), // Rule ID 7363 //
     /* 158261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158264 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158271 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 158274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158278 */     // MIs[0] Rn
     /* 158278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158286 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158290 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>>  =>  (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAH),
     /* 158293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158297 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158303 */     GIR_RootConstrainSelectedInstOperands,
     /* 158304 */     // GIR_Coverage, 7363,
     /* 158304 */     GIR_EraseRootFromParent_Done,
     /* 158305 */   // Label 2835: @158305
     /* 158305 */   GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(158354), // Rule ID 7364 //
     /* 158310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158313 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158320 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 158323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158327 */     // MIs[0] Rn
     /* 158327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158331 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158335 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158339 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>>  =>  (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLH),
     /* 158342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158346 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158352 */     GIR_RootConstrainSelectedInstOperands,
     /* 158353 */     // GIR_Coverage, 7364,
     /* 158353 */     GIR_EraseRootFromParent_Done,
     /* 158354 */   // Label 2836: @158354
     /* 158354 */   GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(158403), // Rule ID 7365 //
     /* 158359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158362 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158369 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 158372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158376 */     // MIs[0] Rn
     /* 158376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158380 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158388 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>>  =>  (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
     /* 158391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158395 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158401 */     GIR_RootConstrainSelectedInstOperands,
     /* 158402 */     // GIR_Coverage, 7365,
     /* 158402 */     GIR_EraseRootFromParent_Done,
     /* 158403 */   // Label 2837: @158403
     /* 158403 */   GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(158452), // Rule ID 7366 //
     /* 158408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158411 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158418 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 158421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158425 */     // MIs[0] Rn
     /* 158425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158429 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158433 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158437 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>>  =>  (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
     /* 158440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158444 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158450 */     GIR_RootConstrainSelectedInstOperands,
     /* 158451 */     // GIR_Coverage, 7366,
     /* 158451 */     GIR_EraseRootFromParent_Done,
     /* 158452 */   // Label 2838: @158452
     /* 158452 */   GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(158501), // Rule ID 7367 //
     /* 158457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158460 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 158467 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 158470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158474 */     // MIs[0] Rn
     /* 158474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158486 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>>  =>  (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINB),
     /* 158489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158491 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158499 */     GIR_RootConstrainSelectedInstOperands,
     /* 158500 */     // GIR_Coverage, 7367,
     /* 158500 */     GIR_EraseRootFromParent_Done,
     /* 158501 */   // Label 2839: @158501
     /* 158501 */   GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(158550), // Rule ID 7368 //
     /* 158506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158509 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 158516 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 158519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158523 */     // MIs[0] Rn
     /* 158523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158527 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158535 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>>  =>  (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAB),
     /* 158538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158542 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158548 */     GIR_RootConstrainSelectedInstOperands,
     /* 158549 */     // GIR_Coverage, 7368,
     /* 158549 */     GIR_EraseRootFromParent_Done,
     /* 158550 */   // Label 2840: @158550
     /* 158550 */   GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(158599), // Rule ID 7369 //
     /* 158555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158558 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 158565 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 158568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158572 */     // MIs[0] Rn
     /* 158572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158576 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158584 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>>  =>  (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLB),
     /* 158587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158589 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158591 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158597 */     GIR_RootConstrainSelectedInstOperands,
     /* 158598 */     // GIR_Coverage, 7369,
     /* 158598 */     GIR_EraseRootFromParent_Done,
     /* 158599 */   // Label 2841: @158599
     /* 158599 */   GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(158648), // Rule ID 7370 //
     /* 158604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158607 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 158614 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 158617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158621 */     // MIs[0] Rn
     /* 158621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158625 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158629 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158633 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>>  =>  (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
     /* 158636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158638 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158640 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158646 */     GIR_RootConstrainSelectedInstOperands,
     /* 158647 */     // GIR_Coverage, 7370,
     /* 158647 */     GIR_EraseRootFromParent_Done,
     /* 158648 */   // Label 2842: @158648
     /* 158648 */   GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(158697), // Rule ID 7371 //
     /* 158653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158656 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 158663 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 158666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158670 */     // MIs[0] Rn
     /* 158670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158678 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158682 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>>  =>  (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
     /* 158685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158689 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158695 */     GIR_RootConstrainSelectedInstOperands,
     /* 158696 */     // GIR_Coverage, 7371,
     /* 158696 */     GIR_EraseRootFromParent_Done,
     /* 158697 */   // Label 2843: @158697
     /* 158697 */   GIM_Reject,
     /* 158698 */ // Label 2828: @158698
     /* 158698 */ GIM_Reject,
     /* 158699 */ // Label 2826: @158699
     /* 158699 */ GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(158925),
     /* 158704 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 158707 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 158714 */   GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(158756), // Rule ID 7352 //
     /* 158719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158722 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 158725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158729 */     // MIs[0] Rn
     /* 158729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158733 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158741 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_monotonic>>  =>  (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINX),
     /* 158744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158748 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158754 */     GIR_RootConstrainSelectedInstOperands,
     /* 158755 */     // GIR_Coverage, 7352,
     /* 158755 */     GIR_EraseRootFromParent_Done,
     /* 158756 */   // Label 2845: @158756
     /* 158756 */   GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(158798), // Rule ID 7353 //
     /* 158761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158764 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 158767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158771 */     // MIs[0] Rn
     /* 158771 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158775 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158779 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158783 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acquire>>  =>  (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAX),
     /* 158786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158790 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158796 */     GIR_RootConstrainSelectedInstOperands,
     /* 158797 */     // GIR_Coverage, 7353,
     /* 158797 */     GIR_EraseRootFromParent_Done,
     /* 158798 */   // Label 2846: @158798
     /* 158798 */   GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(158840), // Rule ID 7354 //
     /* 158803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158806 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 158809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158813 */     // MIs[0] Rn
     /* 158813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158821 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158825 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_release>>  =>  (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLX),
     /* 158828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158830 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158832 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158838 */     GIR_RootConstrainSelectedInstOperands,
     /* 158839 */     // GIR_Coverage, 7354,
     /* 158839 */     GIR_EraseRootFromParent_Done,
     /* 158840 */   // Label 2847: @158840
     /* 158840 */   GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(158882), // Rule ID 7355 //
     /* 158845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158848 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 158851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158855 */     // MIs[0] Rn
     /* 158855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158859 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158863 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158867 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acq_rel>>  =>  (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
     /* 158870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158874 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158880 */     GIR_RootConstrainSelectedInstOperands,
     /* 158881 */     // GIR_Coverage, 7355,
     /* 158881 */     GIR_EraseRootFromParent_Done,
     /* 158882 */   // Label 2848: @158882
     /* 158882 */   GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(158924), // Rule ID 7356 //
     /* 158887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 158890 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 158893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158897 */     // MIs[0] Rn
     /* 158897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158901 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 158909 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_seq_cst>>  =>  (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 158909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
     /* 158912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158916 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158918 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 158922 */     GIR_RootConstrainSelectedInstOperands,
     /* 158923 */     // GIR_Coverage, 7356,
     /* 158923 */     GIR_EraseRootFromParent_Done,
     /* 158924 */   // Label 2849: @158924
     /* 158924 */   GIM_Reject,
     /* 158925 */ // Label 2844: @158925
     /* 158925 */ GIM_Reject,
     /* 158926 */ // Label 2827: @158926
     /* 158926 */ GIM_Reject,
     /* 158927 */ // Label 31: @158927
     /* 158927 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2853*/ GIMT_Encode4(159631),
     /* 158938 */ /*GILLT_s16*//*Label 2850*/ GIMT_Encode4(158950),
     /* 158942 */ /*GILLT_s32*//*Label 2851*/ GIMT_Encode4(159177),
     /* 158946 */ /*GILLT_s64*//*Label 2852*/ GIMT_Encode4(159404),
     /* 158950 */ // Label 2850: @158950
     /* 158950 */ GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(159176),
     /* 158955 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 158958 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 158965 */   GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(159007), // Rule ID 2584 //
     /* 158970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 158973 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 158976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 158980 */     // MIs[0] Rn
     /* 158980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158984 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 158992 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_monotonic>>  =>  (LDFADDH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 158992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDH),
     /* 158995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 158997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 158999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159005 */     GIR_RootConstrainSelectedInstOperands,
     /* 159006 */     // GIR_Coverage, 2584,
     /* 159006 */     GIR_EraseRootFromParent_Done,
     /* 159007 */   // Label 2855: @159007
     /* 159007 */   GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(159049), // Rule ID 2585 //
     /* 159012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159015 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 159018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159022 */     // MIs[0] Rn
     /* 159022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159026 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159034 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_acquire>>  =>  (LDFADDAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAH),
     /* 159037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159047 */     GIR_RootConstrainSelectedInstOperands,
     /* 159048 */     // GIR_Coverage, 2585,
     /* 159048 */     GIR_EraseRootFromParent_Done,
     /* 159049 */   // Label 2856: @159049
     /* 159049 */   GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(159091), // Rule ID 2586 //
     /* 159054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159057 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 159060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159064 */     // MIs[0] Rn
     /* 159064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159068 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159076 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_release>>  =>  (LDFADDLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLH),
     /* 159079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159089 */     GIR_RootConstrainSelectedInstOperands,
     /* 159090 */     // GIR_Coverage, 2586,
     /* 159090 */     GIR_EraseRootFromParent_Done,
     /* 159091 */   // Label 2857: @159091
     /* 159091 */   GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(159133), // Rule ID 2587 //
     /* 159096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159099 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 159102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159106 */     // MIs[0] Rn
     /* 159106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159110 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159114 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159118 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_acq_rel>>  =>  (LDFADDALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALH),
     /* 159121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159125 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159131 */     GIR_RootConstrainSelectedInstOperands,
     /* 159132 */     // GIR_Coverage, 2587,
     /* 159132 */     GIR_EraseRootFromParent_Done,
     /* 159133 */   // Label 2858: @159133
     /* 159133 */   GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(159175), // Rule ID 2588 //
     /* 159138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159141 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 159144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159148 */     // MIs[0] Rn
     /* 159148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159160 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_seq_cst>>  =>  (LDFADDALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALH),
     /* 159163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159167 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159173 */     GIR_RootConstrainSelectedInstOperands,
     /* 159174 */     // GIR_Coverage, 2588,
     /* 159174 */     GIR_EraseRootFromParent_Done,
     /* 159175 */   // Label 2859: @159175
     /* 159175 */   GIM_Reject,
     /* 159176 */ // Label 2854: @159176
     /* 159176 */ GIM_Reject,
     /* 159177 */ // Label 2851: @159177
     /* 159177 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(159403),
     /* 159182 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 159185 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 159192 */   GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(159234), // Rule ID 7447 //
     /* 159197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159200 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 159203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159207 */     // MIs[0] Rn
     /* 159207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159211 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159215 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159219 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_monotonic>>  =>  (LDFADDS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDS),
     /* 159222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159226 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159232 */     GIR_RootConstrainSelectedInstOperands,
     /* 159233 */     // GIR_Coverage, 7447,
     /* 159233 */     GIR_EraseRootFromParent_Done,
     /* 159234 */   // Label 2861: @159234
     /* 159234 */   GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(159276), // Rule ID 7448 //
     /* 159239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159242 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 159245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159249 */     // MIs[0] Rn
     /* 159249 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159253 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159257 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159261 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_acquire>>  =>  (LDFADDAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAS),
     /* 159264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159268 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159274 */     GIR_RootConstrainSelectedInstOperands,
     /* 159275 */     // GIR_Coverage, 7448,
     /* 159275 */     GIR_EraseRootFromParent_Done,
     /* 159276 */   // Label 2862: @159276
     /* 159276 */   GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(159318), // Rule ID 7449 //
     /* 159281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159284 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 159287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159291 */     // MIs[0] Rn
     /* 159291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159295 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159303 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_release>>  =>  (LDFADDLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLS),
     /* 159306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159310 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159316 */     GIR_RootConstrainSelectedInstOperands,
     /* 159317 */     // GIR_Coverage, 7449,
     /* 159317 */     GIR_EraseRootFromParent_Done,
     /* 159318 */   // Label 2863: @159318
     /* 159318 */   GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(159360), // Rule ID 7450 //
     /* 159323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159326 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 159329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159333 */     // MIs[0] Rn
     /* 159333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159337 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159341 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159345 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_acq_rel>>  =>  (LDFADDALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALS),
     /* 159348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159350 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159352 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159358 */     GIR_RootConstrainSelectedInstOperands,
     /* 159359 */     // GIR_Coverage, 7450,
     /* 159359 */     GIR_EraseRootFromParent_Done,
     /* 159360 */   // Label 2864: @159360
     /* 159360 */   GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(159402), // Rule ID 7451 //
     /* 159365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159368 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 159371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159375 */     // MIs[0] Rn
     /* 159375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159379 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159383 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159387 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_seq_cst>>  =>  (LDFADDALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALS),
     /* 159390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159394 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159400 */     GIR_RootConstrainSelectedInstOperands,
     /* 159401 */     // GIR_Coverage, 7451,
     /* 159401 */     GIR_EraseRootFromParent_Done,
     /* 159402 */   // Label 2865: @159402
     /* 159402 */   GIM_Reject,
     /* 159403 */ // Label 2860: @159403
     /* 159403 */ GIM_Reject,
     /* 159404 */ // Label 2852: @159404
     /* 159404 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(159630),
     /* 159409 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 159412 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 159419 */   GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(159461), // Rule ID 7452 //
     /* 159424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159427 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 159430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159434 */     // MIs[0] Rn
     /* 159434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159438 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159446 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_monotonic>>  =>  (LDFADDD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDD),
     /* 159449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159453 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159455 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159459 */     GIR_RootConstrainSelectedInstOperands,
     /* 159460 */     // GIR_Coverage, 7452,
     /* 159460 */     GIR_EraseRootFromParent_Done,
     /* 159461 */   // Label 2867: @159461
     /* 159461 */   GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(159503), // Rule ID 7453 //
     /* 159466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159469 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 159472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159476 */     // MIs[0] Rn
     /* 159476 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159480 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159488 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_acquire>>  =>  (LDFADDAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAD),
     /* 159491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159495 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159501 */     GIR_RootConstrainSelectedInstOperands,
     /* 159502 */     // GIR_Coverage, 7453,
     /* 159502 */     GIR_EraseRootFromParent_Done,
     /* 159503 */   // Label 2868: @159503
     /* 159503 */   GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(159545), // Rule ID 7454 //
     /* 159508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159511 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 159514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159518 */     // MIs[0] Rn
     /* 159518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159522 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159526 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159530 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_release>>  =>  (LDFADDLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLD),
     /* 159533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159535 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159537 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159543 */     GIR_RootConstrainSelectedInstOperands,
     /* 159544 */     // GIR_Coverage, 7454,
     /* 159544 */     GIR_EraseRootFromParent_Done,
     /* 159545 */   // Label 2869: @159545
     /* 159545 */   GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(159587), // Rule ID 7455 //
     /* 159550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159553 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 159556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159560 */     // MIs[0] Rn
     /* 159560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159564 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159572 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_acq_rel>>  =>  (LDFADDALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALD),
     /* 159575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159579 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159585 */     GIR_RootConstrainSelectedInstOperands,
     /* 159586 */     // GIR_Coverage, 7455,
     /* 159586 */     GIR_EraseRootFromParent_Done,
     /* 159587 */   // Label 2870: @159587
     /* 159587 */   GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(159629), // Rule ID 7456 //
     /* 159592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159595 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 159598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159602 */     // MIs[0] Rn
     /* 159602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159606 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159614 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_seq_cst>>  =>  (LDFADDALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALD),
     /* 159617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159621 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159627 */     GIR_RootConstrainSelectedInstOperands,
     /* 159628 */     // GIR_Coverage, 7456,
     /* 159628 */     GIR_EraseRootFromParent_Done,
     /* 159629 */   // Label 2871: @159629
     /* 159629 */   GIM_Reject,
     /* 159630 */ // Label 2866: @159630
     /* 159630 */ GIM_Reject,
     /* 159631 */ // Label 2853: @159631
     /* 159631 */ GIM_Reject,
     /* 159632 */ // Label 32: @159632
     /* 159632 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2875*/ GIMT_Encode4(160336),
     /* 159643 */ /*GILLT_s16*//*Label 2872*/ GIMT_Encode4(159655),
     /* 159647 */ /*GILLT_s32*//*Label 2873*/ GIMT_Encode4(159882),
     /* 159651 */ /*GILLT_s64*//*Label 2874*/ GIMT_Encode4(160109),
     /* 159655 */ // Label 2872: @159655
     /* 159655 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(159881),
     /* 159660 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 159663 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 159670 */   GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(159712), // Rule ID 7457 //
     /* 159675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159678 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 159681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159685 */     // MIs[0] Rn
     /* 159685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159689 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159693 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159697 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_monotonic>>  =>  (LDFMAXNMH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMH),
     /* 159700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159704 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159710 */     GIR_RootConstrainSelectedInstOperands,
     /* 159711 */     // GIR_Coverage, 7457,
     /* 159711 */     GIR_EraseRootFromParent_Done,
     /* 159712 */   // Label 2877: @159712
     /* 159712 */   GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(159754), // Rule ID 7458 //
     /* 159717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159720 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 159723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159727 */     // MIs[0] Rn
     /* 159727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159731 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159739 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_acquire>>  =>  (LDFMAXNMAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAH),
     /* 159742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159746 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159752 */     GIR_RootConstrainSelectedInstOperands,
     /* 159753 */     // GIR_Coverage, 7458,
     /* 159753 */     GIR_EraseRootFromParent_Done,
     /* 159754 */   // Label 2878: @159754
     /* 159754 */   GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(159796), // Rule ID 7459 //
     /* 159759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159762 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 159765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159769 */     // MIs[0] Rn
     /* 159769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159773 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159781 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_release>>  =>  (LDFMAXNMLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLH),
     /* 159784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159788 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159794 */     GIR_RootConstrainSelectedInstOperands,
     /* 159795 */     // GIR_Coverage, 7459,
     /* 159795 */     GIR_EraseRootFromParent_Done,
     /* 159796 */   // Label 2879: @159796
     /* 159796 */   GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(159838), // Rule ID 7460 //
     /* 159801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159804 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 159807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159811 */     // MIs[0] Rn
     /* 159811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159823 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_acq_rel>>  =>  (LDFMAXNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALH),
     /* 159826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159830 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159836 */     GIR_RootConstrainSelectedInstOperands,
     /* 159837 */     // GIR_Coverage, 7460,
     /* 159837 */     GIR_EraseRootFromParent_Done,
     /* 159838 */   // Label 2880: @159838
     /* 159838 */   GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(159880), // Rule ID 7461 //
     /* 159843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159846 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 159849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159853 */     // MIs[0] Rn
     /* 159853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 159865 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_seq_cst>>  =>  (LDFMAXNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALH),
     /* 159868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159872 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159878 */     GIR_RootConstrainSelectedInstOperands,
     /* 159879 */     // GIR_Coverage, 7461,
     /* 159879 */     GIR_EraseRootFromParent_Done,
     /* 159880 */   // Label 2881: @159880
     /* 159880 */   GIM_Reject,
     /* 159881 */ // Label 2876: @159881
     /* 159881 */ GIM_Reject,
     /* 159882 */ // Label 2873: @159882
     /* 159882 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(160108),
     /* 159887 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 159890 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 159897 */   GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(159939), // Rule ID 7462 //
     /* 159902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159905 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 159908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159912 */     // MIs[0] Rn
     /* 159912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159916 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159924 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_monotonic>>  =>  (LDFMAXNMS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMS),
     /* 159927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159929 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159931 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159937 */     GIR_RootConstrainSelectedInstOperands,
     /* 159938 */     // GIR_Coverage, 7462,
     /* 159938 */     GIR_EraseRootFromParent_Done,
     /* 159939 */   // Label 2883: @159939
     /* 159939 */   GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(159981), // Rule ID 7463 //
     /* 159944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159947 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 159950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159954 */     // MIs[0] Rn
     /* 159954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 159958 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159962 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159966 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_acquire>>  =>  (LDFMAXNMAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 159966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAS),
     /* 159969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 159971 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 159973 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 159975 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159979 */     GIR_RootConstrainSelectedInstOperands,
     /* 159980 */     // GIR_Coverage, 7463,
     /* 159980 */     GIR_EraseRootFromParent_Done,
     /* 159981 */   // Label 2884: @159981
     /* 159981 */   GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(160023), // Rule ID 7464 //
     /* 159986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 159989 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 159992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 159996 */     // MIs[0] Rn
     /* 159996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160000 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160004 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160008 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_release>>  =>  (LDFMAXNMLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLS),
     /* 160011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160015 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160021 */     GIR_RootConstrainSelectedInstOperands,
     /* 160022 */     // GIR_Coverage, 7464,
     /* 160022 */     GIR_EraseRootFromParent_Done,
     /* 160023 */   // Label 2885: @160023
     /* 160023 */   GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(160065), // Rule ID 7465 //
     /* 160028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160031 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 160034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160038 */     // MIs[0] Rn
     /* 160038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160046 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160050 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_acq_rel>>  =>  (LDFMAXNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALS),
     /* 160053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160055 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160057 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160063 */     GIR_RootConstrainSelectedInstOperands,
     /* 160064 */     // GIR_Coverage, 7465,
     /* 160064 */     GIR_EraseRootFromParent_Done,
     /* 160065 */   // Label 2886: @160065
     /* 160065 */   GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(160107), // Rule ID 7466 //
     /* 160070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160073 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 160076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160080 */     // MIs[0] Rn
     /* 160080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160084 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160088 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160092 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_seq_cst>>  =>  (LDFMAXNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALS),
     /* 160095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160097 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160099 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160105 */     GIR_RootConstrainSelectedInstOperands,
     /* 160106 */     // GIR_Coverage, 7466,
     /* 160106 */     GIR_EraseRootFromParent_Done,
     /* 160107 */   // Label 2887: @160107
     /* 160107 */   GIM_Reject,
     /* 160108 */ // Label 2882: @160108
     /* 160108 */ GIM_Reject,
     /* 160109 */ // Label 2874: @160109
     /* 160109 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(160335),
     /* 160114 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 160117 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160124 */   GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(160166), // Rule ID 7467 //
     /* 160129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160132 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 160135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160139 */     // MIs[0] Rn
     /* 160139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160151 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_monotonic>>  =>  (LDFMAXNMD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMD),
     /* 160154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160158 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160164 */     GIR_RootConstrainSelectedInstOperands,
     /* 160165 */     // GIR_Coverage, 7467,
     /* 160165 */     GIR_EraseRootFromParent_Done,
     /* 160166 */   // Label 2889: @160166
     /* 160166 */   GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(160208), // Rule ID 7468 //
     /* 160171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160174 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 160177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160181 */     // MIs[0] Rn
     /* 160181 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160185 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160189 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160193 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_acquire>>  =>  (LDFMAXNMAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAD),
     /* 160196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160200 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160206 */     GIR_RootConstrainSelectedInstOperands,
     /* 160207 */     // GIR_Coverage, 7468,
     /* 160207 */     GIR_EraseRootFromParent_Done,
     /* 160208 */   // Label 2890: @160208
     /* 160208 */   GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(160250), // Rule ID 7469 //
     /* 160213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160216 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160223 */     // MIs[0] Rn
     /* 160223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160227 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160235 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_release>>  =>  (LDFMAXNMLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLD),
     /* 160238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160248 */     GIR_RootConstrainSelectedInstOperands,
     /* 160249 */     // GIR_Coverage, 7469,
     /* 160249 */     GIR_EraseRootFromParent_Done,
     /* 160250 */   // Label 2891: @160250
     /* 160250 */   GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(160292), // Rule ID 7470 //
     /* 160255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160258 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 160261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160265 */     // MIs[0] Rn
     /* 160265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160269 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160273 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160277 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_acq_rel>>  =>  (LDFMAXNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALD),
     /* 160280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160282 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160284 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160290 */     GIR_RootConstrainSelectedInstOperands,
     /* 160291 */     // GIR_Coverage, 7470,
     /* 160291 */     GIR_EraseRootFromParent_Done,
     /* 160292 */   // Label 2892: @160292
     /* 160292 */   GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(160334), // Rule ID 7471 //
     /* 160297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160300 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 160303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160307 */     // MIs[0] Rn
     /* 160307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160311 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160319 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_seq_cst>>  =>  (LDFMAXNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALD),
     /* 160322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160326 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160328 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160332 */     GIR_RootConstrainSelectedInstOperands,
     /* 160333 */     // GIR_Coverage, 7471,
     /* 160333 */     GIR_EraseRootFromParent_Done,
     /* 160334 */   // Label 2893: @160334
     /* 160334 */   GIM_Reject,
     /* 160335 */ // Label 2888: @160335
     /* 160335 */ GIM_Reject,
     /* 160336 */ // Label 2875: @160336
     /* 160336 */ GIM_Reject,
     /* 160337 */ // Label 33: @160337
     /* 160337 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2897*/ GIMT_Encode4(161041),
     /* 160348 */ /*GILLT_s16*//*Label 2894*/ GIMT_Encode4(160360),
     /* 160352 */ /*GILLT_s32*//*Label 2895*/ GIMT_Encode4(160587),
     /* 160356 */ /*GILLT_s64*//*Label 2896*/ GIMT_Encode4(160814),
     /* 160360 */ // Label 2894: @160360
     /* 160360 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(160586),
     /* 160365 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 160368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 160375 */   GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(160417), // Rule ID 7472 //
     /* 160380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160383 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 160386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160390 */     // MIs[0] Rn
     /* 160390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160394 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160398 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160402 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_monotonic>>  =>  (LDFMINNMH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMH),
     /* 160405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160409 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160415 */     GIR_RootConstrainSelectedInstOperands,
     /* 160416 */     // GIR_Coverage, 7472,
     /* 160416 */     GIR_EraseRootFromParent_Done,
     /* 160417 */   // Label 2899: @160417
     /* 160417 */   GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(160459), // Rule ID 7473 //
     /* 160422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160425 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 160428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160432 */     // MIs[0] Rn
     /* 160432 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160436 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160444 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_acquire>>  =>  (LDFMINNMAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAH),
     /* 160447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160451 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160457 */     GIR_RootConstrainSelectedInstOperands,
     /* 160458 */     // GIR_Coverage, 7473,
     /* 160458 */     GIR_EraseRootFromParent_Done,
     /* 160459 */   // Label 2900: @160459
     /* 160459 */   GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(160501), // Rule ID 7474 //
     /* 160464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160467 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160474 */     // MIs[0] Rn
     /* 160474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160486 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_release>>  =>  (LDFMINNMLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLH),
     /* 160489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160491 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160499 */     GIR_RootConstrainSelectedInstOperands,
     /* 160500 */     // GIR_Coverage, 7474,
     /* 160500 */     GIR_EraseRootFromParent_Done,
     /* 160501 */   // Label 2901: @160501
     /* 160501 */   GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(160543), // Rule ID 7475 //
     /* 160506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160509 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 160512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160516 */     // MIs[0] Rn
     /* 160516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160520 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160524 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160528 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_acq_rel>>  =>  (LDFMINNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALH),
     /* 160531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160541 */     GIR_RootConstrainSelectedInstOperands,
     /* 160542 */     // GIR_Coverage, 7475,
     /* 160542 */     GIR_EraseRootFromParent_Done,
     /* 160543 */   // Label 2902: @160543
     /* 160543 */   GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(160585), // Rule ID 7476 //
     /* 160548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160551 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 160554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160558 */     // MIs[0] Rn
     /* 160558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160566 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160570 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_seq_cst>>  =>  (LDFMINNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALH),
     /* 160573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160577 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160583 */     GIR_RootConstrainSelectedInstOperands,
     /* 160584 */     // GIR_Coverage, 7476,
     /* 160584 */     GIR_EraseRootFromParent_Done,
     /* 160585 */   // Label 2903: @160585
     /* 160585 */   GIM_Reject,
     /* 160586 */ // Label 2898: @160586
     /* 160586 */ GIM_Reject,
     /* 160587 */ // Label 2895: @160587
     /* 160587 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(160813),
     /* 160592 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 160595 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 160602 */   GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(160644), // Rule ID 7477 //
     /* 160607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160610 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 160613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160617 */     // MIs[0] Rn
     /* 160617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160621 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160629 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_monotonic>>  =>  (LDFMINNMS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMS),
     /* 160632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160636 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160642 */     GIR_RootConstrainSelectedInstOperands,
     /* 160643 */     // GIR_Coverage, 7477,
     /* 160643 */     GIR_EraseRootFromParent_Done,
     /* 160644 */   // Label 2905: @160644
     /* 160644 */   GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(160686), // Rule ID 7478 //
     /* 160649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160652 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 160655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160659 */     // MIs[0] Rn
     /* 160659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160663 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160667 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160671 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_acquire>>  =>  (LDFMINNMAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAS),
     /* 160674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160678 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160684 */     GIR_RootConstrainSelectedInstOperands,
     /* 160685 */     // GIR_Coverage, 7478,
     /* 160685 */     GIR_EraseRootFromParent_Done,
     /* 160686 */   // Label 2906: @160686
     /* 160686 */   GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(160728), // Rule ID 7479 //
     /* 160691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160694 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160701 */     // MIs[0] Rn
     /* 160701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160705 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160709 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160713 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_release>>  =>  (LDFMINNMLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLS),
     /* 160716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160720 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160726 */     GIR_RootConstrainSelectedInstOperands,
     /* 160727 */     // GIR_Coverage, 7479,
     /* 160727 */     GIR_EraseRootFromParent_Done,
     /* 160728 */   // Label 2907: @160728
     /* 160728 */   GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(160770), // Rule ID 7480 //
     /* 160733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160736 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 160739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160743 */     // MIs[0] Rn
     /* 160743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160747 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160751 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160755 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_acq_rel>>  =>  (LDFMINNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALS),
     /* 160758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160760 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160762 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160768 */     GIR_RootConstrainSelectedInstOperands,
     /* 160769 */     // GIR_Coverage, 7480,
     /* 160769 */     GIR_EraseRootFromParent_Done,
     /* 160770 */   // Label 2908: @160770
     /* 160770 */   GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(160812), // Rule ID 7481 //
     /* 160775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160778 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 160781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160785 */     // MIs[0] Rn
     /* 160785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160789 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160797 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_seq_cst>>  =>  (LDFMINNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALS),
     /* 160800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160804 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160810 */     GIR_RootConstrainSelectedInstOperands,
     /* 160811 */     // GIR_Coverage, 7481,
     /* 160811 */     GIR_EraseRootFromParent_Done,
     /* 160812 */   // Label 2909: @160812
     /* 160812 */   GIM_Reject,
     /* 160813 */ // Label 2904: @160813
     /* 160813 */ GIM_Reject,
     /* 160814 */ // Label 2896: @160814
     /* 160814 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(161040),
     /* 160819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 160822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160829 */   GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(160871), // Rule ID 7482 //
     /* 160834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160837 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 160840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160844 */     // MIs[0] Rn
     /* 160844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160848 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160852 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160856 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_monotonic>>  =>  (LDFMINNMD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMD),
     /* 160859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160863 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160865 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160869 */     GIR_RootConstrainSelectedInstOperands,
     /* 160870 */     // GIR_Coverage, 7482,
     /* 160870 */     GIR_EraseRootFromParent_Done,
     /* 160871 */   // Label 2911: @160871
     /* 160871 */   GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(160913), // Rule ID 7483 //
     /* 160876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160879 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 160882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160886 */     // MIs[0] Rn
     /* 160886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160890 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160894 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160898 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_acquire>>  =>  (LDFMINNMAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAD),
     /* 160901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160905 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160911 */     GIR_RootConstrainSelectedInstOperands,
     /* 160912 */     // GIR_Coverage, 7483,
     /* 160912 */     GIR_EraseRootFromParent_Done,
     /* 160913 */   // Label 2912: @160913
     /* 160913 */   GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(160955), // Rule ID 7484 //
     /* 160918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160921 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160928 */     // MIs[0] Rn
     /* 160928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160940 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_release>>  =>  (LDFMINNMLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLD),
     /* 160943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160945 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160947 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160953 */     GIR_RootConstrainSelectedInstOperands,
     /* 160954 */     // GIR_Coverage, 7484,
     /* 160954 */     GIR_EraseRootFromParent_Done,
     /* 160955 */   // Label 2913: @160955
     /* 160955 */   GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(160997), // Rule ID 7485 //
     /* 160960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 160963 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 160966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160970 */     // MIs[0] Rn
     /* 160970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 160974 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160978 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160982 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_acq_rel>>  =>  (LDFMINNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 160982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALD),
     /* 160985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 160987 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 160989 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 160991 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160995 */     GIR_RootConstrainSelectedInstOperands,
     /* 160996 */     // GIR_Coverage, 7485,
     /* 160996 */     GIR_EraseRootFromParent_Done,
     /* 160997 */   // Label 2914: @160997
     /* 160997 */   GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(161039), // Rule ID 7486 //
     /* 161002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161005 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 161008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161012 */     // MIs[0] Rn
     /* 161012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161016 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161024 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_seq_cst>>  =>  (LDFMINNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALD),
     /* 161027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161029 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161031 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161033 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161037 */     GIR_RootConstrainSelectedInstOperands,
     /* 161038 */     // GIR_Coverage, 7486,
     /* 161038 */     GIR_EraseRootFromParent_Done,
     /* 161039 */   // Label 2915: @161039
     /* 161039 */   GIM_Reject,
     /* 161040 */ // Label 2910: @161040
     /* 161040 */ GIM_Reject,
     /* 161041 */ // Label 2897: @161041
     /* 161041 */ GIM_Reject,
     /* 161042 */ // Label 34: @161042
     /* 161042 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2919*/ GIMT_Encode4(161746),
     /* 161053 */ /*GILLT_s16*//*Label 2916*/ GIMT_Encode4(161065),
     /* 161057 */ /*GILLT_s32*//*Label 2917*/ GIMT_Encode4(161292),
     /* 161061 */ /*GILLT_s64*//*Label 2918*/ GIMT_Encode4(161519),
     /* 161065 */ // Label 2916: @161065
     /* 161065 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(161291),
     /* 161070 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 161073 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 161080 */   GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(161122), // Rule ID 7487 //
     /* 161085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161088 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 161091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161095 */     // MIs[0] Rn
     /* 161095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161099 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161103 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161107 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_monotonic>>  =>  (LDFMAXH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXH),
     /* 161110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161112 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161114 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161120 */     GIR_RootConstrainSelectedInstOperands,
     /* 161121 */     // GIR_Coverage, 7487,
     /* 161121 */     GIR_EraseRootFromParent_Done,
     /* 161122 */   // Label 2921: @161122
     /* 161122 */   GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(161164), // Rule ID 7488 //
     /* 161127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161130 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 161133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161137 */     // MIs[0] Rn
     /* 161137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161141 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161149 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_acquire>>  =>  (LDFMAXAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAH),
     /* 161152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161156 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161162 */     GIR_RootConstrainSelectedInstOperands,
     /* 161163 */     // GIR_Coverage, 7488,
     /* 161163 */     GIR_EraseRootFromParent_Done,
     /* 161164 */   // Label 2922: @161164
     /* 161164 */   GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(161206), // Rule ID 7489 //
     /* 161169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161172 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161179 */     // MIs[0] Rn
     /* 161179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161183 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161187 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161191 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_release>>  =>  (LDFMAXLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLH),
     /* 161194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161198 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161204 */     GIR_RootConstrainSelectedInstOperands,
     /* 161205 */     // GIR_Coverage, 7489,
     /* 161205 */     GIR_EraseRootFromParent_Done,
     /* 161206 */   // Label 2923: @161206
     /* 161206 */   GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(161248), // Rule ID 7490 //
     /* 161211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161214 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 161217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161221 */     // MIs[0] Rn
     /* 161221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161233 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_acq_rel>>  =>  (LDFMAXALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALH),
     /* 161236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161240 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161246 */     GIR_RootConstrainSelectedInstOperands,
     /* 161247 */     // GIR_Coverage, 7490,
     /* 161247 */     GIR_EraseRootFromParent_Done,
     /* 161248 */   // Label 2924: @161248
     /* 161248 */   GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(161290), // Rule ID 7491 //
     /* 161253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161256 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 161259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161263 */     // MIs[0] Rn
     /* 161263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161267 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161275 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_seq_cst>>  =>  (LDFMAXALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALH),
     /* 161278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161282 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161288 */     GIR_RootConstrainSelectedInstOperands,
     /* 161289 */     // GIR_Coverage, 7491,
     /* 161289 */     GIR_EraseRootFromParent_Done,
     /* 161290 */   // Label 2925: @161290
     /* 161290 */   GIM_Reject,
     /* 161291 */ // Label 2920: @161291
     /* 161291 */ GIM_Reject,
     /* 161292 */ // Label 2917: @161292
     /* 161292 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(161518),
     /* 161297 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 161300 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 161307 */   GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(161349), // Rule ID 7492 //
     /* 161312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161315 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 161318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161322 */     // MIs[0] Rn
     /* 161322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161326 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161334 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_monotonic>>  =>  (LDFMAXS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXS),
     /* 161337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161341 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161343 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161347 */     GIR_RootConstrainSelectedInstOperands,
     /* 161348 */     // GIR_Coverage, 7492,
     /* 161348 */     GIR_EraseRootFromParent_Done,
     /* 161349 */   // Label 2927: @161349
     /* 161349 */   GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(161391), // Rule ID 7493 //
     /* 161354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161357 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 161360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161364 */     // MIs[0] Rn
     /* 161364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161368 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161376 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_acquire>>  =>  (LDFMAXAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAS),
     /* 161379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161381 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161383 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161389 */     GIR_RootConstrainSelectedInstOperands,
     /* 161390 */     // GIR_Coverage, 7493,
     /* 161390 */     GIR_EraseRootFromParent_Done,
     /* 161391 */   // Label 2928: @161391
     /* 161391 */   GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(161433), // Rule ID 7494 //
     /* 161396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161399 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161406 */     // MIs[0] Rn
     /* 161406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161418 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_release>>  =>  (LDFMAXLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLS),
     /* 161421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161425 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161431 */     GIR_RootConstrainSelectedInstOperands,
     /* 161432 */     // GIR_Coverage, 7494,
     /* 161432 */     GIR_EraseRootFromParent_Done,
     /* 161433 */   // Label 2929: @161433
     /* 161433 */   GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(161475), // Rule ID 7495 //
     /* 161438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161441 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 161444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161448 */     // MIs[0] Rn
     /* 161448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161452 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161460 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_acq_rel>>  =>  (LDFMAXALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALS),
     /* 161463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161465 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161467 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161473 */     GIR_RootConstrainSelectedInstOperands,
     /* 161474 */     // GIR_Coverage, 7495,
     /* 161474 */     GIR_EraseRootFromParent_Done,
     /* 161475 */   // Label 2930: @161475
     /* 161475 */   GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(161517), // Rule ID 7496 //
     /* 161480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161483 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 161486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161490 */     // MIs[0] Rn
     /* 161490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161494 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 161502 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_seq_cst>>  =>  (LDFMAXALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALS),
     /* 161505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161509 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161515 */     GIR_RootConstrainSelectedInstOperands,
     /* 161516 */     // GIR_Coverage, 7496,
     /* 161516 */     GIR_EraseRootFromParent_Done,
     /* 161517 */   // Label 2931: @161517
     /* 161517 */   GIM_Reject,
     /* 161518 */ // Label 2926: @161518
     /* 161518 */ GIM_Reject,
     /* 161519 */ // Label 2918: @161519
     /* 161519 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(161745),
     /* 161524 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 161527 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161534 */   GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(161576), // Rule ID 7497 //
     /* 161539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161542 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 161545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161549 */     // MIs[0] Rn
     /* 161549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161553 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161557 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161561 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_monotonic>>  =>  (LDFMAXD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXD),
     /* 161564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161566 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161568 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161574 */     GIR_RootConstrainSelectedInstOperands,
     /* 161575 */     // GIR_Coverage, 7497,
     /* 161575 */     GIR_EraseRootFromParent_Done,
     /* 161576 */   // Label 2933: @161576
     /* 161576 */   GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(161618), // Rule ID 7498 //
     /* 161581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161584 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 161587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161591 */     // MIs[0] Rn
     /* 161591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161595 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161603 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_acquire>>  =>  (LDFMAXAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAD),
     /* 161606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161610 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161612 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161616 */     GIR_RootConstrainSelectedInstOperands,
     /* 161617 */     // GIR_Coverage, 7498,
     /* 161617 */     GIR_EraseRootFromParent_Done,
     /* 161618 */   // Label 2934: @161618
     /* 161618 */   GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(161660), // Rule ID 7499 //
     /* 161623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161626 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161633 */     // MIs[0] Rn
     /* 161633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161637 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161641 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161645 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_release>>  =>  (LDFMAXLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLD),
     /* 161648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161650 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161652 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161654 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161658 */     GIR_RootConstrainSelectedInstOperands,
     /* 161659 */     // GIR_Coverage, 7499,
     /* 161659 */     GIR_EraseRootFromParent_Done,
     /* 161660 */   // Label 2935: @161660
     /* 161660 */   GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(161702), // Rule ID 7500 //
     /* 161665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161668 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 161671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161675 */     // MIs[0] Rn
     /* 161675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161679 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161687 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_acq_rel>>  =>  (LDFMAXALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALD),
     /* 161690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161694 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161700 */     GIR_RootConstrainSelectedInstOperands,
     /* 161701 */     // GIR_Coverage, 7500,
     /* 161701 */     GIR_EraseRootFromParent_Done,
     /* 161702 */   // Label 2936: @161702
     /* 161702 */   GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(161744), // Rule ID 7501 //
     /* 161707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161710 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 161713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161717 */     // MIs[0] Rn
     /* 161717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161721 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161725 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161729 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_seq_cst>>  =>  (LDFMAXALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALD),
     /* 161732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161734 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161736 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161742 */     GIR_RootConstrainSelectedInstOperands,
     /* 161743 */     // GIR_Coverage, 7501,
     /* 161743 */     GIR_EraseRootFromParent_Done,
     /* 161744 */   // Label 2937: @161744
     /* 161744 */   GIM_Reject,
     /* 161745 */ // Label 2932: @161745
     /* 161745 */ GIM_Reject,
     /* 161746 */ // Label 2919: @161746
     /* 161746 */ GIM_Reject,
     /* 161747 */ // Label 35: @161747
     /* 161747 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2941*/ GIMT_Encode4(162451),
     /* 161758 */ /*GILLT_s16*//*Label 2938*/ GIMT_Encode4(161770),
     /* 161762 */ /*GILLT_s32*//*Label 2939*/ GIMT_Encode4(161997),
     /* 161766 */ /*GILLT_s64*//*Label 2940*/ GIMT_Encode4(162224),
     /* 161770 */ // Label 2938: @161770
     /* 161770 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(161996),
     /* 161775 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 161778 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 161785 */   GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(161827), // Rule ID 7502 //
     /* 161790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161793 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 161796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161800 */     // MIs[0] Rn
     /* 161800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161804 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161808 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161812 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_monotonic>>  =>  (LDFMINH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINH),
     /* 161815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161817 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161819 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161825 */     GIR_RootConstrainSelectedInstOperands,
     /* 161826 */     // GIR_Coverage, 7502,
     /* 161826 */     GIR_EraseRootFromParent_Done,
     /* 161827 */   // Label 2943: @161827
     /* 161827 */   GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(161869), // Rule ID 7503 //
     /* 161832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161835 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 161838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161842 */     // MIs[0] Rn
     /* 161842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161846 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161854 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_acquire>>  =>  (LDFMINAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAH),
     /* 161857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161861 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161867 */     GIR_RootConstrainSelectedInstOperands,
     /* 161868 */     // GIR_Coverage, 7503,
     /* 161868 */     GIR_EraseRootFromParent_Done,
     /* 161869 */   // Label 2944: @161869
     /* 161869 */   GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(161911), // Rule ID 7504 //
     /* 161874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161877 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161884 */     // MIs[0] Rn
     /* 161884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161888 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161892 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161896 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_release>>  =>  (LDFMINLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLH),
     /* 161899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161903 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161909 */     GIR_RootConstrainSelectedInstOperands,
     /* 161910 */     // GIR_Coverage, 7504,
     /* 161910 */     GIR_EraseRootFromParent_Done,
     /* 161911 */   // Label 2945: @161911
     /* 161911 */   GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(161953), // Rule ID 7505 //
     /* 161916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161919 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 161922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161926 */     // MIs[0] Rn
     /* 161926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161930 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161934 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161938 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_acq_rel>>  =>  (LDFMINALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALH),
     /* 161941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161945 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161951 */     GIR_RootConstrainSelectedInstOperands,
     /* 161952 */     // GIR_Coverage, 7505,
     /* 161952 */     GIR_EraseRootFromParent_Done,
     /* 161953 */   // Label 2946: @161953
     /* 161953 */   GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(161995), // Rule ID 7506 //
     /* 161958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 161961 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 161964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161968 */     // MIs[0] Rn
     /* 161968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161972 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 161980 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_seq_cst>>  =>  (LDFMINALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 161980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALH),
     /* 161983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 161985 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 161987 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161993 */     GIR_RootConstrainSelectedInstOperands,
     /* 161994 */     // GIR_Coverage, 7506,
     /* 161994 */     GIR_EraseRootFromParent_Done,
     /* 161995 */   // Label 2947: @161995
     /* 161995 */   GIM_Reject,
     /* 161996 */ // Label 2942: @161996
     /* 161996 */ GIM_Reject,
     /* 161997 */ // Label 2939: @161997
     /* 161997 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(162223),
     /* 162002 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 162005 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 162012 */   GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(162054), // Rule ID 7507 //
     /* 162017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162020 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 162023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162027 */     // MIs[0] Rn
     /* 162027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162031 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162039 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_monotonic>>  =>  (LDFMINS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINS),
     /* 162042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162046 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162052 */     GIR_RootConstrainSelectedInstOperands,
     /* 162053 */     // GIR_Coverage, 7507,
     /* 162053 */     GIR_EraseRootFromParent_Done,
     /* 162054 */   // Label 2949: @162054
     /* 162054 */   GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(162096), // Rule ID 7508 //
     /* 162059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162062 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 162065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162069 */     // MIs[0] Rn
     /* 162069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162073 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162077 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162081 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_acquire>>  =>  (LDFMINAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAS),
     /* 162084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162088 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162094 */     GIR_RootConstrainSelectedInstOperands,
     /* 162095 */     // GIR_Coverage, 7508,
     /* 162095 */     GIR_EraseRootFromParent_Done,
     /* 162096 */   // Label 2950: @162096
     /* 162096 */   GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(162138), // Rule ID 7509 //
     /* 162101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162104 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 162107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162111 */     // MIs[0] Rn
     /* 162111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162115 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162123 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_release>>  =>  (LDFMINLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLS),
     /* 162126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162130 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162136 */     GIR_RootConstrainSelectedInstOperands,
     /* 162137 */     // GIR_Coverage, 7509,
     /* 162137 */     GIR_EraseRootFromParent_Done,
     /* 162138 */   // Label 2951: @162138
     /* 162138 */   GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(162180), // Rule ID 7510 //
     /* 162143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162146 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 162149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162153 */     // MIs[0] Rn
     /* 162153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162157 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162165 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_acq_rel>>  =>  (LDFMINALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALS),
     /* 162168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162170 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162172 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162178 */     GIR_RootConstrainSelectedInstOperands,
     /* 162179 */     // GIR_Coverage, 7510,
     /* 162179 */     GIR_EraseRootFromParent_Done,
     /* 162180 */   // Label 2952: @162180
     /* 162180 */   GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(162222), // Rule ID 7511 //
     /* 162185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162188 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 162191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162195 */     // MIs[0] Rn
     /* 162195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162199 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 162207 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_seq_cst>>  =>  (LDFMINALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALS),
     /* 162210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162214 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162220 */     GIR_RootConstrainSelectedInstOperands,
     /* 162221 */     // GIR_Coverage, 7511,
     /* 162221 */     GIR_EraseRootFromParent_Done,
     /* 162222 */   // Label 2953: @162222
     /* 162222 */   GIM_Reject,
     /* 162223 */ // Label 2948: @162223
     /* 162223 */ GIM_Reject,
     /* 162224 */ // Label 2940: @162224
     /* 162224 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(162450),
     /* 162229 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 162232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 162239 */   GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(162281), // Rule ID 7512 //
     /* 162244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162247 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 162250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162254 */     // MIs[0] Rn
     /* 162254 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162266 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_monotonic>>  =>  (LDFMIND:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMIND),
     /* 162269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162271 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162273 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162279 */     GIR_RootConstrainSelectedInstOperands,
     /* 162280 */     // GIR_Coverage, 7512,
     /* 162280 */     GIR_EraseRootFromParent_Done,
     /* 162281 */   // Label 2955: @162281
     /* 162281 */   GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(162323), // Rule ID 7513 //
     /* 162286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162289 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 162292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162296 */     // MIs[0] Rn
     /* 162296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162300 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162308 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_acquire>>  =>  (LDFMINAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAD),
     /* 162311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162315 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162321 */     GIR_RootConstrainSelectedInstOperands,
     /* 162322 */     // GIR_Coverage, 7513,
     /* 162322 */     GIR_EraseRootFromParent_Done,
     /* 162323 */   // Label 2956: @162323
     /* 162323 */   GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(162365), // Rule ID 7514 //
     /* 162328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162331 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 162334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162338 */     // MIs[0] Rn
     /* 162338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162342 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162346 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162350 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_release>>  =>  (LDFMINLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLD),
     /* 162353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162357 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162363 */     GIR_RootConstrainSelectedInstOperands,
     /* 162364 */     // GIR_Coverage, 7514,
     /* 162364 */     GIR_EraseRootFromParent_Done,
     /* 162365 */   // Label 2957: @162365
     /* 162365 */   GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(162407), // Rule ID 7515 //
     /* 162370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162373 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 162376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162380 */     // MIs[0] Rn
     /* 162380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162384 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162392 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_acq_rel>>  =>  (LDFMINALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALD),
     /* 162395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162399 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162405 */     GIR_RootConstrainSelectedInstOperands,
     /* 162406 */     // GIR_Coverage, 7515,
     /* 162406 */     GIR_EraseRootFromParent_Done,
     /* 162407 */   // Label 2958: @162407
     /* 162407 */   GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(162449), // Rule ID 7516 //
     /* 162412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 162415 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 162418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162422 */     // MIs[0] Rn
     /* 162422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162434 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_seq_cst>>  =>  (LDFMINALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 162434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALD),
     /* 162437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 162439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 162441 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 162443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162447 */     GIR_RootConstrainSelectedInstOperands,
     /* 162448 */     // GIR_Coverage, 7516,
     /* 162448 */     GIR_EraseRootFromParent_Done,
     /* 162449 */   // Label 2959: @162449
     /* 162449 */   GIM_Reject,
     /* 162450 */ // Label 2954: @162450
     /* 162450 */ GIM_Reject,
     /* 162451 */ // Label 2941: @162451
     /* 162451 */ GIM_Reject,
     /* 162452 */ // Label 36: @162452
     /* 162452 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(162479), // Rule ID 7102 //
     /* 162457 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 162460 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 4,
     /* 162464 */   // MIs[0] Operand 1
     /* 162464 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 162467 */   // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (DMB 9:{ *:[i32] })
     /* 162467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 162470 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 162473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162477 */   GIR_RootConstrainSelectedInstOperands,
     /* 162478 */   // GIR_Coverage, 7102,
     /* 162478 */   GIR_EraseRootFromParent_Done,
     /* 162479 */ // Label 2960: @162479
     /* 162479 */ GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(162502), // Rule ID 7103 //
     /* 162484 */   // MIs[0] Operand 0
     /* 162484 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 162487 */   // MIs[0] Operand 1
     /* 162487 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 162490 */   // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] }))  =>  (DMB 11:{ *:[i32] })
     /* 162490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 162493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
     /* 162496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162500 */   GIR_RootConstrainSelectedInstOperands,
     /* 162501 */   // GIR_Coverage, 7103,
     /* 162501 */   GIR_EraseRootFromParent_Done,
     /* 162502 */ // Label 2961: @162502
     /* 162502 */ GIM_Reject,
     /* 162503 */ // Label 37: @162503
     /* 162503 */ GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(175030),
     /* 162508 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 162511 */   GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(162602), // Rule ID 6575 //
     /* 162516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
     /* 162519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
     /* 162524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 162527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 162530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 162538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 162542 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 162545 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
     /* 162550 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 162554 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 162558 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162568 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 162570 */     // (intrinsic_wo_chain:{ *:[v16i8] } 524:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 522:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
     /* 162570 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 162573 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
     /* 162577 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 162582 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /* 162586 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
     /* 162590 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 162592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrrTied),
     /* 162595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 162600 */     GIR_RootConstrainSelectedInstOperands,
     /* 162601 */     // GIR_Coverage, 6575,
     /* 162601 */     GIR_EraseRootFromParent_Done,
     /* 162602 */   // Label 2963: @162602
     /* 162602 */   GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(162693), // Rule ID 6576 //
     /* 162607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
     /* 162610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
     /* 162615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 162618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 162621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 162629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 162633 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 162636 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
     /* 162641 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 162645 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 162649 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162654 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162659 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 162661 */     // (intrinsic_wo_chain:{ *:[v16i8] } 523:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 521:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
     /* 162661 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 162664 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
     /* 162668 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 162673 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /* 162677 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
     /* 162681 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 162683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrrTied),
     /* 162686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162688 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 162691 */     GIR_RootConstrainSelectedInstOperands,
     /* 162692 */     // GIR_Coverage, 6576,
     /* 162692 */     GIR_EraseRootFromParent_Done,
     /* 162693 */   // Label 2964: @162693
     /* 162693 */   GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(162754), // Rule ID 4967 //
     /* 162698 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvthf2fp),
     /* 162703 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 162706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 162709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162713 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 162717 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 162721 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 162725 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162730 */     // MIs[1] Operand 2
     /* 162730 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 162741 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 162743 */     // (intrinsic_wo_chain:{ *:[v4f32] } 777:{ *:[iPTR] }, (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }))  =>  (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8i16] }:$Rn)
     /* 162743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 162746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 162752 */     GIR_RootConstrainSelectedInstOperands,
     /* 162753 */     // GIR_Coverage, 4967,
     /* 162753 */     GIR_EraseRootFromParent_Done,
     /* 162754 */   // Label 2965: @162754
     /* 162754 */   GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(162794), // Rule ID 2651 //
     /* 162759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 162762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /* 162767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 162770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 162774 */     // MIs[0] pattern
     /* 162774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 162777 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 162782 */     // (intrinsic_wo_chain:{ *:[i64] } 1342:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 162782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTB_XPiI),
     /* 162785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162787 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 162789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 162792 */     GIR_RootConstrainSelectedInstOperands,
     /* 162793 */     // GIR_Coverage, 2651,
     /* 162793 */     GIR_EraseRootFromParent_Done,
     /* 162794 */   // Label 2966: @162794
     /* 162794 */   GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(162834), // Rule ID 10048 //
     /* 162799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 162802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /* 162807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 162810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 162814 */     // MIs[0] pattern
     /* 162814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 162817 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 162822 */     // (intrinsic_wo_chain:{ *:[i64] } 1344:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 162822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTH_XPiI),
     /* 162825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162827 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 162829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 162832 */     GIR_RootConstrainSelectedInstOperands,
     /* 162833 */     // GIR_Coverage, 10048,
     /* 162833 */     GIR_EraseRootFromParent_Done,
     /* 162834 */   // Label 2967: @162834
     /* 162834 */   GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(162874), // Rule ID 10051 //
     /* 162839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 162842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /* 162847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 162850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 162854 */     // MIs[0] pattern
     /* 162854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 162857 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 162862 */     // (intrinsic_wo_chain:{ *:[i64] } 1350:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 162862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTW_XPiI),
     /* 162865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162867 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 162869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 162872 */     GIR_RootConstrainSelectedInstOperands,
     /* 162873 */     // GIR_Coverage, 10051,
     /* 162873 */     GIR_EraseRootFromParent_Done,
     /* 162874 */   // Label 2968: @162874
     /* 162874 */   GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(162914), // Rule ID 10054 //
     /* 162879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 162882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /* 162887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 162890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 162894 */     // MIs[0] pattern
     /* 162894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 162897 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 162902 */     // (intrinsic_wo_chain:{ *:[i64] } 1343:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 162902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTD_XPiI),
     /* 162905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162907 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 162909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 162912 */     GIR_RootConstrainSelectedInstOperands,
     /* 162913 */     // GIR_Coverage, 10054,
     /* 162913 */     GIR_EraseRootFromParent_Done,
     /* 162914 */   // Label 2969: @162914
     /* 162914 */   GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(162953), // Rule ID 66 //
     /* 162919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasJS),
     /* 162922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_fjcvtzs),
     /* 162927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 162930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 162933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 162937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162941 */     // (intrinsic_wo_chain:{ *:[i32] } 556:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FJCVTZS:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 162941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FJCVTZS),
     /* 162944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 162948 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 162951 */     GIR_RootConstrainSelectedInstOperands,
     /* 162952 */     // GIR_Coverage, 66,
     /* 162952 */     GIR_EraseRootFromParent_Done,
     /* 162953 */   // Label 2970: @162953
     /* 162953 */   GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(162989), // Rule ID 350 //
     /* 162958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 162961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 162966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 162969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 162972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 162976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 162980 */     // (intrinsic_wo_chain:{ *:[i32] } 593:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 162980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
     /* 162983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 162985 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 162987 */     GIR_RootConstrainSelectedInstOperands,
     /* 162988 */     // GIR_Coverage, 350,
     /* 162988 */     GIR_EraseRootFromParent_Done,
     /* 162989 */   // Label 2971: @162989
     /* 162989 */   GIM_Try, /*On fail goto*//*Label 2972*/ GIMT_Encode4(163025), // Rule ID 351 //
     /* 162994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 162997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 163002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163012 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163016 */     // (intrinsic_wo_chain:{ *:[i64] } 593:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 163016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 163019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163021 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163023 */     GIR_RootConstrainSelectedInstOperands,
     /* 163024 */     // GIR_Coverage, 351,
     /* 163024 */     GIR_EraseRootFromParent_Done,
     /* 163025 */   // Label 2972: @163025
     /* 163025 */   GIM_Try, /*On fail goto*//*Label 2973*/ GIMT_Encode4(163061), // Rule ID 352 //
     /* 163030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 163038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163048 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163052 */     // (intrinsic_wo_chain:{ *:[i32] } 593:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 163052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 163055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163059 */     GIR_RootConstrainSelectedInstOperands,
     /* 163060 */     // GIR_Coverage, 352,
     /* 163060 */     GIR_EraseRootFromParent_Done,
     /* 163061 */   // Label 2973: @163061
     /* 163061 */   GIM_Try, /*On fail goto*//*Label 2974*/ GIMT_Encode4(163097), // Rule ID 353 //
     /* 163066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 163074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163088 */     // (intrinsic_wo_chain:{ *:[i64] } 593:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 163088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 163091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163095 */     GIR_RootConstrainSelectedInstOperands,
     /* 163096 */     // GIR_Coverage, 353,
     /* 163096 */     GIR_EraseRootFromParent_Done,
     /* 163097 */   // Label 2974: @163097
     /* 163097 */   GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(163133), // Rule ID 354 //
     /* 163102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 163110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163124 */     // (intrinsic_wo_chain:{ *:[i32] } 593:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 163124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 163127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163131 */     GIR_RootConstrainSelectedInstOperands,
     /* 163132 */     // GIR_Coverage, 354,
     /* 163132 */     GIR_EraseRootFromParent_Done,
     /* 163133 */   // Label 2975: @163133
     /* 163133 */   GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(163169), // Rule ID 355 //
     /* 163138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 163146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163160 */     // (intrinsic_wo_chain:{ *:[i64] } 593:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 163160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 163163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163167 */     GIR_RootConstrainSelectedInstOperands,
     /* 163168 */     // GIR_Coverage, 355,
     /* 163168 */     GIR_EraseRootFromParent_Done,
     /* 163169 */   // Label 2976: @163169
     /* 163169 */   GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(163205), // Rule ID 356 //
     /* 163174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163192 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163196 */     // (intrinsic_wo_chain:{ *:[i32] } 594:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 163196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWHr),
     /* 163199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163201 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163203 */     GIR_RootConstrainSelectedInstOperands,
     /* 163204 */     // GIR_Coverage, 356,
     /* 163204 */     GIR_EraseRootFromParent_Done,
     /* 163205 */   // Label 2977: @163205
     /* 163205 */   GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(163241), // Rule ID 357 //
     /* 163210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163232 */     // (intrinsic_wo_chain:{ *:[i64] } 594:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 163232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXHr),
     /* 163235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163239 */     GIR_RootConstrainSelectedInstOperands,
     /* 163240 */     // GIR_Coverage, 357,
     /* 163240 */     GIR_EraseRootFromParent_Done,
     /* 163241 */   // Label 2978: @163241
     /* 163241 */   GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(163277), // Rule ID 358 //
     /* 163246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163268 */     // (intrinsic_wo_chain:{ *:[i32] } 594:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 163268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
     /* 163271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163273 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163275 */     GIR_RootConstrainSelectedInstOperands,
     /* 163276 */     // GIR_Coverage, 358,
     /* 163276 */     GIR_EraseRootFromParent_Done,
     /* 163277 */   // Label 2979: @163277
     /* 163277 */   GIM_Try, /*On fail goto*//*Label 2980*/ GIMT_Encode4(163313), // Rule ID 359 //
     /* 163282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163304 */     // (intrinsic_wo_chain:{ *:[i64] } 594:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 163304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
     /* 163307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163311 */     GIR_RootConstrainSelectedInstOperands,
     /* 163312 */     // GIR_Coverage, 359,
     /* 163312 */     GIR_EraseRootFromParent_Done,
     /* 163313 */   // Label 2980: @163313
     /* 163313 */   GIM_Try, /*On fail goto*//*Label 2981*/ GIMT_Encode4(163349), // Rule ID 360 //
     /* 163318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163336 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163340 */     // (intrinsic_wo_chain:{ *:[i32] } 594:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 163340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
     /* 163343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163347 */     GIR_RootConstrainSelectedInstOperands,
     /* 163348 */     // GIR_Coverage, 360,
     /* 163348 */     GIR_EraseRootFromParent_Done,
     /* 163349 */   // Label 2981: @163349
     /* 163349 */   GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(163385), // Rule ID 361 //
     /* 163354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 163362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163376 */     // (intrinsic_wo_chain:{ *:[i64] } 594:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 163376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
     /* 163379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163381 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163383 */     GIR_RootConstrainSelectedInstOperands,
     /* 163384 */     // GIR_Coverage, 361,
     /* 163384 */     GIR_EraseRootFromParent_Done,
     /* 163385 */   // Label 2982: @163385
     /* 163385 */   GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(163421), // Rule ID 362 //
     /* 163390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163412 */     // (intrinsic_wo_chain:{ *:[i32] } 595:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 163412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWHr),
     /* 163415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163419 */     GIR_RootConstrainSelectedInstOperands,
     /* 163420 */     // GIR_Coverage, 362,
     /* 163420 */     GIR_EraseRootFromParent_Done,
     /* 163421 */   // Label 2983: @163421
     /* 163421 */   GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(163457), // Rule ID 363 //
     /* 163426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163429 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163434 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163437 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163448 */     // (intrinsic_wo_chain:{ *:[i64] } 595:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 163448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXHr),
     /* 163451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163455 */     GIR_RootConstrainSelectedInstOperands,
     /* 163456 */     // GIR_Coverage, 363,
     /* 163456 */     GIR_EraseRootFromParent_Done,
     /* 163457 */   // Label 2984: @163457
     /* 163457 */   GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(163493), // Rule ID 364 //
     /* 163462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163480 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163484 */     // (intrinsic_wo_chain:{ *:[i32] } 595:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 163484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
     /* 163487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163491 */     GIR_RootConstrainSelectedInstOperands,
     /* 163492 */     // GIR_Coverage, 364,
     /* 163492 */     GIR_EraseRootFromParent_Done,
     /* 163493 */   // Label 2985: @163493
     /* 163493 */   GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(163529), // Rule ID 365 //
     /* 163498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163516 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163520 */     // (intrinsic_wo_chain:{ *:[i64] } 595:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 163520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
     /* 163523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163525 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163527 */     GIR_RootConstrainSelectedInstOperands,
     /* 163528 */     // GIR_Coverage, 365,
     /* 163528 */     GIR_EraseRootFromParent_Done,
     /* 163529 */   // Label 2986: @163529
     /* 163529 */   GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(163565), // Rule ID 366 //
     /* 163534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163552 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163556 */     // (intrinsic_wo_chain:{ *:[i32] } 595:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 163556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
     /* 163559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163563 */     GIR_RootConstrainSelectedInstOperands,
     /* 163564 */     // GIR_Coverage, 366,
     /* 163564 */     GIR_EraseRootFromParent_Done,
     /* 163565 */   // Label 2987: @163565
     /* 163565 */   GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(163601), // Rule ID 367 //
     /* 163570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 163578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163592 */     // (intrinsic_wo_chain:{ *:[i64] } 595:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 163592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
     /* 163595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163599 */     GIR_RootConstrainSelectedInstOperands,
     /* 163600 */     // GIR_Coverage, 367,
     /* 163600 */     GIR_EraseRootFromParent_Done,
     /* 163601 */   // Label 2988: @163601
     /* 163601 */   GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(163637), // Rule ID 368 //
     /* 163606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163628 */     // (intrinsic_wo_chain:{ *:[i32] } 596:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 163628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWHr),
     /* 163631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163635 */     GIR_RootConstrainSelectedInstOperands,
     /* 163636 */     // GIR_Coverage, 368,
     /* 163636 */     GIR_EraseRootFromParent_Done,
     /* 163637 */   // Label 2989: @163637
     /* 163637 */   GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(163673), // Rule ID 369 //
     /* 163642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163664 */     // (intrinsic_wo_chain:{ *:[i64] } 596:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 163664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXHr),
     /* 163667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163669 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163671 */     GIR_RootConstrainSelectedInstOperands,
     /* 163672 */     // GIR_Coverage, 369,
     /* 163672 */     GIR_EraseRootFromParent_Done,
     /* 163673 */   // Label 2990: @163673
     /* 163673 */   GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(163709), // Rule ID 370 //
     /* 163678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163696 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163700 */     // (intrinsic_wo_chain:{ *:[i32] } 596:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 163700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
     /* 163703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163707 */     GIR_RootConstrainSelectedInstOperands,
     /* 163708 */     // GIR_Coverage, 370,
     /* 163708 */     GIR_EraseRootFromParent_Done,
     /* 163709 */   // Label 2991: @163709
     /* 163709 */   GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(163745), // Rule ID 371 //
     /* 163714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163736 */     // (intrinsic_wo_chain:{ *:[i64] } 596:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 163736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
     /* 163739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163743 */     GIR_RootConstrainSelectedInstOperands,
     /* 163744 */     // GIR_Coverage, 371,
     /* 163744 */     GIR_EraseRootFromParent_Done,
     /* 163745 */   // Label 2992: @163745
     /* 163745 */   GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(163781), // Rule ID 372 //
     /* 163750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163768 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163772 */     // (intrinsic_wo_chain:{ *:[i32] } 596:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 163772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
     /* 163775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163779 */     GIR_RootConstrainSelectedInstOperands,
     /* 163780 */     // GIR_Coverage, 372,
     /* 163780 */     GIR_EraseRootFromParent_Done,
     /* 163781 */   // Label 2993: @163781
     /* 163781 */   GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(163817), // Rule ID 373 //
     /* 163786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 163794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163804 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163808 */     // (intrinsic_wo_chain:{ *:[i64] } 596:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 163808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
     /* 163811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163815 */     GIR_RootConstrainSelectedInstOperands,
     /* 163816 */     // GIR_Coverage, 373,
     /* 163816 */     GIR_EraseRootFromParent_Done,
     /* 163817 */   // Label 2994: @163817
     /* 163817 */   GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(163853), // Rule ID 374 //
     /* 163822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 163830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163844 */     // (intrinsic_wo_chain:{ *:[i32] } 597:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 163844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWHr),
     /* 163847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163851 */     GIR_RootConstrainSelectedInstOperands,
     /* 163852 */     // GIR_Coverage, 374,
     /* 163852 */     GIR_EraseRootFromParent_Done,
     /* 163853 */   // Label 2995: @163853
     /* 163853 */   GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(163889), // Rule ID 375 //
     /* 163858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 163861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 163866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 163872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163876 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 163880 */     // (intrinsic_wo_chain:{ *:[i64] } 597:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 163880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXHr),
     /* 163883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163885 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163887 */     GIR_RootConstrainSelectedInstOperands,
     /* 163888 */     // GIR_Coverage, 375,
     /* 163888 */     GIR_EraseRootFromParent_Done,
     /* 163889 */   // Label 2996: @163889
     /* 163889 */   GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(163925), // Rule ID 376 //
     /* 163894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 163902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163912 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163916 */     // (intrinsic_wo_chain:{ *:[i32] } 597:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 163916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWSr),
     /* 163919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163921 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163923 */     GIR_RootConstrainSelectedInstOperands,
     /* 163924 */     // GIR_Coverage, 376,
     /* 163924 */     GIR_EraseRootFromParent_Done,
     /* 163925 */   // Label 2997: @163925
     /* 163925 */   GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(163961), // Rule ID 377 //
     /* 163930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 163938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 163941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 163944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 163948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 163952 */     // (intrinsic_wo_chain:{ *:[i64] } 597:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 163952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXSr),
     /* 163955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163959 */     GIR_RootConstrainSelectedInstOperands,
     /* 163960 */     // GIR_Coverage, 377,
     /* 163960 */     GIR_EraseRootFromParent_Done,
     /* 163961 */   // Label 2998: @163961
     /* 163961 */   GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(163997), // Rule ID 378 //
     /* 163966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 163969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 163974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 163977 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 163980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 163984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163988 */     // (intrinsic_wo_chain:{ *:[i32] } 597:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 163988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWDr),
     /* 163991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 163993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 163995 */     GIR_RootConstrainSelectedInstOperands,
     /* 163996 */     // GIR_Coverage, 378,
     /* 163996 */     GIR_EraseRootFromParent_Done,
     /* 163997 */   // Label 2999: @163997
     /* 163997 */   GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(164033), // Rule ID 379 //
     /* 164002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 164010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164024 */     // (intrinsic_wo_chain:{ *:[i64] } 597:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 164024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXDr),
     /* 164027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164029 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164031 */     GIR_RootConstrainSelectedInstOperands,
     /* 164032 */     // GIR_Coverage, 379,
     /* 164032 */     GIR_EraseRootFromParent_Done,
     /* 164033 */   // Label 3000: @164033
     /* 164033 */   GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(164069), // Rule ID 380 //
     /* 164038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164056 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164060 */     // (intrinsic_wo_chain:{ *:[i32] } 598:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 164060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWHr),
     /* 164063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164067 */     GIR_RootConstrainSelectedInstOperands,
     /* 164068 */     // GIR_Coverage, 380,
     /* 164068 */     GIR_EraseRootFromParent_Done,
     /* 164069 */   // Label 3001: @164069
     /* 164069 */   GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(164105), // Rule ID 381 //
     /* 164074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164096 */     // (intrinsic_wo_chain:{ *:[i64] } 598:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 164096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXHr),
     /* 164099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164101 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164103 */     GIR_RootConstrainSelectedInstOperands,
     /* 164104 */     // GIR_Coverage, 381,
     /* 164104 */     GIR_EraseRootFromParent_Done,
     /* 164105 */   // Label 3002: @164105
     /* 164105 */   GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(164141), // Rule ID 382 //
     /* 164110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164128 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164132 */     // (intrinsic_wo_chain:{ *:[i32] } 598:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 164132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWSr),
     /* 164135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164139 */     GIR_RootConstrainSelectedInstOperands,
     /* 164140 */     // GIR_Coverage, 382,
     /* 164140 */     GIR_EraseRootFromParent_Done,
     /* 164141 */   // Label 3003: @164141
     /* 164141 */   GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(164177), // Rule ID 383 //
     /* 164146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164164 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164168 */     // (intrinsic_wo_chain:{ *:[i64] } 598:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 164168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXSr),
     /* 164171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164175 */     GIR_RootConstrainSelectedInstOperands,
     /* 164176 */     // GIR_Coverage, 383,
     /* 164176 */     GIR_EraseRootFromParent_Done,
     /* 164177 */   // Label 3004: @164177
     /* 164177 */   GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(164213), // Rule ID 384 //
     /* 164182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164200 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164204 */     // (intrinsic_wo_chain:{ *:[i32] } 598:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 164204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWDr),
     /* 164207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164209 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164211 */     GIR_RootConstrainSelectedInstOperands,
     /* 164212 */     // GIR_Coverage, 384,
     /* 164212 */     GIR_EraseRootFromParent_Done,
     /* 164213 */   // Label 3005: @164213
     /* 164213 */   GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(164249), // Rule ID 385 //
     /* 164218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 164226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164236 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164240 */     // (intrinsic_wo_chain:{ *:[i64] } 598:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 164240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXDr),
     /* 164243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164247 */     GIR_RootConstrainSelectedInstOperands,
     /* 164248 */     // GIR_Coverage, 385,
     /* 164248 */     GIR_EraseRootFromParent_Done,
     /* 164249 */   // Label 3006: @164249
     /* 164249 */   GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(164285), // Rule ID 386 //
     /* 164254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164272 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164276 */     // (intrinsic_wo_chain:{ *:[i32] } 599:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 164276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWHr),
     /* 164279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164281 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164283 */     GIR_RootConstrainSelectedInstOperands,
     /* 164284 */     // GIR_Coverage, 386,
     /* 164284 */     GIR_EraseRootFromParent_Done,
     /* 164285 */   // Label 3007: @164285
     /* 164285 */   GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(164321), // Rule ID 387 //
     /* 164290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164304 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164312 */     // (intrinsic_wo_chain:{ *:[i64] } 599:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 164312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXHr),
     /* 164315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164319 */     GIR_RootConstrainSelectedInstOperands,
     /* 164320 */     // GIR_Coverage, 387,
     /* 164320 */     GIR_EraseRootFromParent_Done,
     /* 164321 */   // Label 3008: @164321
     /* 164321 */   GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(164357), // Rule ID 388 //
     /* 164326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164329 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164334 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164337 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164344 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164348 */     // (intrinsic_wo_chain:{ *:[i32] } 599:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 164348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
     /* 164351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164353 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164355 */     GIR_RootConstrainSelectedInstOperands,
     /* 164356 */     // GIR_Coverage, 388,
     /* 164356 */     GIR_EraseRootFromParent_Done,
     /* 164357 */   // Label 3009: @164357
     /* 164357 */   GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(164393), // Rule ID 389 //
     /* 164362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164365 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164370 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164373 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164384 */     // (intrinsic_wo_chain:{ *:[i64] } 599:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 164384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
     /* 164387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164391 */     GIR_RootConstrainSelectedInstOperands,
     /* 164392 */     // GIR_Coverage, 389,
     /* 164392 */     GIR_EraseRootFromParent_Done,
     /* 164393 */   // Label 3010: @164393
     /* 164393 */   GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(164429), // Rule ID 390 //
     /* 164398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164416 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164420 */     // (intrinsic_wo_chain:{ *:[i32] } 599:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 164420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
     /* 164423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164425 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164427 */     GIR_RootConstrainSelectedInstOperands,
     /* 164428 */     // GIR_Coverage, 390,
     /* 164428 */     GIR_EraseRootFromParent_Done,
     /* 164429 */   // Label 3011: @164429
     /* 164429 */   GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(164465), // Rule ID 391 //
     /* 164434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 164442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164456 */     // (intrinsic_wo_chain:{ *:[i64] } 599:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 164456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
     /* 164459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164461 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164463 */     GIR_RootConstrainSelectedInstOperands,
     /* 164464 */     // GIR_Coverage, 391,
     /* 164464 */     GIR_EraseRootFromParent_Done,
     /* 164465 */   // Label 3012: @164465
     /* 164465 */   GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(164501), // Rule ID 392 //
     /* 164470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164492 */     // (intrinsic_wo_chain:{ *:[i32] } 600:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 164492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWHr),
     /* 164495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164499 */     GIR_RootConstrainSelectedInstOperands,
     /* 164500 */     // GIR_Coverage, 392,
     /* 164500 */     GIR_EraseRootFromParent_Done,
     /* 164501 */   // Label 3013: @164501
     /* 164501 */   GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(164537), // Rule ID 393 //
     /* 164506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 164509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 164520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164524 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 164528 */     // (intrinsic_wo_chain:{ *:[i64] } 600:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 164528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXHr),
     /* 164531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164535 */     GIR_RootConstrainSelectedInstOperands,
     /* 164536 */     // GIR_Coverage, 393,
     /* 164536 */     GIR_EraseRootFromParent_Done,
     /* 164537 */   // Label 3014: @164537
     /* 164537 */   GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(164573), // Rule ID 394 //
     /* 164542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164564 */     // (intrinsic_wo_chain:{ *:[i32] } 600:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 164564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
     /* 164567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164571 */     GIR_RootConstrainSelectedInstOperands,
     /* 164572 */     // GIR_Coverage, 394,
     /* 164572 */     GIR_EraseRootFromParent_Done,
     /* 164573 */   // Label 3015: @164573
     /* 164573 */   GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(164609), // Rule ID 395 //
     /* 164578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164600 */     // (intrinsic_wo_chain:{ *:[i64] } 600:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 164600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
     /* 164603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164607 */     GIR_RootConstrainSelectedInstOperands,
     /* 164608 */     // GIR_Coverage, 395,
     /* 164608 */     GIR_EraseRootFromParent_Done,
     /* 164609 */   // Label 3016: @164609
     /* 164609 */   GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(164645), // Rule ID 396 //
     /* 164614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 164632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164636 */     // (intrinsic_wo_chain:{ *:[i32] } 600:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 164636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
     /* 164639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164641 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164643 */     GIR_RootConstrainSelectedInstOperands,
     /* 164644 */     // GIR_Coverage, 396,
     /* 164644 */     GIR_EraseRootFromParent_Done,
     /* 164645 */   // Label 3017: @164645
     /* 164645 */   GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(164681), // Rule ID 397 //
     /* 164650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 164653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 164658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164668 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164672 */     // (intrinsic_wo_chain:{ *:[i64] } 600:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 164672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
     /* 164675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164679 */     GIR_RootConstrainSelectedInstOperands,
     /* 164680 */     // GIR_Coverage, 397,
     /* 164680 */     GIR_EraseRootFromParent_Done,
     /* 164681 */   // Label 3018: @164681
     /* 164681 */   GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(164717), // Rule ID 579 //
     /* 164686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
     /* 164694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164704 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164708 */     // (intrinsic_wo_chain:{ *:[f32] } 558:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT32ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 164708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZSr),
     /* 164711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164715 */     GIR_RootConstrainSelectedInstOperands,
     /* 164716 */     // GIR_Coverage, 579,
     /* 164716 */     GIR_EraseRootFromParent_Done,
     /* 164717 */   // Label 3019: @164717
     /* 164717 */   GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(164753), // Rule ID 580 //
     /* 164722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
     /* 164730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164744 */     // (intrinsic_wo_chain:{ *:[f64] } 558:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT32ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 164744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
     /* 164747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164751 */     GIR_RootConstrainSelectedInstOperands,
     /* 164752 */     // GIR_Coverage, 580,
     /* 164752 */     GIR_EraseRootFromParent_Done,
     /* 164753 */   // Label 3020: @164753
     /* 164753 */   GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(164789), // Rule ID 581 //
     /* 164758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
     /* 164766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164780 */     // (intrinsic_wo_chain:{ *:[f32] } 560:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT64ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 164780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZSr),
     /* 164783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164787 */     GIR_RootConstrainSelectedInstOperands,
     /* 164788 */     // GIR_Coverage, 581,
     /* 164788 */     GIR_EraseRootFromParent_Done,
     /* 164789 */   // Label 3021: @164789
     /* 164789 */   GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(164825), // Rule ID 582 //
     /* 164794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
     /* 164802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164812 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164816 */     // (intrinsic_wo_chain:{ *:[f64] } 560:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT64ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 164816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
     /* 164819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164823 */     GIR_RootConstrainSelectedInstOperands,
     /* 164824 */     // GIR_Coverage, 582,
     /* 164824 */     GIR_EraseRootFromParent_Done,
     /* 164825 */   // Label 3022: @164825
     /* 164825 */   GIM_Try, /*On fail goto*//*Label 3023*/ GIMT_Encode4(164861), // Rule ID 583 //
     /* 164830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
     /* 164838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164848 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164852 */     // (intrinsic_wo_chain:{ *:[f32] } 557:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT32XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 164852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XSr),
     /* 164855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164859 */     GIR_RootConstrainSelectedInstOperands,
     /* 164860 */     // GIR_Coverage, 583,
     /* 164860 */     GIR_EraseRootFromParent_Done,
     /* 164861 */   // Label 3023: @164861
     /* 164861 */   GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(164897), // Rule ID 584 //
     /* 164866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164869 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
     /* 164874 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164877 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164884 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164888 */     // (intrinsic_wo_chain:{ *:[f64] } 557:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT32XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 164888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
     /* 164891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164893 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164895 */     GIR_RootConstrainSelectedInstOperands,
     /* 164896 */     // GIR_Coverage, 584,
     /* 164896 */     GIR_EraseRootFromParent_Done,
     /* 164897 */   // Label 3024: @164897
     /* 164897 */   GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(164933), // Rule ID 585 //
     /* 164902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
     /* 164910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 164913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 164916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 164924 */     // (intrinsic_wo_chain:{ *:[f32] } 559:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT64XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 164924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XSr),
     /* 164927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164929 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164931 */     GIR_RootConstrainSelectedInstOperands,
     /* 164932 */     // GIR_Coverage, 585,
     /* 164932 */     GIR_EraseRootFromParent_Done,
     /* 164933 */   // Label 3025: @164933
     /* 164933 */   GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(164969), // Rule ID 586 //
     /* 164938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 164941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
     /* 164946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 164949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 164952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164956 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164960 */     // (intrinsic_wo_chain:{ *:[f64] } 559:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT64XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 164960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
     /* 164963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 164965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 164967 */     GIR_RootConstrainSelectedInstOperands,
     /* 164968 */     // GIR_Coverage, 586,
     /* 164968 */     GIR_EraseRootFromParent_Done,
     /* 164969 */   // Label 3026: @164969
     /* 164969 */   GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(165005), // Rule ID 714 //
     /* 164974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 164977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 164982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 164985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 164988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164996 */     // (intrinsic_wo_chain:{ *:[v8i8] } 585:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 164996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i8),
     /* 164999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165003 */     GIR_RootConstrainSelectedInstOperands,
     /* 165004 */     // GIR_Coverage, 714,
     /* 165004 */     GIR_EraseRootFromParent_Done,
     /* 165005 */   // Label 3027: @165005
     /* 165005 */   GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(165041), // Rule ID 715 //
     /* 165010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 165018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 165021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 165024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165032 */     // (intrinsic_wo_chain:{ *:[v16i8] } 585:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 165032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv16i8),
     /* 165035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165039 */     GIR_RootConstrainSelectedInstOperands,
     /* 165040 */     // GIR_Coverage, 715,
     /* 165040 */     GIR_EraseRootFromParent_Done,
     /* 165041 */   // Label 3028: @165041
     /* 165041 */   GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(165077), // Rule ID 716 //
     /* 165046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 165054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165064 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165068 */     // (intrinsic_wo_chain:{ *:[v4i16] } 585:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 165068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i16),
     /* 165071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165075 */     GIR_RootConstrainSelectedInstOperands,
     /* 165076 */     // GIR_Coverage, 716,
     /* 165076 */     GIR_EraseRootFromParent_Done,
     /* 165077 */   // Label 3029: @165077
     /* 165077 */   GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(165113), // Rule ID 717 //
     /* 165082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 165090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165104 */     // (intrinsic_wo_chain:{ *:[v8i16] } 585:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 165104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i16),
     /* 165107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165111 */     GIR_RootConstrainSelectedInstOperands,
     /* 165112 */     // GIR_Coverage, 717,
     /* 165112 */     GIR_EraseRootFromParent_Done,
     /* 165113 */   // Label 3030: @165113
     /* 165113 */   GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(165149), // Rule ID 718 //
     /* 165118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 165126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165136 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165140 */     // (intrinsic_wo_chain:{ *:[v2i32] } 585:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 165140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv2i32),
     /* 165143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165147 */     GIR_RootConstrainSelectedInstOperands,
     /* 165148 */     // GIR_Coverage, 718,
     /* 165148 */     GIR_EraseRootFromParent_Done,
     /* 165149 */   // Label 3031: @165149
     /* 165149 */   GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(165185), // Rule ID 719 //
     /* 165154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 165162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 165165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 165168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165172 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165176 */     // (intrinsic_wo_chain:{ *:[v4i32] } 585:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 165176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i32),
     /* 165179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165183 */     GIR_RootConstrainSelectedInstOperands,
     /* 165184 */     // GIR_Coverage, 719,
     /* 165184 */     GIR_EraseRootFromParent_Done,
     /* 165185 */   // Label 3032: @165185
     /* 165185 */   GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(165221), // Rule ID 800 //
     /* 165190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 165198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165212 */     // (intrinsic_wo_chain:{ *:[v4i16] } 593:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 165212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f16),
     /* 165215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165219 */     GIR_RootConstrainSelectedInstOperands,
     /* 165220 */     // GIR_Coverage, 800,
     /* 165220 */     GIR_EraseRootFromParent_Done,
     /* 165221 */   // Label 3033: @165221
     /* 165221 */   GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(165257), // Rule ID 801 //
     /* 165226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165229 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 165234 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165237 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165244 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165248 */     // (intrinsic_wo_chain:{ *:[v8i16] } 593:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 165248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv8f16),
     /* 165251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165255 */     GIR_RootConstrainSelectedInstOperands,
     /* 165256 */     // GIR_Coverage, 801,
     /* 165256 */     GIR_EraseRootFromParent_Done,
     /* 165257 */   // Label 3034: @165257
     /* 165257 */   GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(165293), // Rule ID 802 //
     /* 165262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 165270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165284 */     // (intrinsic_wo_chain:{ *:[v2i32] } 593:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 165284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f32),
     /* 165287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165289 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165291 */     GIR_RootConstrainSelectedInstOperands,
     /* 165292 */     // GIR_Coverage, 802,
     /* 165292 */     GIR_EraseRootFromParent_Done,
     /* 165293 */   // Label 3035: @165293
     /* 165293 */   GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(165329), // Rule ID 803 //
     /* 165298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 165306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 165309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 165312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165316 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165320 */     // (intrinsic_wo_chain:{ *:[v4i32] } 593:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 165320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f32),
     /* 165323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165327 */     GIR_RootConstrainSelectedInstOperands,
     /* 165328 */     // GIR_Coverage, 803,
     /* 165328 */     GIR_EraseRootFromParent_Done,
     /* 165329 */   // Label 3036: @165329
     /* 165329 */   GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(165365), // Rule ID 804 //
     /* 165334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 165342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 165345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 165348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165352 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165356 */     // (intrinsic_wo_chain:{ *:[v2i64] } 593:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 165356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f64),
     /* 165359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165363 */     GIR_RootConstrainSelectedInstOperands,
     /* 165364 */     // GIR_Coverage, 804,
     /* 165364 */     GIR_EraseRootFromParent_Done,
     /* 165365 */   // Label 3037: @165365
     /* 165365 */   GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(165401), // Rule ID 805 //
     /* 165370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165373 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 165378 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165381 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165392 */     // (intrinsic_wo_chain:{ *:[v4i16] } 594:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 165392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f16),
     /* 165395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165399 */     GIR_RootConstrainSelectedInstOperands,
     /* 165400 */     // GIR_Coverage, 805,
     /* 165400 */     GIR_EraseRootFromParent_Done,
     /* 165401 */   // Label 3038: @165401
     /* 165401 */   GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(165437), // Rule ID 806 //
     /* 165406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 165414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165417 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165428 */     // (intrinsic_wo_chain:{ *:[v8i16] } 594:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 165428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv8f16),
     /* 165431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165433 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165435 */     GIR_RootConstrainSelectedInstOperands,
     /* 165436 */     // GIR_Coverage, 806,
     /* 165436 */     GIR_EraseRootFromParent_Done,
     /* 165437 */   // Label 3039: @165437
     /* 165437 */   GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(165473), // Rule ID 807 //
     /* 165442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 165450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165460 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165464 */     // (intrinsic_wo_chain:{ *:[v2i32] } 594:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 165464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f32),
     /* 165467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165471 */     GIR_RootConstrainSelectedInstOperands,
     /* 165472 */     // GIR_Coverage, 807,
     /* 165472 */     GIR_EraseRootFromParent_Done,
     /* 165473 */   // Label 3040: @165473
     /* 165473 */   GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(165509), // Rule ID 808 //
     /* 165478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 165486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 165489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 165492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165496 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165500 */     // (intrinsic_wo_chain:{ *:[v4i32] } 594:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 165500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f32),
     /* 165503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165507 */     GIR_RootConstrainSelectedInstOperands,
     /* 165508 */     // GIR_Coverage, 808,
     /* 165508 */     GIR_EraseRootFromParent_Done,
     /* 165509 */   // Label 3041: @165509
     /* 165509 */   GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(165545), // Rule ID 809 //
     /* 165514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 165522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 165525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 165528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165532 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165536 */     // (intrinsic_wo_chain:{ *:[v2i64] } 594:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 165536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f64),
     /* 165539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165541 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165543 */     GIR_RootConstrainSelectedInstOperands,
     /* 165544 */     // GIR_Coverage, 809,
     /* 165544 */     GIR_EraseRootFromParent_Done,
     /* 165545 */   // Label 3042: @165545
     /* 165545 */   GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(165581), // Rule ID 810 //
     /* 165550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165553 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 165558 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165561 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165572 */     // (intrinsic_wo_chain:{ *:[v4i16] } 595:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 165572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f16),
     /* 165575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165579 */     GIR_RootConstrainSelectedInstOperands,
     /* 165580 */     // GIR_Coverage, 810,
     /* 165580 */     GIR_EraseRootFromParent_Done,
     /* 165581 */   // Label 3043: @165581
     /* 165581 */   GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(165617), // Rule ID 811 //
     /* 165586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 165594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165608 */     // (intrinsic_wo_chain:{ *:[v8i16] } 595:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 165608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv8f16),
     /* 165611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165615 */     GIR_RootConstrainSelectedInstOperands,
     /* 165616 */     // GIR_Coverage, 811,
     /* 165616 */     GIR_EraseRootFromParent_Done,
     /* 165617 */   // Label 3044: @165617
     /* 165617 */   GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(165653), // Rule ID 812 //
     /* 165622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165625 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 165630 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165633 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165644 */     // (intrinsic_wo_chain:{ *:[v2i32] } 595:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 165644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f32),
     /* 165647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165649 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165651 */     GIR_RootConstrainSelectedInstOperands,
     /* 165652 */     // GIR_Coverage, 812,
     /* 165652 */     GIR_EraseRootFromParent_Done,
     /* 165653 */   // Label 3045: @165653
     /* 165653 */   GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(165689), // Rule ID 813 //
     /* 165658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 165666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 165669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 165672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165676 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165680 */     // (intrinsic_wo_chain:{ *:[v4i32] } 595:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 165680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f32),
     /* 165683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165687 */     GIR_RootConstrainSelectedInstOperands,
     /* 165688 */     // GIR_Coverage, 813,
     /* 165688 */     GIR_EraseRootFromParent_Done,
     /* 165689 */   // Label 3046: @165689
     /* 165689 */   GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(165725), // Rule ID 814 //
     /* 165694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 165702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 165705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 165708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165712 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165716 */     // (intrinsic_wo_chain:{ *:[v2i64] } 595:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 165716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f64),
     /* 165719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165723 */     GIR_RootConstrainSelectedInstOperands,
     /* 165724 */     // GIR_Coverage, 814,
     /* 165724 */     GIR_EraseRootFromParent_Done,
     /* 165725 */   // Label 3047: @165725
     /* 165725 */   GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(165761), // Rule ID 815 //
     /* 165730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 165738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165748 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165752 */     // (intrinsic_wo_chain:{ *:[v4i16] } 596:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 165752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f16),
     /* 165755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165759 */     GIR_RootConstrainSelectedInstOperands,
     /* 165760 */     // GIR_Coverage, 815,
     /* 165760 */     GIR_EraseRootFromParent_Done,
     /* 165761 */   // Label 3048: @165761
     /* 165761 */   GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(165797), // Rule ID 816 //
     /* 165766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 165774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165788 */     // (intrinsic_wo_chain:{ *:[v8i16] } 596:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 165788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv8f16),
     /* 165791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165795 */     GIR_RootConstrainSelectedInstOperands,
     /* 165796 */     // GIR_Coverage, 816,
     /* 165796 */     GIR_EraseRootFromParent_Done,
     /* 165797 */   // Label 3049: @165797
     /* 165797 */   GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(165833), // Rule ID 817 //
     /* 165802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 165810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165824 */     // (intrinsic_wo_chain:{ *:[v2i32] } 596:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 165824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f32),
     /* 165827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165831 */     GIR_RootConstrainSelectedInstOperands,
     /* 165832 */     // GIR_Coverage, 817,
     /* 165832 */     GIR_EraseRootFromParent_Done,
     /* 165833 */   // Label 3050: @165833
     /* 165833 */   GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(165869), // Rule ID 818 //
     /* 165838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 165846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 165849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 165852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165856 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165860 */     // (intrinsic_wo_chain:{ *:[v4i32] } 596:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 165860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f32),
     /* 165863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165867 */     GIR_RootConstrainSelectedInstOperands,
     /* 165868 */     // GIR_Coverage, 818,
     /* 165868 */     GIR_EraseRootFromParent_Done,
     /* 165869 */   // Label 3051: @165869
     /* 165869 */   GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(165905), // Rule ID 819 //
     /* 165874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 165882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 165885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 165888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165892 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165896 */     // (intrinsic_wo_chain:{ *:[v2i64] } 596:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 165896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f64),
     /* 165899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165903 */     GIR_RootConstrainSelectedInstOperands,
     /* 165904 */     // GIR_Coverage, 819,
     /* 165904 */     GIR_EraseRootFromParent_Done,
     /* 165905 */   // Label 3052: @165905
     /* 165905 */   GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(165941), // Rule ID 820 //
     /* 165910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 165918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 165921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 165924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 165932 */     // (intrinsic_wo_chain:{ *:[v4i16] } 597:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 165932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f16),
     /* 165935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165939 */     GIR_RootConstrainSelectedInstOperands,
     /* 165940 */     // GIR_Coverage, 820,
     /* 165940 */     GIR_EraseRootFromParent_Done,
     /* 165941 */   // Label 3053: @165941
     /* 165941 */   GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(165977), // Rule ID 821 //
     /* 165946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 165949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 165954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 165957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 165960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 165968 */     // (intrinsic_wo_chain:{ *:[v8i16] } 597:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 165968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv8f16),
     /* 165971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 165973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 165975 */     GIR_RootConstrainSelectedInstOperands,
     /* 165976 */     // GIR_Coverage, 821,
     /* 165976 */     GIR_EraseRootFromParent_Done,
     /* 165977 */   // Label 3054: @165977
     /* 165977 */   GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(166013), // Rule ID 822 //
     /* 165982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 165985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 165990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 165993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 165996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166004 */     // (intrinsic_wo_chain:{ *:[v2i32] } 597:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 166004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f32),
     /* 166007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166011 */     GIR_RootConstrainSelectedInstOperands,
     /* 166012 */     // GIR_Coverage, 822,
     /* 166012 */     GIR_EraseRootFromParent_Done,
     /* 166013 */   // Label 3055: @166013
     /* 166013 */   GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(166049), // Rule ID 823 //
     /* 166018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 166026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166036 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166040 */     // (intrinsic_wo_chain:{ *:[v4i32] } 597:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 166040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f32),
     /* 166043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166045 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166047 */     GIR_RootConstrainSelectedInstOperands,
     /* 166048 */     // GIR_Coverage, 823,
     /* 166048 */     GIR_EraseRootFromParent_Done,
     /* 166049 */   // Label 3056: @166049
     /* 166049 */   GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(166085), // Rule ID 824 //
     /* 166054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 166062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166076 */     // (intrinsic_wo_chain:{ *:[v2i64] } 597:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 166076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f64),
     /* 166079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166083 */     GIR_RootConstrainSelectedInstOperands,
     /* 166084 */     // GIR_Coverage, 824,
     /* 166084 */     GIR_EraseRootFromParent_Done,
     /* 166085 */   // Label 3057: @166085
     /* 166085 */   GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(166121), // Rule ID 825 //
     /* 166090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 166098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 166101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 166104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166112 */     // (intrinsic_wo_chain:{ *:[v4i16] } 598:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 166112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f16),
     /* 166115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166119 */     GIR_RootConstrainSelectedInstOperands,
     /* 166120 */     // GIR_Coverage, 825,
     /* 166120 */     GIR_EraseRootFromParent_Done,
     /* 166121 */   // Label 3058: @166121
     /* 166121 */   GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(166157), // Rule ID 826 //
     /* 166126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166129 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 166134 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 166137 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 166140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166148 */     // (intrinsic_wo_chain:{ *:[v8i16] } 598:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 166148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv8f16),
     /* 166151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166155 */     GIR_RootConstrainSelectedInstOperands,
     /* 166156 */     // GIR_Coverage, 826,
     /* 166156 */     GIR_EraseRootFromParent_Done,
     /* 166157 */   // Label 3059: @166157
     /* 166157 */   GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(166193), // Rule ID 827 //
     /* 166162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 166170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166184 */     // (intrinsic_wo_chain:{ *:[v2i32] } 598:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 166184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f32),
     /* 166187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166189 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166191 */     GIR_RootConstrainSelectedInstOperands,
     /* 166192 */     // GIR_Coverage, 827,
     /* 166192 */     GIR_EraseRootFromParent_Done,
     /* 166193 */   // Label 3060: @166193
     /* 166193 */   GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(166229), // Rule ID 828 //
     /* 166198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 166206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166216 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166220 */     // (intrinsic_wo_chain:{ *:[v4i32] } 598:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 166220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f32),
     /* 166223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166225 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166227 */     GIR_RootConstrainSelectedInstOperands,
     /* 166228 */     // GIR_Coverage, 828,
     /* 166228 */     GIR_EraseRootFromParent_Done,
     /* 166229 */   // Label 3061: @166229
     /* 166229 */   GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(166265), // Rule ID 829 //
     /* 166234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 166242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166252 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166256 */     // (intrinsic_wo_chain:{ *:[v2i64] } 598:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 166256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f64),
     /* 166259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166263 */     GIR_RootConstrainSelectedInstOperands,
     /* 166264 */     // GIR_Coverage, 829,
     /* 166264 */     GIR_EraseRootFromParent_Done,
     /* 166265 */   // Label 3062: @166265
     /* 166265 */   GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(166301), // Rule ID 830 //
     /* 166270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 166278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 166281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 166284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166292 */     // (intrinsic_wo_chain:{ *:[v4i16] } 599:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 166292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f16),
     /* 166295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166299 */     GIR_RootConstrainSelectedInstOperands,
     /* 166300 */     // GIR_Coverage, 830,
     /* 166300 */     GIR_EraseRootFromParent_Done,
     /* 166301 */   // Label 3063: @166301
     /* 166301 */   GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(166337), // Rule ID 831 //
     /* 166306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 166314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 166317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 166320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166328 */     // (intrinsic_wo_chain:{ *:[v8i16] } 599:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 166328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv8f16),
     /* 166331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166335 */     GIR_RootConstrainSelectedInstOperands,
     /* 166336 */     // GIR_Coverage, 831,
     /* 166336 */     GIR_EraseRootFromParent_Done,
     /* 166337 */   // Label 3064: @166337
     /* 166337 */   GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(166373), // Rule ID 832 //
     /* 166342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 166350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166364 */     // (intrinsic_wo_chain:{ *:[v2i32] } 599:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 166364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f32),
     /* 166367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166371 */     GIR_RootConstrainSelectedInstOperands,
     /* 166372 */     // GIR_Coverage, 832,
     /* 166372 */     GIR_EraseRootFromParent_Done,
     /* 166373 */   // Label 3065: @166373
     /* 166373 */   GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(166409), // Rule ID 833 //
     /* 166378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 166386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166400 */     // (intrinsic_wo_chain:{ *:[v4i32] } 599:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 166400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f32),
     /* 166403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166407 */     GIR_RootConstrainSelectedInstOperands,
     /* 166408 */     // GIR_Coverage, 833,
     /* 166408 */     GIR_EraseRootFromParent_Done,
     /* 166409 */   // Label 3066: @166409
     /* 166409 */   GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(166445), // Rule ID 834 //
     /* 166414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 166422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166436 */     // (intrinsic_wo_chain:{ *:[v2i64] } 599:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 166436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f64),
     /* 166439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166443 */     GIR_RootConstrainSelectedInstOperands,
     /* 166444 */     // GIR_Coverage, 834,
     /* 166444 */     GIR_EraseRootFromParent_Done,
     /* 166445 */   // Label 3067: @166445
     /* 166445 */   GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(166481), // Rule ID 835 //
     /* 166450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 166458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 166461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 166464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166468 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166472 */     // (intrinsic_wo_chain:{ *:[v4i16] } 600:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 166472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f16),
     /* 166475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166479 */     GIR_RootConstrainSelectedInstOperands,
     /* 166480 */     // GIR_Coverage, 835,
     /* 166480 */     GIR_EraseRootFromParent_Done,
     /* 166481 */   // Label 3068: @166481
     /* 166481 */   GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(166517), // Rule ID 836 //
     /* 166486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 166494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 166497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 166500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166508 */     // (intrinsic_wo_chain:{ *:[v8i16] } 600:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 166508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv8f16),
     /* 166511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166513 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166515 */     GIR_RootConstrainSelectedInstOperands,
     /* 166516 */     // GIR_Coverage, 836,
     /* 166516 */     GIR_EraseRootFromParent_Done,
     /* 166517 */   // Label 3069: @166517
     /* 166517 */   GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(166553), // Rule ID 837 //
     /* 166522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 166530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166544 */     // (intrinsic_wo_chain:{ *:[v2i32] } 600:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 166544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f32),
     /* 166547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166549 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166551 */     GIR_RootConstrainSelectedInstOperands,
     /* 166552 */     // GIR_Coverage, 837,
     /* 166552 */     GIR_EraseRootFromParent_Done,
     /* 166553 */   // Label 3070: @166553
     /* 166553 */   GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(166589), // Rule ID 838 //
     /* 166558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 166566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166580 */     // (intrinsic_wo_chain:{ *:[v4i32] } 600:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 166580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f32),
     /* 166583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166587 */     GIR_RootConstrainSelectedInstOperands,
     /* 166588 */     // GIR_Coverage, 838,
     /* 166588 */     GIR_EraseRootFromParent_Done,
     /* 166589 */   // Label 3071: @166589
     /* 166589 */   GIM_Try, /*On fail goto*//*Label 3072*/ GIMT_Encode4(166625), // Rule ID 839 //
     /* 166594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 166602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166612 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166616 */     // (intrinsic_wo_chain:{ *:[v2i64] } 600:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 166616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f64),
     /* 166619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166621 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166623 */     GIR_RootConstrainSelectedInstOperands,
     /* 166624 */     // GIR_Coverage, 839,
     /* 166624 */     GIR_EraseRootFromParent_Done,
     /* 166625 */   // Label 3072: @166625
     /* 166625 */   GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(166661), // Rule ID 840 //
     /* 166630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
     /* 166638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166652 */     // (intrinsic_wo_chain:{ *:[v2f32] } 601:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
     /* 166652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv2f32),
     /* 166655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166659 */     GIR_RootConstrainSelectedInstOperands,
     /* 166660 */     // GIR_Coverage, 840,
     /* 166660 */     GIR_EraseRootFromParent_Done,
     /* 166661 */   // Label 3073: @166661
     /* 166661 */   GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(166697), // Rule ID 867 //
     /* 166666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 166674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 166677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 166680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166688 */     // (intrinsic_wo_chain:{ *:[v4f16] } 642:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 166688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f16),
     /* 166691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166693 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166695 */     GIR_RootConstrainSelectedInstOperands,
     /* 166696 */     // GIR_Coverage, 867,
     /* 166696 */     GIR_EraseRootFromParent_Done,
     /* 166697 */   // Label 3074: @166697
     /* 166697 */   GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(166733), // Rule ID 868 //
     /* 166702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 166705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 166710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 166713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 166716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166724 */     // (intrinsic_wo_chain:{ *:[v8f16] } 642:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 166724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv8f16),
     /* 166727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166731 */     GIR_RootConstrainSelectedInstOperands,
     /* 166732 */     // GIR_Coverage, 868,
     /* 166732 */     GIR_EraseRootFromParent_Done,
     /* 166733 */   // Label 3075: @166733
     /* 166733 */   GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(166769), // Rule ID 869 //
     /* 166738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 166746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166756 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166760 */     // (intrinsic_wo_chain:{ *:[v2f32] } 642:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 166760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f32),
     /* 166763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166767 */     GIR_RootConstrainSelectedInstOperands,
     /* 166768 */     // GIR_Coverage, 869,
     /* 166768 */     GIR_EraseRootFromParent_Done,
     /* 166769 */   // Label 3076: @166769
     /* 166769 */   GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(166805), // Rule ID 870 //
     /* 166774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 166782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166792 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166796 */     // (intrinsic_wo_chain:{ *:[v4f32] } 642:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 166796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f32),
     /* 166799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166803 */     GIR_RootConstrainSelectedInstOperands,
     /* 166804 */     // GIR_Coverage, 870,
     /* 166804 */     GIR_EraseRootFromParent_Done,
     /* 166805 */   // Label 3077: @166805
     /* 166805 */   GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(166841), // Rule ID 871 //
     /* 166810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 166813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 166818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166832 */     // (intrinsic_wo_chain:{ *:[v2f64] } 642:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 166832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f64),
     /* 166835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166839 */     GIR_RootConstrainSelectedInstOperands,
     /* 166840 */     // GIR_Coverage, 871,
     /* 166840 */     GIR_EraseRootFromParent_Done,
     /* 166841 */   // Label 3078: @166841
     /* 166841 */   GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(166877), // Rule ID 942 //
     /* 166846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 166849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 166854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166868 */     // (intrinsic_wo_chain:{ *:[v2f32] } 646:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT32Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 166868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f32),
     /* 166871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166875 */     GIR_RootConstrainSelectedInstOperands,
     /* 166876 */     // GIR_Coverage, 942,
     /* 166876 */     GIR_EraseRootFromParent_Done,
     /* 166877 */   // Label 3079: @166877
     /* 166877 */   GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(166913), // Rule ID 943 //
     /* 166882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 166885 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 166890 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 166893 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 166896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166904 */     // (intrinsic_wo_chain:{ *:[v4f32] } 646:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT32Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 166904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv4f32),
     /* 166907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166911 */     GIR_RootConstrainSelectedInstOperands,
     /* 166912 */     // GIR_Coverage, 943,
     /* 166912 */     GIR_EraseRootFromParent_Done,
     /* 166913 */   // Label 3080: @166913
     /* 166913 */   GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(166949), // Rule ID 944 //
     /* 166918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 166921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 166926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 166929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 166932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 166940 */     // (intrinsic_wo_chain:{ *:[v2f64] } 646:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT32Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 166940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f64),
     /* 166943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166945 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166947 */     GIR_RootConstrainSelectedInstOperands,
     /* 166948 */     // GIR_Coverage, 944,
     /* 166948 */     GIR_EraseRootFromParent_Done,
     /* 166949 */   // Label 3081: @166949
     /* 166949 */   GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(166985), // Rule ID 945 //
     /* 166954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 166957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 166962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 166965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 166968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 166976 */     // (intrinsic_wo_chain:{ *:[v2f32] } 648:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT64Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 166976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f32),
     /* 166979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 166983 */     GIR_RootConstrainSelectedInstOperands,
     /* 166984 */     // GIR_Coverage, 945,
     /* 166984 */     GIR_EraseRootFromParent_Done,
     /* 166985 */   // Label 3082: @166985
     /* 166985 */   GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(167021), // Rule ID 946 //
     /* 166990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 166993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 166998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167012 */     // (intrinsic_wo_chain:{ *:[v4f32] } 648:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT64Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 167012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv4f32),
     /* 167015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167019 */     GIR_RootConstrainSelectedInstOperands,
     /* 167020 */     // GIR_Coverage, 946,
     /* 167020 */     GIR_EraseRootFromParent_Done,
     /* 167021 */   // Label 3083: @167021
     /* 167021 */   GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(167057), // Rule ID 947 //
     /* 167026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 167034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 167040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167048 */     // (intrinsic_wo_chain:{ *:[v2f64] } 648:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT64Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 167048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f64),
     /* 167051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167055 */     GIR_RootConstrainSelectedInstOperands,
     /* 167056 */     // GIR_Coverage, 947,
     /* 167056 */     GIR_EraseRootFromParent_Done,
     /* 167057 */   // Label 3084: @167057
     /* 167057 */   GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(167093), // Rule ID 948 //
     /* 167062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 167070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 167073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 167076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167084 */     // (intrinsic_wo_chain:{ *:[v2f32] } 645:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT32Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 167084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f32),
     /* 167087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167091 */     GIR_RootConstrainSelectedInstOperands,
     /* 167092 */     // GIR_Coverage, 948,
     /* 167092 */     GIR_EraseRootFromParent_Done,
     /* 167093 */   // Label 3085: @167093
     /* 167093 */   GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(167129), // Rule ID 949 //
     /* 167098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 167106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167116 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167120 */     // (intrinsic_wo_chain:{ *:[v4f32] } 645:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT32Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 167120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv4f32),
     /* 167123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167127 */     GIR_RootConstrainSelectedInstOperands,
     /* 167128 */     // GIR_Coverage, 949,
     /* 167128 */     GIR_EraseRootFromParent_Done,
     /* 167129 */   // Label 3086: @167129
     /* 167129 */   GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(167165), // Rule ID 950 //
     /* 167134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 167142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 167148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167156 */     // (intrinsic_wo_chain:{ *:[v2f64] } 645:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT32Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 167156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f64),
     /* 167159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167163 */     GIR_RootConstrainSelectedInstOperands,
     /* 167164 */     // GIR_Coverage, 950,
     /* 167164 */     GIR_EraseRootFromParent_Done,
     /* 167165 */   // Label 3087: @167165
     /* 167165 */   GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(167201), // Rule ID 951 //
     /* 167170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 167178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 167181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 167184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167192 */     // (intrinsic_wo_chain:{ *:[v2f32] } 647:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT64Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 167192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f32),
     /* 167195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167199 */     GIR_RootConstrainSelectedInstOperands,
     /* 167200 */     // GIR_Coverage, 951,
     /* 167200 */     GIR_EraseRootFromParent_Done,
     /* 167201 */   // Label 3088: @167201
     /* 167201 */   GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(167237), // Rule ID 952 //
     /* 167206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 167214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167228 */     // (intrinsic_wo_chain:{ *:[v4f32] } 647:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT64Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 167228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv4f32),
     /* 167231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167235 */     GIR_RootConstrainSelectedInstOperands,
     /* 167236 */     // GIR_Coverage, 952,
     /* 167236 */     GIR_EraseRootFromParent_Done,
     /* 167237 */   // Label 3089: @167237
     /* 167237 */   GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(167273), // Rule ID 953 //
     /* 167242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 167245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 167250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 167256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167264 */     // (intrinsic_wo_chain:{ *:[v2f64] } 647:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT64Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 167264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f64),
     /* 167267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167271 */     GIR_RootConstrainSelectedInstOperands,
     /* 167272 */     // GIR_Coverage, 953,
     /* 167272 */     GIR_EraseRootFromParent_Done,
     /* 167273 */   // Label 3090: @167273
     /* 167273 */   GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(167309), // Rule ID 954 //
     /* 167278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 167281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 167286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 167289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 167292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167300 */     // (intrinsic_wo_chain:{ *:[v4f16] } 649:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 167300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f16),
     /* 167303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167305 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167307 */     GIR_RootConstrainSelectedInstOperands,
     /* 167308 */     // GIR_Coverage, 954,
     /* 167308 */     GIR_EraseRootFromParent_Done,
     /* 167309 */   // Label 3091: @167309
     /* 167309 */   GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(167345), // Rule ID 955 //
     /* 167314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 167317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 167322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 167325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 167328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167336 */     // (intrinsic_wo_chain:{ *:[v8f16] } 649:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 167336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv8f16),
     /* 167339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167343 */     GIR_RootConstrainSelectedInstOperands,
     /* 167344 */     // GIR_Coverage, 955,
     /* 167344 */     GIR_EraseRootFromParent_Done,
     /* 167345 */   // Label 3092: @167345
     /* 167345 */   GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(167381), // Rule ID 956 //
     /* 167350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 167358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 167361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 167364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167368 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167372 */     // (intrinsic_wo_chain:{ *:[v2f32] } 649:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 167372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f32),
     /* 167375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167379 */     GIR_RootConstrainSelectedInstOperands,
     /* 167380 */     // GIR_Coverage, 956,
     /* 167380 */     GIR_EraseRootFromParent_Done,
     /* 167381 */   // Label 3093: @167381
     /* 167381 */   GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(167417), // Rule ID 957 //
     /* 167386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 167394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167404 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167408 */     // (intrinsic_wo_chain:{ *:[v4f32] } 649:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 167408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f32),
     /* 167411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167415 */     GIR_RootConstrainSelectedInstOperands,
     /* 167416 */     // GIR_Coverage, 957,
     /* 167416 */     GIR_EraseRootFromParent_Done,
     /* 167417 */   // Label 3094: @167417
     /* 167417 */   GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(167453), // Rule ID 958 //
     /* 167422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 167430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 167436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167444 */     // (intrinsic_wo_chain:{ *:[v2f64] } 649:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 167444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f64),
     /* 167447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167451 */     GIR_RootConstrainSelectedInstOperands,
     /* 167452 */     // GIR_Coverage, 958,
     /* 167452 */     GIR_EraseRootFromParent_Done,
     /* 167453 */   // Label 3095: @167453
     /* 167453 */   GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(167489), // Rule ID 1005 //
     /* 167458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 167469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 167472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167476 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167480 */     // (intrinsic_wo_chain:{ *:[v4i16] } 670:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 167480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
     /* 167483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167487 */     GIR_RootConstrainSelectedInstOperands,
     /* 167488 */     // GIR_Coverage, 1005,
     /* 167488 */     GIR_EraseRootFromParent_Done,
     /* 167489 */   // Label 3096: @167489
     /* 167489 */   GIM_Try, /*On fail goto*//*Label 3097*/ GIMT_Encode4(167525), // Rule ID 1007 //
     /* 167494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 167505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 167508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167516 */     // (intrinsic_wo_chain:{ *:[v8i16] } 670:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 167516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
     /* 167519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167523 */     GIR_RootConstrainSelectedInstOperands,
     /* 167524 */     // GIR_Coverage, 1007,
     /* 167524 */     GIR_EraseRootFromParent_Done,
     /* 167525 */   // Label 3097: @167525
     /* 167525 */   GIM_Try, /*On fail goto*//*Label 3098*/ GIMT_Encode4(167561), // Rule ID 1009 //
     /* 167530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 167541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 167544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167552 */     // (intrinsic_wo_chain:{ *:[v2i32] } 670:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 167552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
     /* 167555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167559 */     GIR_RootConstrainSelectedInstOperands,
     /* 167560 */     // GIR_Coverage, 1009,
     /* 167560 */     GIR_EraseRootFromParent_Done,
     /* 167561 */   // Label 3098: @167561
     /* 167561 */   GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(167597), // Rule ID 1011 //
     /* 167566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 167580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167588 */     // (intrinsic_wo_chain:{ *:[v4i32] } 670:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 167588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
     /* 167591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167595 */     GIR_RootConstrainSelectedInstOperands,
     /* 167596 */     // GIR_Coverage, 1011,
     /* 167596 */     GIR_EraseRootFromParent_Done,
     /* 167597 */   // Label 3099: @167597
     /* 167597 */   GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(167633), // Rule ID 1013 //
     /* 167602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 167613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 167616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167624 */     // (intrinsic_wo_chain:{ *:[v1i64] } 670:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 167624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 167627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167631 */     GIR_RootConstrainSelectedInstOperands,
     /* 167632 */     // GIR_Coverage, 1013,
     /* 167632 */     GIR_EraseRootFromParent_Done,
     /* 167633 */   // Label 3100: @167633
     /* 167633 */   GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(167669), // Rule ID 1015 //
     /* 167638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 167646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167656 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167660 */     // (intrinsic_wo_chain:{ *:[v2i64] } 670:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 167660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
     /* 167663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167667 */     GIR_RootConstrainSelectedInstOperands,
     /* 167668 */     // GIR_Coverage, 1015,
     /* 167668 */     GIR_EraseRootFromParent_Done,
     /* 167669 */   // Label 3101: @167669
     /* 167669 */   GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(167705), // Rule ID 1026 //
     /* 167674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 167685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 167688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167696 */     // (intrinsic_wo_chain:{ *:[v8i8] } 688:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 167696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i8),
     /* 167699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167703 */     GIR_RootConstrainSelectedInstOperands,
     /* 167704 */     // GIR_Coverage, 1026,
     /* 167704 */     GIR_EraseRootFromParent_Done,
     /* 167705 */   // Label 3102: @167705
     /* 167705 */   GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(167741), // Rule ID 1027 //
     /* 167710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 167721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 167724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167732 */     // (intrinsic_wo_chain:{ *:[v16i8] } 688:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 167732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv16i8),
     /* 167735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167739 */     GIR_RootConstrainSelectedInstOperands,
     /* 167740 */     // GIR_Coverage, 1027,
     /* 167740 */     GIR_EraseRootFromParent_Done,
     /* 167741 */   // Label 3103: @167741
     /* 167741 */   GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(167777), // Rule ID 1028 //
     /* 167746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 167757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 167760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167768 */     // (intrinsic_wo_chain:{ *:[v4i16] } 688:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 167768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i16),
     /* 167771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167775 */     GIR_RootConstrainSelectedInstOperands,
     /* 167776 */     // GIR_Coverage, 1028,
     /* 167776 */     GIR_EraseRootFromParent_Done,
     /* 167777 */   // Label 3104: @167777
     /* 167777 */   GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(167813), // Rule ID 1029 //
     /* 167782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 167793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 167796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167804 */     // (intrinsic_wo_chain:{ *:[v8i16] } 688:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 167804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i16),
     /* 167807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167809 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167811 */     GIR_RootConstrainSelectedInstOperands,
     /* 167812 */     // GIR_Coverage, 1029,
     /* 167812 */     GIR_EraseRootFromParent_Done,
     /* 167813 */   // Label 3105: @167813
     /* 167813 */   GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(167849), // Rule ID 1030 //
     /* 167818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 167829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 167832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167836 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167840 */     // (intrinsic_wo_chain:{ *:[v2i32] } 688:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 167840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i32),
     /* 167843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167847 */     GIR_RootConstrainSelectedInstOperands,
     /* 167848 */     // GIR_Coverage, 1030,
     /* 167848 */     GIR_EraseRootFromParent_Done,
     /* 167849 */   // Label 3106: @167849
     /* 167849 */   GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(167885), // Rule ID 1031 //
     /* 167854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 167865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 167868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167872 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167876 */     // (intrinsic_wo_chain:{ *:[v4i32] } 688:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 167876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i32),
     /* 167879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167881 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167883 */     GIR_RootConstrainSelectedInstOperands,
     /* 167884 */     // GIR_Coverage, 1031,
     /* 167884 */     GIR_EraseRootFromParent_Done,
     /* 167885 */   // Label 3107: @167885
     /* 167885 */   GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(167921), // Rule ID 1032 //
     /* 167890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 167898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 167901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 167904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167908 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167912 */     // (intrinsic_wo_chain:{ *:[v2i64] } 688:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 167912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i64),
     /* 167915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167919 */     GIR_RootConstrainSelectedInstOperands,
     /* 167920 */     // GIR_Coverage, 1032,
     /* 167920 */     GIR_EraseRootFromParent_Done,
     /* 167921 */   // Label 3108: @167921
     /* 167921 */   GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(167957), // Rule ID 1033 //
     /* 167926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 167934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 167937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 167940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 167948 */     // (intrinsic_wo_chain:{ *:[v8i8] } 695:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 167948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i8),
     /* 167951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167955 */     GIR_RootConstrainSelectedInstOperands,
     /* 167956 */     // GIR_Coverage, 1033,
     /* 167956 */     GIR_EraseRootFromParent_Done,
     /* 167957 */   // Label 3109: @167957
     /* 167957 */   GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(167993), // Rule ID 1034 //
     /* 167962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 167965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 167970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 167973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 167976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 167984 */     // (intrinsic_wo_chain:{ *:[v16i8] } 695:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 167984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv16i8),
     /* 167987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 167989 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 167991 */     GIR_RootConstrainSelectedInstOperands,
     /* 167992 */     // GIR_Coverage, 1034,
     /* 167992 */     GIR_EraseRootFromParent_Done,
     /* 167993 */   // Label 3110: @167993
     /* 167993 */   GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(168029), // Rule ID 1035 //
     /* 167998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168001 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168006 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 168009 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 168012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168016 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168020 */     // (intrinsic_wo_chain:{ *:[v4i16] } 695:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 168020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i16),
     /* 168023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168027 */     GIR_RootConstrainSelectedInstOperands,
     /* 168028 */     // GIR_Coverage, 1035,
     /* 168028 */     GIR_EraseRootFromParent_Done,
     /* 168029 */   // Label 3111: @168029
     /* 168029 */   GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(168065), // Rule ID 1036 //
     /* 168034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 168045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 168048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168052 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168056 */     // (intrinsic_wo_chain:{ *:[v8i16] } 695:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 168056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i16),
     /* 168059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168063 */     GIR_RootConstrainSelectedInstOperands,
     /* 168064 */     // GIR_Coverage, 1036,
     /* 168064 */     GIR_EraseRootFromParent_Done,
     /* 168065 */   // Label 3112: @168065
     /* 168065 */   GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(168101), // Rule ID 1037 //
     /* 168070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 168081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 168084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168088 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168092 */     // (intrinsic_wo_chain:{ *:[v2i32] } 695:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 168092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i32),
     /* 168095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168097 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168099 */     GIR_RootConstrainSelectedInstOperands,
     /* 168100 */     // GIR_Coverage, 1037,
     /* 168100 */     GIR_EraseRootFromParent_Done,
     /* 168101 */   // Label 3113: @168101
     /* 168101 */   GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(168137), // Rule ID 1038 //
     /* 168106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 168117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 168120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168128 */     // (intrinsic_wo_chain:{ *:[v4i32] } 695:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 168128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i32),
     /* 168131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168135 */     GIR_RootConstrainSelectedInstOperands,
     /* 168136 */     // GIR_Coverage, 1038,
     /* 168136 */     GIR_EraseRootFromParent_Done,
     /* 168137 */   // Label 3114: @168137
     /* 168137 */   GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(168173), // Rule ID 1039 //
     /* 168142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 168153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 168156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168160 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168164 */     // (intrinsic_wo_chain:{ *:[v2i64] } 695:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 168164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i64),
     /* 168167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168171 */     GIR_RootConstrainSelectedInstOperands,
     /* 168172 */     // GIR_Coverage, 1039,
     /* 168172 */     GIR_EraseRootFromParent_Done,
     /* 168173 */   // Label 3115: @168173
     /* 168173 */   GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(168209), // Rule ID 1066 //
     /* 168178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 168189 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 168192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168196 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168200 */     // (intrinsic_wo_chain:{ *:[v4i16] } 735:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 168200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
     /* 168203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168207 */     GIR_RootConstrainSelectedInstOperands,
     /* 168208 */     // GIR_Coverage, 1066,
     /* 168208 */     GIR_EraseRootFromParent_Done,
     /* 168209 */   // Label 3116: @168209
     /* 168209 */   GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(168245), // Rule ID 1068 //
     /* 168214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 168225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 168228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168232 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168236 */     // (intrinsic_wo_chain:{ *:[v8i16] } 735:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 168236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
     /* 168239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168243 */     GIR_RootConstrainSelectedInstOperands,
     /* 168244 */     // GIR_Coverage, 1068,
     /* 168244 */     GIR_EraseRootFromParent_Done,
     /* 168245 */   // Label 3117: @168245
     /* 168245 */   GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(168281), // Rule ID 1070 //
     /* 168250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 168261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 168264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168268 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168272 */     // (intrinsic_wo_chain:{ *:[v2i32] } 735:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 168272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
     /* 168275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168279 */     GIR_RootConstrainSelectedInstOperands,
     /* 168280 */     // GIR_Coverage, 1070,
     /* 168280 */     GIR_EraseRootFromParent_Done,
     /* 168281 */   // Label 3118: @168281
     /* 168281 */   GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(168317), // Rule ID 1072 //
     /* 168286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168294 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 168297 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 168300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168308 */     // (intrinsic_wo_chain:{ *:[v4i32] } 735:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 168308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
     /* 168311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168315 */     GIR_RootConstrainSelectedInstOperands,
     /* 168316 */     // GIR_Coverage, 1072,
     /* 168316 */     GIR_EraseRootFromParent_Done,
     /* 168317 */   // Label 3119: @168317
     /* 168317 */   GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(168353), // Rule ID 1074 //
     /* 168322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 168333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 168336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168340 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168344 */     // (intrinsic_wo_chain:{ *:[v1i64] } 735:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 168344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 168347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168351 */     GIR_RootConstrainSelectedInstOperands,
     /* 168352 */     // GIR_Coverage, 1074,
     /* 168352 */     GIR_EraseRootFromParent_Done,
     /* 168353 */   // Label 3120: @168353
     /* 168353 */   GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(168389), // Rule ID 1076 //
     /* 168358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 168366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 168369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 168372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168380 */     // (intrinsic_wo_chain:{ *:[v2i64] } 735:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 168380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
     /* 168383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168387 */     GIR_RootConstrainSelectedInstOperands,
     /* 168388 */     // GIR_Coverage, 1076,
     /* 168388 */     GIR_EraseRootFromParent_Done,
     /* 168389 */   // Label 3121: @168389
     /* 168389 */   GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(168425), // Rule ID 1090 //
     /* 168394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
     /* 168402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 168405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 168408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168412 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168416 */     // (intrinsic_wo_chain:{ *:[v2i32] } 756:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 168416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv2i32),
     /* 168419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168423 */     GIR_RootConstrainSelectedInstOperands,
     /* 168424 */     // GIR_Coverage, 1090,
     /* 168424 */     GIR_EraseRootFromParent_Done,
     /* 168425 */   // Label 3122: @168425
     /* 168425 */   GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(168461), // Rule ID 1091 //
     /* 168430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
     /* 168438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 168441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 168444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168448 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168452 */     // (intrinsic_wo_chain:{ *:[v4i32] } 756:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 168452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv4i32),
     /* 168455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168459 */     GIR_RootConstrainSelectedInstOperands,
     /* 168460 */     // GIR_Coverage, 1091,
     /* 168460 */     GIR_EraseRootFromParent_Done,
     /* 168461 */   // Label 3123: @168461
     /* 168461 */   GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(168497), // Rule ID 1092 //
     /* 168466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
     /* 168474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 168477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 168480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168488 */     // (intrinsic_wo_chain:{ *:[v2i32] } 759:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 168488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv2i32),
     /* 168491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168495 */     GIR_RootConstrainSelectedInstOperands,
     /* 168496 */     // GIR_Coverage, 1092,
     /* 168496 */     GIR_EraseRootFromParent_Done,
     /* 168497 */   // Label 3124: @168497
     /* 168497 */   GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(168533), // Rule ID 1093 //
     /* 168502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
     /* 168510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 168513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 168516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168524 */     // (intrinsic_wo_chain:{ *:[v4i32] } 759:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 168524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv4i32),
     /* 168527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168531 */     GIR_RootConstrainSelectedInstOperands,
     /* 168532 */     // GIR_Coverage, 1093,
     /* 168532 */     GIR_EraseRootFromParent_Done,
     /* 168533 */   // Label 3125: @168533
     /* 168533 */   GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(168569), // Rule ID 1657 //
     /* 168538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fcvtxn),
     /* 168546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168556 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168560 */     // (intrinsic_wo_chain:{ *:[f32] } 796:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 168560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv1i64),
     /* 168563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168567 */     GIR_RootConstrainSelectedInstOperands,
     /* 168568 */     // GIR_Coverage, 1657,
     /* 168568 */     GIR_EraseRootFromParent_Done,
     /* 168569 */   // Label 3126: @168569
     /* 168569 */   GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(168605), // Rule ID 1663 //
     /* 168574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 168582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 168585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168592 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168596 */     // (intrinsic_wo_chain:{ *:[i64] } 688:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn)  =>  (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 168596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
     /* 168599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168601 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168603 */     GIR_RootConstrainSelectedInstOperands,
     /* 168604 */     // GIR_Coverage, 1663,
     /* 168604 */     GIR_EraseRootFromParent_Done,
     /* 168605 */   // Label 3127: @168605
     /* 168605 */   GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(168641), // Rule ID 1664 //
     /* 168610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 168618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 168624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168632 */     // (intrinsic_wo_chain:{ *:[i32] } 688:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 168632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i32),
     /* 168635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168639 */     GIR_RootConstrainSelectedInstOperands,
     /* 168640 */     // GIR_Coverage, 1664,
     /* 168640 */     GIR_EraseRootFromParent_Done,
     /* 168641 */   // Label 3128: @168641
     /* 168641 */   GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(168677), // Rule ID 1665 //
     /* 168646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 168657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168668 */     // (intrinsic_wo_chain:{ *:[i64] } 695:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn)  =>  (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 168668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
     /* 168671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168675 */     GIR_RootConstrainSelectedInstOperands,
     /* 168676 */     // GIR_Coverage, 1665,
     /* 168676 */     GIR_EraseRootFromParent_Done,
     /* 168677 */   // Label 3129: @168677
     /* 168677 */   GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(168713), // Rule ID 1666 //
     /* 168682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 168690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 168696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168700 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168704 */     // (intrinsic_wo_chain:{ *:[i32] } 695:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 168704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i32),
     /* 168707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168711 */     GIR_RootConstrainSelectedInstOperands,
     /* 168712 */     // GIR_Coverage, 1666,
     /* 168712 */     GIR_EraseRootFromParent_Done,
     /* 168713 */   // Label 3130: @168713
     /* 168713 */   GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(168749), // Rule ID 1667 //
     /* 168718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtn),
     /* 168726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168740 */     // (intrinsic_wo_chain:{ *:[f32] } 673:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (SQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 168740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv1i32),
     /* 168743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168747 */     GIR_RootConstrainSelectedInstOperands,
     /* 168748 */     // GIR_Coverage, 1667,
     /* 168748 */     GIR_EraseRootFromParent_Done,
     /* 168749 */   // Label 3131: @168749
     /* 168749 */   GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(168785), // Rule ID 1668 //
     /* 168754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtun),
     /* 168762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168772 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168776 */     // (intrinsic_wo_chain:{ *:[f32] } 674:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (SQXTUNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 168776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv1i32),
     /* 168779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168781 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168783 */     GIR_RootConstrainSelectedInstOperands,
     /* 168784 */     // GIR_Coverage, 1668,
     /* 168784 */     GIR_EraseRootFromParent_Done,
     /* 168785 */   // Label 3132: @168785
     /* 168785 */   GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(168821), // Rule ID 1674 //
     /* 168790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168793 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_uqxtn),
     /* 168798 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168801 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168808 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168812 */     // (intrinsic_wo_chain:{ *:[f32] } 675:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (UQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 168812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv1i32),
     /* 168815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168817 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168819 */     GIR_RootConstrainSelectedInstOperands,
     /* 168820 */     // GIR_Coverage, 1674,
     /* 168820 */     GIR_EraseRootFromParent_Done,
     /* 168821 */   // Label 3133: @168821
     /* 168821 */   GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(168857), // Rule ID 1947 //
     /* 168826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 168829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 168834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 168837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 168840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 168844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168848 */     // (intrinsic_wo_chain:{ *:[f16] } 607:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 168848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
     /* 168851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168855 */     GIR_RootConstrainSelectedInstOperands,
     /* 168856 */     // GIR_Coverage, 1947,
     /* 168856 */     GIR_EraseRootFromParent_Done,
     /* 168857 */   // Label 3134: @168857
     /* 168857 */   GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(168893), // Rule ID 1949 //
     /* 168862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 168865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 168870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 168873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 168876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 168880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168884 */     // (intrinsic_wo_chain:{ *:[f16] } 607:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 168884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
     /* 168887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168891 */     GIR_RootConstrainSelectedInstOperands,
     /* 168892 */     // GIR_Coverage, 1949,
     /* 168892 */     GIR_EraseRootFromParent_Done,
     /* 168893 */   // Label 3135: @168893
     /* 168893 */   GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(168929), // Rule ID 1951 //
     /* 168898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 168901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 168906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 168909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 168912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 168916 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168920 */     // (intrinsic_wo_chain:{ *:[f32] } 607:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 168920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
     /* 168923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168927 */     GIR_RootConstrainSelectedInstOperands,
     /* 168928 */     // GIR_Coverage, 1951,
     /* 168928 */     GIR_EraseRootFromParent_Done,
     /* 168929 */   // Label 3136: @168929
     /* 168929 */   GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(168965), // Rule ID 1953 //
     /* 168934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 168937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 168942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 168945 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 168948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 168952 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 168956 */     // (intrinsic_wo_chain:{ *:[f16] } 609:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 168956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
     /* 168959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168963 */     GIR_RootConstrainSelectedInstOperands,
     /* 168964 */     // GIR_Coverage, 1953,
     /* 168964 */     GIR_EraseRootFromParent_Done,
     /* 168965 */   // Label 3137: @168965
     /* 168965 */   GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(169001), // Rule ID 1955 //
     /* 168970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 168973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 168978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 168981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 168984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 168988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 168992 */     // (intrinsic_wo_chain:{ *:[f16] } 609:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 168992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
     /* 168995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 168997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 168999 */     GIR_RootConstrainSelectedInstOperands,
     /* 169000 */     // GIR_Coverage, 1955,
     /* 169000 */     GIR_EraseRootFromParent_Done,
     /* 169001 */   // Label 3138: @169001
     /* 169001 */   GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(169037), // Rule ID 1957 //
     /* 169006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 169009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 169014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 169020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 169024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169028 */     // (intrinsic_wo_chain:{ *:[f32] } 609:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 169028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
     /* 169031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169035 */     GIR_RootConstrainSelectedInstOperands,
     /* 169036 */     // GIR_Coverage, 1957,
     /* 169036 */     GIR_EraseRootFromParent_Done,
     /* 169037 */   // Label 3139: @169037
     /* 169037 */   GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(169073), // Rule ID 1959 //
     /* 169042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 169045 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 169050 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 169053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 169056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 169060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169064 */     // (intrinsic_wo_chain:{ *:[f16] } 613:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 169064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
     /* 169067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169071 */     GIR_RootConstrainSelectedInstOperands,
     /* 169072 */     // GIR_Coverage, 1959,
     /* 169072 */     GIR_EraseRootFromParent_Done,
     /* 169073 */   // Label 3140: @169073
     /* 169073 */   GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(169109), // Rule ID 1961 //
     /* 169078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 169081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 169086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 169089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 169092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 169096 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169100 */     // (intrinsic_wo_chain:{ *:[f16] } 613:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 169100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
     /* 169103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169107 */     GIR_RootConstrainSelectedInstOperands,
     /* 169108 */     // GIR_Coverage, 1961,
     /* 169108 */     GIR_EraseRootFromParent_Done,
     /* 169109 */   // Label 3141: @169109
     /* 169109 */   GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(169145), // Rule ID 1963 //
     /* 169114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 169117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 169122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 169128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 169132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169136 */     // (intrinsic_wo_chain:{ *:[f32] } 613:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 169136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
     /* 169139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169143 */     GIR_RootConstrainSelectedInstOperands,
     /* 169144 */     // GIR_Coverage, 1963,
     /* 169144 */     GIR_EraseRootFromParent_Done,
     /* 169145 */   // Label 3142: @169145
     /* 169145 */   GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(169181), // Rule ID 1965 //
     /* 169150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 169153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 169158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 169161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 169164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 169168 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169172 */     // (intrinsic_wo_chain:{ *:[f16] } 615:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 169172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
     /* 169175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169179 */     GIR_RootConstrainSelectedInstOperands,
     /* 169180 */     // GIR_Coverage, 1965,
     /* 169180 */     GIR_EraseRootFromParent_Done,
     /* 169181 */   // Label 3143: @169181
     /* 169181 */   GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(169217), // Rule ID 1967 //
     /* 169186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 169189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 169194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 169197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 169200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 169204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169208 */     // (intrinsic_wo_chain:{ *:[f16] } 615:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 169208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
     /* 169211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169215 */     GIR_RootConstrainSelectedInstOperands,
     /* 169216 */     // GIR_Coverage, 1967,
     /* 169216 */     GIR_EraseRootFromParent_Done,
     /* 169217 */   // Label 3144: @169217
     /* 169217 */   GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(169253), // Rule ID 1969 //
     /* 169222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 169225 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 169230 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169233 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 169236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 169240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169244 */     // (intrinsic_wo_chain:{ *:[f32] } 615:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 169244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
     /* 169247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169251 */     GIR_RootConstrainSelectedInstOperands,
     /* 169252 */     // GIR_Coverage, 1969,
     /* 169252 */     GIR_EraseRootFromParent_Done,
     /* 169253 */   // Label 3145: @169253
     /* 169253 */   GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(169289), // Rule ID 2309 //
     /* 169258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 169261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
     /* 169266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 169269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 169272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169276 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169280 */     // (intrinsic_wo_chain:{ *:[v16i8] } 524:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 169280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrr),
     /* 169283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169287 */     GIR_RootConstrainSelectedInstOperands,
     /* 169288 */     // GIR_Coverage, 2309,
     /* 169288 */     GIR_EraseRootFromParent_Done,
     /* 169289 */   // Label 3146: @169289
     /* 169289 */   GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(169325), // Rule ID 2310 //
     /* 169294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 169297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
     /* 169302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 169305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 169308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169312 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 169316 */     // (intrinsic_wo_chain:{ *:[v16i8] } 523:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 169316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrr),
     /* 169319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169321 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169323 */     GIR_RootConstrainSelectedInstOperands,
     /* 169324 */     // GIR_Coverage, 2310,
     /* 169324 */     GIR_EraseRootFromParent_Done,
     /* 169325 */   // Label 3147: @169325
     /* 169325 */   GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(169361), // Rule ID 2318 //
     /* 169330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 169333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1h),
     /* 169338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 169344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 169348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 169352 */     // (intrinsic_wo_chain:{ *:[i32] } 531:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 169352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Hrr),
     /* 169355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169359 */     GIR_RootConstrainSelectedInstOperands,
     /* 169360 */     // GIR_Coverage, 2318,
     /* 169360 */     GIR_EraseRootFromParent_Done,
     /* 169361 */   // Label 3148: @169361
     /* 169361 */   GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(169397), // Rule ID 2515 //
     /* 169366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 169369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 169374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 169377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169388 */     // (intrinsic_wo_chain:{ *:[v1i64] } 688:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 169388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
     /* 169391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169395 */     GIR_RootConstrainSelectedInstOperands,
     /* 169396 */     // GIR_Coverage, 2515,
     /* 169396 */     GIR_EraseRootFromParent_Done,
     /* 169397 */   // Label 3149: @169397
     /* 169397 */   GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(169436), // Rule ID 3575 //
     /* 169402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 169410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 169413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 169416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169420 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169424 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1637:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn)  =>  (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, 0:{ *:[i32] })
     /* 169424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
     /* 169427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 169429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 169431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169434 */     GIR_RootConstrainSelectedInstOperands,
     /* 169435 */     // GIR_Coverage, 3575,
     /* 169435 */     GIR_EraseRootFromParent_Done,
     /* 169436 */   // Label 3150: @169436
     /* 169436 */   GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(169475), // Rule ID 3576 //
     /* 169441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 169449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 169452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 169455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169463 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1637:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn)  =>  (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, 0:{ *:[i32] })
     /* 169463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
     /* 169466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 169468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 169470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169473 */     GIR_RootConstrainSelectedInstOperands,
     /* 169474 */     // GIR_Coverage, 3576,
     /* 169474 */     GIR_EraseRootFromParent_Done,
     /* 169475 */   // Label 3151: @169475
     /* 169475 */   GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(169514), // Rule ID 3577 //
     /* 169480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 169488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 169491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 169494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169502 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1637:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn)  =>  (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, 0:{ *:[i32] })
     /* 169502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
     /* 169505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 169507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 169509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169512 */     GIR_RootConstrainSelectedInstOperands,
     /* 169513 */     // GIR_Coverage, 3577,
     /* 169513 */     GIR_EraseRootFromParent_Done,
     /* 169514 */   // Label 3152: @169514
     /* 169514 */   GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(169553), // Rule ID 3578 //
     /* 169519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 169527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 169530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 169533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169537 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169541 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1637:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn)  =>  (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, 0:{ *:[i32] })
     /* 169541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
     /* 169544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 169546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 169548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169551 */     GIR_RootConstrainSelectedInstOperands,
     /* 169552 */     // GIR_Coverage, 3578,
     /* 169552 */     GIR_EraseRootFromParent_Done,
     /* 169553 */   // Label 3153: @169553
     /* 169553 */   GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(169609), // Rule ID 3582 //
     /* 169558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 169566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 169569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 169572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169580 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1639:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn)  =>  (PMOV_ZIP_B:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i64] }, PPR8:{ *:[nxv16i1] }:$Pn)
     /* 169580 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 169583 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 169587 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169592 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_B),
     /* 169597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 169599 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 169607 */     GIR_RootConstrainSelectedInstOperands,
     /* 169608 */     // GIR_Coverage, 3582,
     /* 169608 */     GIR_EraseRootFromParent_Done,
     /* 169609 */   // Label 3154: @169609
     /* 169609 */   GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(169665), // Rule ID 3583 //
     /* 169614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 169622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 169625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 169628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169636 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1639:{ *:[iPTR] }, PPR16:{ *:[nxv8i1] }:$Pn)  =>  (PMOV_ZIP_H:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR16:{ *:[nxv8i1] }:$Pn)
     /* 169636 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 169639 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 169643 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169648 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
     /* 169653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 169655 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 169663 */     GIR_RootConstrainSelectedInstOperands,
     /* 169664 */     // GIR_Coverage, 3583,
     /* 169664 */     GIR_EraseRootFromParent_Done,
     /* 169665 */   // Label 3155: @169665
     /* 169665 */   GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(169721), // Rule ID 3584 //
     /* 169670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 169678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 169681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 169684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169692 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1639:{ *:[iPTR] }, PPR32:{ *:[nxv4i1] }:$Pn)  =>  (PMOV_ZIP_S:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR32:{ *:[nxv4i1] }:$Pn)
     /* 169692 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 169695 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 169699 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169704 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
     /* 169709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 169711 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 169719 */     GIR_RootConstrainSelectedInstOperands,
     /* 169720 */     // GIR_Coverage, 3584,
     /* 169720 */     GIR_EraseRootFromParent_Done,
     /* 169721 */   // Label 3156: @169721
     /* 169721 */   GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(169777), // Rule ID 3585 //
     /* 169726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 169729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 169734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 169737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 169740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 169744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 169748 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1639:{ *:[iPTR] }, PPR64:{ *:[nxv2i1] }:$Pn)  =>  (PMOV_ZIP_D:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR64:{ *:[nxv2i1] }:$Pn)
     /* 169748 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 169751 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 169755 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169760 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
     /* 169765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 169767 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 169773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 169775 */     GIR_RootConstrainSelectedInstOperands,
     /* 169776 */     // GIR_Coverage, 3585,
     /* 169776 */     GIR_EraseRootFromParent_Done,
     /* 169777 */   // Label 3157: @169777
     /* 169777 */   GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(169810), // Rule ID 4042 //
     /* 169782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_cls),
     /* 169787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 169793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169797 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169801 */     // (intrinsic_wo_chain:{ *:[i32] } 511:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn)  =>  (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 169801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
     /* 169804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169808 */     GIR_RootConstrainSelectedInstOperands,
     /* 169809 */     // GIR_Coverage, 4042,
     /* 169809 */     GIR_EraseRootFromParent_Done,
     /* 169810 */   // Label 3158: @169810
     /* 169810 */   GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(169875), // Rule ID 4043 //
     /* 169815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_cls64),
     /* 169820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 169823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169830 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 169834 */     // (intrinsic_wo_chain:{ *:[i32] } 512:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rm)  =>  (EXTRACT_SUBREG:{ *:[i32] } (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] })
     /* 169834 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 169837 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
     /* 169841 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169846 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169850 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 169855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 169857 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /* 169864 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169869 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 169874 */     // GIR_Coverage, 4043,
     /* 169874 */     GIR_EraseRootFromParent_Done,
     /* 169875 */   // Label 3159: @169875
     /* 169875 */   GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(169908), // Rule ID 4849 //
     /* 169880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 169885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 169888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169899 */     // (intrinsic_wo_chain:{ *:[v1f64] } 646:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT32ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 169899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
     /* 169902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169906 */     GIR_RootConstrainSelectedInstOperands,
     /* 169907 */     // GIR_Coverage, 4849,
     /* 169907 */     GIR_EraseRootFromParent_Done,
     /* 169908 */   // Label 3160: @169908
     /* 169908 */   GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(169941), // Rule ID 4850 //
     /* 169913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 169918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 169921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169932 */     // (intrinsic_wo_chain:{ *:[v1f64] } 648:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT64ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 169932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
     /* 169935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169939 */     GIR_RootConstrainSelectedInstOperands,
     /* 169940 */     // GIR_Coverage, 4850,
     /* 169940 */     GIR_EraseRootFromParent_Done,
     /* 169941 */   // Label 3161: @169941
     /* 169941 */   GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(169974), // Rule ID 4851 //
     /* 169946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 169951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 169954 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169961 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169965 */     // (intrinsic_wo_chain:{ *:[v1f64] } 645:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT32XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 169965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
     /* 169968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 169970 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 169972 */     GIR_RootConstrainSelectedInstOperands,
     /* 169973 */     // GIR_Coverage, 4851,
     /* 169973 */     GIR_EraseRootFromParent_Done,
     /* 169974 */   // Label 3162: @169974
     /* 169974 */   GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(170007), // Rule ID 4852 //
     /* 169979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 169984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 169987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 169990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 169998 */     // (intrinsic_wo_chain:{ *:[v1f64] } 647:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT64XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 169998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
     /* 170001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170005 */     GIR_RootConstrainSelectedInstOperands,
     /* 170006 */     // GIR_Coverage, 4852,
     /* 170006 */     GIR_EraseRootFromParent_Done,
     /* 170007 */   // Label 3163: @170007
     /* 170007 */   GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(170040), // Rule ID 4966 //
     /* 170012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvthf2fp),
     /* 170017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 170020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 170023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 170027 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170031 */     // (intrinsic_wo_chain:{ *:[v4f32] } 777:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn)
     /* 170031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 170034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170038 */     GIR_RootConstrainSelectedInstOperands,
     /* 170039 */     // GIR_Coverage, 4966,
     /* 170039 */     GIR_EraseRootFromParent_Done,
     /* 170040 */   // Label 3164: @170040
     /* 170040 */   GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(170073), // Rule ID 4976 //
     /* 170045 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
     /* 170050 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 170053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 170056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 170064 */     // (intrinsic_wo_chain:{ *:[v4i16] } 774:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn)
     /* 170064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 170067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170071 */     GIR_RootConstrainSelectedInstOperands,
     /* 170072 */     // GIR_Coverage, 4976,
     /* 170072 */     GIR_EraseRootFromParent_Done,
     /* 170073 */   // Label 3165: @170073
     /* 170073 */   GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(170109), // Rule ID 5297 //
     /* 170078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 170081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 170086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170096 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170100 */     // (intrinsic_wo_chain:{ *:[v1i64] } 695:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 170100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
     /* 170103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170107 */     GIR_RootConstrainSelectedInstOperands,
     /* 170108 */     // GIR_Coverage, 5297,
     /* 170108 */     GIR_EraseRootFromParent_Done,
     /* 170109 */   // Label 3166: @170109
     /* 170109 */   GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(170142), // Rule ID 5300 //
     /* 170114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 170119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170133 */     // (intrinsic_wo_chain:{ *:[v1i64] } 593:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 170136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170138 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170140 */     GIR_RootConstrainSelectedInstOperands,
     /* 170141 */     // GIR_Coverage, 5300,
     /* 170141 */     GIR_EraseRootFromParent_Done,
     /* 170142 */   // Label 3167: @170142
     /* 170142 */   GIM_Try, /*On fail goto*//*Label 3168*/ GIMT_Encode4(170175), // Rule ID 5301 //
     /* 170147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 170152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170166 */     // (intrinsic_wo_chain:{ *:[v1i64] } 594:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 170169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170173 */     GIR_RootConstrainSelectedInstOperands,
     /* 170174 */     // GIR_Coverage, 5301,
     /* 170174 */     GIR_EraseRootFromParent_Done,
     /* 170175 */   // Label 3168: @170175
     /* 170175 */   GIM_Try, /*On fail goto*//*Label 3169*/ GIMT_Encode4(170208), // Rule ID 5302 //
     /* 170180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 170185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170199 */     // (intrinsic_wo_chain:{ *:[v1i64] } 595:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 170202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170206 */     GIR_RootConstrainSelectedInstOperands,
     /* 170207 */     // GIR_Coverage, 5302,
     /* 170207 */     GIR_EraseRootFromParent_Done,
     /* 170208 */   // Label 3169: @170208
     /* 170208 */   GIM_Try, /*On fail goto*//*Label 3170*/ GIMT_Encode4(170241), // Rule ID 5303 //
     /* 170213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 170218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170232 */     // (intrinsic_wo_chain:{ *:[v1i64] } 596:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 170235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170239 */     GIR_RootConstrainSelectedInstOperands,
     /* 170240 */     // GIR_Coverage, 5303,
     /* 170240 */     GIR_EraseRootFromParent_Done,
     /* 170241 */   // Label 3170: @170241
     /* 170241 */   GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(170274), // Rule ID 5304 //
     /* 170246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 170251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170265 */     // (intrinsic_wo_chain:{ *:[v1i64] } 597:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i64),
     /* 170268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170272 */     GIR_RootConstrainSelectedInstOperands,
     /* 170273 */     // GIR_Coverage, 5304,
     /* 170273 */     GIR_EraseRootFromParent_Done,
     /* 170274 */   // Label 3171: @170274
     /* 170274 */   GIM_Try, /*On fail goto*//*Label 3172*/ GIMT_Encode4(170307), // Rule ID 5305 //
     /* 170279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 170284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170298 */     // (intrinsic_wo_chain:{ *:[v1i64] } 598:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i64),
     /* 170301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170305 */     GIR_RootConstrainSelectedInstOperands,
     /* 170306 */     // GIR_Coverage, 5305,
     /* 170306 */     GIR_EraseRootFromParent_Done,
     /* 170307 */   // Label 3172: @170307
     /* 170307 */   GIM_Try, /*On fail goto*//*Label 3173*/ GIMT_Encode4(170340), // Rule ID 5306 //
     /* 170312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 170317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170327 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170331 */     // (intrinsic_wo_chain:{ *:[v1i64] } 599:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 170334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170336 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170338 */     GIR_RootConstrainSelectedInstOperands,
     /* 170339 */     // GIR_Coverage, 5306,
     /* 170339 */     GIR_EraseRootFromParent_Done,
     /* 170340 */   // Label 3173: @170340
     /* 170340 */   GIM_Try, /*On fail goto*//*Label 3174*/ GIMT_Encode4(170373), // Rule ID 5307 //
     /* 170345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 170350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170364 */     // (intrinsic_wo_chain:{ *:[v1i64] } 600:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 170367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170371 */     GIR_RootConstrainSelectedInstOperands,
     /* 170372 */     // GIR_Coverage, 5307,
     /* 170372 */     GIR_EraseRootFromParent_Done,
     /* 170373 */   // Label 3174: @170373
     /* 170373 */   GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(170406), // Rule ID 5308 //
     /* 170378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 170383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170393 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170397 */     // (intrinsic_wo_chain:{ *:[v1i64] } 602:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 170400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170402 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170404 */     GIR_RootConstrainSelectedInstOperands,
     /* 170405 */     // GIR_Coverage, 5308,
     /* 170405 */     GIR_EraseRootFromParent_Done,
     /* 170406 */   // Label 3175: @170406
     /* 170406 */   GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(170439), // Rule ID 5309 //
     /* 170411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 170416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170426 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170430 */     // (intrinsic_wo_chain:{ *:[v1i64] } 603:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTZUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 170433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170437 */     GIR_RootConstrainSelectedInstOperands,
     /* 170438 */     // GIR_Coverage, 5309,
     /* 170438 */     GIR_EraseRootFromParent_Done,
     /* 170439 */   // Label 3176: @170439
     /* 170439 */   GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(170472), // Rule ID 5310 //
     /* 170444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 170449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 170452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 170455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170463 */     // (intrinsic_wo_chain:{ *:[f16] } 642:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 170463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1f16),
     /* 170466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170470 */     GIR_RootConstrainSelectedInstOperands,
     /* 170471 */     // GIR_Coverage, 5310,
     /* 170471 */     GIR_EraseRootFromParent_Done,
     /* 170472 */   // Label 3177: @170472
     /* 170472 */   GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(170505), // Rule ID 5311 //
     /* 170477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 170482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 170488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170496 */     // (intrinsic_wo_chain:{ *:[f32] } 642:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 170496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i32),
     /* 170499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170501 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170503 */     GIR_RootConstrainSelectedInstOperands,
     /* 170504 */     // GIR_Coverage, 5311,
     /* 170504 */     GIR_EraseRootFromParent_Done,
     /* 170505 */   // Label 3178: @170505
     /* 170505 */   GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(170538), // Rule ID 5312 //
     /* 170510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 170515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170525 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170529 */     // (intrinsic_wo_chain:{ *:[f64] } 642:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 170529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
     /* 170532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170536 */     GIR_RootConstrainSelectedInstOperands,
     /* 170537 */     // GIR_Coverage, 5312,
     /* 170537 */     GIR_EraseRootFromParent_Done,
     /* 170538 */   // Label 3179: @170538
     /* 170538 */   GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(170571), // Rule ID 5313 //
     /* 170543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 170548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170558 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170562 */     // (intrinsic_wo_chain:{ *:[v1f64] } 642:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
     /* 170565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170569 */     GIR_RootConstrainSelectedInstOperands,
     /* 170570 */     // GIR_Coverage, 5313,
     /* 170570 */     GIR_EraseRootFromParent_Done,
     /* 170571 */   // Label 3180: @170571
     /* 170571 */   GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(170604), // Rule ID 5325 //
     /* 170576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 170581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 170584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 170587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170591 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170595 */     // (intrinsic_wo_chain:{ *:[f16] } 644:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 170595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1f16),
     /* 170598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170602 */     GIR_RootConstrainSelectedInstOperands,
     /* 170603 */     // GIR_Coverage, 5325,
     /* 170603 */     GIR_EraseRootFromParent_Done,
     /* 170604 */   // Label 3181: @170604
     /* 170604 */   GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(170637), // Rule ID 5326 //
     /* 170609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 170614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 170620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170628 */     // (intrinsic_wo_chain:{ *:[f32] } 644:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 170628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i32),
     /* 170631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170635 */     GIR_RootConstrainSelectedInstOperands,
     /* 170636 */     // GIR_Coverage, 5326,
     /* 170636 */     GIR_EraseRootFromParent_Done,
     /* 170637 */   // Label 3182: @170637
     /* 170637 */   GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(170670), // Rule ID 5327 //
     /* 170642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 170647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170657 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170661 */     // (intrinsic_wo_chain:{ *:[f64] } 644:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 170661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i64),
     /* 170664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170668 */     GIR_RootConstrainSelectedInstOperands,
     /* 170669 */     // GIR_Coverage, 5327,
     /* 170669 */     GIR_EraseRootFromParent_Done,
     /* 170670 */   // Label 3183: @170670
     /* 170670 */   GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(170703), // Rule ID 5328 //
     /* 170675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 170680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 170683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 170686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 170694 */     // (intrinsic_wo_chain:{ *:[f16] } 649:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 170694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1f16),
     /* 170697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170701 */     GIR_RootConstrainSelectedInstOperands,
     /* 170702 */     // GIR_Coverage, 5328,
     /* 170702 */     GIR_EraseRootFromParent_Done,
     /* 170703 */   // Label 3184: @170703
     /* 170703 */   GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(170736), // Rule ID 5329 //
     /* 170708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 170713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 170719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170727 */     // (intrinsic_wo_chain:{ *:[f32] } 649:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 170727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i32),
     /* 170730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170734 */     GIR_RootConstrainSelectedInstOperands,
     /* 170735 */     // GIR_Coverage, 5329,
     /* 170735 */     GIR_EraseRootFromParent_Done,
     /* 170736 */   // Label 3185: @170736
     /* 170736 */   GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(170769), // Rule ID 5330 //
     /* 170741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 170746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170756 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170760 */     // (intrinsic_wo_chain:{ *:[f64] } 649:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 170760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
     /* 170763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170767 */     GIR_RootConstrainSelectedInstOperands,
     /* 170768 */     // GIR_Coverage, 5330,
     /* 170768 */     GIR_EraseRootFromParent_Done,
     /* 170769 */   // Label 3186: @170769
     /* 170769 */   GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(170802), // Rule ID 5331 //
     /* 170774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 170779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170789 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170793 */     // (intrinsic_wo_chain:{ *:[v1f64] } 649:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 170793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
     /* 170796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170798 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170800 */     GIR_RootConstrainSelectedInstOperands,
     /* 170801 */     // GIR_Coverage, 5331,
     /* 170801 */     GIR_EraseRootFromParent_Done,
     /* 170802 */   // Label 3187: @170802
     /* 170802 */   GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(170835), // Rule ID 5661 //
     /* 170807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 170812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 170818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170822 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170826 */     // (intrinsic_wo_chain:{ *:[f32] } 590:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 170826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 170829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170833 */     GIR_RootConstrainSelectedInstOperands,
     /* 170834 */     // GIR_Coverage, 5661,
     /* 170834 */     GIR_EraseRootFromParent_Done,
     /* 170835 */   // Label 3188: @170835
     /* 170835 */   GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(170920), // Rule ID 5662 //
     /* 170840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 170845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 170851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170855 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 170859 */     // (intrinsic_wo_chain:{ *:[f32] } 590:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
     /* 170859 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 170862 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 170866 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170871 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 170875 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 170879 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 170881 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170884 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 170888 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170893 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 170900 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170905 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 170910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 170913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170915 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170918 */     GIR_RootConstrainSelectedInstOperands,
     /* 170919 */     // GIR_Coverage, 5662,
     /* 170919 */     GIR_EraseRootFromParent_Done,
     /* 170920 */   // Label 3189: @170920
     /* 170920 */   GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(170953), // Rule ID 5663 //
     /* 170925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 170930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 170936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 170944 */     // (intrinsic_wo_chain:{ *:[f64] } 590:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 170944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 170947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170951 */     GIR_RootConstrainSelectedInstOperands,
     /* 170952 */     // GIR_Coverage, 5663,
     /* 170952 */     GIR_EraseRootFromParent_Done,
     /* 170953 */   // Label 3190: @170953
     /* 170953 */   GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(170986), // Rule ID 5665 //
     /* 170958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 170963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 170966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 170969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 170973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 170977 */     // (intrinsic_wo_chain:{ *:[f32] } 607:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 170977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
     /* 170980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 170982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 170984 */     GIR_RootConstrainSelectedInstOperands,
     /* 170985 */     // GIR_Coverage, 5665,
     /* 170985 */     GIR_EraseRootFromParent_Done,
     /* 170986 */   // Label 3191: @170986
     /* 170986 */   GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(171019), // Rule ID 5667 //
     /* 170991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 170996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 170999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 171002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171010 */     // (intrinsic_wo_chain:{ *:[f64] } 607:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 171010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
     /* 171013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171017 */     GIR_RootConstrainSelectedInstOperands,
     /* 171018 */     // GIR_Coverage, 5667,
     /* 171018 */     GIR_EraseRootFromParent_Done,
     /* 171019 */   // Label 3192: @171019
     /* 171019 */   GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(171052), // Rule ID 5669 //
     /* 171024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 171029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 171035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171043 */     // (intrinsic_wo_chain:{ *:[f32] } 609:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 171043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
     /* 171046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171050 */     GIR_RootConstrainSelectedInstOperands,
     /* 171051 */     // GIR_Coverage, 5669,
     /* 171051 */     GIR_EraseRootFromParent_Done,
     /* 171052 */   // Label 3193: @171052
     /* 171052 */   GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(171085), // Rule ID 5671 //
     /* 171057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 171062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 171065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 171068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171076 */     // (intrinsic_wo_chain:{ *:[f64] } 609:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 171076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
     /* 171079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171083 */     GIR_RootConstrainSelectedInstOperands,
     /* 171084 */     // GIR_Coverage, 5671,
     /* 171084 */     GIR_EraseRootFromParent_Done,
     /* 171085 */   // Label 3194: @171085
     /* 171085 */   GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(171118), // Rule ID 5673 //
     /* 171090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 171095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 171101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171105 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171109 */     // (intrinsic_wo_chain:{ *:[f32] } 613:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 171109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
     /* 171112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171116 */     GIR_RootConstrainSelectedInstOperands,
     /* 171117 */     // GIR_Coverage, 5673,
     /* 171117 */     GIR_EraseRootFromParent_Done,
     /* 171118 */   // Label 3195: @171118
     /* 171118 */   GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(171151), // Rule ID 5675 //
     /* 171123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 171128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 171131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 171134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171138 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171142 */     // (intrinsic_wo_chain:{ *:[f64] } 613:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 171142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
     /* 171145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171149 */     GIR_RootConstrainSelectedInstOperands,
     /* 171150 */     // GIR_Coverage, 5675,
     /* 171150 */     GIR_EraseRootFromParent_Done,
     /* 171151 */   // Label 3196: @171151
     /* 171151 */   GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(171184), // Rule ID 5677 //
     /* 171156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 171161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 171167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171175 */     // (intrinsic_wo_chain:{ *:[f32] } 615:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 171175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
     /* 171178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171182 */     GIR_RootConstrainSelectedInstOperands,
     /* 171183 */     // GIR_Coverage, 5677,
     /* 171183 */     GIR_EraseRootFromParent_Done,
     /* 171184 */   // Label 3197: @171184
     /* 171184 */   GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(171217), // Rule ID 5679 //
     /* 171189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 171194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 171197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 171200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171208 */     // (intrinsic_wo_chain:{ *:[f64] } 615:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 171208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
     /* 171211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171215 */     GIR_RootConstrainSelectedInstOperands,
     /* 171216 */     // GIR_Coverage, 5679,
     /* 171216 */     GIR_EraseRootFromParent_Done,
     /* 171217 */   // Label 3198: @171217
     /* 171217 */   GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(171250), // Rule ID 13424 //
     /* 171222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 171230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 171233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 171237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171241 */     // (intrinsic_wo_chain:{ *:[i8] } 672:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 171241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 171244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171248 */     GIR_RootConstrainSelectedInstOperands,
     /* 171249 */     // GIR_Coverage, 13424,
     /* 171249 */     GIR_EraseRootFromParent_Done,
     /* 171250 */   // Label 3199: @171250
     /* 171250 */   GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(171283), // Rule ID 13426 //
     /* 171255 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171260 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 171263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 171266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 171270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171274 */     // (intrinsic_wo_chain:{ *:[i8] } 672:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 171274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 171277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171281 */     GIR_RootConstrainSelectedInstOperands,
     /* 171282 */     // GIR_Coverage, 13426,
     /* 171282 */     GIR_EraseRootFromParent_Done,
     /* 171283 */   // Label 3200: @171283
     /* 171283 */   GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(171316), // Rule ID 13428 //
     /* 171288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 171296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 171299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 171303 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171307 */     // (intrinsic_wo_chain:{ *:[i16] } 672:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 171307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 171310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171314 */     GIR_RootConstrainSelectedInstOperands,
     /* 171315 */     // GIR_Coverage, 13428,
     /* 171315 */     GIR_EraseRootFromParent_Done,
     /* 171316 */   // Label 3201: @171316
     /* 171316 */   GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(171349), // Rule ID 13430 //
     /* 171321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 171329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 171332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 171336 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171340 */     // (intrinsic_wo_chain:{ *:[i16] } 672:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 171340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 171343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171347 */     GIR_RootConstrainSelectedInstOperands,
     /* 171348 */     // GIR_Coverage, 13430,
     /* 171348 */     GIR_EraseRootFromParent_Done,
     /* 171349 */   // Label 3202: @171349
     /* 171349 */   GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(171464), // Rule ID 13431 //
     /* 171354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 171365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171373 */     // (intrinsic_wo_chain:{ *:[i32] } 672:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 171373 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 171376 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 171380 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171385 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171389 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 171391 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 171394 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 171398 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171403 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 171405 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 171408 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 171412 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171417 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 171420 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 171423 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 171426 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171431 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171436 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 171444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 171446 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 171453 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171458 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171463 */     // GIR_Coverage, 13431,
     /* 171463 */     GIR_EraseRootFromParent_Done,
     /* 171464 */   // Label 3203: @171464
     /* 171464 */   GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(171497), // Rule ID 13433 //
     /* 171469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 171477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 171480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 171484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171488 */     // (intrinsic_wo_chain:{ *:[i8] } 737:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 171488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 171491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171495 */     GIR_RootConstrainSelectedInstOperands,
     /* 171496 */     // GIR_Coverage, 13433,
     /* 171496 */     GIR_EraseRootFromParent_Done,
     /* 171497 */   // Label 3204: @171497
     /* 171497 */   GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(171530), // Rule ID 13435 //
     /* 171502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 171510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 171513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 171517 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171521 */     // (intrinsic_wo_chain:{ *:[i8] } 737:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 171521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 171524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171528 */     GIR_RootConstrainSelectedInstOperands,
     /* 171529 */     // GIR_Coverage, 13435,
     /* 171529 */     GIR_EraseRootFromParent_Done,
     /* 171530 */   // Label 3205: @171530
     /* 171530 */   GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(171563), // Rule ID 13437 //
     /* 171535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 171543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 171546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 171550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171554 */     // (intrinsic_wo_chain:{ *:[i16] } 737:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 171554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 171557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171561 */     GIR_RootConstrainSelectedInstOperands,
     /* 171562 */     // GIR_Coverage, 13437,
     /* 171562 */     GIR_EraseRootFromParent_Done,
     /* 171563 */   // Label 3206: @171563
     /* 171563 */   GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(171596), // Rule ID 13439 //
     /* 171568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 171576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 171579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 171583 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171587 */     // (intrinsic_wo_chain:{ *:[i16] } 737:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 171587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 171590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 171592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 171594 */     GIR_RootConstrainSelectedInstOperands,
     /* 171595 */     // GIR_Coverage, 13439,
     /* 171595 */     GIR_EraseRootFromParent_Done,
     /* 171596 */   // Label 3207: @171596
     /* 171596 */   GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(171711), // Rule ID 13440 //
     /* 171601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 171612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171616 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171620 */     // (intrinsic_wo_chain:{ *:[i32] } 737:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 171620 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 171623 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 171627 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171632 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171636 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 171638 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 171641 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 171645 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171650 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 171652 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 171655 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 171659 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171664 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 171667 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 171670 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 171673 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171678 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171683 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 171691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 171693 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 171700 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171710 */     // GIR_Coverage, 13440,
     /* 171710 */     GIR_EraseRootFromParent_Done,
     /* 171711 */   // Label 3208: @171711
     /* 171711 */   GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(171830), // Rule ID 13441 //
     /* 171716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 171727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171735 */     // (intrinsic_wo_chain:{ *:[i32] } 672:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 171735 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 171738 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 171742 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171747 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171751 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171755 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 171757 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 171760 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 171764 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171769 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 171771 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 171774 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 171778 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171783 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 171786 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 171789 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 171792 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171797 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171802 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 171810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 171812 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 171819 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171824 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171829 */     // GIR_Coverage, 13441,
     /* 171829 */     GIR_EraseRootFromParent_Done,
     /* 171830 */   // Label 3209: @171830
     /* 171830 */   GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(171945), // Rule ID 13442 //
     /* 171835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 171840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 171843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 171846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171854 */     // (intrinsic_wo_chain:{ *:[i64] } 672:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
     /* 171854 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 171857 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 171861 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171866 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171870 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 171872 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 171875 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 171879 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171884 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 171886 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 171889 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 171893 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171898 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 171901 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 171904 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 171907 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171912 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171917 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 171925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 171927 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 171934 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171939 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 171944 */     // GIR_Coverage, 13442,
     /* 171944 */     GIR_EraseRootFromParent_Done,
     /* 171945 */   // Label 3210: @171945
     /* 171945 */   GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(172064), // Rule ID 13443 //
     /* 171950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 171955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 171958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 171961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 171965 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 171969 */     // (intrinsic_wo_chain:{ *:[i32] } 737:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 171969 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 171972 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 171976 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171981 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171985 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 171989 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 171991 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 171994 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 171998 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172003 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172005 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 172008 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172012 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172017 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172020 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172023 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 172026 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172031 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172036 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172046 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 172053 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172058 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172063 */     // GIR_Coverage, 13443,
     /* 172063 */     GIR_EraseRootFromParent_Done,
     /* 172064 */   // Label 3211: @172064
     /* 172064 */   GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(172179), // Rule ID 13444 //
     /* 172069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 172074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 172077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 172080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172088 */     // (intrinsic_wo_chain:{ *:[i64] } 737:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
     /* 172088 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 172091 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 172095 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172100 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172104 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 172106 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 172109 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 172113 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172118 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172120 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 172123 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172127 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172132 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172135 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172138 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 172141 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172146 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172151 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172161 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 172168 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172173 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172178 */     // GIR_Coverage, 13444,
     /* 172178 */     GIR_EraseRootFromParent_Done,
     /* 172179 */   // Label 3212: @172179
     /* 172179 */   GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(172212), // Rule ID 13446 //
     /* 172184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 172195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172199 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172203 */     // (intrinsic_wo_chain:{ *:[i8] } 682:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 172203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 172206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172210 */     GIR_RootConstrainSelectedInstOperands,
     /* 172211 */     // GIR_Coverage, 13446,
     /* 172211 */     GIR_EraseRootFromParent_Done,
     /* 172212 */   // Label 3213: @172212
     /* 172212 */   GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(172245), // Rule ID 13448 //
     /* 172217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 172228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172232 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172236 */     // (intrinsic_wo_chain:{ *:[i8] } 682:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 172236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 172239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172243 */     GIR_RootConstrainSelectedInstOperands,
     /* 172244 */     // GIR_Coverage, 13448,
     /* 172244 */     GIR_EraseRootFromParent_Done,
     /* 172245 */   // Label 3214: @172245
     /* 172245 */   GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(172278), // Rule ID 13450 //
     /* 172250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 172258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 172261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 172265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172269 */     // (intrinsic_wo_chain:{ *:[i16] } 682:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 172269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 172272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172276 */     GIR_RootConstrainSelectedInstOperands,
     /* 172277 */     // GIR_Coverage, 13450,
     /* 172277 */     GIR_EraseRootFromParent_Done,
     /* 172278 */   // Label 3215: @172278
     /* 172278 */   GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(172311), // Rule ID 13452 //
     /* 172283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 172291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 172294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 172298 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172302 */     // (intrinsic_wo_chain:{ *:[i16] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 172302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 172305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172309 */     GIR_RootConstrainSelectedInstOperands,
     /* 172310 */     // GIR_Coverage, 13452,
     /* 172310 */     GIR_EraseRootFromParent_Done,
     /* 172311 */   // Label 3216: @172311
     /* 172311 */   GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(172426), // Rule ID 13453 //
     /* 172316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 172324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 172327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172331 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172335 */     // (intrinsic_wo_chain:{ *:[i32] } 682:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 172335 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 172338 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
     /* 172342 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172347 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172351 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 172353 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 172356 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 172360 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172365 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172367 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 172370 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172374 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172379 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172382 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172385 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 172388 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172393 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172398 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172408 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 172415 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172420 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172425 */     // GIR_Coverage, 13453,
     /* 172425 */     GIR_EraseRootFromParent_Done,
     /* 172426 */   // Label 3217: @172426
     /* 172426 */   GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(172545), // Rule ID 13454 //
     /* 172431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 172436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 172439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 172442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172446 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172450 */     // (intrinsic_wo_chain:{ *:[i32] } 682:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 172450 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 172453 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 172457 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172462 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172466 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172470 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 172472 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 172475 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 172479 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172486 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 172489 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172493 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172498 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172501 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172504 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 172507 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172512 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172517 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172527 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 172534 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172539 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172544 */     // GIR_Coverage, 13454,
     /* 172544 */     GIR_EraseRootFromParent_Done,
     /* 172545 */   // Label 3218: @172545
     /* 172545 */   GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(172578), // Rule ID 13456 //
     /* 172550 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172555 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172558 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 172561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172565 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172569 */     // (intrinsic_wo_chain:{ *:[i8] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 172569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 172572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172576 */     GIR_RootConstrainSelectedInstOperands,
     /* 172577 */     // GIR_Coverage, 13456,
     /* 172577 */     GIR_EraseRootFromParent_Done,
     /* 172578 */   // Label 3219: @172578
     /* 172578 */   GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(172611), // Rule ID 13458 //
     /* 172583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 172594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172602 */     // (intrinsic_wo_chain:{ *:[i8] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 172602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 172605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172607 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172609 */     GIR_RootConstrainSelectedInstOperands,
     /* 172610 */     // GIR_Coverage, 13458,
     /* 172610 */     GIR_EraseRootFromParent_Done,
     /* 172611 */   // Label 3220: @172611
     /* 172611 */   GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(172644), // Rule ID 13460 //
     /* 172616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 172624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 172627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 172631 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172635 */     // (intrinsic_wo_chain:{ *:[i16] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 172635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 172638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172642 */     GIR_RootConstrainSelectedInstOperands,
     /* 172643 */     // GIR_Coverage, 13460,
     /* 172643 */     GIR_EraseRootFromParent_Done,
     /* 172644 */   // Label 3221: @172644
     /* 172644 */   GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(172677), // Rule ID 13462 //
     /* 172649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 172657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 172660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 172664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172668 */     // (intrinsic_wo_chain:{ *:[i16] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 172668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 172671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172675 */     GIR_RootConstrainSelectedInstOperands,
     /* 172676 */     // GIR_Coverage, 13462,
     /* 172676 */     GIR_EraseRootFromParent_Done,
     /* 172677 */   // Label 3222: @172677
     /* 172677 */   GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(172792), // Rule ID 13463 //
     /* 172682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 172690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 172693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172701 */     // (intrinsic_wo_chain:{ *:[i32] } 685:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 172701 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 172704 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
     /* 172708 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172713 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172717 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 172719 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 172722 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 172726 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172731 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172733 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 172736 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172740 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172745 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172748 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172751 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 172754 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172759 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172764 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172774 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 172781 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172786 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172791 */     // GIR_Coverage, 13463,
     /* 172791 */     GIR_EraseRootFromParent_Done,
     /* 172792 */   // Label 3223: @172792
     /* 172792 */   GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(172911), // Rule ID 13464 //
     /* 172797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 172802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 172805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 172808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172812 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172816 */     // (intrinsic_wo_chain:{ *:[i32] } 685:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 172816 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 172819 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 172823 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172828 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172832 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 172836 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 172838 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 172841 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 172845 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172850 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 172852 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 172855 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 172859 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 172864 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 172867 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 172870 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 172873 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172878 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172883 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 172891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 172893 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 172900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 172905 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172910 */     // GIR_Coverage, 13464,
     /* 172910 */     GIR_EraseRootFromParent_Done,
     /* 172911 */   // Label 3224: @172911
     /* 172911 */   GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(172944), // Rule ID 13466 //
     /* 172916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 172921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 172927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172931 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 172935 */     // (intrinsic_wo_chain:{ *:[i8] } 743:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 172935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 172938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172940 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172942 */     GIR_RootConstrainSelectedInstOperands,
     /* 172943 */     // GIR_Coverage, 13466,
     /* 172943 */     GIR_EraseRootFromParent_Done,
     /* 172944 */   // Label 3225: @172944
     /* 172944 */   GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(172977), // Rule ID 13468 //
     /* 172949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 172954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 172957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 172960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 172964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 172968 */     // (intrinsic_wo_chain:{ *:[i8] } 743:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 172968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 172971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 172973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 172975 */     GIR_RootConstrainSelectedInstOperands,
     /* 172976 */     // GIR_Coverage, 13468,
     /* 172976 */     GIR_EraseRootFromParent_Done,
     /* 172977 */   // Label 3226: @172977
     /* 172977 */   GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(173010), // Rule ID 13470 //
     /* 172982 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 172987 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 172990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 172993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 172997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173001 */     // (intrinsic_wo_chain:{ *:[i16] } 743:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 173001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 173004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173008 */     GIR_RootConstrainSelectedInstOperands,
     /* 173009 */     // GIR_Coverage, 13470,
     /* 173009 */     GIR_EraseRootFromParent_Done,
     /* 173010 */   // Label 3227: @173010
     /* 173010 */   GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(173043), // Rule ID 13472 //
     /* 173015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 173020 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 173023 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 173026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 173030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173034 */     // (intrinsic_wo_chain:{ *:[i16] } 743:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 173034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 173037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173041 */     GIR_RootConstrainSelectedInstOperands,
     /* 173042 */     // GIR_Coverage, 13472,
     /* 173042 */     GIR_EraseRootFromParent_Done,
     /* 173043 */   // Label 3228: @173043
     /* 173043 */   GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(173158), // Rule ID 13473 //
     /* 173048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 173053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 173056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 173059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173067 */     // (intrinsic_wo_chain:{ *:[i32] } 743:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 173067 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 173070 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
     /* 173074 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173079 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173083 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 173085 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 173088 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 173092 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 173099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 173102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 173106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173111 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 173114 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 173117 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 173120 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173125 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173130 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 173138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 173140 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 173147 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173157 */     // GIR_Coverage, 13473,
     /* 173157 */     GIR_EraseRootFromParent_Done,
     /* 173158 */   // Label 3229: @173158
     /* 173158 */   GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(173277), // Rule ID 13474 //
     /* 173163 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 173168 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 173171 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 173174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173178 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173182 */     // (intrinsic_wo_chain:{ *:[i32] } 743:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 173182 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 173185 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 173189 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173194 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173198 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173202 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 173204 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 173207 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 173211 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173216 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 173218 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 173221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 173225 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173230 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 173233 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 173236 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 173239 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173244 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173249 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 173257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 173259 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 173266 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173271 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173276 */     // GIR_Coverage, 13474,
     /* 173276 */     GIR_EraseRootFromParent_Done,
     /* 173277 */   // Label 3230: @173277
     /* 173277 */   GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(173310), // Rule ID 13476 //
     /* 173282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 173290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 173293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 173297 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173301 */     // (intrinsic_wo_chain:{ *:[i8] } 746:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 173301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 173304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173308 */     GIR_RootConstrainSelectedInstOperands,
     /* 173309 */     // GIR_Coverage, 13476,
     /* 173309 */     GIR_EraseRootFromParent_Done,
     /* 173310 */   // Label 3231: @173310
     /* 173310 */   GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(173343), // Rule ID 13478 //
     /* 173315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 173323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 173326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 173330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173334 */     // (intrinsic_wo_chain:{ *:[i8] } 746:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 173334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 173337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173341 */     GIR_RootConstrainSelectedInstOperands,
     /* 173342 */     // GIR_Coverage, 13478,
     /* 173342 */     GIR_EraseRootFromParent_Done,
     /* 173343 */   // Label 3232: @173343
     /* 173343 */   GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(173376), // Rule ID 13480 //
     /* 173348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 173356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 173359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 173363 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173367 */     // (intrinsic_wo_chain:{ *:[i16] } 746:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 173367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 173370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173372 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173374 */     GIR_RootConstrainSelectedInstOperands,
     /* 173375 */     // GIR_Coverage, 13480,
     /* 173375 */     GIR_EraseRootFromParent_Done,
     /* 173376 */   // Label 3233: @173376
     /* 173376 */   GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(173409), // Rule ID 13482 //
     /* 173381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 173389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 173392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 173396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173400 */     // (intrinsic_wo_chain:{ *:[i16] } 746:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 173400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 173403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 173405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 173407 */     GIR_RootConstrainSelectedInstOperands,
     /* 173408 */     // GIR_Coverage, 13482,
     /* 173408 */     GIR_EraseRootFromParent_Done,
     /* 173409 */   // Label 3234: @173409
     /* 173409 */   GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(173524), // Rule ID 13483 //
     /* 173414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 173422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 173425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173433 */     // (intrinsic_wo_chain:{ *:[i32] } 746:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 173433 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 173436 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
     /* 173440 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173445 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173449 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 173451 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 173454 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 173458 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173463 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 173465 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 173468 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 173472 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173477 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 173480 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 173483 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 173486 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173491 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173496 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 173504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 173506 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 173513 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173518 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173523 */     // GIR_Coverage, 13483,
     /* 173523 */     GIR_EraseRootFromParent_Done,
     /* 173524 */   // Label 3235: @173524
     /* 173524 */   GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(173643), // Rule ID 13484 //
     /* 173529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 173534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 173537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 173540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173548 */     // (intrinsic_wo_chain:{ *:[i32] } 746:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 173548 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 173551 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 173555 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173560 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173564 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 173568 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 173570 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 173573 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 173577 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173582 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 173584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 173587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 173591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 173596 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 173599 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 173602 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 173605 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173610 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173615 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 173620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 173623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 173625 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 173632 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 173637 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 173642 */     // GIR_Coverage, 13484,
     /* 173642 */     GIR_EraseRootFromParent_Done,
     /* 173643 */   // Label 3236: @173643
     /* 173643 */   GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(173675), // Rule ID 2397 //
     /* 173648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b16),
     /* 173656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 173659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 173662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173666 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1679:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 173666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_H),
     /* 173669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 173673 */     GIR_RootConstrainSelectedInstOperands,
     /* 173674 */     // GIR_Coverage, 2397,
     /* 173674 */     GIR_EraseRootFromParent_Done,
     /* 173675 */   // Label 3237: @173675
     /* 173675 */   GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(173707), // Rule ID 2398 //
     /* 173680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b32),
     /* 173688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 173691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 173694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173698 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1680:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 173698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_S),
     /* 173701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 173705 */     GIR_RootConstrainSelectedInstOperands,
     /* 173706 */     // GIR_Coverage, 2398,
     /* 173706 */     GIR_EraseRootFromParent_Done,
     /* 173707 */   // Label 3238: @173707
     /* 173707 */   GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(173739), // Rule ID 2399 //
     /* 173712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b64),
     /* 173720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 173723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 173726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173730 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1681:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 173730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_D),
     /* 173733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173735 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 173737 */     GIR_RootConstrainSelectedInstOperands,
     /* 173738 */     // GIR_Coverage, 2399,
     /* 173738 */     GIR_EraseRootFromParent_Done,
     /* 173739 */   // Label 3239: @173739
     /* 173739 */   GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(173771), // Rule ID 3108 //
     /* 173744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 173747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 173752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 173755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 173758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 173762 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1861:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (SQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 173762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_B),
     /* 173765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 173767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173769 */     GIR_RootConstrainSelectedInstOperands,
     /* 173770 */     // GIR_Coverage, 3108,
     /* 173770 */     GIR_EraseRootFromParent_Done,
     /* 173771 */   // Label 3240: @173771
     /* 173771 */   GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(173803), // Rule ID 3109 //
     /* 173776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 173779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 173784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 173787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 173790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 173794 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1861:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (SQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 173794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_H),
     /* 173797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 173799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173801 */     GIR_RootConstrainSelectedInstOperands,
     /* 173802 */     // GIR_Coverage, 3109,
     /* 173802 */     GIR_EraseRootFromParent_Done,
     /* 173803 */   // Label 3241: @173803
     /* 173803 */   GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(173835), // Rule ID 3110 //
     /* 173808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 173811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 173816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 173819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 173822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 173826 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1861:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (SQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 173826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_S),
     /* 173829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 173831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173833 */     GIR_RootConstrainSelectedInstOperands,
     /* 173834 */     // GIR_Coverage, 3110,
     /* 173834 */     GIR_EraseRootFromParent_Done,
     /* 173835 */   // Label 3242: @173835
     /* 173835 */   GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(173867), // Rule ID 3368 //
     /* 173840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 173848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 173851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 173854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173858 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1671:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
     /* 173858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 173861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173865 */     GIR_RootConstrainSelectedInstOperands,
     /* 173866 */     // GIR_Coverage, 3368,
     /* 173866 */     GIR_EraseRootFromParent_Done,
     /* 173867 */   // Label 3243: @173867
     /* 173867 */   GIM_Try, /*On fail goto*//*Label 3244*/ GIMT_Encode4(173899), // Rule ID 3369 //
     /* 173872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 173880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 173883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 173886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173890 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1671:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
     /* 173890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 173893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173895 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173897 */     GIR_RootConstrainSelectedInstOperands,
     /* 173898 */     // GIR_Coverage, 3369,
     /* 173898 */     GIR_EraseRootFromParent_Done,
     /* 173899 */   // Label 3244: @173899
     /* 173899 */   GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(173931), // Rule ID 3370 //
     /* 173904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 173907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 173912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 173915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 173918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 173922 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1671:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
     /* 173922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 173925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 173927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173929 */     GIR_RootConstrainSelectedInstOperands,
     /* 173930 */     // GIR_Coverage, 3370,
     /* 173930 */     GIR_EraseRootFromParent_Done,
     /* 173931 */   // Label 3245: @173931
     /* 173931 */   GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(173963), // Rule ID 3452 //
     /* 173936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 173939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 173944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 173947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 173950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 173954 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1432:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (FEXPA_ZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i16] }:$Op1)
     /* 173954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_H),
     /* 173957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 173959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173961 */     GIR_RootConstrainSelectedInstOperands,
     /* 173962 */     // GIR_Coverage, 3452,
     /* 173962 */     GIR_EraseRootFromParent_Done,
     /* 173963 */   // Label 3246: @173963
     /* 173963 */   GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(173995), // Rule ID 3453 //
     /* 173968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 173971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 173976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 173979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 173982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 173986 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1432:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (FEXPA_ZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i32] }:$Op1)
     /* 173986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_S),
     /* 173989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 173991 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 173993 */     GIR_RootConstrainSelectedInstOperands,
     /* 173994 */     // GIR_Coverage, 3453,
     /* 173994 */     GIR_EraseRootFromParent_Done,
     /* 173995 */   // Label 3247: @173995
     /* 173995 */   GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(174027), // Rule ID 3454 //
     /* 174000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 174003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 174008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 174011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 174014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174018 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1432:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (FEXPA_ZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i64] }:$Op1)
     /* 174018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_D),
     /* 174021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174025 */     GIR_RootConstrainSelectedInstOperands,
     /* 174026 */     // GIR_Coverage, 3454,
     /* 174026 */     GIR_EraseRootFromParent_Done,
     /* 174027 */   // Label 3248: @174027
     /* 174027 */   GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(174059), // Rule ID 3479 //
     /* 174032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 174035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesmc),
     /* 174040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 174043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 174046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174050 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1271:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (AESMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
     /* 174050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMC_ZZ_B),
     /* 174053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 174055 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174057 */     GIR_RootConstrainSelectedInstOperands,
     /* 174058 */     // GIR_Coverage, 3479,
     /* 174058 */     GIR_EraseRootFromParent_Done,
     /* 174059 */   // Label 3249: @174059
     /* 174059 */   GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(174091), // Rule ID 4694 //
     /* 174064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 174067 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174072 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174075 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 174078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174082 */     // (intrinsic_wo_chain:{ *:[i32] } 602:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 174082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 174085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174089 */     GIR_RootConstrainSelectedInstOperands,
     /* 174090 */     // GIR_Coverage, 4694,
     /* 174090 */     GIR_EraseRootFromParent_Done,
     /* 174091 */   // Label 3250: @174091
     /* 174091 */   GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(174123), // Rule ID 4695 //
     /* 174096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 174099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 174110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174114 */     // (intrinsic_wo_chain:{ *:[i64] } 602:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 174114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 174117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174121 */     GIR_RootConstrainSelectedInstOperands,
     /* 174122 */     // GIR_Coverage, 4695,
     /* 174122 */     GIR_EraseRootFromParent_Done,
     /* 174123 */   // Label 3251: @174123
     /* 174123 */   GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(174152), // Rule ID 4696 //
     /* 174128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 174139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174143 */     // (intrinsic_wo_chain:{ *:[i32] } 602:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 174143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 174146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174150 */     GIR_RootConstrainSelectedInstOperands,
     /* 174151 */     // GIR_Coverage, 4696,
     /* 174151 */     GIR_EraseRootFromParent_Done,
     /* 174152 */   // Label 3252: @174152
     /* 174152 */   GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(174181), // Rule ID 4697 //
     /* 174157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 174168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174172 */     // (intrinsic_wo_chain:{ *:[i64] } 602:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 174172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 174175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174179 */     GIR_RootConstrainSelectedInstOperands,
     /* 174180 */     // GIR_Coverage, 4697,
     /* 174180 */     GIR_EraseRootFromParent_Done,
     /* 174181 */   // Label 3253: @174181
     /* 174181 */   GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(174210), // Rule ID 4698 //
     /* 174186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 174197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174201 */     // (intrinsic_wo_chain:{ *:[i32] } 602:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 174201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 174204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174208 */     GIR_RootConstrainSelectedInstOperands,
     /* 174209 */     // GIR_Coverage, 4698,
     /* 174209 */     GIR_EraseRootFromParent_Done,
     /* 174210 */   // Label 3254: @174210
     /* 174210 */   GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(174239), // Rule ID 4699 //
     /* 174215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 174226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174230 */     // (intrinsic_wo_chain:{ *:[i64] } 602:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 174230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 174233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174237 */     GIR_RootConstrainSelectedInstOperands,
     /* 174238 */     // GIR_Coverage, 4699,
     /* 174238 */     GIR_EraseRootFromParent_Done,
     /* 174239 */   // Label 3255: @174239
     /* 174239 */   GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(174271), // Rule ID 4706 //
     /* 174244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 174247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 174258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174262 */     // (intrinsic_wo_chain:{ *:[i32] } 603:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 174262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 174265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174269 */     GIR_RootConstrainSelectedInstOperands,
     /* 174270 */     // GIR_Coverage, 4706,
     /* 174270 */     GIR_EraseRootFromParent_Done,
     /* 174271 */   // Label 3256: @174271
     /* 174271 */   GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(174303), // Rule ID 4707 //
     /* 174276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 174279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 174290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174294 */     // (intrinsic_wo_chain:{ *:[i64] } 603:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 174294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 174297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174299 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174301 */     GIR_RootConstrainSelectedInstOperands,
     /* 174302 */     // GIR_Coverage, 4707,
     /* 174302 */     GIR_EraseRootFromParent_Done,
     /* 174303 */   // Label 3257: @174303
     /* 174303 */   GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(174332), // Rule ID 4708 //
     /* 174308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 174319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174323 */     // (intrinsic_wo_chain:{ *:[i32] } 603:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 174323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 174326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174328 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174330 */     GIR_RootConstrainSelectedInstOperands,
     /* 174331 */     // GIR_Coverage, 4708,
     /* 174331 */     GIR_EraseRootFromParent_Done,
     /* 174332 */   // Label 3258: @174332
     /* 174332 */   GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(174361), // Rule ID 4709 //
     /* 174337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 174348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174352 */     // (intrinsic_wo_chain:{ *:[i64] } 603:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 174352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 174355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174359 */     GIR_RootConstrainSelectedInstOperands,
     /* 174360 */     // GIR_Coverage, 4709,
     /* 174360 */     GIR_EraseRootFromParent_Done,
     /* 174361 */   // Label 3259: @174361
     /* 174361 */   GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(174390), // Rule ID 4710 //
     /* 174366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 174374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 174377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174381 */     // (intrinsic_wo_chain:{ *:[i32] } 603:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 174381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 174384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174386 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174388 */     GIR_RootConstrainSelectedInstOperands,
     /* 174389 */     // GIR_Coverage, 4710,
     /* 174389 */     GIR_EraseRootFromParent_Done,
     /* 174390 */   // Label 3260: @174390
     /* 174390 */   GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(174419), // Rule ID 4711 //
     /* 174395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 174403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 174406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174410 */     // (intrinsic_wo_chain:{ *:[i64] } 603:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 174410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 174413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174417 */     GIR_RootConstrainSelectedInstOperands,
     /* 174418 */     // GIR_Coverage, 4711,
     /* 174418 */     GIR_EraseRootFromParent_Done,
     /* 174419 */   // Label 3261: @174419
     /* 174419 */   GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(174448), // Rule ID 5006 //
     /* 174424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 174432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 174435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 174439 */     // (intrinsic_wo_chain:{ *:[v4i16] } 602:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
     /* 174439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 174442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174446 */     GIR_RootConstrainSelectedInstOperands,
     /* 174447 */     // GIR_Coverage, 5006,
     /* 174447 */     GIR_EraseRootFromParent_Done,
     /* 174448 */   // Label 3262: @174448
     /* 174448 */   GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(174477), // Rule ID 5007 //
     /* 174453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 174461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 174464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174468 */     // (intrinsic_wo_chain:{ *:[v8i16] } 602:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
     /* 174468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 174471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174475 */     GIR_RootConstrainSelectedInstOperands,
     /* 174476 */     // GIR_Coverage, 5007,
     /* 174476 */     GIR_EraseRootFromParent_Done,
     /* 174477 */   // Label 3263: @174477
     /* 174477 */   GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(174506), // Rule ID 5008 //
     /* 174482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 174490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 174493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 174497 */     // (intrinsic_wo_chain:{ *:[v2i32] } 602:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
     /* 174497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 174500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174504 */     GIR_RootConstrainSelectedInstOperands,
     /* 174505 */     // GIR_Coverage, 5008,
     /* 174505 */     GIR_EraseRootFromParent_Done,
     /* 174506 */   // Label 3264: @174506
     /* 174506 */   GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(174535), // Rule ID 5009 //
     /* 174511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 174519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 174522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174526 */     // (intrinsic_wo_chain:{ *:[v4i32] } 602:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
     /* 174526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 174529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174533 */     GIR_RootConstrainSelectedInstOperands,
     /* 174534 */     // GIR_Coverage, 5009,
     /* 174534 */     GIR_EraseRootFromParent_Done,
     /* 174535 */   // Label 3265: @174535
     /* 174535 */   GIM_Try, /*On fail goto*//*Label 3266*/ GIMT_Encode4(174564), // Rule ID 5010 //
     /* 174540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 174545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 174548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 174551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174555 */     // (intrinsic_wo_chain:{ *:[v2i64] } 602:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
     /* 174555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 174558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174562 */     GIR_RootConstrainSelectedInstOperands,
     /* 174563 */     // GIR_Coverage, 5010,
     /* 174563 */     GIR_EraseRootFromParent_Done,
     /* 174564 */   // Label 3266: @174564
     /* 174564 */   GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(174593), // Rule ID 5011 //
     /* 174569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 174577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 174580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 174584 */     // (intrinsic_wo_chain:{ *:[v4i16] } 603:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
     /* 174584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 174587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174589 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174591 */     GIR_RootConstrainSelectedInstOperands,
     /* 174592 */     // GIR_Coverage, 5011,
     /* 174592 */     GIR_EraseRootFromParent_Done,
     /* 174593 */   // Label 3267: @174593
     /* 174593 */   GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(174622), // Rule ID 5012 //
     /* 174598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 174606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 174609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174613 */     // (intrinsic_wo_chain:{ *:[v8i16] } 603:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
     /* 174613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 174616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174620 */     GIR_RootConstrainSelectedInstOperands,
     /* 174621 */     // GIR_Coverage, 5012,
     /* 174621 */     GIR_EraseRootFromParent_Done,
     /* 174622 */   // Label 3268: @174622
     /* 174622 */   GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(174651), // Rule ID 5013 //
     /* 174627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 174635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 174638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 174642 */     // (intrinsic_wo_chain:{ *:[v2i32] } 603:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
     /* 174642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 174645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174649 */     GIR_RootConstrainSelectedInstOperands,
     /* 174650 */     // GIR_Coverage, 5013,
     /* 174650 */     GIR_EraseRootFromParent_Done,
     /* 174651 */   // Label 3269: @174651
     /* 174651 */   GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(174680), // Rule ID 5014 //
     /* 174656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 174664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 174667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174671 */     // (intrinsic_wo_chain:{ *:[v4i32] } 603:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
     /* 174671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 174674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174678 */     GIR_RootConstrainSelectedInstOperands,
     /* 174679 */     // GIR_Coverage, 5014,
     /* 174679 */     GIR_EraseRootFromParent_Done,
     /* 174680 */   // Label 3270: @174680
     /* 174680 */   GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(174709), // Rule ID 5015 //
     /* 174685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 174690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 174693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 174696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 174700 */     // (intrinsic_wo_chain:{ *:[v2i64] } 603:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
     /* 174700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 174703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 174705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 174707 */     GIR_RootConstrainSelectedInstOperands,
     /* 174708 */     // GIR_Coverage, 5015,
     /* 174708 */     GIR_EraseRootFromParent_Done,
     /* 174709 */   // Label 3271: @174709
     /* 174709 */   GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(174741), // Rule ID 8526 //
     /* 174714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 174717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 174722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 174725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 174728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 174732 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1670:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
     /* 174732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 174735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 174737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174739 */     GIR_RootConstrainSelectedInstOperands,
     /* 174740 */     // GIR_Coverage, 8526,
     /* 174740 */     GIR_EraseRootFromParent_Done,
     /* 174741 */   // Label 3272: @174741
     /* 174741 */   GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(174773), // Rule ID 8527 //
     /* 174746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 174749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 174754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 174757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 174760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 174764 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1670:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
     /* 174764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 174767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 174769 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174771 */     GIR_RootConstrainSelectedInstOperands,
     /* 174772 */     // GIR_Coverage, 8527,
     /* 174772 */     GIR_EraseRootFromParent_Done,
     /* 174773 */   // Label 3273: @174773
     /* 174773 */   GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(174805), // Rule ID 8528 //
     /* 174778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 174781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 174786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 174789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 174792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 174796 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1670:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
     /* 174796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 174799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 174801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174803 */     GIR_RootConstrainSelectedInstOperands,
     /* 174804 */     // GIR_Coverage, 8528,
     /* 174804 */     GIR_EraseRootFromParent_Done,
     /* 174805 */   // Label 3274: @174805
     /* 174805 */   GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(174837), // Rule ID 11951 //
     /* 174810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 174818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 174821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 174824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174828 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2054:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (UQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 174828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_B),
     /* 174831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174833 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174835 */     GIR_RootConstrainSelectedInstOperands,
     /* 174836 */     // GIR_Coverage, 11951,
     /* 174836 */     GIR_EraseRootFromParent_Done,
     /* 174837 */   // Label 3275: @174837
     /* 174837 */   GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(174869), // Rule ID 11952 //
     /* 174842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174845 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 174850 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 174853 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 174856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174860 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2054:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (UQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 174860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_H),
     /* 174863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174867 */     GIR_RootConstrainSelectedInstOperands,
     /* 174868 */     // GIR_Coverage, 11952,
     /* 174868 */     GIR_EraseRootFromParent_Done,
     /* 174869 */   // Label 3276: @174869
     /* 174869 */   GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(174901), // Rule ID 11953 //
     /* 174874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 174882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 174885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 174888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174892 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2054:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (UQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 174892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_S),
     /* 174895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174899 */     GIR_RootConstrainSelectedInstOperands,
     /* 174900 */     // GIR_Coverage, 11953,
     /* 174900 */     GIR_EraseRootFromParent_Done,
     /* 174901 */   // Label 3277: @174901
     /* 174901 */   GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(174933), // Rule ID 11954 //
     /* 174906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 174914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 174917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 174920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174924 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1863:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (SQXTUNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 174924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_B),
     /* 174927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174929 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174931 */     GIR_RootConstrainSelectedInstOperands,
     /* 174932 */     // GIR_Coverage, 11954,
     /* 174932 */     GIR_EraseRootFromParent_Done,
     /* 174933 */   // Label 3278: @174933
     /* 174933 */   GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(174965), // Rule ID 11955 //
     /* 174938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 174946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 174949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 174952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174956 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1863:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (SQXTUNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 174956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_H),
     /* 174959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174963 */     GIR_RootConstrainSelectedInstOperands,
     /* 174964 */     // GIR_Coverage, 11955,
     /* 174964 */     GIR_EraseRootFromParent_Done,
     /* 174965 */   // Label 3279: @174965
     /* 174965 */   GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(174997), // Rule ID 11956 //
     /* 174970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 174973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 174978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 174981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 174984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 174988 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1863:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (SQXTUNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 174988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_S),
     /* 174991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 174993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 174995 */     GIR_RootConstrainSelectedInstOperands,
     /* 174996 */     // GIR_Coverage, 11956,
     /* 174996 */     GIR_EraseRootFromParent_Done,
     /* 174997 */   // Label 3280: @174997
     /* 174997 */   GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(175029), // Rule ID 12270 //
     /* 175002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 175005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesimc),
     /* 175010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 175013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 175016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 175020 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1270:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (AESIMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
     /* 175020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMC_ZZ_B),
     /* 175023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 175025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 175027 */     GIR_RootConstrainSelectedInstOperands,
     /* 175028 */     // GIR_Coverage, 12270,
     /* 175028 */     GIR_EraseRootFromParent_Done,
     /* 175029 */   // Label 3281: @175029
     /* 175029 */   GIM_Reject,
     /* 175030 */ // Label 2962: @175030
     /* 175030 */ GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(217467),
     /* 175035 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 175038 */   GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(175222), // Rule ID 2568 //
     /* 175043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 175051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 175054 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 175057 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 175060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175064 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 175076 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175080 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 175084 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175088 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 175092 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 175095 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175100 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 175104 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 175108 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175113 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 175117 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 175121 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175125 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 175129 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 175133 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175137 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 175141 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 175146 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 175150 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175154 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 175158 */     // MIs[5] Operand 1
     /* 175158 */     // No operand predicates
     /* 175158 */     // MIs[3] Operand 2
     /* 175158 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /* 175169 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 175173 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /* 175175 */     // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 175175 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 175178 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 175182 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 175187 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 175193 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 175198 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 175206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 175208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 175210 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 175213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /* 175217 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // idx
     /* 175220 */     GIR_RootConstrainSelectedInstOperands,
     /* 175221 */     // GIR_Coverage, 2568,
     /* 175221 */     GIR_EraseRootFromParent_Done,
     /* 175222 */   // Label 3283: @175222
     /* 175222 */   GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(175406), // Rule ID 6335 //
     /* 175227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 175235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 175238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 175241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 175244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175248 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175252 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175256 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 175260 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175264 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 175268 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175272 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 175276 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 175279 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175284 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 175288 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 175292 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175297 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 175301 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 175305 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175309 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 175313 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 175317 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175321 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 175325 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 175330 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 175334 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175338 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 175342 */     // MIs[5] Operand 1
     /* 175342 */     // No operand predicates
     /* 175342 */     // MIs[3] Operand 2
     /* 175342 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /* 175353 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 175357 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /* 175359 */     // (intrinsic_wo_chain:{ *:[i32] } 708:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 175359 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 175362 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 175366 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 175371 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 175377 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 175382 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 175390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 175392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 175394 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 175397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /* 175401 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // idx
     /* 175404 */     GIR_RootConstrainSelectedInstOperands,
     /* 175405 */     // GIR_Coverage, 6335,
     /* 175405 */     GIR_EraseRootFromParent_Done,
     /* 175406 */   // Label 3284: @175406
     /* 175406 */   GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(175567), // Rule ID 2569 //
     /* 175411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 175419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 175422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 175425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 175428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 175444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175448 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 175452 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175456 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 175460 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 175463 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175468 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 175472 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 175476 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175481 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 175485 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 175489 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175493 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 175497 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 175502 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 175506 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175510 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 175514 */     // MIs[4] Operand 1
     /* 175514 */     // No operand predicates
     /* 175514 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 175518 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 175520 */     // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 175520 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 175523 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 175527 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 175532 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 175538 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 175543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 175551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 175553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 175555 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 175558 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 175562 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 175565 */     GIR_RootConstrainSelectedInstOperands,
     /* 175566 */     // GIR_Coverage, 2569,
     /* 175566 */     GIR_EraseRootFromParent_Done,
     /* 175567 */   // Label 3285: @175567
     /* 175567 */   GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(175728), // Rule ID 6336 //
     /* 175572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 175580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 175583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 175586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 175589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175593 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 175597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 175605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175609 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 175613 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175617 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 175621 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 175624 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175629 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 175633 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 175637 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175642 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 175646 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 175650 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175654 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 175658 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 175663 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 175667 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175671 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 175675 */     // MIs[4] Operand 1
     /* 175675 */     // No operand predicates
     /* 175675 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 175679 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 175681 */     // (intrinsic_wo_chain:{ *:[i32] } 708:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 175681 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 175684 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 175688 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 175693 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 175699 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 175704 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 175712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 175714 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 175716 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 175719 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 175723 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 175726 */     GIR_RootConstrainSelectedInstOperands,
     /* 175727 */     // GIR_Coverage, 6336,
     /* 175727 */     GIR_EraseRootFromParent_Done,
     /* 175728 */   // Label 3286: @175728
     /* 175728 */   GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(175838), // Rule ID 2089 //
     /* 175733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 175744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 175747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 175750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 175754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 175762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175766 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175770 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 175774 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 175778 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 175782 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 175787 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 175791 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175795 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 175799 */     // MIs[3] Operand 1
     /* 175799 */     // No operand predicates
     /* 175799 */     // MIs[1] Operand 2
     /* 175799 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 175810 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 175812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 175819 */     // (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (SQDMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 175819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv8i16_indexed),
     /* 175822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 175824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 175829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 175833 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 175836 */     GIR_RootConstrainSelectedInstOperands,
     /* 175837 */     // GIR_Coverage, 2089,
     /* 175837 */     GIR_EraseRootFromParent_Done,
     /* 175838 */   // Label 3287: @175838
     /* 175838 */   GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(175948), // Rule ID 2092 //
     /* 175843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 175846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 175851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 175854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 175857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 175860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 175864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 175868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 175872 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175876 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 175880 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 175884 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175888 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 175892 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 175897 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 175901 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 175905 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 175909 */     // MIs[3] Operand 1
     /* 175909 */     // No operand predicates
     /* 175909 */     // MIs[1] Operand 2
     /* 175909 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 175920 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 175922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 175929 */     // (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (SQDMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 175929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i32_indexed),
     /* 175932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 175934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 175939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 175943 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 175946 */     GIR_RootConstrainSelectedInstOperands,
     /* 175947 */     // GIR_Coverage, 2092,
     /* 175947 */     GIR_EraseRootFromParent_Done,
     /* 175948 */   // Label 3288: @175948
     /* 175948 */   GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(176070), // Rule ID 6997 //
     /* 175953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 175958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 175961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 175964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 175967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 175971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 175975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 175979 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 175983 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 175988 */     // MIs[1] Operand 2
     /* 175988 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 175999 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 176003 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176007 */     // MIs[2] Rn
     /* 176007 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 176012 */     // MIs[2] Operand 2
     /* 176012 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 176023 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176025 */     // (intrinsic_wo_chain:{ *:[v2i32] } 580:{ *:[iPTR] }, (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 176025 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 176028 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /* 176032 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176037 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176041 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176045 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 176047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176052 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 176059 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176064 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176069 */     // GIR_Coverage, 6997,
     /* 176069 */     GIR_EraseRootFromParent_Done,
     /* 176070 */   // Label 3289: @176070
     /* 176070 */   GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(176192), // Rule ID 6999 //
     /* 176075 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 176080 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 176083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 176086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 176089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 176097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 176105 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176110 */     // MIs[1] Operand 2
     /* 176110 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 176121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 176125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176129 */     // MIs[2] Rn
     /* 176129 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 176134 */     // MIs[2] Operand 2
     /* 176134 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 176145 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176147 */     // (intrinsic_wo_chain:{ *:[v4i16] } 580:{ *:[iPTR] }, (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /* 176147 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 176150 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /* 176154 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176159 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176163 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176167 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 176169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176174 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 176181 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176186 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176191 */     // GIR_Coverage, 6999,
     /* 176191 */     GIR_EraseRootFromParent_Done,
     /* 176192 */   // Label 3290: @176192
     /* 176192 */   GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(176314), // Rule ID 7001 //
     /* 176197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 176202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 176205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 176208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 176211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176215 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 176219 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176223 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 176227 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176232 */     // MIs[1] Operand 2
     /* 176232 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 176243 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 176247 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176251 */     // MIs[2] Rn
     /* 176251 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 176256 */     // MIs[2] Operand 2
     /* 176256 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 176267 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176269 */     // (intrinsic_wo_chain:{ *:[v8i8] } 580:{ *:[iPTR] }, (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /* 176269 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 176272 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /* 176276 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176281 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176285 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176289 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 176291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176296 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 176303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176313 */     // GIR_Coverage, 7001,
     /* 176313 */     GIR_EraseRootFromParent_Done,
     /* 176314 */   // Label 3291: @176314
     /* 176314 */   GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(176436), // Rule ID 7003 //
     /* 176319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 176324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 176327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 176330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 176333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176337 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 176341 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176345 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 176349 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176354 */     // MIs[1] Operand 2
     /* 176354 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 176365 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 176369 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176373 */     // MIs[2] Rn
     /* 176373 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 176378 */     // MIs[2] Operand 2
     /* 176378 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 176389 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176391 */     // (intrinsic_wo_chain:{ *:[v2f32] } 589:{ *:[iPTR] }, (extract_subvector:{ *:[v2f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2f32] } FPR128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (FADDPv4f32:{ *:[f128] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] })
     /* 176391 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 176394 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 176398 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176403 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176407 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176411 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 176413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176418 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 176425 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176430 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176435 */     // GIR_Coverage, 7003,
     /* 176435 */     GIR_EraseRootFromParent_Done,
     /* 176436 */   // Label 3292: @176436
     /* 176436 */   GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(176558), // Rule ID 7005 //
     /* 176441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 176446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 176449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 176452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 176455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 176463 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176467 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 176471 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176476 */     // MIs[1] Operand 2
     /* 176476 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 176487 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 176491 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176495 */     // MIs[2] Rn
     /* 176495 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 176500 */     // MIs[2] Operand 2
     /* 176500 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 176511 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176513 */     // (intrinsic_wo_chain:{ *:[v4f16] } 589:{ *:[iPTR] }, (extract_subvector:{ *:[v4f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4f16] } FPR128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (FADDPv8f16:{ *:[f128] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rn), dsub:{ *:[i32] })
     /* 176513 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 176516 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 176520 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176525 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176529 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 176533 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 176535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176540 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 176547 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176552 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176557 */     // GIR_Coverage, 7005,
     /* 176557 */     GIR_EraseRootFromParent_Done,
     /* 176558 */   // Label 3293: @176558
     /* 176558 */   GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(176741), // Rule ID 2567 //
     /* 176563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 176566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 176571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 176574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 176577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 176580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 176584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 176588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 176592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 176596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 176600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 176604 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 176608 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 176612 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 176615 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 176620 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 176624 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 176628 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176633 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176638 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 176642 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176644 */     // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 176644 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 176647 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 176651 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176656 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 176658 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 176661 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 176665 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176670 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 176673 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /* 176677 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 176680 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176685 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176690 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176695 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 176698 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176702 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176707 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 176713 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 176718 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 176726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 176730 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 176733 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 176736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 176739 */     GIR_RootConstrainSelectedInstOperands,
     /* 176740 */     // GIR_Coverage, 2567,
     /* 176740 */     GIR_EraseRootFromParent_Done,
     /* 176741 */   // Label 3294: @176741
     /* 176741 */   GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(176924), // Rule ID 6334 //
     /* 176746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 176749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 176754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 176757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 176760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 176763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 176767 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 176771 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 176775 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 176779 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 176783 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 176787 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 176791 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 176795 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 176798 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 176803 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 176807 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 176811 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176821 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 176825 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 176827 */     // (intrinsic_wo_chain:{ *:[i32] } 708:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 176827 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 176830 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 176834 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176839 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 176841 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 176844 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 176848 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176853 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 176856 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /* 176860 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 176863 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176868 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 176873 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176878 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 176881 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 176885 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 176890 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 176896 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 176901 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 176909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 176911 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 176913 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 176916 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 176919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 176922 */     GIR_RootConstrainSelectedInstOperands,
     /* 176923 */     // GIR_Coverage, 6334,
     /* 176923 */     GIR_EraseRootFromParent_Done,
     /* 176924 */   // Label 3295: @176924
     /* 176924 */   GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(177028), // Rule ID 13741 //
     /* 176929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 176932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 176937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 176940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 176943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 176946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 176950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 176954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 176958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 176962 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 176966 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 176970 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 176974 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 176978 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 176983 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 176987 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 176991 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 176995 */     // MIs[3] Operand 1
     /* 176995 */     // No operand predicates
     /* 176995 */     // MIs[1] Operand 2
     /* 176995 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 177006 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177010 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177012 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 177012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 177015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 177019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 177023 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 177026 */     GIR_RootConstrainSelectedInstOperands,
     /* 177027 */     // GIR_Coverage, 13741,
     /* 177027 */     GIR_EraseRootFromParent_Done,
     /* 177028 */   // Label 3296: @177028
     /* 177028 */   GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(177132), // Rule ID 13744 //
     /* 177033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 177044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 177047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 177050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 177062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177066 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 177070 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 177074 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177078 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 177082 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177087 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 177091 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177095 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 177099 */     // MIs[3] Operand 1
     /* 177099 */     // No operand predicates
     /* 177099 */     // MIs[1] Operand 2
     /* 177099 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 177110 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177114 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177116 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 177116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 177119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177121 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 177123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 177127 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 177130 */     GIR_RootConstrainSelectedInstOperands,
     /* 177131 */     // GIR_Coverage, 13744,
     /* 177131 */     GIR_EraseRootFromParent_Done,
     /* 177132 */   // Label 3297: @177132
     /* 177132 */   GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(177263), // Rule ID 2524 //
     /* 177137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 177140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 177148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 177151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 177154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 177170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177174 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177179 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 177183 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 177187 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177191 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 177195 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 177199 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177204 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 177208 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177212 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 177216 */     // MIs[3] Operand 1
     /* 177216 */     // No operand predicates
     /* 177216 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177218 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 177218 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 177221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177225 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177230 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 177236 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177241 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 177249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177251 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 177258 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 177261 */     GIR_RootConstrainSelectedInstOperands,
     /* 177262 */     // GIR_Coverage, 2524,
     /* 177262 */     GIR_EraseRootFromParent_Done,
     /* 177263 */   // Label 3298: @177263
     /* 177263 */   GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(177394), // Rule ID 2525 //
     /* 177268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 177279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 177282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 177285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 177289 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177293 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177297 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177301 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177305 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177310 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 177314 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 177318 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177322 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177326 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 177330 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177335 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 177339 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177343 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 177347 */     // MIs[3] Operand 1
     /* 177347 */     // No operand predicates
     /* 177347 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177349 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 177349 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 177352 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177356 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177361 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 177367 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 177372 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 177380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177382 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 177389 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 177392 */     GIR_RootConstrainSelectedInstOperands,
     /* 177393 */     // GIR_Coverage, 2525,
     /* 177393 */     GIR_EraseRootFromParent_Done,
     /* 177394 */   // Label 3299: @177394
     /* 177394 */   GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(177525), // Rule ID 2526 //
     /* 177399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 177410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 177413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 177416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177424 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177428 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 177432 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177436 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177441 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 177445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 177449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177453 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 177457 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 177461 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177466 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 177470 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177474 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 177478 */     // MIs[3] Operand 1
     /* 177478 */     // No operand predicates
     /* 177478 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177480 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 177480 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 177483 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177487 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177492 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 177498 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177503 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 177511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177513 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 177520 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 177523 */     GIR_RootConstrainSelectedInstOperands,
     /* 177524 */     // GIR_Coverage, 2526,
     /* 177524 */     GIR_EraseRootFromParent_Done,
     /* 177525 */   // Label 3300: @177525
     /* 177525 */   GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(177656), // Rule ID 13933 //
     /* 177530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 177533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 177541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 177544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 177547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 177563 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177567 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177572 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 177576 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177580 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 177584 */     // MIs[2] Operand 1
     /* 177584 */     // No operand predicates
     /* 177584 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 177588 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177592 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 177596 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 177600 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177605 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 177609 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177611 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 177611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 177614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177623 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 177629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177634 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 177642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177644 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 177651 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 177654 */     GIR_RootConstrainSelectedInstOperands,
     /* 177655 */     // GIR_Coverage, 13933,
     /* 177655 */     GIR_EraseRootFromParent_Done,
     /* 177656 */   // Label 3301: @177656
     /* 177656 */   GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(177787), // Rule ID 13934 //
     /* 177661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 177672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 177675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 177678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 177682 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177686 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177690 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177694 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177698 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177703 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 177707 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177711 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 177715 */     // MIs[2] Operand 1
     /* 177715 */     // No operand predicates
     /* 177715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 177719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177723 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177727 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 177731 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177736 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 177740 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177742 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 177742 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 177745 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177749 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177754 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 177760 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 177765 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 177773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177775 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 177782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 177785 */     GIR_RootConstrainSelectedInstOperands,
     /* 177786 */     // GIR_Coverage, 13934,
     /* 177786 */     GIR_EraseRootFromParent_Done,
     /* 177787 */   // Label 3302: @177787
     /* 177787 */   GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(177918), // Rule ID 13935 //
     /* 177792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 177800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 177803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 177806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 177809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 177817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 177825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 177829 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177834 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 177838 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 177842 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 177846 */     // MIs[2] Operand 1
     /* 177846 */     // No operand predicates
     /* 177846 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 177850 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177854 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 177858 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 177862 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177867 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 177871 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 177873 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 177873 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 177876 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 177880 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 177885 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 177891 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177896 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 177904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 177906 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 177909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 177913 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 177916 */     GIR_RootConstrainSelectedInstOperands,
     /* 177917 */     // GIR_Coverage, 13935,
     /* 177917 */     GIR_EraseRootFromParent_Done,
     /* 177918 */   // Label 3303: @177918
     /* 177918 */   GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(178032), // Rule ID 2065 //
     /* 177923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 177926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 177931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 177934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 177937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 177940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 177952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 177956 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 177959 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 177964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 177968 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 177972 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 177977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 177981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 177985 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 177989 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 177993 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 177998 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178002 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178006 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178010 */     // MIs[3] Operand 1
     /* 178010 */     // No operand predicates
     /* 178010 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178012 */     // (intrinsic_wo_chain:{ *:[i64] } 689:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLALv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i64_indexed),
     /* 178015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 178017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 178019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 178023 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178027 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178030 */     GIR_RootConstrainSelectedInstOperands,
     /* 178031 */     // GIR_Coverage, 2065,
     /* 178031 */     GIR_EraseRootFromParent_Done,
     /* 178032 */   // Label 3304: @178032
     /* 178032 */   GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(178146), // Rule ID 2072 //
     /* 178037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 178045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 178048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 178051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 178054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 178070 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 178073 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 178078 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 178082 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 178086 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 178095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 178099 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178103 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178107 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178112 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178116 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178120 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178124 */     // MIs[3] Operand 1
     /* 178124 */     // No operand predicates
     /* 178124 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178126 */     // (intrinsic_wo_chain:{ *:[i64] } 708:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLSLv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i64_indexed),
     /* 178129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 178131 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 178133 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 178137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178141 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178144 */     GIR_RootConstrainSelectedInstOperands,
     /* 178145 */     // GIR_Coverage, 2072,
     /* 178145 */     GIR_EraseRootFromParent_Done,
     /* 178146 */   // Label 3305: @178146
     /* 178146 */   GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(178250), // Rule ID 1991 //
     /* 178151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 178154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 178159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 178162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 178165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 178168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178172 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178188 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178192 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 178196 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178200 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178204 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 178209 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178213 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178217 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 178221 */     // MIs[3] Operand 1
     /* 178221 */     // No operand predicates
     /* 178221 */     // MIs[1] Operand 2
     /* 178221 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178232 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178234 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 178237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178239 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178245 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178248 */     GIR_RootConstrainSelectedInstOperands,
     /* 178249 */     // GIR_Coverage, 1991,
     /* 178249 */     GIR_EraseRootFromParent_Done,
     /* 178250 */   // Label 3306: @178250
     /* 178250 */   GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(178354), // Rule ID 2021 //
     /* 178255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 178263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 178266 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 178269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 178272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178276 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178292 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178296 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 178300 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178304 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178308 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 178313 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178317 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178321 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 178325 */     // MIs[3] Operand 1
     /* 178325 */     // No operand predicates
     /* 178325 */     // MIs[1] Operand 2
     /* 178325 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178336 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178338 */     // (intrinsic_wo_chain:{ *:[v4i16] } 690:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16_indexed),
     /* 178341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178345 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178349 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178352 */     GIR_RootConstrainSelectedInstOperands,
     /* 178353 */     // GIR_Coverage, 2021,
     /* 178353 */     GIR_EraseRootFromParent_Done,
     /* 178354 */   // Label 3307: @178354
     /* 178354 */   GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(178458), // Rule ID 2028 //
     /* 178359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 178367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 178370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 178373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 178376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 178404 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178408 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178412 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 178417 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178421 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178425 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 178429 */     // MIs[3] Operand 1
     /* 178429 */     // No operand predicates
     /* 178429 */     // MIs[1] Operand 2
     /* 178429 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178440 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178442 */     // (intrinsic_wo_chain:{ *:[v4i16] } 698:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16_indexed),
     /* 178445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178453 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178456 */     GIR_RootConstrainSelectedInstOperands,
     /* 178457 */     // GIR_Coverage, 2028,
     /* 178457 */     GIR_EraseRootFromParent_Done,
     /* 178458 */   // Label 3308: @178458
     /* 178458 */   GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(178562), // Rule ID 2087 //
     /* 178463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 178471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 178474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 178477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 178480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178488 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178492 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178496 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178500 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178504 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 178508 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 178512 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178516 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 178521 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178525 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178529 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 178533 */     // MIs[3] Operand 1
     /* 178533 */     // No operand predicates
     /* 178533 */     // MIs[1] Operand 2
     /* 178533 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178544 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178546 */     // (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_indexed),
     /* 178549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178551 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178553 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178557 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178560 */     GIR_RootConstrainSelectedInstOperands,
     /* 178561 */     // GIR_Coverage, 2087,
     /* 178561 */     GIR_EraseRootFromParent_Done,
     /* 178562 */   // Label 3309: @178562
     /* 178562 */   GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(178666), // Rule ID 1994 //
     /* 178567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178570 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 178575 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 178578 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 178581 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 178584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178604 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178608 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 178612 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178616 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178620 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178625 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178629 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178633 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178637 */     // MIs[3] Operand 1
     /* 178637 */     // No operand predicates
     /* 178637 */     // MIs[1] Operand 2
     /* 178637 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178648 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178650 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 178653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178657 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178661 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178664 */     GIR_RootConstrainSelectedInstOperands,
     /* 178665 */     // GIR_Coverage, 1994,
     /* 178665 */     GIR_EraseRootFromParent_Done,
     /* 178666 */   // Label 3310: @178666
     /* 178666 */   GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(178770), // Rule ID 2024 //
     /* 178671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 178679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 178682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 178685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 178688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178708 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178712 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 178716 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178720 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178724 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178729 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178733 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178737 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178741 */     // MIs[3] Operand 1
     /* 178741 */     // No operand predicates
     /* 178741 */     // MIs[1] Operand 2
     /* 178741 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178752 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178754 */     // (intrinsic_wo_chain:{ *:[v2i32] } 690:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32_indexed),
     /* 178757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178759 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178765 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178768 */     GIR_RootConstrainSelectedInstOperands,
     /* 178769 */     // GIR_Coverage, 2024,
     /* 178769 */     GIR_EraseRootFromParent_Done,
     /* 178770 */   // Label 3311: @178770
     /* 178770 */   GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(178874), // Rule ID 2031 //
     /* 178775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178778 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 178783 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 178786 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 178789 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 178792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178796 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178812 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178816 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 178820 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178824 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178828 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178833 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178837 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178841 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178845 */     // MIs[3] Operand 1
     /* 178845 */     // No operand predicates
     /* 178845 */     // MIs[1] Operand 2
     /* 178845 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178856 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178858 */     // (intrinsic_wo_chain:{ *:[v2i32] } 698:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32_indexed),
     /* 178861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178865 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178869 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178872 */     GIR_RootConstrainSelectedInstOperands,
     /* 178873 */     // GIR_Coverage, 2031,
     /* 178873 */     GIR_EraseRootFromParent_Done,
     /* 178874 */   // Label 3312: @178874
     /* 178874 */   GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(178978), // Rule ID 2090 //
     /* 178879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 178887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 178890 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 178893 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 178896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178904 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 178908 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 178912 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178916 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 178920 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 178924 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 178928 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 178932 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 178937 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 178941 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 178945 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 178949 */     // MIs[3] Operand 1
     /* 178949 */     // No operand predicates
     /* 178949 */     // MIs[1] Operand 2
     /* 178949 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 178960 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 178962 */     // (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 178962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_indexed),
     /* 178965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 178967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 178969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 178973 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 178976 */     GIR_RootConstrainSelectedInstOperands,
     /* 178977 */     // GIR_Coverage, 2090,
     /* 178977 */     GIR_EraseRootFromParent_Done,
     /* 178978 */   // Label 3313: @178978
     /* 178978 */   GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(179035), // Rule ID 1755 //
     /* 178983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 178986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 178991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 178994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 178997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 179000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179004 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 179011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 179018 */     // (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (SQDMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 179018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv8i16_v4i32),
     /* 179021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 179028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 179033 */     GIR_RootConstrainSelectedInstOperands,
     /* 179034 */     // GIR_Coverage, 1755,
     /* 179034 */     GIR_EraseRootFromParent_Done,
     /* 179035 */   // Label 3314: @179035
     /* 179035 */   GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(179092), // Rule ID 1757 //
     /* 179040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 179043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 179048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 179051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 179054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 179057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 179068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 179075 */     // (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (SQDMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 179075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i32_v2i64),
     /* 179078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 179085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 179090 */     GIR_RootConstrainSelectedInstOperands,
     /* 179091 */     // GIR_Coverage, 1757,
     /* 179091 */     GIR_EraseRootFromParent_Done,
     /* 179092 */   // Label 3315: @179092
     /* 179092 */   GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(179202), // Rule ID 6353 //
     /* 179097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 179102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 179105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 179108 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 179111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179115 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 179119 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 179123 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 179127 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 179131 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179136 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 179147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 179151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 179155 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 179159 */     // MIs[2] Operand 1
     /* 179159 */     // No operand predicates
     /* 179159 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 179161 */     // (intrinsic_wo_chain:{ *:[f16] } 776:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 179161 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 179164 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179168 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179173 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 179179 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179184 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 179192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179194 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 179200 */     GIR_RootConstrainSelectedInstOperands,
     /* 179201 */     // GIR_Coverage, 6353,
     /* 179201 */     GIR_EraseRootFromParent_Done,
     /* 179202 */   // Label 3316: @179202
     /* 179202 */   GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(179299), // Rule ID 14209 //
     /* 179207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 179210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 179218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 179221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 179224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 179232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 179240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179244 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179249 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179253 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179257 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179259 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 179259 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 179262 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179266 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179271 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 179277 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179282 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 179290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179292 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 179294 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179297 */     GIR_RootConstrainSelectedInstOperands,
     /* 179298 */     // GIR_Coverage, 14209,
     /* 179298 */     GIR_EraseRootFromParent_Done,
     /* 179299 */   // Label 3317: @179299
     /* 179299 */   GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(179396), // Rule ID 14210 //
     /* 179304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 179307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 179315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 179318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 179321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 179329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 179337 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179346 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179350 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179354 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179356 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 179356 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 179359 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179363 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179368 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 179374 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 179387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179389 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 179391 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179394 */     GIR_RootConstrainSelectedInstOperands,
     /* 179395 */     // GIR_Coverage, 14210,
     /* 179395 */     GIR_EraseRootFromParent_Done,
     /* 179396 */   // Label 3318: @179396
     /* 179396 */   GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(179493), // Rule ID 14211 //
     /* 179401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 179404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 179412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 179418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 179426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 179434 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179438 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179443 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179453 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 179453 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 179456 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179460 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179465 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 179471 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179476 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 179484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 179488 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179491 */     GIR_RootConstrainSelectedInstOperands,
     /* 179492 */     // GIR_Coverage, 14211,
     /* 179492 */     GIR_EraseRootFromParent_Done,
     /* 179493 */   // Label 3319: @179493
     /* 179493 */   GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(179573), // Rule ID 5285 //
     /* 179498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 179503 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 179506 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179509 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 179512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179516 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 179524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 179528 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 179531 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 179536 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 179540 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 179544 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179549 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179554 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179556 */     // (intrinsic_wo_chain:{ *:[i64] } 689:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 179556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALi32),
     /* 179559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 179561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 179563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 179567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 179571 */     GIR_RootConstrainSelectedInstOperands,
     /* 179572 */     // GIR_Coverage, 5285,
     /* 179572 */     GIR_EraseRootFromParent_Done,
     /* 179573 */   // Label 3320: @179573
     /* 179573 */   GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(179653), // Rule ID 5286 //
     /* 179578 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 179583 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 179586 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179589 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 179592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 179604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 179608 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 179611 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 179616 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 179620 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 179624 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179629 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179634 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179636 */     // (intrinsic_wo_chain:{ *:[i64] } 708:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm))  =>  (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 179636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLi32),
     /* 179639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 179641 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 179643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 179647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 179651 */     GIR_RootConstrainSelectedInstOperands,
     /* 179652 */     // GIR_Coverage, 5286,
     /* 179652 */     GIR_EraseRootFromParent_Done,
     /* 179653 */   // Label 3321: @179653
     /* 179653 */   GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(179750), // Rule ID 5282 //
     /* 179658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 179661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 179669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 179672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 179675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179679 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 179687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179691 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 179695 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179699 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179704 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179708 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179710 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 179710 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 179713 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179717 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179722 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 179728 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179733 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 179741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 179745 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179748 */     GIR_RootConstrainSelectedInstOperands,
     /* 179749 */     // GIR_Coverage, 5282,
     /* 179749 */     GIR_EraseRootFromParent_Done,
     /* 179750 */   // Label 3322: @179750
     /* 179750 */   GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(179847), // Rule ID 5283 //
     /* 179755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 179758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 179766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 179769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 179772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 179784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 179792 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179796 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179801 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179805 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179807 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 179807 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 179810 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179814 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179819 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 179825 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179830 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 179838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 179842 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179845 */     GIR_RootConstrainSelectedInstOperands,
     /* 179846 */     // GIR_Coverage, 5283,
     /* 179846 */     GIR_EraseRootFromParent_Done,
     /* 179847 */   // Label 3323: @179847
     /* 179847 */   GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(179944), // Rule ID 5284 //
     /* 179852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 179855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 179863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 179869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179873 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179877 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 179881 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 179885 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 179889 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179898 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 179902 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 179904 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 179904 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 179907 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 179911 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 179916 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 179922 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179927 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 179932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 179935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 179937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 179939 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 179942 */     GIR_RootConstrainSelectedInstOperands,
     /* 179943 */     // GIR_Coverage, 5284,
     /* 179943 */     GIR_EraseRootFromParent_Done,
     /* 179944 */   // Label 3324: @179944
     /* 179944 */   GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(180025), // Rule ID 13742 //
     /* 179949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 179952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 179957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 179960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 179963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 179966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179970 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 179974 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 179978 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 179982 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 179986 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 179991 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 179995 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 179999 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180003 */     // MIs[2] Operand 1
     /* 180003 */     // No operand predicates
     /* 180003 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180007 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180009 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 180012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180014 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180016 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180020 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180023 */     GIR_RootConstrainSelectedInstOperands,
     /* 180024 */     // GIR_Coverage, 13742,
     /* 180024 */     GIR_EraseRootFromParent_Done,
     /* 180025 */   // Label 3325: @180025
     /* 180025 */   GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(180106), // Rule ID 13743 //
     /* 180030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 180033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 180041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 180044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 180047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180051 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180055 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 180059 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180063 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180067 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180072 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180076 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180080 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180084 */     // MIs[2] Operand 1
     /* 180084 */     // No operand predicates
     /* 180084 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180088 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180090 */     // (intrinsic_wo_chain:{ *:[v8f16] } 620:{ *:[iPTR] }, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
     /* 180093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180097 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180101 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180104 */     GIR_RootConstrainSelectedInstOperands,
     /* 180105 */     // GIR_Coverage, 13743,
     /* 180105 */     GIR_EraseRootFromParent_Done,
     /* 180106 */   // Label 3326: @180106
     /* 180106 */   GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(180187), // Rule ID 13745 //
     /* 180111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 180122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 180125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 180128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 180140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 180144 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180148 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180161 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 180165 */     // MIs[2] Operand 1
     /* 180165 */     // No operand predicates
     /* 180165 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180169 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180171 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 180174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180182 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180185 */     GIR_RootConstrainSelectedInstOperands,
     /* 180186 */     // GIR_Coverage, 13745,
     /* 180186 */     GIR_EraseRootFromParent_Done,
     /* 180187 */   // Label 3327: @180187
     /* 180187 */   GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(180268), // Rule ID 13746 //
     /* 180192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 180203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 180206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 180209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180213 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180217 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 180221 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 180225 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180229 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180242 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 180246 */     // MIs[2] Operand 1
     /* 180246 */     // No operand predicates
     /* 180246 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180250 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180252 */     // (intrinsic_wo_chain:{ *:[v4f32] } 620:{ *:[iPTR] }, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
     /* 180255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180263 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180266 */     GIR_RootConstrainSelectedInstOperands,
     /* 180267 */     // GIR_Coverage, 13746,
     /* 180267 */     GIR_EraseRootFromParent_Done,
     /* 180268 */   // Label 3328: @180268
     /* 180268 */   GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(180349), // Rule ID 13747 //
     /* 180273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 180284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 180287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 180290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180294 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 180302 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 180306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180315 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180319 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180323 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 180327 */     // MIs[2] Operand 1
     /* 180327 */     // No operand predicates
     /* 180327 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180331 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180333 */     // (intrinsic_wo_chain:{ *:[v2f64] } 620:{ *:[iPTR] }, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
     /* 180336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180338 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180344 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180347 */     GIR_RootConstrainSelectedInstOperands,
     /* 180348 */     // GIR_Coverage, 13747,
     /* 180348 */     GIR_EraseRootFromParent_Done,
     /* 180349 */   // Label 3329: @180349
     /* 180349 */   GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(180430), // Rule ID 13748 //
     /* 180354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 180357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 180365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 180368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 180371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180375 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180379 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 180383 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180387 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180391 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180404 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180408 */     // MIs[2] Operand 1
     /* 180408 */     // No operand predicates
     /* 180408 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180412 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180414 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 180417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180425 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180428 */     GIR_RootConstrainSelectedInstOperands,
     /* 180429 */     // GIR_Coverage, 13748,
     /* 180429 */     GIR_EraseRootFromParent_Done,
     /* 180430 */   // Label 3330: @180430
     /* 180430 */   GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(180511), // Rule ID 13749 //
     /* 180435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 180446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 180449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 180452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180460 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 180464 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 180468 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180472 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180477 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180481 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180485 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 180489 */     // MIs[2] Operand 1
     /* 180489 */     // No operand predicates
     /* 180489 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180493 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180495 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 180498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180500 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180502 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180506 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180509 */     GIR_RootConstrainSelectedInstOperands,
     /* 180510 */     // GIR_Coverage, 13749,
     /* 180510 */     GIR_EraseRootFromParent_Done,
     /* 180511 */   // Label 3331: @180511
     /* 180511 */   GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(180592), // Rule ID 13750 //
     /* 180516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 180527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 180530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 180533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 180545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 180549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180553 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180562 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180566 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 180570 */     // MIs[2] Operand 1
     /* 180570 */     // No operand predicates
     /* 180570 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180574 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180576 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 180579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180581 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 180583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180587 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180590 */     GIR_RootConstrainSelectedInstOperands,
     /* 180591 */     // GIR_Coverage, 13750,
     /* 180591 */     GIR_EraseRootFromParent_Done,
     /* 180592 */   // Label 3332: @180592
     /* 180592 */   GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(180698), // Rule ID 6350 //
     /* 180597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 180602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 180605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 180608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 180611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180615 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 180619 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 180623 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 180627 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180632 */     // MIs[1] Operand 2
     /* 180632 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 180643 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 180647 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180651 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 180655 */     // MIs[2] Operand 1
     /* 180655 */     // No operand predicates
     /* 180655 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180657 */     // (intrinsic_wo_chain:{ *:[f16] } 775:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 180657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 180660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 180664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 180669 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 180675 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180680 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 180688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180690 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 180693 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 180696 */     GIR_RootConstrainSelectedInstOperands,
     /* 180697 */     // GIR_Coverage, 6350,
     /* 180697 */     GIR_EraseRootFromParent_Done,
     /* 180698 */   // Label 3333: @180698
     /* 180698 */   GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(180779), // Rule ID 1992 //
     /* 180703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 180706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 180714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 180717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 180720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180724 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 180732 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 180736 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180740 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180744 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180757 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180761 */     // MIs[2] Operand 1
     /* 180761 */     // No operand predicates
     /* 180761 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180763 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 180766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 180770 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180774 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180777 */     GIR_RootConstrainSelectedInstOperands,
     /* 180778 */     // GIR_Coverage, 1992,
     /* 180778 */     GIR_EraseRootFromParent_Done,
     /* 180779 */   // Label 3334: @180779
     /* 180779 */   GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(180860), // Rule ID 1993 //
     /* 180784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 180787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 180792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 180795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 180798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 180801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180809 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 180813 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 180817 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180821 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180825 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180830 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180834 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180838 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180842 */     // MIs[2] Operand 1
     /* 180842 */     // No operand predicates
     /* 180842 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180844 */     // (intrinsic_wo_chain:{ *:[v8f16] } 620:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
     /* 180847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 180851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180855 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180858 */     GIR_RootConstrainSelectedInstOperands,
     /* 180859 */     // GIR_Coverage, 1993,
     /* 180859 */     GIR_EraseRootFromParent_Done,
     /* 180860 */   // Label 3335: @180860
     /* 180860 */   GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(180941), // Rule ID 2022 //
     /* 180865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 180873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 180876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 180879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 180882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180886 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 180894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 180898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180902 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180911 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180915 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 180919 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 180923 */     // MIs[2] Operand 1
     /* 180923 */     // No operand predicates
     /* 180923 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 180925 */     // (intrinsic_wo_chain:{ *:[v4i16] } 690:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 180925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16_indexed),
     /* 180928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 180930 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 180932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 180936 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 180939 */     GIR_RootConstrainSelectedInstOperands,
     /* 180940 */     // GIR_Coverage, 2022,
     /* 180940 */     GIR_EraseRootFromParent_Done,
     /* 180941 */   // Label 3336: @180941
     /* 180941 */   GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(181022), // Rule ID 2023 //
     /* 180946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 180949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 180954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 180957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 180960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 180963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 180971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 180975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 180979 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 180983 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 180987 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 180992 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 180996 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181000 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 181004 */     // MIs[2] Operand 1
     /* 181004 */     // No operand predicates
     /* 181004 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181006 */     // (intrinsic_wo_chain:{ *:[v8i16] } 690:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16_indexed),
     /* 181009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181017 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181020 */     GIR_RootConstrainSelectedInstOperands,
     /* 181021 */     // GIR_Coverage, 2023,
     /* 181021 */     GIR_EraseRootFromParent_Done,
     /* 181022 */   // Label 3337: @181022
     /* 181022 */   GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(181103), // Rule ID 2029 //
     /* 181027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 181035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 181038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 181041 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 181044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181048 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 181060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 181064 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181068 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 181073 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181077 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181081 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 181085 */     // MIs[2] Operand 1
     /* 181085 */     // No operand predicates
     /* 181085 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181087 */     // (intrinsic_wo_chain:{ *:[v4i16] } 698:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16_indexed),
     /* 181090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181092 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181098 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181101 */     GIR_RootConstrainSelectedInstOperands,
     /* 181102 */     // GIR_Coverage, 2029,
     /* 181102 */     GIR_EraseRootFromParent_Done,
     /* 181103 */   // Label 3338: @181103
     /* 181103 */   GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(181184), // Rule ID 2030 //
     /* 181108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 181116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 181119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 181122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 181125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181133 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181137 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 181141 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 181145 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181149 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 181154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181162 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 181166 */     // MIs[2] Operand 1
     /* 181166 */     // No operand predicates
     /* 181166 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181168 */     // (intrinsic_wo_chain:{ *:[v8i16] } 698:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16_indexed),
     /* 181171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181182 */     GIR_RootConstrainSelectedInstOperands,
     /* 181183 */     // GIR_Coverage, 2030,
     /* 181183 */     GIR_EraseRootFromParent_Done,
     /* 181184 */   // Label 3339: @181184
     /* 181184 */   GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(181265), // Rule ID 2088 //
     /* 181189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 181197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 181200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 181203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 181206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181214 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181218 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 181222 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 181226 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181230 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 181235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181243 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 181247 */     // MIs[2] Operand 1
     /* 181247 */     // No operand predicates
     /* 181247 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181249 */     // (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_indexed),
     /* 181252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181260 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181263 */     GIR_RootConstrainSelectedInstOperands,
     /* 181264 */     // GIR_Coverage, 2088,
     /* 181264 */     GIR_EraseRootFromParent_Done,
     /* 181265 */   // Label 3340: @181265
     /* 181265 */   GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(181346), // Rule ID 1995 //
     /* 181270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 181278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 181281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 181284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 181287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181291 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181307 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181311 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181320 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181324 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181328 */     // MIs[2] Operand 1
     /* 181328 */     // No operand predicates
     /* 181328 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181330 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 181333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181337 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181341 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181344 */     GIR_RootConstrainSelectedInstOperands,
     /* 181345 */     // GIR_Coverage, 1995,
     /* 181345 */     GIR_EraseRootFromParent_Done,
     /* 181346 */   // Label 3341: @181346
     /* 181346 */   GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(181427), // Rule ID 1996 //
     /* 181351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 181359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 181362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 181365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 181368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181380 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181384 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181388 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181405 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181409 */     // MIs[2] Operand 1
     /* 181409 */     // No operand predicates
     /* 181409 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181411 */     // (intrinsic_wo_chain:{ *:[v4f32] } 620:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
     /* 181414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181418 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181422 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181425 */     GIR_RootConstrainSelectedInstOperands,
     /* 181426 */     // GIR_Coverage, 1996,
     /* 181426 */     GIR_EraseRootFromParent_Done,
     /* 181427 */   // Label 3342: @181427
     /* 181427 */   GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(181508), // Rule ID 2025 //
     /* 181432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 181440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 181443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 181446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 181449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181457 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181461 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181465 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181469 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181473 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181478 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181482 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181486 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181490 */     // MIs[2] Operand 1
     /* 181490 */     // No operand predicates
     /* 181490 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181492 */     // (intrinsic_wo_chain:{ *:[v2i32] } 690:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32_indexed),
     /* 181495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181506 */     GIR_RootConstrainSelectedInstOperands,
     /* 181507 */     // GIR_Coverage, 2025,
     /* 181507 */     GIR_EraseRootFromParent_Done,
     /* 181508 */   // Label 3343: @181508
     /* 181508 */   GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(181589), // Rule ID 2026 //
     /* 181513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 181521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 181524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 181527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 181530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181534 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181538 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181542 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181546 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181550 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181554 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181559 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181563 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181567 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181571 */     // MIs[2] Operand 1
     /* 181571 */     // No operand predicates
     /* 181571 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181573 */     // (intrinsic_wo_chain:{ *:[v4i32] } 690:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32_indexed),
     /* 181576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181580 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181584 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181587 */     GIR_RootConstrainSelectedInstOperands,
     /* 181588 */     // GIR_Coverage, 2026,
     /* 181588 */     GIR_EraseRootFromParent_Done,
     /* 181589 */   // Label 3344: @181589
     /* 181589 */   GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(181670), // Rule ID 2032 //
     /* 181594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 181602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 181605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 181608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 181611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181619 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181623 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181627 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181631 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181635 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181640 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181644 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181648 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181652 */     // MIs[2] Operand 1
     /* 181652 */     // No operand predicates
     /* 181652 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181654 */     // (intrinsic_wo_chain:{ *:[v2i32] } 698:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32_indexed),
     /* 181657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181659 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181665 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181668 */     GIR_RootConstrainSelectedInstOperands,
     /* 181669 */     // GIR_Coverage, 2032,
     /* 181669 */     GIR_EraseRootFromParent_Done,
     /* 181670 */   // Label 3345: @181670
     /* 181670 */   GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(181751), // Rule ID 2033 //
     /* 181675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 181683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 181686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 181689 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 181692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181696 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181712 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181716 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181729 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181733 */     // MIs[2] Operand 1
     /* 181733 */     // No operand predicates
     /* 181733 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181735 */     // (intrinsic_wo_chain:{ *:[v4i32] } 698:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32_indexed),
     /* 181738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181742 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181746 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181749 */     GIR_RootConstrainSelectedInstOperands,
     /* 181750 */     // GIR_Coverage, 2033,
     /* 181750 */     GIR_EraseRootFromParent_Done,
     /* 181751 */   // Label 3346: @181751
     /* 181751 */   GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(181832), // Rule ID 2091 //
     /* 181756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 181764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 181767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 181770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 181773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 181789 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 181793 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181810 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 181814 */     // MIs[2] Operand 1
     /* 181814 */     // No operand predicates
     /* 181814 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181816 */     // (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_indexed),
     /* 181819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181827 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181830 */     GIR_RootConstrainSelectedInstOperands,
     /* 181831 */     // GIR_Coverage, 2091,
     /* 181831 */     GIR_EraseRootFromParent_Done,
     /* 181832 */   // Label 3347: @181832
     /* 181832 */   GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(181913), // Rule ID 1997 //
     /* 181837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 181840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 181845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 181848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 181851 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 181854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 181870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 181874 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181878 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181883 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181887 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181891 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 181895 */     // MIs[2] Operand 1
     /* 181895 */     // No operand predicates
     /* 181895 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181897 */     // (intrinsic_wo_chain:{ *:[v2f64] } 620:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
     /* 181900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181911 */     GIR_RootConstrainSelectedInstOperands,
     /* 181912 */     // GIR_Coverage, 1997,
     /* 181912 */     GIR_EraseRootFromParent_Done,
     /* 181913 */   // Label 3348: @181913
     /* 181913 */   GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(181994), // Rule ID 1998 //
     /* 181918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 181921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 181926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 181929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 181932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 181935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 181939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 181943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 181947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 181951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 181955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 181959 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 181964 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 181968 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 181972 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 181976 */     // MIs[2] Operand 1
     /* 181976 */     // No operand predicates
     /* 181976 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 181978 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 181978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 181981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 181989 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 181992 */     GIR_RootConstrainSelectedInstOperands,
     /* 181993 */     // GIR_Coverage, 1998,
     /* 181993 */     GIR_EraseRootFromParent_Done,
     /* 181994 */   // Label 3349: @181994
     /* 181994 */   GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(182075), // Rule ID 1999 //
     /* 181999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 182002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 182007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 182032 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 182036 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 182040 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 182049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182053 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 182057 */     // MIs[2] Operand 1
     /* 182057 */     // No operand predicates
     /* 182057 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 182059 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 182059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 182062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182066 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 182070 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 182073 */     GIR_RootConstrainSelectedInstOperands,
     /* 182074 */     // GIR_Coverage, 1999,
     /* 182074 */     GIR_EraseRootFromParent_Done,
     /* 182075 */   // Label 3350: @182075
     /* 182075 */   GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(182156), // Rule ID 2000 //
     /* 182080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 182083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 182088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 182097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182101 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 182113 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 182117 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 182121 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182126 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 182130 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182134 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 182138 */     // MIs[2] Operand 1
     /* 182138 */     // No operand predicates
     /* 182138 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 182140 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 182140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 182143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182147 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 182151 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 182154 */     GIR_RootConstrainSelectedInstOperands,
     /* 182155 */     // GIR_Coverage, 2000,
     /* 182155 */     GIR_EraseRootFromParent_Done,
     /* 182156 */   // Label 3351: @182156
     /* 182156 */   GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(182237), // Rule ID 2027 //
     /* 182161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 182164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 182169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182182 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 182194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 182198 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 182202 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182207 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 182211 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182215 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 182219 */     // MIs[2] Operand 1
     /* 182219 */     // No operand predicates
     /* 182219 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 182221 */     // (intrinsic_wo_chain:{ *:[i32] } 690:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 182221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32_indexed),
     /* 182224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 182232 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 182235 */     GIR_RootConstrainSelectedInstOperands,
     /* 182236 */     // GIR_Coverage, 2027,
     /* 182236 */     GIR_EraseRootFromParent_Done,
     /* 182237 */   // Label 3352: @182237
     /* 182237 */   GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(182318), // Rule ID 2034 //
     /* 182242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 182245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 182250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182263 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 182275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 182279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 182283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182288 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 182292 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182296 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 182300 */     // MIs[2] Operand 1
     /* 182300 */     // No operand predicates
     /* 182300 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 182302 */     // (intrinsic_wo_chain:{ *:[i32] } 698:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 182302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32_indexed),
     /* 182305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182309 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 182313 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 182316 */     GIR_RootConstrainSelectedInstOperands,
     /* 182317 */     // GIR_Coverage, 2034,
     /* 182317 */     GIR_EraseRootFromParent_Done,
     /* 182318 */   // Label 3353: @182318
     /* 182318 */   GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(182396), // Rule ID 6337 //
     /* 182323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 182328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182341 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182345 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182349 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 182353 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 182357 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 182361 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182366 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 182370 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182374 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 182378 */     // MIs[2] Operand 1
     /* 182378 */     // No operand predicates
     /* 182378 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 182380 */     // (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 182380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv1i64_indexed),
     /* 182383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /* 182391 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 182394 */     GIR_RootConstrainSelectedInstOperands,
     /* 182395 */     // GIR_Coverage, 6337,
     /* 182395 */     GIR_EraseRootFromParent_Done,
     /* 182396 */   // Label 3354: @182396
     /* 182396 */   GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(182456), // Rule ID 6403 //
     /* 182401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 182406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 182409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 182412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182423 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
     /* 182427 */     // (intrinsic_wo_chain:{ *:[v8i8] } 667:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })  =>  (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
     /* 182427 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 182430 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 182434 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 182439 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 182442 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 182444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
     /* 182447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 182451 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 182454 */     GIR_RootConstrainSelectedInstOperands,
     /* 182455 */     // GIR_Coverage, 6403,
     /* 182455 */     GIR_EraseRootFromParent_Done,
     /* 182456 */   // Label 3355: @182456
     /* 182456 */   GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(182516), // Rule ID 6404 //
     /* 182461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 182466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 182469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 182472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182483 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
     /* 182487 */     // (intrinsic_wo_chain:{ *:[v4i16] } 667:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })  =>  (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
     /* 182487 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 182490 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 182494 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 182499 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 182502 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 182504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
     /* 182507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182509 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 182511 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 182514 */     GIR_RootConstrainSelectedInstOperands,
     /* 182515 */     // GIR_Coverage, 6404,
     /* 182515 */     GIR_EraseRootFromParent_Done,
     /* 182516 */   // Label 3356: @182516
     /* 182516 */   GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(182576), // Rule ID 6405 //
     /* 182521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 182526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 182529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 182532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 182543 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 32,
     /* 182547 */     // (intrinsic_wo_chain:{ *:[v2i32] } 667:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })  =>  (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
     /* 182547 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 182550 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 182554 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 182559 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 182562 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 182564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
     /* 182567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 182571 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 182574 */     GIR_RootConstrainSelectedInstOperands,
     /* 182575 */     // GIR_Coverage, 6405,
     /* 182575 */     GIR_EraseRootFromParent_Done,
     /* 182576 */   // Label 3357: @182576
     /* 182576 */   GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(182623), // Rule ID 3930 //
     /* 182581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 182584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 182589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182603 */     // MIs[0] Operand 3
     /* 182603 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /* 182614 */     // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] })  =>  (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 182614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
     /* 182617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 182621 */     GIR_RootConstrainSelectedInstOperands,
     /* 182622 */     // GIR_Coverage, 3930,
     /* 182622 */     GIR_EraseRootFromParent_Done,
     /* 182623 */   // Label 3358: @182623
     /* 182623 */   GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(182670), // Rule ID 3931 //
     /* 182628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 182631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 182636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182646 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182650 */     // MIs[0] Operand 3
     /* 182650 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /* 182661 */     // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] })  =>  (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 182661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
     /* 182664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 182668 */     GIR_RootConstrainSelectedInstOperands,
     /* 182669 */     // GIR_Coverage, 3931,
     /* 182669 */     GIR_EraseRootFromParent_Done,
     /* 182670 */   // Label 3359: @182670
     /* 182670 */   GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(182717), // Rule ID 3932 //
     /* 182675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 182678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 182683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182693 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182697 */     // MIs[0] Operand 3
     /* 182697 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /* 182708 */     // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] })  =>  (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 182708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
     /* 182711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 182715 */     GIR_RootConstrainSelectedInstOperands,
     /* 182716 */     // GIR_Coverage, 3932,
     /* 182716 */     GIR_EraseRootFromParent_Done,
     /* 182717 */   // Label 3360: @182717
     /* 182717 */   GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(182764), // Rule ID 3933 //
     /* 182722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 182725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 182730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182744 */     // MIs[0] Operand 3
     /* 182744 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /* 182755 */     // (intrinsic_wo_chain:{ *:[i64] } 302:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] })  =>  (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 182755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
     /* 182758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182760 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 182762 */     GIR_RootConstrainSelectedInstOperands,
     /* 182763 */     // GIR_Coverage, 3933,
     /* 182763 */     GIR_EraseRootFromParent_Done,
     /* 182764 */   // Label 3361: @182764
     /* 182764 */   GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(182810), // Rule ID 3571 //
     /* 182769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 182772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 182777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 182780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 182783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 182787 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 182791 */     // MIs[0] Idx
     /* 182791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 182794 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_0),
     /* 182799 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1636:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx)  =>  (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx)
     /* 182799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
     /* 182802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 182804 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 182806 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 182808 */     GIR_RootConstrainSelectedInstOperands,
     /* 182809 */     // GIR_Coverage, 3571,
     /* 182809 */     GIR_EraseRootFromParent_Done,
     /* 182810 */   // Label 3362: @182810
     /* 182810 */   GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(182856), // Rule ID 3572 //
     /* 182815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 182818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 182823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 182826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 182829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 182833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 182837 */     // MIs[0] Idx
     /* 182837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 182840 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 182845 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1636:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx)  =>  (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx)
     /* 182845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
     /* 182848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 182850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 182852 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 182854 */     GIR_RootConstrainSelectedInstOperands,
     /* 182855 */     // GIR_Coverage, 3572,
     /* 182855 */     GIR_EraseRootFromParent_Done,
     /* 182856 */   // Label 3363: @182856
     /* 182856 */   GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(182902), // Rule ID 3573 //
     /* 182861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 182864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 182869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 182872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 182875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 182879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 182883 */     // MIs[0] Idx
     /* 182883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 182886 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 182891 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1636:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx)  =>  (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx)
     /* 182891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
     /* 182894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 182896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 182898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 182900 */     GIR_RootConstrainSelectedInstOperands,
     /* 182901 */     // GIR_Coverage, 3573,
     /* 182901 */     GIR_EraseRootFromParent_Done,
     /* 182902 */   // Label 3364: @182902
     /* 182902 */   GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(182948), // Rule ID 3574 //
     /* 182907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 182910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 182915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 182918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 182921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 182925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 182929 */     // MIs[0] Idx
     /* 182929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 182932 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 182937 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1636:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx)  =>  (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx)
     /* 182937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
     /* 182940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 182942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 182944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 182946 */     GIR_RootConstrainSelectedInstOperands,
     /* 182947 */     // GIR_Coverage, 3574,
     /* 182947 */     GIR_EraseRootFromParent_Done,
     /* 182948 */   // Label 3365: @182948
     /* 182948 */   GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(183004), // Rule ID 2113 //
     /* 182953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 182956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
     /* 182961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182967 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 182970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182974 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 182982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 182986 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 182990 */     // MIs[1] Operand 1
     /* 182990 */     // No operand predicates
     /* 182990 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 182992 */     // (intrinsic_wo_chain:{ *:[i32] } 702:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 182992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNs),
     /* 182995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182999 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183002 */     GIR_RootConstrainSelectedInstOperands,
     /* 183003 */     // GIR_Coverage, 2113,
     /* 183003 */     GIR_EraseRootFromParent_Done,
     /* 183004 */   // Label 3366: @183004
     /* 183004 */   GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(183060), // Rule ID 2114 //
     /* 183009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
     /* 183017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183034 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183038 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183042 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183046 */     // MIs[1] Operand 1
     /* 183046 */     // No operand predicates
     /* 183046 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183048 */     // (intrinsic_wo_chain:{ *:[i32] } 703:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNs),
     /* 183051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183055 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183058 */     GIR_RootConstrainSelectedInstOperands,
     /* 183059 */     // GIR_Coverage, 2114,
     /* 183059 */     GIR_EraseRootFromParent_Done,
     /* 183060 */   // Label 3367: @183060
     /* 183060 */   GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(183116), // Rule ID 2119 //
     /* 183065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
     /* 183073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183079 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183086 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183098 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183102 */     // MIs[1] Operand 1
     /* 183102 */     // No operand predicates
     /* 183102 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183104 */     // (intrinsic_wo_chain:{ *:[i32] } 706:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNs),
     /* 183107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183111 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183114 */     GIR_RootConstrainSelectedInstOperands,
     /* 183115 */     // GIR_Coverage, 2119,
     /* 183115 */     GIR_EraseRootFromParent_Done,
     /* 183116 */   // Label 3368: @183116
     /* 183116 */   GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(183172), // Rule ID 2120 //
     /* 183121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
     /* 183129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183142 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183154 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183158 */     // MIs[1] Operand 1
     /* 183158 */     // No operand predicates
     /* 183158 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183160 */     // (intrinsic_wo_chain:{ *:[i32] } 707:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNs),
     /* 183163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183167 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183170 */     GIR_RootConstrainSelectedInstOperands,
     /* 183171 */     // GIR_Coverage, 2120,
     /* 183171 */     GIR_EraseRootFromParent_Done,
     /* 183172 */   // Label 3369: @183172
     /* 183172 */   GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(183228), // Rule ID 2127 //
     /* 183177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
     /* 183185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183202 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183206 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183210 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183214 */     // MIs[1] Operand 1
     /* 183214 */     // No operand predicates
     /* 183214 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183216 */     // (intrinsic_wo_chain:{ *:[i32] } 751:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNs),
     /* 183219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183223 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183226 */     GIR_RootConstrainSelectedInstOperands,
     /* 183227 */     // GIR_Coverage, 2127,
     /* 183227 */     GIR_EraseRootFromParent_Done,
     /* 183228 */   // Label 3370: @183228
     /* 183228 */   GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(183284), // Rule ID 2130 //
     /* 183233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
     /* 183241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183254 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183266 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183270 */     // MIs[1] Operand 1
     /* 183270 */     // No operand predicates
     /* 183270 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183272 */     // (intrinsic_wo_chain:{ *:[i32] } 753:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNs),
     /* 183275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183279 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183282 */     GIR_RootConstrainSelectedInstOperands,
     /* 183283 */     // GIR_Coverage, 2130,
     /* 183283 */     GIR_EraseRootFromParent_Done,
     /* 183284 */   // Label 3371: @183284
     /* 183284 */   GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(183340), // Rule ID 2152 //
     /* 183289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 183297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 183300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 183303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 183314 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183318 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183322 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 183326 */     // MIs[1] Operand 1
     /* 183326 */     // No operand predicates
     /* 183326 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183328 */     // (intrinsic_wo_chain:{ *:[v8i8] } 667:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i8_shift),
     /* 183331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183335 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183338 */     GIR_RootConstrainSelectedInstOperands,
     /* 183339 */     // GIR_Coverage, 2152,
     /* 183339 */     GIR_EraseRootFromParent_Done,
     /* 183340 */   // Label 3372: @183340
     /* 183340 */   GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(183396), // Rule ID 2154 //
     /* 183345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 183353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 183356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 183359 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 183370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183378 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 183382 */     // MIs[1] Operand 1
     /* 183382 */     // No operand predicates
     /* 183382 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183384 */     // (intrinsic_wo_chain:{ *:[v4i16] } 667:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i16_shift),
     /* 183387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183391 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183394 */     GIR_RootConstrainSelectedInstOperands,
     /* 183395 */     // GIR_Coverage, 2154,
     /* 183395 */     GIR_EraseRootFromParent_Done,
     /* 183396 */   // Label 3373: @183396
     /* 183396 */   GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(183452), // Rule ID 2156 //
     /* 183401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 183404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 183409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 183412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 183415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183422 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 183426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183434 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 183438 */     // MIs[1] Operand 1
     /* 183438 */     // No operand predicates
     /* 183438 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183440 */     // (intrinsic_wo_chain:{ *:[v2i32] } 667:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 183440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv2i32_shift),
     /* 183443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183445 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183447 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183450 */     GIR_RootConstrainSelectedInstOperands,
     /* 183451 */     // GIR_Coverage, 2156,
     /* 183451 */     GIR_EraseRootFromParent_Done,
     /* 183452 */   // Label 3374: @183452
     /* 183452 */   GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(183505), // Rule ID 6338 //
     /* 183457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 183462 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183465 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183468 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183487 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183491 */     // MIs[1] Operand 1
     /* 183491 */     // No operand predicates
     /* 183491 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183493 */     // (intrinsic_wo_chain:{ *:[i32] } 772:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 183493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSs),
     /* 183496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183500 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183503 */     GIR_RootConstrainSelectedInstOperands,
     /* 183504 */     // GIR_Coverage, 6338,
     /* 183504 */     GIR_EraseRootFromParent_Done,
     /* 183505 */   // Label 3375: @183505
     /* 183505 */   GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(183558), // Rule ID 6339 //
     /* 183510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 183515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183528 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183540 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183544 */     // MIs[1] Operand 1
     /* 183544 */     // No operand predicates
     /* 183544 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183546 */     // (intrinsic_wo_chain:{ *:[i32] } 773:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 183546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUs),
     /* 183549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183551 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183553 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183556 */     GIR_RootConstrainSelectedInstOperands,
     /* 183557 */     // GIR_Coverage, 6339,
     /* 183557 */     GIR_EraseRootFromParent_Done,
     /* 183558 */   // Label 3376: @183558
     /* 183558 */   GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(183611), // Rule ID 6340 //
     /* 183563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 183568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183581 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183585 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183589 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183593 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183597 */     // MIs[1] Operand 1
     /* 183597 */     // No operand predicates
     /* 183597 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183599 */     // (intrinsic_wo_chain:{ *:[i64] } 772:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
     /* 183602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183606 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183609 */     GIR_RootConstrainSelectedInstOperands,
     /* 183610 */     // GIR_Coverage, 6340,
     /* 183610 */     GIR_EraseRootFromParent_Done,
     /* 183611 */   // Label 3377: @183611
     /* 183611 */   GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(183664), // Rule ID 6341 //
     /* 183616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 183621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183634 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183642 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183646 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183650 */     // MIs[1] Operand 1
     /* 183650 */     // No operand predicates
     /* 183650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183652 */     // (intrinsic_wo_chain:{ *:[i64] } 773:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
     /* 183655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183659 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183662 */     GIR_RootConstrainSelectedInstOperands,
     /* 183663 */     // GIR_Coverage, 6341,
     /* 183663 */     GIR_EraseRootFromParent_Done,
     /* 183664 */   // Label 3378: @183664
     /* 183664 */   GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(183717), // Rule ID 6342 //
     /* 183669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 183674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183687 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183691 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183695 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183699 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183703 */     // MIs[1] Operand 1
     /* 183703 */     // No operand predicates
     /* 183703 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183705 */     // (intrinsic_wo_chain:{ *:[v1i64] } 772:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
     /* 183708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183712 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183715 */     GIR_RootConstrainSelectedInstOperands,
     /* 183716 */     // GIR_Coverage, 6342,
     /* 183716 */     GIR_EraseRootFromParent_Done,
     /* 183717 */   // Label 3379: @183717
     /* 183717 */   GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(183770), // Rule ID 6343 //
     /* 183722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 183727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183752 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183756 */     // MIs[1] Operand 1
     /* 183756 */     // No operand predicates
     /* 183756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183758 */     // (intrinsic_wo_chain:{ *:[v1i64] } 773:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
     /* 183761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183765 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183768 */     GIR_RootConstrainSelectedInstOperands,
     /* 183769 */     // GIR_Coverage, 6343,
     /* 183769 */     GIR_EraseRootFromParent_Done,
     /* 183770 */   // Label 3380: @183770
     /* 183770 */   GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(183823), // Rule ID 6344 //
     /* 183775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 183780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183797 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183801 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183805 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 183809 */     // MIs[1] Operand 1
     /* 183809 */     // No operand predicates
     /* 183809 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183811 */     // (intrinsic_wo_chain:{ *:[f32] } 776:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 183811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFs),
     /* 183814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183818 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183821 */     GIR_RootConstrainSelectedInstOperands,
     /* 183822 */     // GIR_Coverage, 6344,
     /* 183822 */     GIR_EraseRootFromParent_Done,
     /* 183823 */   // Label 3381: @183823
     /* 183823 */   GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(183876), // Rule ID 6345 //
     /* 183828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 183833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183854 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183858 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183862 */     // MIs[1] Operand 1
     /* 183862 */     // No operand predicates
     /* 183862 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183864 */     // (intrinsic_wo_chain:{ *:[f64] } 776:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
     /* 183867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183869 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183871 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183874 */     GIR_RootConstrainSelectedInstOperands,
     /* 183875 */     // GIR_Coverage, 6345,
     /* 183875 */     GIR_EraseRootFromParent_Done,
     /* 183876 */   // Label 3382: @183876
     /* 183876 */   GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(183929), // Rule ID 6346 //
     /* 183881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 183886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183911 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183915 */     // MIs[1] Operand 1
     /* 183915 */     // No operand predicates
     /* 183915 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183917 */     // (intrinsic_wo_chain:{ *:[v1f64] } 775:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
     /* 183920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183924 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183927 */     GIR_RootConstrainSelectedInstOperands,
     /* 183928 */     // GIR_Coverage, 6346,
     /* 183928 */     GIR_EraseRootFromParent_Done,
     /* 183929 */   // Label 3383: @183929
     /* 183929 */   GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(183982), // Rule ID 6347 //
     /* 183934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 183939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 183948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183952 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183956 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 183960 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 183964 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 183968 */     // MIs[1] Operand 1
     /* 183968 */     // No operand predicates
     /* 183968 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 183970 */     // (intrinsic_wo_chain:{ *:[f64] } 775:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 183970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
     /* 183973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183977 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 183980 */     GIR_RootConstrainSelectedInstOperands,
     /* 183981 */     // GIR_Coverage, 6347,
     /* 183981 */     GIR_EraseRootFromParent_Done,
     /* 183982 */   // Label 3384: @183982
     /* 183982 */   GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(184035), // Rule ID 6348 //
     /* 183987 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 183992 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183995 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183998 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184009 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184013 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184017 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 184021 */     // MIs[1] Operand 1
     /* 184021 */     // No operand predicates
     /* 184021 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184023 */     // (intrinsic_wo_chain:{ *:[v1f64] } 776:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 184023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
     /* 184026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184030 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184033 */     GIR_RootConstrainSelectedInstOperands,
     /* 184034 */     // GIR_Coverage, 6348,
     /* 184034 */     GIR_EraseRootFromParent_Done,
     /* 184035 */   // Label 3385: @184035
     /* 184035 */   GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(184088), // Rule ID 6349 //
     /* 184040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 184045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184070 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 184074 */     // MIs[1] Operand 1
     /* 184074 */     // No operand predicates
     /* 184074 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184076 */     // (intrinsic_wo_chain:{ *:[f32] } 775:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 184076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFs),
     /* 184079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184083 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184086 */     GIR_RootConstrainSelectedInstOperands,
     /* 184087 */     // GIR_Coverage, 6349,
     /* 184087 */     GIR_EraseRootFromParent_Done,
     /* 184088 */   // Label 3386: @184088
     /* 184088 */   GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(184170), // Rule ID 6351 //
     /* 184093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 184098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 184101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184115 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184119 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184123 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 184127 */     // MIs[1] Operand 1
     /* 184127 */     // No operand predicates
     /* 184127 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184129 */     // (intrinsic_wo_chain:{ *:[f16] } 775:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 184129 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 184132 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 184136 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184141 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 184147 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184152 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 184160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184162 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184165 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184168 */     GIR_RootConstrainSelectedInstOperands,
     /* 184169 */     // GIR_Coverage, 6351,
     /* 184169 */     GIR_EraseRootFromParent_Done,
     /* 184170 */   // Label 3387: @184170
     /* 184170 */   GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(184252), // Rule ID 6352 //
     /* 184175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 184180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 184183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184201 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184205 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 184209 */     // MIs[1] Operand 1
     /* 184209 */     // No operand predicates
     /* 184209 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184211 */     // (intrinsic_wo_chain:{ *:[f16] } 775:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 184211 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 184214 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 184218 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184223 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 184229 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184234 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 184242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184244 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184247 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184250 */     GIR_RootConstrainSelectedInstOperands,
     /* 184251 */     // GIR_Coverage, 6352,
     /* 184251 */     GIR_EraseRootFromParent_Done,
     /* 184252 */   // Label 3388: @184252
     /* 184252 */   GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(184334), // Rule ID 6354 //
     /* 184257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 184262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 184265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184287 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 184291 */     // MIs[1] Operand 1
     /* 184291 */     // No operand predicates
     /* 184291 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184293 */     // (intrinsic_wo_chain:{ *:[f16] } 776:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 184293 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 184296 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 184300 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184305 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 184311 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184316 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 184324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184326 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184329 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184332 */     GIR_RootConstrainSelectedInstOperands,
     /* 184333 */     // GIR_Coverage, 6354,
     /* 184333 */     GIR_EraseRootFromParent_Done,
     /* 184334 */   // Label 3389: @184334
     /* 184334 */   GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(184416), // Rule ID 6355 //
     /* 184339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 184344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 184347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184357 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184369 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 184373 */     // MIs[1] Operand 1
     /* 184373 */     // No operand predicates
     /* 184373 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184375 */     // (intrinsic_wo_chain:{ *:[f16] } 776:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 184375 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 184378 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 184382 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184387 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 184393 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184398 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 184406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184408 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184411 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 184414 */     GIR_RootConstrainSelectedInstOperands,
     /* 184415 */     // GIR_Coverage, 6355,
     /* 184415 */     GIR_EraseRootFromParent_Done,
     /* 184416 */   // Label 3390: @184416
     /* 184416 */   GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(184522), // Rule ID 6356 //
     /* 184421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 184426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184439 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184443 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184447 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184451 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 184455 */     // MIs[1] Operand 1
     /* 184455 */     // No operand predicates
     /* 184455 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184457 */     // (intrinsic_wo_chain:{ *:[i32] } 772:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
     /* 184457 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 184460 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
     /* 184464 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184469 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 184473 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
     /* 184476 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 184478 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 184481 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 184485 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184490 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 184492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 184495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 184497 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184500 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 184503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 184506 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184511 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184516 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184521 */     // GIR_Coverage, 6356,
     /* 184521 */     GIR_EraseRootFromParent_Done,
     /* 184522 */   // Label 3391: @184522
     /* 184522 */   GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(184628), // Rule ID 6357 //
     /* 184527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 184532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184545 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184557 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 184561 */     // MIs[1] Operand 1
     /* 184561 */     // No operand predicates
     /* 184561 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184563 */     // (intrinsic_wo_chain:{ *:[i64] } 772:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
     /* 184563 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 184566 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
     /* 184570 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184575 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 184579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
     /* 184582 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 184584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 184587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 184591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184596 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 184598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 184601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 184603 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184606 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 184609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 184612 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184617 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184622 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184627 */     // GIR_Coverage, 6357,
     /* 184627 */     GIR_EraseRootFromParent_Done,
     /* 184628 */   // Label 3392: @184628
     /* 184628 */   GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(184734), // Rule ID 6358 //
     /* 184633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 184638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184651 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184663 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 184667 */     // MIs[1] Operand 1
     /* 184667 */     // No operand predicates
     /* 184667 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184669 */     // (intrinsic_wo_chain:{ *:[i32] } 773:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
     /* 184669 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 184672 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
     /* 184676 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184681 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 184685 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
     /* 184688 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 184690 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 184693 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 184697 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184702 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 184704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 184707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 184709 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184712 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 184715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 184718 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184723 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184728 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184733 */     // GIR_Coverage, 6358,
     /* 184733 */     GIR_EraseRootFromParent_Done,
     /* 184734 */   // Label 3393: @184734
     /* 184734 */   GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(184840), // Rule ID 6359 //
     /* 184739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 184744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184750 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 184753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184757 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184765 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184769 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 184773 */     // MIs[1] Operand 1
     /* 184773 */     // No operand predicates
     /* 184773 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184775 */     // (intrinsic_wo_chain:{ *:[i64] } 773:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
     /* 184775 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 184778 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
     /* 184782 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184787 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 184791 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
     /* 184794 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 184796 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 184799 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 184803 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 184808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 184810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 184813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 184815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 184818 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 184821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 184824 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184829 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184834 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184839 */     // GIR_Coverage, 6359,
     /* 184839 */     GIR_EraseRootFromParent_Done,
     /* 184840 */   // Label 3394: @184840
     /* 184840 */   GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(184898), // Rule ID 7058 //
     /* 184845 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
     /* 184850 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184853 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184856 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 184859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 184863 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 184867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 184871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 184875 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64_0_65535),
     /* 184879 */     // MIs[1] Operand 1
     /* 184879 */     // No operand predicates
     /* 184879 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 184881 */     // (intrinsic_wo_chain:{ *:[i64] } 298:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm)  =>  (MOVKXi:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm), 48:{ *:[i32] })
     /* 184881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVKXi),
     /* 184884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 184888 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // imm
     /* 184893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/48,
     /* 184896 */     GIR_RootConstrainSelectedInstOperands,
     /* 184897 */     // GIR_Coverage, 7058,
     /* 184897 */     GIR_EraseRootFromParent_Done,
     /* 184898 */   // Label 3395: @184898
     /* 184898 */   GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(184940), // Rule ID 3060 //
     /* 184903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 184906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 184911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 184914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 184917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 184921 */     // MIs[0] Op2
     /* 184921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 184924 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
     /* 184929 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1874:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)  =>  (SSHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
     /* 184929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_H),
     /* 184932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 184934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 184936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 184938 */     GIR_RootConstrainSelectedInstOperands,
     /* 184939 */     // GIR_Coverage, 3060,
     /* 184939 */     GIR_EraseRootFromParent_Done,
     /* 184940 */   // Label 3396: @184940
     /* 184940 */   GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(184982), // Rule ID 3061 //
     /* 184945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 184948 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 184953 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 184956 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 184959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 184963 */     // MIs[0] Op2
     /* 184963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 184966 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
     /* 184971 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1874:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)  =>  (SSHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
     /* 184971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_S),
     /* 184974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 184976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 184978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 184980 */     GIR_RootConstrainSelectedInstOperands,
     /* 184981 */     // GIR_Coverage, 3061,
     /* 184981 */     GIR_EraseRootFromParent_Done,
     /* 184982 */   // Label 3397: @184982
     /* 184982 */   GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(185024), // Rule ID 3062 //
     /* 184987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 184990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 184995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 184998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185005 */     // MIs[0] Op2
     /* 185005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185008 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
     /* 185013 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1874:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)  =>  (SSHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
     /* 185013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_D),
     /* 185016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185022 */     GIR_RootConstrainSelectedInstOperands,
     /* 185023 */     // GIR_Coverage, 3062,
     /* 185023 */     GIR_EraseRootFromParent_Done,
     /* 185024 */   // Label 3398: @185024
     /* 185024 */   GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(185066), // Rule ID 3096 //
     /* 185029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 185037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185040 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185047 */     // MIs[0] Op2
     /* 185047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185050 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185055 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1855:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (SQSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_B),
     /* 185058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185064 */     GIR_RootConstrainSelectedInstOperands,
     /* 185065 */     // GIR_Coverage, 3096,
     /* 185065 */     GIR_EraseRootFromParent_Done,
     /* 185066 */   // Label 3399: @185066
     /* 185066 */   GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(185108), // Rule ID 3097 //
     /* 185071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185074 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 185079 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185089 */     // MIs[0] Op2
     /* 185089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185092 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 185097 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1855:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (SQSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 185097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_H),
     /* 185100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185106 */     GIR_RootConstrainSelectedInstOperands,
     /* 185107 */     // GIR_Coverage, 3097,
     /* 185107 */     GIR_EraseRootFromParent_Done,
     /* 185108 */   // Label 3400: @185108
     /* 185108 */   GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(185150), // Rule ID 3098 //
     /* 185113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 185121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185131 */     // MIs[0] Op2
     /* 185131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185134 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 185139 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1855:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (SQSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 185139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_S),
     /* 185142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185148 */     GIR_RootConstrainSelectedInstOperands,
     /* 185149 */     // GIR_Coverage, 3098,
     /* 185149 */     GIR_EraseRootFromParent_Done,
     /* 185150 */   // Label 3401: @185150
     /* 185150 */   GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(185192), // Rule ID 3557 //
     /* 185155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 185169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185173 */     // MIs[0] Op2
     /* 185173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185176 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 185181 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1355:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2)  =>  (DUPQ_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2)
     /* 185181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_B),
     /* 185184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185190 */     GIR_RootConstrainSelectedInstOperands,
     /* 185191 */     // GIR_Coverage, 3557,
     /* 185191 */     GIR_EraseRootFromParent_Done,
     /* 185192 */   // Label 3402: @185192
     /* 185192 */   GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(185234), // Rule ID 3558 //
     /* 185197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185208 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185215 */     // MIs[0] Op2
     /* 185215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185218 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 185223 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1355:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)  =>  (DUPQ_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
     /* 185223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
     /* 185226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185232 */     GIR_RootConstrainSelectedInstOperands,
     /* 185233 */     // GIR_Coverage, 3558,
     /* 185233 */     GIR_EraseRootFromParent_Done,
     /* 185234 */   // Label 3403: @185234
     /* 185234 */   GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(185276), // Rule ID 3559 //
     /* 185239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185257 */     // MIs[0] Op2
     /* 185257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185260 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 185265 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1355:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)  =>  (DUPQ_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
     /* 185265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
     /* 185268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185274 */     GIR_RootConstrainSelectedInstOperands,
     /* 185275 */     // GIR_Coverage, 3559,
     /* 185275 */     GIR_EraseRootFromParent_Done,
     /* 185276 */   // Label 3404: @185276
     /* 185276 */   GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(185318), // Rule ID 3560 //
     /* 185281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 185292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185299 */     // MIs[0] Op2
     /* 185299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185302 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 185307 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1355:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)  =>  (DUPQ_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
     /* 185307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
     /* 185310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185316 */     GIR_RootConstrainSelectedInstOperands,
     /* 185317 */     // GIR_Coverage, 3560,
     /* 185317 */     GIR_EraseRootFromParent_Done,
     /* 185318 */   // Label 3405: @185318
     /* 185318 */   GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(185360), // Rule ID 3561 //
     /* 185323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185341 */     // MIs[0] Op2
     /* 185341 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185344 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 185349 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1355:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)  =>  (DUPQ_ZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
     /* 185349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
     /* 185352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185354 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185356 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185358 */     GIR_RootConstrainSelectedInstOperands,
     /* 185359 */     // GIR_Coverage, 3561,
     /* 185359 */     GIR_EraseRootFromParent_Done,
     /* 185360 */   // Label 3406: @185360
     /* 185360 */   GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(185402), // Rule ID 3562 //
     /* 185365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185368 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185373 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185376 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185383 */     // MIs[0] Op2
     /* 185383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185386 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 185391 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1355:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)  =>  (DUPQ_ZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
     /* 185391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
     /* 185394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185400 */     GIR_RootConstrainSelectedInstOperands,
     /* 185401 */     // GIR_Coverage, 3562,
     /* 185401 */     GIR_EraseRootFromParent_Done,
     /* 185402 */   // Label 3407: @185402
     /* 185402 */   GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(185444), // Rule ID 3563 //
     /* 185407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 185410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 185415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 185418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185425 */     // MIs[0] Op2
     /* 185425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185428 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 185433 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1355:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)  =>  (DUPQ_ZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
     /* 185433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
     /* 185436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185442 */     GIR_RootConstrainSelectedInstOperands,
     /* 185443 */     // GIR_Coverage, 3563,
     /* 185443 */     GIR_EraseRootFromParent_Done,
     /* 185444 */   // Label 3408: @185444
     /* 185444 */   GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(185486), // Rule ID 11888 //
     /* 185449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 185457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185467 */     // MIs[0] Op2
     /* 185467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185470 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185475 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1849:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (SQRSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_B),
     /* 185478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185484 */     GIR_RootConstrainSelectedInstOperands,
     /* 185485 */     // GIR_Coverage, 11888,
     /* 185485 */     GIR_EraseRootFromParent_Done,
     /* 185486 */   // Label 3409: @185486
     /* 185486 */   GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(185528), // Rule ID 11889 //
     /* 185491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 185499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185509 */     // MIs[0] Op2
     /* 185509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185512 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 185517 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1849:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (SQRSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 185517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_H),
     /* 185520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185526 */     GIR_RootConstrainSelectedInstOperands,
     /* 185527 */     // GIR_Coverage, 11889,
     /* 185527 */     GIR_EraseRootFromParent_Done,
     /* 185528 */   // Label 3410: @185528
     /* 185528 */   GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(185570), // Rule ID 11890 //
     /* 185533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 185541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185551 */     // MIs[0] Op2
     /* 185551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185554 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 185559 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1849:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (SQRSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 185559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_S),
     /* 185562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185568 */     GIR_RootConstrainSelectedInstOperands,
     /* 185569 */     // GIR_Coverage, 11890,
     /* 185569 */     GIR_EraseRootFromParent_Done,
     /* 185570 */   // Label 3411: @185570
     /* 185570 */   GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(185612), // Rule ID 11891 //
     /* 185575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185578 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 185583 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185586 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185593 */     // MIs[0] Op2
     /* 185593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185596 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185601 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1728:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (SHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_B),
     /* 185604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185610 */     GIR_RootConstrainSelectedInstOperands,
     /* 185611 */     // GIR_Coverage, 11891,
     /* 185611 */     GIR_EraseRootFromParent_Done,
     /* 185612 */   // Label 3412: @185612
     /* 185612 */   GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(185654), // Rule ID 11892 //
     /* 185617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 185625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185635 */     // MIs[0] Op2
     /* 185635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185638 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 185643 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1728:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (SHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 185643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_H),
     /* 185646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185652 */     GIR_RootConstrainSelectedInstOperands,
     /* 185653 */     // GIR_Coverage, 11892,
     /* 185653 */     GIR_EraseRootFromParent_Done,
     /* 185654 */   // Label 3413: @185654
     /* 185654 */   GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(185696), // Rule ID 11893 //
     /* 185659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 185667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185677 */     // MIs[0] Op2
     /* 185677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185680 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 185685 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1728:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (SHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 185685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_S),
     /* 185688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185694 */     GIR_RootConstrainSelectedInstOperands,
     /* 185695 */     // GIR_Coverage, 11893,
     /* 185695 */     GIR_EraseRootFromParent_Done,
     /* 185696 */   // Label 3414: @185696
     /* 185696 */   GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(185738), // Rule ID 11895 //
     /* 185701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 185709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185719 */     // MIs[0] Op2
     /* 185719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185722 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185727 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1686:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (RSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_B),
     /* 185730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185736 */     GIR_RootConstrainSelectedInstOperands,
     /* 185737 */     // GIR_Coverage, 11895,
     /* 185737 */     GIR_EraseRootFromParent_Done,
     /* 185738 */   // Label 3415: @185738
     /* 185738 */   GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(185780), // Rule ID 11897 //
     /* 185743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 185751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185761 */     // MIs[0] Op2
     /* 185761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185764 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 185769 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1686:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (RSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 185769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_H),
     /* 185772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185778 */     GIR_RootConstrainSelectedInstOperands,
     /* 185779 */     // GIR_Coverage, 11897,
     /* 185779 */     GIR_EraseRootFromParent_Done,
     /* 185780 */   // Label 3416: @185780
     /* 185780 */   GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(185822), // Rule ID 11899 //
     /* 185785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185788 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 185793 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185803 */     // MIs[0] Op2
     /* 185803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185806 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 185811 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1686:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (RSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 185811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_S),
     /* 185814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185820 */     GIR_RootConstrainSelectedInstOperands,
     /* 185821 */     // GIR_Coverage, 11899,
     /* 185821 */     GIR_EraseRootFromParent_Done,
     /* 185822 */   // Label 3417: @185822
     /* 185822 */   GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(185864), // Rule ID 11900 //
     /* 185827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 185835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185838 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185845 */     // MIs[0] Op2
     /* 185845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185848 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185853 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1853:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (SQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_B),
     /* 185856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185862 */     GIR_RootConstrainSelectedInstOperands,
     /* 185863 */     // GIR_Coverage, 11900,
     /* 185863 */     GIR_EraseRootFromParent_Done,
     /* 185864 */   // Label 3418: @185864
     /* 185864 */   GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(185906), // Rule ID 11901 //
     /* 185869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 185877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 185880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 185883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185887 */     // MIs[0] Op2
     /* 185887 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185890 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 185895 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1853:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (SQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 185895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_H),
     /* 185898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185904 */     GIR_RootConstrainSelectedInstOperands,
     /* 185905 */     // GIR_Coverage, 11901,
     /* 185905 */     GIR_EraseRootFromParent_Done,
     /* 185906 */   // Label 3419: @185906
     /* 185906 */   GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(185948), // Rule ID 11902 //
     /* 185911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 185919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 185922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 185925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185929 */     // MIs[0] Op2
     /* 185929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185932 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 185937 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1853:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (SQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 185937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_S),
     /* 185940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185946 */     GIR_RootConstrainSelectedInstOperands,
     /* 185947 */     // GIR_Coverage, 11902,
     /* 185947 */     GIR_EraseRootFromParent_Done,
     /* 185948 */   // Label 3420: @185948
     /* 185948 */   GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(185990), // Rule ID 11903 //
     /* 185953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 185961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 185964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 185967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 185971 */     // MIs[0] Op2
     /* 185971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 185974 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 185979 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1843:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (SQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 185979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_B),
     /* 185982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 185984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 185986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 185988 */     GIR_RootConstrainSelectedInstOperands,
     /* 185989 */     // GIR_Coverage, 11903,
     /* 185989 */     GIR_EraseRootFromParent_Done,
     /* 185990 */   // Label 3421: @185990
     /* 185990 */   GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(186032), // Rule ID 11904 //
     /* 185995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 185998 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 186003 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186006 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186013 */     // MIs[0] Op2
     /* 186013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186016 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 186021 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1843:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (SQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 186021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_H),
     /* 186024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186030 */     GIR_RootConstrainSelectedInstOperands,
     /* 186031 */     // GIR_Coverage, 11904,
     /* 186031 */     GIR_EraseRootFromParent_Done,
     /* 186032 */   // Label 3422: @186032
     /* 186032 */   GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(186074), // Rule ID 11905 //
     /* 186037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 186045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 186051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186055 */     // MIs[0] Op2
     /* 186055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186058 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 186063 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1843:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (SQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 186063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_S),
     /* 186066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186072 */     GIR_RootConstrainSelectedInstOperands,
     /* 186073 */     // GIR_Coverage, 11905,
     /* 186073 */     GIR_EraseRootFromParent_Done,
     /* 186074 */   // Label 3423: @186074
     /* 186074 */   GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(186116), // Rule ID 11906 //
     /* 186079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 186087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 186090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 186093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186097 */     // MIs[0] Op2
     /* 186097 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186100 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 186105 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2048:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (UQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 186105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_B),
     /* 186108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186114 */     GIR_RootConstrainSelectedInstOperands,
     /* 186115 */     // GIR_Coverage, 11906,
     /* 186115 */     GIR_EraseRootFromParent_Done,
     /* 186116 */   // Label 3424: @186116
     /* 186116 */   GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(186158), // Rule ID 11907 //
     /* 186121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 186129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186139 */     // MIs[0] Op2
     /* 186139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186142 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 186147 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2048:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (UQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 186147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_H),
     /* 186150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186156 */     GIR_RootConstrainSelectedInstOperands,
     /* 186157 */     // GIR_Coverage, 11907,
     /* 186157 */     GIR_EraseRootFromParent_Done,
     /* 186158 */   // Label 3425: @186158
     /* 186158 */   GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(186200), // Rule ID 11908 //
     /* 186163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 186171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 186177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186181 */     // MIs[0] Op2
     /* 186181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186184 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 186189 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2048:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (UQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 186189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_S),
     /* 186192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186198 */     GIR_RootConstrainSelectedInstOperands,
     /* 186199 */     // GIR_Coverage, 11908,
     /* 186199 */     GIR_EraseRootFromParent_Done,
     /* 186200 */   // Label 3426: @186200
     /* 186200 */   GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(186242), // Rule ID 11909 //
     /* 186205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 186213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 186216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 186219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186223 */     // MIs[0] Op2
     /* 186223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186226 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 186231 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2045:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)  =>  (UQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
     /* 186231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_B),
     /* 186234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186240 */     GIR_RootConstrainSelectedInstOperands,
     /* 186241 */     // GIR_Coverage, 11909,
     /* 186241 */     GIR_EraseRootFromParent_Done,
     /* 186242 */   // Label 3427: @186242
     /* 186242 */   GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(186284), // Rule ID 11910 //
     /* 186247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 186255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186265 */     // MIs[0] Op2
     /* 186265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186268 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 186273 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2045:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)  =>  (UQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
     /* 186273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_H),
     /* 186276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186282 */     GIR_RootConstrainSelectedInstOperands,
     /* 186283 */     // GIR_Coverage, 11910,
     /* 186283 */     GIR_EraseRootFromParent_Done,
     /* 186284 */   // Label 3428: @186284
     /* 186284 */   GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(186326), // Rule ID 11911 //
     /* 186289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 186297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 186303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186307 */     // MIs[0] Op2
     /* 186307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186310 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 186315 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2045:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)  =>  (UQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
     /* 186315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_S),
     /* 186318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186320 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186322 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186324 */     GIR_RootConstrainSelectedInstOperands,
     /* 186325 */     // GIR_Coverage, 11911,
     /* 186325 */     GIR_EraseRootFromParent_Done,
     /* 186326 */   // Label 3429: @186326
     /* 186326 */   GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(186368), // Rule ID 11969 //
     /* 186331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 186339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 186345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186349 */     // MIs[0] Op2
     /* 186349 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186352 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
     /* 186357 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1875:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)  =>  (SSHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
     /* 186357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_H),
     /* 186360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186366 */     GIR_RootConstrainSelectedInstOperands,
     /* 186367 */     // GIR_Coverage, 11969,
     /* 186367 */     GIR_EraseRootFromParent_Done,
     /* 186368 */   // Label 3430: @186368
     /* 186368 */   GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(186410), // Rule ID 11970 //
     /* 186373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 186381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 186387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186391 */     // MIs[0] Op2
     /* 186391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186394 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
     /* 186399 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1875:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)  =>  (SSHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
     /* 186399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_S),
     /* 186402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186408 */     GIR_RootConstrainSelectedInstOperands,
     /* 186409 */     // GIR_Coverage, 11970,
     /* 186409 */     GIR_EraseRootFromParent_Done,
     /* 186410 */   // Label 3431: @186410
     /* 186410 */   GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(186452), // Rule ID 11971 //
     /* 186415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 186423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 186426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186433 */     // MIs[0] Op2
     /* 186433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186436 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
     /* 186441 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1875:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)  =>  (SSHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
     /* 186441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_D),
     /* 186444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186446 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186448 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186450 */     GIR_RootConstrainSelectedInstOperands,
     /* 186451 */     // GIR_Coverage, 11971,
     /* 186451 */     GIR_EraseRootFromParent_Done,
     /* 186452 */   // Label 3432: @186452
     /* 186452 */   GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(186494), // Rule ID 11972 //
     /* 186457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 186465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 186471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186475 */     // MIs[0] Op2
     /* 186475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186478 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
     /* 186483 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2068:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)  =>  (USHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
     /* 186483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_H),
     /* 186486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186490 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186492 */     GIR_RootConstrainSelectedInstOperands,
     /* 186493 */     // GIR_Coverage, 11972,
     /* 186493 */     GIR_EraseRootFromParent_Done,
     /* 186494 */   // Label 3433: @186494
     /* 186494 */   GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(186536), // Rule ID 11973 //
     /* 186499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 186507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 186513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186517 */     // MIs[0] Op2
     /* 186517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186520 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
     /* 186525 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2068:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)  =>  (USHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
     /* 186525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_S),
     /* 186528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186530 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186532 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186534 */     GIR_RootConstrainSelectedInstOperands,
     /* 186535 */     // GIR_Coverage, 11973,
     /* 186535 */     GIR_EraseRootFromParent_Done,
     /* 186536 */   // Label 3434: @186536
     /* 186536 */   GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(186578), // Rule ID 11974 //
     /* 186541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 186549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 186552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186559 */     // MIs[0] Op2
     /* 186559 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186562 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
     /* 186567 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2068:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)  =>  (USHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
     /* 186567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_D),
     /* 186570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186574 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186576 */     GIR_RootConstrainSelectedInstOperands,
     /* 186577 */     // GIR_Coverage, 11974,
     /* 186577 */     GIR_EraseRootFromParent_Done,
     /* 186578 */   // Label 3435: @186578
     /* 186578 */   GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(186620), // Rule ID 11975 //
     /* 186583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 186591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 186594 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 186597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186601 */     // MIs[0] Op2
     /* 186601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186604 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
     /* 186609 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2069:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)  =>  (USHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
     /* 186609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_H),
     /* 186612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186618 */     GIR_RootConstrainSelectedInstOperands,
     /* 186619 */     // GIR_Coverage, 11975,
     /* 186619 */     GIR_EraseRootFromParent_Done,
     /* 186620 */   // Label 3436: @186620
     /* 186620 */   GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(186662), // Rule ID 11976 //
     /* 186625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 186633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 186636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 186639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186643 */     // MIs[0] Op2
     /* 186643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186646 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
     /* 186651 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2069:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)  =>  (USHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
     /* 186651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_S),
     /* 186654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186656 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186658 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186660 */     GIR_RootConstrainSelectedInstOperands,
     /* 186661 */     // GIR_Coverage, 11976,
     /* 186661 */     GIR_EraseRootFromParent_Done,
     /* 186662 */   // Label 3437: @186662
     /* 186662 */   GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(186704), // Rule ID 11977 //
     /* 186667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 186670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 186675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 186678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 186681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 186685 */     // MIs[0] Op2
     /* 186685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 186688 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
     /* 186693 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2069:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)  =>  (USHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
     /* 186693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_D),
     /* 186696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 186698 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 186700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 186702 */     GIR_RootConstrainSelectedInstOperands,
     /* 186703 */     // GIR_Coverage, 11977,
     /* 186703 */     GIR_EraseRootFromParent_Done,
     /* 186704 */   // Label 3438: @186704
     /* 186704 */   GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(186756), // Rule ID 2136 //
     /* 186709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 186717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186734 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186738 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 186742 */     // MIs[1] Operand 1
     /* 186742 */     // No operand predicates
     /* 186742 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 186744 */     // (intrinsic_wo_chain:{ *:[v4i16] } 772:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 186744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i16_shift),
     /* 186747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186751 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 186754 */     GIR_RootConstrainSelectedInstOperands,
     /* 186755 */     // GIR_Coverage, 2136,
     /* 186755 */     GIR_EraseRootFromParent_Done,
     /* 186756 */   // Label 3439: @186756
     /* 186756 */   GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(186808), // Rule ID 2137 //
     /* 186761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 186769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 186772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 186775 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186786 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186790 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 186794 */     // MIs[1] Operand 1
     /* 186794 */     // No operand predicates
     /* 186794 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 186796 */     // (intrinsic_wo_chain:{ *:[v8i16] } 772:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 186796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8i16_shift),
     /* 186799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186803 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 186806 */     GIR_RootConstrainSelectedInstOperands,
     /* 186807 */     // GIR_Coverage, 2137,
     /* 186807 */     GIR_EraseRootFromParent_Done,
     /* 186808 */   // Label 3440: @186808
     /* 186808 */   GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(186860), // Rule ID 2138 //
     /* 186813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 186821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186834 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 186846 */     // MIs[1] Operand 1
     /* 186846 */     // No operand predicates
     /* 186846 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 186848 */     // (intrinsic_wo_chain:{ *:[v2i32] } 772:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 186848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i32_shift),
     /* 186851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186855 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 186858 */     GIR_RootConstrainSelectedInstOperands,
     /* 186859 */     // GIR_Coverage, 2138,
     /* 186859 */     GIR_EraseRootFromParent_Done,
     /* 186860 */   // Label 3441: @186860
     /* 186860 */   GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(186912), // Rule ID 2139 //
     /* 186865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 186873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186886 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 186898 */     // MIs[1] Operand 1
     /* 186898 */     // No operand predicates
     /* 186898 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 186900 */     // (intrinsic_wo_chain:{ *:[v4i32] } 772:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 186900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i32_shift),
     /* 186903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186907 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 186910 */     GIR_RootConstrainSelectedInstOperands,
     /* 186911 */     // GIR_Coverage, 2139,
     /* 186911 */     GIR_EraseRootFromParent_Done,
     /* 186912 */   // Label 3442: @186912
     /* 186912 */   GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(186964), // Rule ID 2140 //
     /* 186917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 186925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186938 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186942 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186946 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 186950 */     // MIs[1] Operand 1
     /* 186950 */     // No operand predicates
     /* 186950 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 186952 */     // (intrinsic_wo_chain:{ *:[v2i64] } 772:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 186952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i64_shift),
     /* 186955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186959 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 186962 */     GIR_RootConstrainSelectedInstOperands,
     /* 186963 */     // GIR_Coverage, 2140,
     /* 186963 */     GIR_EraseRootFromParent_Done,
     /* 186964 */   // Label 3443: @186964
     /* 186964 */   GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(187016), // Rule ID 2141 //
     /* 186969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 186977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 186986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186994 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 186998 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187002 */     // MIs[1] Operand 1
     /* 187002 */     // No operand predicates
     /* 187002 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187004 */     // (intrinsic_wo_chain:{ *:[v4i16] } 773:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i16_shift),
     /* 187007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187011 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187014 */     GIR_RootConstrainSelectedInstOperands,
     /* 187015 */     // GIR_Coverage, 2141,
     /* 187015 */     GIR_EraseRootFromParent_Done,
     /* 187016 */   // Label 3444: @187016
     /* 187016 */   GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(187068), // Rule ID 2142 //
     /* 187021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 187029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187035 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187054 */     // MIs[1] Operand 1
     /* 187054 */     // No operand predicates
     /* 187054 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187056 */     // (intrinsic_wo_chain:{ *:[v8i16] } 773:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8i16_shift),
     /* 187059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187063 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187066 */     GIR_RootConstrainSelectedInstOperands,
     /* 187067 */     // GIR_Coverage, 2142,
     /* 187067 */     GIR_EraseRootFromParent_Done,
     /* 187068 */   // Label 3445: @187068
     /* 187068 */   GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(187120), // Rule ID 2143 //
     /* 187073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 187081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187102 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187106 */     // MIs[1] Operand 1
     /* 187106 */     // No operand predicates
     /* 187106 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187108 */     // (intrinsic_wo_chain:{ *:[v2i32] } 773:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i32_shift),
     /* 187111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187113 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187115 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187118 */     GIR_RootConstrainSelectedInstOperands,
     /* 187119 */     // GIR_Coverage, 2143,
     /* 187119 */     GIR_EraseRootFromParent_Done,
     /* 187120 */   // Label 3446: @187120
     /* 187120 */   GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(187172), // Rule ID 2144 //
     /* 187125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 187133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187139 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187146 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187158 */     // MIs[1] Operand 1
     /* 187158 */     // No operand predicates
     /* 187158 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187160 */     // (intrinsic_wo_chain:{ *:[v4i32] } 773:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i32_shift),
     /* 187163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187167 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187170 */     GIR_RootConstrainSelectedInstOperands,
     /* 187171 */     // GIR_Coverage, 2144,
     /* 187171 */     GIR_EraseRootFromParent_Done,
     /* 187172 */   // Label 3447: @187172
     /* 187172 */   GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(187224), // Rule ID 2145 //
     /* 187177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 187185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187202 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187206 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187210 */     // MIs[1] Operand 1
     /* 187210 */     // No operand predicates
     /* 187210 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187212 */     // (intrinsic_wo_chain:{ *:[v2i64] } 773:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i64_shift),
     /* 187215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187219 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187222 */     GIR_RootConstrainSelectedInstOperands,
     /* 187223 */     // GIR_Coverage, 2145,
     /* 187223 */     GIR_EraseRootFromParent_Done,
     /* 187224 */   // Label 3448: @187224
     /* 187224 */   GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(187276), // Rule ID 2146 //
     /* 187229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 187237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 187240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 187243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187262 */     // MIs[1] Operand 1
     /* 187262 */     // No operand predicates
     /* 187262 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187264 */     // (intrinsic_wo_chain:{ *:[v4f16] } 775:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i16_shift),
     /* 187267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187271 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187274 */     GIR_RootConstrainSelectedInstOperands,
     /* 187275 */     // GIR_Coverage, 2146,
     /* 187275 */     GIR_EraseRootFromParent_Done,
     /* 187276 */   // Label 3449: @187276
     /* 187276 */   GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(187328), // Rule ID 2147 //
     /* 187281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 187289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187314 */     // MIs[1] Operand 1
     /* 187314 */     // No operand predicates
     /* 187314 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187316 */     // (intrinsic_wo_chain:{ *:[v8f16] } 775:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8i16_shift),
     /* 187319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187321 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187323 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187326 */     GIR_RootConstrainSelectedInstOperands,
     /* 187327 */     // GIR_Coverage, 2147,
     /* 187327 */     GIR_EraseRootFromParent_Done,
     /* 187328 */   // Label 3450: @187328
     /* 187328 */   GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(187380), // Rule ID 2148 //
     /* 187333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 187341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187358 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187362 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187366 */     // MIs[1] Operand 1
     /* 187366 */     // No operand predicates
     /* 187366 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187368 */     // (intrinsic_wo_chain:{ *:[v2f32] } 775:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i32_shift),
     /* 187371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187373 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187375 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187378 */     GIR_RootConstrainSelectedInstOperands,
     /* 187379 */     // GIR_Coverage, 2148,
     /* 187379 */     GIR_EraseRootFromParent_Done,
     /* 187380 */   // Label 3451: @187380
     /* 187380 */   GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(187432), // Rule ID 2149 //
     /* 187385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 187393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187418 */     // MIs[1] Operand 1
     /* 187418 */     // No operand predicates
     /* 187418 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187420 */     // (intrinsic_wo_chain:{ *:[v4f32] } 775:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i32_shift),
     /* 187423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187425 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187427 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187430 */     GIR_RootConstrainSelectedInstOperands,
     /* 187431 */     // GIR_Coverage, 2149,
     /* 187431 */     GIR_EraseRootFromParent_Done,
     /* 187432 */   // Label 3452: @187432
     /* 187432 */   GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(187484), // Rule ID 2150 //
     /* 187437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 187445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187462 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187466 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187470 */     // MIs[1] Operand 1
     /* 187470 */     // No operand predicates
     /* 187470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187472 */     // (intrinsic_wo_chain:{ *:[v2f64] } 775:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i64_shift),
     /* 187475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187479 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187482 */     GIR_RootConstrainSelectedInstOperands,
     /* 187483 */     // GIR_Coverage, 2150,
     /* 187483 */     GIR_EraseRootFromParent_Done,
     /* 187484 */   // Label 3453: @187484
     /* 187484 */   GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(187536), // Rule ID 2248 //
     /* 187489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 187497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 187500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 187503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187518 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187522 */     // MIs[1] Operand 1
     /* 187522 */     // No operand predicates
     /* 187522 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187524 */     // (intrinsic_wo_chain:{ *:[v4f16] } 776:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i16_shift),
     /* 187527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187531 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187534 */     GIR_RootConstrainSelectedInstOperands,
     /* 187535 */     // GIR_Coverage, 2248,
     /* 187535 */     GIR_EraseRootFromParent_Done,
     /* 187536 */   // Label 3454: @187536
     /* 187536 */   GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(187588), // Rule ID 2249 //
     /* 187541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 187549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187555 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187570 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187574 */     // MIs[1] Operand 1
     /* 187574 */     // No operand predicates
     /* 187574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187576 */     // (intrinsic_wo_chain:{ *:[v8f16] } 776:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8i16_shift),
     /* 187579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187581 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187583 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187586 */     GIR_RootConstrainSelectedInstOperands,
     /* 187587 */     // GIR_Coverage, 2249,
     /* 187587 */     GIR_EraseRootFromParent_Done,
     /* 187588 */   // Label 3455: @187588
     /* 187588 */   GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(187640), // Rule ID 2250 //
     /* 187593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 187601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187626 */     // MIs[1] Operand 1
     /* 187626 */     // No operand predicates
     /* 187626 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187628 */     // (intrinsic_wo_chain:{ *:[v2f32] } 776:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i32_shift),
     /* 187631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187635 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187638 */     GIR_RootConstrainSelectedInstOperands,
     /* 187639 */     // GIR_Coverage, 2250,
     /* 187639 */     GIR_EraseRootFromParent_Done,
     /* 187640 */   // Label 3456: @187640
     /* 187640 */   GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(187692), // Rule ID 2251 //
     /* 187645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 187653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187678 */     // MIs[1] Operand 1
     /* 187678 */     // No operand predicates
     /* 187678 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187680 */     // (intrinsic_wo_chain:{ *:[v4f32] } 776:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i32_shift),
     /* 187683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187687 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187690 */     GIR_RootConstrainSelectedInstOperands,
     /* 187691 */     // GIR_Coverage, 2251,
     /* 187691 */     GIR_EraseRootFromParent_Done,
     /* 187692 */   // Label 3457: @187692
     /* 187692 */   GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(187744), // Rule ID 2252 //
     /* 187697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 187705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 187726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 187730 */     // MIs[1] Operand 1
     /* 187730 */     // No operand predicates
     /* 187730 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 187732 */     // (intrinsic_wo_chain:{ *:[v2f64] } 776:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)  =>  (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 187732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i64_shift),
     /* 187735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187739 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 187742 */     GIR_RootConstrainSelectedInstOperands,
     /* 187743 */     // GIR_Coverage, 2252,
     /* 187743 */     GIR_EraseRootFromParent_Done,
     /* 187744 */   // Label 3458: @187744
     /* 187744 */   GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(187789), // Rule ID 63 //
     /* 187749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 187752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign_generic),
     /* 187757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 187760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 187763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 187766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 187770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 187774 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 187778 */     // (intrinsic_wo_chain:{ *:[i64] } 301:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (PACGA:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
     /* 187778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACGA),
     /* 187781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 187787 */     GIR_RootConstrainSelectedInstOperands,
     /* 187788 */     // GIR_Coverage, 63,
     /* 187788 */     GIR_EraseRootFromParent_Done,
     /* 187789 */   // Label 3459: @187789
     /* 187789 */   GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(187834), // Rule ID 129 //
     /* 187794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 187797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32b),
     /* 187802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 187805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 187808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187819 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187823 */     // (intrinsic_wo_chain:{ *:[i32] } 513:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 187823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Brr),
     /* 187826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 187832 */     GIR_RootConstrainSelectedInstOperands,
     /* 187833 */     // GIR_Coverage, 129,
     /* 187833 */     GIR_EraseRootFromParent_Done,
     /* 187834 */   // Label 3460: @187834
     /* 187834 */   GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(187879), // Rule ID 130 //
     /* 187839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 187842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32h),
     /* 187847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 187850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 187853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187864 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187868 */     // (intrinsic_wo_chain:{ *:[i32] } 518:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 187868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Hrr),
     /* 187871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 187877 */     GIR_RootConstrainSelectedInstOperands,
     /* 187878 */     // GIR_Coverage, 130,
     /* 187878 */     GIR_EraseRootFromParent_Done,
     /* 187879 */   // Label 3461: @187879
     /* 187879 */   GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(187924), // Rule ID 131 //
     /* 187884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 187887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32w),
     /* 187892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 187895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 187898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187909 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187913 */     // (intrinsic_wo_chain:{ *:[i32] } 519:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 187913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Wrr),
     /* 187916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 187922 */     GIR_RootConstrainSelectedInstOperands,
     /* 187923 */     // GIR_Coverage, 131,
     /* 187923 */     GIR_EraseRootFromParent_Done,
     /* 187924 */   // Label 3462: @187924
     /* 187924 */   GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(187969), // Rule ID 132 //
     /* 187929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 187932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32x),
     /* 187937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 187940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 187943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 187946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187950 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187954 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 187958 */     // (intrinsic_wo_chain:{ *:[i32] } 520:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 187958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Xrr),
     /* 187961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187965 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 187967 */     GIR_RootConstrainSelectedInstOperands,
     /* 187968 */     // GIR_Coverage, 132,
     /* 187968 */     GIR_EraseRootFromParent_Done,
     /* 187969 */   // Label 3463: @187969
     /* 187969 */   GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(188014), // Rule ID 133 //
     /* 187974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 187977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cb),
     /* 187982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 187985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 187988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 187991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 187999 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188003 */     // (intrinsic_wo_chain:{ *:[i32] } 514:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 188003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CBrr),
     /* 188006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188008 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188010 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188012 */     GIR_RootConstrainSelectedInstOperands,
     /* 188013 */     // GIR_Coverage, 133,
     /* 188013 */     GIR_EraseRootFromParent_Done,
     /* 188014 */   // Label 3464: @188014
     /* 188014 */   GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(188059), // Rule ID 134 //
     /* 188019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 188022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32ch),
     /* 188027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 188036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188044 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188048 */     // (intrinsic_wo_chain:{ *:[i32] } 515:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 188048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CHrr),
     /* 188051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188057 */     GIR_RootConstrainSelectedInstOperands,
     /* 188058 */     // GIR_Coverage, 134,
     /* 188058 */     GIR_EraseRootFromParent_Done,
     /* 188059 */   // Label 3465: @188059
     /* 188059 */   GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(188104), // Rule ID 135 //
     /* 188064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 188067 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cw),
     /* 188072 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188075 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188078 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 188081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188085 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188089 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188093 */     // (intrinsic_wo_chain:{ *:[i32] } 516:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 188093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CWrr),
     /* 188096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188098 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188102 */     GIR_RootConstrainSelectedInstOperands,
     /* 188103 */     // GIR_Coverage, 135,
     /* 188103 */     GIR_EraseRootFromParent_Done,
     /* 188104 */   // Label 3466: @188104
     /* 188104 */   GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(188149), // Rule ID 136 //
     /* 188109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 188112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cx),
     /* 188117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 188126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 188134 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 188138 */     // (intrinsic_wo_chain:{ *:[i32] } 517:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 188138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CXrr),
     /* 188141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188147 */     GIR_RootConstrainSelectedInstOperands,
     /* 188148 */     // GIR_Coverage, 136,
     /* 188148 */     GIR_EraseRootFromParent_Done,
     /* 188149 */   // Label 3467: @188149
     /* 188149 */   GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(188194), // Rule ID 1046 //
     /* 188154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 188165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 188168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 188171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188183 */     // (intrinsic_wo_chain:{ *:[v8i8] } 725:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /* 188183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i8),
     /* 188186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188192 */     GIR_RootConstrainSelectedInstOperands,
     /* 188193 */     // GIR_Coverage, 1046,
     /* 188193 */     GIR_EraseRootFromParent_Done,
     /* 188194 */   // Label 3468: @188194
     /* 188194 */   GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(188239), // Rule ID 1047 //
     /* 188199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 188210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 188213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 188216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188224 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188228 */     // (intrinsic_wo_chain:{ *:[v16i8] } 725:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 188228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv16i8),
     /* 188231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188237 */     GIR_RootConstrainSelectedInstOperands,
     /* 188238 */     // GIR_Coverage, 1047,
     /* 188238 */     GIR_EraseRootFromParent_Done,
     /* 188239 */   // Label 3469: @188239
     /* 188239 */   GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(188284), // Rule ID 1048 //
     /* 188244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 188255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 188258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 188261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188269 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188273 */     // (intrinsic_wo_chain:{ *:[v4i16] } 725:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /* 188273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i16),
     /* 188276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188282 */     GIR_RootConstrainSelectedInstOperands,
     /* 188283 */     // GIR_Coverage, 1048,
     /* 188283 */     GIR_EraseRootFromParent_Done,
     /* 188284 */   // Label 3470: @188284
     /* 188284 */   GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(188329), // Rule ID 1049 //
     /* 188289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 188300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 188303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 188306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188314 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188318 */     // (intrinsic_wo_chain:{ *:[v8i16] } 725:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)  =>  (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /* 188318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i16),
     /* 188321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188327 */     GIR_RootConstrainSelectedInstOperands,
     /* 188328 */     // GIR_Coverage, 1049,
     /* 188328 */     GIR_EraseRootFromParent_Done,
     /* 188329 */   // Label 3471: @188329
     /* 188329 */   GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(188374), // Rule ID 1050 //
     /* 188334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 188351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188355 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188359 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188363 */     // (intrinsic_wo_chain:{ *:[v2i32] } 725:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /* 188363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i32),
     /* 188366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188370 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188372 */     GIR_RootConstrainSelectedInstOperands,
     /* 188373 */     // GIR_Coverage, 1050,
     /* 188373 */     GIR_EraseRootFromParent_Done,
     /* 188374 */   // Label 3472: @188374
     /* 188374 */   GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(188419), // Rule ID 1051 //
     /* 188379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 188396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188400 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188404 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188408 */     // (intrinsic_wo_chain:{ *:[v4i32] } 725:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 188408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i32),
     /* 188411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188417 */     GIR_RootConstrainSelectedInstOperands,
     /* 188418 */     // GIR_Coverage, 1051,
     /* 188418 */     GIR_EraseRootFromParent_Done,
     /* 188419 */   // Label 3473: @188419
     /* 188419 */   GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(188464), // Rule ID 1052 //
     /* 188424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 188432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 188435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 188438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 188441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188445 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188449 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188453 */     // (intrinsic_wo_chain:{ *:[v2i64] } 725:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)  =>  (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
     /* 188453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i64),
     /* 188456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188460 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188462 */     GIR_RootConstrainSelectedInstOperands,
     /* 188463 */     // GIR_Coverage, 1052,
     /* 188463 */     GIR_EraseRootFromParent_Done,
     /* 188464 */   // Label 3474: @188464
     /* 188464 */   GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(188509), // Rule ID 1094 //
     /* 188469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 188480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 188483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 188486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188490 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188494 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188498 */     // (intrinsic_wo_chain:{ *:[v8i8] } 764:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /* 188498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i8),
     /* 188501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188507 */     GIR_RootConstrainSelectedInstOperands,
     /* 188508 */     // GIR_Coverage, 1094,
     /* 188508 */     GIR_EraseRootFromParent_Done,
     /* 188509 */   // Label 3475: @188509
     /* 188509 */   GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(188554), // Rule ID 1095 //
     /* 188514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 188525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 188528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 188531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188539 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188543 */     // (intrinsic_wo_chain:{ *:[v16i8] } 764:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 188543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv16i8),
     /* 188546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188552 */     GIR_RootConstrainSelectedInstOperands,
     /* 188553 */     // GIR_Coverage, 1095,
     /* 188553 */     GIR_EraseRootFromParent_Done,
     /* 188554 */   // Label 3476: @188554
     /* 188554 */   GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(188599), // Rule ID 1096 //
     /* 188559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 188570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 188573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 188576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188584 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188588 */     // (intrinsic_wo_chain:{ *:[v4i16] } 764:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /* 188588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i16),
     /* 188591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188595 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188597 */     GIR_RootConstrainSelectedInstOperands,
     /* 188598 */     // GIR_Coverage, 1096,
     /* 188598 */     GIR_EraseRootFromParent_Done,
     /* 188599 */   // Label 3477: @188599
     /* 188599 */   GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(188644), // Rule ID 1097 //
     /* 188604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 188615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 188618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 188621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188629 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188633 */     // (intrinsic_wo_chain:{ *:[v8i16] } 764:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)  =>  (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /* 188633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i16),
     /* 188636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188638 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188642 */     GIR_RootConstrainSelectedInstOperands,
     /* 188643 */     // GIR_Coverage, 1097,
     /* 188643 */     GIR_EraseRootFromParent_Done,
     /* 188644 */   // Label 3478: @188644
     /* 188644 */   GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(188689), // Rule ID 1098 //
     /* 188649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 188666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188674 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188678 */     // (intrinsic_wo_chain:{ *:[v2i32] } 764:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /* 188678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i32),
     /* 188681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188683 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188685 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188687 */     GIR_RootConstrainSelectedInstOperands,
     /* 188688 */     // GIR_Coverage, 1098,
     /* 188688 */     GIR_EraseRootFromParent_Done,
     /* 188689 */   // Label 3479: @188689
     /* 188689 */   GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(188734), // Rule ID 1099 //
     /* 188694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 188711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188715 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188719 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188723 */     // (intrinsic_wo_chain:{ *:[v4i32] } 764:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 188723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i32),
     /* 188726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188732 */     GIR_RootConstrainSelectedInstOperands,
     /* 188733 */     // GIR_Coverage, 1099,
     /* 188733 */     GIR_EraseRootFromParent_Done,
     /* 188734 */   // Label 3480: @188734
     /* 188734 */   GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(188779), // Rule ID 1100 //
     /* 188739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 188747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 188750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 188753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 188756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188764 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188768 */     // (intrinsic_wo_chain:{ *:[v2i64] } 764:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)  =>  (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
     /* 188768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i64),
     /* 188771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 188773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 188775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 188777 */     GIR_RootConstrainSelectedInstOperands,
     /* 188778 */     // GIR_Coverage, 1100,
     /* 188778 */     GIR_EraseRootFromParent_Done,
     /* 188779 */   // Label 3481: @188779
     /* 188779 */   GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(188824), // Rule ID 1112 //
     /* 188784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 188792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 188795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 188798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 188801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188809 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188813 */     // (intrinsic_wo_chain:{ *:[v8i8] } 580:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 188813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i8),
     /* 188816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188822 */     GIR_RootConstrainSelectedInstOperands,
     /* 188823 */     // GIR_Coverage, 1112,
     /* 188823 */     GIR_EraseRootFromParent_Done,
     /* 188824 */   // Label 3482: @188824
     /* 188824 */   GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(188869), // Rule ID 1114 //
     /* 188829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 188837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 188840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 188843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 188846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188854 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188858 */     // (intrinsic_wo_chain:{ *:[v16i8] } 580:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 188858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /* 188861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188865 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188867 */     GIR_RootConstrainSelectedInstOperands,
     /* 188868 */     // GIR_Coverage, 1114,
     /* 188868 */     GIR_EraseRootFromParent_Done,
     /* 188869 */   // Label 3483: @188869
     /* 188869 */   GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(188914), // Rule ID 1116 //
     /* 188874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 188882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 188885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 188888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 188891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188899 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188903 */     // (intrinsic_wo_chain:{ *:[v4i16] } 580:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 188903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i16),
     /* 188906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188908 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188910 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188912 */     GIR_RootConstrainSelectedInstOperands,
     /* 188913 */     // GIR_Coverage, 1116,
     /* 188913 */     GIR_EraseRootFromParent_Done,
     /* 188914 */   // Label 3484: @188914
     /* 188914 */   GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(188959), // Rule ID 1118 //
     /* 188919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 188927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 188930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 188933 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 188936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188944 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188948 */     // (intrinsic_wo_chain:{ *:[v8i16] } 580:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 188948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /* 188951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188955 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 188957 */     GIR_RootConstrainSelectedInstOperands,
     /* 188958 */     // GIR_Coverage, 1118,
     /* 188958 */     GIR_EraseRootFromParent_Done,
     /* 188959 */   // Label 3485: @188959
     /* 188959 */   GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(189004), // Rule ID 1120 //
     /* 188964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 188972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 188981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188989 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188993 */     // (intrinsic_wo_chain:{ *:[v2i32] } 580:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 188993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 188996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189002 */     GIR_RootConstrainSelectedInstOperands,
     /* 189003 */     // GIR_Coverage, 1120,
     /* 189003 */     GIR_EraseRootFromParent_Done,
     /* 189004 */   // Label 3486: @189004
     /* 189004 */   GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(189049), // Rule ID 1122 //
     /* 189009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 189017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 189020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 189026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189034 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189038 */     // (intrinsic_wo_chain:{ *:[v4i32] } 580:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 189038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /* 189041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189047 */     GIR_RootConstrainSelectedInstOperands,
     /* 189048 */     // GIR_Coverage, 1122,
     /* 189048 */     GIR_EraseRootFromParent_Done,
     /* 189049 */   // Label 3487: @189049
     /* 189049 */   GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(189094), // Rule ID 1124 //
     /* 189054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 189062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 189065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 189068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 189071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189075 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189079 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189083 */     // (intrinsic_wo_chain:{ *:[v2i64] } 580:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 189083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /* 189086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189092 */     GIR_RootConstrainSelectedInstOperands,
     /* 189093 */     // GIR_Coverage, 1124,
     /* 189093 */     GIR_EraseRootFromParent_Done,
     /* 189094 */   // Label 3488: @189094
     /* 189094 */   GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(189139), // Rule ID 1167 //
     /* 189099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 189107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 189110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 189116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189124 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189128 */     // (intrinsic_wo_chain:{ *:[v4f16] } 586:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 189128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
     /* 189131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189135 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189137 */     GIR_RootConstrainSelectedInstOperands,
     /* 189138 */     // GIR_Coverage, 1167,
     /* 189138 */     GIR_EraseRootFromParent_Done,
     /* 189139 */   // Label 3489: @189139
     /* 189139 */   GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(189184), // Rule ID 1168 //
     /* 189144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 189152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 189155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 189161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189169 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189173 */     // (intrinsic_wo_chain:{ *:[v8f16] } 586:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 189173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
     /* 189176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189182 */     GIR_RootConstrainSelectedInstOperands,
     /* 189183 */     // GIR_Coverage, 1168,
     /* 189183 */     GIR_EraseRootFromParent_Done,
     /* 189184 */   // Label 3490: @189184
     /* 189184 */   GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(189229), // Rule ID 1169 //
     /* 189189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 189197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 189200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 189203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 189206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189214 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189218 */     // (intrinsic_wo_chain:{ *:[v2f32] } 586:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 189218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
     /* 189221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189223 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189225 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189227 */     GIR_RootConstrainSelectedInstOperands,
     /* 189228 */     // GIR_Coverage, 1169,
     /* 189228 */     GIR_EraseRootFromParent_Done,
     /* 189229 */   // Label 3491: @189229
     /* 189229 */   GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(189274), // Rule ID 1170 //
     /* 189234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 189242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 189245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 189251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189259 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189263 */     // (intrinsic_wo_chain:{ *:[v4f32] } 586:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 189263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
     /* 189266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189270 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189272 */     GIR_RootConstrainSelectedInstOperands,
     /* 189273 */     // GIR_Coverage, 1170,
     /* 189273 */     GIR_EraseRootFromParent_Done,
     /* 189274 */   // Label 3492: @189274
     /* 189274 */   GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(189319), // Rule ID 1171 //
     /* 189279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 189287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 189290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 189293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 189296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189304 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189308 */     // (intrinsic_wo_chain:{ *:[v2f64] } 586:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 189308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
     /* 189311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189317 */     GIR_RootConstrainSelectedInstOperands,
     /* 189318 */     // GIR_Coverage, 1171,
     /* 189318 */     GIR_EraseRootFromParent_Done,
     /* 189319 */   // Label 3493: @189319
     /* 189319 */   GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(189364), // Rule ID 1173 //
     /* 189324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 189332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 189335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 189341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189345 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189349 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189353 */     // (intrinsic_wo_chain:{ *:[v4i16] } 587:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 189353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
     /* 189356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189360 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189362 */     GIR_RootConstrainSelectedInstOperands,
     /* 189363 */     // GIR_Coverage, 1173,
     /* 189363 */     GIR_EraseRootFromParent_Done,
     /* 189364 */   // Label 3494: @189364
     /* 189364 */   GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(189409), // Rule ID 1175 //
     /* 189369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 189377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 189380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 189386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189390 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189394 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189398 */     // (intrinsic_wo_chain:{ *:[v8i16] } 587:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 189398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
     /* 189401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189407 */     GIR_RootConstrainSelectedInstOperands,
     /* 189408 */     // GIR_Coverage, 1175,
     /* 189408 */     GIR_EraseRootFromParent_Done,
     /* 189409 */   // Label 3495: @189409
     /* 189409 */   GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(189454), // Rule ID 1177 //
     /* 189414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 189422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 189425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 189428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 189431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189435 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189439 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189443 */     // (intrinsic_wo_chain:{ *:[v2i32] } 587:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 189443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
     /* 189446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189452 */     GIR_RootConstrainSelectedInstOperands,
     /* 189453 */     // GIR_Coverage, 1177,
     /* 189453 */     GIR_EraseRootFromParent_Done,
     /* 189454 */   // Label 3496: @189454
     /* 189454 */   GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(189499), // Rule ID 1179 //
     /* 189459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189462 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 189467 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 189470 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189473 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 189476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189480 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189484 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189488 */     // (intrinsic_wo_chain:{ *:[v4i32] } 587:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 189488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
     /* 189491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189497 */     GIR_RootConstrainSelectedInstOperands,
     /* 189498 */     // GIR_Coverage, 1179,
     /* 189498 */     GIR_EraseRootFromParent_Done,
     /* 189499 */   // Label 3497: @189499
     /* 189499 */   GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(189544), // Rule ID 1181 //
     /* 189504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 189512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 189515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 189518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 189521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189525 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189529 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189533 */     // (intrinsic_wo_chain:{ *:[v2i64] } 587:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 189533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
     /* 189536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189538 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189540 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189542 */     GIR_RootConstrainSelectedInstOperands,
     /* 189543 */     // GIR_Coverage, 1181,
     /* 189543 */     GIR_EraseRootFromParent_Done,
     /* 189544 */   // Label 3498: @189544
     /* 189544 */   GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(189589), // Rule ID 1183 //
     /* 189549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 189557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 189560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 189566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189574 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189578 */     // (intrinsic_wo_chain:{ *:[v4i16] } 588:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 189578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
     /* 189581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189583 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189585 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189587 */     GIR_RootConstrainSelectedInstOperands,
     /* 189588 */     // GIR_Coverage, 1183,
     /* 189588 */     GIR_EraseRootFromParent_Done,
     /* 189589 */   // Label 3499: @189589
     /* 189589 */   GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(189634), // Rule ID 1185 //
     /* 189594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 189602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 189605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 189611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189619 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189623 */     // (intrinsic_wo_chain:{ *:[v8i16] } 588:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 189623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
     /* 189626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189632 */     GIR_RootConstrainSelectedInstOperands,
     /* 189633 */     // GIR_Coverage, 1185,
     /* 189633 */     GIR_EraseRootFromParent_Done,
     /* 189634 */   // Label 3500: @189634
     /* 189634 */   GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(189679), // Rule ID 1187 //
     /* 189639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 189647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 189650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 189653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 189656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189664 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189668 */     // (intrinsic_wo_chain:{ *:[v2i32] } 588:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 189668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
     /* 189671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189677 */     GIR_RootConstrainSelectedInstOperands,
     /* 189678 */     // GIR_Coverage, 1187,
     /* 189678 */     GIR_EraseRootFromParent_Done,
     /* 189679 */   // Label 3501: @189679
     /* 189679 */   GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(189724), // Rule ID 1189 //
     /* 189684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 189692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 189695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 189701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189709 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189713 */     // (intrinsic_wo_chain:{ *:[v4i32] } 588:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 189713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
     /* 189716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189722 */     GIR_RootConstrainSelectedInstOperands,
     /* 189723 */     // GIR_Coverage, 1189,
     /* 189723 */     GIR_EraseRootFromParent_Done,
     /* 189724 */   // Label 3502: @189724
     /* 189724 */   GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(189769), // Rule ID 1191 //
     /* 189729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 189737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 189740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 189743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 189746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189754 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189758 */     // (intrinsic_wo_chain:{ *:[v2i64] } 588:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 189758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
     /* 189761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189767 */     GIR_RootConstrainSelectedInstOperands,
     /* 189768 */     // GIR_Coverage, 1191,
     /* 189768 */     GIR_EraseRootFromParent_Done,
     /* 189769 */   // Label 3503: @189769
     /* 189769 */   GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(189814), // Rule ID 1193 //
     /* 189774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 189782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 189785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189788 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 189791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189799 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189803 */     // (intrinsic_wo_chain:{ *:[v4f16] } 589:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 189803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
     /* 189806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189812 */     GIR_RootConstrainSelectedInstOperands,
     /* 189813 */     // GIR_Coverage, 1193,
     /* 189813 */     GIR_EraseRootFromParent_Done,
     /* 189814 */   // Label 3504: @189814
     /* 189814 */   GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(189859), // Rule ID 1195 //
     /* 189819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 189827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 189830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 189836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189848 */     // (intrinsic_wo_chain:{ *:[v8f16] } 589:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 189848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 189851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189855 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189857 */     GIR_RootConstrainSelectedInstOperands,
     /* 189858 */     // GIR_Coverage, 1195,
     /* 189858 */     GIR_EraseRootFromParent_Done,
     /* 189859 */   // Label 3505: @189859
     /* 189859 */   GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(189904), // Rule ID 1197 //
     /* 189864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 189872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 189875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 189878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 189881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189889 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189893 */     // (intrinsic_wo_chain:{ *:[v2f32] } 589:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 189893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f32),
     /* 189896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189898 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189900 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189902 */     GIR_RootConstrainSelectedInstOperands,
     /* 189903 */     // GIR_Coverage, 1197,
     /* 189903 */     GIR_EraseRootFromParent_Done,
     /* 189904 */   // Label 3506: @189904
     /* 189904 */   GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(189949), // Rule ID 1199 //
     /* 189909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189912 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 189917 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 189920 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189923 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 189926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189934 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189938 */     // (intrinsic_wo_chain:{ *:[v4f32] } 589:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 189938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 189941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189945 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189947 */     GIR_RootConstrainSelectedInstOperands,
     /* 189948 */     // GIR_Coverage, 1199,
     /* 189948 */     GIR_EraseRootFromParent_Done,
     /* 189949 */   // Label 3507: @189949
     /* 189949 */   GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(189994), // Rule ID 1201 //
     /* 189954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 189962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 189965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 189968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 189971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189975 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189979 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189983 */     // (intrinsic_wo_chain:{ *:[v2f64] } 589:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 189983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 189986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 189992 */     GIR_RootConstrainSelectedInstOperands,
     /* 189993 */     // GIR_Coverage, 1201,
     /* 189993 */     GIR_EraseRootFromParent_Done,
     /* 189994 */   // Label 3508: @189994
     /* 189994 */   GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(190039), // Rule ID 1237 //
     /* 189999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 190007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 190016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190024 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190028 */     // (intrinsic_wo_chain:{ *:[v4f16] } 606:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 190028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f16),
     /* 190031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190037 */     GIR_RootConstrainSelectedInstOperands,
     /* 190038 */     // GIR_Coverage, 1237,
     /* 190038 */     GIR_EraseRootFromParent_Done,
     /* 190039 */   // Label 3509: @190039
     /* 190039 */   GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(190084), // Rule ID 1238 //
     /* 190044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 190052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 190055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 190061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190069 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190073 */     // (intrinsic_wo_chain:{ *:[v8f16] } 606:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 190073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv8f16),
     /* 190076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190082 */     GIR_RootConstrainSelectedInstOperands,
     /* 190083 */     // GIR_Coverage, 1238,
     /* 190083 */     GIR_EraseRootFromParent_Done,
     /* 190084 */   // Label 3510: @190084
     /* 190084 */   GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(190129), // Rule ID 1239 //
     /* 190089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 190097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 190100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 190103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 190106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190110 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190114 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190118 */     // (intrinsic_wo_chain:{ *:[v2f32] } 606:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 190118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f32),
     /* 190121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190127 */     GIR_RootConstrainSelectedInstOperands,
     /* 190128 */     // GIR_Coverage, 1239,
     /* 190128 */     GIR_EraseRootFromParent_Done,
     /* 190129 */   // Label 3511: @190129
     /* 190129 */   GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(190174), // Rule ID 1240 //
     /* 190134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 190142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 190145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 190151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190159 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190163 */     // (intrinsic_wo_chain:{ *:[v4f32] } 606:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 190163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f32),
     /* 190166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190172 */     GIR_RootConstrainSelectedInstOperands,
     /* 190173 */     // GIR_Coverage, 1240,
     /* 190173 */     GIR_EraseRootFromParent_Done,
     /* 190174 */   // Label 3512: @190174
     /* 190174 */   GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(190219), // Rule ID 1241 //
     /* 190179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 190187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 190190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 190193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 190196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190200 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190204 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190208 */     // (intrinsic_wo_chain:{ *:[v2f64] } 606:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 190208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f64),
     /* 190211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190215 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190217 */     GIR_RootConstrainSelectedInstOperands,
     /* 190218 */     // GIR_Coverage, 1241,
     /* 190218 */     GIR_EraseRootFromParent_Done,
     /* 190219 */   // Label 3513: @190219
     /* 190219 */   GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(190264), // Rule ID 1252 //
     /* 190224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 190232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 190241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190249 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190253 */     // (intrinsic_wo_chain:{ *:[v4f16] } 608:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 190253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f16),
     /* 190256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190262 */     GIR_RootConstrainSelectedInstOperands,
     /* 190263 */     // GIR_Coverage, 1252,
     /* 190263 */     GIR_EraseRootFromParent_Done,
     /* 190264 */   // Label 3514: @190264
     /* 190264 */   GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(190309), // Rule ID 1253 //
     /* 190269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 190277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 190280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 190286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190290 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190298 */     // (intrinsic_wo_chain:{ *:[v8f16] } 608:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 190298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv8f16),
     /* 190301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190307 */     GIR_RootConstrainSelectedInstOperands,
     /* 190308 */     // GIR_Coverage, 1253,
     /* 190308 */     GIR_EraseRootFromParent_Done,
     /* 190309 */   // Label 3515: @190309
     /* 190309 */   GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(190354), // Rule ID 1254 //
     /* 190314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 190322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 190325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 190328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 190331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190335 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190339 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190343 */     // (intrinsic_wo_chain:{ *:[v2f32] } 608:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 190343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f32),
     /* 190346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190352 */     GIR_RootConstrainSelectedInstOperands,
     /* 190353 */     // GIR_Coverage, 1254,
     /* 190353 */     GIR_EraseRootFromParent_Done,
     /* 190354 */   // Label 3516: @190354
     /* 190354 */   GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(190399), // Rule ID 1255 //
     /* 190359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 190367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 190370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 190376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190384 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190388 */     // (intrinsic_wo_chain:{ *:[v4f32] } 608:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 190388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f32),
     /* 190391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190395 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190397 */     GIR_RootConstrainSelectedInstOperands,
     /* 190398 */     // GIR_Coverage, 1255,
     /* 190398 */     GIR_EraseRootFromParent_Done,
     /* 190399 */   // Label 3517: @190399
     /* 190399 */   GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(190444), // Rule ID 1256 //
     /* 190404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 190412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 190415 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 190418 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 190421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190429 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190433 */     // (intrinsic_wo_chain:{ *:[v2f64] } 608:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 190433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f64),
     /* 190436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190442 */     GIR_RootConstrainSelectedInstOperands,
     /* 190443 */     // GIR_Coverage, 1256,
     /* 190443 */     GIR_EraseRootFromParent_Done,
     /* 190444 */   // Label 3518: @190444
     /* 190444 */   GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(190489), // Rule ID 1267 //
     /* 190449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 190457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 190466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190470 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190474 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190478 */     // (intrinsic_wo_chain:{ *:[v4f16] } 612:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 190478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f16),
     /* 190481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190483 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190485 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190487 */     GIR_RootConstrainSelectedInstOperands,
     /* 190488 */     // GIR_Coverage, 1267,
     /* 190488 */     GIR_EraseRootFromParent_Done,
     /* 190489 */   // Label 3519: @190489
     /* 190489 */   GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(190534), // Rule ID 1268 //
     /* 190494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 190502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 190505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 190511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190515 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190519 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190523 */     // (intrinsic_wo_chain:{ *:[v8f16] } 612:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 190523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv8f16),
     /* 190526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190530 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190532 */     GIR_RootConstrainSelectedInstOperands,
     /* 190533 */     // GIR_Coverage, 1268,
     /* 190533 */     GIR_EraseRootFromParent_Done,
     /* 190534 */   // Label 3520: @190534
     /* 190534 */   GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(190579), // Rule ID 1269 //
     /* 190539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 190547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 190550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 190553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 190556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190564 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190568 */     // (intrinsic_wo_chain:{ *:[v2f32] } 612:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 190568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f32),
     /* 190571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190577 */     GIR_RootConstrainSelectedInstOperands,
     /* 190578 */     // GIR_Coverage, 1269,
     /* 190578 */     GIR_EraseRootFromParent_Done,
     /* 190579 */   // Label 3521: @190579
     /* 190579 */   GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(190624), // Rule ID 1270 //
     /* 190584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 190592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 190595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 190601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190605 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190609 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190613 */     // (intrinsic_wo_chain:{ *:[v4f32] } 612:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 190613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f32),
     /* 190616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190622 */     GIR_RootConstrainSelectedInstOperands,
     /* 190623 */     // GIR_Coverage, 1270,
     /* 190623 */     GIR_EraseRootFromParent_Done,
     /* 190624 */   // Label 3522: @190624
     /* 190624 */   GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(190669), // Rule ID 1271 //
     /* 190629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 190637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 190640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 190643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 190646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190654 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190658 */     // (intrinsic_wo_chain:{ *:[v2f64] } 612:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 190658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f64),
     /* 190661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190667 */     GIR_RootConstrainSelectedInstOperands,
     /* 190668 */     // GIR_Coverage, 1271,
     /* 190668 */     GIR_EraseRootFromParent_Done,
     /* 190669 */   // Label 3523: @190669
     /* 190669 */   GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(190714), // Rule ID 1282 //
     /* 190674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 190682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 190691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190699 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190703 */     // (intrinsic_wo_chain:{ *:[v4f16] } 614:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 190703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f16),
     /* 190706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190710 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190712 */     GIR_RootConstrainSelectedInstOperands,
     /* 190713 */     // GIR_Coverage, 1282,
     /* 190713 */     GIR_EraseRootFromParent_Done,
     /* 190714 */   // Label 3524: @190714
     /* 190714 */   GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(190759), // Rule ID 1283 //
     /* 190719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 190727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 190730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 190736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190744 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190748 */     // (intrinsic_wo_chain:{ *:[v8f16] } 614:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 190748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv8f16),
     /* 190751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190757 */     GIR_RootConstrainSelectedInstOperands,
     /* 190758 */     // GIR_Coverage, 1283,
     /* 190758 */     GIR_EraseRootFromParent_Done,
     /* 190759 */   // Label 3525: @190759
     /* 190759 */   GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(190804), // Rule ID 1284 //
     /* 190764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 190772 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 190775 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 190778 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 190781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190785 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190789 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190793 */     // (intrinsic_wo_chain:{ *:[v2f32] } 614:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 190793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f32),
     /* 190796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190798 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190800 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190802 */     GIR_RootConstrainSelectedInstOperands,
     /* 190803 */     // GIR_Coverage, 1284,
     /* 190803 */     GIR_EraseRootFromParent_Done,
     /* 190804 */   // Label 3526: @190804
     /* 190804 */   GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(190849), // Rule ID 1285 //
     /* 190809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190812 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 190817 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 190820 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 190826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190830 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190834 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190838 */     // (intrinsic_wo_chain:{ *:[v4f32] } 614:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 190838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f32),
     /* 190841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190847 */     GIR_RootConstrainSelectedInstOperands,
     /* 190848 */     // GIR_Coverage, 1285,
     /* 190848 */     GIR_EraseRootFromParent_Done,
     /* 190849 */   // Label 3527: @190849
     /* 190849 */   GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(190894), // Rule ID 1286 //
     /* 190854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 190862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 190865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 190868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 190871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190879 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190883 */     // (intrinsic_wo_chain:{ *:[v2f64] } 614:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 190883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f64),
     /* 190886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190890 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190892 */     GIR_RootConstrainSelectedInstOperands,
     /* 190893 */     // GIR_Coverage, 1286,
     /* 190893 */     GIR_EraseRootFromParent_Done,
     /* 190894 */   // Label 3528: @190894
     /* 190894 */   GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(190939), // Rule ID 1317 //
     /* 190899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 190907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 190916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190924 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190928 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 190928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f16),
     /* 190931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190937 */     GIR_RootConstrainSelectedInstOperands,
     /* 190938 */     // GIR_Coverage, 1317,
     /* 190938 */     GIR_EraseRootFromParent_Done,
     /* 190939 */   // Label 3529: @190939
     /* 190939 */   GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(190984), // Rule ID 1318 //
     /* 190944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 190952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 190955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 190961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190965 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190969 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190973 */     // (intrinsic_wo_chain:{ *:[v8f16] } 620:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 190973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8f16),
     /* 190976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 190982 */     GIR_RootConstrainSelectedInstOperands,
     /* 190983 */     // GIR_Coverage, 1318,
     /* 190983 */     GIR_EraseRootFromParent_Done,
     /* 190984 */   // Label 3530: @190984
     /* 190984 */   GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(191029), // Rule ID 1319 //
     /* 190989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 190997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 191000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 191006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191014 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191018 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 191018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f32),
     /* 191021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191025 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191027 */     GIR_RootConstrainSelectedInstOperands,
     /* 191028 */     // GIR_Coverage, 1319,
     /* 191028 */     GIR_EraseRootFromParent_Done,
     /* 191029 */   // Label 3531: @191029
     /* 191029 */   GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(191074), // Rule ID 1320 //
     /* 191034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 191042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 191045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 191048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 191051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191055 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191059 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191063 */     // (intrinsic_wo_chain:{ *:[v4f32] } 620:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 191063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f32),
     /* 191066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191072 */     GIR_RootConstrainSelectedInstOperands,
     /* 191073 */     // GIR_Coverage, 1320,
     /* 191073 */     GIR_EraseRootFromParent_Done,
     /* 191074 */   // Label 3532: @191074
     /* 191074 */   GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(191119), // Rule ID 1321 //
     /* 191079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 191087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 191090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191093 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 191096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191108 */     // (intrinsic_wo_chain:{ *:[v2f64] } 620:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 191108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f64),
     /* 191111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191113 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191115 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191117 */     GIR_RootConstrainSelectedInstOperands,
     /* 191118 */     // GIR_Coverage, 1321,
     /* 191118 */     GIR_EraseRootFromParent_Done,
     /* 191119 */   // Label 3533: @191119
     /* 191119 */   GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(191164), // Rule ID 1332 //
     /* 191124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 191127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 191132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 191135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 191138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 191141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191153 */     // (intrinsic_wo_chain:{ *:[v4f16] } 643:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 191153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f16),
     /* 191156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191160 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191162 */     GIR_RootConstrainSelectedInstOperands,
     /* 191163 */     // GIR_Coverage, 1332,
     /* 191163 */     GIR_EraseRootFromParent_Done,
     /* 191164 */   // Label 3534: @191164
     /* 191164 */   GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(191209), // Rule ID 1333 //
     /* 191169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 191172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 191177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 191180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 191183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 191186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191190 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191194 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191198 */     // (intrinsic_wo_chain:{ *:[v8f16] } 643:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 191198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv8f16),
     /* 191201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191207 */     GIR_RootConstrainSelectedInstOperands,
     /* 191208 */     // GIR_Coverage, 1333,
     /* 191208 */     GIR_EraseRootFromParent_Done,
     /* 191209 */   // Label 3535: @191209
     /* 191209 */   GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(191254), // Rule ID 1334 //
     /* 191214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 191222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 191225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 191231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191239 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191243 */     // (intrinsic_wo_chain:{ *:[v2f32] } 643:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 191243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f32),
     /* 191246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191250 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191252 */     GIR_RootConstrainSelectedInstOperands,
     /* 191253 */     // GIR_Coverage, 1334,
     /* 191253 */     GIR_EraseRootFromParent_Done,
     /* 191254 */   // Label 3536: @191254
     /* 191254 */   GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(191299), // Rule ID 1335 //
     /* 191259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 191267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 191270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 191273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 191276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191284 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191288 */     // (intrinsic_wo_chain:{ *:[v4f32] } 643:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 191288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f32),
     /* 191291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191297 */     GIR_RootConstrainSelectedInstOperands,
     /* 191298 */     // GIR_Coverage, 1335,
     /* 191298 */     GIR_EraseRootFromParent_Done,
     /* 191299 */   // Label 3537: @191299
     /* 191299 */   GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(191344), // Rule ID 1336 //
     /* 191304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 191312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 191315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 191321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191329 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191333 */     // (intrinsic_wo_chain:{ *:[v2f64] } 643:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 191333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f64),
     /* 191336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191342 */     GIR_RootConstrainSelectedInstOperands,
     /* 191343 */     // GIR_Coverage, 1336,
     /* 191343 */     GIR_EraseRootFromParent_Done,
     /* 191344 */   // Label 3538: @191344
     /* 191344 */   GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(191389), // Rule ID 1337 //
     /* 191349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 191352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 191357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 191360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 191363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 191366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191370 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191374 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191378 */     // (intrinsic_wo_chain:{ *:[v4f16] } 650:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 191378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f16),
     /* 191381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191385 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191387 */     GIR_RootConstrainSelectedInstOperands,
     /* 191388 */     // GIR_Coverage, 1337,
     /* 191388 */     GIR_EraseRootFromParent_Done,
     /* 191389 */   // Label 3539: @191389
     /* 191389 */   GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(191434), // Rule ID 1338 //
     /* 191394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 191397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 191402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 191405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 191408 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 191411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191423 */     // (intrinsic_wo_chain:{ *:[v8f16] } 650:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 191423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv8f16),
     /* 191426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191430 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191432 */     GIR_RootConstrainSelectedInstOperands,
     /* 191433 */     // GIR_Coverage, 1338,
     /* 191433 */     GIR_EraseRootFromParent_Done,
     /* 191434 */   // Label 3540: @191434
     /* 191434 */   GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(191479), // Rule ID 1339 //
     /* 191439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 191447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 191450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 191456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191460 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191464 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191468 */     // (intrinsic_wo_chain:{ *:[v2f32] } 650:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 191468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f32),
     /* 191471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191477 */     GIR_RootConstrainSelectedInstOperands,
     /* 191478 */     // GIR_Coverage, 1339,
     /* 191478 */     GIR_EraseRootFromParent_Done,
     /* 191479 */   // Label 3541: @191479
     /* 191479 */   GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(191524), // Rule ID 1340 //
     /* 191484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 191492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 191495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 191498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 191501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191509 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191513 */     // (intrinsic_wo_chain:{ *:[v4f32] } 650:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 191513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f32),
     /* 191516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191522 */     GIR_RootConstrainSelectedInstOperands,
     /* 191523 */     // GIR_Coverage, 1340,
     /* 191523 */     GIR_EraseRootFromParent_Done,
     /* 191524 */   // Label 3542: @191524
     /* 191524 */   GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(191569), // Rule ID 1341 //
     /* 191529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 191537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 191540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 191546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191554 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191558 */     // (intrinsic_wo_chain:{ *:[v2f64] } 650:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 191558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f64),
     /* 191561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191567 */     GIR_RootConstrainSelectedInstOperands,
     /* 191568 */     // GIR_Coverage, 1341,
     /* 191568 */     GIR_EraseRootFromParent_Done,
     /* 191569 */   // Label 3543: @191569
     /* 191569 */   GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(191614), // Rule ID 1358 //
     /* 191574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
     /* 191582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 191585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 191588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 191591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191599 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191603 */     // (intrinsic_wo_chain:{ *:[v8i8] } 663:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 191603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv8i8),
     /* 191606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191612 */     GIR_RootConstrainSelectedInstOperands,
     /* 191613 */     // GIR_Coverage, 1358,
     /* 191613 */     GIR_EraseRootFromParent_Done,
     /* 191614 */   // Label 3544: @191614
     /* 191614 */   GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(191659), // Rule ID 1359 //
     /* 191619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
     /* 191627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 191630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 191633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 191636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191644 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191648 */     // (intrinsic_wo_chain:{ *:[v16i8] } 663:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 191648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv16i8),
     /* 191651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191655 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191657 */     GIR_RootConstrainSelectedInstOperands,
     /* 191658 */     // GIR_Coverage, 1359,
     /* 191658 */     GIR_EraseRootFromParent_Done,
     /* 191659 */   // Label 3545: @191659
     /* 191659 */   GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(191704), // Rule ID 1373 //
     /* 191664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 191675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 191678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 191681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191685 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191689 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191693 */     // (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 191693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i8),
     /* 191696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191698 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191702 */     GIR_RootConstrainSelectedInstOperands,
     /* 191703 */     // GIR_Coverage, 1373,
     /* 191703 */     GIR_EraseRootFromParent_Done,
     /* 191704 */   // Label 3546: @191704
     /* 191704 */   GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(191749), // Rule ID 1375 //
     /* 191709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 191720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 191723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 191726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191734 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191738 */     // (intrinsic_wo_chain:{ *:[v16i8] } 669:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 191738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv16i8),
     /* 191741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191745 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191747 */     GIR_RootConstrainSelectedInstOperands,
     /* 191748 */     // GIR_Coverage, 1375,
     /* 191748 */     GIR_EraseRootFromParent_Done,
     /* 191749 */   // Label 3547: @191749
     /* 191749 */   GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(191794), // Rule ID 1377 //
     /* 191754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 191765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 191768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 191771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191775 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191779 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191783 */     // (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 191783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i16),
     /* 191786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191790 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191792 */     GIR_RootConstrainSelectedInstOperands,
     /* 191793 */     // GIR_Coverage, 1377,
     /* 191793 */     GIR_EraseRootFromParent_Done,
     /* 191794 */   // Label 3548: @191794
     /* 191794 */   GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(191839), // Rule ID 1379 //
     /* 191799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 191810 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 191813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 191816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191824 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191828 */     // (intrinsic_wo_chain:{ *:[v8i16] } 669:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 191828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i16),
     /* 191831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191833 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191835 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191837 */     GIR_RootConstrainSelectedInstOperands,
     /* 191838 */     // GIR_Coverage, 1379,
     /* 191838 */     GIR_EraseRootFromParent_Done,
     /* 191839 */   // Label 3549: @191839
     /* 191839 */   GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(191884), // Rule ID 1381 //
     /* 191844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 191855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 191861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191865 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191869 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191873 */     // (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 191873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv2i32),
     /* 191876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191880 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191882 */     GIR_RootConstrainSelectedInstOperands,
     /* 191883 */     // GIR_Coverage, 1381,
     /* 191883 */     GIR_EraseRootFromParent_Done,
     /* 191884 */   // Label 3550: @191884
     /* 191884 */   GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(191929), // Rule ID 1383 //
     /* 191889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 191897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 191900 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 191903 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 191906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191910 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191914 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191918 */     // (intrinsic_wo_chain:{ *:[v4i32] } 669:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 191918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i32),
     /* 191921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191927 */     GIR_RootConstrainSelectedInstOperands,
     /* 191928 */     // GIR_Coverage, 1383,
     /* 191928 */     GIR_EraseRootFromParent_Done,
     /* 191929 */   // Label 3551: @191929
     /* 191929 */   GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(191974), // Rule ID 1390 //
     /* 191934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 191942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 191945 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 191948 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 191951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191959 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191963 */     // (intrinsic_wo_chain:{ *:[v8i8] } 679:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 191963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i8),
     /* 191966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 191972 */     GIR_RootConstrainSelectedInstOperands,
     /* 191973 */     // GIR_Coverage, 1390,
     /* 191973 */     GIR_EraseRootFromParent_Done,
     /* 191974 */   // Label 3552: @191974
     /* 191974 */   GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(192019), // Rule ID 1391 //
     /* 191979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 191982 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 191987 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 191990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 191993 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 191996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192004 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192008 */     // (intrinsic_wo_chain:{ *:[v16i8] } 679:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 192008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv16i8),
     /* 192011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192015 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192017 */     GIR_RootConstrainSelectedInstOperands,
     /* 192018 */     // GIR_Coverage, 1391,
     /* 192018 */     GIR_EraseRootFromParent_Done,
     /* 192019 */   // Label 3553: @192019
     /* 192019 */   GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(192064), // Rule ID 1392 //
     /* 192024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 192032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 192035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 192041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192045 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192049 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192053 */     // (intrinsic_wo_chain:{ *:[v4i16] } 679:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 192053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i16),
     /* 192056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192058 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192060 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192062 */     GIR_RootConstrainSelectedInstOperands,
     /* 192063 */     // GIR_Coverage, 1392,
     /* 192063 */     GIR_EraseRootFromParent_Done,
     /* 192064 */   // Label 3554: @192064
     /* 192064 */   GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(192109), // Rule ID 1393 //
     /* 192069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 192077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 192080 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192083 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 192086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192094 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192098 */     // (intrinsic_wo_chain:{ *:[v8i16] } 679:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 192098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i16),
     /* 192101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192103 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192105 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192107 */     GIR_RootConstrainSelectedInstOperands,
     /* 192108 */     // GIR_Coverage, 1393,
     /* 192108 */     GIR_EraseRootFromParent_Done,
     /* 192109 */   // Label 3555: @192109
     /* 192109 */   GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(192154), // Rule ID 1394 //
     /* 192114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 192122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 192125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192128 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 192131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192139 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192143 */     // (intrinsic_wo_chain:{ *:[v2i32] } 679:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 192143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv2i32),
     /* 192146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192150 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192152 */     GIR_RootConstrainSelectedInstOperands,
     /* 192153 */     // GIR_Coverage, 1394,
     /* 192153 */     GIR_EraseRootFromParent_Done,
     /* 192154 */   // Label 3556: @192154
     /* 192154 */   GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(192199), // Rule ID 1395 //
     /* 192159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 192167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 192170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 192176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192184 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192188 */     // (intrinsic_wo_chain:{ *:[v4i32] } 679:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 192188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i32),
     /* 192191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192195 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192197 */     GIR_RootConstrainSelectedInstOperands,
     /* 192198 */     // GIR_Coverage, 1395,
     /* 192198 */     GIR_EraseRootFromParent_Done,
     /* 192199 */   // Label 3557: @192199
     /* 192199 */   GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(192244), // Rule ID 1396 //
     /* 192204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 192215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 192218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 192221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192233 */     // (intrinsic_wo_chain:{ *:[v8i8] } 681:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 192233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i8),
     /* 192236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192242 */     GIR_RootConstrainSelectedInstOperands,
     /* 192243 */     // GIR_Coverage, 1396,
     /* 192243 */     GIR_EraseRootFromParent_Done,
     /* 192244 */   // Label 3558: @192244
     /* 192244 */   GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(192289), // Rule ID 1397 //
     /* 192249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 192260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 192263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 192266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192274 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192278 */     // (intrinsic_wo_chain:{ *:[v16i8] } 681:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 192278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv16i8),
     /* 192281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192283 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192285 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192287 */     GIR_RootConstrainSelectedInstOperands,
     /* 192288 */     // GIR_Coverage, 1397,
     /* 192288 */     GIR_EraseRootFromParent_Done,
     /* 192289 */   // Label 3559: @192289
     /* 192289 */   GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(192334), // Rule ID 1398 //
     /* 192294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 192305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 192311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192319 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192323 */     // (intrinsic_wo_chain:{ *:[v4i16] } 681:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 192323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i16),
     /* 192326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192328 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192330 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192332 */     GIR_RootConstrainSelectedInstOperands,
     /* 192333 */     // GIR_Coverage, 1398,
     /* 192333 */     GIR_EraseRootFromParent_Done,
     /* 192334 */   // Label 3560: @192334
     /* 192334 */   GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(192379), // Rule ID 1399 //
     /* 192339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192347 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 192350 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192353 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 192356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192364 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192368 */     // (intrinsic_wo_chain:{ *:[v8i16] } 681:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 192368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i16),
     /* 192371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192373 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192375 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192377 */     GIR_RootConstrainSelectedInstOperands,
     /* 192378 */     // GIR_Coverage, 1399,
     /* 192378 */     GIR_EraseRootFromParent_Done,
     /* 192379 */   // Label 3561: @192379
     /* 192379 */   GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(192424), // Rule ID 1400 //
     /* 192384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 192395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 192401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192409 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192413 */     // (intrinsic_wo_chain:{ *:[v2i32] } 681:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 192413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 192416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192422 */     GIR_RootConstrainSelectedInstOperands,
     /* 192423 */     // GIR_Coverage, 1400,
     /* 192423 */     GIR_EraseRootFromParent_Done,
     /* 192424 */   // Label 3562: @192424
     /* 192424 */   GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(192469), // Rule ID 1401 //
     /* 192429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 192437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 192440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 192446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192454 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192458 */     // (intrinsic_wo_chain:{ *:[v4i32] } 681:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 192458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i32),
     /* 192461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192465 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192467 */     GIR_RootConstrainSelectedInstOperands,
     /* 192468 */     // GIR_Coverage, 1401,
     /* 192468 */     GIR_EraseRootFromParent_Done,
     /* 192469 */   // Label 3563: @192469
     /* 192469 */   GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(192514), // Rule ID 1408 //
     /* 192474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 192485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 192488 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 192491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192495 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192499 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192503 */     // (intrinsic_wo_chain:{ *:[v8i8] } 684:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 192503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i8),
     /* 192506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192508 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192510 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192512 */     GIR_RootConstrainSelectedInstOperands,
     /* 192513 */     // GIR_Coverage, 1408,
     /* 192513 */     GIR_EraseRootFromParent_Done,
     /* 192514 */   // Label 3564: @192514
     /* 192514 */   GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(192559), // Rule ID 1409 //
     /* 192519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 192530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 192533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 192536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192548 */     // (intrinsic_wo_chain:{ *:[v16i8] } 684:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 192548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv16i8),
     /* 192551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192557 */     GIR_RootConstrainSelectedInstOperands,
     /* 192558 */     // GIR_Coverage, 1409,
     /* 192558 */     GIR_EraseRootFromParent_Done,
     /* 192559 */   // Label 3565: @192559
     /* 192559 */   GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(192604), // Rule ID 1410 //
     /* 192564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192567 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192572 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 192575 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192578 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 192581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192585 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192589 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192593 */     // (intrinsic_wo_chain:{ *:[v4i16] } 684:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 192593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i16),
     /* 192596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192602 */     GIR_RootConstrainSelectedInstOperands,
     /* 192603 */     // GIR_Coverage, 1410,
     /* 192603 */     GIR_EraseRootFromParent_Done,
     /* 192604 */   // Label 3566: @192604
     /* 192604 */   GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(192649), // Rule ID 1411 //
     /* 192609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 192620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 192626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192630 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192634 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192638 */     // (intrinsic_wo_chain:{ *:[v8i16] } 684:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 192638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i16),
     /* 192641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192645 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192647 */     GIR_RootConstrainSelectedInstOperands,
     /* 192648 */     // GIR_Coverage, 1411,
     /* 192648 */     GIR_EraseRootFromParent_Done,
     /* 192649 */   // Label 3567: @192649
     /* 192649 */   GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(192694), // Rule ID 1412 //
     /* 192654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 192665 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192668 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 192671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192675 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192679 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192683 */     // (intrinsic_wo_chain:{ *:[v2i32] } 684:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 192683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 192686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192688 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192690 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192692 */     GIR_RootConstrainSelectedInstOperands,
     /* 192693 */     // GIR_Coverage, 1412,
     /* 192693 */     GIR_EraseRootFromParent_Done,
     /* 192694 */   // Label 3568: @192694
     /* 192694 */   GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(192739), // Rule ID 1413 //
     /* 192699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 192707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 192710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 192716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192724 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192728 */     // (intrinsic_wo_chain:{ *:[v4i32] } 684:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 192728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i32),
     /* 192731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192733 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192735 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192737 */     GIR_RootConstrainSelectedInstOperands,
     /* 192738 */     // GIR_Coverage, 1413,
     /* 192738 */     GIR_EraseRootFromParent_Done,
     /* 192739 */   // Label 3569: @192739
     /* 192739 */   GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(192784), // Rule ID 1427 //
     /* 192744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 192752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 192755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 192761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192765 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192769 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192773 */     // (intrinsic_wo_chain:{ *:[v4i16] } 690:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 192773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16),
     /* 192776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192778 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192780 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192782 */     GIR_RootConstrainSelectedInstOperands,
     /* 192783 */     // GIR_Coverage, 1427,
     /* 192783 */     GIR_EraseRootFromParent_Done,
     /* 192784 */   // Label 3570: @192784
     /* 192784 */   GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(192829), // Rule ID 1428 //
     /* 192789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 192797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 192800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 192806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192814 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192818 */     // (intrinsic_wo_chain:{ *:[v8i16] } 690:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 192818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16),
     /* 192821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192823 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192825 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192827 */     GIR_RootConstrainSelectedInstOperands,
     /* 192828 */     // GIR_Coverage, 1428,
     /* 192828 */     GIR_EraseRootFromParent_Done,
     /* 192829 */   // Label 3571: @192829
     /* 192829 */   GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(192874), // Rule ID 1429 //
     /* 192834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 192842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 192845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 192851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192855 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192859 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192863 */     // (intrinsic_wo_chain:{ *:[v2i32] } 690:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 192863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32),
     /* 192866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192870 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192872 */     GIR_RootConstrainSelectedInstOperands,
     /* 192873 */     // GIR_Coverage, 1429,
     /* 192873 */     GIR_EraseRootFromParent_Done,
     /* 192874 */   // Label 3572: @192874
     /* 192874 */   GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(192919), // Rule ID 1430 //
     /* 192879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 192887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 192890 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192893 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 192896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192904 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192908 */     // (intrinsic_wo_chain:{ *:[v4i32] } 690:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 192908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32),
     /* 192911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192913 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192915 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192917 */     GIR_RootConstrainSelectedInstOperands,
     /* 192918 */     // GIR_Coverage, 1430,
     /* 192918 */     GIR_EraseRootFromParent_Done,
     /* 192919 */   // Label 3573: @192919
     /* 192919 */   GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(192964), // Rule ID 1431 //
     /* 192924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192927 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 192932 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 192935 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192938 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 192941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192945 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192949 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192953 */     // (intrinsic_wo_chain:{ *:[v4i16] } 698:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 192953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16),
     /* 192956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192958 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192960 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 192962 */     GIR_RootConstrainSelectedInstOperands,
     /* 192963 */     // GIR_Coverage, 1431,
     /* 192963 */     GIR_EraseRootFromParent_Done,
     /* 192964 */   // Label 3574: @192964
     /* 192964 */   GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(193009), // Rule ID 1432 //
     /* 192969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 192972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 192977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 192980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 192986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192994 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192998 */     // (intrinsic_wo_chain:{ *:[v8i16] } 698:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 192998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16),
     /* 193001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193007 */     GIR_RootConstrainSelectedInstOperands,
     /* 193008 */     // GIR_Coverage, 1432,
     /* 193008 */     GIR_EraseRootFromParent_Done,
     /* 193009 */   // Label 3575: @193009
     /* 193009 */   GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(193054), // Rule ID 1433 //
     /* 193014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 193022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 193025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 193031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193039 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193043 */     // (intrinsic_wo_chain:{ *:[v2i32] } 698:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 193043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32),
     /* 193046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193050 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193052 */     GIR_RootConstrainSelectedInstOperands,
     /* 193053 */     // GIR_Coverage, 1433,
     /* 193053 */     GIR_EraseRootFromParent_Done,
     /* 193054 */   // Label 3576: @193054
     /* 193054 */   GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(193099), // Rule ID 1434 //
     /* 193059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 193067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 193070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 193076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193084 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193088 */     // (intrinsic_wo_chain:{ *:[v4i32] } 698:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 193088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32),
     /* 193091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193097 */     GIR_RootConstrainSelectedInstOperands,
     /* 193098 */     // GIR_Coverage, 1434,
     /* 193098 */     GIR_EraseRootFromParent_Done,
     /* 193099 */   // Label 3577: @193099
     /* 193099 */   GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(193144), // Rule ID 1435 //
     /* 193104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 193115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 193118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 193121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193125 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193129 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193133 */     // (intrinsic_wo_chain:{ *:[v8i8] } 701:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 193133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i8),
     /* 193136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193138 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193140 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193142 */     GIR_RootConstrainSelectedInstOperands,
     /* 193143 */     // GIR_Coverage, 1435,
     /* 193143 */     GIR_EraseRootFromParent_Done,
     /* 193144 */   // Label 3578: @193144
     /* 193144 */   GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(193189), // Rule ID 1436 //
     /* 193149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 193160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 193166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193170 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193174 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193178 */     // (intrinsic_wo_chain:{ *:[v16i8] } 701:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 193178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv16i8),
     /* 193181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193185 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193187 */     GIR_RootConstrainSelectedInstOperands,
     /* 193188 */     // GIR_Coverage, 1436,
     /* 193188 */     GIR_EraseRootFromParent_Done,
     /* 193189 */   // Label 3579: @193189
     /* 193189 */   GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(193234), // Rule ID 1437 //
     /* 193194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 193205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 193211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193215 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193219 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193223 */     // (intrinsic_wo_chain:{ *:[v4i16] } 701:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 193223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i16),
     /* 193226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193232 */     GIR_RootConstrainSelectedInstOperands,
     /* 193233 */     // GIR_Coverage, 1437,
     /* 193233 */     GIR_EraseRootFromParent_Done,
     /* 193234 */   // Label 3580: @193234
     /* 193234 */   GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(193279), // Rule ID 1438 //
     /* 193239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 193250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193253 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 193256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193264 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193268 */     // (intrinsic_wo_chain:{ *:[v8i16] } 701:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 193268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i16),
     /* 193271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193273 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193275 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193277 */     GIR_RootConstrainSelectedInstOperands,
     /* 193278 */     // GIR_Coverage, 1438,
     /* 193278 */     GIR_EraseRootFromParent_Done,
     /* 193279 */   // Label 3581: @193279
     /* 193279 */   GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(193324), // Rule ID 1439 //
     /* 193284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 193295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 193301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193305 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193309 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193313 */     // (intrinsic_wo_chain:{ *:[v2i32] } 701:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 193313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i32),
     /* 193316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193320 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193322 */     GIR_RootConstrainSelectedInstOperands,
     /* 193323 */     // GIR_Coverage, 1439,
     /* 193323 */     GIR_EraseRootFromParent_Done,
     /* 193324 */   // Label 3582: @193324
     /* 193324 */   GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(193369), // Rule ID 1440 //
     /* 193329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 193340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 193346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193350 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193354 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193358 */     // (intrinsic_wo_chain:{ *:[v4i32] } 701:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 193358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i32),
     /* 193361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193367 */     GIR_RootConstrainSelectedInstOperands,
     /* 193368 */     // GIR_Coverage, 1440,
     /* 193368 */     GIR_EraseRootFromParent_Done,
     /* 193369 */   // Label 3583: @193369
     /* 193369 */   GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(193414), // Rule ID 1441 //
     /* 193374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 193382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 193385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 193388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 193391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193399 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193403 */     // (intrinsic_wo_chain:{ *:[v2i64] } 701:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 193403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i64),
     /* 193406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193412 */     GIR_RootConstrainSelectedInstOperands,
     /* 193413 */     // GIR_Coverage, 1441,
     /* 193413 */     GIR_EraseRootFromParent_Done,
     /* 193414 */   // Label 3584: @193414
     /* 193414 */   GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(193459), // Rule ID 1442 //
     /* 193419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193422 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193427 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 193430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 193433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 193436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193444 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193448 */     // (intrinsic_wo_chain:{ *:[v8i8] } 704:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 193448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i8),
     /* 193451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193455 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193457 */     GIR_RootConstrainSelectedInstOperands,
     /* 193458 */     // GIR_Coverage, 1442,
     /* 193458 */     GIR_EraseRootFromParent_Done,
     /* 193459 */   // Label 3585: @193459
     /* 193459 */   GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(193504), // Rule ID 1443 //
     /* 193464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 193475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193478 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 193481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193485 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193489 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193493 */     // (intrinsic_wo_chain:{ *:[v16i8] } 704:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 193493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv16i8),
     /* 193496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193500 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193502 */     GIR_RootConstrainSelectedInstOperands,
     /* 193503 */     // GIR_Coverage, 1443,
     /* 193503 */     GIR_EraseRootFromParent_Done,
     /* 193504 */   // Label 3586: @193504
     /* 193504 */   GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(193549), // Rule ID 1444 //
     /* 193509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 193520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 193526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193534 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193538 */     // (intrinsic_wo_chain:{ *:[v4i16] } 704:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 193538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i16),
     /* 193541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193543 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193545 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193547 */     GIR_RootConstrainSelectedInstOperands,
     /* 193548 */     // GIR_Coverage, 1444,
     /* 193548 */     GIR_EraseRootFromParent_Done,
     /* 193549 */   // Label 3587: @193549
     /* 193549 */   GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(193594), // Rule ID 1445 //
     /* 193554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193557 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193562 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 193565 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193568 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 193571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193575 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193579 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193583 */     // (intrinsic_wo_chain:{ *:[v8i16] } 704:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 193583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i16),
     /* 193586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193590 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193592 */     GIR_RootConstrainSelectedInstOperands,
     /* 193593 */     // GIR_Coverage, 1445,
     /* 193593 */     GIR_EraseRootFromParent_Done,
     /* 193594 */   // Label 3588: @193594
     /* 193594 */   GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(193639), // Rule ID 1446 //
     /* 193599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 193610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 193616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193624 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193628 */     // (intrinsic_wo_chain:{ *:[v2i32] } 704:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 193628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i32),
     /* 193631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193635 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193637 */     GIR_RootConstrainSelectedInstOperands,
     /* 193638 */     // GIR_Coverage, 1446,
     /* 193638 */     GIR_EraseRootFromParent_Done,
     /* 193639 */   // Label 3589: @193639
     /* 193639 */   GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(193684), // Rule ID 1447 //
     /* 193644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193647 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193652 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 193655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 193661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193673 */     // (intrinsic_wo_chain:{ *:[v4i32] } 704:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 193673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i32),
     /* 193676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193682 */     GIR_RootConstrainSelectedInstOperands,
     /* 193683 */     // GIR_Coverage, 1447,
     /* 193683 */     GIR_EraseRootFromParent_Done,
     /* 193684 */   // Label 3590: @193684
     /* 193684 */   GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(193729), // Rule ID 1448 //
     /* 193689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 193697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 193700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 193703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 193706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193710 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193714 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193718 */     // (intrinsic_wo_chain:{ *:[v2i64] } 704:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 193718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i64),
     /* 193721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193727 */     GIR_RootConstrainSelectedInstOperands,
     /* 193728 */     // GIR_Coverage, 1448,
     /* 193728 */     GIR_EraseRootFromParent_Done,
     /* 193729 */   // Label 3591: @193729
     /* 193729 */   GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(193774), // Rule ID 1462 //
     /* 193734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 193745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 193748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 193751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193755 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193759 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193763 */     // (intrinsic_wo_chain:{ *:[v8i8] } 712:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 193763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i8),
     /* 193766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193770 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193772 */     GIR_RootConstrainSelectedInstOperands,
     /* 193773 */     // GIR_Coverage, 1462,
     /* 193773 */     GIR_EraseRootFromParent_Done,
     /* 193774 */   // Label 3592: @193774
     /* 193774 */   GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(193819), // Rule ID 1463 //
     /* 193779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 193790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 193796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193804 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193808 */     // (intrinsic_wo_chain:{ *:[v16i8] } 712:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 193808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv16i8),
     /* 193811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193815 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193817 */     GIR_RootConstrainSelectedInstOperands,
     /* 193818 */     // GIR_Coverage, 1463,
     /* 193818 */     GIR_EraseRootFromParent_Done,
     /* 193819 */   // Label 3593: @193819
     /* 193819 */   GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(193864), // Rule ID 1464 //
     /* 193824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 193835 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 193841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193845 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193849 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193853 */     // (intrinsic_wo_chain:{ *:[v4i16] } 712:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 193853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i16),
     /* 193856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193862 */     GIR_RootConstrainSelectedInstOperands,
     /* 193863 */     // GIR_Coverage, 1464,
     /* 193863 */     GIR_EraseRootFromParent_Done,
     /* 193864 */   // Label 3594: @193864
     /* 193864 */   GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(193909), // Rule ID 1465 //
     /* 193869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 193880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 193886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193894 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193898 */     // (intrinsic_wo_chain:{ *:[v8i16] } 712:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 193898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i16),
     /* 193901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193907 */     GIR_RootConstrainSelectedInstOperands,
     /* 193908 */     // GIR_Coverage, 1465,
     /* 193908 */     GIR_EraseRootFromParent_Done,
     /* 193909 */   // Label 3595: @193909
     /* 193909 */   GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(193954), // Rule ID 1466 //
     /* 193914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 193925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 193931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193935 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193939 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193943 */     // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 193943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i32),
     /* 193946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193948 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193950 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193952 */     GIR_RootConstrainSelectedInstOperands,
     /* 193953 */     // GIR_Coverage, 1466,
     /* 193953 */     GIR_EraseRootFromParent_Done,
     /* 193954 */   // Label 3596: @193954
     /* 193954 */   GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(193999), // Rule ID 1467 //
     /* 193959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 193962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 193967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 193970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 193976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193988 */     // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 193988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i32),
     /* 193991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 193997 */     GIR_RootConstrainSelectedInstOperands,
     /* 193998 */     // GIR_Coverage, 1467,
     /* 193998 */     GIR_EraseRootFromParent_Done,
     /* 193999 */   // Label 3597: @193999
     /* 193999 */   GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(194044), // Rule ID 1468 //
     /* 194004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 194012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 194015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 194018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 194021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194025 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194029 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194033 */     // (intrinsic_wo_chain:{ *:[v2i64] } 712:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 194033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i64),
     /* 194036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194040 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194042 */     GIR_RootConstrainSelectedInstOperands,
     /* 194043 */     // GIR_Coverage, 1468,
     /* 194043 */     GIR_EraseRootFromParent_Done,
     /* 194044 */   // Label 3598: @194044
     /* 194044 */   GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(194089), // Rule ID 1469 //
     /* 194049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 194060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 194063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 194066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194074 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194078 */     // (intrinsic_wo_chain:{ *:[v8i8] } 713:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 194078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i8),
     /* 194081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194083 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194085 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194087 */     GIR_RootConstrainSelectedInstOperands,
     /* 194088 */     // GIR_Coverage, 1469,
     /* 194088 */     GIR_EraseRootFromParent_Done,
     /* 194089 */   // Label 3599: @194089
     /* 194089 */   GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(194134), // Rule ID 1470 //
     /* 194094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 194105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 194108 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 194111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194115 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194119 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194123 */     // (intrinsic_wo_chain:{ *:[v16i8] } 713:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 194123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv16i8),
     /* 194126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194130 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194132 */     GIR_RootConstrainSelectedInstOperands,
     /* 194133 */     // GIR_Coverage, 1470,
     /* 194133 */     GIR_EraseRootFromParent_Done,
     /* 194134 */   // Label 3600: @194134
     /* 194134 */   GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(194179), // Rule ID 1471 //
     /* 194139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 194150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 194153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 194156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194160 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194164 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194168 */     // (intrinsic_wo_chain:{ *:[v4i16] } 713:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 194168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i16),
     /* 194171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194175 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194177 */     GIR_RootConstrainSelectedInstOperands,
     /* 194178 */     // GIR_Coverage, 1471,
     /* 194178 */     GIR_EraseRootFromParent_Done,
     /* 194179 */   // Label 3601: @194179
     /* 194179 */   GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(194224), // Rule ID 1472 //
     /* 194184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 194195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 194198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 194201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194205 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194209 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194213 */     // (intrinsic_wo_chain:{ *:[v8i16] } 713:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 194213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i16),
     /* 194216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194220 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194222 */     GIR_RootConstrainSelectedInstOperands,
     /* 194223 */     // GIR_Coverage, 1472,
     /* 194223 */     GIR_EraseRootFromParent_Done,
     /* 194224 */   // Label 3602: @194224
     /* 194224 */   GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(194269), // Rule ID 1473 //
     /* 194229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 194240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 194243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 194246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194254 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194258 */     // (intrinsic_wo_chain:{ *:[v2i32] } 713:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 194258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i32),
     /* 194261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194265 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194267 */     GIR_RootConstrainSelectedInstOperands,
     /* 194268 */     // GIR_Coverage, 1473,
     /* 194268 */     GIR_EraseRootFromParent_Done,
     /* 194269 */   // Label 3603: @194269
     /* 194269 */   GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(194314), // Rule ID 1474 //
     /* 194274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194277 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194282 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 194285 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 194288 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 194291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194299 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194303 */     // (intrinsic_wo_chain:{ *:[v4i32] } 713:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 194303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i32),
     /* 194306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194312 */     GIR_RootConstrainSelectedInstOperands,
     /* 194313 */     // GIR_Coverage, 1474,
     /* 194313 */     GIR_EraseRootFromParent_Done,
     /* 194314 */   // Label 3604: @194314
     /* 194314 */   GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(194359), // Rule ID 1475 //
     /* 194319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194322 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 194327 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 194330 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 194333 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 194336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194340 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194344 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194348 */     // (intrinsic_wo_chain:{ *:[v2i64] } 713:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 194348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i64),
     /* 194351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194353 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194355 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194357 */     GIR_RootConstrainSelectedInstOperands,
     /* 194358 */     // GIR_Coverage, 1475,
     /* 194358 */     GIR_EraseRootFromParent_Done,
     /* 194359 */   // Label 3605: @194359
     /* 194359 */   GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(194404), // Rule ID 1496 //
     /* 194364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 194375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 194378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 194381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194389 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194393 */     // (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 194393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i8),
     /* 194396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194400 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194402 */     GIR_RootConstrainSelectedInstOperands,
     /* 194403 */     // GIR_Coverage, 1496,
     /* 194403 */     GIR_EraseRootFromParent_Done,
     /* 194404 */   // Label 3606: @194404
     /* 194404 */   GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(194449), // Rule ID 1498 //
     /* 194409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 194420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 194423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 194426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194434 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194438 */     // (intrinsic_wo_chain:{ *:[v16i8] } 734:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 194438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv16i8),
     /* 194441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194445 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194447 */     GIR_RootConstrainSelectedInstOperands,
     /* 194448 */     // GIR_Coverage, 1498,
     /* 194448 */     GIR_EraseRootFromParent_Done,
     /* 194449 */   // Label 3607: @194449
     /* 194449 */   GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(194494), // Rule ID 1500 //
     /* 194454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194462 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 194465 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 194468 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 194471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194479 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194483 */     // (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 194483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i16),
     /* 194486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194490 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194492 */     GIR_RootConstrainSelectedInstOperands,
     /* 194493 */     // GIR_Coverage, 1500,
     /* 194493 */     GIR_EraseRootFromParent_Done,
     /* 194494 */   // Label 3608: @194494
     /* 194494 */   GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(194539), // Rule ID 1502 //
     /* 194499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 194510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 194513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 194516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194524 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194528 */     // (intrinsic_wo_chain:{ *:[v8i16] } 734:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 194528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i16),
     /* 194531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194537 */     GIR_RootConstrainSelectedInstOperands,
     /* 194538 */     // GIR_Coverage, 1502,
     /* 194538 */     GIR_EraseRootFromParent_Done,
     /* 194539 */   // Label 3609: @194539
     /* 194539 */   GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(194584), // Rule ID 1504 //
     /* 194544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 194555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 194558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 194561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194565 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194569 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194573 */     // (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 194573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv2i32),
     /* 194576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194580 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194582 */     GIR_RootConstrainSelectedInstOperands,
     /* 194583 */     // GIR_Coverage, 1504,
     /* 194583 */     GIR_EraseRootFromParent_Done,
     /* 194584 */   // Label 3610: @194584
     /* 194584 */   GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(194629), // Rule ID 1506 //
     /* 194589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 194597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 194600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 194603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 194606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194614 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194618 */     // (intrinsic_wo_chain:{ *:[v4i32] } 734:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 194618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i32),
     /* 194621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194627 */     GIR_RootConstrainSelectedInstOperands,
     /* 194628 */     // GIR_Coverage, 1506,
     /* 194628 */     GIR_EraseRootFromParent_Done,
     /* 194629 */   // Label 3611: @194629
     /* 194629 */   GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(194674), // Rule ID 1513 //
     /* 194634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 194645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 194648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 194651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194659 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194663 */     // (intrinsic_wo_chain:{ *:[v8i8] } 740:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 194663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i8),
     /* 194666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194668 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194670 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194672 */     GIR_RootConstrainSelectedInstOperands,
     /* 194673 */     // GIR_Coverage, 1513,
     /* 194673 */     GIR_EraseRootFromParent_Done,
     /* 194674 */   // Label 3612: @194674
     /* 194674 */   GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(194719), // Rule ID 1514 //
     /* 194679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 194690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 194693 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 194696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194700 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194704 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194708 */     // (intrinsic_wo_chain:{ *:[v16i8] } 740:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 194708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv16i8),
     /* 194711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194715 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194717 */     GIR_RootConstrainSelectedInstOperands,
     /* 194718 */     // GIR_Coverage, 1514,
     /* 194718 */     GIR_EraseRootFromParent_Done,
     /* 194719 */   // Label 3613: @194719
     /* 194719 */   GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(194764), // Rule ID 1515 //
     /* 194724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 194735 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 194738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 194741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194749 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194753 */     // (intrinsic_wo_chain:{ *:[v4i16] } 740:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 194753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i16),
     /* 194756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194762 */     GIR_RootConstrainSelectedInstOperands,
     /* 194763 */     // GIR_Coverage, 1515,
     /* 194763 */     GIR_EraseRootFromParent_Done,
     /* 194764 */   // Label 3614: @194764
     /* 194764 */   GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(194809), // Rule ID 1516 //
     /* 194769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 194780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 194783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 194786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194790 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194794 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194798 */     // (intrinsic_wo_chain:{ *:[v8i16] } 740:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 194798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i16),
     /* 194801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194803 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194805 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194807 */     GIR_RootConstrainSelectedInstOperands,
     /* 194808 */     // GIR_Coverage, 1516,
     /* 194808 */     GIR_EraseRootFromParent_Done,
     /* 194809 */   // Label 3615: @194809
     /* 194809 */   GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(194854), // Rule ID 1517 //
     /* 194814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 194825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 194828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 194831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194835 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194839 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194843 */     // (intrinsic_wo_chain:{ *:[v2i32] } 740:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 194843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv2i32),
     /* 194846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194848 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194850 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194852 */     GIR_RootConstrainSelectedInstOperands,
     /* 194853 */     // GIR_Coverage, 1517,
     /* 194853 */     GIR_EraseRootFromParent_Done,
     /* 194854 */   // Label 3616: @194854
     /* 194854 */   GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(194899), // Rule ID 1518 //
     /* 194859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 194867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 194870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 194873 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 194876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194884 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194888 */     // (intrinsic_wo_chain:{ *:[v4i32] } 740:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 194888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i32),
     /* 194891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194893 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194895 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194897 */     GIR_RootConstrainSelectedInstOperands,
     /* 194898 */     // GIR_Coverage, 1518,
     /* 194898 */     GIR_EraseRootFromParent_Done,
     /* 194899 */   // Label 3617: @194899
     /* 194899 */   GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(194944), // Rule ID 1519 //
     /* 194904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 194912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 194915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 194918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 194921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194929 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194933 */     // (intrinsic_wo_chain:{ *:[v8i8] } 742:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 194933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i8),
     /* 194936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194942 */     GIR_RootConstrainSelectedInstOperands,
     /* 194943 */     // GIR_Coverage, 1519,
     /* 194943 */     GIR_EraseRootFromParent_Done,
     /* 194944 */   // Label 3618: @194944
     /* 194944 */   GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(194989), // Rule ID 1520 //
     /* 194949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 194957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 194960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 194963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 194966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194970 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194974 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194978 */     // (intrinsic_wo_chain:{ *:[v16i8] } 742:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 194978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv16i8),
     /* 194981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194985 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 194987 */     GIR_RootConstrainSelectedInstOperands,
     /* 194988 */     // GIR_Coverage, 1520,
     /* 194988 */     GIR_EraseRootFromParent_Done,
     /* 194989 */   // Label 3619: @194989
     /* 194989 */   GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(195034), // Rule ID 1521 //
     /* 194994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 194997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 195002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 195005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 195008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 195011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195019 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195023 */     // (intrinsic_wo_chain:{ *:[v4i16] } 742:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 195023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i16),
     /* 195026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195032 */     GIR_RootConstrainSelectedInstOperands,
     /* 195033 */     // GIR_Coverage, 1521,
     /* 195033 */     GIR_EraseRootFromParent_Done,
     /* 195034 */   // Label 3620: @195034
     /* 195034 */   GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(195079), // Rule ID 1522 //
     /* 195039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 195047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 195050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 195053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 195056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195064 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195068 */     // (intrinsic_wo_chain:{ *:[v8i16] } 742:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 195068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i16),
     /* 195071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195075 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195077 */     GIR_RootConstrainSelectedInstOperands,
     /* 195078 */     // GIR_Coverage, 1522,
     /* 195078 */     GIR_EraseRootFromParent_Done,
     /* 195079 */   // Label 3621: @195079
     /* 195079 */   GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(195124), // Rule ID 1523 //
     /* 195084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195087 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 195092 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 195095 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 195098 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 195101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195105 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195109 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195113 */     // (intrinsic_wo_chain:{ *:[v2i32] } 742:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 195113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 195116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195118 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195120 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195122 */     GIR_RootConstrainSelectedInstOperands,
     /* 195123 */     // GIR_Coverage, 1523,
     /* 195123 */     GIR_EraseRootFromParent_Done,
     /* 195124 */   // Label 3622: @195124
     /* 195124 */   GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(195169), // Rule ID 1524 //
     /* 195129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 195137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 195140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 195143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 195146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195158 */     // (intrinsic_wo_chain:{ *:[v4i32] } 742:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 195158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i32),
     /* 195161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195167 */     GIR_RootConstrainSelectedInstOperands,
     /* 195168 */     // GIR_Coverage, 1524,
     /* 195168 */     GIR_EraseRootFromParent_Done,
     /* 195169 */   // Label 3623: @195169
     /* 195169 */   GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(195214), // Rule ID 1531 //
     /* 195174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 195185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 195188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 195191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195199 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195203 */     // (intrinsic_wo_chain:{ *:[v8i8] } 745:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 195203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i8),
     /* 195206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195210 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195212 */     GIR_RootConstrainSelectedInstOperands,
     /* 195213 */     // GIR_Coverage, 1531,
     /* 195213 */     GIR_EraseRootFromParent_Done,
     /* 195214 */   // Label 3624: @195214
     /* 195214 */   GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(195259), // Rule ID 1532 //
     /* 195219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 195230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 195233 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 195236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195244 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195248 */     // (intrinsic_wo_chain:{ *:[v16i8] } 745:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 195248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv16i8),
     /* 195251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195257 */     GIR_RootConstrainSelectedInstOperands,
     /* 195258 */     // GIR_Coverage, 1532,
     /* 195258 */     GIR_EraseRootFromParent_Done,
     /* 195259 */   // Label 3625: @195259
     /* 195259 */   GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(195304), // Rule ID 1533 //
     /* 195264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 195275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 195278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 195281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195289 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195293 */     // (intrinsic_wo_chain:{ *:[v4i16] } 745:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 195293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i16),
     /* 195296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195298 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195300 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195302 */     GIR_RootConstrainSelectedInstOperands,
     /* 195303 */     // GIR_Coverage, 1533,
     /* 195303 */     GIR_EraseRootFromParent_Done,
     /* 195304 */   // Label 3626: @195304
     /* 195304 */   GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(195349), // Rule ID 1534 //
     /* 195309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 195320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 195323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 195326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195334 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195338 */     // (intrinsic_wo_chain:{ *:[v8i16] } 745:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 195338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i16),
     /* 195341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195347 */     GIR_RootConstrainSelectedInstOperands,
     /* 195348 */     // GIR_Coverage, 1534,
     /* 195348 */     GIR_EraseRootFromParent_Done,
     /* 195349 */   // Label 3627: @195349
     /* 195349 */   GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(195394), // Rule ID 1535 //
     /* 195354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 195365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 195368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 195371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195383 */     // (intrinsic_wo_chain:{ *:[v2i32] } 745:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 195383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 195386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195392 */     GIR_RootConstrainSelectedInstOperands,
     /* 195393 */     // GIR_Coverage, 1535,
     /* 195393 */     GIR_EraseRootFromParent_Done,
     /* 195394 */   // Label 3628: @195394
     /* 195394 */   GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(195439), // Rule ID 1536 //
     /* 195399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 195407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 195410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 195413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 195416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195420 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195424 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195428 */     // (intrinsic_wo_chain:{ *:[v4i32] } 745:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 195428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i32),
     /* 195431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195433 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195435 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195437 */     GIR_RootConstrainSelectedInstOperands,
     /* 195438 */     // GIR_Coverage, 1536,
     /* 195438 */     GIR_EraseRootFromParent_Done,
     /* 195439 */   // Label 3629: @195439
     /* 195439 */   GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(195484), // Rule ID 1550 //
     /* 195444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 195455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 195458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 195461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195469 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195473 */     // (intrinsic_wo_chain:{ *:[v8i8] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 195473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i8),
     /* 195476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195480 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195482 */     GIR_RootConstrainSelectedInstOperands,
     /* 195483 */     // GIR_Coverage, 1550,
     /* 195483 */     GIR_EraseRootFromParent_Done,
     /* 195484 */   // Label 3630: @195484
     /* 195484 */   GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(195529), // Rule ID 1551 //
     /* 195489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 195500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 195503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 195506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195514 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195518 */     // (intrinsic_wo_chain:{ *:[v16i8] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 195518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv16i8),
     /* 195521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195523 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195525 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195527 */     GIR_RootConstrainSelectedInstOperands,
     /* 195528 */     // GIR_Coverage, 1551,
     /* 195528 */     GIR_EraseRootFromParent_Done,
     /* 195529 */   // Label 3631: @195529
     /* 195529 */   GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(195574), // Rule ID 1552 //
     /* 195534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 195545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 195548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 195551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195555 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195559 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195563 */     // (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 195563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i16),
     /* 195566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195572 */     GIR_RootConstrainSelectedInstOperands,
     /* 195573 */     // GIR_Coverage, 1552,
     /* 195573 */     GIR_EraseRootFromParent_Done,
     /* 195574 */   // Label 3632: @195574
     /* 195574 */   GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(195619), // Rule ID 1553 //
     /* 195579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 195590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 195593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 195596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195600 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195604 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195608 */     // (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 195608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i16),
     /* 195611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195615 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195617 */     GIR_RootConstrainSelectedInstOperands,
     /* 195618 */     // GIR_Coverage, 1553,
     /* 195618 */     GIR_EraseRootFromParent_Done,
     /* 195619 */   // Label 3633: @195619
     /* 195619 */   GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(195664), // Rule ID 1554 //
     /* 195624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 195635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 195638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 195641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195649 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195653 */     // (intrinsic_wo_chain:{ *:[v2i32] } 750:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 195653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i32),
     /* 195656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195662 */     GIR_RootConstrainSelectedInstOperands,
     /* 195663 */     // GIR_Coverage, 1554,
     /* 195663 */     GIR_EraseRootFromParent_Done,
     /* 195664 */   // Label 3634: @195664
     /* 195664 */   GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(195709), // Rule ID 1555 //
     /* 195669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 195680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 195683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 195686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195694 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195698 */     // (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 195698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i32),
     /* 195701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195707 */     GIR_RootConstrainSelectedInstOperands,
     /* 195708 */     // GIR_Coverage, 1555,
     /* 195708 */     GIR_EraseRootFromParent_Done,
     /* 195709 */   // Label 3635: @195709
     /* 195709 */   GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(195754), // Rule ID 1556 //
     /* 195714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 195722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 195725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 195728 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 195731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195739 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195743 */     // (intrinsic_wo_chain:{ *:[v2i64] } 750:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 195743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i64),
     /* 195746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195748 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195750 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195752 */     GIR_RootConstrainSelectedInstOperands,
     /* 195753 */     // GIR_Coverage, 1556,
     /* 195753 */     GIR_EraseRootFromParent_Done,
     /* 195754 */   // Label 3636: @195754
     /* 195754 */   GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(195799), // Rule ID 1557 //
     /* 195759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 195770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 195773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 195776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195784 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195788 */     // (intrinsic_wo_chain:{ *:[v8i8] } 752:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 195788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i8),
     /* 195791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195797 */     GIR_RootConstrainSelectedInstOperands,
     /* 195798 */     // GIR_Coverage, 1557,
     /* 195798 */     GIR_EraseRootFromParent_Done,
     /* 195799 */   // Label 3637: @195799
     /* 195799 */   GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(195844), // Rule ID 1558 //
     /* 195804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 195815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 195818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 195821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195825 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195829 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195833 */     // (intrinsic_wo_chain:{ *:[v16i8] } 752:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 195833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv16i8),
     /* 195836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195842 */     GIR_RootConstrainSelectedInstOperands,
     /* 195843 */     // GIR_Coverage, 1558,
     /* 195843 */     GIR_EraseRootFromParent_Done,
     /* 195844 */   // Label 3638: @195844
     /* 195844 */   GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(195889), // Rule ID 1559 //
     /* 195849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 195860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 195863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 195866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195878 */     // (intrinsic_wo_chain:{ *:[v4i16] } 752:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 195878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i16),
     /* 195881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195887 */     GIR_RootConstrainSelectedInstOperands,
     /* 195888 */     // GIR_Coverage, 1559,
     /* 195888 */     GIR_EraseRootFromParent_Done,
     /* 195889 */   // Label 3639: @195889
     /* 195889 */   GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(195934), // Rule ID 1560 //
     /* 195894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 195905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 195908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 195911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195919 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195923 */     // (intrinsic_wo_chain:{ *:[v8i16] } 752:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 195923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i16),
     /* 195926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195930 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195932 */     GIR_RootConstrainSelectedInstOperands,
     /* 195933 */     // GIR_Coverage, 1560,
     /* 195933 */     GIR_EraseRootFromParent_Done,
     /* 195934 */   // Label 3640: @195934
     /* 195934 */   GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(195979), // Rule ID 1561 //
     /* 195939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195942 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195947 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 195950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 195953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 195956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195960 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195964 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195968 */     // (intrinsic_wo_chain:{ *:[v2i32] } 752:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 195968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i32),
     /* 195971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 195977 */     GIR_RootConstrainSelectedInstOperands,
     /* 195978 */     // GIR_Coverage, 1561,
     /* 195978 */     GIR_EraseRootFromParent_Done,
     /* 195979 */   // Label 3641: @195979
     /* 195979 */   GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(196024), // Rule ID 1562 //
     /* 195984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 195987 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 195992 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 195995 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 195998 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 196001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196009 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196013 */     // (intrinsic_wo_chain:{ *:[v4i32] } 752:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 196013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i32),
     /* 196016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196022 */     GIR_RootConstrainSelectedInstOperands,
     /* 196023 */     // GIR_Coverage, 1562,
     /* 196023 */     GIR_EraseRootFromParent_Done,
     /* 196024 */   // Label 3642: @196024
     /* 196024 */   GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(196069), // Rule ID 1563 //
     /* 196029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 196037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 196040 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 196043 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 196046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196054 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196058 */     // (intrinsic_wo_chain:{ *:[v2i64] } 752:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 196058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i64),
     /* 196061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196063 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196065 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196067 */     GIR_RootConstrainSelectedInstOperands,
     /* 196068 */     // GIR_Coverage, 1563,
     /* 196068 */     GIR_EraseRootFromParent_Done,
     /* 196069 */   // Label 3643: @196069
     /* 196069 */   GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(196114), // Rule ID 1577 //
     /* 196074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 196085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 196088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 196091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196099 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196103 */     // (intrinsic_wo_chain:{ *:[v8i8] } 758:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 196103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i8),
     /* 196106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196110 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196112 */     GIR_RootConstrainSelectedInstOperands,
     /* 196113 */     // GIR_Coverage, 1577,
     /* 196113 */     GIR_EraseRootFromParent_Done,
     /* 196114 */   // Label 3644: @196114
     /* 196114 */   GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(196159), // Rule ID 1578 //
     /* 196119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 196130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 196133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 196136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196144 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196148 */     // (intrinsic_wo_chain:{ *:[v16i8] } 758:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 196148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv16i8),
     /* 196151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196155 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196157 */     GIR_RootConstrainSelectedInstOperands,
     /* 196158 */     // GIR_Coverage, 1578,
     /* 196158 */     GIR_EraseRootFromParent_Done,
     /* 196159 */   // Label 3645: @196159
     /* 196159 */   GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(196204), // Rule ID 1579 //
     /* 196164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 196175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196189 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196193 */     // (intrinsic_wo_chain:{ *:[v4i16] } 758:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 196193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i16),
     /* 196196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196200 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196202 */     GIR_RootConstrainSelectedInstOperands,
     /* 196203 */     // GIR_Coverage, 1579,
     /* 196203 */     GIR_EraseRootFromParent_Done,
     /* 196204 */   // Label 3646: @196204
     /* 196204 */   GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(196249), // Rule ID 1580 //
     /* 196209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 196220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 196223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 196226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196230 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196234 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196238 */     // (intrinsic_wo_chain:{ *:[v8i16] } 758:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 196238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i16),
     /* 196241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196247 */     GIR_RootConstrainSelectedInstOperands,
     /* 196248 */     // GIR_Coverage, 1580,
     /* 196248 */     GIR_EraseRootFromParent_Done,
     /* 196249 */   // Label 3647: @196249
     /* 196249 */   GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(196294), // Rule ID 1581 //
     /* 196254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 196265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 196268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 196271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196279 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196283 */     // (intrinsic_wo_chain:{ *:[v2i32] } 758:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 196283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i32),
     /* 196286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196292 */     GIR_RootConstrainSelectedInstOperands,
     /* 196293 */     // GIR_Coverage, 1581,
     /* 196293 */     GIR_EraseRootFromParent_Done,
     /* 196294 */   // Label 3648: @196294
     /* 196294 */   GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(196339), // Rule ID 1582 //
     /* 196299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196307 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 196310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 196313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 196316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196324 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196328 */     // (intrinsic_wo_chain:{ *:[v4i32] } 758:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 196328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i32),
     /* 196331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196335 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196337 */     GIR_RootConstrainSelectedInstOperands,
     /* 196338 */     // GIR_Coverage, 1582,
     /* 196338 */     GIR_EraseRootFromParent_Done,
     /* 196339 */   // Label 3649: @196339
     /* 196339 */   GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(196384), // Rule ID 1583 //
     /* 196344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 196352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 196355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 196358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 196361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196369 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196373 */     // (intrinsic_wo_chain:{ *:[v2i64] } 758:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 196373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i64),
     /* 196376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196378 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196382 */     GIR_RootConstrainSelectedInstOperands,
     /* 196383 */     // GIR_Coverage, 1583,
     /* 196383 */     GIR_EraseRootFromParent_Done,
     /* 196384 */   // Label 3650: @196384
     /* 196384 */   GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(196429), // Rule ID 1584 //
     /* 196389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 196400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 196403 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 196406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196414 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196418 */     // (intrinsic_wo_chain:{ *:[v8i8] } 761:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 196418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i8),
     /* 196421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196427 */     GIR_RootConstrainSelectedInstOperands,
     /* 196428 */     // GIR_Coverage, 1584,
     /* 196428 */     GIR_EraseRootFromParent_Done,
     /* 196429 */   // Label 3651: @196429
     /* 196429 */   GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(196474), // Rule ID 1585 //
     /* 196434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 196445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 196448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 196451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196459 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196463 */     // (intrinsic_wo_chain:{ *:[v16i8] } 761:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 196463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv16i8),
     /* 196466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196470 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196472 */     GIR_RootConstrainSelectedInstOperands,
     /* 196473 */     // GIR_Coverage, 1585,
     /* 196473 */     GIR_EraseRootFromParent_Done,
     /* 196474 */   // Label 3652: @196474
     /* 196474 */   GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(196519), // Rule ID 1586 //
     /* 196479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 196490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196500 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196504 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196508 */     // (intrinsic_wo_chain:{ *:[v4i16] } 761:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 196508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i16),
     /* 196511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196513 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196515 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196517 */     GIR_RootConstrainSelectedInstOperands,
     /* 196518 */     // GIR_Coverage, 1586,
     /* 196518 */     GIR_EraseRootFromParent_Done,
     /* 196519 */   // Label 3653: @196519
     /* 196519 */   GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(196564), // Rule ID 1587 //
     /* 196524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 196535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 196538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 196541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196545 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196549 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196553 */     // (intrinsic_wo_chain:{ *:[v8i16] } 761:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 196553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i16),
     /* 196556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196562 */     GIR_RootConstrainSelectedInstOperands,
     /* 196563 */     // GIR_Coverage, 1587,
     /* 196563 */     GIR_EraseRootFromParent_Done,
     /* 196564 */   // Label 3654: @196564
     /* 196564 */   GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(196609), // Rule ID 1588 //
     /* 196569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 196580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 196583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 196586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196590 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196594 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196598 */     // (intrinsic_wo_chain:{ *:[v2i32] } 761:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 196598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i32),
     /* 196601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196607 */     GIR_RootConstrainSelectedInstOperands,
     /* 196608 */     // GIR_Coverage, 1588,
     /* 196608 */     GIR_EraseRootFromParent_Done,
     /* 196609 */   // Label 3655: @196609
     /* 196609 */   GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(196654), // Rule ID 1589 //
     /* 196614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 196625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 196628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 196631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196635 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196639 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196643 */     // (intrinsic_wo_chain:{ *:[v4i32] } 761:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 196643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i32),
     /* 196646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196652 */     GIR_RootConstrainSelectedInstOperands,
     /* 196653 */     // GIR_Coverage, 1589,
     /* 196653 */     GIR_EraseRootFromParent_Done,
     /* 196654 */   // Label 3656: @196654
     /* 196654 */   GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(196699), // Rule ID 1590 //
     /* 196659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 196667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 196670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 196673 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 196676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196680 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196684 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196688 */     // (intrinsic_wo_chain:{ *:[v2i64] } 761:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 196688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i64),
     /* 196691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196693 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196695 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196697 */     GIR_RootConstrainSelectedInstOperands,
     /* 196698 */     // GIR_Coverage, 1590,
     /* 196698 */     GIR_EraseRootFromParent_Done,
     /* 196699 */   // Label 3657: @196699
     /* 196699 */   GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(196744), // Rule ID 1618 //
     /* 196704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196707 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 196712 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 196715 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 196718 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 196721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196725 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196729 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196733 */     // (intrinsic_wo_chain:{ *:[f64] } 795:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 196733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 196736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196740 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196742 */     GIR_RootConstrainSelectedInstOperands,
     /* 196743 */     // GIR_Coverage, 1618,
     /* 196743 */     GIR_EraseRootFromParent_Done,
     /* 196744 */   // Label 3658: @196744
     /* 196744 */   GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(196789), // Rule ID 1619 //
     /* 196749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 196757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196774 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196778 */     // (intrinsic_wo_chain:{ *:[f32] } 795:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 196778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
     /* 196781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196787 */     GIR_RootConstrainSelectedInstOperands,
     /* 196788 */     // GIR_Coverage, 1619,
     /* 196788 */     GIR_EraseRootFromParent_Done,
     /* 196789 */   // Label 3659: @196789
     /* 196789 */   GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(196834), // Rule ID 1620 //
     /* 196794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 196797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 196802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 196805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 196808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 196811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196819 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196823 */     // (intrinsic_wo_chain:{ *:[f16] } 795:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 196823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
     /* 196826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196832 */     GIR_RootConstrainSelectedInstOperands,
     /* 196833 */     // GIR_Coverage, 1620,
     /* 196833 */     GIR_EraseRootFromParent_Done,
     /* 196834 */   // Label 3660: @196834
     /* 196834 */   GIM_Try, /*On fail goto*//*Label 3661*/ GIMT_Encode4(196879), // Rule ID 1621 //
     /* 196839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 196847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 196850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 196853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 196856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196864 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196868 */     // (intrinsic_wo_chain:{ *:[i64] } 587:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 196868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
     /* 196871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196877 */     GIR_RootConstrainSelectedInstOperands,
     /* 196878 */     // GIR_Coverage, 1621,
     /* 196878 */     GIR_EraseRootFromParent_Done,
     /* 196879 */   // Label 3661: @196879
     /* 196879 */   GIM_Try, /*On fail goto*//*Label 3662*/ GIMT_Encode4(196924), // Rule ID 1622 //
     /* 196884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 196892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196909 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196913 */     // (intrinsic_wo_chain:{ *:[i32] } 587:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 196913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE32),
     /* 196916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196922 */     GIR_RootConstrainSelectedInstOperands,
     /* 196923 */     // GIR_Coverage, 1622,
     /* 196923 */     GIR_EraseRootFromParent_Done,
     /* 196924 */   // Label 3662: @196924
     /* 196924 */   GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(196969), // Rule ID 1623 //
     /* 196929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 196937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 196940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 196943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 196946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196950 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196954 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196958 */     // (intrinsic_wo_chain:{ *:[i64] } 588:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 196958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
     /* 196961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 196965 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 196967 */     GIR_RootConstrainSelectedInstOperands,
     /* 196968 */     // GIR_Coverage, 1623,
     /* 196968 */     GIR_EraseRootFromParent_Done,
     /* 196969 */   // Label 3663: @196969
     /* 196969 */   GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(197014), // Rule ID 1624 //
     /* 196974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 196982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196999 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197003 */     // (intrinsic_wo_chain:{ *:[i32] } 588:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 197003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT32),
     /* 197006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197008 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197010 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197012 */     GIR_RootConstrainSelectedInstOperands,
     /* 197013 */     // GIR_Coverage, 1624,
     /* 197013 */     GIR_EraseRootFromParent_Done,
     /* 197014 */   // Label 3664: @197014
     /* 197014 */   GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(197059), // Rule ID 1631 //
     /* 197019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 197027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197044 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197048 */     // (intrinsic_wo_chain:{ *:[f64] } 620:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 197048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 197051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197057 */     GIR_RootConstrainSelectedInstOperands,
     /* 197058 */     // GIR_Coverage, 1631,
     /* 197058 */     GIR_EraseRootFromParent_Done,
     /* 197059 */   // Label 3665: @197059
     /* 197059 */   GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(197104), // Rule ID 1632 //
     /* 197064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197067 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 197072 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197075 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197078 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197085 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197089 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197093 */     // (intrinsic_wo_chain:{ *:[f32] } 620:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 197093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 197096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197098 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197102 */     GIR_RootConstrainSelectedInstOperands,
     /* 197103 */     // GIR_Coverage, 1632,
     /* 197103 */     GIR_EraseRootFromParent_Done,
     /* 197104 */   // Label 3666: @197104
     /* 197104 */   GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(197149), // Rule ID 1633 //
     /* 197109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 197112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 197117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 197120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 197123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 197126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197134 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197138 */     // (intrinsic_wo_chain:{ *:[f16] } 620:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 197138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 197141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197147 */     GIR_RootConstrainSelectedInstOperands,
     /* 197148 */     // GIR_Coverage, 1633,
     /* 197148 */     GIR_EraseRootFromParent_Done,
     /* 197149 */   // Label 3667: @197149
     /* 197149 */   GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(197194), // Rule ID 1634 //
     /* 197154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 197162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197183 */     // (intrinsic_wo_chain:{ *:[f64] } 643:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 197183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
     /* 197186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197192 */     GIR_RootConstrainSelectedInstOperands,
     /* 197193 */     // GIR_Coverage, 1634,
     /* 197193 */     GIR_EraseRootFromParent_Done,
     /* 197194 */   // Label 3668: @197194
     /* 197194 */   GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(197239), // Rule ID 1635 //
     /* 197199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 197207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197224 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197228 */     // (intrinsic_wo_chain:{ *:[f32] } 643:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 197228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS32),
     /* 197231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197237 */     GIR_RootConstrainSelectedInstOperands,
     /* 197238 */     // GIR_Coverage, 1635,
     /* 197238 */     GIR_EraseRootFromParent_Done,
     /* 197239 */   // Label 3669: @197239
     /* 197239 */   GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(197284), // Rule ID 1636 //
     /* 197244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 197247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 197252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 197255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 197258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 197261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197269 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197273 */     // (intrinsic_wo_chain:{ *:[f16] } 643:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 197273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS16),
     /* 197276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197282 */     GIR_RootConstrainSelectedInstOperands,
     /* 197283 */     // GIR_Coverage, 1636,
     /* 197283 */     GIR_EraseRootFromParent_Done,
     /* 197284 */   // Label 3670: @197284
     /* 197284 */   GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(197329), // Rule ID 1637 //
     /* 197289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 197297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197314 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197318 */     // (intrinsic_wo_chain:{ *:[f64] } 650:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 197318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
     /* 197321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197327 */     GIR_RootConstrainSelectedInstOperands,
     /* 197328 */     // GIR_Coverage, 1637,
     /* 197328 */     GIR_EraseRootFromParent_Done,
     /* 197329 */   // Label 3671: @197329
     /* 197329 */   GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(197374), // Rule ID 1638 //
     /* 197334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 197337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 197342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197355 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197359 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197363 */     // (intrinsic_wo_chain:{ *:[f32] } 650:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 197363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS32),
     /* 197366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197370 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197372 */     GIR_RootConstrainSelectedInstOperands,
     /* 197373 */     // GIR_Coverage, 1638,
     /* 197373 */     GIR_EraseRootFromParent_Done,
     /* 197374 */   // Label 3672: @197374
     /* 197374 */   GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(197419), // Rule ID 1639 //
     /* 197379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 197382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 197387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 197390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 197393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 197396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197400 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197404 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197408 */     // (intrinsic_wo_chain:{ *:[f16] } 650:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 197408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS16),
     /* 197411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197417 */     GIR_RootConstrainSelectedInstOperands,
     /* 197418 */     // GIR_Coverage, 1639,
     /* 197418 */     GIR_EraseRootFromParent_Done,
     /* 197419 */   // Label 3673: @197419
     /* 197419 */   GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(197464), // Rule ID 1641 //
     /* 197424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 197432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197445 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197449 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197453 */     // (intrinsic_wo_chain:{ *:[i32] } 690:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 197453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32),
     /* 197456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197460 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197462 */     GIR_RootConstrainSelectedInstOperands,
     /* 197463 */     // GIR_Coverage, 1641,
     /* 197463 */     GIR_EraseRootFromParent_Done,
     /* 197464 */   // Label 3674: @197464
     /* 197464 */   GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(197509), // Rule ID 1642 //
     /* 197469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 197477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197490 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197494 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197498 */     // (intrinsic_wo_chain:{ *:[i32] } 698:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 197498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32),
     /* 197501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197507 */     GIR_RootConstrainSelectedInstOperands,
     /* 197508 */     // GIR_Coverage, 1642,
     /* 197508 */     GIR_EraseRootFromParent_Done,
     /* 197509 */   // Label 3675: @197509
     /* 197509 */   GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(197554), // Rule ID 1643 //
     /* 197514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 197522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197539 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197543 */     // (intrinsic_wo_chain:{ *:[v1i64] } 701:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
     /* 197546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197552 */     GIR_RootConstrainSelectedInstOperands,
     /* 197553 */     // GIR_Coverage, 1643,
     /* 197553 */     GIR_EraseRootFromParent_Done,
     /* 197554 */   // Label 3676: @197554
     /* 197554 */   GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(197599), // Rule ID 1644 //
     /* 197559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 197567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197584 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197588 */     // (intrinsic_wo_chain:{ *:[v1i64] } 704:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
     /* 197591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197595 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197597 */     GIR_RootConstrainSelectedInstOperands,
     /* 197598 */     // GIR_Coverage, 1644,
     /* 197598 */     GIR_EraseRootFromParent_Done,
     /* 197599 */   // Label 3677: @197599
     /* 197599 */   GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(197644), // Rule ID 1646 //
     /* 197604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 197612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197629 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197633 */     // (intrinsic_wo_chain:{ *:[v1i64] } 712:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
     /* 197636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197638 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197642 */     GIR_RootConstrainSelectedInstOperands,
     /* 197643 */     // GIR_Coverage, 1646,
     /* 197643 */     GIR_EraseRootFromParent_Done,
     /* 197644 */   // Label 3678: @197644
     /* 197644 */   GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(197689), // Rule ID 1647 //
     /* 197649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 197657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197674 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197678 */     // (intrinsic_wo_chain:{ *:[v1i64] } 713:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
     /* 197681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197683 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197685 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197687 */     GIR_RootConstrainSelectedInstOperands,
     /* 197688 */     // GIR_Coverage, 1647,
     /* 197688 */     GIR_EraseRootFromParent_Done,
     /* 197689 */   // Label 3679: @197689
     /* 197689 */   GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(197734), // Rule ID 1650 //
     /* 197694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 197702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197715 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197719 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197723 */     // (intrinsic_wo_chain:{ *:[v1i64] } 750:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
     /* 197726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197732 */     GIR_RootConstrainSelectedInstOperands,
     /* 197733 */     // GIR_Coverage, 1650,
     /* 197733 */     GIR_EraseRootFromParent_Done,
     /* 197734 */   // Label 3680: @197734
     /* 197734 */   GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(197779), // Rule ID 1651 //
     /* 197739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 197747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197764 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197768 */     // (intrinsic_wo_chain:{ *:[v1i64] } 752:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
     /* 197771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197777 */     GIR_RootConstrainSelectedInstOperands,
     /* 197778 */     // GIR_Coverage, 1651,
     /* 197778 */     GIR_EraseRootFromParent_Done,
     /* 197779 */   // Label 3681: @197779
     /* 197779 */   GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(197824), // Rule ID 1653 //
     /* 197784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 197792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197809 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197813 */     // (intrinsic_wo_chain:{ *:[v1i64] } 758:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
     /* 197816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197822 */     GIR_RootConstrainSelectedInstOperands,
     /* 197823 */     // GIR_Coverage, 1653,
     /* 197823 */     GIR_EraseRootFromParent_Done,
     /* 197824 */   // Label 3682: @197824
     /* 197824 */   GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(197869), // Rule ID 1654 //
     /* 197829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 197837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197854 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197858 */     // (intrinsic_wo_chain:{ *:[v1i64] } 761:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 197858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
     /* 197861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197865 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197867 */     GIR_RootConstrainSelectedInstOperands,
     /* 197868 */     // GIR_Coverage, 1654,
     /* 197868 */     GIR_EraseRootFromParent_Done,
     /* 197869 */   // Label 3683: @197869
     /* 197869 */   GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(197914), // Rule ID 1655 //
     /* 197874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 197882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197899 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197903 */     // (intrinsic_wo_chain:{ *:[i64] } 694:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 197903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLi32),
     /* 197906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197908 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 197910 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 197912 */     GIR_RootConstrainSelectedInstOperands,
     /* 197913 */     // GIR_Coverage, 1655,
     /* 197913 */     GIR_EraseRootFromParent_Done,
     /* 197914 */   // Label 3684: @197914
     /* 197914 */   GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(197959), // Rule ID 1669 //
     /* 197919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 197927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 197930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 197933 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 197936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197944 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197948 */     // (intrinsic_wo_chain:{ *:[i64] } 725:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)  =>  (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
     /* 197948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
     /* 197951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 197955 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 197957 */     GIR_RootConstrainSelectedInstOperands,
     /* 197958 */     // GIR_Coverage, 1669,
     /* 197958 */     GIR_EraseRootFromParent_Done,
     /* 197959 */   // Label 3685: @197959
     /* 197959 */   GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(198004), // Rule ID 1670 //
     /* 197964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 197972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197989 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197993 */     // (intrinsic_wo_chain:{ *:[i32] } 725:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)  =>  (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
     /* 197993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i32),
     /* 197996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198002 */     GIR_RootConstrainSelectedInstOperands,
     /* 198003 */     // GIR_Coverage, 1670,
     /* 198003 */     GIR_EraseRootFromParent_Done,
     /* 198004 */   // Label 3686: @198004
     /* 198004 */   GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(198049), // Rule ID 1675 //
     /* 198009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 198017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 198020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 198023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 198026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198034 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198038 */     // (intrinsic_wo_chain:{ *:[i64] } 764:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)  =>  (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
     /* 198038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
     /* 198041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198047 */     GIR_RootConstrainSelectedInstOperands,
     /* 198048 */     // GIR_Coverage, 1675,
     /* 198048 */     GIR_EraseRootFromParent_Done,
     /* 198049 */   // Label 3687: @198049
     /* 198049 */   GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(198094), // Rule ID 1676 //
     /* 198054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 198062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 198065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 198068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 198071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198075 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198079 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198083 */     // (intrinsic_wo_chain:{ *:[i32] } 764:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)  =>  (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
     /* 198083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i32),
     /* 198086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198092 */     GIR_RootConstrainSelectedInstOperands,
     /* 198093 */     // GIR_Coverage, 1676,
     /* 198093 */     GIR_EraseRootFromParent_Done,
     /* 198094 */   // Label 3688: @198094
     /* 198094 */   GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(198139), // Rule ID 1677 //
     /* 198099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 198107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 198110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 198113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 198116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198124 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198128 */     // (intrinsic_wo_chain:{ *:[v8i8] } 579:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 198128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
     /* 198131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198135 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198137 */     GIR_RootConstrainSelectedInstOperands,
     /* 198138 */     // GIR_Coverage, 1677,
     /* 198138 */     GIR_EraseRootFromParent_Done,
     /* 198139 */   // Label 3689: @198139
     /* 198139 */   GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(198184), // Rule ID 1678 //
     /* 198144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 198152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198169 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198173 */     // (intrinsic_wo_chain:{ *:[v4i16] } 579:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 198173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
     /* 198176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198182 */     GIR_RootConstrainSelectedInstOperands,
     /* 198183 */     // GIR_Coverage, 1678,
     /* 198183 */     GIR_EraseRootFromParent_Done,
     /* 198184 */   // Label 3690: @198184
     /* 198184 */   GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(198229), // Rule ID 1679 //
     /* 198189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 198197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 198200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 198203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 198206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198214 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198218 */     // (intrinsic_wo_chain:{ *:[v2i32] } 579:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 198218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
     /* 198221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198223 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198225 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198227 */     GIR_RootConstrainSelectedInstOperands,
     /* 198228 */     // GIR_Coverage, 1679,
     /* 198228 */     GIR_EraseRootFromParent_Done,
     /* 198229 */   // Label 3691: @198229
     /* 198229 */   GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(198274), // Rule ID 1680 //
     /* 198234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 198242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 198245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 198248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 198251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198259 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198263 */     // (intrinsic_wo_chain:{ *:[v8i8] } 724:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 198263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 198266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198270 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198272 */     GIR_RootConstrainSelectedInstOperands,
     /* 198273 */     // GIR_Coverage, 1680,
     /* 198273 */     GIR_EraseRootFromParent_Done,
     /* 198274 */   // Label 3692: @198274
     /* 198274 */   GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(198319), // Rule ID 1681 //
     /* 198279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 198287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198304 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198308 */     // (intrinsic_wo_chain:{ *:[v4i16] } 724:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 198308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 198311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198317 */     GIR_RootConstrainSelectedInstOperands,
     /* 198318 */     // GIR_Coverage, 1681,
     /* 198318 */     GIR_EraseRootFromParent_Done,
     /* 198319 */   // Label 3693: @198319
     /* 198319 */   GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(198364), // Rule ID 1682 //
     /* 198324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 198332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 198335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 198338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 198341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198345 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198349 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198353 */     // (intrinsic_wo_chain:{ *:[v2i32] } 724:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 198353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 198356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198360 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198362 */     GIR_RootConstrainSelectedInstOperands,
     /* 198363 */     // GIR_Coverage, 1682,
     /* 198363 */     GIR_EraseRootFromParent_Done,
     /* 198364 */   // Label 3694: @198364
     /* 198364 */   GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(198409), // Rule ID 1683 //
     /* 198369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 198377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 198380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 198383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 198386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198390 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198394 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198398 */     // (intrinsic_wo_chain:{ *:[v8i8] } 666:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 198398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
     /* 198401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198407 */     GIR_RootConstrainSelectedInstOperands,
     /* 198408 */     // GIR_Coverage, 1683,
     /* 198408 */     GIR_EraseRootFromParent_Done,
     /* 198409 */   // Label 3695: @198409
     /* 198409 */   GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(198454), // Rule ID 1684 //
     /* 198414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 198422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198435 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198439 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198443 */     // (intrinsic_wo_chain:{ *:[v4i16] } 666:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 198443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
     /* 198446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198452 */     GIR_RootConstrainSelectedInstOperands,
     /* 198453 */     // GIR_Coverage, 1684,
     /* 198453 */     GIR_EraseRootFromParent_Done,
     /* 198454 */   // Label 3696: @198454
     /* 198454 */   GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(198499), // Rule ID 1685 //
     /* 198459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198462 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 198467 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 198470 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 198473 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 198476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198480 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198484 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198488 */     // (intrinsic_wo_chain:{ *:[v2i32] } 666:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 198488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
     /* 198491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198497 */     GIR_RootConstrainSelectedInstOperands,
     /* 198498 */     // GIR_Coverage, 1685,
     /* 198498 */     GIR_EraseRootFromParent_Done,
     /* 198499 */   // Label 3697: @198499
     /* 198499 */   GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(198544), // Rule ID 1686 //
     /* 198504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 198512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 198515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 198518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 198521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198525 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198529 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198533 */     // (intrinsic_wo_chain:{ *:[v8i8] } 668:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 198533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v8i8),
     /* 198536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198538 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198540 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198542 */     GIR_RootConstrainSelectedInstOperands,
     /* 198543 */     // GIR_Coverage, 1686,
     /* 198543 */     GIR_EraseRootFromParent_Done,
     /* 198544 */   // Label 3698: @198544
     /* 198544 */   GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(198589), // Rule ID 1687 //
     /* 198549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 198557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198574 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198578 */     // (intrinsic_wo_chain:{ *:[v4i16] } 668:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 198578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v4i16),
     /* 198581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198583 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198585 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198587 */     GIR_RootConstrainSelectedInstOperands,
     /* 198588 */     // GIR_Coverage, 1687,
     /* 198588 */     GIR_EraseRootFromParent_Done,
     /* 198589 */   // Label 3699: @198589
     /* 198589 */   GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(198634), // Rule ID 1688 //
     /* 198594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 198602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 198605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 198608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 198611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198619 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198623 */     // (intrinsic_wo_chain:{ *:[v2i32] } 668:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 198623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v2i32),
     /* 198626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198632 */     GIR_RootConstrainSelectedInstOperands,
     /* 198633 */     // GIR_Coverage, 1688,
     /* 198633 */     GIR_EraseRootFromParent_Done,
     /* 198634 */   // Label 3700: @198634
     /* 198634 */   GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(198679), // Rule ID 1754 //
     /* 198639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 198647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 198650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 198653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 198656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198664 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198668 */     // (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 198668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_v4i32),
     /* 198671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198677 */     GIR_RootConstrainSelectedInstOperands,
     /* 198678 */     // GIR_Coverage, 1754,
     /* 198678 */     GIR_EraseRootFromParent_Done,
     /* 198679 */   // Label 3701: @198679
     /* 198679 */   GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(198724), // Rule ID 1756 //
     /* 198684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 198692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 198695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 198698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 198701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198709 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198713 */     // (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 198713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_v2i64),
     /* 198716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198722 */     GIR_RootConstrainSelectedInstOperands,
     /* 198723 */     // GIR_Coverage, 1756,
     /* 198723 */     GIR_EraseRootFromParent_Done,
     /* 198724 */   // Label 3702: @198724
     /* 198724 */   GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(198769), // Rule ID 2307 //
     /* 198729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 198732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
     /* 198737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 198740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 198743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 198746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198754 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198758 */     // (intrinsic_wo_chain:{ *:[v16i8] } 522:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 198758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
     /* 198761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198767 */     GIR_RootConstrainSelectedInstOperands,
     /* 198768 */     // GIR_Coverage, 2307,
     /* 198768 */     GIR_EraseRootFromParent_Done,
     /* 198769 */   // Label 3703: @198769
     /* 198769 */   GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(198814), // Rule ID 2308 //
     /* 198774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 198777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
     /* 198782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 198785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 198788 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 198791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198799 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198803 */     // (intrinsic_wo_chain:{ *:[v16i8] } 521:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 198803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
     /* 198806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198812 */     GIR_RootConstrainSelectedInstOperands,
     /* 198813 */     // GIR_Coverage, 2308,
     /* 198813 */     GIR_EraseRootFromParent_Done,
     /* 198814 */   // Label 3704: @198814
     /* 198814 */   GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(198859), // Rule ID 2319 //
     /* 198819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 198822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su1),
     /* 198827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 198830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198848 */     // (intrinsic_wo_chain:{ *:[v4i32] } 535:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 198848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU1rr),
     /* 198851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198855 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198857 */     GIR_RootConstrainSelectedInstOperands,
     /* 198858 */     // GIR_Coverage, 2319,
     /* 198858 */     GIR_EraseRootFromParent_Done,
     /* 198859 */   // Label 3705: @198859
     /* 198859 */   GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(198904), // Rule ID 2320 //
     /* 198864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 198867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su0),
     /* 198872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 198875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 198878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 198881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198889 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198893 */     // (intrinsic_wo_chain:{ *:[v4i32] } 538:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 198893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU0rr),
     /* 198896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198898 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198900 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198902 */     GIR_RootConstrainSelectedInstOperands,
     /* 198903 */     // GIR_Coverage, 2320,
     /* 198903 */     GIR_EraseRootFromParent_Done,
     /* 198904 */   // Label 3706: @198904
     /* 198904 */   GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(198949), // Rule ID 2343 //
     /* 198909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 198912 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 198917 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198920 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 198923 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 198926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198934 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198938 */     // (intrinsic_wo_chain:{ *:[v4f16] } 641:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (FSCALEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 198938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv4f16),
     /* 198941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198945 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198947 */     GIR_RootConstrainSelectedInstOperands,
     /* 198948 */     // GIR_Coverage, 2343,
     /* 198948 */     GIR_EraseRootFromParent_Done,
     /* 198949 */   // Label 3707: @198949
     /* 198949 */   GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(198994), // Rule ID 2344 //
     /* 198954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 198957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 198962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 198965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 198968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 198971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198975 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198979 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198983 */     // (intrinsic_wo_chain:{ *:[v8f16] } 641:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (FSCALEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 198983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv8f16),
     /* 198986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 198990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 198992 */     GIR_RootConstrainSelectedInstOperands,
     /* 198993 */     // GIR_Coverage, 2344,
     /* 198993 */     GIR_EraseRootFromParent_Done,
     /* 198994 */   // Label 3708: @198994
     /* 198994 */   GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(199039), // Rule ID 2345 //
     /* 198999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 199002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 199007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199024 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199028 */     // (intrinsic_wo_chain:{ *:[v2f32] } 641:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (FSCALEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 199028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv2f32),
     /* 199031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199037 */     GIR_RootConstrainSelectedInstOperands,
     /* 199038 */     // GIR_Coverage, 2345,
     /* 199038 */     GIR_EraseRootFromParent_Done,
     /* 199039 */   // Label 3709: @199039
     /* 199039 */   GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(199084), // Rule ID 2346 //
     /* 199044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 199047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 199052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 199055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 199058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 199061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199069 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199073 */     // (intrinsic_wo_chain:{ *:[v4f32] } 641:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (FSCALEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 199073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv4f32),
     /* 199076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199082 */     GIR_RootConstrainSelectedInstOperands,
     /* 199083 */     // GIR_Coverage, 2346,
     /* 199083 */     GIR_EraseRootFromParent_Done,
     /* 199084 */   // Label 3710: @199084
     /* 199084 */   GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(199129), // Rule ID 2347 //
     /* 199089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 199092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 199097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 199100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 199103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 199106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199110 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199114 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199118 */     // (intrinsic_wo_chain:{ *:[v2f64] } 641:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (FSCALEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 199118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv2f64),
     /* 199121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199127 */     GIR_RootConstrainSelectedInstOperands,
     /* 199128 */     // GIR_Coverage, 2347,
     /* 199128 */     GIR_EraseRootFromParent_Done,
     /* 199129 */   // Label 3711: @199129
     /* 199129 */   GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(199174), // Rule ID 2348 //
     /* 199134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 199142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 199145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199159 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199163 */     // (intrinsic_wo_chain:{ *:[v4f16] } 591:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FAMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 199163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f16),
     /* 199166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199172 */     GIR_RootConstrainSelectedInstOperands,
     /* 199173 */     // GIR_Coverage, 2348,
     /* 199173 */     GIR_EraseRootFromParent_Done,
     /* 199174 */   // Label 3712: @199174
     /* 199174 */   GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(199219), // Rule ID 2351 //
     /* 199179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 199187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 199190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 199193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 199196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199200 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199204 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199208 */     // (intrinsic_wo_chain:{ *:[v8f16] } 591:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FAMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 199208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv8f16),
     /* 199211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199215 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199217 */     GIR_RootConstrainSelectedInstOperands,
     /* 199218 */     // GIR_Coverage, 2351,
     /* 199218 */     GIR_EraseRootFromParent_Done,
     /* 199219 */   // Label 3713: @199219
     /* 199219 */   GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(199264), // Rule ID 2354 //
     /* 199224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 199232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199249 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199253 */     // (intrinsic_wo_chain:{ *:[v2f32] } 591:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FAMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 199253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f32),
     /* 199256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199262 */     GIR_RootConstrainSelectedInstOperands,
     /* 199263 */     // GIR_Coverage, 2354,
     /* 199263 */     GIR_EraseRootFromParent_Done,
     /* 199264 */   // Label 3714: @199264
     /* 199264 */   GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(199309), // Rule ID 2357 //
     /* 199269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 199277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 199280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 199283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 199286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199290 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199298 */     // (intrinsic_wo_chain:{ *:[v4f32] } 591:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FAMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 199298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f32),
     /* 199301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199307 */     GIR_RootConstrainSelectedInstOperands,
     /* 199308 */     // GIR_Coverage, 2357,
     /* 199308 */     GIR_EraseRootFromParent_Done,
     /* 199309 */   // Label 3715: @199309
     /* 199309 */   GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(199354), // Rule ID 2360 //
     /* 199314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 199322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 199325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 199328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 199331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199335 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199339 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199343 */     // (intrinsic_wo_chain:{ *:[v2f64] } 591:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FAMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 199343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f64),
     /* 199346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199352 */     GIR_RootConstrainSelectedInstOperands,
     /* 199353 */     // GIR_Coverage, 2360,
     /* 199353 */     GIR_EraseRootFromParent_Done,
     /* 199354 */   // Label 3716: @199354
     /* 199354 */   GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(199399), // Rule ID 2363 //
     /* 199359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 199367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 199370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199384 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199388 */     // (intrinsic_wo_chain:{ *:[v4f16] } 592:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FAMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 199388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f16),
     /* 199391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199395 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199397 */     GIR_RootConstrainSelectedInstOperands,
     /* 199398 */     // GIR_Coverage, 2363,
     /* 199398 */     GIR_EraseRootFromParent_Done,
     /* 199399 */   // Label 3717: @199399
     /* 199399 */   GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(199444), // Rule ID 2366 //
     /* 199404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 199412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 199415 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 199418 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 199421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199429 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199433 */     // (intrinsic_wo_chain:{ *:[v8f16] } 592:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FAMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 199433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv8f16),
     /* 199436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199442 */     GIR_RootConstrainSelectedInstOperands,
     /* 199443 */     // GIR_Coverage, 2366,
     /* 199443 */     GIR_EraseRootFromParent_Done,
     /* 199444 */   // Label 3718: @199444
     /* 199444 */   GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(199489), // Rule ID 2369 //
     /* 199449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 199457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199470 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199474 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199478 */     // (intrinsic_wo_chain:{ *:[v2f32] } 592:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FAMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 199478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f32),
     /* 199481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199483 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199485 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199487 */     GIR_RootConstrainSelectedInstOperands,
     /* 199488 */     // GIR_Coverage, 2369,
     /* 199488 */     GIR_EraseRootFromParent_Done,
     /* 199489 */   // Label 3719: @199489
     /* 199489 */   GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(199534), // Rule ID 2372 //
     /* 199494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 199502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 199505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 199508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 199511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199515 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199519 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199523 */     // (intrinsic_wo_chain:{ *:[v4f32] } 592:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FAMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 199523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f32),
     /* 199526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199530 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199532 */     GIR_RootConstrainSelectedInstOperands,
     /* 199533 */     // GIR_Coverage, 2372,
     /* 199533 */     GIR_EraseRootFromParent_Done,
     /* 199534 */   // Label 3720: @199534
     /* 199534 */   GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(199579), // Rule ID 2375 //
     /* 199539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 199542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 199547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 199550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 199553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 199556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199564 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199568 */     // (intrinsic_wo_chain:{ *:[v2f64] } 592:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FAMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 199568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f64),
     /* 199571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199577 */     GIR_RootConstrainSelectedInstOperands,
     /* 199578 */     // GIR_Coverage, 2375,
     /* 199578 */     GIR_EraseRootFromParent_Done,
     /* 199579 */   // Label 3721: @199579
     /* 199579 */   GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(199624), // Rule ID 2427 //
     /* 199584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 199587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aese),
     /* 199592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 199595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 199598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 199601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199605 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199609 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199613 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1269:{ *:[iPTR] }, ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)  =>  (AESE_ZZZ_B:{ *:[nxv16i8] } ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)
     /* 199613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESE_ZZZ_B),
     /* 199616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 199618 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 199620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 199622 */     GIR_RootConstrainSelectedInstOperands,
     /* 199623 */     // GIR_Coverage, 2427,
     /* 199623 */     GIR_EraseRootFromParent_Done,
     /* 199624 */   // Label 3722: @199624
     /* 199624 */   GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(199669), // Rule ID 2428 //
     /* 199629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 199632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesd),
     /* 199637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 199640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 199643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 199646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199654 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199658 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1268:{ *:[iPTR] }, ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)  =>  (AESD_ZZZ_B:{ *:[nxv16i8] } ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)
     /* 199658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESD_ZZZ_B),
     /* 199661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 199663 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 199665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 199667 */     GIR_RootConstrainSelectedInstOperands,
     /* 199668 */     // GIR_Coverage, 2428,
     /* 199668 */     GIR_EraseRootFromParent_Done,
     /* 199669 */   // Label 3723: @199669
     /* 199669 */   GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(199714), // Rule ID 2429 //
     /* 199674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVESM4),
     /* 199677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4e),
     /* 199682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 199685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 199688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 199691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199699 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 199703 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1733:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$_Zdn, ZPR32:{ *:[nxv4i32] }:$Zm)  =>  (SM4E_ZZZ_S:{ *:[nxv4i32] } ZPR32:{ *:[nxv4i32] }:$_Zdn, ZPR32:{ *:[nxv4i32] }:$Zm)
     /* 199703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E_ZZZ_S),
     /* 199706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 199708 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 199710 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 199712 */     GIR_RootConstrainSelectedInstOperands,
     /* 199713 */     // GIR_Coverage, 2429,
     /* 199713 */     GIR_EraseRootFromParent_Done,
     /* 199714 */   // Label 3724: @199714
     /* 199714 */   GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(199759), // Rule ID 2508 //
     /* 199719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 199727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 199730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 199733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 199736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199744 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199748 */     // (intrinsic_wo_chain:{ *:[i64] } 689:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 199748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
     /* 199751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199757 */     GIR_RootConstrainSelectedInstOperands,
     /* 199758 */     // GIR_Coverage, 2508,
     /* 199758 */     GIR_EraseRootFromParent_Done,
     /* 199759 */   // Label 3725: @199759
     /* 199759 */   GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(199804), // Rule ID 2509 //
     /* 199764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 199772 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 199775 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 199778 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 199781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 199785 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 199789 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 199793 */     // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 199793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i32),
     /* 199796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199798 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199800 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199802 */     GIR_RootConstrainSelectedInstOperands,
     /* 199803 */     // GIR_Coverage, 2509,
     /* 199803 */     GIR_EraseRootFromParent_Done,
     /* 199804 */   // Label 3726: @199804
     /* 199804 */   GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(199849), // Rule ID 2510 //
     /* 199809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199812 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 199817 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 199820 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 199823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 199826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199830 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199834 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199838 */     // (intrinsic_wo_chain:{ *:[v1f64] } 795:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 199838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 199841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199847 */     GIR_RootConstrainSelectedInstOperands,
     /* 199848 */     // GIR_Coverage, 2510,
     /* 199848 */     GIR_EraseRootFromParent_Done,
     /* 199849 */   // Label 3727: @199849
     /* 199849 */   GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(199894), // Rule ID 2511 //
     /* 199854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 199862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 199865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 199868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 199871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199879 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199883 */     // (intrinsic_wo_chain:{ *:[v1i64] } 587:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 199883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
     /* 199886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199890 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 199892 */     GIR_RootConstrainSelectedInstOperands,
     /* 199893 */     // GIR_Coverage, 2511,
     /* 199893 */     GIR_EraseRootFromParent_Done,
     /* 199894 */   // Label 3728: @199894
     /* 199894 */   GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(199939), // Rule ID 2516 //
     /* 199899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 199907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 199910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 199913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 199916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199924 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199928 */     // (intrinsic_wo_chain:{ *:[v1i64] } 725:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)  =>  (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
     /* 199928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
     /* 199931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 199933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 199935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 199937 */     GIR_RootConstrainSelectedInstOperands,
     /* 199938 */     // GIR_Coverage, 2516,
     /* 199938 */     GIR_EraseRootFromParent_Done,
     /* 199939 */   // Label 3729: @199939
     /* 199939 */   GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(199984), // Rule ID 2634 //
     /* 199944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 199947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 199952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 199955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 199958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 199961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 199965 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 199969 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 199973 */     // (intrinsic_wo_chain:{ *:[i32] } 2035:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQINCP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 199973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_B),
     /* 199976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 199978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 199980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199982 */     GIR_RootConstrainSelectedInstOperands,
     /* 199983 */     // GIR_Coverage, 2634,
     /* 199983 */     GIR_EraseRootFromParent_Done,
     /* 199984 */   // Label 3730: @199984
     /* 199984 */   GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(200029), // Rule ID 2635 //
     /* 199989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 199992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 199997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 200006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200014 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200018 */     // (intrinsic_wo_chain:{ *:[i32] } 2035:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQINCP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 200018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_H),
     /* 200021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200023 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200027 */     GIR_RootConstrainSelectedInstOperands,
     /* 200028 */     // GIR_Coverage, 2635,
     /* 200028 */     GIR_EraseRootFromParent_Done,
     /* 200029 */   // Label 3731: @200029
     /* 200029 */   GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(200074), // Rule ID 2636 //
     /* 200034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 200042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 200051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200055 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200059 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200063 */     // (intrinsic_wo_chain:{ *:[i32] } 2035:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQINCP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 200063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_S),
     /* 200066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200070 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200072 */     GIR_RootConstrainSelectedInstOperands,
     /* 200073 */     // GIR_Coverage, 2636,
     /* 200073 */     GIR_EraseRootFromParent_Done,
     /* 200074 */   // Label 3732: @200074
     /* 200074 */   GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(200119), // Rule ID 2637 //
     /* 200079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 200087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200093 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 200096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200108 */     // (intrinsic_wo_chain:{ *:[i32] } 2035:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQINCP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 200108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_D),
     /* 200111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200113 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200117 */     GIR_RootConstrainSelectedInstOperands,
     /* 200118 */     // GIR_Coverage, 2637,
     /* 200118 */     GIR_EraseRootFromParent_Done,
     /* 200119 */   // Label 3733: @200119
     /* 200119 */   GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(200164), // Rule ID 2638 //
     /* 200124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 200132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 200141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200153 */     // (intrinsic_wo_chain:{ *:[i64] } 1825:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (SQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 200153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_B),
     /* 200156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200160 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200162 */     GIR_RootConstrainSelectedInstOperands,
     /* 200163 */     // GIR_Coverage, 2638,
     /* 200163 */     GIR_EraseRootFromParent_Done,
     /* 200164 */   // Label 3734: @200164
     /* 200164 */   GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(200209), // Rule ID 2639 //
     /* 200169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 200177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 200186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200190 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200194 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200198 */     // (intrinsic_wo_chain:{ *:[i64] } 1825:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (SQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 200198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_H),
     /* 200201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200203 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200207 */     GIR_RootConstrainSelectedInstOperands,
     /* 200208 */     // GIR_Coverage, 2639,
     /* 200208 */     GIR_EraseRootFromParent_Done,
     /* 200209 */   // Label 3735: @200209
     /* 200209 */   GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(200254), // Rule ID 2640 //
     /* 200214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 200222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 200231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200239 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200243 */     // (intrinsic_wo_chain:{ *:[i64] } 1825:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (SQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 200243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_S),
     /* 200246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200248 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200252 */     GIR_RootConstrainSelectedInstOperands,
     /* 200253 */     // GIR_Coverage, 2640,
     /* 200253 */     GIR_EraseRootFromParent_Done,
     /* 200254 */   // Label 3736: @200254
     /* 200254 */   GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(200299), // Rule ID 2641 //
     /* 200259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 200262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 200267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 200276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 200284 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 200288 */     // (intrinsic_wo_chain:{ *:[i64] } 1825:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (SQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 200288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_D),
     /* 200291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 200293 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 200295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200297 */     GIR_RootConstrainSelectedInstOperands,
     /* 200298 */     // GIR_Coverage, 2641,
     /* 200298 */     GIR_EraseRootFromParent_Done,
     /* 200299 */   // Label 3737: @200299
     /* 200299 */   GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(200344), // Rule ID 3848 //
     /* 200304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 200307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su0),
     /* 200312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 200315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 200318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 200321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200329 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200333 */     // (intrinsic_wo_chain:{ *:[v2i64] } 542:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512SU0:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 200333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU0),
     /* 200336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 200338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 200340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 200342 */     GIR_RootConstrainSelectedInstOperands,
     /* 200343 */     // GIR_Coverage, 3848,
     /* 200343 */     GIR_EraseRootFromParent_Done,
     /* 200344 */   // Label 3738: @200344
     /* 200344 */   GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(200389), // Rule ID 3876 //
     /* 200349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 200352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_rax1),
     /* 200357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 200360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 200363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 200366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200370 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200374 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200378 */     // (intrinsic_wo_chain:{ *:[v2i64] } 529:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (RAX1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 200378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1),
     /* 200381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 200383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 200385 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 200387 */     GIR_RootConstrainSelectedInstOperands,
     /* 200388 */     // GIR_Coverage, 3876,
     /* 200388 */     GIR_EraseRootFromParent_Done,
     /* 200389 */   // Label 3739: @200389
     /* 200389 */   GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(200434), // Rule ID 3886 //
     /* 200394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 200397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4ekey),
     /* 200402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 200405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 200408 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 200411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200423 */     // (intrinsic_wo_chain:{ *:[v4i32] } 552:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM4ENCKEY:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 200423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4ENCKEY),
     /* 200426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 200428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 200430 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 200432 */     GIR_RootConstrainSelectedInstOperands,
     /* 200433 */     // GIR_Coverage, 3886,
     /* 200433 */     GIR_EraseRootFromParent_Done,
     /* 200434 */   // Label 3740: @200434
     /* 200434 */   GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(200479), // Rule ID 3887 //
     /* 200439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 200442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4e),
     /* 200447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 200450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 200453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 200456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200460 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200464 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200468 */     // (intrinsic_wo_chain:{ *:[v4i32] } 551:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM4E:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 200468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E),
     /* 200471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 200473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 200475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 200477 */     GIR_RootConstrainSelectedInstOperands,
     /* 200478 */     // GIR_Coverage, 3887,
     /* 200478 */     GIR_EraseRootFromParent_Done,
     /* 200479 */   // Label 3741: @200479
     /* 200479 */   GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(200527), // Rule ID 3888 //
     /* 200484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 200487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 200492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 200495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 200498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 200501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200509 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200513 */     // (intrinsic_wo_chain:{ *:[v4f16] } 766:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
     /* 200513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
     /* 200516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 200525 */     GIR_RootConstrainSelectedInstOperands,
     /* 200526 */     // GIR_Coverage, 3888,
     /* 200526 */     GIR_EraseRootFromParent_Done,
     /* 200527 */   // Label 3742: @200527
     /* 200527 */   GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(200575), // Rule ID 3889 //
     /* 200532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 200535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 200540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 200543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 200546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 200549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200553 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200557 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200561 */     // (intrinsic_wo_chain:{ *:[v4f16] } 765:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
     /* 200561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
     /* 200564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200566 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200568 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 200573 */     GIR_RootConstrainSelectedInstOperands,
     /* 200574 */     // GIR_Coverage, 3889,
     /* 200574 */     GIR_EraseRootFromParent_Done,
     /* 200575 */   // Label 3743: @200575
     /* 200575 */   GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(200623), // Rule ID 3890 //
     /* 200580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 200583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 200588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 200591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 200594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 200597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200601 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200605 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200609 */     // (intrinsic_wo_chain:{ *:[v8f16] } 766:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
     /* 200609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
     /* 200612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 200621 */     GIR_RootConstrainSelectedInstOperands,
     /* 200622 */     // GIR_Coverage, 3890,
     /* 200622 */     GIR_EraseRootFromParent_Done,
     /* 200623 */   // Label 3744: @200623
     /* 200623 */   GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(200671), // Rule ID 3891 //
     /* 200628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 200631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 200636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 200639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 200642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 200645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200649 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200653 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200657 */     // (intrinsic_wo_chain:{ *:[v8f16] } 765:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
     /* 200657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
     /* 200660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 200669 */     GIR_RootConstrainSelectedInstOperands,
     /* 200670 */     // GIR_Coverage, 3891,
     /* 200670 */     GIR_EraseRootFromParent_Done,
     /* 200671 */   // Label 3745: @200671
     /* 200671 */   GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(200719), // Rule ID 3892 //
     /* 200676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 200684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 200687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 200690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 200693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200701 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200705 */     // (intrinsic_wo_chain:{ *:[v2f32] } 766:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
     /* 200705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
     /* 200708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200712 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 200717 */     GIR_RootConstrainSelectedInstOperands,
     /* 200718 */     // GIR_Coverage, 3892,
     /* 200718 */     GIR_EraseRootFromParent_Done,
     /* 200719 */   // Label 3746: @200719
     /* 200719 */   GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(200767), // Rule ID 3893 //
     /* 200724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 200732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 200735 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 200738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 200741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200749 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200753 */     // (intrinsic_wo_chain:{ *:[v2f32] } 765:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
     /* 200753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
     /* 200756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 200765 */     GIR_RootConstrainSelectedInstOperands,
     /* 200766 */     // GIR_Coverage, 3893,
     /* 200766 */     GIR_EraseRootFromParent_Done,
     /* 200767 */   // Label 3747: @200767
     /* 200767 */   GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(200815), // Rule ID 3894 //
     /* 200772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 200780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 200783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 200786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 200789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200801 */     // (intrinsic_wo_chain:{ *:[v4f32] } 766:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
     /* 200801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
     /* 200804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 200813 */     GIR_RootConstrainSelectedInstOperands,
     /* 200814 */     // GIR_Coverage, 3894,
     /* 200814 */     GIR_EraseRootFromParent_Done,
     /* 200815 */   // Label 3748: @200815
     /* 200815 */   GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(200863), // Rule ID 3895 //
     /* 200820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 200828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 200831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 200834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 200837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200845 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200849 */     // (intrinsic_wo_chain:{ *:[v4f32] } 765:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
     /* 200849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
     /* 200852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 200861 */     GIR_RootConstrainSelectedInstOperands,
     /* 200862 */     // GIR_Coverage, 3895,
     /* 200862 */     GIR_EraseRootFromParent_Done,
     /* 200863 */   // Label 3749: @200863
     /* 200863 */   GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(200911), // Rule ID 3896 //
     /* 200868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 200876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 200879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 200882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 200885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200893 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200897 */     // (intrinsic_wo_chain:{ *:[v2f64] } 766:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
     /* 200897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
     /* 200900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 200909 */     GIR_RootConstrainSelectedInstOperands,
     /* 200910 */     // GIR_Coverage, 3896,
     /* 200910 */     GIR_EraseRootFromParent_Done,
     /* 200911 */   // Label 3750: @200911
     /* 200911 */   GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(200959), // Rule ID 3897 //
     /* 200916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 200919 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 200924 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 200927 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 200930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 200933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200941 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200945 */     // (intrinsic_wo_chain:{ *:[v2f64] } 765:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
     /* 200945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
     /* 200948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200950 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200952 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 200957 */     GIR_RootConstrainSelectedInstOperands,
     /* 200958 */     // GIR_Coverage, 3897,
     /* 200958 */     GIR_EraseRootFromParent_Done,
     /* 200959 */   // Label 3751: @200959
     /* 200959 */   GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(201001), // Rule ID 3962 //
     /* 200964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
     /* 200969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200975 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 200978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200986 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 200990 */     // (intrinsic_wo_chain:{ *:[i32] } 2179:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 200990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
     /* 200993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200995 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200997 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 200999 */     GIR_RootConstrainSelectedInstOperands,
     /* 201000 */     // GIR_Coverage, 3962,
     /* 201000 */     GIR_EraseRootFromParent_Done,
     /* 201001 */   // Label 3752: @201001
     /* 201001 */   GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(201043), // Rule ID 3963 //
     /* 201006 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
     /* 201011 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201014 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201017 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201028 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201032 */     // (intrinsic_wo_chain:{ *:[i64] } 2179:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 201032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
     /* 201035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201039 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201041 */     GIR_RootConstrainSelectedInstOperands,
     /* 201042 */     // GIR_Coverage, 3963,
     /* 201042 */     GIR_EraseRootFromParent_Done,
     /* 201043 */   // Label 3753: @201043
     /* 201043 */   GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(201085), // Rule ID 3964 //
     /* 201048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
     /* 201053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201059 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 201066 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 201070 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 201074 */     // (intrinsic_wo_chain:{ *:[i32] } 789:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 201074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
     /* 201077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201079 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201081 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201083 */     GIR_RootConstrainSelectedInstOperands,
     /* 201084 */     // GIR_Coverage, 3964,
     /* 201084 */     GIR_EraseRootFromParent_Done,
     /* 201085 */   // Label 3754: @201085
     /* 201085 */   GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(201127), // Rule ID 3965 //
     /* 201090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
     /* 201095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201112 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 201116 */     // (intrinsic_wo_chain:{ *:[i64] } 789:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 201116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
     /* 201119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201125 */     GIR_RootConstrainSelectedInstOperands,
     /* 201126 */     // GIR_Coverage, 3965,
     /* 201126 */     GIR_EraseRootFromParent_Done,
     /* 201127 */   // Label 3755: @201127
     /* 201127 */   GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(201169), // Rule ID 5255 //
     /* 201132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 201137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201158 */     // (intrinsic_wo_chain:{ *:[v1f64] } 586:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 201158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 201161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201167 */     GIR_RootConstrainSelectedInstOperands,
     /* 201168 */     // GIR_Coverage, 5255,
     /* 201168 */     GIR_EraseRootFromParent_Done,
     /* 201169 */   // Label 3756: @201169
     /* 201169 */   GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(201214), // Rule ID 5259 //
     /* 201174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 201182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201199 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201203 */     // (intrinsic_wo_chain:{ *:[v1i64] } 588:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 201203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
     /* 201206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201210 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201212 */     GIR_RootConstrainSelectedInstOperands,
     /* 201213 */     // GIR_Coverage, 5259,
     /* 201213 */     GIR_EraseRootFromParent_Done,
     /* 201214 */   // Label 3757: @201214
     /* 201214 */   GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(201259), // Rule ID 5263 //
     /* 201219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201233 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201244 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201248 */     // (intrinsic_wo_chain:{ *:[v1f64] } 620:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 201248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 201251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201257 */     GIR_RootConstrainSelectedInstOperands,
     /* 201258 */     // GIR_Coverage, 5263,
     /* 201258 */     GIR_EraseRootFromParent_Done,
     /* 201259 */   // Label 3758: @201259
     /* 201259 */   GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(201304), // Rule ID 5264 //
     /* 201264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 201272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201289 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201293 */     // (intrinsic_wo_chain:{ *:[v1f64] } 643:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 201293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
     /* 201296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201298 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201300 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201302 */     GIR_RootConstrainSelectedInstOperands,
     /* 201303 */     // GIR_Coverage, 5264,
     /* 201303 */     GIR_EraseRootFromParent_Done,
     /* 201304 */   // Label 3759: @201304
     /* 201304 */   GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(201349), // Rule ID 5265 //
     /* 201309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 201317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201334 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201338 */     // (intrinsic_wo_chain:{ *:[v1f64] } 650:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 201338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
     /* 201341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201347 */     GIR_RootConstrainSelectedInstOperands,
     /* 201348 */     // GIR_Coverage, 5265,
     /* 201348 */     GIR_EraseRootFromParent_Done,
     /* 201349 */   // Label 3760: @201349
     /* 201349 */   GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(201394), // Rule ID 5266 //
     /* 201354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 201362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201383 */     // (intrinsic_wo_chain:{ *:[i64] } 701:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
     /* 201386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201392 */     GIR_RootConstrainSelectedInstOperands,
     /* 201393 */     // GIR_Coverage, 5266,
     /* 201393 */     GIR_EraseRootFromParent_Done,
     /* 201394 */   // Label 3761: @201394
     /* 201394 */   GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(201439), // Rule ID 5267 //
     /* 201399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 201407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201420 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201424 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201428 */     // (intrinsic_wo_chain:{ *:[i32] } 701:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i32),
     /* 201431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201433 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201435 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201437 */     GIR_RootConstrainSelectedInstOperands,
     /* 201438 */     // GIR_Coverage, 5267,
     /* 201438 */     GIR_EraseRootFromParent_Done,
     /* 201439 */   // Label 3762: @201439
     /* 201439 */   GIM_Try, /*On fail goto*//*Label 3763*/ GIMT_Encode4(201484), // Rule ID 5268 //
     /* 201444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 201452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201469 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201473 */     // (intrinsic_wo_chain:{ *:[i64] } 704:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
     /* 201476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201480 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201482 */     GIR_RootConstrainSelectedInstOperands,
     /* 201483 */     // GIR_Coverage, 5268,
     /* 201483 */     GIR_EraseRootFromParent_Done,
     /* 201484 */   // Label 3763: @201484
     /* 201484 */   GIM_Try, /*On fail goto*//*Label 3764*/ GIMT_Encode4(201529), // Rule ID 5269 //
     /* 201489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 201497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201514 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201518 */     // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i32),
     /* 201521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201523 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201525 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201527 */     GIR_RootConstrainSelectedInstOperands,
     /* 201528 */     // GIR_Coverage, 5269,
     /* 201528 */     GIR_EraseRootFromParent_Done,
     /* 201529 */   // Label 3764: @201529
     /* 201529 */   GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(201574), // Rule ID 5270 //
     /* 201534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 201542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201555 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201559 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201563 */     // (intrinsic_wo_chain:{ *:[i64] } 708:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
     /* 201566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201572 */     GIR_RootConstrainSelectedInstOperands,
     /* 201573 */     // GIR_Coverage, 5270,
     /* 201573 */     GIR_EraseRootFromParent_Done,
     /* 201574 */   // Label 3765: @201574
     /* 201574 */   GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(201619), // Rule ID 5271 //
     /* 201579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 201587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201600 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201604 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201608 */     // (intrinsic_wo_chain:{ *:[i32] } 708:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i32),
     /* 201611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201615 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201617 */     GIR_RootConstrainSelectedInstOperands,
     /* 201618 */     // GIR_Coverage, 5271,
     /* 201618 */     GIR_EraseRootFromParent_Done,
     /* 201619 */   // Label 3766: @201619
     /* 201619 */   GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(201664), // Rule ID 5272 //
     /* 201624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
     /* 201632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201649 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201653 */     // (intrinsic_wo_chain:{ *:[i64] } 749:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
     /* 201656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201662 */     GIR_RootConstrainSelectedInstOperands,
     /* 201663 */     // GIR_Coverage, 5272,
     /* 201663 */     GIR_EraseRootFromParent_Done,
     /* 201664 */   // Label 3767: @201664
     /* 201664 */   GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(201709), // Rule ID 5273 //
     /* 201669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
     /* 201677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201694 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201698 */     // (intrinsic_wo_chain:{ *:[i32] } 749:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i32),
     /* 201701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201707 */     GIR_RootConstrainSelectedInstOperands,
     /* 201708 */     // GIR_Coverage, 5273,
     /* 201708 */     GIR_EraseRootFromParent_Done,
     /* 201709 */   // Label 3768: @201709
     /* 201709 */   GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(201754), // Rule ID 5274 //
     /* 201714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 201722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201728 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201739 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201743 */     // (intrinsic_wo_chain:{ *:[i64] } 750:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
     /* 201746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201748 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201750 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201752 */     GIR_RootConstrainSelectedInstOperands,
     /* 201753 */     // GIR_Coverage, 5274,
     /* 201753 */     GIR_EraseRootFromParent_Done,
     /* 201754 */   // Label 3769: @201754
     /* 201754 */   GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(201799), // Rule ID 5275 //
     /* 201759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 201767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201784 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201788 */     // (intrinsic_wo_chain:{ *:[i32] } 750:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i32),
     /* 201791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201797 */     GIR_RootConstrainSelectedInstOperands,
     /* 201798 */     // GIR_Coverage, 5275,
     /* 201798 */     GIR_EraseRootFromParent_Done,
     /* 201799 */   // Label 3770: @201799
     /* 201799 */   GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(201844), // Rule ID 5276 //
     /* 201804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 201812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201825 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201829 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201833 */     // (intrinsic_wo_chain:{ *:[i64] } 752:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
     /* 201836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201842 */     GIR_RootConstrainSelectedInstOperands,
     /* 201843 */     // GIR_Coverage, 5276,
     /* 201843 */     GIR_EraseRootFromParent_Done,
     /* 201844 */   // Label 3771: @201844
     /* 201844 */   GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(201889), // Rule ID 5277 //
     /* 201849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 201857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201878 */     // (intrinsic_wo_chain:{ *:[i32] } 752:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i32),
     /* 201881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201887 */     GIR_RootConstrainSelectedInstOperands,
     /* 201888 */     // GIR_Coverage, 5277,
     /* 201888 */     GIR_EraseRootFromParent_Done,
     /* 201889 */   // Label 3772: @201889
     /* 201889 */   GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(201934), // Rule ID 5278 //
     /* 201894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
     /* 201902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201919 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201923 */     // (intrinsic_wo_chain:{ *:[i64] } 754:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 201923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
     /* 201926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201930 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201932 */     GIR_RootConstrainSelectedInstOperands,
     /* 201933 */     // GIR_Coverage, 5278,
     /* 201933 */     GIR_EraseRootFromParent_Done,
     /* 201934 */   // Label 3773: @201934
     /* 201934 */   GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(201979), // Rule ID 5279 //
     /* 201939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201942 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
     /* 201947 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201960 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201964 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201968 */     // (intrinsic_wo_chain:{ *:[i32] } 754:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 201968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i32),
     /* 201971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 201977 */     GIR_RootConstrainSelectedInstOperands,
     /* 201978 */     // GIR_Coverage, 5279,
     /* 201978 */     GIR_EraseRootFromParent_Done,
     /* 201979 */   // Label 3774: @201979
     /* 201979 */   GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(202024), // Rule ID 5298 //
     /* 201984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201987 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 201992 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201995 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201998 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202009 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202013 */     // (intrinsic_wo_chain:{ *:[v1i64] } 764:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)  =>  (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
     /* 202013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
     /* 202016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 202018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 202020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 202022 */     GIR_RootConstrainSelectedInstOperands,
     /* 202023 */     // GIR_Coverage, 5298,
     /* 202023 */     GIR_EraseRootFromParent_Done,
     /* 202024 */   // Label 3775: @202024
     /* 202024 */   GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(202066), // Rule ID 5632 //
     /* 202029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
     /* 202034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 202037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 202040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 202043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202047 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202051 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202055 */     // (intrinsic_wo_chain:{ *:[v8i8] } 726:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)  =>  (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
     /* 202055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv8i8One),
     /* 202058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 202060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ri
     /* 202064 */     GIR_RootConstrainSelectedInstOperands,
     /* 202065 */     // GIR_Coverage, 5632,
     /* 202065 */     GIR_EraseRootFromParent_Done,
     /* 202066 */   // Label 3776: @202066
     /* 202066 */   GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(202108), // Rule ID 5633 //
     /* 202071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
     /* 202076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 202079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 202082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 202085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202089 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202093 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202097 */     // (intrinsic_wo_chain:{ *:[v16i8] } 726:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)  =>  (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
     /* 202097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv16i8One),
     /* 202100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 202102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ri
     /* 202104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 202106 */     GIR_RootConstrainSelectedInstOperands,
     /* 202107 */     // GIR_Coverage, 5633,
     /* 202107 */     GIR_EraseRootFromParent_Done,
     /* 202108 */   // Label 3777: @202108
     /* 202108 */   GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(202205), // Rule ID 6360 //
     /* 202113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 202118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 202124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 202127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202135 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202139 */     // (intrinsic_wo_chain:{ *:[i32] } 587:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
     /* 202139 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 202142 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGE16),
     /* 202146 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 202151 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 202155 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 202159 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 202161 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 202164 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 202168 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 202173 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 202175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 202178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 202180 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 202183 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 202186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 202189 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202194 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202199 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202204 */     // GIR_Coverage, 6360,
     /* 202204 */     GIR_EraseRootFromParent_Done,
     /* 202205 */   // Label 3778: @202205
     /* 202205 */   GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(202302), // Rule ID 6361 //
     /* 202210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 202215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 202221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 202224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202232 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202236 */     // (intrinsic_wo_chain:{ *:[i32] } 588:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
     /* 202236 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 202239 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGT16),
     /* 202243 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 202248 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 202252 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 202256 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 202258 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 202261 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 202265 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 202270 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 202272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 202275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 202277 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 202280 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 202283 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 202286 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202291 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202296 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202301 */     // GIR_Coverage, 6361,
     /* 202301 */     GIR_EraseRootFromParent_Done,
     /* 202302 */   // Label 3779: @202302
     /* 202302 */   GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(202344), // Rule ID 7016 //
     /* 202307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 202312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202329 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202333 */     // (intrinsic_wo_chain:{ *:[i64] } 713:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 202333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
     /* 202336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 202342 */     GIR_RootConstrainSelectedInstOperands,
     /* 202343 */     // GIR_Coverage, 7016,
     /* 202343 */     GIR_EraseRootFromParent_Done,
     /* 202344 */   // Label 3780: @202344
     /* 202344 */   GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(202386), // Rule ID 7017 //
     /* 202349 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 202354 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202357 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202360 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202371 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202375 */     // (intrinsic_wo_chain:{ *:[i64] } 761:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 202375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
     /* 202378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202380 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202382 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 202384 */     GIR_RootConstrainSelectedInstOperands,
     /* 202385 */     // GIR_Coverage, 7017,
     /* 202385 */     GIR_EraseRootFromParent_Done,
     /* 202386 */   // Label 3781: @202386
     /* 202386 */   GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(202428), // Rule ID 7018 //
     /* 202391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 202396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202413 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202417 */     // (intrinsic_wo_chain:{ *:[i64] } 712:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 202417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
     /* 202420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 202426 */     GIR_RootConstrainSelectedInstOperands,
     /* 202427 */     // GIR_Coverage, 7018,
     /* 202427 */     GIR_EraseRootFromParent_Done,
     /* 202428 */   // Label 3782: @202428
     /* 202428 */   GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(202470), // Rule ID 7019 //
     /* 202433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 202438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202451 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202455 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202459 */     // (intrinsic_wo_chain:{ *:[i64] } 758:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 202459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
     /* 202462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 202468 */     GIR_RootConstrainSelectedInstOperands,
     /* 202469 */     // GIR_Coverage, 7019,
     /* 202469 */     GIR_EraseRootFromParent_Done,
     /* 202470 */   // Label 3783: @202470
     /* 202470 */   GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(202518), // Rule ID 7059 //
     /* 202475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
     /* 202480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202486 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202493 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202497 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202501 */     // (intrinsic_wo_chain:{ *:[i64] } 298:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn)  =>  (BFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, 16:{ *:[i64] }, 15:{ *:[i64] })
     /* 202501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMXri),
     /* 202504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 202508 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 202510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /* 202513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 202516 */     GIR_RootConstrainSelectedInstOperands,
     /* 202517 */     // GIR_Coverage, 7059,
     /* 202517 */     GIR_EraseRootFromParent_Done,
     /* 202518 */   // Label 3784: @202518
     /* 202518 */   GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(202563), // Rule ID 10148 //
     /* 202523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 202531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 202540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202548 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202552 */     // (intrinsic_wo_chain:{ *:[i64] } 2036:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_B),
     /* 202555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202557 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202561 */     GIR_RootConstrainSelectedInstOperands,
     /* 202562 */     // GIR_Coverage, 10148,
     /* 202562 */     GIR_EraseRootFromParent_Done,
     /* 202563 */   // Label 3785: @202563
     /* 202563 */   GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(202608), // Rule ID 10149 //
     /* 202568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 202576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 202585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202597 */     // (intrinsic_wo_chain:{ *:[i64] } 2036:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_H),
     /* 202600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202606 */     GIR_RootConstrainSelectedInstOperands,
     /* 202607 */     // GIR_Coverage, 10149,
     /* 202607 */     GIR_EraseRootFromParent_Done,
     /* 202608 */   // Label 3786: @202608
     /* 202608 */   GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(202653), // Rule ID 10150 //
     /* 202613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 202621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 202630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202634 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202638 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202642 */     // (intrinsic_wo_chain:{ *:[i64] } 2036:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_S),
     /* 202645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202647 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202649 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202651 */     GIR_RootConstrainSelectedInstOperands,
     /* 202652 */     // GIR_Coverage, 10150,
     /* 202652 */     GIR_EraseRootFromParent_Done,
     /* 202653 */   // Label 3787: @202653
     /* 202653 */   GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(202698), // Rule ID 10151 //
     /* 202658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 202666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 202675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202679 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202683 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202687 */     // (intrinsic_wo_chain:{ *:[i64] } 2036:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_D),
     /* 202690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202696 */     GIR_RootConstrainSelectedInstOperands,
     /* 202697 */     // GIR_Coverage, 10151,
     /* 202697 */     GIR_EraseRootFromParent_Done,
     /* 202698 */   // Label 3788: @202698
     /* 202698 */   GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(202743), // Rule ID 10160 //
     /* 202703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 202711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 202720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202724 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202728 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202732 */     // (intrinsic_wo_chain:{ *:[i64] } 1791:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (SQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_B),
     /* 202735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202737 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202741 */     GIR_RootConstrainSelectedInstOperands,
     /* 202742 */     // GIR_Coverage, 10160,
     /* 202742 */     GIR_EraseRootFromParent_Done,
     /* 202743 */   // Label 3789: @202743
     /* 202743 */   GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(202788), // Rule ID 10161 //
     /* 202748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 202756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 202765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202773 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202777 */     // (intrinsic_wo_chain:{ *:[i64] } 1791:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (SQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_H),
     /* 202780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202782 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202786 */     GIR_RootConstrainSelectedInstOperands,
     /* 202787 */     // GIR_Coverage, 10161,
     /* 202787 */     GIR_EraseRootFromParent_Done,
     /* 202788 */   // Label 3790: @202788
     /* 202788 */   GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(202833), // Rule ID 10162 //
     /* 202793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 202801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202807 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 202810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202822 */     // (intrinsic_wo_chain:{ *:[i64] } 1791:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (SQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_S),
     /* 202825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202827 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202831 */     GIR_RootConstrainSelectedInstOperands,
     /* 202832 */     // GIR_Coverage, 10162,
     /* 202832 */     GIR_EraseRootFromParent_Done,
     /* 202833 */   // Label 3791: @202833
     /* 202833 */   GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(202878), // Rule ID 10163 //
     /* 202838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 202846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 202855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 202863 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202867 */     // (intrinsic_wo_chain:{ *:[i64] } 1791:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (SQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 202867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_D),
     /* 202870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202874 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202876 */     GIR_RootConstrainSelectedInstOperands,
     /* 202877 */     // GIR_Coverage, 10163,
     /* 202877 */     GIR_EraseRootFromParent_Done,
     /* 202878 */   // Label 3792: @202878
     /* 202878 */   GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(202923), // Rule ID 10164 //
     /* 202883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 202891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 202897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 202900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202904 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202908 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202912 */     // (intrinsic_wo_chain:{ *:[i32] } 2021:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQDECP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 202912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_B),
     /* 202915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202917 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202919 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202921 */     GIR_RootConstrainSelectedInstOperands,
     /* 202922 */     // GIR_Coverage, 10164,
     /* 202922 */     GIR_EraseRootFromParent_Done,
     /* 202923 */   // Label 3793: @202923
     /* 202923 */   GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(202968), // Rule ID 10165 //
     /* 202928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 202936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 202942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 202945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202949 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202953 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 202957 */     // (intrinsic_wo_chain:{ *:[i32] } 2021:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQDECP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 202957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_H),
     /* 202960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 202962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 202964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202966 */     GIR_RootConstrainSelectedInstOperands,
     /* 202967 */     // GIR_Coverage, 10165,
     /* 202967 */     GIR_EraseRootFromParent_Done,
     /* 202968 */   // Label 3794: @202968
     /* 202968 */   GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(203013), // Rule ID 10166 //
     /* 202973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 202976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 202981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 202987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 202990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 202998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203002 */     // (intrinsic_wo_chain:{ *:[i32] } 2021:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQDECP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 203002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_S),
     /* 203005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203007 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203011 */     GIR_RootConstrainSelectedInstOperands,
     /* 203012 */     // GIR_Coverage, 10166,
     /* 203012 */     GIR_EraseRootFromParent_Done,
     /* 203013 */   // Label 3795: @203013
     /* 203013 */   GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(203058), // Rule ID 10167 //
     /* 203018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 203026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 203032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 203035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 203039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 203043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203047 */     // (intrinsic_wo_chain:{ *:[i32] } 2021:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQDECP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 203047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_D),
     /* 203050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203052 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203056 */     GIR_RootConstrainSelectedInstOperands,
     /* 203057 */     // GIR_Coverage, 10167,
     /* 203057 */     GIR_EraseRootFromParent_Done,
     /* 203058 */   // Label 3796: @203058
     /* 203058 */   GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(203103), // Rule ID 10168 //
     /* 203063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 203071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203088 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203092 */     // (intrinsic_wo_chain:{ *:[i64] } 2022:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 203092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_B),
     /* 203095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203099 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203101 */     GIR_RootConstrainSelectedInstOperands,
     /* 203102 */     // GIR_Coverage, 10168,
     /* 203102 */     GIR_EraseRootFromParent_Done,
     /* 203103 */   // Label 3797: @203103
     /* 203103 */   GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(203148), // Rule ID 10169 //
     /* 203108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 203116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 203125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203133 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203137 */     // (intrinsic_wo_chain:{ *:[i64] } 2022:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 203137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_H),
     /* 203140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203146 */     GIR_RootConstrainSelectedInstOperands,
     /* 203147 */     // GIR_Coverage, 10169,
     /* 203147 */     GIR_EraseRootFromParent_Done,
     /* 203148 */   // Label 3798: @203148
     /* 203148 */   GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(203193), // Rule ID 10170 //
     /* 203153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 203161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 203170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203178 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203182 */     // (intrinsic_wo_chain:{ *:[i64] } 2022:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 203182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_S),
     /* 203185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203187 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203189 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203191 */     GIR_RootConstrainSelectedInstOperands,
     /* 203192 */     // GIR_Coverage, 10170,
     /* 203192 */     GIR_EraseRootFromParent_Done,
     /* 203193 */   // Label 3799: @203193
     /* 203193 */   GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(203238), // Rule ID 10171 //
     /* 203198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 203206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 203215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203223 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203227 */     // (intrinsic_wo_chain:{ *:[i64] } 2022:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 203227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_D),
     /* 203230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 203232 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 203234 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203236 */     GIR_RootConstrainSelectedInstOperands,
     /* 203237 */     // GIR_Coverage, 10171,
     /* 203237 */     GIR_EraseRootFromParent_Done,
     /* 203238 */   // Label 3800: @203238
     /* 203238 */   GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(203284), // Rule ID 138 //
     /* 203243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 203246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gmi),
     /* 203251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 203257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203261 */     // MIs[0] Rn
     /* 203261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 203265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 203269 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203273 */     // (intrinsic_wo_chain:{ *:[i64] } 565:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 203273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GMI),
     /* 203276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 203282 */     GIR_RootConstrainSelectedInstOperands,
     /* 203283 */     // GIR_Coverage, 138,
     /* 203283 */     GIR_EraseRootFromParent_Done,
     /* 203284 */   // Label 3801: @203284
     /* 203284 */   GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(203331), // Rule ID 139 //
     /* 203289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 203292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_subp),
     /* 203297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203304 */     // MIs[0] Rn
     /* 203304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 203308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 203312 */     // MIs[0] Rm
     /* 203312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 203316 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 203320 */     // (intrinsic_wo_chain:{ *:[i64] } 1252:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
     /* 203320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBP),
     /* 203323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203327 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 203329 */     GIR_RootConstrainSelectedInstOperands,
     /* 203330 */     // GIR_Coverage, 139,
     /* 203330 */     GIR_EraseRootFromParent_Done,
     /* 203331 */   // Label 3802: @203331
     /* 203331 */   GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(203368), // Rule ID 2403 //
     /* 203336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b16),
     /* 203344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203357 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2161:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
     /* 203360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203366 */     GIR_RootConstrainSelectedInstOperands,
     /* 203367 */     // GIR_Coverage, 2403,
     /* 203367 */     GIR_EraseRootFromParent_Done,
     /* 203368 */   // Label 3803: @203368
     /* 203368 */   GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(203405), // Rule ID 2404 //
     /* 203373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b32),
     /* 203381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203394 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2162:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
     /* 203397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203401 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203403 */     GIR_RootConstrainSelectedInstOperands,
     /* 203404 */     // GIR_Coverage, 2404,
     /* 203404 */     GIR_EraseRootFromParent_Done,
     /* 203405 */   // Label 3804: @203405
     /* 203405 */   GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(203442), // Rule ID 2405 //
     /* 203410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b64),
     /* 203418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203424 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203431 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2163:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
     /* 203434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203436 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203438 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203440 */     GIR_RootConstrainSelectedInstOperands,
     /* 203441 */     // GIR_Coverage, 2405,
     /* 203441 */     GIR_EraseRootFromParent_Done,
     /* 203442 */   // Label 3805: @203442
     /* 203442 */   GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(203479), // Rule ID 2407 //
     /* 203447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b16),
     /* 203455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203468 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2166:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
     /* 203471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203477 */     GIR_RootConstrainSelectedInstOperands,
     /* 203478 */     // GIR_Coverage, 2407,
     /* 203478 */     GIR_EraseRootFromParent_Done,
     /* 203479 */   // Label 3806: @203479
     /* 203479 */   GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(203516), // Rule ID 2408 //
     /* 203484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b32),
     /* 203492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203505 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2167:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
     /* 203508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203514 */     GIR_RootConstrainSelectedInstOperands,
     /* 203515 */     // GIR_Coverage, 2408,
     /* 203515 */     GIR_EraseRootFromParent_Done,
     /* 203516 */   // Label 3807: @203516
     /* 203516 */   GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(203553), // Rule ID 2409 //
     /* 203521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203524 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b64),
     /* 203529 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203532 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203535 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203542 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2168:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
     /* 203545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203551 */     GIR_RootConstrainSelectedInstOperands,
     /* 203552 */     // GIR_Coverage, 2409,
     /* 203552 */     GIR_EraseRootFromParent_Done,
     /* 203553 */   // Label 3808: @203553
     /* 203553 */   GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(203590), // Rule ID 2411 //
     /* 203558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b16),
     /* 203566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203579 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2087:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 203582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203588 */     GIR_RootConstrainSelectedInstOperands,
     /* 203589 */     // GIR_Coverage, 2411,
     /* 203589 */     GIR_EraseRootFromParent_Done,
     /* 203590 */   // Label 3809: @203590
     /* 203590 */   GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(203627), // Rule ID 2412 //
     /* 203595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b32),
     /* 203603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203616 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2088:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 203619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203621 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203623 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203625 */     GIR_RootConstrainSelectedInstOperands,
     /* 203626 */     // GIR_Coverage, 2412,
     /* 203626 */     GIR_EraseRootFromParent_Done,
     /* 203627 */   // Label 3810: @203627
     /* 203627 */   GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(203664), // Rule ID 2413 //
     /* 203632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b64),
     /* 203640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203653 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2089:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 203656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203662 */     GIR_RootConstrainSelectedInstOperands,
     /* 203663 */     // GIR_Coverage, 2413,
     /* 203663 */     GIR_EraseRootFromParent_Done,
     /* 203664 */   // Label 3811: @203664
     /* 203664 */   GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(203701), // Rule ID 2415 //
     /* 203669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b16),
     /* 203677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203690 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2092:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
     /* 203693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203697 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203699 */     GIR_RootConstrainSelectedInstOperands,
     /* 203700 */     // GIR_Coverage, 2415,
     /* 203700 */     GIR_EraseRootFromParent_Done,
     /* 203701 */   // Label 3812: @203701
     /* 203701 */   GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(203738), // Rule ID 2416 //
     /* 203706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b32),
     /* 203714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203727 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2093:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
     /* 203730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203736 */     GIR_RootConstrainSelectedInstOperands,
     /* 203737 */     // GIR_Coverage, 2416,
     /* 203737 */     GIR_EraseRootFromParent_Done,
     /* 203738 */   // Label 3813: @203738
     /* 203738 */   GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(203775), // Rule ID 2417 //
     /* 203743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b64),
     /* 203751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203764 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2094:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
     /* 203767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203769 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203771 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203773 */     GIR_RootConstrainSelectedInstOperands,
     /* 203774 */     // GIR_Coverage, 2417,
     /* 203774 */     GIR_EraseRootFromParent_Done,
     /* 203775 */   // Label 3814: @203775
     /* 203775 */   GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(203812), // Rule ID 2419 //
     /* 203780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b16),
     /* 203788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203801 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1931:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
     /* 203804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203810 */     GIR_RootConstrainSelectedInstOperands,
     /* 203811 */     // GIR_Coverage, 2419,
     /* 203811 */     GIR_EraseRootFromParent_Done,
     /* 203812 */   // Label 3815: @203812
     /* 203812 */   GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(203849), // Rule ID 2420 //
     /* 203817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b32),
     /* 203825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203838 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1932:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
     /* 203841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203847 */     GIR_RootConstrainSelectedInstOperands,
     /* 203848 */     // GIR_Coverage, 2420,
     /* 203848 */     GIR_EraseRootFromParent_Done,
     /* 203849 */   // Label 3816: @203849
     /* 203849 */   GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(203886), // Rule ID 2421 //
     /* 203854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b64),
     /* 203862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203875 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1933:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
     /* 203878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203882 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203884 */     GIR_RootConstrainSelectedInstOperands,
     /* 203885 */     // GIR_Coverage, 2421,
     /* 203885 */     GIR_EraseRootFromParent_Done,
     /* 203886 */   // Label 3817: @203886
     /* 203886 */   GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(203923), // Rule ID 2423 //
     /* 203891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b16),
     /* 203899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203912 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1936:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
     /* 203915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203921 */     GIR_RootConstrainSelectedInstOperands,
     /* 203922 */     // GIR_Coverage, 2423,
     /* 203922 */     GIR_EraseRootFromParent_Done,
     /* 203923 */   // Label 3818: @203923
     /* 203923 */   GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(203960), // Rule ID 2424 //
     /* 203928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b32),
     /* 203936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203949 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1937:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
     /* 203952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203958 */     GIR_RootConstrainSelectedInstOperands,
     /* 203959 */     // GIR_Coverage, 2424,
     /* 203959 */     GIR_EraseRootFromParent_Done,
     /* 203960 */   // Label 3819: @203960
     /* 203960 */   GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(203997), // Rule ID 2425 //
     /* 203965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 203968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b64),
     /* 203973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 203976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 203979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 203982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 203986 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1938:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 203986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
     /* 203989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 203991 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 203993 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 203995 */     GIR_RootConstrainSelectedInstOperands,
     /* 203996 */     // GIR_Coverage, 2425,
     /* 203996 */     GIR_EraseRootFromParent_Done,
     /* 203997 */   // Label 3820: @203997
     /* 203997 */   GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(204034), // Rule ID 2426 //
     /* 204002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 204005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histseg),
     /* 204010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 204013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 204019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204023 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1556:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (HISTSEG_ZZZ:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)
     /* 204023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTSEG_ZZZ),
     /* 204026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 204030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 204032 */     GIR_RootConstrainSelectedInstOperands,
     /* 204033 */     // GIR_Coverage, 2426,
     /* 204033 */     GIR_EraseRootFromParent_Done,
     /* 204034 */   // Label 3821: @204034
     /* 204034 */   GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(204074), // Rule ID 2621 //
     /* 204039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pfirst),
     /* 204047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 204050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 204053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 204056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204060 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1635:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (PFIRST_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 204060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PFIRST_B),
     /* 204063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 204065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204069 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 204072 */     GIR_RootConstrainSelectedInstOperands,
     /* 204073 */     // GIR_Coverage, 2621,
     /* 204073 */     GIR_EraseRootFromParent_Done,
     /* 204074 */   // Label 3822: @204074
     /* 204074 */   GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(204114), // Rule ID 2622 //
     /* 204079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 204087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 204090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 204093 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 204096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204100 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1643:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (PNEXT_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 204100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_B),
     /* 204103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 204105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204109 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 204112 */     GIR_RootConstrainSelectedInstOperands,
     /* 204113 */     // GIR_Coverage, 2622,
     /* 204113 */     GIR_EraseRootFromParent_Done,
     /* 204114 */   // Label 3823: @204114
     /* 204114 */   GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(204154), // Rule ID 2623 //
     /* 204119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 204127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 204130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 204133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 204136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204140 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1643:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (PNEXT_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 204140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_H),
     /* 204143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 204145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204147 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204149 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 204152 */     GIR_RootConstrainSelectedInstOperands,
     /* 204153 */     // GIR_Coverage, 2623,
     /* 204153 */     GIR_EraseRootFromParent_Done,
     /* 204154 */   // Label 3824: @204154
     /* 204154 */   GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(204194), // Rule ID 2624 //
     /* 204159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 204167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 204170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 204173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 204176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204180 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1643:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (PNEXT_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 204180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_S),
     /* 204183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 204185 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204187 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204189 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 204192 */     GIR_RootConstrainSelectedInstOperands,
     /* 204193 */     // GIR_Coverage, 2624,
     /* 204193 */     GIR_EraseRootFromParent_Done,
     /* 204194 */   // Label 3825: @204194
     /* 204194 */   GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(204234), // Rule ID 2625 //
     /* 204199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 204207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 204210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 204213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 204216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204220 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1643:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (PNEXT_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 204220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_D),
     /* 204223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 204225 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204227 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204229 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 204232 */     GIR_RootConstrainSelectedInstOperands,
     /* 204233 */     // GIR_Coverage, 2625,
     /* 204233 */     GIR_EraseRootFromParent_Done,
     /* 204234 */   // Label 3826: @204234
     /* 204234 */   GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(204271), // Rule ID 2642 //
     /* 204239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 204247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 204250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 204253 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 204256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204260 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1823:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 204260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_H),
     /* 204263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 204265 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204267 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204269 */     GIR_RootConstrainSelectedInstOperands,
     /* 204270 */     // GIR_Coverage, 2642,
     /* 204270 */     GIR_EraseRootFromParent_Done,
     /* 204271 */   // Label 3827: @204271
     /* 204271 */   GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(204308), // Rule ID 2643 //
     /* 204276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 204284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 204287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 204293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204297 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1823:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 204297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_S),
     /* 204300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 204302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204306 */     GIR_RootConstrainSelectedInstOperands,
     /* 204307 */     // GIR_Coverage, 2643,
     /* 204307 */     GIR_EraseRootFromParent_Done,
     /* 204308 */   // Label 3828: @204308
     /* 204308 */   GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(204345), // Rule ID 2644 //
     /* 204313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 204321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 204324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 204327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 204330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204334 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1823:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 204334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_D),
     /* 204337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 204339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204343 */     GIR_RootConstrainSelectedInstOperands,
     /* 204344 */     // GIR_Coverage, 2644,
     /* 204344 */     GIR_EraseRootFromParent_Done,
     /* 204345 */   // Label 3829: @204345
     /* 204345 */   GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(204382), // Rule ID 2645 //
     /* 204350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 204358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 204361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 204364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 204367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 204371 */     // (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (CNTP_XPP_B:{ *:[i64] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 204371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_B),
     /* 204374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204378 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204380 */     GIR_RootConstrainSelectedInstOperands,
     /* 204381 */     // GIR_Coverage, 2645,
     /* 204381 */     GIR_EraseRootFromParent_Done,
     /* 204382 */   // Label 3830: @204382
     /* 204382 */   GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(204419), // Rule ID 2646 //
     /* 204387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 204395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 204398 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 204401 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 204404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 204408 */     // (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (CNTP_XPP_H:{ *:[i64] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 204408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_H),
     /* 204411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204417 */     GIR_RootConstrainSelectedInstOperands,
     /* 204418 */     // GIR_Coverage, 2646,
     /* 204418 */     GIR_EraseRootFromParent_Done,
     /* 204419 */   // Label 3831: @204419
     /* 204419 */   GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(204456), // Rule ID 2647 //
     /* 204424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 204432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 204435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 204438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 204441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 204445 */     // (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (CNTP_XPP_S:{ *:[i64] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 204445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_S),
     /* 204448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204454 */     GIR_RootConstrainSelectedInstOperands,
     /* 204455 */     // GIR_Coverage, 2647,
     /* 204455 */     GIR_EraseRootFromParent_Done,
     /* 204456 */   // Label 3832: @204456
     /* 204456 */   GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(204493), // Rule ID 2648 //
     /* 204461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 204464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 204469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 204472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 204475 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 204478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 204482 */     // (intrinsic_wo_chain:{ *:[i64] } 1345:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (CNTP_XPP_D:{ *:[i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 204482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_D),
     /* 204485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204491 */     GIR_RootConstrainSelectedInstOperands,
     /* 204492 */     // GIR_Coverage, 2648,
     /* 204492 */     GIR_EraseRootFromParent_Done,
     /* 204493 */   // Label 3833: @204493
     /* 204493 */   GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(204530), // Rule ID 2826 //
     /* 204498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 204501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 204506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 204509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 204512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 204515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204519 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1553:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (FTSMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 204519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_H),
     /* 204522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204528 */     GIR_RootConstrainSelectedInstOperands,
     /* 204529 */     // GIR_Coverage, 2826,
     /* 204529 */     GIR_EraseRootFromParent_Done,
     /* 204530 */   // Label 3834: @204530
     /* 204530 */   GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(204567), // Rule ID 2827 //
     /* 204535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 204538 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 204543 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 204546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204549 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 204552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204556 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1553:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (FTSMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 204556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_S),
     /* 204559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204563 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204565 */     GIR_RootConstrainSelectedInstOperands,
     /* 204566 */     // GIR_Coverage, 2827,
     /* 204566 */     GIR_EraseRootFromParent_Done,
     /* 204567 */   // Label 3835: @204567
     /* 204567 */   GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(204604), // Rule ID 2828 //
     /* 204572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 204575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 204580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 204583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 204586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 204589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204593 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1553:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (FTSMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 204593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_D),
     /* 204596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204602 */     GIR_RootConstrainSelectedInstOperands,
     /* 204603 */     // GIR_Coverage, 2828,
     /* 204603 */     GIR_EraseRootFromParent_Done,
     /* 204604 */   // Label 3836: @204604
     /* 204604 */   GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(204641), // Rule ID 3014 //
     /* 204609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 204617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 204620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 204626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204630 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1805:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 204630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_B),
     /* 204633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204637 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204639 */     GIR_RootConstrainSelectedInstOperands,
     /* 204640 */     // GIR_Coverage, 3014,
     /* 204640 */     GIR_EraseRootFromParent_Done,
     /* 204641 */   // Label 3837: @204641
     /* 204641 */   GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(204678), // Rule ID 3015 //
     /* 204646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 204654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 204657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 204660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 204663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204667 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1805:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 204667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_H),
     /* 204670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204676 */     GIR_RootConstrainSelectedInstOperands,
     /* 204677 */     // GIR_Coverage, 3015,
     /* 204677 */     GIR_EraseRootFromParent_Done,
     /* 204678 */   // Label 3838: @204678
     /* 204678 */   GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(204715), // Rule ID 3016 //
     /* 204683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 204691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 204694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204697 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 204700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204704 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1805:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 204704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_S),
     /* 204707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204713 */     GIR_RootConstrainSelectedInstOperands,
     /* 204714 */     // GIR_Coverage, 3016,
     /* 204714 */     GIR_EraseRootFromParent_Done,
     /* 204715 */   // Label 3839: @204715
     /* 204715 */   GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(204752), // Rule ID 3017 //
     /* 204720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 204728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 204731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 204734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 204737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204741 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1805:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 204741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_D),
     /* 204744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204750 */     GIR_RootConstrainSelectedInstOperands,
     /* 204751 */     // GIR_Coverage, 3017,
     /* 204751 */     GIR_EraseRootFromParent_Done,
     /* 204752 */   // Label 3840: @204752
     /* 204752 */   GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(204789), // Rule ID 3018 //
     /* 204757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmul),
     /* 204765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 204768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 204774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204778 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1640:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMUL_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 204778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMUL_ZZZ_B),
     /* 204781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204787 */     GIR_RootConstrainSelectedInstOperands,
     /* 204788 */     // GIR_Coverage, 3018,
     /* 204788 */     GIR_EraseRootFromParent_Done,
     /* 204789 */   // Label 3841: @204789
     /* 204789 */   GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(204826), // Rule ID 3040 //
     /* 204794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 204802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 204805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 204811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204815 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1698:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 204815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_H),
     /* 204818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204822 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204824 */     GIR_RootConstrainSelectedInstOperands,
     /* 204825 */     // GIR_Coverage, 3040,
     /* 204825 */     GIR_EraseRootFromParent_Done,
     /* 204826 */   // Label 3842: @204826
     /* 204826 */   GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(204863), // Rule ID 3041 //
     /* 204831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 204839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 204842 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 204845 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 204848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204852 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1698:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 204852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_S),
     /* 204855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204859 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204861 */     GIR_RootConstrainSelectedInstOperands,
     /* 204862 */     // GIR_Coverage, 3041,
     /* 204862 */     GIR_EraseRootFromParent_Done,
     /* 204863 */   // Label 3843: @204863
     /* 204863 */   GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(204900), // Rule ID 3042 //
     /* 204868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 204876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 204879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 204885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204889 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1698:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 204889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_D),
     /* 204892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204898 */     GIR_RootConstrainSelectedInstOperands,
     /* 204899 */     // GIR_Coverage, 3042,
     /* 204899 */     GIR_EraseRootFromParent_Done,
     /* 204900 */   // Label 3844: @204900
     /* 204900 */   GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(204937), // Rule ID 3046 //
     /* 204905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 204908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 204913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 204916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 204919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 204922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204926 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1641:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (PMULLB_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 204926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_Q),
     /* 204929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204933 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204935 */     GIR_RootConstrainSelectedInstOperands,
     /* 204936 */     // GIR_Coverage, 3046,
     /* 204936 */     GIR_EraseRootFromParent_Done,
     /* 204937 */   // Label 3845: @204937
     /* 204937 */   GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(204974), // Rule ID 3047 //
     /* 204942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 204950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 204953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 204959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204963 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1641:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMULLB_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 204963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_H),
     /* 204966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 204968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 204970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 204972 */     GIR_RootConstrainSelectedInstOperands,
     /* 204973 */     // GIR_Coverage, 3047,
     /* 204973 */     GIR_EraseRootFromParent_Done,
     /* 204974 */   // Label 3846: @204974
     /* 204974 */   GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(205011), // Rule ID 3048 //
     /* 204979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 204982 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 204987 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 204990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204993 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 204996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205000 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1641:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (PMULLB_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_D),
     /* 205003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205005 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205007 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205009 */     GIR_RootConstrainSelectedInstOperands,
     /* 205010 */     // GIR_Coverage, 3048,
     /* 205010 */     GIR_EraseRootFromParent_Done,
     /* 205011 */   // Label 3847: @205011
     /* 205011 */   GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(205048), // Rule ID 3049 //
     /* 205016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 205019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 205024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 205027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 205030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 205033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205037 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1283:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BEXT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 205037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_B),
     /* 205040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205042 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205044 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205046 */     GIR_RootConstrainSelectedInstOperands,
     /* 205047 */     // GIR_Coverage, 3049,
     /* 205047 */     GIR_EraseRootFromParent_Done,
     /* 205048 */   // Label 3848: @205048
     /* 205048 */   GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(205085), // Rule ID 3050 //
     /* 205053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 205056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 205061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 205064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 205067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 205070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205074 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1283:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BEXT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 205074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_H),
     /* 205077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205079 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205081 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205083 */     GIR_RootConstrainSelectedInstOperands,
     /* 205084 */     // GIR_Coverage, 3050,
     /* 205084 */     GIR_EraseRootFromParent_Done,
     /* 205085 */   // Label 3849: @205085
     /* 205085 */   GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(205122), // Rule ID 3051 //
     /* 205090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 205093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 205098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 205104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205111 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1283:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BEXT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_S),
     /* 205114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205116 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205118 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205120 */     GIR_RootConstrainSelectedInstOperands,
     /* 205121 */     // GIR_Coverage, 3051,
     /* 205121 */     GIR_EraseRootFromParent_Done,
     /* 205122 */   // Label 3850: @205122
     /* 205122 */   GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(205159), // Rule ID 3052 //
     /* 205127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 205130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 205135 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 205138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 205141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 205144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205148 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1283:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BEXT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 205148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_D),
     /* 205151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205155 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205157 */     GIR_RootConstrainSelectedInstOperands,
     /* 205158 */     // GIR_Coverage, 3052,
     /* 205158 */     GIR_EraseRootFromParent_Done,
     /* 205159 */   // Label 3851: @205159
     /* 205159 */   GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(205196), // Rule ID 3053 //
     /* 205164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 205172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 205175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 205178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 205181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205185 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1699:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 205185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_H),
     /* 205188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205194 */     GIR_RootConstrainSelectedInstOperands,
     /* 205195 */     // GIR_Coverage, 3053,
     /* 205195 */     GIR_EraseRootFromParent_Done,
     /* 205196 */   // Label 3852: @205196
     /* 205196 */   GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(205233), // Rule ID 3054 //
     /* 205201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 205209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 205215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 205218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205222 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1699:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 205222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_S),
     /* 205225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205227 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205231 */     GIR_RootConstrainSelectedInstOperands,
     /* 205232 */     // GIR_Coverage, 3054,
     /* 205232 */     GIR_EraseRootFromParent_Done,
     /* 205233 */   // Label 3853: @205233
     /* 205233 */   GIM_Try, /*On fail goto*//*Label 3854*/ GIMT_Encode4(205270), // Rule ID 3055 //
     /* 205238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 205246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 205249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 205252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205259 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1699:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_D),
     /* 205262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205268 */     GIR_RootConstrainSelectedInstOperands,
     /* 205269 */     // GIR_Coverage, 3055,
     /* 205269 */     GIR_EraseRootFromParent_Done,
     /* 205270 */   // Label 3854: @205270
     /* 205270 */   GIM_Try, /*On fail goto*//*Label 3855*/ GIMT_Encode4(205307), // Rule ID 3102 //
     /* 205275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 205283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 205286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 205289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 205292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205296 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1260:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 205296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_B),
     /* 205299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205303 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205305 */     GIR_RootConstrainSelectedInstOperands,
     /* 205306 */     // GIR_Coverage, 3102,
     /* 205306 */     GIR_EraseRootFromParent_Done,
     /* 205307 */   // Label 3855: @205307
     /* 205307 */   GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(205344), // Rule ID 3103 //
     /* 205312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 205320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 205323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 205326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205333 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1260:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_H),
     /* 205336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205342 */     GIR_RootConstrainSelectedInstOperands,
     /* 205343 */     // GIR_Coverage, 3103,
     /* 205343 */     GIR_EraseRootFromParent_Done,
     /* 205344 */   // Label 3856: @205344
     /* 205344 */   GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(205381), // Rule ID 3104 //
     /* 205349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 205357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 205363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 205366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205370 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1260:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 205370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_S),
     /* 205373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205375 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205377 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205379 */     GIR_RootConstrainSelectedInstOperands,
     /* 205380 */     // GIR_Coverage, 3104,
     /* 205380 */     GIR_EraseRootFromParent_Done,
     /* 205381 */   // Label 3857: @205381
     /* 205381 */   GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(205418), // Rule ID 3111 //
     /* 205386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 205394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 205397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 205400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 205403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205407 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1862:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 205407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_B),
     /* 205410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205412 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205414 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205416 */     GIR_RootConstrainSelectedInstOperands,
     /* 205417 */     // GIR_Coverage, 3111,
     /* 205417 */     GIR_EraseRootFromParent_Done,
     /* 205418 */   // Label 3858: @205418
     /* 205418 */   GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(205455), // Rule ID 3112 //
     /* 205423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 205431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 205434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 205437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205444 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1862:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_H),
     /* 205447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205451 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205453 */     GIR_RootConstrainSelectedInstOperands,
     /* 205454 */     // GIR_Coverage, 3112,
     /* 205454 */     GIR_EraseRootFromParent_Done,
     /* 205455 */   // Label 3859: @205455
     /* 205455 */   GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(205492), // Rule ID 3113 //
     /* 205460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 205463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 205468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 205474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 205477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205481 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1862:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 205481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_S),
     /* 205484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205490 */     GIR_RootConstrainSelectedInstOperands,
     /* 205491 */     // GIR_Coverage, 3113,
     /* 205491 */     GIR_EraseRootFromParent_Done,
     /* 205492 */   // Label 3860: @205492
     /* 205492 */   GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(205532), // Rule ID 3221 //
     /* 205497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 205508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 205514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205518 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2142:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 205518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_B),
     /* 205521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205523 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205525 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205527 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205530 */     GIR_RootConstrainSelectedInstOperands,
     /* 205531 */     // GIR_Coverage, 3221,
     /* 205531 */     GIR_EraseRootFromParent_Done,
     /* 205532 */   // Label 3861: @205532
     /* 205532 */   GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(205572), // Rule ID 3222 //
     /* 205537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 205548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 205554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205558 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2142:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 205558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_H),
     /* 205561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205567 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205570 */     GIR_RootConstrainSelectedInstOperands,
     /* 205571 */     // GIR_Coverage, 3222,
     /* 205571 */     GIR_EraseRootFromParent_Done,
     /* 205572 */   // Label 3862: @205572
     /* 205572 */   GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(205612), // Rule ID 3223 //
     /* 205577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 205588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 205594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205598 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2142:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 205598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_S),
     /* 205601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205607 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205610 */     GIR_RootConstrainSelectedInstOperands,
     /* 205611 */     // GIR_Coverage, 3223,
     /* 205611 */     GIR_EraseRootFromParent_Done,
     /* 205612 */   // Label 3863: @205612
     /* 205612 */   GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(205652), // Rule ID 3224 //
     /* 205617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 205628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 205634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205638 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2142:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 205638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_D),
     /* 205641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205645 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205647 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205650 */     GIR_RootConstrainSelectedInstOperands,
     /* 205651 */     // GIR_Coverage, 3224,
     /* 205651 */     GIR_EraseRootFromParent_Done,
     /* 205652 */   // Label 3864: @205652
     /* 205652 */   GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(205692), // Rule ID 3229 //
     /* 205657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 205668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 205674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205678 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2142:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 205678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_B),
     /* 205681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205683 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205685 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205687 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205690 */     GIR_RootConstrainSelectedInstOperands,
     /* 205691 */     // GIR_Coverage, 3229,
     /* 205691 */     GIR_EraseRootFromParent_Done,
     /* 205692 */   // Label 3865: @205692
     /* 205692 */   GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(205732), // Rule ID 3230 //
     /* 205697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 205708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 205714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205718 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2142:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 205718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_H),
     /* 205721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205727 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205730 */     GIR_RootConstrainSelectedInstOperands,
     /* 205731 */     // GIR_Coverage, 3230,
     /* 205731 */     GIR_EraseRootFromParent_Done,
     /* 205732 */   // Label 3866: @205732
     /* 205732 */   GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(205772), // Rule ID 3231 //
     /* 205737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 205748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 205754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205758 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2142:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 205758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_S),
     /* 205761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205767 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205770 */     GIR_RootConstrainSelectedInstOperands,
     /* 205771 */     // GIR_Coverage, 3231,
     /* 205771 */     GIR_EraseRootFromParent_Done,
     /* 205772 */   // Label 3867: @205772
     /* 205772 */   GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(205812), // Rule ID 3232 //
     /* 205777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 205780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 205785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 205788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 205794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205798 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2142:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 205798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_D),
     /* 205801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205803 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205805 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205807 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 205810 */     GIR_RootConstrainSelectedInstOperands,
     /* 205811 */     // GIR_Coverage, 3232,
     /* 205811 */     GIR_EraseRootFromParent_Done,
     /* 205812 */   // Label 3868: @205812
     /* 205812 */   GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(205849), // Rule ID 3421 //
     /* 205817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 205820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 205825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 205831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205838 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1351:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (COMPACT_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 205838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
     /* 205841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205847 */     GIR_RootConstrainSelectedInstOperands,
     /* 205848 */     // GIR_Coverage, 3421,
     /* 205848 */     GIR_EraseRootFromParent_Done,
     /* 205849 */   // Label 3869: @205849
     /* 205849 */   GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(205886), // Rule ID 3422 //
     /* 205854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 205857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 205862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 205865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 205868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 205871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205875 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1351:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (COMPACT_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 205875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
     /* 205878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205882 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205884 */     GIR_RootConstrainSelectedInstOperands,
     /* 205885 */     // GIR_Coverage, 3422,
     /* 205885 */     GIR_EraseRootFromParent_Done,
     /* 205886 */   // Label 3870: @205886
     /* 205886 */   GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(205923), // Rule ID 3423 //
     /* 205891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 205894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 205899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 205902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 205905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 205908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205912 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1351:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (COMPACT_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 205912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
     /* 205915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205921 */     GIR_RootConstrainSelectedInstOperands,
     /* 205922 */     // GIR_Coverage, 3423,
     /* 205922 */     GIR_EraseRootFromParent_Done,
     /* 205923 */   // Label 3871: @205923
     /* 205923 */   GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(205960), // Rule ID 3424 //
     /* 205928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 205931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 205936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 205939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 205942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 205945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205949 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1351:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (COMPACT_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 205949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
     /* 205952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205958 */     GIR_RootConstrainSelectedInstOperands,
     /* 205959 */     // GIR_Coverage, 3424,
     /* 205959 */     GIR_EraseRootFromParent_Done,
     /* 205960 */   // Label 3872: @205960
     /* 205960 */   GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(205997), // Rule ID 3425 //
     /* 205965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 205968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 205973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 205976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 205979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 205982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205986 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1351:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (COMPACT_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 205986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_B),
     /* 205989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 205991 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 205993 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 205995 */     GIR_RootConstrainSelectedInstOperands,
     /* 205996 */     // GIR_Coverage, 3425,
     /* 205996 */     GIR_EraseRootFromParent_Done,
     /* 205997 */   // Label 3873: @205997
     /* 205997 */   GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(206034), // Rule ID 3426 //
     /* 206002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 206005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 206010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 206016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206023 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1351:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (COMPACT_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 206023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_H),
     /* 206026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206032 */     GIR_RootConstrainSelectedInstOperands,
     /* 206033 */     // GIR_Coverage, 3426,
     /* 206033 */     GIR_EraseRootFromParent_Done,
     /* 206034 */   // Label 3874: @206034
     /* 206034 */   GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(206071), // Rule ID 3427 //
     /* 206039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 206042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 206047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 206053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206060 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1351:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (COMPACT_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 206060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_H),
     /* 206063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206069 */     GIR_RootConstrainSelectedInstOperands,
     /* 206070 */     // GIR_Coverage, 3427,
     /* 206070 */     GIR_EraseRootFromParent_Done,
     /* 206071 */   // Label 3875: @206071
     /* 206071 */   GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(206108), // Rule ID 3449 //
     /* 206076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 206079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 206084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206097 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1554:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (FTSSEL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 206097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_H),
     /* 206100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206106 */     GIR_RootConstrainSelectedInstOperands,
     /* 206107 */     // GIR_Coverage, 3449,
     /* 206107 */     GIR_EraseRootFromParent_Done,
     /* 206108 */   // Label 3876: @206108
     /* 206108 */   GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(206145), // Rule ID 3450 //
     /* 206113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 206116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 206121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206134 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1554:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (FTSSEL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 206134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_S),
     /* 206137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206139 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206141 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206143 */     GIR_RootConstrainSelectedInstOperands,
     /* 206144 */     // GIR_Coverage, 3450,
     /* 206144 */     GIR_EraseRootFromParent_Done,
     /* 206145 */   // Label 3877: @206145
     /* 206145 */   GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(206182), // Rule ID 3451 //
     /* 206150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 206153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 206158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206171 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1554:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (FTSSEL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 206171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_D),
     /* 206174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206178 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206180 */     GIR_RootConstrainSelectedInstOperands,
     /* 206181 */     // GIR_Coverage, 3451,
     /* 206181 */     GIR_EraseRootFromParent_Done,
     /* 206182 */   // Label 3878: @206182
     /* 206182 */   GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(206219), // Rule ID 3473 //
     /* 206187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 206190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka_z),
     /* 206195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 206198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 206201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 206204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 206208 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1304:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (BRKA_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 206208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPzP),
     /* 206211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 206213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206215 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206217 */     GIR_RootConstrainSelectedInstOperands,
     /* 206218 */     // GIR_Coverage, 3473,
     /* 206218 */     GIR_EraseRootFromParent_Done,
     /* 206219 */   // Label 3879: @206219
     /* 206219 */   GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(206256), // Rule ID 3478 //
     /* 206224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVESM4),
     /* 206227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4ekey),
     /* 206232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206245 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1734:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SM4EKEY_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 206245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4EKEY_ZZZ_S),
     /* 206248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206254 */     GIR_RootConstrainSelectedInstOperands,
     /* 206255 */     // GIR_Coverage, 3478,
     /* 206255 */     GIR_EraseRootFromParent_Done,
     /* 206256 */   // Label 3880: @206256
     /* 206256 */   GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(206293), // Rule ID 3487 //
     /* 206261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 206272 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 206275 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 206278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206282 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2164:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 206282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206291 */     GIR_RootConstrainSelectedInstOperands,
     /* 206292 */     // GIR_Coverage, 3487,
     /* 206292 */     GIR_EraseRootFromParent_Done,
     /* 206293 */   // Label 3881: @206293
     /* 206293 */   GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(206330), // Rule ID 3488 //
     /* 206298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206319 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2164:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 206319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206328 */     GIR_RootConstrainSelectedInstOperands,
     /* 206329 */     // GIR_Coverage, 3488,
     /* 206329 */     GIR_EraseRootFromParent_Done,
     /* 206330 */   // Label 3882: @206330
     /* 206330 */   GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(206367), // Rule ID 3489 //
     /* 206335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206346 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206349 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206356 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2164:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 206356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206363 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206365 */     GIR_RootConstrainSelectedInstOperands,
     /* 206366 */     // GIR_Coverage, 3489,
     /* 206366 */     GIR_EraseRootFromParent_Done,
     /* 206367 */   // Label 3883: @206367
     /* 206367 */   GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(206404), // Rule ID 3490 //
     /* 206372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206393 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2164:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 206393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206400 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206402 */     GIR_RootConstrainSelectedInstOperands,
     /* 206403 */     // GIR_Coverage, 3490,
     /* 206403 */     GIR_EraseRootFromParent_Done,
     /* 206404 */   // Label 3884: @206404
     /* 206404 */   GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(206441), // Rule ID 3491 //
     /* 206409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206430 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2164:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 206430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206437 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206439 */     GIR_RootConstrainSelectedInstOperands,
     /* 206440 */     // GIR_Coverage, 3491,
     /* 206440 */     GIR_EraseRootFromParent_Done,
     /* 206441 */   // Label 3885: @206441
     /* 206441 */   GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(206478), // Rule ID 3492 //
     /* 206446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206467 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2164:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 206467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206474 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206476 */     GIR_RootConstrainSelectedInstOperands,
     /* 206477 */     // GIR_Coverage, 3492,
     /* 206477 */     GIR_EraseRootFromParent_Done,
     /* 206478 */   // Label 3886: @206478
     /* 206478 */   GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(206515), // Rule ID 3493 //
     /* 206483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 206486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 206491 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206497 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206504 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2164:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 206504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 206507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206509 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206511 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206513 */     GIR_RootConstrainSelectedInstOperands,
     /* 206514 */     // GIR_Coverage, 3493,
     /* 206514 */     GIR_EraseRootFromParent_Done,
     /* 206515 */   // Label 3887: @206515
     /* 206515 */   GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(206552), // Rule ID 3554 //
     /* 206520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 206528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 206531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 206534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206541 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1377:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FADDQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 206541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_H),
     /* 206544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206548 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206550 */     GIR_RootConstrainSelectedInstOperands,
     /* 206551 */     // GIR_Coverage, 3554,
     /* 206551 */     GIR_EraseRootFromParent_Done,
     /* 206552 */   // Label 3888: @206552
     /* 206552 */   GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(206589), // Rule ID 3555 //
     /* 206557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 206565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 206568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 206571 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206578 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1377:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FADDQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 206578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_S),
     /* 206581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206583 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206585 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206587 */     GIR_RootConstrainSelectedInstOperands,
     /* 206588 */     // GIR_Coverage, 3555,
     /* 206588 */     GIR_EraseRootFromParent_Done,
     /* 206589 */   // Label 3889: @206589
     /* 206589 */   GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(206626), // Rule ID 3556 //
     /* 206594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 206602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 206605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 206608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206615 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1377:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FADDQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 206615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_D),
     /* 206618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206620 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206622 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206624 */     GIR_RootConstrainSelectedInstOperands,
     /* 206625 */     // GIR_Coverage, 3556,
     /* 206625 */     GIR_EraseRootFromParent_Done,
     /* 206626 */   // Label 3890: @206626
     /* 206626 */   GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(206663), // Rule ID 3586 //
     /* 206631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 206639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 206642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 206645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 206648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206652 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 206652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_B),
     /* 206655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206661 */     GIR_RootConstrainSelectedInstOperands,
     /* 206662 */     // GIR_Coverage, 3586,
     /* 206662 */     GIR_EraseRootFromParent_Done,
     /* 206663 */   // Label 3891: @206663
     /* 206663 */   GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(206700), // Rule ID 3587 //
     /* 206668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 206676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 206679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 206682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206689 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 206689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_H),
     /* 206692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206696 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206698 */     GIR_RootConstrainSelectedInstOperands,
     /* 206699 */     // GIR_Coverage, 3587,
     /* 206699 */     GIR_EraseRootFromParent_Done,
     /* 206700 */   // Label 3892: @206700
     /* 206700 */   GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(206737), // Rule ID 3588 //
     /* 206705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 206713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 206716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 206719 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206726 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 206726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_S),
     /* 206729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206731 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206733 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206735 */     GIR_RootConstrainSelectedInstOperands,
     /* 206736 */     // GIR_Coverage, 3588,
     /* 206736 */     GIR_EraseRootFromParent_Done,
     /* 206737 */   // Label 3893: @206737
     /* 206737 */   GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(206774), // Rule ID 3589 //
     /* 206742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 206750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 206753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 206756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 206763 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1628:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 206763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_D),
     /* 206766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 206768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206770 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206772 */     GIR_RootConstrainSelectedInstOperands,
     /* 206773 */     // GIR_Coverage, 3589,
     /* 206773 */     GIR_EraseRootFromParent_Done,
     /* 206774 */   // Label 3894: @206774
     /* 206774 */   GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(206811), // Rule ID 3590 //
     /* 206779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 206790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 206793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 206796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206800 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2172:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 206800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_B),
     /* 206803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206809 */     GIR_RootConstrainSelectedInstOperands,
     /* 206810 */     // GIR_Coverage, 3590,
     /* 206810 */     GIR_EraseRootFromParent_Done,
     /* 206811 */   // Label 3895: @206811
     /* 206811 */   GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(206848), // Rule ID 3591 //
     /* 206816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206837 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2172:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 206837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
     /* 206840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206844 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206846 */     GIR_RootConstrainSelectedInstOperands,
     /* 206847 */     // GIR_Coverage, 3591,
     /* 206847 */     GIR_EraseRootFromParent_Done,
     /* 206848 */   // Label 3896: @206848
     /* 206848 */   GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(206885), // Rule ID 3592 //
     /* 206853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206874 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2172:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 206874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
     /* 206877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206879 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206881 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206883 */     GIR_RootConstrainSelectedInstOperands,
     /* 206884 */     // GIR_Coverage, 3592,
     /* 206884 */     GIR_EraseRootFromParent_Done,
     /* 206885 */   // Label 3897: @206885
     /* 206885 */   GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(206922), // Rule ID 3593 //
     /* 206890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 206907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206911 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2172:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 206911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
     /* 206914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206916 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206918 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206920 */     GIR_RootConstrainSelectedInstOperands,
     /* 206921 */     // GIR_Coverage, 3593,
     /* 206921 */     GIR_EraseRootFromParent_Done,
     /* 206922 */   // Label 3898: @206922
     /* 206922 */   GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(206959), // Rule ID 3594 //
     /* 206927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 206944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206948 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2172:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 206948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
     /* 206951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206955 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206957 */     GIR_RootConstrainSelectedInstOperands,
     /* 206958 */     // GIR_Coverage, 3594,
     /* 206958 */     GIR_EraseRootFromParent_Done,
     /* 206959 */   // Label 3899: @206959
     /* 206959 */   GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(206996), // Rule ID 3595 //
     /* 206964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 206972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 206981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206985 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2172:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 206985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
     /* 206988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206990 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206992 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206994 */     GIR_RootConstrainSelectedInstOperands,
     /* 206995 */     // GIR_Coverage, 3595,
     /* 206995 */     GIR_EraseRootFromParent_Done,
     /* 206996 */   // Label 3900: @206996
     /* 206996 */   GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(207033), // Rule ID 3596 //
     /* 207001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 207009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207022 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2172:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 207022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
     /* 207025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207031 */     GIR_RootConstrainSelectedInstOperands,
     /* 207032 */     // GIR_Coverage, 3596,
     /* 207032 */     GIR_EraseRootFromParent_Done,
     /* 207033 */   // Label 3901: @207033
     /* 207033 */   GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(207070), // Rule ID 3597 //
     /* 207038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 207052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 207055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207059 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1927:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TBLQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 207059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_B),
     /* 207062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207068 */     GIR_RootConstrainSelectedInstOperands,
     /* 207069 */     // GIR_Coverage, 3597,
     /* 207069 */     GIR_EraseRootFromParent_Done,
     /* 207070 */   // Label 3902: @207070
     /* 207070 */   GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(207107), // Rule ID 3598 //
     /* 207075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 207092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207096 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1927:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TBLQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 207096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
     /* 207099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207101 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207103 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207105 */     GIR_RootConstrainSelectedInstOperands,
     /* 207106 */     // GIR_Coverage, 3598,
     /* 207106 */     GIR_EraseRootFromParent_Done,
     /* 207107 */   // Label 3903: @207107
     /* 207107 */   GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(207144), // Rule ID 3599 //
     /* 207112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207133 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1927:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TBLQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
     /* 207136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207138 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207140 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207142 */     GIR_RootConstrainSelectedInstOperands,
     /* 207143 */     // GIR_Coverage, 3599,
     /* 207143 */     GIR_EraseRootFromParent_Done,
     /* 207144 */   // Label 3904: @207144
     /* 207144 */   GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(207181), // Rule ID 3600 //
     /* 207149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207170 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1927:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TBLQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
     /* 207173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207177 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207179 */     GIR_RootConstrainSelectedInstOperands,
     /* 207180 */     // GIR_Coverage, 3600,
     /* 207180 */     GIR_EraseRootFromParent_Done,
     /* 207181 */   // Label 3905: @207181
     /* 207181 */   GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(207218), // Rule ID 3601 //
     /* 207186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207200 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 207203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207207 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1927:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TBLQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 207207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
     /* 207210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207214 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207216 */     GIR_RootConstrainSelectedInstOperands,
     /* 207217 */     // GIR_Coverage, 3601,
     /* 207217 */     GIR_EraseRootFromParent_Done,
     /* 207218 */   // Label 3906: @207218
     /* 207218 */   GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(207255), // Rule ID 3602 //
     /* 207223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207226 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207231 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207234 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207237 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207244 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1927:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TBLQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
     /* 207247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207253 */     GIR_RootConstrainSelectedInstOperands,
     /* 207254 */     // GIR_Coverage, 3602,
     /* 207254 */     GIR_EraseRootFromParent_Done,
     /* 207255 */   // Label 3907: @207255
     /* 207255 */   GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(207292), // Rule ID 3603 //
     /* 207260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 207263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 207268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207281 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1927:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TBLQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
     /* 207284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207286 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207288 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207290 */     GIR_RootConstrainSelectedInstOperands,
     /* 207291 */     // GIR_Coverage, 3603,
     /* 207291 */     GIR_EraseRootFromParent_Done,
     /* 207292 */   // Label 3908: @207292
     /* 207292 */   GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(207329), // Rule ID 8531 //
     /* 207297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb_z),
     /* 207305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 207308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 207311 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 207314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207318 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1306:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (BRKB_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 207318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPzP),
     /* 207321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207327 */     GIR_RootConstrainSelectedInstOperands,
     /* 207328 */     // GIR_Coverage, 8531,
     /* 207328 */     GIR_EraseRootFromParent_Done,
     /* 207329 */   // Label 3909: @207329
     /* 207329 */   GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(207366), // Rule ID 9007 //
     /* 207334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
     /* 207342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207355 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1264:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_0:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_0),
     /* 207358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207364 */     GIR_RootConstrainSelectedInstOperands,
     /* 207365 */     // GIR_Coverage, 9007,
     /* 207365 */     GIR_EraseRootFromParent_Done,
     /* 207366 */   // Label 3910: @207366
     /* 207366 */   GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(207403), // Rule ID 9008 //
     /* 207371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
     /* 207379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207392 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1266:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_1:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_1),
     /* 207395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207401 */     GIR_RootConstrainSelectedInstOperands,
     /* 207402 */     // GIR_Coverage, 9008,
     /* 207402 */     GIR_EraseRootFromParent_Done,
     /* 207403 */   // Label 3911: @207403
     /* 207403 */   GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(207440), // Rule ID 9009 //
     /* 207408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
     /* 207416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207429 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1267:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_2:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_2),
     /* 207432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207434 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207436 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207438 */     GIR_RootConstrainSelectedInstOperands,
     /* 207439 */     // GIR_Coverage, 9009,
     /* 207439 */     GIR_EraseRootFromParent_Done,
     /* 207440 */   // Label 3912: @207440
     /* 207440 */   GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(207477), // Rule ID 9010 //
     /* 207445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
     /* 207453 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207456 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207459 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 207462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207466 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1265:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_3:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 207466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_3),
     /* 207469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207475 */     GIR_RootConstrainSelectedInstOperands,
     /* 207476 */     // GIR_Coverage, 9010,
     /* 207476 */     GIR_EraseRootFromParent_Done,
     /* 207477 */   // Label 3913: @207477
     /* 207477 */   GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(207514), // Rule ID 9011 //
     /* 207482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
     /* 207490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207503 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1264:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_0),
     /* 207506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207508 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207510 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207512 */     GIR_RootConstrainSelectedInstOperands,
     /* 207513 */     // GIR_Coverage, 9011,
     /* 207513 */     GIR_EraseRootFromParent_Done,
     /* 207514 */   // Label 3914: @207514
     /* 207514 */   GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(207551), // Rule ID 9012 //
     /* 207519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
     /* 207527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207540 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1266:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_1:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_1),
     /* 207543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207549 */     GIR_RootConstrainSelectedInstOperands,
     /* 207550 */     // GIR_Coverage, 9012,
     /* 207550 */     GIR_EraseRootFromParent_Done,
     /* 207551 */   // Label 3915: @207551
     /* 207551 */   GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(207588), // Rule ID 9013 //
     /* 207556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207559 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
     /* 207564 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207567 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207570 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207577 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1267:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_2:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_2),
     /* 207580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207582 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207584 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207586 */     GIR_RootConstrainSelectedInstOperands,
     /* 207587 */     // GIR_Coverage, 9013,
     /* 207587 */     GIR_EraseRootFromParent_Done,
     /* 207588 */   // Label 3916: @207588
     /* 207588 */   GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(207625), // Rule ID 9014 //
     /* 207593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 207596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
     /* 207601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 207610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207614 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1265:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_3:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 207614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_3),
     /* 207617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207621 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207623 */     GIR_RootConstrainSelectedInstOperands,
     /* 207624 */     // GIR_Coverage, 9014,
     /* 207624 */     GIR_EraseRootFromParent_Done,
     /* 207625 */   // Label 3917: @207625
     /* 207625 */   GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(207665), // Rule ID 10014 //
     /* 207630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 207641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207651 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2124:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_B),
     /* 207654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207656 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207658 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207660 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207663 */     GIR_RootConstrainSelectedInstOperands,
     /* 207664 */     // GIR_Coverage, 10014,
     /* 207664 */     GIR_EraseRootFromParent_Done,
     /* 207665 */   // Label 3918: @207665
     /* 207665 */   GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(207705), // Rule ID 10015 //
     /* 207670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 207681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207691 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2124:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_H),
     /* 207694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207698 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207700 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207703 */     GIR_RootConstrainSelectedInstOperands,
     /* 207704 */     // GIR_Coverage, 10015,
     /* 207704 */     GIR_EraseRootFromParent_Done,
     /* 207705 */   // Label 3919: @207705
     /* 207705 */   GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(207745), // Rule ID 10016 //
     /* 207710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 207721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207731 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2124:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_S),
     /* 207734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207740 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207743 */     GIR_RootConstrainSelectedInstOperands,
     /* 207744 */     // GIR_Coverage, 10016,
     /* 207744 */     GIR_EraseRootFromParent_Done,
     /* 207745 */   // Label 3920: @207745
     /* 207745 */   GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(207785), // Rule ID 10017 //
     /* 207750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 207761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207771 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2124:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_D),
     /* 207774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207778 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207780 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207783 */     GIR_RootConstrainSelectedInstOperands,
     /* 207784 */     // GIR_Coverage, 10017,
     /* 207784 */     GIR_EraseRootFromParent_Done,
     /* 207785 */   // Label 3921: @207785
     /* 207785 */   GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(207825), // Rule ID 10026 //
     /* 207790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207793 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 207798 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 207801 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207804 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207811 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2136:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_B),
     /* 207814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207820 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207823 */     GIR_RootConstrainSelectedInstOperands,
     /* 207824 */     // GIR_Coverage, 10026,
     /* 207824 */     GIR_EraseRootFromParent_Done,
     /* 207825 */   // Label 3922: @207825
     /* 207825 */   GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(207865), // Rule ID 10027 //
     /* 207830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 207838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 207841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207851 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2136:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_H),
     /* 207854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207860 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207863 */     GIR_RootConstrainSelectedInstOperands,
     /* 207864 */     // GIR_Coverage, 10027,
     /* 207864 */     GIR_EraseRootFromParent_Done,
     /* 207865 */   // Label 3923: @207865
     /* 207865 */   GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(207905), // Rule ID 10028 //
     /* 207870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 207878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 207881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207891 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2136:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_S),
     /* 207894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207900 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207903 */     GIR_RootConstrainSelectedInstOperands,
     /* 207904 */     // GIR_Coverage, 10028,
     /* 207904 */     GIR_EraseRootFromParent_Done,
     /* 207905 */   // Label 3924: @207905
     /* 207905 */   GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(207945), // Rule ID 10029 //
     /* 207910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 207918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 207921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 207924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 207927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207931 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2136:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 207931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_D),
     /* 207934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207938 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207940 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207943 */     GIR_RootConstrainSelectedInstOperands,
     /* 207944 */     // GIR_Coverage, 10029,
     /* 207944 */     GIR_EraseRootFromParent_Done,
     /* 207945 */   // Label 3925: @207945
     /* 207945 */   GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(207985), // Rule ID 10030 //
     /* 207950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 207961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 207964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 207967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 207971 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2124:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 207971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_B),
     /* 207974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 207976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207980 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 207983 */     GIR_RootConstrainSelectedInstOperands,
     /* 207984 */     // GIR_Coverage, 10030,
     /* 207984 */     GIR_EraseRootFromParent_Done,
     /* 207985 */   // Label 3926: @207985
     /* 207985 */   GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(208025), // Rule ID 10031 //
     /* 207990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 207993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 207998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 208001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208011 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2124:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_H),
     /* 208014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208016 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208018 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208020 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208023 */     GIR_RootConstrainSelectedInstOperands,
     /* 208024 */     // GIR_Coverage, 10031,
     /* 208024 */     GIR_EraseRootFromParent_Done,
     /* 208025 */   // Label 3927: @208025
     /* 208025 */   GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(208065), // Rule ID 10032 //
     /* 208030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 208038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 208041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208051 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2124:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_S),
     /* 208054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208058 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208060 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208063 */     GIR_RootConstrainSelectedInstOperands,
     /* 208064 */     // GIR_Coverage, 10032,
     /* 208064 */     GIR_EraseRootFromParent_Done,
     /* 208065 */   // Label 3928: @208065
     /* 208065 */   GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(208105), // Rule ID 10033 //
     /* 208070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 208078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 208081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208091 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2124:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_D),
     /* 208094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208100 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208103 */     GIR_RootConstrainSelectedInstOperands,
     /* 208104 */     // GIR_Coverage, 10033,
     /* 208104 */     GIR_EraseRootFromParent_Done,
     /* 208105 */   // Label 3929: @208105
     /* 208105 */   GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(208145), // Rule ID 10042 //
     /* 208110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 208118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 208121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208131 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2136:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
     /* 208134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208138 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208140 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208143 */     GIR_RootConstrainSelectedInstOperands,
     /* 208144 */     // GIR_Coverage, 10042,
     /* 208144 */     GIR_EraseRootFromParent_Done,
     /* 208145 */   // Label 3930: @208145
     /* 208145 */   GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(208185), // Rule ID 10043 //
     /* 208150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 208158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 208161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208171 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2136:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 208174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208178 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208180 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208183 */     GIR_RootConstrainSelectedInstOperands,
     /* 208184 */     // GIR_Coverage, 10043,
     /* 208184 */     GIR_EraseRootFromParent_Done,
     /* 208185 */   // Label 3931: @208185
     /* 208185 */   GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(208225), // Rule ID 10044 //
     /* 208190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 208198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 208201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208211 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2136:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 208214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208220 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208223 */     GIR_RootConstrainSelectedInstOperands,
     /* 208224 */     // GIR_Coverage, 10044,
     /* 208224 */     GIR_EraseRootFromParent_Done,
     /* 208225 */   // Label 3932: @208225
     /* 208225 */   GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(208265), // Rule ID 10045 //
     /* 208230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 208238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 208241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 208251 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2136:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 208251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 208254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 208256 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208258 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208260 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 208263 */     GIR_RootConstrainSelectedInstOperands,
     /* 208264 */     // GIR_Coverage, 10045,
     /* 208264 */     GIR_EraseRootFromParent_Done,
     /* 208265 */   // Label 3933: @208265
     /* 208265 */   GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(208302), // Rule ID 10204 //
     /* 208270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 208278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 208287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208291 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2034:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 208291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_H),
     /* 208294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208300 */     GIR_RootConstrainSelectedInstOperands,
     /* 208301 */     // GIR_Coverage, 10204,
     /* 208301 */     GIR_EraseRootFromParent_Done,
     /* 208302 */   // Label 3934: @208302
     /* 208302 */   GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(208339), // Rule ID 10205 //
     /* 208307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 208315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 208324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208328 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2034:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 208328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_S),
     /* 208331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208335 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208337 */     GIR_RootConstrainSelectedInstOperands,
     /* 208338 */     // GIR_Coverage, 10205,
     /* 208338 */     GIR_EraseRootFromParent_Done,
     /* 208339 */   // Label 3935: @208339
     /* 208339 */   GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(208376), // Rule ID 10206 //
     /* 208344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 208352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 208358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 208361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208365 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2034:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 208365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_D),
     /* 208368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208370 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208372 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208374 */     GIR_RootConstrainSelectedInstOperands,
     /* 208375 */     // GIR_Coverage, 10206,
     /* 208375 */     GIR_EraseRootFromParent_Done,
     /* 208376 */   // Label 3936: @208376
     /* 208376 */   GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(208413), // Rule ID 10207 //
     /* 208381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 208389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208395 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 208398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208402 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1789:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 208402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_H),
     /* 208405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208409 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208411 */     GIR_RootConstrainSelectedInstOperands,
     /* 208412 */     // GIR_Coverage, 10207,
     /* 208412 */     GIR_EraseRootFromParent_Done,
     /* 208413 */   // Label 3937: @208413
     /* 208413 */   GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(208450), // Rule ID 10208 //
     /* 208418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 208426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 208435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208439 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1789:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 208439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_S),
     /* 208442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208446 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208448 */     GIR_RootConstrainSelectedInstOperands,
     /* 208449 */     // GIR_Coverage, 10208,
     /* 208449 */     GIR_EraseRootFromParent_Done,
     /* 208450 */   // Label 3938: @208450
     /* 208450 */   GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(208487), // Rule ID 10209 //
     /* 208455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 208463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 208469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 208472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208476 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1789:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 208476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_D),
     /* 208479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208481 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208483 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208485 */     GIR_RootConstrainSelectedInstOperands,
     /* 208486 */     // GIR_Coverage, 10209,
     /* 208486 */     GIR_EraseRootFromParent_Done,
     /* 208487 */   // Label 3939: @208487
     /* 208487 */   GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(208524), // Rule ID 10210 //
     /* 208492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208495 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 208500 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 208509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208513 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2020:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 208513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_H),
     /* 208516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208522 */     GIR_RootConstrainSelectedInstOperands,
     /* 208523 */     // GIR_Coverage, 10210,
     /* 208523 */     GIR_EraseRootFromParent_Done,
     /* 208524 */   // Label 3940: @208524
     /* 208524 */   GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(208561), // Rule ID 10211 //
     /* 208529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 208537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 208546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208550 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2020:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 208550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_S),
     /* 208553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208557 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208559 */     GIR_RootConstrainSelectedInstOperands,
     /* 208560 */     // GIR_Coverage, 10211,
     /* 208560 */     GIR_EraseRootFromParent_Done,
     /* 208561 */   // Label 3941: @208561
     /* 208561 */   GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(208598), // Rule ID 10212 //
     /* 208566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 208569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 208574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 208580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 208583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208587 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2020:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 208587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_D),
     /* 208590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 208592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208594 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208596 */     GIR_RootConstrainSelectedInstOperands,
     /* 208597 */     // GIR_Coverage, 10212,
     /* 208597 */     GIR_EraseRootFromParent_Done,
     /* 208598 */   // Label 3942: @208598
     /* 208598 */   GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(208635), // Rule ID 11402 //
     /* 208603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 208614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 208617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 208620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208624 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2169:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 208624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208631 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208633 */     GIR_RootConstrainSelectedInstOperands,
     /* 208634 */     // GIR_Coverage, 11402,
     /* 208634 */     GIR_EraseRootFromParent_Done,
     /* 208635 */   // Label 3943: @208635
     /* 208635 */   GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(208672), // Rule ID 11403 //
     /* 208640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 208657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208661 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2169:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 208661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208668 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208670 */     GIR_RootConstrainSelectedInstOperands,
     /* 208671 */     // GIR_Coverage, 11403,
     /* 208671 */     GIR_EraseRootFromParent_Done,
     /* 208672 */   // Label 3944: @208672
     /* 208672 */   GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(208709), // Rule ID 11404 //
     /* 208677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208691 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 208694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208698 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2169:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 208698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208707 */     GIR_RootConstrainSelectedInstOperands,
     /* 208708 */     // GIR_Coverage, 11404,
     /* 208708 */     GIR_EraseRootFromParent_Done,
     /* 208709 */   // Label 3945: @208709
     /* 208709 */   GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(208746), // Rule ID 11405 //
     /* 208714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208728 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 208731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208735 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2169:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 208735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208742 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208744 */     GIR_RootConstrainSelectedInstOperands,
     /* 208745 */     // GIR_Coverage, 11405,
     /* 208745 */     GIR_EraseRootFromParent_Done,
     /* 208746 */   // Label 3946: @208746
     /* 208746 */   GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(208783), // Rule ID 11406 //
     /* 208751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208754 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208759 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208762 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208765 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 208768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208772 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2169:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 208772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208779 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208781 */     GIR_RootConstrainSelectedInstOperands,
     /* 208782 */     // GIR_Coverage, 11406,
     /* 208782 */     GIR_EraseRootFromParent_Done,
     /* 208783 */   // Label 3947: @208783
     /* 208783 */   GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(208820), // Rule ID 11407 //
     /* 208788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 208802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 208805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208809 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2169:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 208809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208814 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208816 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208818 */     GIR_RootConstrainSelectedInstOperands,
     /* 208819 */     // GIR_Coverage, 11407,
     /* 208819 */     GIR_EraseRootFromParent_Done,
     /* 208820 */   // Label 3948: @208820
     /* 208820 */   GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(208857), // Rule ID 11408 //
     /* 208825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 208833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 208839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 208842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208846 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2169:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 208846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 208849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208851 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208853 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208855 */     GIR_RootConstrainSelectedInstOperands,
     /* 208856 */     // GIR_Coverage, 11408,
     /* 208856 */     GIR_EraseRootFromParent_Done,
     /* 208857 */   // Label 3949: @208857
     /* 208857 */   GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(208894), // Rule ID 11409 //
     /* 208862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 208870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 208873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 208876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 208879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208883 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2090:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 208883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 208886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208890 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208892 */     GIR_RootConstrainSelectedInstOperands,
     /* 208893 */     // GIR_Coverage, 11409,
     /* 208893 */     GIR_EraseRootFromParent_Done,
     /* 208894 */   // Label 3950: @208894
     /* 208894 */   GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(208931), // Rule ID 11410 //
     /* 208899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 208907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 208916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208920 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2090:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 208920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 208923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208929 */     GIR_RootConstrainSelectedInstOperands,
     /* 208930 */     // GIR_Coverage, 11410,
     /* 208930 */     GIR_EraseRootFromParent_Done,
     /* 208931 */   // Label 3951: @208931
     /* 208931 */   GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(208968), // Rule ID 11411 //
     /* 208936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 208944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 208953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208957 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2090:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 208957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 208960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208962 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208964 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208966 */     GIR_RootConstrainSelectedInstOperands,
     /* 208967 */     // GIR_Coverage, 11411,
     /* 208967 */     GIR_EraseRootFromParent_Done,
     /* 208968 */   // Label 3952: @208968
     /* 208968 */   GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(209005), // Rule ID 11412 //
     /* 208973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 208976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 208981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 208990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208994 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2090:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 208994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 208997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209001 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209003 */     GIR_RootConstrainSelectedInstOperands,
     /* 209004 */     // GIR_Coverage, 11412,
     /* 209004 */     GIR_EraseRootFromParent_Done,
     /* 209005 */   // Label 3953: @209005
     /* 209005 */   GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(209042), // Rule ID 11413 //
     /* 209010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 209018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209031 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2090:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 209031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 209034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209040 */     GIR_RootConstrainSelectedInstOperands,
     /* 209041 */     // GIR_Coverage, 11413,
     /* 209041 */     GIR_EraseRootFromParent_Done,
     /* 209042 */   // Label 3954: @209042
     /* 209042 */   GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(209079), // Rule ID 11414 //
     /* 209047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 209055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209058 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209061 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209068 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2090:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 209068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 209071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209075 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209077 */     GIR_RootConstrainSelectedInstOperands,
     /* 209078 */     // GIR_Coverage, 11414,
     /* 209078 */     GIR_EraseRootFromParent_Done,
     /* 209079 */   // Label 3955: @209079
     /* 209079 */   GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(209116), // Rule ID 11415 //
     /* 209084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209087 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 209092 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209095 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209098 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209105 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2090:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 209105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 209108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209114 */     GIR_RootConstrainSelectedInstOperands,
     /* 209115 */     // GIR_Coverage, 11415,
     /* 209115 */     GIR_EraseRootFromParent_Done,
     /* 209116 */   // Label 3956: @209116
     /* 209116 */   GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(209153), // Rule ID 11416 //
     /* 209121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 209132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 209135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 209138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209142 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2095:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 209142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209149 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209151 */     GIR_RootConstrainSelectedInstOperands,
     /* 209152 */     // GIR_Coverage, 11416,
     /* 209152 */     GIR_EraseRootFromParent_Done,
     /* 209153 */   // Label 3957: @209153
     /* 209153 */   GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(209190), // Rule ID 11417 //
     /* 209158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209169 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209179 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2095:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 209179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209186 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209188 */     GIR_RootConstrainSelectedInstOperands,
     /* 209189 */     // GIR_Coverage, 11417,
     /* 209189 */     GIR_EraseRootFromParent_Done,
     /* 209190 */   // Label 3958: @209190
     /* 209190 */   GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(209227), // Rule ID 11418 //
     /* 209195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209203 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209206 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209216 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2095:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 209216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209225 */     GIR_RootConstrainSelectedInstOperands,
     /* 209226 */     // GIR_Coverage, 11418,
     /* 209226 */     GIR_EraseRootFromParent_Done,
     /* 209227 */   // Label 3959: @209227
     /* 209227 */   GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(209264), // Rule ID 11419 //
     /* 209232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209253 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2095:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 209253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209262 */     GIR_RootConstrainSelectedInstOperands,
     /* 209263 */     // GIR_Coverage, 11419,
     /* 209263 */     GIR_EraseRootFromParent_Done,
     /* 209264 */   // Label 3960: @209264
     /* 209264 */   GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(209301), // Rule ID 11420 //
     /* 209269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209290 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2095:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 209290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209297 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209299 */     GIR_RootConstrainSelectedInstOperands,
     /* 209300 */     // GIR_Coverage, 11420,
     /* 209300 */     GIR_EraseRootFromParent_Done,
     /* 209301 */   // Label 3961: @209301
     /* 209301 */   GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(209338), // Rule ID 11421 //
     /* 209306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209320 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209327 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2095:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 209327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209334 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209336 */     GIR_RootConstrainSelectedInstOperands,
     /* 209337 */     // GIR_Coverage, 11421,
     /* 209337 */     GIR_EraseRootFromParent_Done,
     /* 209338 */   // Label 3962: @209338
     /* 209338 */   GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(209375), // Rule ID 11422 //
     /* 209343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 209351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209364 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2095:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 209364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 209367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209371 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209373 */     GIR_RootConstrainSelectedInstOperands,
     /* 209374 */     // GIR_Coverage, 11422,
     /* 209374 */     GIR_EraseRootFromParent_Done,
     /* 209375 */   // Label 3963: @209375
     /* 209375 */   GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(209412), // Rule ID 11423 //
     /* 209380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 209391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 209394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 209397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209401 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1934:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 209401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209408 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209410 */     GIR_RootConstrainSelectedInstOperands,
     /* 209411 */     // GIR_Coverage, 11423,
     /* 209411 */     GIR_EraseRootFromParent_Done,
     /* 209412 */   // Label 3964: @209412
     /* 209412 */   GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(209449), // Rule ID 11424 //
     /* 209417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209438 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1934:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 209438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209445 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209447 */     GIR_RootConstrainSelectedInstOperands,
     /* 209448 */     // GIR_Coverage, 11424,
     /* 209448 */     GIR_EraseRootFromParent_Done,
     /* 209449 */   // Label 3965: @209449
     /* 209449 */   GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(209486), // Rule ID 11425 //
     /* 209454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209462 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209465 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209468 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209475 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1934:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 209475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209484 */     GIR_RootConstrainSelectedInstOperands,
     /* 209485 */     // GIR_Coverage, 11425,
     /* 209485 */     GIR_EraseRootFromParent_Done,
     /* 209486 */   // Label 3966: @209486
     /* 209486 */   GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(209523), // Rule ID 11426 //
     /* 209491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209512 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1934:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 209512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209519 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209521 */     GIR_RootConstrainSelectedInstOperands,
     /* 209522 */     // GIR_Coverage, 11426,
     /* 209522 */     GIR_EraseRootFromParent_Done,
     /* 209523 */   // Label 3967: @209523
     /* 209523 */   GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(209560), // Rule ID 11427 //
     /* 209528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209549 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1934:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 209549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209554 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209556 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209558 */     GIR_RootConstrainSelectedInstOperands,
     /* 209559 */     // GIR_Coverage, 11427,
     /* 209559 */     GIR_EraseRootFromParent_Done,
     /* 209560 */   // Label 3968: @209560
     /* 209560 */   GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(209597), // Rule ID 11428 //
     /* 209565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209586 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1934:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 209586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209595 */     GIR_RootConstrainSelectedInstOperands,
     /* 209596 */     // GIR_Coverage, 11428,
     /* 209596 */     GIR_EraseRootFromParent_Done,
     /* 209597 */   // Label 3969: @209597
     /* 209597 */   GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(209634), // Rule ID 11429 //
     /* 209602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 209610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209623 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1934:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 209623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 209626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209632 */     GIR_RootConstrainSelectedInstOperands,
     /* 209633 */     // GIR_Coverage, 11429,
     /* 209633 */     GIR_EraseRootFromParent_Done,
     /* 209634 */   // Label 3970: @209634
     /* 209634 */   GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(209671), // Rule ID 11430 //
     /* 209639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 209650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 209653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 209656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209660 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1939:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 209660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209669 */     GIR_RootConstrainSelectedInstOperands,
     /* 209670 */     // GIR_Coverage, 11430,
     /* 209670 */     GIR_EraseRootFromParent_Done,
     /* 209671 */   // Label 3971: @209671
     /* 209671 */   GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(209708), // Rule ID 11431 //
     /* 209676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209697 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1939:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 209697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209706 */     GIR_RootConstrainSelectedInstOperands,
     /* 209707 */     // GIR_Coverage, 11431,
     /* 209707 */     GIR_EraseRootFromParent_Done,
     /* 209708 */   // Label 3972: @209708
     /* 209708 */   GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(209745), // Rule ID 11432 //
     /* 209713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209734 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1939:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 209734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209743 */     GIR_RootConstrainSelectedInstOperands,
     /* 209744 */     // GIR_Coverage, 11432,
     /* 209744 */     GIR_EraseRootFromParent_Done,
     /* 209745 */   // Label 3973: @209745
     /* 209745 */   GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(209782), // Rule ID 11433 //
     /* 209750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209771 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1939:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 209771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209778 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209780 */     GIR_RootConstrainSelectedInstOperands,
     /* 209781 */     // GIR_Coverage, 11433,
     /* 209781 */     GIR_EraseRootFromParent_Done,
     /* 209782 */   // Label 3974: @209782
     /* 209782 */   GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(209819), // Rule ID 11434 //
     /* 209787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209795 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209798 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209808 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1939:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 209808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209815 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209817 */     GIR_RootConstrainSelectedInstOperands,
     /* 209818 */     // GIR_Coverage, 11434,
     /* 209818 */     GIR_EraseRootFromParent_Done,
     /* 209819 */   // Label 3975: @209819
     /* 209819 */   GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(209856), // Rule ID 11435 //
     /* 209824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209835 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209845 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1939:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 209845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209852 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209854 */     GIR_RootConstrainSelectedInstOperands,
     /* 209855 */     // GIR_Coverage, 11435,
     /* 209855 */     GIR_EraseRootFromParent_Done,
     /* 209856 */   // Label 3976: @209856
     /* 209856 */   GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(209893), // Rule ID 11436 //
     /* 209861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 209864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 209869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 209872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 209875 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 209878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209882 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1939:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 209882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 209885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209889 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209891 */     GIR_RootConstrainSelectedInstOperands,
     /* 209892 */     // GIR_Coverage, 11436,
     /* 209892 */     GIR_EraseRootFromParent_Done,
     /* 209893 */   // Label 3977: @209893
     /* 209893 */   GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(209930), // Rule ID 11456 //
     /* 209898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 209901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 209906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 209909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 209912 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 209915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209919 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1836:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQRDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 209919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_B),
     /* 209922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209924 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209926 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209928 */     GIR_RootConstrainSelectedInstOperands,
     /* 209929 */     // GIR_Coverage, 11456,
     /* 209929 */     GIR_EraseRootFromParent_Done,
     /* 209930 */   // Label 3978: @209930
     /* 209930 */   GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(209967), // Rule ID 11457 //
     /* 209935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 209938 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 209943 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 209946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 209949 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 209952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209956 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1836:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQRDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 209956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_H),
     /* 209959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 209963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 209965 */     GIR_RootConstrainSelectedInstOperands,
     /* 209966 */     // GIR_Coverage, 11457,
     /* 209966 */     GIR_EraseRootFromParent_Done,
     /* 209967 */   // Label 3979: @209967
     /* 209967 */   GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(210004), // Rule ID 11458 //
     /* 209972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 209975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 209980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 209983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 209986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 209989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 209993 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1836:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQRDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 209993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_S),
     /* 209996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 209998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210002 */     GIR_RootConstrainSelectedInstOperands,
     /* 210003 */     // GIR_Coverage, 11458,
     /* 210003 */     GIR_EraseRootFromParent_Done,
     /* 210004 */   // Label 3980: @210004
     /* 210004 */   GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(210041), // Rule ID 11459 //
     /* 210009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 210017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 210023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 210026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210030 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1836:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQRDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 210030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_D),
     /* 210033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210039 */     GIR_RootConstrainSelectedInstOperands,
     /* 210040 */     // GIR_Coverage, 11459,
     /* 210040 */     GIR_EraseRootFromParent_Done,
     /* 210041 */   // Label 3981: @210041
     /* 210041 */   GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(210078), // Rule ID 11747 //
     /* 210046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 210054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210067 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1700:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_H),
     /* 210070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210076 */     GIR_RootConstrainSelectedInstOperands,
     /* 210077 */     // GIR_Coverage, 11747,
     /* 210077 */     GIR_EraseRootFromParent_Done,
     /* 210078 */   // Label 3982: @210078
     /* 210078 */   GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(210115), // Rule ID 11748 //
     /* 210083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 210091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210094 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210097 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210104 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1700:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_S),
     /* 210107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210113 */     GIR_RootConstrainSelectedInstOperands,
     /* 210114 */     // GIR_Coverage, 11748,
     /* 210114 */     GIR_EraseRootFromParent_Done,
     /* 210115 */   // Label 3983: @210115
     /* 210115 */   GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(210152), // Rule ID 11749 //
     /* 210120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 210128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210141 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1700:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_D),
     /* 210144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210148 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210150 */     GIR_RootConstrainSelectedInstOperands,
     /* 210151 */     // GIR_Coverage, 11749,
     /* 210151 */     GIR_EraseRootFromParent_Done,
     /* 210152 */   // Label 3984: @210152
     /* 210152 */   GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(210189), // Rule ID 11750 //
     /* 210157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 210165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210178 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1948:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_H),
     /* 210181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210185 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210187 */     GIR_RootConstrainSelectedInstOperands,
     /* 210188 */     // GIR_Coverage, 11750,
     /* 210188 */     GIR_EraseRootFromParent_Done,
     /* 210189 */   // Label 3985: @210189
     /* 210189 */   GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(210226), // Rule ID 11751 //
     /* 210194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 210202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210215 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1948:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_S),
     /* 210218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210222 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210224 */     GIR_RootConstrainSelectedInstOperands,
     /* 210225 */     // GIR_Coverage, 11751,
     /* 210225 */     GIR_EraseRootFromParent_Done,
     /* 210226 */   // Label 3986: @210226
     /* 210226 */   GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(210263), // Rule ID 11752 //
     /* 210231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210234 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 210239 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210242 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210245 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210252 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1948:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_D),
     /* 210255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210257 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210259 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210261 */     GIR_RootConstrainSelectedInstOperands,
     /* 210262 */     // GIR_Coverage, 11752,
     /* 210262 */     GIR_EraseRootFromParent_Done,
     /* 210263 */   // Label 3987: @210263
     /* 210263 */   GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(210300), // Rule ID 11753 //
     /* 210268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 210276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210289 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1949:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_H),
     /* 210292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210296 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210298 */     GIR_RootConstrainSelectedInstOperands,
     /* 210299 */     // GIR_Coverage, 11753,
     /* 210299 */     GIR_EraseRootFromParent_Done,
     /* 210300 */   // Label 3988: @210300
     /* 210300 */   GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(210337), // Rule ID 11754 //
     /* 210305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 210313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210319 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210326 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1949:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_S),
     /* 210329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210335 */     GIR_RootConstrainSelectedInstOperands,
     /* 210336 */     // GIR_Coverage, 11754,
     /* 210336 */     GIR_EraseRootFromParent_Done,
     /* 210337 */   // Label 3989: @210337
     /* 210337 */   GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(210374), // Rule ID 11755 //
     /* 210342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 210350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210363 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1949:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_D),
     /* 210366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210370 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210372 */     GIR_RootConstrainSelectedInstOperands,
     /* 210373 */     // GIR_Coverage, 11755,
     /* 210373 */     GIR_EraseRootFromParent_Done,
     /* 210374 */   // Label 3990: @210374
     /* 210374 */   GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(210411), // Rule ID 11756 //
     /* 210379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 210387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210400 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1877:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_H),
     /* 210403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210407 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210409 */     GIR_RootConstrainSelectedInstOperands,
     /* 210410 */     // GIR_Coverage, 11756,
     /* 210410 */     GIR_EraseRootFromParent_Done,
     /* 210411 */   // Label 3991: @210411
     /* 210411 */   GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(210448), // Rule ID 11757 //
     /* 210416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 210424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210437 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1877:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_S),
     /* 210440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210444 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210446 */     GIR_RootConstrainSelectedInstOperands,
     /* 210447 */     // GIR_Coverage, 11757,
     /* 210447 */     GIR_EraseRootFromParent_Done,
     /* 210448 */   // Label 3992: @210448
     /* 210448 */   GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(210485), // Rule ID 11758 //
     /* 210453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 210461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210474 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1877:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_D),
     /* 210477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210481 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210483 */     GIR_RootConstrainSelectedInstOperands,
     /* 210484 */     // GIR_Coverage, 11758,
     /* 210484 */     GIR_EraseRootFromParent_Done,
     /* 210485 */   // Label 3993: @210485
     /* 210485 */   GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(210522), // Rule ID 11759 //
     /* 210490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 210498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210511 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1879:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_H),
     /* 210514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210520 */     GIR_RootConstrainSelectedInstOperands,
     /* 210521 */     // GIR_Coverage, 11759,
     /* 210521 */     GIR_EraseRootFromParent_Done,
     /* 210522 */   // Label 3994: @210522
     /* 210522 */   GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(210559), // Rule ID 11760 //
     /* 210527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 210535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210548 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1879:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_S),
     /* 210551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210557 */     GIR_RootConstrainSelectedInstOperands,
     /* 210558 */     // GIR_Coverage, 11760,
     /* 210558 */     GIR_EraseRootFromParent_Done,
     /* 210559 */   // Label 3995: @210559
     /* 210559 */   GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(210596), // Rule ID 11761 //
     /* 210564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210567 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 210572 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210575 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210578 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210585 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1879:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_D),
     /* 210588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210590 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210592 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210594 */     GIR_RootConstrainSelectedInstOperands,
     /* 210595 */     // GIR_Coverage, 11761,
     /* 210595 */     GIR_EraseRootFromParent_Done,
     /* 210596 */   // Label 3996: @210596
     /* 210596 */   GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(210633), // Rule ID 11762 //
     /* 210601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 210609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210612 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210615 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210622 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2073:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_H),
     /* 210625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210627 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210629 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210631 */     GIR_RootConstrainSelectedInstOperands,
     /* 210632 */     // GIR_Coverage, 11762,
     /* 210632 */     GIR_EraseRootFromParent_Done,
     /* 210633 */   // Label 3997: @210633
     /* 210633 */   GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(210670), // Rule ID 11763 //
     /* 210638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 210646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210659 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2073:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_S),
     /* 210662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210668 */     GIR_RootConstrainSelectedInstOperands,
     /* 210669 */     // GIR_Coverage, 11763,
     /* 210669 */     GIR_EraseRootFromParent_Done,
     /* 210670 */   // Label 3998: @210670
     /* 210670 */   GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(210707), // Rule ID 11764 //
     /* 210675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 210683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210689 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210696 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2073:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_D),
     /* 210699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210703 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210705 */     GIR_RootConstrainSelectedInstOperands,
     /* 210706 */     // GIR_Coverage, 11764,
     /* 210706 */     GIR_EraseRootFromParent_Done,
     /* 210707 */   // Label 3999: @210707
     /* 210707 */   GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(210744), // Rule ID 11765 //
     /* 210712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 210720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210733 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2074:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_H),
     /* 210736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210740 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210742 */     GIR_RootConstrainSelectedInstOperands,
     /* 210743 */     // GIR_Coverage, 11765,
     /* 210743 */     GIR_EraseRootFromParent_Done,
     /* 210744 */   // Label 4000: @210744
     /* 210744 */   GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(210781), // Rule ID 11766 //
     /* 210749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 210757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210770 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2074:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_S),
     /* 210773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210777 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210779 */     GIR_RootConstrainSelectedInstOperands,
     /* 210780 */     // GIR_Coverage, 11766,
     /* 210780 */     GIR_EraseRootFromParent_Done,
     /* 210781 */   // Label 4001: @210781
     /* 210781 */   GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(210818), // Rule ID 11767 //
     /* 210786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 210794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210807 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2074:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_D),
     /* 210810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210814 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210816 */     GIR_RootConstrainSelectedInstOperands,
     /* 210817 */     // GIR_Coverage, 11767,
     /* 210817 */     GIR_EraseRootFromParent_Done,
     /* 210818 */   // Label 4002: @210818
     /* 210818 */   GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(210855), // Rule ID 11768 //
     /* 210823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 210831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210844 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1695:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_H),
     /* 210847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210851 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210853 */     GIR_RootConstrainSelectedInstOperands,
     /* 210854 */     // GIR_Coverage, 11768,
     /* 210854 */     GIR_EraseRootFromParent_Done,
     /* 210855 */   // Label 4003: @210855
     /* 210855 */   GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(210892), // Rule ID 11769 //
     /* 210860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 210868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210881 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1695:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_S),
     /* 210884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210890 */     GIR_RootConstrainSelectedInstOperands,
     /* 210891 */     // GIR_Coverage, 11769,
     /* 210891 */     GIR_EraseRootFromParent_Done,
     /* 210892 */   // Label 4004: @210892
     /* 210892 */   GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(210929), // Rule ID 11770 //
     /* 210897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 210905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 210908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 210911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 210914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210918 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1695:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 210918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_D),
     /* 210921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210927 */     GIR_RootConstrainSelectedInstOperands,
     /* 210928 */     // GIR_Coverage, 11770,
     /* 210928 */     GIR_EraseRootFromParent_Done,
     /* 210929 */   // Label 4005: @210929
     /* 210929 */   GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(210966), // Rule ID 11771 //
     /* 210934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 210942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 210945 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 210948 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 210951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210955 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1696:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 210955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_H),
     /* 210958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 210964 */     GIR_RootConstrainSelectedInstOperands,
     /* 210965 */     // GIR_Coverage, 11771,
     /* 210965 */     GIR_EraseRootFromParent_Done,
     /* 210966 */   // Label 4006: @210966
     /* 210966 */   GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(211003), // Rule ID 11772 //
     /* 210971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 210974 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 210979 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 210982 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 210985 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 210988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 210992 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1696:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 210992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_S),
     /* 210995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 210997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 210999 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211001 */     GIR_RootConstrainSelectedInstOperands,
     /* 211002 */     // GIR_Coverage, 11772,
     /* 211002 */     GIR_EraseRootFromParent_Done,
     /* 211003 */   // Label 4007: @211003
     /* 211003 */   GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(211040), // Rule ID 11773 //
     /* 211008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211011 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 211016 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211019 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211022 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211029 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1696:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_D),
     /* 211032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211036 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211038 */     GIR_RootConstrainSelectedInstOperands,
     /* 211039 */     // GIR_Coverage, 11773,
     /* 211039 */     GIR_EraseRootFromParent_Done,
     /* 211040 */   // Label 4008: @211040
     /* 211040 */   GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(211077), // Rule ID 11774 //
     /* 211045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 211053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 211059 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211066 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1945:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_H),
     /* 211069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211073 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211075 */     GIR_RootConstrainSelectedInstOperands,
     /* 211076 */     // GIR_Coverage, 11774,
     /* 211076 */     GIR_EraseRootFromParent_Done,
     /* 211077 */   // Label 4009: @211077
     /* 211077 */   GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(211114), // Rule ID 11775 //
     /* 211082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 211090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211103 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1945:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_S),
     /* 211106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211110 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211112 */     GIR_RootConstrainSelectedInstOperands,
     /* 211113 */     // GIR_Coverage, 11775,
     /* 211113 */     GIR_EraseRootFromParent_Done,
     /* 211114 */   // Label 4010: @211114
     /* 211114 */   GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(211151), // Rule ID 11776 //
     /* 211119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 211127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211140 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1945:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_D),
     /* 211143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211147 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211149 */     GIR_RootConstrainSelectedInstOperands,
     /* 211150 */     // GIR_Coverage, 11776,
     /* 211150 */     GIR_EraseRootFromParent_Done,
     /* 211151 */   // Label 4011: @211151
     /* 211151 */   GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(211188), // Rule ID 11777 //
     /* 211156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 211164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 211170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211177 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1946:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_H),
     /* 211180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211186 */     GIR_RootConstrainSelectedInstOperands,
     /* 211187 */     // GIR_Coverage, 11777,
     /* 211187 */     GIR_EraseRootFromParent_Done,
     /* 211188 */   // Label 4012: @211188
     /* 211188 */   GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(211225), // Rule ID 11778 //
     /* 211193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 211201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211214 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1946:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_S),
     /* 211217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211223 */     GIR_RootConstrainSelectedInstOperands,
     /* 211224 */     // GIR_Coverage, 11778,
     /* 211224 */     GIR_EraseRootFromParent_Done,
     /* 211225 */   // Label 4013: @211225
     /* 211225 */   GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(211262), // Rule ID 11779 //
     /* 211230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 211238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211251 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1946:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_D),
     /* 211254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211256 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211258 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211260 */     GIR_RootConstrainSelectedInstOperands,
     /* 211261 */     // GIR_Coverage, 11779,
     /* 211261 */     GIR_EraseRootFromParent_Done,
     /* 211262 */   // Label 4014: @211262
     /* 211262 */   GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(211299), // Rule ID 11789 //
     /* 211267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 211275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211288 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1881:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_H),
     /* 211291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211297 */     GIR_RootConstrainSelectedInstOperands,
     /* 211298 */     // GIR_Coverage, 11789,
     /* 211298 */     GIR_EraseRootFromParent_Done,
     /* 211299 */   // Label 4015: @211299
     /* 211299 */   GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(211336), // Rule ID 11790 //
     /* 211304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 211312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211325 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1881:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_S),
     /* 211328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211334 */     GIR_RootConstrainSelectedInstOperands,
     /* 211335 */     // GIR_Coverage, 11790,
     /* 211335 */     GIR_EraseRootFromParent_Done,
     /* 211336 */   // Label 4016: @211336
     /* 211336 */   GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(211373), // Rule ID 11791 //
     /* 211341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 211349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 211355 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211362 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1881:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_D),
     /* 211365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211369 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211371 */     GIR_RootConstrainSelectedInstOperands,
     /* 211372 */     // GIR_Coverage, 11791,
     /* 211372 */     GIR_EraseRootFromParent_Done,
     /* 211373 */   // Label 4017: @211373
     /* 211373 */   GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(211410), // Rule ID 11792 //
     /* 211378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 211386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211392 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211399 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1882:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_H),
     /* 211402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211408 */     GIR_RootConstrainSelectedInstOperands,
     /* 211409 */     // GIR_Coverage, 11792,
     /* 211409 */     GIR_EraseRootFromParent_Done,
     /* 211410 */   // Label 4018: @211410
     /* 211410 */   GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(211447), // Rule ID 11793 //
     /* 211415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 211423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211429 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211436 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1882:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_S),
     /* 211439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211443 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211445 */     GIR_RootConstrainSelectedInstOperands,
     /* 211446 */     // GIR_Coverage, 11793,
     /* 211446 */     GIR_EraseRootFromParent_Done,
     /* 211447 */   // Label 4019: @211447
     /* 211447 */   GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(211484), // Rule ID 11794 //
     /* 211452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 211460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 211466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211473 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1882:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_D),
     /* 211476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211480 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211482 */     GIR_RootConstrainSelectedInstOperands,
     /* 211483 */     // GIR_Coverage, 11794,
     /* 211483 */     GIR_EraseRootFromParent_Done,
     /* 211484 */   // Label 4020: @211484
     /* 211484 */   GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(211521), // Rule ID 11795 //
     /* 211489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 211497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211510 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2075:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_H),
     /* 211513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211517 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211519 */     GIR_RootConstrainSelectedInstOperands,
     /* 211520 */     // GIR_Coverage, 11795,
     /* 211520 */     GIR_EraseRootFromParent_Done,
     /* 211521 */   // Label 4021: @211521
     /* 211521 */   GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(211558), // Rule ID 11796 //
     /* 211526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 211534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211540 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211547 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2075:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_S),
     /* 211550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211554 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211556 */     GIR_RootConstrainSelectedInstOperands,
     /* 211557 */     // GIR_Coverage, 11796,
     /* 211557 */     GIR_EraseRootFromParent_Done,
     /* 211558 */   // Label 4022: @211558
     /* 211558 */   GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(211595), // Rule ID 11797 //
     /* 211563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 211571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 211577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211584 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2075:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_D),
     /* 211587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211589 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211591 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211593 */     GIR_RootConstrainSelectedInstOperands,
     /* 211594 */     // GIR_Coverage, 11797,
     /* 211594 */     GIR_EraseRootFromParent_Done,
     /* 211595 */   // Label 4023: @211595
     /* 211595 */   GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(211632), // Rule ID 11798 //
     /* 211600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 211608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211621 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2076:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_H),
     /* 211624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211630 */     GIR_RootConstrainSelectedInstOperands,
     /* 211631 */     // GIR_Coverage, 11798,
     /* 211631 */     GIR_EraseRootFromParent_Done,
     /* 211632 */   // Label 4024: @211632
     /* 211632 */   GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(211669), // Rule ID 11799 //
     /* 211637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 211645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211648 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211651 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211658 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2076:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_S),
     /* 211661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211667 */     GIR_RootConstrainSelectedInstOperands,
     /* 211668 */     // GIR_Coverage, 11799,
     /* 211668 */     GIR_EraseRootFromParent_Done,
     /* 211669 */   // Label 4025: @211669
     /* 211669 */   GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(211706), // Rule ID 11800 //
     /* 211674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 211682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 211688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211695 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2076:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_D),
     /* 211698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211702 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211704 */     GIR_RootConstrainSelectedInstOperands,
     /* 211705 */     // GIR_Coverage, 11800,
     /* 211705 */     GIR_EraseRootFromParent_Done,
     /* 211706 */   // Label 4026: @211706
     /* 211706 */   GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(211743), // Rule ID 11813 //
     /* 211711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211714 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 211719 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 211725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211732 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1811:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_H),
     /* 211735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211739 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211741 */     GIR_RootConstrainSelectedInstOperands,
     /* 211742 */     // GIR_Coverage, 11813,
     /* 211742 */     GIR_EraseRootFromParent_Done,
     /* 211743 */   // Label 4027: @211743
     /* 211743 */   GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(211780), // Rule ID 11814 //
     /* 211748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 211756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211769 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1811:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_S),
     /* 211772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211778 */     GIR_RootConstrainSelectedInstOperands,
     /* 211779 */     // GIR_Coverage, 11814,
     /* 211779 */     GIR_EraseRootFromParent_Done,
     /* 211780 */   // Label 4028: @211780
     /* 211780 */   GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(211817), // Rule ID 11815 //
     /* 211785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211788 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 211793 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211799 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211806 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1811:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_D),
     /* 211809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211811 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211813 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211815 */     GIR_RootConstrainSelectedInstOperands,
     /* 211816 */     // GIR_Coverage, 11815,
     /* 211816 */     GIR_EraseRootFromParent_Done,
     /* 211817 */   // Label 4029: @211817
     /* 211817 */   GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(211854), // Rule ID 11816 //
     /* 211822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 211830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 211836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211843 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1813:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_H),
     /* 211846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211848 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211850 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211852 */     GIR_RootConstrainSelectedInstOperands,
     /* 211853 */     // GIR_Coverage, 11816,
     /* 211853 */     GIR_EraseRootFromParent_Done,
     /* 211854 */   // Label 4030: @211854
     /* 211854 */   GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(211891), // Rule ID 11817 //
     /* 211859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 211867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211873 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211880 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1813:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_S),
     /* 211883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211885 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211887 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211889 */     GIR_RootConstrainSelectedInstOperands,
     /* 211890 */     // GIR_Coverage, 11817,
     /* 211890 */     GIR_EraseRootFromParent_Done,
     /* 211891 */   // Label 4031: @211891
     /* 211891 */   GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(211928), // Rule ID 11818 //
     /* 211896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 211904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 211907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 211910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 211913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211917 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1813:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 211917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_D),
     /* 211920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211924 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211926 */     GIR_RootConstrainSelectedInstOperands,
     /* 211927 */     // GIR_Coverage, 11818,
     /* 211927 */     GIR_EraseRootFromParent_Done,
     /* 211928 */   // Label 4032: @211928
     /* 211928 */   GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(211965), // Rule ID 11819 //
     /* 211933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 211941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 211944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 211947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 211950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211954 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1764:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 211954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_H),
     /* 211957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 211963 */     GIR_RootConstrainSelectedInstOperands,
     /* 211964 */     // GIR_Coverage, 11819,
     /* 211964 */     GIR_EraseRootFromParent_Done,
     /* 211965 */   // Label 4033: @211965
     /* 211965 */   GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(212002), // Rule ID 11820 //
     /* 211970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 211973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 211978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 211981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 211984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 211987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 211991 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1764:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 211991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_S),
     /* 211994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 211996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 211998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212000 */     GIR_RootConstrainSelectedInstOperands,
     /* 212001 */     // GIR_Coverage, 11820,
     /* 212001 */     GIR_EraseRootFromParent_Done,
     /* 212002 */   // Label 4034: @212002
     /* 212002 */   GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(212039), // Rule ID 11821 //
     /* 212007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 212015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 212018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212028 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1764:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_D),
     /* 212031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212037 */     GIR_RootConstrainSelectedInstOperands,
     /* 212038 */     // GIR_Coverage, 11821,
     /* 212038 */     GIR_EraseRootFromParent_Done,
     /* 212039 */   // Label 4035: @212039
     /* 212039 */   GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(212076), // Rule ID 11822 //
     /* 212044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 212052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 212061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212065 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1766:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 212065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_H),
     /* 212068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212070 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212072 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212074 */     GIR_RootConstrainSelectedInstOperands,
     /* 212075 */     // GIR_Coverage, 11822,
     /* 212075 */     GIR_EraseRootFromParent_Done,
     /* 212076 */   // Label 4036: @212076
     /* 212076 */   GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(212113), // Rule ID 11823 //
     /* 212081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 212089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212102 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1766:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_S),
     /* 212105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212111 */     GIR_RootConstrainSelectedInstOperands,
     /* 212112 */     // GIR_Coverage, 11823,
     /* 212112 */     GIR_EraseRootFromParent_Done,
     /* 212113 */   // Label 4037: @212113
     /* 212113 */   GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(212150), // Rule ID 11824 //
     /* 212118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 212126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 212129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212139 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1766:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_D),
     /* 212142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212148 */     GIR_RootConstrainSelectedInstOperands,
     /* 212149 */     // GIR_Coverage, 11824,
     /* 212149 */     GIR_EraseRootFromParent_Done,
     /* 212150 */   // Label 4038: @212150
     /* 212150 */   GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(212187), // Rule ID 11825 //
     /* 212155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 212163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 212172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212176 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2002:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 212176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_H),
     /* 212179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212183 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212185 */     GIR_RootConstrainSelectedInstOperands,
     /* 212186 */     // GIR_Coverage, 11825,
     /* 212186 */     GIR_EraseRootFromParent_Done,
     /* 212187 */   // Label 4039: @212187
     /* 212187 */   GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(212224), // Rule ID 11826 //
     /* 212192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 212200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212213 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2002:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_S),
     /* 212216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212220 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212222 */     GIR_RootConstrainSelectedInstOperands,
     /* 212223 */     // GIR_Coverage, 11826,
     /* 212223 */     GIR_EraseRootFromParent_Done,
     /* 212224 */   // Label 4040: @212224
     /* 212224 */   GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(212261), // Rule ID 11827 //
     /* 212229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 212237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 212240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212250 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2002:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_D),
     /* 212253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212259 */     GIR_RootConstrainSelectedInstOperands,
     /* 212260 */     // GIR_Coverage, 11827,
     /* 212260 */     GIR_EraseRootFromParent_Done,
     /* 212261 */   // Label 4041: @212261
     /* 212261 */   GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(212298), // Rule ID 11828 //
     /* 212266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 212274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 212283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212287 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2004:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 212287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_H),
     /* 212290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212296 */     GIR_RootConstrainSelectedInstOperands,
     /* 212297 */     // GIR_Coverage, 11828,
     /* 212297 */     GIR_EraseRootFromParent_Done,
     /* 212298 */   // Label 4042: @212298
     /* 212298 */   GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(212335), // Rule ID 11829 //
     /* 212303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 212311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212324 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2004:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_S),
     /* 212327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212329 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212331 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212333 */     GIR_RootConstrainSelectedInstOperands,
     /* 212334 */     // GIR_Coverage, 11829,
     /* 212334 */     GIR_EraseRootFromParent_Done,
     /* 212335 */   // Label 4043: @212335
     /* 212335 */   GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(212372), // Rule ID 11830 //
     /* 212340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 212348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 212351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212361 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2004:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_D),
     /* 212364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212368 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212370 */     GIR_RootConstrainSelectedInstOperands,
     /* 212371 */     // GIR_Coverage, 11830,
     /* 212371 */     GIR_EraseRootFromParent_Done,
     /* 212372 */   // Label 4044: @212372
     /* 212372 */   GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(212409), // Rule ID 11831 //
     /* 212377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 212385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 212394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212398 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1642:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMULLT_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 212398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_H),
     /* 212401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212407 */     GIR_RootConstrainSelectedInstOperands,
     /* 212408 */     // GIR_Coverage, 11831,
     /* 212408 */     GIR_EraseRootFromParent_Done,
     /* 212409 */   // Label 4045: @212409
     /* 212409 */   GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(212446), // Rule ID 11832 //
     /* 212414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 212422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212435 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1642:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (PMULLT_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_D),
     /* 212438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212442 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212444 */     GIR_RootConstrainSelectedInstOperands,
     /* 212445 */     // GIR_Coverage, 11832,
     /* 212445 */     GIR_EraseRootFromParent_Done,
     /* 212446 */   // Label 4046: @212446
     /* 212446 */   GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(212483), // Rule ID 11933 //
     /* 212451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 212459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212472 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1672:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (RADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_B),
     /* 212475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212481 */     GIR_RootConstrainSelectedInstOperands,
     /* 212482 */     // GIR_Coverage, 11933,
     /* 212482 */     GIR_EraseRootFromParent_Done,
     /* 212483 */   // Label 4047: @212483
     /* 212483 */   GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(212520), // Rule ID 11934 //
     /* 212488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 212496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212509 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1672:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (RADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_H),
     /* 212512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212518 */     GIR_RootConstrainSelectedInstOperands,
     /* 212519 */     // GIR_Coverage, 11934,
     /* 212519 */     GIR_EraseRootFromParent_Done,
     /* 212520 */   // Label 4048: @212520
     /* 212520 */   GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(212557), // Rule ID 11935 //
     /* 212525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 212533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 212539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 212542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212546 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1672:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 212546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_S),
     /* 212549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212551 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212553 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212555 */     GIR_RootConstrainSelectedInstOperands,
     /* 212556 */     // GIR_Coverage, 11935,
     /* 212556 */     GIR_EraseRootFromParent_Done,
     /* 212557 */   // Label 4049: @212557
     /* 212557 */   GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(212594), // Rule ID 11936 //
     /* 212562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 212570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212583 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1913:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_B),
     /* 212586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212590 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212592 */     GIR_RootConstrainSelectedInstOperands,
     /* 212593 */     // GIR_Coverage, 11936,
     /* 212593 */     GIR_EraseRootFromParent_Done,
     /* 212594 */   // Label 4050: @212594
     /* 212594 */   GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(212631), // Rule ID 11937 //
     /* 212599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 212607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212620 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1913:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_H),
     /* 212623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212629 */     GIR_RootConstrainSelectedInstOperands,
     /* 212630 */     // GIR_Coverage, 11937,
     /* 212630 */     GIR_EraseRootFromParent_Done,
     /* 212631 */   // Label 4051: @212631
     /* 212631 */   GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(212668), // Rule ID 11938 //
     /* 212636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 212644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 212650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 212653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212657 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1913:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 212657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_S),
     /* 212660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212666 */     GIR_RootConstrainSelectedInstOperands,
     /* 212667 */     // GIR_Coverage, 11938,
     /* 212667 */     GIR_EraseRootFromParent_Done,
     /* 212668 */   // Label 4052: @212668
     /* 212668 */   GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(212705), // Rule ID 11939 //
     /* 212673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 212681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212694 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1688:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (RSUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_B),
     /* 212697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212701 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212703 */     GIR_RootConstrainSelectedInstOperands,
     /* 212704 */     // GIR_Coverage, 11939,
     /* 212704 */     GIR_EraseRootFromParent_Done,
     /* 212705 */   // Label 4053: @212705
     /* 212705 */   GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(212742), // Rule ID 11940 //
     /* 212710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 212718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212731 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1688:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (RSUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_H),
     /* 212734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212740 */     GIR_RootConstrainSelectedInstOperands,
     /* 212741 */     // GIR_Coverage, 11940,
     /* 212741 */     GIR_EraseRootFromParent_Done,
     /* 212742 */   // Label 4054: @212742
     /* 212742 */   GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(212779), // Rule ID 11941 //
     /* 212747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 212755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 212761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 212764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212768 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1688:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RSUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 212768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_S),
     /* 212771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212777 */     GIR_RootConstrainSelectedInstOperands,
     /* 212778 */     // GIR_Coverage, 11941,
     /* 212778 */     GIR_EraseRootFromParent_Done,
     /* 212779 */   // Label 4055: @212779
     /* 212779 */   GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(212816), // Rule ID 11957 //
     /* 212784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 212792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212805 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2055:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_B),
     /* 212808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212810 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212812 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212814 */     GIR_RootConstrainSelectedInstOperands,
     /* 212815 */     // GIR_Coverage, 11957,
     /* 212815 */     GIR_EraseRootFromParent_Done,
     /* 212816 */   // Label 4056: @212816
     /* 212816 */   GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(212853), // Rule ID 11958 //
     /* 212821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212824 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 212829 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212842 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2055:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_H),
     /* 212845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212847 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212851 */     GIR_RootConstrainSelectedInstOperands,
     /* 212852 */     // GIR_Coverage, 11958,
     /* 212852 */     GIR_EraseRootFromParent_Done,
     /* 212853 */   // Label 4057: @212853
     /* 212853 */   GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(212890), // Rule ID 11959 //
     /* 212858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 212866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212872 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 212875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212879 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2055:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 212879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_S),
     /* 212882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212886 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212888 */     GIR_RootConstrainSelectedInstOperands,
     /* 212889 */     // GIR_Coverage, 11959,
     /* 212889 */     GIR_EraseRootFromParent_Done,
     /* 212890 */   // Label 4058: @212890
     /* 212890 */   GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(212927), // Rule ID 11960 //
     /* 212895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 212903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 212906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 212909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 212912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212916 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1864:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQXTUNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 212916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_B),
     /* 212919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212921 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212923 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212925 */     GIR_RootConstrainSelectedInstOperands,
     /* 212926 */     // GIR_Coverage, 11960,
     /* 212926 */     GIR_EraseRootFromParent_Done,
     /* 212927 */   // Label 4059: @212927
     /* 212927 */   GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(212964), // Rule ID 11961 //
     /* 212932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 212940 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 212943 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 212946 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 212949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212953 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1864:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQXTUNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 212953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_H),
     /* 212956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212958 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212960 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212962 */     GIR_RootConstrainSelectedInstOperands,
     /* 212963 */     // GIR_Coverage, 11961,
     /* 212963 */     GIR_EraseRootFromParent_Done,
     /* 212964 */   // Label 4060: @212964
     /* 212964 */   GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(213001), // Rule ID 11962 //
     /* 212969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 212972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 212977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 212980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 212983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 212986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 212990 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1864:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQXTUNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 212990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_S),
     /* 212993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 212995 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 212997 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 212999 */     GIR_RootConstrainSelectedInstOperands,
     /* 213000 */     // GIR_Coverage, 11962,
     /* 213000 */     GIR_EraseRootFromParent_Done,
     /* 213001 */   // Label 4061: @213001
     /* 213001 */   GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(213038), // Rule ID 11978 //
     /* 213006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 213014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 213017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 213020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 213023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213027 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1878:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 213027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_H),
     /* 213030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213032 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213034 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213036 */     GIR_RootConstrainSelectedInstOperands,
     /* 213037 */     // GIR_Coverage, 11978,
     /* 213037 */     GIR_EraseRootFromParent_Done,
     /* 213038 */   // Label 4062: @213038
     /* 213038 */   GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(213075), // Rule ID 11979 //
     /* 213043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 213051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 213054 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 213057 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 213060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213064 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1878:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 213064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_S),
     /* 213067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213071 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213073 */     GIR_RootConstrainSelectedInstOperands,
     /* 213074 */     // GIR_Coverage, 11979,
     /* 213074 */     GIR_EraseRootFromParent_Done,
     /* 213075 */   // Label 4063: @213075
     /* 213075 */   GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(213112), // Rule ID 11980 //
     /* 213080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 213088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 213091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 213094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 213097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213101 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1878:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 213101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_D),
     /* 213104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213108 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213110 */     GIR_RootConstrainSelectedInstOperands,
     /* 213111 */     // GIR_Coverage, 11980,
     /* 213111 */     GIR_EraseRootFromParent_Done,
     /* 213112 */   // Label 4064: @213112
     /* 213112 */   GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(213149), // Rule ID 11981 //
     /* 213117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 213125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 213128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 213131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 213134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213138 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1880:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 213138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_H),
     /* 213141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213147 */     GIR_RootConstrainSelectedInstOperands,
     /* 213148 */     // GIR_Coverage, 11981,
     /* 213148 */     GIR_EraseRootFromParent_Done,
     /* 213149 */   // Label 4065: @213149
     /* 213149 */   GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(213186), // Rule ID 11982 //
     /* 213154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 213162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 213165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 213168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 213171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213175 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1880:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 213175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_S),
     /* 213178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213182 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213184 */     GIR_RootConstrainSelectedInstOperands,
     /* 213185 */     // GIR_Coverage, 11982,
     /* 213185 */     GIR_EraseRootFromParent_Done,
     /* 213186 */   // Label 4066: @213186
     /* 213186 */   GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(213223), // Rule ID 11983 //
     /* 213191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213194 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 213199 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 213202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 213205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 213208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 213212 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1880:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 213212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_D),
     /* 213215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 213217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213219 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213221 */     GIR_RootConstrainSelectedInstOperands,
     /* 213222 */     // GIR_Coverage, 11983,
     /* 213222 */     GIR_EraseRootFromParent_Done,
     /* 213223 */   // Label 4067: @213223
     /* 213223 */   GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(213263), // Rule ID 12218 //
     /* 213228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 213239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213249 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2100:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_B),
     /* 213252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213258 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213261 */     GIR_RootConstrainSelectedInstOperands,
     /* 213262 */     // GIR_Coverage, 12218,
     /* 213262 */     GIR_EraseRootFromParent_Done,
     /* 213263 */   // Label 4068: @213263
     /* 213263 */   GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(213303), // Rule ID 12219 //
     /* 213268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 213279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213289 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2100:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_H),
     /* 213292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213296 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213298 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213301 */     GIR_RootConstrainSelectedInstOperands,
     /* 213302 */     // GIR_Coverage, 12219,
     /* 213302 */     GIR_EraseRootFromParent_Done,
     /* 213303 */   // Label 4069: @213303
     /* 213303 */   GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(213343), // Rule ID 12220 //
     /* 213308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 213319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213329 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2100:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_S),
     /* 213332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213338 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213341 */     GIR_RootConstrainSelectedInstOperands,
     /* 213342 */     // GIR_Coverage, 12220,
     /* 213342 */     GIR_EraseRootFromParent_Done,
     /* 213343 */   // Label 4070: @213343
     /* 213343 */   GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(213383), // Rule ID 12221 //
     /* 213348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 213359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213369 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2100:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_D),
     /* 213372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213378 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213381 */     GIR_RootConstrainSelectedInstOperands,
     /* 213382 */     // GIR_Coverage, 12221,
     /* 213382 */     GIR_EraseRootFromParent_Done,
     /* 213383 */   // Label 4071: @213383
     /* 213383 */   GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(213423), // Rule ID 12222 //
     /* 213388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 213396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 213399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213409 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2106:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_B),
     /* 213412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213418 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213421 */     GIR_RootConstrainSelectedInstOperands,
     /* 213422 */     // GIR_Coverage, 12222,
     /* 213422 */     GIR_EraseRootFromParent_Done,
     /* 213423 */   // Label 4072: @213423
     /* 213423 */   GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(213463), // Rule ID 12223 //
     /* 213428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 213436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 213439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213449 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2106:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_H),
     /* 213452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213454 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213456 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213458 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213461 */     GIR_RootConstrainSelectedInstOperands,
     /* 213462 */     // GIR_Coverage, 12223,
     /* 213462 */     GIR_EraseRootFromParent_Done,
     /* 213463 */   // Label 4073: @213463
     /* 213463 */   GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(213503), // Rule ID 12224 //
     /* 213468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 213476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 213479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213489 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2106:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_S),
     /* 213492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213498 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213501 */     GIR_RootConstrainSelectedInstOperands,
     /* 213502 */     // GIR_Coverage, 12224,
     /* 213502 */     GIR_EraseRootFromParent_Done,
     /* 213503 */   // Label 4074: @213503
     /* 213503 */   GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(213543), // Rule ID 12225 //
     /* 213508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 213516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 213519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213529 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2106:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_D),
     /* 213532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213538 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213541 */     GIR_RootConstrainSelectedInstOperands,
     /* 213542 */     // GIR_Coverage, 12225,
     /* 213542 */     GIR_EraseRootFromParent_Done,
     /* 213543 */   // Label 4075: @213543
     /* 213543 */   GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(213583), // Rule ID 12230 //
     /* 213548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 213556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 213559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213569 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2118:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_B),
     /* 213572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213576 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213578 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213581 */     GIR_RootConstrainSelectedInstOperands,
     /* 213582 */     // GIR_Coverage, 12230,
     /* 213582 */     GIR_EraseRootFromParent_Done,
     /* 213583 */   // Label 4076: @213583
     /* 213583 */   GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(213623), // Rule ID 12231 //
     /* 213588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 213596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 213599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213609 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2118:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_H),
     /* 213612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213618 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213621 */     GIR_RootConstrainSelectedInstOperands,
     /* 213622 */     // GIR_Coverage, 12231,
     /* 213622 */     GIR_EraseRootFromParent_Done,
     /* 213623 */   // Label 4077: @213623
     /* 213623 */   GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(213663), // Rule ID 12232 //
     /* 213628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 213636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 213639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213649 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2118:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_S),
     /* 213652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213654 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213656 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213658 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213661 */     GIR_RootConstrainSelectedInstOperands,
     /* 213662 */     // GIR_Coverage, 12232,
     /* 213662 */     GIR_EraseRootFromParent_Done,
     /* 213663 */   // Label 4078: @213663
     /* 213663 */   GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(213703), // Rule ID 12233 //
     /* 213668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 213676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 213679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213689 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2118:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_D),
     /* 213692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213696 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213698 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213701 */     GIR_RootConstrainSelectedInstOperands,
     /* 213702 */     // GIR_Coverage, 12233,
     /* 213702 */     GIR_EraseRootFromParent_Done,
     /* 213703 */   // Label 4079: @213703
     /* 213703 */   GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(213743), // Rule ID 12234 //
     /* 213708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 213716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 213719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213729 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2112:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_B),
     /* 213732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213734 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213736 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213738 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213741 */     GIR_RootConstrainSelectedInstOperands,
     /* 213742 */     // GIR_Coverage, 12234,
     /* 213742 */     GIR_EraseRootFromParent_Done,
     /* 213743 */   // Label 4080: @213743
     /* 213743 */   GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(213783), // Rule ID 12235 //
     /* 213748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 213756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 213759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213769 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2112:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_H),
     /* 213772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213778 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213781 */     GIR_RootConstrainSelectedInstOperands,
     /* 213782 */     // GIR_Coverage, 12235,
     /* 213782 */     GIR_EraseRootFromParent_Done,
     /* 213783 */   // Label 4081: @213783
     /* 213783 */   GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(213823), // Rule ID 12236 //
     /* 213788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 213796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 213799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213809 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2112:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_S),
     /* 213812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213814 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213816 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213818 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213821 */     GIR_RootConstrainSelectedInstOperands,
     /* 213822 */     // GIR_Coverage, 12236,
     /* 213822 */     GIR_EraseRootFromParent_Done,
     /* 213823 */   // Label 4082: @213823
     /* 213823 */   GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(213863), // Rule ID 12237 //
     /* 213828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 213836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 213839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 213842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 213845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213849 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2112:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 213849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_D),
     /* 213852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213858 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213861 */     GIR_RootConstrainSelectedInstOperands,
     /* 213862 */     // GIR_Coverage, 12237,
     /* 213862 */     GIR_EraseRootFromParent_Done,
     /* 213863 */   // Label 4083: @213863
     /* 213863 */   GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(213903), // Rule ID 12242 //
     /* 213868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 213879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 213882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 213885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213889 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2100:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 213889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_B),
     /* 213892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213898 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213901 */     GIR_RootConstrainSelectedInstOperands,
     /* 213902 */     // GIR_Coverage, 12242,
     /* 213902 */     GIR_EraseRootFromParent_Done,
     /* 213903 */   // Label 4084: @213903
     /* 213903 */   GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(213943), // Rule ID 12243 //
     /* 213908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 213919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 213922 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 213925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213929 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2100:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 213929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_H),
     /* 213932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213938 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213941 */     GIR_RootConstrainSelectedInstOperands,
     /* 213942 */     // GIR_Coverage, 12243,
     /* 213942 */     GIR_EraseRootFromParent_Done,
     /* 213943 */   // Label 4085: @213943
     /* 213943 */   GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(213983), // Rule ID 12244 //
     /* 213948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213951 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213956 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 213959 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 213962 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 213965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 213969 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2100:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 213969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_S),
     /* 213972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 213974 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 213976 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 213978 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 213981 */     GIR_RootConstrainSelectedInstOperands,
     /* 213982 */     // GIR_Coverage, 12244,
     /* 213982 */     GIR_EraseRootFromParent_Done,
     /* 213983 */   // Label 4086: @213983
     /* 213983 */   GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(214023), // Rule ID 12245 //
     /* 213988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 213991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 213996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 213999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214009 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2100:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_D),
     /* 214012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214016 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214018 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214021 */     GIR_RootConstrainSelectedInstOperands,
     /* 214022 */     // GIR_Coverage, 12245,
     /* 214022 */     GIR_EraseRootFromParent_Done,
     /* 214023 */   // Label 4087: @214023
     /* 214023 */   GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(214063), // Rule ID 12246 //
     /* 214028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 214036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 214039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214049 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2106:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_B),
     /* 214052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214056 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214058 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214061 */     GIR_RootConstrainSelectedInstOperands,
     /* 214062 */     // GIR_Coverage, 12246,
     /* 214062 */     GIR_EraseRootFromParent_Done,
     /* 214063 */   // Label 4088: @214063
     /* 214063 */   GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(214103), // Rule ID 12247 //
     /* 214068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 214076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 214079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214089 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2106:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_H),
     /* 214092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214098 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214101 */     GIR_RootConstrainSelectedInstOperands,
     /* 214102 */     // GIR_Coverage, 12247,
     /* 214102 */     GIR_EraseRootFromParent_Done,
     /* 214103 */   // Label 4089: @214103
     /* 214103 */   GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(214143), // Rule ID 12248 //
     /* 214108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 214116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 214119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214129 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2106:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_S),
     /* 214132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214136 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214138 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214141 */     GIR_RootConstrainSelectedInstOperands,
     /* 214142 */     // GIR_Coverage, 12248,
     /* 214142 */     GIR_EraseRootFromParent_Done,
     /* 214143 */   // Label 4090: @214143
     /* 214143 */   GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(214183), // Rule ID 12249 //
     /* 214148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 214156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 214159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214169 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2106:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_D),
     /* 214172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214178 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214181 */     GIR_RootConstrainSelectedInstOperands,
     /* 214182 */     // GIR_Coverage, 12249,
     /* 214182 */     GIR_EraseRootFromParent_Done,
     /* 214183 */   // Label 4091: @214183
     /* 214183 */   GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(214223), // Rule ID 12254 //
     /* 214188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 214196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 214199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214209 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2118:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_B),
     /* 214212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214218 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214221 */     GIR_RootConstrainSelectedInstOperands,
     /* 214222 */     // GIR_Coverage, 12254,
     /* 214222 */     GIR_EraseRootFromParent_Done,
     /* 214223 */   // Label 4092: @214223
     /* 214223 */   GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(214263), // Rule ID 12255 //
     /* 214228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 214236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 214239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214249 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2118:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_H),
     /* 214252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214258 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214261 */     GIR_RootConstrainSelectedInstOperands,
     /* 214262 */     // GIR_Coverage, 12255,
     /* 214262 */     GIR_EraseRootFromParent_Done,
     /* 214263 */   // Label 4093: @214263
     /* 214263 */   GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(214303), // Rule ID 12256 //
     /* 214268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 214276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 214279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214289 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2118:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_S),
     /* 214292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214296 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214298 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214301 */     GIR_RootConstrainSelectedInstOperands,
     /* 214302 */     // GIR_Coverage, 12256,
     /* 214302 */     GIR_EraseRootFromParent_Done,
     /* 214303 */   // Label 4094: @214303
     /* 214303 */   GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(214343), // Rule ID 12257 //
     /* 214308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 214316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 214319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214329 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2118:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_D),
     /* 214332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214338 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214341 */     GIR_RootConstrainSelectedInstOperands,
     /* 214342 */     // GIR_Coverage, 12257,
     /* 214342 */     GIR_EraseRootFromParent_Done,
     /* 214343 */   // Label 4095: @214343
     /* 214343 */   GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(214383), // Rule ID 12258 //
     /* 214348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 214356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 214359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214369 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2112:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_B),
     /* 214372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214378 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214381 */     GIR_RootConstrainSelectedInstOperands,
     /* 214382 */     // GIR_Coverage, 12258,
     /* 214382 */     GIR_EraseRootFromParent_Done,
     /* 214383 */   // Label 4096: @214383
     /* 214383 */   GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(214423), // Rule ID 12259 //
     /* 214388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 214396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 214399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214409 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2112:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_H),
     /* 214412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214418 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214421 */     GIR_RootConstrainSelectedInstOperands,
     /* 214422 */     // GIR_Coverage, 12259,
     /* 214422 */     GIR_EraseRootFromParent_Done,
     /* 214423 */   // Label 4097: @214423
     /* 214423 */   GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(214463), // Rule ID 12260 //
     /* 214428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 214436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 214439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214449 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2112:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_S),
     /* 214452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214454 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214456 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214458 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214461 */     GIR_RootConstrainSelectedInstOperands,
     /* 214462 */     // GIR_Coverage, 12260,
     /* 214462 */     GIR_EraseRootFromParent_Done,
     /* 214463 */   // Label 4098: @214463
     /* 214463 */   GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(214503), // Rule ID 12261 //
     /* 214468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 214471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 214476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 214479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 214482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 214485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 214489 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2112:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 214489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_D),
     /* 214492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 214494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214498 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 214501 */     GIR_RootConstrainSelectedInstOperands,
     /* 214502 */     // GIR_Coverage, 12261,
     /* 214502 */     GIR_EraseRootFromParent_Done,
     /* 214503 */   // Label 4099: @214503
     /* 214503 */   GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(214540), // Rule ID 12271 //
     /* 214508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 214511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 214516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 214519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 214522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 214525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214529 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1642:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (PMULLT_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 214529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_Q),
     /* 214532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214538 */     GIR_RootConstrainSelectedInstOperands,
     /* 214539 */     // GIR_Coverage, 12271,
     /* 214539 */     GIR_EraseRootFromParent_Done,
     /* 214540 */   // Label 4100: @214540
     /* 214540 */   GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(214577), // Rule ID 12272 //
     /* 214545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p1_HasSVESHA3),
     /* 214548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rax1),
     /* 214553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 214556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 214559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 214562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214566 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1674:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RAX1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 214566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1_ZZZ_D),
     /* 214569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214575 */     GIR_RootConstrainSelectedInstOperands,
     /* 214576 */     // GIR_Coverage, 12272,
     /* 214576 */     GIR_EraseRootFromParent_Done,
     /* 214577 */   // Label 4101: @214577
     /* 214577 */   GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(214614), // Rule ID 12273 //
     /* 214582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 214590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 214593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 214596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 214599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214603 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1282:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BDEP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 214603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_B),
     /* 214606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214612 */     GIR_RootConstrainSelectedInstOperands,
     /* 214613 */     // GIR_Coverage, 12273,
     /* 214613 */     GIR_EraseRootFromParent_Done,
     /* 214614 */   // Label 4102: @214614
     /* 214614 */   GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(214651), // Rule ID 12274 //
     /* 214619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 214627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 214630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 214633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 214636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214640 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1282:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BDEP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 214640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_H),
     /* 214643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214647 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214649 */     GIR_RootConstrainSelectedInstOperands,
     /* 214650 */     // GIR_Coverage, 12274,
     /* 214650 */     GIR_EraseRootFromParent_Done,
     /* 214651 */   // Label 4103: @214651
     /* 214651 */   GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(214688), // Rule ID 12275 //
     /* 214656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 214664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 214667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 214670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 214673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214677 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1282:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BDEP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 214677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_S),
     /* 214680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214686 */     GIR_RootConstrainSelectedInstOperands,
     /* 214687 */     // GIR_Coverage, 12275,
     /* 214687 */     GIR_EraseRootFromParent_Done,
     /* 214688 */   // Label 4104: @214688
     /* 214688 */   GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(214725), // Rule ID 12276 //
     /* 214693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 214701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 214704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 214707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 214710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214714 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1282:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BDEP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 214714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_D),
     /* 214717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214723 */     GIR_RootConstrainSelectedInstOperands,
     /* 214724 */     // GIR_Coverage, 12276,
     /* 214724 */     GIR_EraseRootFromParent_Done,
     /* 214725 */   // Label 4105: @214725
     /* 214725 */   GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(214762), // Rule ID 12277 //
     /* 214730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 214738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 214741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 214744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 214747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214751 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1299:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BGRP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 214751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_B),
     /* 214754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214760 */     GIR_RootConstrainSelectedInstOperands,
     /* 214761 */     // GIR_Coverage, 12277,
     /* 214761 */     GIR_EraseRootFromParent_Done,
     /* 214762 */   // Label 4106: @214762
     /* 214762 */   GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(214799), // Rule ID 12278 //
     /* 214767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 214775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 214778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 214781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 214784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214788 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1299:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BGRP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 214788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_H),
     /* 214791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214797 */     GIR_RootConstrainSelectedInstOperands,
     /* 214798 */     // GIR_Coverage, 12278,
     /* 214798 */     GIR_EraseRootFromParent_Done,
     /* 214799 */   // Label 4107: @214799
     /* 214799 */   GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(214836), // Rule ID 12279 //
     /* 214804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 214812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 214815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 214818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 214821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214825 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1299:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BGRP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 214825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_S),
     /* 214828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214830 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214832 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214834 */     GIR_RootConstrainSelectedInstOperands,
     /* 214835 */     // GIR_Coverage, 12279,
     /* 214835 */     GIR_EraseRootFromParent_Done,
     /* 214836 */   // Label 4108: @214836
     /* 214836 */   GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(214873), // Rule ID 12280 //
     /* 214841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 214844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 214849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 214852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 214855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 214858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 214862 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1299:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BGRP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 214862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_D),
     /* 214865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 214867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214871 */     GIR_RootConstrainSelectedInstOperands,
     /* 214872 */     // GIR_Coverage, 12280,
     /* 214872 */     GIR_EraseRootFromParent_Done,
     /* 214873 */   // Label 4109: @214873
     /* 214873 */   GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(214910), // Rule ID 12394 //
     /* 214878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 214881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 214886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 214889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 214892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 214895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214899 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1448:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMAXNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 214899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_H),
     /* 214902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 214904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214908 */     GIR_RootConstrainSelectedInstOperands,
     /* 214909 */     // GIR_Coverage, 12394,
     /* 214909 */     GIR_EraseRootFromParent_Done,
     /* 214910 */   // Label 4110: @214910
     /* 214910 */   GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(214947), // Rule ID 12395 //
     /* 214915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 214918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 214923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 214926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 214929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 214932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214936 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1448:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMAXNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 214936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_S),
     /* 214939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 214941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214945 */     GIR_RootConstrainSelectedInstOperands,
     /* 214946 */     // GIR_Coverage, 12395,
     /* 214946 */     GIR_EraseRootFromParent_Done,
     /* 214947 */   // Label 4111: @214947
     /* 214947 */   GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(214984), // Rule ID 12396 //
     /* 214952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 214955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 214960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 214963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 214966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 214969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214973 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1448:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMAXNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 214973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_D),
     /* 214976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 214978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 214980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 214982 */     GIR_RootConstrainSelectedInstOperands,
     /* 214983 */     // GIR_Coverage, 12396,
     /* 214983 */     GIR_EraseRootFromParent_Done,
     /* 214984 */   // Label 4112: @214984
     /* 214984 */   GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(215021), // Rule ID 12397 //
     /* 214989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 214992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 214997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215010 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1466:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMINNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 215010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_H),
     /* 215013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215019 */     GIR_RootConstrainSelectedInstOperands,
     /* 215020 */     // GIR_Coverage, 12397,
     /* 215020 */     GIR_EraseRootFromParent_Done,
     /* 215021 */   // Label 4113: @215021
     /* 215021 */   GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(215058), // Rule ID 12398 //
     /* 215026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 215034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215047 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1466:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMINNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 215047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_S),
     /* 215050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215056 */     GIR_RootConstrainSelectedInstOperands,
     /* 215057 */     // GIR_Coverage, 12398,
     /* 215057 */     GIR_EraseRootFromParent_Done,
     /* 215058 */   // Label 4114: @215058
     /* 215058 */   GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(215095), // Rule ID 12399 //
     /* 215063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 215071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215084 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1466:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMINNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 215084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_D),
     /* 215087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215091 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215093 */     GIR_RootConstrainSelectedInstOperands,
     /* 215094 */     // GIR_Coverage, 12399,
     /* 215094 */     GIR_EraseRootFromParent_Done,
     /* 215095 */   // Label 4115: @215095
     /* 215095 */   GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(215132), // Rule ID 12400 //
     /* 215100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 215108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215121 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1451:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMAXQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 215121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_H),
     /* 215124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215130 */     GIR_RootConstrainSelectedInstOperands,
     /* 215131 */     // GIR_Coverage, 12400,
     /* 215131 */     GIR_EraseRootFromParent_Done,
     /* 215132 */   // Label 4116: @215132
     /* 215132 */   GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(215169), // Rule ID 12401 //
     /* 215137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 215145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215158 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1451:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMAXQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 215158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_S),
     /* 215161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215167 */     GIR_RootConstrainSelectedInstOperands,
     /* 215168 */     // GIR_Coverage, 12401,
     /* 215168 */     GIR_EraseRootFromParent_Done,
     /* 215169 */   // Label 4117: @215169
     /* 215169 */   GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(215206), // Rule ID 12402 //
     /* 215174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 215182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215195 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1451:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMAXQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 215195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_D),
     /* 215198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215202 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215204 */     GIR_RootConstrainSelectedInstOperands,
     /* 215205 */     // GIR_Coverage, 12402,
     /* 215205 */     GIR_EraseRootFromParent_Done,
     /* 215206 */   // Label 4118: @215206
     /* 215206 */   GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(215243), // Rule ID 12403 //
     /* 215211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 215219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215232 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1469:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMINQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 215232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_H),
     /* 215235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215241 */     GIR_RootConstrainSelectedInstOperands,
     /* 215242 */     // GIR_Coverage, 12403,
     /* 215242 */     GIR_EraseRootFromParent_Done,
     /* 215243 */   // Label 4119: @215243
     /* 215243 */   GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(215280), // Rule ID 12404 //
     /* 215248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 215256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215269 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1469:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMINQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 215269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_S),
     /* 215272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215278 */     GIR_RootConstrainSelectedInstOperands,
     /* 215279 */     // GIR_Coverage, 12404,
     /* 215279 */     GIR_EraseRootFromParent_Done,
     /* 215280 */   // Label 4120: @215280
     /* 215280 */   GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(215317), // Rule ID 12405 //
     /* 215285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 215293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215299 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215306 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1469:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMINQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 215306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_D),
     /* 215309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215313 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215315 */     GIR_RootConstrainSelectedInstOperands,
     /* 215316 */     // GIR_Coverage, 12405,
     /* 215316 */     GIR_EraseRootFromParent_Done,
     /* 215317 */   // Label 4121: @215317
     /* 215317 */   GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(215354), // Rule ID 12406 //
     /* 215322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 215330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 215336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 215339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215343 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1363:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (EORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 215343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_B),
     /* 215346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215352 */     GIR_RootConstrainSelectedInstOperands,
     /* 215353 */     // GIR_Coverage, 12406,
     /* 215353 */     GIR_EraseRootFromParent_Done,
     /* 215354 */   // Label 4122: @215354
     /* 215354 */   GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(215391), // Rule ID 12407 //
     /* 215359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 215367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215380 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1363:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (EORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 215380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_H),
     /* 215383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215387 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215389 */     GIR_RootConstrainSelectedInstOperands,
     /* 215390 */     // GIR_Coverage, 12407,
     /* 215390 */     GIR_EraseRootFromParent_Done,
     /* 215391 */   // Label 4123: @215391
     /* 215391 */   GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(215428), // Rule ID 12408 //
     /* 215396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 215404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215417 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1363:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (EORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 215417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_S),
     /* 215420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215426 */     GIR_RootConstrainSelectedInstOperands,
     /* 215427 */     // GIR_Coverage, 12408,
     /* 215427 */     GIR_EraseRootFromParent_Done,
     /* 215428 */   // Label 4124: @215428
     /* 215428 */   GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(215465), // Rule ID 12409 //
     /* 215433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 215441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215454 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1363:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (EORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 215454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_D),
     /* 215457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215463 */     GIR_RootConstrainSelectedInstOperands,
     /* 215464 */     // GIR_Coverage, 12409,
     /* 215464 */     GIR_EraseRootFromParent_Done,
     /* 215465 */   // Label 4125: @215465
     /* 215465 */   GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(215502), // Rule ID 12410 //
     /* 215470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 215478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 215484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 215487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215491 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1275:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ANDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 215491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_B),
     /* 215494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215498 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215500 */     GIR_RootConstrainSelectedInstOperands,
     /* 215501 */     // GIR_Coverage, 12410,
     /* 215501 */     GIR_EraseRootFromParent_Done,
     /* 215502 */   // Label 4126: @215502
     /* 215502 */   GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(215539), // Rule ID 12411 //
     /* 215507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 215515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215528 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1275:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ANDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 215528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_H),
     /* 215531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215537 */     GIR_RootConstrainSelectedInstOperands,
     /* 215538 */     // GIR_Coverage, 12411,
     /* 215538 */     GIR_EraseRootFromParent_Done,
     /* 215539 */   // Label 4127: @215539
     /* 215539 */   GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(215576), // Rule ID 12412 //
     /* 215544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 215552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215565 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1275:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ANDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 215565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_S),
     /* 215568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215574 */     GIR_RootConstrainSelectedInstOperands,
     /* 215575 */     // GIR_Coverage, 12412,
     /* 215575 */     GIR_EraseRootFromParent_Done,
     /* 215576 */   // Label 4128: @215576
     /* 215576 */   GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(215613), // Rule ID 12413 //
     /* 215581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 215589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215602 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1275:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ANDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 215602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_D),
     /* 215605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215607 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215609 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215611 */     GIR_RootConstrainSelectedInstOperands,
     /* 215612 */     // GIR_Coverage, 12413,
     /* 215612 */     GIR_EraseRootFromParent_Done,
     /* 215613 */   // Label 4129: @215613
     /* 215613 */   GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(215650), // Rule ID 12414 //
     /* 215618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 215626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 215632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 215635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215639 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1263:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ADDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 215639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_B),
     /* 215642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215648 */     GIR_RootConstrainSelectedInstOperands,
     /* 215649 */     // GIR_Coverage, 12414,
     /* 215649 */     GIR_EraseRootFromParent_Done,
     /* 215650 */   // Label 4130: @215650
     /* 215650 */   GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(215687), // Rule ID 12415 //
     /* 215655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215658 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 215663 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215666 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215676 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1263:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 215676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_H),
     /* 215679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215683 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215685 */     GIR_RootConstrainSelectedInstOperands,
     /* 215686 */     // GIR_Coverage, 12415,
     /* 215686 */     GIR_EraseRootFromParent_Done,
     /* 215687 */   // Label 4131: @215687
     /* 215687 */   GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(215724), // Rule ID 12416 //
     /* 215692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 215700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215713 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1263:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 215713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_S),
     /* 215716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215722 */     GIR_RootConstrainSelectedInstOperands,
     /* 215723 */     // GIR_Coverage, 12416,
     /* 215723 */     GIR_EraseRootFromParent_Done,
     /* 215724 */   // Label 4132: @215724
     /* 215724 */   GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(215761), // Rule ID 12417 //
     /* 215729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 215737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215750 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1263:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 215750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_D),
     /* 215753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215757 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215759 */     GIR_RootConstrainSelectedInstOperands,
     /* 215760 */     // GIR_Coverage, 12417,
     /* 215760 */     GIR_EraseRootFromParent_Done,
     /* 215761 */   // Label 4133: @215761
     /* 215761 */   GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(215798), // Rule ID 12418 //
     /* 215766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 215774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 215780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 215783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215787 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1742:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 215787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_B),
     /* 215790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215796 */     GIR_RootConstrainSelectedInstOperands,
     /* 215797 */     // GIR_Coverage, 12418,
     /* 215797 */     GIR_EraseRootFromParent_Done,
     /* 215798 */   // Label 4134: @215798
     /* 215798 */   GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(215835), // Rule ID 12419 //
     /* 215803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 215811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215824 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1742:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 215824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_H),
     /* 215827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215831 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215833 */     GIR_RootConstrainSelectedInstOperands,
     /* 215834 */     // GIR_Coverage, 12419,
     /* 215834 */     GIR_EraseRootFromParent_Done,
     /* 215835 */   // Label 4135: @215835
     /* 215835 */   GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(215872), // Rule ID 12420 //
     /* 215840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 215848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 215854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 215857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215861 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1742:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 215861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_S),
     /* 215864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215868 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215870 */     GIR_RootConstrainSelectedInstOperands,
     /* 215871 */     // GIR_Coverage, 12420,
     /* 215871 */     GIR_EraseRootFromParent_Done,
     /* 215872 */   // Label 4136: @215872
     /* 215872 */   GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(215909), // Rule ID 12421 //
     /* 215877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 215885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 215891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 215894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215898 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1742:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 215898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_D),
     /* 215901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215907 */     GIR_RootConstrainSelectedInstOperands,
     /* 215908 */     // GIR_Coverage, 12421,
     /* 215908 */     GIR_EraseRootFromParent_Done,
     /* 215909 */   // Label 4137: @215909
     /* 215909 */   GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(215946), // Rule ID 12422 //
     /* 215914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 215922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 215928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 215931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215935 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1980:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 215935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_B),
     /* 215938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215940 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215944 */     GIR_RootConstrainSelectedInstOperands,
     /* 215945 */     // GIR_Coverage, 12422,
     /* 215945 */     GIR_EraseRootFromParent_Done,
     /* 215946 */   // Label 4138: @215946
     /* 215946 */   GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(215983), // Rule ID 12423 //
     /* 215951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 215959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 215965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 215968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215972 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1980:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 215972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_H),
     /* 215975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 215977 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 215979 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 215981 */     GIR_RootConstrainSelectedInstOperands,
     /* 215982 */     // GIR_Coverage, 12423,
     /* 215982 */     GIR_EraseRootFromParent_Done,
     /* 215983 */   // Label 4139: @215983
     /* 215983 */   GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(216020), // Rule ID 12424 //
     /* 215988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 215991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 215996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 216002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216009 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1980:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_S),
     /* 216012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216016 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216018 */     GIR_RootConstrainSelectedInstOperands,
     /* 216019 */     // GIR_Coverage, 12424,
     /* 216019 */     GIR_EraseRootFromParent_Done,
     /* 216020 */   // Label 4140: @216020
     /* 216020 */   GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(216057), // Rule ID 12425 //
     /* 216025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 216033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 216036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 216039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216046 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1980:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 216046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_D),
     /* 216049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216053 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216055 */     GIR_RootConstrainSelectedInstOperands,
     /* 216056 */     // GIR_Coverage, 12425,
     /* 216056 */     GIR_EraseRootFromParent_Done,
     /* 216057 */   // Label 4141: @216057
     /* 216057 */   GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(216094), // Rule ID 12426 //
     /* 216062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 216070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 216073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 216076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 216079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216083 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1751:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 216083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_B),
     /* 216086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216092 */     GIR_RootConstrainSelectedInstOperands,
     /* 216093 */     // GIR_Coverage, 12426,
     /* 216093 */     GIR_EraseRootFromParent_Done,
     /* 216094 */   // Label 4142: @216094
     /* 216094 */   GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(216131), // Rule ID 12427 //
     /* 216099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 216107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 216110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 216113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216120 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1751:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 216120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_H),
     /* 216123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216127 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216129 */     GIR_RootConstrainSelectedInstOperands,
     /* 216130 */     // GIR_Coverage, 12427,
     /* 216130 */     GIR_EraseRootFromParent_Done,
     /* 216131 */   // Label 4143: @216131
     /* 216131 */   GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(216168), // Rule ID 12428 //
     /* 216136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 216144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 216147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 216150 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216157 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1751:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_S),
     /* 216160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216166 */     GIR_RootConstrainSelectedInstOperands,
     /* 216167 */     // GIR_Coverage, 12428,
     /* 216167 */     GIR_EraseRootFromParent_Done,
     /* 216168 */   // Label 4144: @216168
     /* 216168 */   GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(216205), // Rule ID 12429 //
     /* 216173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 216181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 216184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 216187 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216194 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1751:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 216194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_D),
     /* 216197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216199 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216201 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216203 */     GIR_RootConstrainSelectedInstOperands,
     /* 216204 */     // GIR_Coverage, 12429,
     /* 216204 */     GIR_EraseRootFromParent_Done,
     /* 216205 */   // Label 4145: @216205
     /* 216205 */   GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(216242), // Rule ID 12430 //
     /* 216210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 216218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 216221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 216224 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 216227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216231 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1989:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 216231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_B),
     /* 216234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216240 */     GIR_RootConstrainSelectedInstOperands,
     /* 216241 */     // GIR_Coverage, 12430,
     /* 216241 */     GIR_EraseRootFromParent_Done,
     /* 216242 */   // Label 4146: @216242
     /* 216242 */   GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(216279), // Rule ID 12431 //
     /* 216247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 216255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 216258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 216261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216268 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1989:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 216268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_H),
     /* 216271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216273 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216275 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216277 */     GIR_RootConstrainSelectedInstOperands,
     /* 216278 */     // GIR_Coverage, 12431,
     /* 216278 */     GIR_EraseRootFromParent_Done,
     /* 216279 */   // Label 4147: @216279
     /* 216279 */   GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(216316), // Rule ID 12432 //
     /* 216284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 216292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 216295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 216298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216305 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1989:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_S),
     /* 216308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216312 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216314 */     GIR_RootConstrainSelectedInstOperands,
     /* 216315 */     // GIR_Coverage, 12432,
     /* 216315 */     GIR_EraseRootFromParent_Done,
     /* 216316 */   // Label 4148: @216316
     /* 216316 */   GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(216353), // Rule ID 12433 //
     /* 216321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 216329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 216332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 216335 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216342 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1989:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 216342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_D),
     /* 216345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 216347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216349 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216351 */     GIR_RootConstrainSelectedInstOperands,
     /* 216352 */     // GIR_Coverage, 12433,
     /* 216352 */     GIR_EraseRootFromParent_Done,
     /* 216353 */   // Label 4149: @216353
     /* 216353 */   GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(216390), // Rule ID 12434 //
     /* 216358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 216369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 216372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 216375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216379 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2173:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 216379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_B),
     /* 216382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216386 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216388 */     GIR_RootConstrainSelectedInstOperands,
     /* 216389 */     // GIR_Coverage, 12434,
     /* 216389 */     GIR_EraseRootFromParent_Done,
     /* 216390 */   // Label 4150: @216390
     /* 216390 */   GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(216427), // Rule ID 12435 //
     /* 216395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 216406 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 216409 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216416 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2173:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 216416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
     /* 216419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216423 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216425 */     GIR_RootConstrainSelectedInstOperands,
     /* 216426 */     // GIR_Coverage, 12435,
     /* 216426 */     GIR_EraseRootFromParent_Done,
     /* 216427 */   // Label 4151: @216427
     /* 216427 */   GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(216464), // Rule ID 12436 //
     /* 216432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 216443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 216446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216453 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2173:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
     /* 216456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216460 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216462 */     GIR_RootConstrainSelectedInstOperands,
     /* 216463 */     // GIR_Coverage, 12436,
     /* 216463 */     GIR_EraseRootFromParent_Done,
     /* 216464 */   // Label 4152: @216464
     /* 216464 */   GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(216501), // Rule ID 12437 //
     /* 216469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 216480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 216483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216490 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2173:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 216490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
     /* 216493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216497 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216499 */     GIR_RootConstrainSelectedInstOperands,
     /* 216500 */     // GIR_Coverage, 12437,
     /* 216500 */     GIR_EraseRootFromParent_Done,
     /* 216501 */   // Label 4153: @216501
     /* 216501 */   GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(216538), // Rule ID 12438 //
     /* 216506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 216517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 216520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216527 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2173:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 216527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
     /* 216530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216536 */     GIR_RootConstrainSelectedInstOperands,
     /* 216537 */     // GIR_Coverage, 12438,
     /* 216537 */     GIR_EraseRootFromParent_Done,
     /* 216538 */   // Label 4154: @216538
     /* 216538 */   GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(216575), // Rule ID 12439 //
     /* 216543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 216554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 216557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216564 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2173:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 216564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
     /* 216567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216573 */     GIR_RootConstrainSelectedInstOperands,
     /* 216574 */     // GIR_Coverage, 12439,
     /* 216574 */     GIR_EraseRootFromParent_Done,
     /* 216575 */   // Label 4155: @216575
     /* 216575 */   GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(216612), // Rule ID 12440 //
     /* 216580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 216588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 216591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 216594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216601 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2173:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 216601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
     /* 216604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216610 */     GIR_RootConstrainSelectedInstOperands,
     /* 216611 */     // GIR_Coverage, 12440,
     /* 216611 */     GIR_EraseRootFromParent_Done,
     /* 216612 */   // Label 4156: @216612
     /* 216612 */   GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(216649), // Rule ID 12441 //
     /* 216617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 216628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 216631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 216634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216638 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2098:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 216638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_B),
     /* 216641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216645 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216647 */     GIR_RootConstrainSelectedInstOperands,
     /* 216648 */     // GIR_Coverage, 12441,
     /* 216648 */     GIR_EraseRootFromParent_Done,
     /* 216649 */   // Label 4157: @216649
     /* 216649 */   GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(216686), // Rule ID 12442 //
     /* 216654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 216665 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 216668 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216675 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2098:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 216675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
     /* 216678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216680 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216682 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216684 */     GIR_RootConstrainSelectedInstOperands,
     /* 216685 */     // GIR_Coverage, 12442,
     /* 216685 */     GIR_EraseRootFromParent_Done,
     /* 216686 */   // Label 4158: @216686
     /* 216686 */   GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(216723), // Rule ID 12443 //
     /* 216691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216694 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216699 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 216702 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 216705 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216712 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2098:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
     /* 216715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216721 */     GIR_RootConstrainSelectedInstOperands,
     /* 216722 */     // GIR_Coverage, 12443,
     /* 216722 */     GIR_EraseRootFromParent_Done,
     /* 216723 */   // Label 4159: @216723
     /* 216723 */   GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(216760), // Rule ID 12444 //
     /* 216728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 216739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 216742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216749 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2098:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 216749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
     /* 216752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216754 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216756 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216758 */     GIR_RootConstrainSelectedInstOperands,
     /* 216759 */     // GIR_Coverage, 12444,
     /* 216759 */     GIR_EraseRootFromParent_Done,
     /* 216760 */   // Label 4160: @216760
     /* 216760 */   GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(216797), // Rule ID 12445 //
     /* 216765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 216776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 216779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216786 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2098:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 216786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
     /* 216789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216793 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216795 */     GIR_RootConstrainSelectedInstOperands,
     /* 216796 */     // GIR_Coverage, 12445,
     /* 216796 */     GIR_EraseRootFromParent_Done,
     /* 216797 */   // Label 4161: @216797
     /* 216797 */   GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(216834), // Rule ID 12446 //
     /* 216802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 216813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 216816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216823 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2098:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 216823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
     /* 216826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216832 */     GIR_RootConstrainSelectedInstOperands,
     /* 216833 */     // GIR_Coverage, 12446,
     /* 216833 */     GIR_EraseRootFromParent_Done,
     /* 216834 */   // Label 4162: @216834
     /* 216834 */   GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(216871), // Rule ID 12447 //
     /* 216839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 216847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 216850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 216853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 216856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216860 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2098:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 216860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
     /* 216863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216869 */     GIR_RootConstrainSelectedInstOperands,
     /* 216870 */     // GIR_Coverage, 12447,
     /* 216870 */     GIR_EraseRootFromParent_Done,
     /* 216871 */   // Label 4163: @216871
     /* 216871 */   GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(216908), // Rule ID 12448 //
     /* 216876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 216884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 216887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 216890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 216893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216897 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2099:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 216897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_B),
     /* 216900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216906 */     GIR_RootConstrainSelectedInstOperands,
     /* 216907 */     // GIR_Coverage, 12448,
     /* 216907 */     GIR_EraseRootFromParent_Done,
     /* 216908 */   // Label 4164: @216908
     /* 216908 */   GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(216945), // Rule ID 12449 //
     /* 216913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 216921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 216924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 216927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 216930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216934 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2099:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 216934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
     /* 216937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216943 */     GIR_RootConstrainSelectedInstOperands,
     /* 216944 */     // GIR_Coverage, 12449,
     /* 216944 */     GIR_EraseRootFromParent_Done,
     /* 216945 */   // Label 4165: @216945
     /* 216945 */   GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(216982), // Rule ID 12450 //
     /* 216950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 216958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 216961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 216964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 216967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 216971 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2099:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 216971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
     /* 216974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 216976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 216978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 216980 */     GIR_RootConstrainSelectedInstOperands,
     /* 216981 */     // GIR_Coverage, 12450,
     /* 216981 */     GIR_EraseRootFromParent_Done,
     /* 216982 */   // Label 4166: @216982
     /* 216982 */   GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(217019), // Rule ID 12451 //
     /* 216987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 216990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 216995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 216998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 217001 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 217004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 217008 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2099:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 217008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
     /* 217011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 217013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217015 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217017 */     GIR_RootConstrainSelectedInstOperands,
     /* 217018 */     // GIR_Coverage, 12451,
     /* 217018 */     GIR_EraseRootFromParent_Done,
     /* 217019 */   // Label 4167: @217019
     /* 217019 */   GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(217056), // Rule ID 12452 //
     /* 217024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 217027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 217032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 217035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 217038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 217041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 217045 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2099:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 217045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
     /* 217048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 217050 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217052 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217054 */     GIR_RootConstrainSelectedInstOperands,
     /* 217055 */     // GIR_Coverage, 12452,
     /* 217055 */     GIR_EraseRootFromParent_Done,
     /* 217056 */   // Label 4168: @217056
     /* 217056 */   GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(217093), // Rule ID 12453 //
     /* 217061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 217064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 217069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 217072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 217075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 217078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 217082 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2099:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 217082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
     /* 217085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 217087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217091 */     GIR_RootConstrainSelectedInstOperands,
     /* 217092 */     // GIR_Coverage, 12453,
     /* 217092 */     GIR_EraseRootFromParent_Done,
     /* 217093 */   // Label 4169: @217093
     /* 217093 */   GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(217130), // Rule ID 12454 //
     /* 217098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 217101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 217106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 217109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 217112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 217115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 217119 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2099:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 217119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
     /* 217122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 217124 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217128 */     GIR_RootConstrainSelectedInstOperands,
     /* 217129 */     // GIR_Coverage, 12454,
     /* 217129 */     GIR_EraseRootFromParent_Done,
     /* 217130 */   // Label 4170: @217130
     /* 217130 */   GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(217172), // Rule ID 3237 //
     /* 217135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_b),
     /* 217143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 217146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217150 */     // MIs[0] Op1
     /* 217150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217154 */     // MIs[0] Op2
     /* 217154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217158 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2152:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEWR_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_B),
     /* 217161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217167 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217170 */     GIR_RootConstrainSelectedInstOperands,
     /* 217171 */     // GIR_Coverage, 3237,
     /* 217171 */     GIR_EraseRootFromParent_Done,
     /* 217172 */   // Label 4171: @217172
     /* 217172 */   GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(217214), // Rule ID 3238 //
     /* 217177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_h),
     /* 217185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 217188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217192 */     // MIs[0] Op1
     /* 217192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217196 */     // MIs[0] Op2
     /* 217196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217200 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2154:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEWR_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_H),
     /* 217203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217207 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217209 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217212 */     GIR_RootConstrainSelectedInstOperands,
     /* 217213 */     // GIR_Coverage, 3238,
     /* 217213 */     GIR_EraseRootFromParent_Done,
     /* 217214 */   // Label 4172: @217214
     /* 217214 */   GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(217256), // Rule ID 3239 //
     /* 217219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_s),
     /* 217227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 217230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217234 */     // MIs[0] Op1
     /* 217234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217238 */     // MIs[0] Op2
     /* 217238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217242 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2155:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEWR_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_S),
     /* 217245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217247 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217249 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217251 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217254 */     GIR_RootConstrainSelectedInstOperands,
     /* 217255 */     // GIR_Coverage, 3239,
     /* 217255 */     GIR_EraseRootFromParent_Done,
     /* 217256 */   // Label 4173: @217256
     /* 217256 */   GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(217298), // Rule ID 3240 //
     /* 217261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_d),
     /* 217269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 217272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217276 */     // MIs[0] Op1
     /* 217276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217280 */     // MIs[0] Op2
     /* 217280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217284 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2153:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEWR_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_D),
     /* 217287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217289 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217291 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217293 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217296 */     GIR_RootConstrainSelectedInstOperands,
     /* 217297 */     // GIR_Coverage, 3240,
     /* 217297 */     GIR_EraseRootFromParent_Done,
     /* 217298 */   // Label 4174: @217298
     /* 217298 */   GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(217340), // Rule ID 12266 //
     /* 217303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_b),
     /* 217311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 217314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217318 */     // MIs[0] Op1
     /* 217318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217322 */     // MIs[0] Op2
     /* 217322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217326 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2148:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILERW_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_B),
     /* 217329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217335 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217338 */     GIR_RootConstrainSelectedInstOperands,
     /* 217339 */     // GIR_Coverage, 12266,
     /* 217339 */     GIR_EraseRootFromParent_Done,
     /* 217340 */   // Label 4175: @217340
     /* 217340 */   GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(217382), // Rule ID 12267 //
     /* 217345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_h),
     /* 217353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 217356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217360 */     // MIs[0] Op1
     /* 217360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217364 */     // MIs[0] Op2
     /* 217364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217368 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2150:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILERW_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_H),
     /* 217371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217373 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217375 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217377 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217380 */     GIR_RootConstrainSelectedInstOperands,
     /* 217381 */     // GIR_Coverage, 12267,
     /* 217381 */     GIR_EraseRootFromParent_Done,
     /* 217382 */   // Label 4176: @217382
     /* 217382 */   GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(217424), // Rule ID 12268 //
     /* 217387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_s),
     /* 217395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 217398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217402 */     // MIs[0] Op1
     /* 217402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217406 */     // MIs[0] Op2
     /* 217406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217410 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2151:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILERW_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_S),
     /* 217413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217417 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217419 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217422 */     GIR_RootConstrainSelectedInstOperands,
     /* 217423 */     // GIR_Coverage, 12268,
     /* 217423 */     GIR_EraseRootFromParent_Done,
     /* 217424 */   // Label 4177: @217424
     /* 217424 */   GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(217466), // Rule ID 12269 //
     /* 217429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 217432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_d),
     /* 217437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 217440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 217444 */     // MIs[0] Op1
     /* 217444 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 217448 */     // MIs[0] Op2
     /* 217448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 217452 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2149:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILERW_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 217452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_D),
     /* 217455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 217457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 217459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 217461 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 217464 */     GIR_RootConstrainSelectedInstOperands,
     /* 217465 */     // GIR_Coverage, 12269,
     /* 217465 */     GIR_EraseRootFromParent_Done,
     /* 217466 */   // Label 4178: @217466
     /* 217466 */   GIM_Reject,
     /* 217467 */ // Label 3282: @217467
     /* 217467 */ GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(260578),
     /* 217472 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /* 217475 */   GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(217588), // Rule ID 2073 //
     /* 217480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 217483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 217488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 217491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 217494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 217497 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 217500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217508 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217512 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 217516 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 217520 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 217524 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 217528 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 217532 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 217536 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 217540 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 217545 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 217549 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 217553 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 217557 */     // MIs[3] Operand 1
     /* 217557 */     // No operand predicates
     /* 217557 */     // MIs[1] Operand 2
     /* 217557 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 217568 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 217570 */     // (intrinsic_wo_chain:{ *:[v4i16] } 696:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 217570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16_indexed),
     /* 217573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217577 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 217583 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 217586 */     GIR_RootConstrainSelectedInstOperands,
     /* 217587 */     // GIR_Coverage, 2073,
     /* 217587 */     GIR_EraseRootFromParent_Done,
     /* 217588 */   // Label 4180: @217588
     /* 217588 */   GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(217701), // Rule ID 2080 //
     /* 217593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 217596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 217601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 217604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 217607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 217610 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 217613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217617 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217621 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 217629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 217633 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 217637 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 217641 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 217645 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 217649 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 217653 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 217658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 217662 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 217666 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 217670 */     // MIs[3] Operand 1
     /* 217670 */     // No operand predicates
     /* 217670 */     // MIs[1] Operand 2
     /* 217670 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 217681 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 217683 */     // (intrinsic_wo_chain:{ *:[v4i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 217683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16_indexed),
     /* 217686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217688 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217690 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 217696 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 217699 */     GIR_RootConstrainSelectedInstOperands,
     /* 217700 */     // GIR_Coverage, 2080,
     /* 217700 */     GIR_EraseRootFromParent_Done,
     /* 217701 */   // Label 4181: @217701
     /* 217701 */   GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(217814), // Rule ID 2076 //
     /* 217706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 217709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 217714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 217717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 217720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 217723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 217726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217734 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 217742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 217746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 217750 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 217754 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 217758 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 217762 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 217766 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217771 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 217775 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 217779 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 217783 */     // MIs[3] Operand 1
     /* 217783 */     // No operand predicates
     /* 217783 */     // MIs[1] Operand 2
     /* 217783 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 217794 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 217796 */     // (intrinsic_wo_chain:{ *:[v2i32] } 696:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 217796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32_indexed),
     /* 217799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 217809 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 217812 */     GIR_RootConstrainSelectedInstOperands,
     /* 217813 */     // GIR_Coverage, 2076,
     /* 217813 */     GIR_EraseRootFromParent_Done,
     /* 217814 */   // Label 4182: @217814
     /* 217814 */   GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(217927), // Rule ID 2083 //
     /* 217819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 217822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 217827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 217830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 217833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 217836 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 217839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217847 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217851 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 217855 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 217859 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 217863 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 217867 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 217871 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 217875 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 217879 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217884 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 217888 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 217892 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 217896 */     // MIs[3] Operand 1
     /* 217896 */     // No operand predicates
     /* 217896 */     // MIs[1] Operand 2
     /* 217896 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 217907 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 217909 */     // (intrinsic_wo_chain:{ *:[v2i32] } 697:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 217909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32_indexed),
     /* 217912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217916 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 217922 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 217925 */     GIR_RootConstrainSelectedInstOperands,
     /* 217926 */     // GIR_Coverage, 2083,
     /* 217926 */     GIR_EraseRootFromParent_Done,
     /* 217927 */   // Label 4183: @217927
     /* 217927 */   GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(218032), // Rule ID 3902 //
     /* 217932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 217935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 217940 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 217943 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 217946 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 217949 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 217952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217956 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217960 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 217968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 217972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 217976 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 217980 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 217984 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 217988 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 217992 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217997 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218001 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218005 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218009 */     // MIs[3] Operand 1
     /* 218009 */     // No operand predicates
     /* 218009 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218011 */     // (intrinsic_wo_chain:{ *:[v4f16] } 767:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 218011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 218014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218016 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218018 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218020 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218024 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 218030 */     GIR_RootConstrainSelectedInstOperands,
     /* 218031 */     // GIR_Coverage, 3902,
     /* 218031 */     GIR_EraseRootFromParent_Done,
     /* 218032 */   // Label 4184: @218032
     /* 218032 */   GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(218137), // Rule ID 3903 //
     /* 218037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 218045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218054 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 218057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218065 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218069 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218073 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218077 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 218081 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218085 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218089 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218093 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218097 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218102 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218106 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218110 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218114 */     // MIs[3] Operand 1
     /* 218114 */     // No operand predicates
     /* 218114 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218116 */     // (intrinsic_wo_chain:{ *:[v4f16] } 770:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 218116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 218119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218129 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 218135 */     GIR_RootConstrainSelectedInstOperands,
     /* 218136 */     // GIR_Coverage, 3903,
     /* 218136 */     GIR_EraseRootFromParent_Done,
     /* 218137 */   // Label 4185: @218137
     /* 218137 */   GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(218242), // Rule ID 3904 //
     /* 218142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 218150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218159 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 218162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218166 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218170 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 218186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218194 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218198 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218202 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218207 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218211 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218215 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218219 */     // MIs[3] Operand 1
     /* 218219 */     // No operand predicates
     /* 218219 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218221 */     // (intrinsic_wo_chain:{ *:[v4f16] } 768:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 218221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 218224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218228 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218230 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218234 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 218240 */     GIR_RootConstrainSelectedInstOperands,
     /* 218241 */     // GIR_Coverage, 3904,
     /* 218241 */     GIR_EraseRootFromParent_Done,
     /* 218242 */   // Label 4186: @218242
     /* 218242 */   GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(218347), // Rule ID 3905 //
     /* 218247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 218255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218264 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 218267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218275 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 218291 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218295 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218299 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218303 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218307 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218312 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218316 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218320 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218324 */     // MIs[3] Operand 1
     /* 218324 */     // No operand predicates
     /* 218324 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218326 */     // (intrinsic_wo_chain:{ *:[v4f16] } 769:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 218326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 218329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218339 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 218345 */     GIR_RootConstrainSelectedInstOperands,
     /* 218346 */     // GIR_Coverage, 3905,
     /* 218346 */     GIR_EraseRootFromParent_Done,
     /* 218347 */   // Label 4187: @218347
     /* 218347 */   GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(218452), // Rule ID 3910 //
     /* 218352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 218360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218369 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 218372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218380 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218404 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218408 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218412 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218417 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218421 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218425 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 218429 */     // MIs[3] Operand 1
     /* 218429 */     // No operand predicates
     /* 218429 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218431 */     // (intrinsic_wo_chain:{ *:[v8f16] } 767:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 218431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 218434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218436 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218438 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218440 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218444 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 218450 */     GIR_RootConstrainSelectedInstOperands,
     /* 218451 */     // GIR_Coverage, 3910,
     /* 218451 */     GIR_EraseRootFromParent_Done,
     /* 218452 */   // Label 4188: @218452
     /* 218452 */   GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(218557), // Rule ID 3911 //
     /* 218457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 218465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218471 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218474 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 218477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218481 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218485 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218501 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218505 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218509 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218513 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218517 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218522 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218526 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218530 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 218534 */     // MIs[3] Operand 1
     /* 218534 */     // No operand predicates
     /* 218534 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218536 */     // (intrinsic_wo_chain:{ *:[v8f16] } 770:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 218536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 218539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218541 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218543 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218549 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 218555 */     GIR_RootConstrainSelectedInstOperands,
     /* 218556 */     // GIR_Coverage, 3911,
     /* 218556 */     GIR_EraseRootFromParent_Done,
     /* 218557 */   // Label 4189: @218557
     /* 218557 */   GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(218662), // Rule ID 3912 //
     /* 218562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 218570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 218582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218586 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218590 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218594 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218598 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218602 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218606 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218610 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218614 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218618 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218622 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218627 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218631 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218635 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 218639 */     // MIs[3] Operand 1
     /* 218639 */     // No operand predicates
     /* 218639 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218641 */     // (intrinsic_wo_chain:{ *:[v8f16] } 768:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 218641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 218644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218646 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218648 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218650 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218654 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 218660 */     GIR_RootConstrainSelectedInstOperands,
     /* 218661 */     // GIR_Coverage, 3912,
     /* 218661 */     GIR_EraseRootFromParent_Done,
     /* 218662 */   // Label 4190: @218662
     /* 218662 */   GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(218767), // Rule ID 3913 //
     /* 218667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 218670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 218675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218681 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218684 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 218687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218695 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218707 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218711 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218715 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 218719 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 218723 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218727 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218732 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218736 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218740 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 218744 */     // MIs[3] Operand 1
     /* 218744 */     // No operand predicates
     /* 218744 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218746 */     // (intrinsic_wo_chain:{ *:[v8f16] } 769:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 218746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 218749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218753 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218759 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 218765 */     GIR_RootConstrainSelectedInstOperands,
     /* 218766 */     // GIR_Coverage, 3913,
     /* 218766 */     GIR_EraseRootFromParent_Done,
     /* 218767 */   // Label 4191: @218767
     /* 218767 */   GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(218872), // Rule ID 3926 //
     /* 218772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 218775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 218780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218789 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 218792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218796 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218800 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218808 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218812 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 218816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 218824 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 218828 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218832 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218837 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218841 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218845 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218849 */     // MIs[3] Operand 1
     /* 218849 */     // No operand predicates
     /* 218849 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218851 */     // (intrinsic_wo_chain:{ *:[v4f32] } 767:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 218851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 218854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218864 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 218870 */     GIR_RootConstrainSelectedInstOperands,
     /* 218871 */     // GIR_Coverage, 3926,
     /* 218871 */     GIR_EraseRootFromParent_Done,
     /* 218872 */   // Label 4192: @218872
     /* 218872 */   GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(218977), // Rule ID 3927 //
     /* 218877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 218880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 218885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218894 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 218897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218901 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218905 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 218913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 218917 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 218921 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 218925 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 218929 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 218933 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 218937 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218942 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 218946 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 218950 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 218954 */     // MIs[3] Operand 1
     /* 218954 */     // No operand predicates
     /* 218954 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 218956 */     // (intrinsic_wo_chain:{ *:[v4f32] } 770:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 218956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 218959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 218969 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 218972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 218975 */     GIR_RootConstrainSelectedInstOperands,
     /* 218976 */     // GIR_Coverage, 3927,
     /* 218976 */     GIR_EraseRootFromParent_Done,
     /* 218977 */   // Label 4193: @218977
     /* 218977 */   GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(219082), // Rule ID 3928 //
     /* 218982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 218985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 218990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218999 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 219002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219010 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219014 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 219018 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 219022 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 219026 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 219030 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 219034 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 219038 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 219042 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219047 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 219051 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 219055 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 219059 */     // MIs[3] Operand 1
     /* 219059 */     // No operand predicates
     /* 219059 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 219061 */     // (intrinsic_wo_chain:{ *:[v4f32] } 768:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 219061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 219064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 219070 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 219074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 219077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 219080 */     GIR_RootConstrainSelectedInstOperands,
     /* 219081 */     // GIR_Coverage, 3928,
     /* 219081 */     GIR_EraseRootFromParent_Done,
     /* 219082 */   // Label 4194: @219082
     /* 219082 */   GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(219187), // Rule ID 3929 //
     /* 219087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 219090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 219095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 219098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 219101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 219104 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 219107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219115 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 219123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 219127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 219131 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 219135 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 219139 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 219143 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 219147 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219152 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 219156 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 219160 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 219164 */     // MIs[3] Operand 1
     /* 219164 */     // No operand predicates
     /* 219164 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 219166 */     // (intrinsic_wo_chain:{ *:[v4f32] } 769:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 219166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 219169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219173 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 219175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 219179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 219182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 219185 */     GIR_RootConstrainSelectedInstOperands,
     /* 219186 */     // GIR_Coverage, 3929,
     /* 219186 */     GIR_EraseRootFromParent_Done,
     /* 219187 */   // Label 4195: @219187
     /* 219187 */   GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(219241), // Rule ID 59 //
     /* 219192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 219195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 219200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219206 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 219209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219213 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219217 */     // MIs[0] Operand 3
     /* 219217 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /* 219228 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
     /* 219232 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, 0:{ *:[i64] })  =>  (PACIZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 219232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIZA),
     /* 219235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219239 */     GIR_RootConstrainSelectedInstOperands,
     /* 219240 */     // GIR_Coverage, 59,
     /* 219240 */     GIR_EraseRootFromParent_Done,
     /* 219241 */   // Label 4196: @219241
     /* 219241 */   GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(219295), // Rule ID 60 //
     /* 219246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 219249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 219254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219260 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 219263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219267 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219271 */     // MIs[0] Operand 3
     /* 219271 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /* 219282 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
     /* 219286 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, 0:{ *:[i64] })  =>  (PACDZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 219286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDZA),
     /* 219289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219291 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219293 */     GIR_RootConstrainSelectedInstOperands,
     /* 219294 */     // GIR_Coverage, 60,
     /* 219294 */     GIR_EraseRootFromParent_Done,
     /* 219295 */   // Label 4197: @219295
     /* 219295 */   GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(219349), // Rule ID 61 //
     /* 219300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 219303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 219308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219314 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 219317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219325 */     // MIs[0] Operand 3
     /* 219325 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /* 219336 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
     /* 219340 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, 0:{ *:[i64] })  =>  (PACIZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 219340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIZB),
     /* 219343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219347 */     GIR_RootConstrainSelectedInstOperands,
     /* 219348 */     // GIR_Coverage, 61,
     /* 219348 */     GIR_EraseRootFromParent_Done,
     /* 219349 */   // Label 4198: @219349
     /* 219349 */   GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(219403), // Rule ID 62 //
     /* 219354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 219357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 219362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 219371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219379 */     // MIs[0] Operand 3
     /* 219379 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /* 219390 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
     /* 219394 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, 0:{ *:[i64] })  =>  (PACDZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 219394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDZB),
     /* 219397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219401 */     GIR_RootConstrainSelectedInstOperands,
     /* 219402 */     // GIR_Coverage, 62,
     /* 219402 */     GIR_EraseRootFromParent_Done,
     /* 219403 */   // Label 4199: @219403
     /* 219403 */   GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(219459), // Rule ID 2652 //
     /* 219408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch),
     /* 219416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 219419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 219422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219426 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219430 */     // MIs[0] pattern
     /* 219430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219433 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219438 */     // MIs[0] imm4
     /* 219438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219441 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219446 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1820:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_ZPiI),
     /* 219449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 219451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 219453 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219455 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219457 */     GIR_RootConstrainSelectedInstOperands,
     /* 219458 */     // GIR_Coverage, 2652,
     /* 219458 */     GIR_EraseRootFromParent_Done,
     /* 219459 */   // Label 4200: @219459
     /* 219459 */   GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(219515), // Rule ID 2661 //
     /* 219464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n32),
     /* 219472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219486 */     // MIs[0] pattern
     /* 219486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219489 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219494 */     // MIs[0] imm4
     /* 219494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219497 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219502 */     // (intrinsic_wo_chain:{ *:[i32] } 2026:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_WPiI),
     /* 219505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219509 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219511 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219513 */     GIR_RootConstrainSelectedInstOperands,
     /* 219514 */     // GIR_Coverage, 2661,
     /* 219514 */     GIR_EraseRootFromParent_Done,
     /* 219515 */   // Label 4201: @219515
     /* 219515 */   GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(219571), // Rule ID 2662 //
     /* 219520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincb_n64),
     /* 219528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219538 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219542 */     // MIs[0] pattern
     /* 219542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219545 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219550 */     // MIs[0] imm4
     /* 219550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219553 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219558 */     // (intrinsic_wo_chain:{ *:[i64] } 1816:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCB_XPiI),
     /* 219561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219565 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219567 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219569 */     GIR_RootConstrainSelectedInstOperands,
     /* 219570 */     // GIR_Coverage, 2662,
     /* 219570 */     GIR_EraseRootFromParent_Done,
     /* 219571 */   // Label 4202: @219571
     /* 219571 */   GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(219627), // Rule ID 10103 //
     /* 219576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n32),
     /* 219584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219594 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219598 */     // MIs[0] pattern
     /* 219598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219601 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219606 */     // MIs[0] imm4
     /* 219606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219609 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219614 */     // (intrinsic_wo_chain:{ *:[i32] } 2012:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_WPiI),
     /* 219617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219621 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219623 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219625 */     GIR_RootConstrainSelectedInstOperands,
     /* 219626 */     // GIR_Coverage, 10103,
     /* 219626 */     GIR_EraseRootFromParent_Done,
     /* 219627 */   // Label 4203: @219627
     /* 219627 */   GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(219683), // Rule ID 10104 //
     /* 219632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n64),
     /* 219640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219654 */     // MIs[0] pattern
     /* 219654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219657 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219662 */     // MIs[0] imm4
     /* 219662 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219665 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219670 */     // (intrinsic_wo_chain:{ *:[i64] } 2027:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_XPiI),
     /* 219673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219675 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219677 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219679 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219681 */     GIR_RootConstrainSelectedInstOperands,
     /* 219682 */     // GIR_Coverage, 10104,
     /* 219682 */     GIR_EraseRootFromParent_Done,
     /* 219683 */   // Label 4204: @219683
     /* 219683 */   GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(219739), // Rule ID 10105 //
     /* 219688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecb_n64),
     /* 219696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219710 */     // MIs[0] pattern
     /* 219710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219713 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219718 */     // MIs[0] imm4
     /* 219718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219721 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219726 */     // (intrinsic_wo_chain:{ *:[i64] } 1782:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECB_XPiI),
     /* 219729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219731 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219733 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219735 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219737 */     GIR_RootConstrainSelectedInstOperands,
     /* 219738 */     // GIR_Coverage, 10105,
     /* 219738 */     GIR_EraseRootFromParent_Done,
     /* 219739 */   // Label 4205: @219739
     /* 219739 */   GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(219795), // Rule ID 10106 //
     /* 219744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n64),
     /* 219752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219766 */     // MIs[0] pattern
     /* 219766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219769 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219774 */     // MIs[0] imm4
     /* 219774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219777 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219782 */     // (intrinsic_wo_chain:{ *:[i64] } 2013:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_XPiI),
     /* 219785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219789 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219791 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219793 */     GIR_RootConstrainSelectedInstOperands,
     /* 219794 */     // GIR_Coverage, 10106,
     /* 219794 */     GIR_EraseRootFromParent_Done,
     /* 219795 */   // Label 4206: @219795
     /* 219795 */   GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(219851), // Rule ID 10109 //
     /* 219800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n32),
     /* 219808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219822 */     // MIs[0] pattern
     /* 219822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219825 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219830 */     // MIs[0] imm4
     /* 219830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219833 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219838 */     // (intrinsic_wo_chain:{ *:[i32] } 2032:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_WPiI),
     /* 219841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219845 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219847 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219849 */     GIR_RootConstrainSelectedInstOperands,
     /* 219850 */     // GIR_Coverage, 10109,
     /* 219850 */     GIR_EraseRootFromParent_Done,
     /* 219851 */   // Label 4207: @219851
     /* 219851 */   GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(219907), // Rule ID 10112 //
     /* 219856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n32),
     /* 219864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219867 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219874 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219878 */     // MIs[0] pattern
     /* 219878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219881 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219886 */     // MIs[0] imm4
     /* 219886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219889 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219894 */     // (intrinsic_wo_chain:{ *:[i32] } 2018:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_WPiI),
     /* 219897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219901 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219903 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219905 */     GIR_RootConstrainSelectedInstOperands,
     /* 219906 */     // GIR_Coverage, 10112,
     /* 219906 */     GIR_EraseRootFromParent_Done,
     /* 219907 */   // Label 4208: @219907
     /* 219907 */   GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(219963), // Rule ID 10113 //
     /* 219912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch_n64),
     /* 219920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219934 */     // MIs[0] pattern
     /* 219934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219937 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219942 */     // MIs[0] imm4
     /* 219942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 219945 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 219950 */     // (intrinsic_wo_chain:{ *:[i64] } 1822:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 219950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_XPiI),
     /* 219953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219957 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 219959 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 219961 */     GIR_RootConstrainSelectedInstOperands,
     /* 219962 */     // GIR_Coverage, 10113,
     /* 219962 */     GIR_EraseRootFromParent_Done,
     /* 219963 */   // Label 4209: @219963
     /* 219963 */   GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(220019), // Rule ID 10114 //
     /* 219968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n64),
     /* 219976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219986 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219990 */     // MIs[0] pattern
     /* 219990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 219993 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 219998 */     // MIs[0] imm4
     /* 219998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220001 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220006 */     // (intrinsic_wo_chain:{ *:[i64] } 2033:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_XPiI),
     /* 220009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220013 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220015 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220017 */     GIR_RootConstrainSelectedInstOperands,
     /* 220018 */     // GIR_Coverage, 10114,
     /* 220018 */     GIR_EraseRootFromParent_Done,
     /* 220019 */   // Label 4210: @220019
     /* 220019 */   GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(220075), // Rule ID 10115 //
     /* 220024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech_n64),
     /* 220032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220046 */     // MIs[0] pattern
     /* 220046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220049 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220054 */     // MIs[0] imm4
     /* 220054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220057 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220062 */     // (intrinsic_wo_chain:{ *:[i64] } 1788:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_XPiI),
     /* 220065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220069 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220071 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220073 */     GIR_RootConstrainSelectedInstOperands,
     /* 220074 */     // GIR_Coverage, 10115,
     /* 220074 */     GIR_EraseRootFromParent_Done,
     /* 220075 */   // Label 4211: @220075
     /* 220075 */   GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(220131), // Rule ID 10116 //
     /* 220080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n64),
     /* 220088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220102 */     // MIs[0] pattern
     /* 220102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220105 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220110 */     // MIs[0] imm4
     /* 220110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220113 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220118 */     // (intrinsic_wo_chain:{ *:[i64] } 2019:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_XPiI),
     /* 220121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220125 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220127 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220129 */     GIR_RootConstrainSelectedInstOperands,
     /* 220130 */     // GIR_Coverage, 10116,
     /* 220130 */     GIR_EraseRootFromParent_Done,
     /* 220131 */   // Label 4212: @220131
     /* 220131 */   GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(220187), // Rule ID 10119 //
     /* 220136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n32),
     /* 220144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220158 */     // MIs[0] pattern
     /* 220158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220161 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220166 */     // MIs[0] imm4
     /* 220166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220169 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220174 */     // (intrinsic_wo_chain:{ *:[i32] } 2038:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_WPiI),
     /* 220177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220179 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220181 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220183 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220185 */     GIR_RootConstrainSelectedInstOperands,
     /* 220186 */     // GIR_Coverage, 10119,
     /* 220186 */     GIR_EraseRootFromParent_Done,
     /* 220187 */   // Label 4213: @220187
     /* 220187 */   GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(220243), // Rule ID 10122 //
     /* 220192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n32),
     /* 220200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220214 */     // MIs[0] pattern
     /* 220214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220217 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220222 */     // MIs[0] imm4
     /* 220222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220225 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220230 */     // (intrinsic_wo_chain:{ *:[i32] } 2024:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_WPiI),
     /* 220233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220237 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220239 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220241 */     GIR_RootConstrainSelectedInstOperands,
     /* 220242 */     // GIR_Coverage, 10122,
     /* 220242 */     GIR_EraseRootFromParent_Done,
     /* 220243 */   // Label 4214: @220243
     /* 220243 */   GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(220299), // Rule ID 10123 //
     /* 220248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw_n64),
     /* 220256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220266 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220270 */     // MIs[0] pattern
     /* 220270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220273 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220278 */     // MIs[0] imm4
     /* 220278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220281 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220286 */     // (intrinsic_wo_chain:{ *:[i64] } 1828:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_XPiI),
     /* 220289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220291 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220293 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220295 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220297 */     GIR_RootConstrainSelectedInstOperands,
     /* 220298 */     // GIR_Coverage, 10123,
     /* 220298 */     GIR_EraseRootFromParent_Done,
     /* 220299 */   // Label 4215: @220299
     /* 220299 */   GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(220355), // Rule ID 10124 //
     /* 220304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n64),
     /* 220312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220322 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220326 */     // MIs[0] pattern
     /* 220326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220329 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220334 */     // MIs[0] imm4
     /* 220334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220337 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220342 */     // (intrinsic_wo_chain:{ *:[i64] } 2039:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_XPiI),
     /* 220345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220349 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220351 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220353 */     GIR_RootConstrainSelectedInstOperands,
     /* 220354 */     // GIR_Coverage, 10124,
     /* 220354 */     GIR_EraseRootFromParent_Done,
     /* 220355 */   // Label 4216: @220355
     /* 220355 */   GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(220411), // Rule ID 10125 //
     /* 220360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw_n64),
     /* 220368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220382 */     // MIs[0] pattern
     /* 220382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220385 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220390 */     // MIs[0] imm4
     /* 220390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220393 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220398 */     // (intrinsic_wo_chain:{ *:[i64] } 1794:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_XPiI),
     /* 220401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220405 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220407 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220409 */     GIR_RootConstrainSelectedInstOperands,
     /* 220410 */     // GIR_Coverage, 10125,
     /* 220410 */     GIR_EraseRootFromParent_Done,
     /* 220411 */   // Label 4217: @220411
     /* 220411 */   GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(220467), // Rule ID 10126 //
     /* 220416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n64),
     /* 220424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220434 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220438 */     // MIs[0] pattern
     /* 220438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220441 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220446 */     // MIs[0] imm4
     /* 220446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220449 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220454 */     // (intrinsic_wo_chain:{ *:[i64] } 2025:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_XPiI),
     /* 220457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220461 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220463 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220465 */     GIR_RootConstrainSelectedInstOperands,
     /* 220466 */     // GIR_Coverage, 10126,
     /* 220466 */     GIR_EraseRootFromParent_Done,
     /* 220467 */   // Label 4218: @220467
     /* 220467 */   GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(220523), // Rule ID 10129 //
     /* 220472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n32),
     /* 220480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220490 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220494 */     // MIs[0] pattern
     /* 220494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220497 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220502 */     // MIs[0] imm4
     /* 220502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220505 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220510 */     // (intrinsic_wo_chain:{ *:[i32] } 2029:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_WPiI),
     /* 220513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220517 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220519 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220521 */     GIR_RootConstrainSelectedInstOperands,
     /* 220522 */     // GIR_Coverage, 10129,
     /* 220522 */     GIR_EraseRootFromParent_Done,
     /* 220523 */   // Label 4219: @220523
     /* 220523 */   GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(220579), // Rule ID 10132 //
     /* 220528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n32),
     /* 220536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220546 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220550 */     // MIs[0] pattern
     /* 220550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220553 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220558 */     // MIs[0] imm4
     /* 220558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220561 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220566 */     // (intrinsic_wo_chain:{ *:[i32] } 2015:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_WPiI),
     /* 220569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220573 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220575 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220577 */     GIR_RootConstrainSelectedInstOperands,
     /* 220578 */     // GIR_Coverage, 10132,
     /* 220578 */     GIR_EraseRootFromParent_Done,
     /* 220579 */   // Label 4220: @220579
     /* 220579 */   GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(220635), // Rule ID 10133 //
     /* 220584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd_n64),
     /* 220592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220602 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220606 */     // MIs[0] pattern
     /* 220606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220609 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220614 */     // MIs[0] imm4
     /* 220614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220617 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220622 */     // (intrinsic_wo_chain:{ *:[i64] } 1819:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_XPiI),
     /* 220625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220627 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220629 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220631 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220633 */     GIR_RootConstrainSelectedInstOperands,
     /* 220634 */     // GIR_Coverage, 10133,
     /* 220634 */     GIR_EraseRootFromParent_Done,
     /* 220635 */   // Label 4221: @220635
     /* 220635 */   GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(220691), // Rule ID 10134 //
     /* 220640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n64),
     /* 220648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220662 */     // MIs[0] pattern
     /* 220662 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220665 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220670 */     // MIs[0] imm4
     /* 220670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220673 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220678 */     // (intrinsic_wo_chain:{ *:[i64] } 2030:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_XPiI),
     /* 220681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220683 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220685 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220687 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220689 */     GIR_RootConstrainSelectedInstOperands,
     /* 220690 */     // GIR_Coverage, 10134,
     /* 220690 */     GIR_EraseRootFromParent_Done,
     /* 220691 */   // Label 4222: @220691
     /* 220691 */   GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(220747), // Rule ID 10135 //
     /* 220696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd_n64),
     /* 220704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220718 */     // MIs[0] pattern
     /* 220718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220721 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220726 */     // MIs[0] imm4
     /* 220726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220729 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220734 */     // (intrinsic_wo_chain:{ *:[i64] } 1785:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_XPiI),
     /* 220737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220741 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220743 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220745 */     GIR_RootConstrainSelectedInstOperands,
     /* 220746 */     // GIR_Coverage, 10135,
     /* 220746 */     GIR_EraseRootFromParent_Done,
     /* 220747 */   // Label 4223: @220747
     /* 220747 */   GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(220803), // Rule ID 10136 //
     /* 220752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n64),
     /* 220760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220774 */     // MIs[0] pattern
     /* 220774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220777 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220782 */     // MIs[0] imm4
     /* 220782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220785 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220790 */     // (intrinsic_wo_chain:{ *:[i64] } 2016:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_XPiI),
     /* 220793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220797 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220799 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220801 */     GIR_RootConstrainSelectedInstOperands,
     /* 220802 */     // GIR_Coverage, 10136,
     /* 220802 */     GIR_EraseRootFromParent_Done,
     /* 220803 */   // Label 4224: @220803
     /* 220803 */   GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(220859), // Rule ID 10137 //
     /* 220808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch),
     /* 220816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 220819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 220822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220826 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220830 */     // MIs[0] pattern
     /* 220830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220833 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220838 */     // MIs[0] imm4
     /* 220838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220841 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220846 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2031:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_ZPiI),
     /* 220849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 220851 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 220853 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220855 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220857 */     GIR_RootConstrainSelectedInstOperands,
     /* 220858 */     // GIR_Coverage, 10137,
     /* 220858 */     GIR_EraseRootFromParent_Done,
     /* 220859 */   // Label 4225: @220859
     /* 220859 */   GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(220915), // Rule ID 10138 //
     /* 220864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech),
     /* 220872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 220875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 220878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220882 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220886 */     // MIs[0] pattern
     /* 220886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220889 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220894 */     // MIs[0] imm4
     /* 220894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220897 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220902 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1786:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_ZPiI),
     /* 220905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 220907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 220909 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220911 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220913 */     GIR_RootConstrainSelectedInstOperands,
     /* 220914 */     // GIR_Coverage, 10138,
     /* 220914 */     GIR_EraseRootFromParent_Done,
     /* 220915 */   // Label 4226: @220915
     /* 220915 */   GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(220971), // Rule ID 10139 //
     /* 220920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech),
     /* 220928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 220931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 220934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220938 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220942 */     // MIs[0] pattern
     /* 220942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 220945 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 220950 */     // MIs[0] imm4
     /* 220950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 220953 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 220958 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2017:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 220958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_ZPiI),
     /* 220961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 220963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 220965 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 220967 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 220969 */     GIR_RootConstrainSelectedInstOperands,
     /* 220970 */     // GIR_Coverage, 10139,
     /* 220970 */     GIR_EraseRootFromParent_Done,
     /* 220971 */   // Label 4227: @220971
     /* 220971 */   GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(221027), // Rule ID 10140 //
     /* 220976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw),
     /* 220984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 220987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 220990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 220998 */     // MIs[0] pattern
     /* 220998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221001 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221006 */     // MIs[0] imm4
     /* 221006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221009 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221014 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1826:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_ZPiI),
     /* 221017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221019 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221021 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221023 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221025 */     GIR_RootConstrainSelectedInstOperands,
     /* 221026 */     // GIR_Coverage, 10140,
     /* 221026 */     GIR_EraseRootFromParent_Done,
     /* 221027 */   // Label 4228: @221027
     /* 221027 */   GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(221083), // Rule ID 10141 //
     /* 221032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw),
     /* 221040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 221043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 221046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221054 */     // MIs[0] pattern
     /* 221054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221057 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221062 */     // MIs[0] imm4
     /* 221062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221065 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221070 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2037:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_ZPiI),
     /* 221073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221077 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221079 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221081 */     GIR_RootConstrainSelectedInstOperands,
     /* 221082 */     // GIR_Coverage, 10141,
     /* 221082 */     GIR_EraseRootFromParent_Done,
     /* 221083 */   // Label 4229: @221083
     /* 221083 */   GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(221139), // Rule ID 10142 //
     /* 221088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw),
     /* 221096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 221099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 221102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221106 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221110 */     // MIs[0] pattern
     /* 221110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221113 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221118 */     // MIs[0] imm4
     /* 221118 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221121 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221126 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1792:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_ZPiI),
     /* 221129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221131 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221133 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221135 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221137 */     GIR_RootConstrainSelectedInstOperands,
     /* 221138 */     // GIR_Coverage, 10142,
     /* 221138 */     GIR_EraseRootFromParent_Done,
     /* 221139 */   // Label 4230: @221139
     /* 221139 */   GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(221195), // Rule ID 10143 //
     /* 221144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw),
     /* 221152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 221155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 221158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221166 */     // MIs[0] pattern
     /* 221166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221169 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221174 */     // MIs[0] imm4
     /* 221174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221177 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221182 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2023:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_ZPiI),
     /* 221185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221189 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221191 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221193 */     GIR_RootConstrainSelectedInstOperands,
     /* 221194 */     // GIR_Coverage, 10143,
     /* 221194 */     GIR_EraseRootFromParent_Done,
     /* 221195 */   // Label 4231: @221195
     /* 221195 */   GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(221251), // Rule ID 10144 //
     /* 221200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd),
     /* 221208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 221211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 221214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221218 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221222 */     // MIs[0] pattern
     /* 221222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221225 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221230 */     // MIs[0] imm4
     /* 221230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221233 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221238 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1817:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_ZPiI),
     /* 221241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221245 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221247 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221249 */     GIR_RootConstrainSelectedInstOperands,
     /* 221250 */     // GIR_Coverage, 10144,
     /* 221250 */     GIR_EraseRootFromParent_Done,
     /* 221251 */   // Label 4232: @221251
     /* 221251 */   GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(221307), // Rule ID 10145 //
     /* 221256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd),
     /* 221264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 221267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 221270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221274 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221278 */     // MIs[0] pattern
     /* 221278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221281 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221286 */     // MIs[0] imm4
     /* 221286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221289 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221294 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2028:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_ZPiI),
     /* 221297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221299 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221301 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221303 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221305 */     GIR_RootConstrainSelectedInstOperands,
     /* 221306 */     // GIR_Coverage, 10145,
     /* 221306 */     GIR_EraseRootFromParent_Done,
     /* 221307 */   // Label 4233: @221307
     /* 221307 */   GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(221363), // Rule ID 10146 //
     /* 221312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd),
     /* 221320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 221323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 221326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221334 */     // MIs[0] pattern
     /* 221334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221337 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221342 */     // MIs[0] imm4
     /* 221342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221345 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221350 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1783:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_ZPiI),
     /* 221353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221357 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221359 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221361 */     GIR_RootConstrainSelectedInstOperands,
     /* 221362 */     // GIR_Coverage, 10146,
     /* 221362 */     GIR_EraseRootFromParent_Done,
     /* 221363 */   // Label 4234: @221363
     /* 221363 */   GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(221419), // Rule ID 10147 //
     /* 221368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 221371 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd),
     /* 221376 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 221379 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 221382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221386 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 221390 */     // MIs[0] pattern
     /* 221390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 221393 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 221398 */     // MIs[0] imm4
     /* 221398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 221401 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 221406 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2014:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 221406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_ZPiI),
     /* 221409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 221411 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 221413 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 221415 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 221417 */     GIR_RootConstrainSelectedInstOperands,
     /* 221418 */     // GIR_Coverage, 10147,
     /* 221418 */     GIR_EraseRootFromParent_Done,
     /* 221419 */   // Label 4235: @221419
     /* 221419 */   GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(221509), // Rule ID 47 //
     /* 221424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 221432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 221435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 221438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 221441 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 221444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221448 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221452 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221460 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221464 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221468 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221472 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221477 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221481 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221485 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221489 */     // MIs[2] Operand 1
     /* 221489 */     // No operand predicates
     /* 221489 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221491 */     // (intrinsic_wo_chain:{ *:[v2f32] } 616:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLALlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev4f16),
     /* 221494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221498 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221500 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221504 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221507 */     GIR_RootConstrainSelectedInstOperands,
     /* 221508 */     // GIR_Coverage, 47,
     /* 221508 */     GIR_EraseRootFromParent_Done,
     /* 221509 */   // Label 4236: @221509
     /* 221509 */   GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(221599), // Rule ID 48 //
     /* 221514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 221522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 221525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 221528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 221531 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 221534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221538 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221542 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221562 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221571 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221575 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221579 */     // MIs[2] Operand 1
     /* 221579 */     // No operand predicates
     /* 221579 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221581 */     // (intrinsic_wo_chain:{ *:[v4f32] } 616:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLALlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev8f16),
     /* 221584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221586 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221588 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221594 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221597 */     GIR_RootConstrainSelectedInstOperands,
     /* 221598 */     // GIR_Coverage, 48,
     /* 221598 */     GIR_EraseRootFromParent_Done,
     /* 221599 */   // Label 4237: @221599
     /* 221599 */   GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(221689), // Rule ID 49 //
     /* 221604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 221612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 221615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 221618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 221621 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 221624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221632 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221657 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221661 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221665 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221669 */     // MIs[2] Operand 1
     /* 221669 */     // No operand predicates
     /* 221669 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221671 */     // (intrinsic_wo_chain:{ *:[v2f32] } 618:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSLlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev4f16),
     /* 221674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221678 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221684 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221687 */     GIR_RootConstrainSelectedInstOperands,
     /* 221688 */     // GIR_Coverage, 49,
     /* 221688 */     GIR_EraseRootFromParent_Done,
     /* 221689 */   // Label 4238: @221689
     /* 221689 */   GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(221779), // Rule ID 50 //
     /* 221694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 221702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 221705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 221708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 221711 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 221714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221722 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221742 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221755 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221759 */     // MIs[2] Operand 1
     /* 221759 */     // No operand predicates
     /* 221759 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221761 */     // (intrinsic_wo_chain:{ *:[v4f32] } 618:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSLlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev8f16),
     /* 221764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221768 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221770 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221774 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221777 */     GIR_RootConstrainSelectedInstOperands,
     /* 221778 */     // GIR_Coverage, 50,
     /* 221778 */     GIR_EraseRootFromParent_Done,
     /* 221779 */   // Label 4239: @221779
     /* 221779 */   GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(221869), // Rule ID 51 //
     /* 221784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 221792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 221795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 221798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 221801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 221804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221808 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221812 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221824 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221828 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221832 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221837 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221841 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221845 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221849 */     // MIs[2] Operand 1
     /* 221849 */     // No operand predicates
     /* 221849 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221851 */     // (intrinsic_wo_chain:{ *:[v2f32] } 617:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLAL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev4f16),
     /* 221854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221864 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221867 */     GIR_RootConstrainSelectedInstOperands,
     /* 221868 */     // GIR_Coverage, 51,
     /* 221868 */     GIR_EraseRootFromParent_Done,
     /* 221869 */   // Label 4240: @221869
     /* 221869 */   GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(221959), // Rule ID 52 //
     /* 221874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 221882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 221885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 221888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 221891 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 221894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221898 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221902 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221906 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 221910 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 221914 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 221918 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 221922 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 221927 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 221931 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 221935 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 221939 */     // MIs[2] Operand 1
     /* 221939 */     // No operand predicates
     /* 221939 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 221941 */     // (intrinsic_wo_chain:{ *:[v4f32] } 617:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLAL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 221941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev8f16),
     /* 221944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221950 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 221954 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 221957 */     GIR_RootConstrainSelectedInstOperands,
     /* 221958 */     // GIR_Coverage, 52,
     /* 221958 */     GIR_EraseRootFromParent_Done,
     /* 221959 */   // Label 4241: @221959
     /* 221959 */   GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(222049), // Rule ID 53 //
     /* 221964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 221967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 221972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 221975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 221978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 221981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 221984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221992 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222017 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222021 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222025 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222029 */     // MIs[2] Operand 1
     /* 222029 */     // No operand predicates
     /* 222029 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222031 */     // (intrinsic_wo_chain:{ *:[v2f32] } 619:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev4f16),
     /* 222034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222044 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222047 */     GIR_RootConstrainSelectedInstOperands,
     /* 222048 */     // GIR_Coverage, 53,
     /* 222048 */     GIR_EraseRootFromParent_Done,
     /* 222049 */   // Label 4242: @222049
     /* 222049 */   GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(222139), // Rule ID 54 //
     /* 222054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 222057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 222062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 222065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 222068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 222071 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 222074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222078 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222082 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222090 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222094 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222098 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222102 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222107 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222111 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222115 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222119 */     // MIs[2] Operand 1
     /* 222119 */     // No operand predicates
     /* 222119 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222121 */     // (intrinsic_wo_chain:{ *:[v4f32] } 619:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev8f16),
     /* 222124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222134 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222137 */     GIR_RootConstrainSelectedInstOperands,
     /* 222138 */     // GIR_Coverage, 54,
     /* 222138 */     GIR_EraseRootFromParent_Done,
     /* 222139 */   // Label 4243: @222139
     /* 222139 */   GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(222229), // Rule ID 2074 //
     /* 222144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 222152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 222155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 222158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 222161 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 222164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222168 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222172 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222205 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222209 */     // MIs[2] Operand 1
     /* 222209 */     // No operand predicates
     /* 222209 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222211 */     // (intrinsic_wo_chain:{ *:[v4i16] } 696:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16_indexed),
     /* 222214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222224 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222227 */     GIR_RootConstrainSelectedInstOperands,
     /* 222228 */     // GIR_Coverage, 2074,
     /* 222228 */     GIR_EraseRootFromParent_Done,
     /* 222229 */   // Label 4244: @222229
     /* 222229 */   GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(222319), // Rule ID 2075 //
     /* 222234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 222242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 222245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 222248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 222251 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 222254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222262 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222278 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222282 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222287 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222291 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222295 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222299 */     // MIs[2] Operand 1
     /* 222299 */     // No operand predicates
     /* 222299 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222301 */     // (intrinsic_wo_chain:{ *:[v8i16] } 696:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLAHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16_indexed),
     /* 222304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222308 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222310 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222314 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222317 */     GIR_RootConstrainSelectedInstOperands,
     /* 222318 */     // GIR_Coverage, 2075,
     /* 222318 */     GIR_EraseRootFromParent_Done,
     /* 222319 */   // Label 4245: @222319
     /* 222319 */   GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(222409), // Rule ID 2081 //
     /* 222324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 222332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 222335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 222338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 222341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 222344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222352 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222360 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222364 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222368 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222372 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222377 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222381 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222385 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222389 */     // MIs[2] Operand 1
     /* 222389 */     // No operand predicates
     /* 222389 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222391 */     // (intrinsic_wo_chain:{ *:[v4i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16_indexed),
     /* 222394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222404 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222407 */     GIR_RootConstrainSelectedInstOperands,
     /* 222408 */     // GIR_Coverage, 2081,
     /* 222408 */     GIR_EraseRootFromParent_Done,
     /* 222409 */   // Label 4246: @222409
     /* 222409 */   GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(222499), // Rule ID 2082 //
     /* 222414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 222422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 222425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 222428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 222431 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 222434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222438 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222442 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 222454 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 222458 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222462 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 222467 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222471 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222475 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 222479 */     // MIs[2] Operand 1
     /* 222479 */     // No operand predicates
     /* 222479 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222481 */     // (intrinsic_wo_chain:{ *:[v8i16] } 697:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLSHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16_indexed),
     /* 222484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222494 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222497 */     GIR_RootConstrainSelectedInstOperands,
     /* 222498 */     // GIR_Coverage, 2082,
     /* 222498 */     GIR_EraseRootFromParent_Done,
     /* 222499 */   // Label 4247: @222499
     /* 222499 */   GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(222589), // Rule ID 2077 //
     /* 222504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 222512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 222515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 222518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 222521 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 222524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222528 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222532 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222536 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222540 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 222544 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222548 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222552 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222557 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222561 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222565 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 222569 */     // MIs[2] Operand 1
     /* 222569 */     // No operand predicates
     /* 222569 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222571 */     // (intrinsic_wo_chain:{ *:[v2i32] } 696:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32_indexed),
     /* 222574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222578 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222580 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222584 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222587 */     GIR_RootConstrainSelectedInstOperands,
     /* 222588 */     // GIR_Coverage, 2077,
     /* 222588 */     GIR_EraseRootFromParent_Done,
     /* 222589 */   // Label 4248: @222589
     /* 222589 */   GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(222679), // Rule ID 2078 //
     /* 222594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 222602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 222605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 222608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 222611 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 222614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222622 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 222634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222638 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222642 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222647 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222651 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222655 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 222659 */     // MIs[2] Operand 1
     /* 222659 */     // No operand predicates
     /* 222659 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222661 */     // (intrinsic_wo_chain:{ *:[v4i32] } 696:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32_indexed),
     /* 222664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222668 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222670 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222674 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222677 */     GIR_RootConstrainSelectedInstOperands,
     /* 222678 */     // GIR_Coverage, 2078,
     /* 222678 */     GIR_EraseRootFromParent_Done,
     /* 222679 */   // Label 4249: @222679
     /* 222679 */   GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(222769), // Rule ID 2084 //
     /* 222684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 222692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 222695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 222698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 222701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 222704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222712 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 222724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222728 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222745 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 222749 */     // MIs[2] Operand 1
     /* 222749 */     // No operand predicates
     /* 222749 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222751 */     // (intrinsic_wo_chain:{ *:[v2i32] } 697:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32_indexed),
     /* 222754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222764 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222767 */     GIR_RootConstrainSelectedInstOperands,
     /* 222768 */     // GIR_Coverage, 2084,
     /* 222768 */     GIR_EraseRootFromParent_Done,
     /* 222769 */   // Label 4250: @222769
     /* 222769 */   GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(222859), // Rule ID 2085 //
     /* 222774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 222782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 222785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 222788 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 222791 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 222794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222798 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222802 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 222814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222818 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222822 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222835 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 222839 */     // MIs[2] Operand 1
     /* 222839 */     // No operand predicates
     /* 222839 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222841 */     // (intrinsic_wo_chain:{ *:[v4i32] } 697:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32_indexed),
     /* 222844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222846 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222850 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222854 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222857 */     GIR_RootConstrainSelectedInstOperands,
     /* 222858 */     // GIR_Coverage, 2085,
     /* 222858 */     GIR_EraseRootFromParent_Done,
     /* 222859 */   // Label 4251: @222859
     /* 222859 */   GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(222949), // Rule ID 2079 //
     /* 222864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 222872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 222881 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 222884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222888 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222892 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 222904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222908 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 222912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 222917 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 222921 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 222925 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 222929 */     // MIs[2] Operand 1
     /* 222929 */     // No operand predicates
     /* 222929 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 222931 */     // (intrinsic_wo_chain:{ *:[i32] } 696:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 222931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32_indexed),
     /* 222934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222938 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222940 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 222944 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 222947 */     GIR_RootConstrainSelectedInstOperands,
     /* 222948 */     // GIR_Coverage, 2079,
     /* 222948 */     GIR_EraseRootFromParent_Done,
     /* 222949 */   // Label 4252: @222949
     /* 222949 */   GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(223039), // Rule ID 2086 //
     /* 222954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 222957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 222962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 222971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 222974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222978 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222982 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222986 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 222990 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 222994 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 222998 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 223002 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 223007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 223011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 223015 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 223019 */     // MIs[2] Operand 1
     /* 223019 */     // No operand predicates
     /* 223019 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223021 */     // (intrinsic_wo_chain:{ *:[i32] } 697:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 223021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32_indexed),
     /* 223024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 223026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 223028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 223030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 223034 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 223037 */     GIR_RootConstrainSelectedInstOperands,
     /* 223038 */     // GIR_Coverage, 2086,
     /* 223038 */     GIR_EraseRootFromParent_Done,
     /* 223039 */   // Label 4253: @223039
     /* 223039 */   GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(223116), // Rule ID 2781 //
     /* 223044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 223055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 223061 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 223064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223068 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223072 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223080 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223084 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 223088 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223092 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223096 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223100 */     // MIs[2] Operand 1
     /* 223100 */     // No operand predicates
     /* 223100 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223102 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 223102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_H),
     /* 223105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223114 */     GIR_RootConstrainSelectedInstOperands,
     /* 223115 */     // GIR_Coverage, 2781,
     /* 223115 */     GIR_EraseRootFromParent_Done,
     /* 223116 */   // Label 4254: @223116
     /* 223116 */   GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(223193), // Rule ID 2782 //
     /* 223121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 223132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 223138 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 223141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223153 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223157 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223161 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 223165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223173 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223177 */     // MIs[2] Operand 1
     /* 223177 */     // No operand predicates
     /* 223177 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223179 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 223179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_H),
     /* 223182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223186 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223191 */     GIR_RootConstrainSelectedInstOperands,
     /* 223192 */     // GIR_Coverage, 2782,
     /* 223192 */     GIR_EraseRootFromParent_Done,
     /* 223193 */   // Label 4255: @223193
     /* 223193 */   GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(223270), // Rule ID 2783 //
     /* 223198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 223209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 223212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 223215 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 223218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223222 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223226 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223230 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223234 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223238 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 223242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223250 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223254 */     // MIs[2] Operand 1
     /* 223254 */     // No operand predicates
     /* 223254 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223256 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 223256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_S),
     /* 223259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223268 */     GIR_RootConstrainSelectedInstOperands,
     /* 223269 */     // GIR_Coverage, 2783,
     /* 223269 */     GIR_EraseRootFromParent_Done,
     /* 223270 */   // Label 4256: @223270
     /* 223270 */   GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(223347), // Rule ID 2784 //
     /* 223275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 223286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 223289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 223292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 223295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223307 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 223319 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223323 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223327 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223331 */     // MIs[2] Operand 1
     /* 223331 */     // No operand predicates
     /* 223331 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223333 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 223333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_S),
     /* 223336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223345 */     GIR_RootConstrainSelectedInstOperands,
     /* 223346 */     // GIR_Coverage, 2784,
     /* 223346 */     GIR_EraseRootFromParent_Done,
     /* 223347 */   // Label 4257: @223347
     /* 223347 */   GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(223424), // Rule ID 2785 //
     /* 223352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 223363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 223366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 223369 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 223372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223380 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 223396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223404 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223408 */     // MIs[2] Operand 1
     /* 223408 */     // No operand predicates
     /* 223408 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223410 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 223410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_D),
     /* 223413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223417 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223422 */     GIR_RootConstrainSelectedInstOperands,
     /* 223423 */     // GIR_Coverage, 2785,
     /* 223423 */     GIR_EraseRootFromParent_Done,
     /* 223424 */   // Label 4258: @223424
     /* 223424 */   GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(223501), // Rule ID 2786 //
     /* 223429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 223437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 223440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 223443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 223446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 223449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223457 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 223473 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223477 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223481 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223485 */     // MIs[2] Operand 1
     /* 223485 */     // No operand predicates
     /* 223485 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223487 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1373:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 223487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_D),
     /* 223490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223492 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223494 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223499 */     GIR_RootConstrainSelectedInstOperands,
     /* 223500 */     // GIR_Coverage, 2786,
     /* 223500 */     GIR_EraseRootFromParent_Done,
     /* 223501 */   // Label 4259: @223501
     /* 223501 */   GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(223578), // Rule ID 7965 //
     /* 223506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 223517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 223523 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 223526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223534 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223538 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223542 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223546 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 223550 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223554 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223558 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223562 */     // MIs[2] Operand 1
     /* 223562 */     // No operand predicates
     /* 223562 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223564 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 223564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_H),
     /* 223567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223576 */     GIR_RootConstrainSelectedInstOperands,
     /* 223577 */     // GIR_Coverage, 7965,
     /* 223577 */     GIR_EraseRootFromParent_Done,
     /* 223578 */   // Label 4260: @223578
     /* 223578 */   GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(223655), // Rule ID 7966 //
     /* 223583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 223594 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223597 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 223600 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 223603 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223607 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223611 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223615 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223619 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223623 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 223627 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223631 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223635 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223639 */     // MIs[2] Operand 1
     /* 223639 */     // No operand predicates
     /* 223639 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223641 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 223641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_H),
     /* 223644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223646 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223648 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223653 */     GIR_RootConstrainSelectedInstOperands,
     /* 223654 */     // GIR_Coverage, 7966,
     /* 223654 */     GIR_EraseRootFromParent_Done,
     /* 223655 */   // Label 4261: @223655
     /* 223655 */   GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(223732), // Rule ID 7967 //
     /* 223660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 223671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 223674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 223677 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 223680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223688 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223700 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 223704 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223708 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223712 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223716 */     // MIs[2] Operand 1
     /* 223716 */     // No operand predicates
     /* 223716 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223718 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 223718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_S),
     /* 223721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223730 */     GIR_RootConstrainSelectedInstOperands,
     /* 223731 */     // GIR_Coverage, 7967,
     /* 223731 */     GIR_EraseRootFromParent_Done,
     /* 223732 */   // Label 4262: @223732
     /* 223732 */   GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(223809), // Rule ID 7968 //
     /* 223737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 223748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 223751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 223754 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 223757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223765 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 223781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223789 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223793 */     // MIs[2] Operand 1
     /* 223793 */     // No operand predicates
     /* 223793 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223795 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 223795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_S),
     /* 223798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223802 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223807 */     GIR_RootConstrainSelectedInstOperands,
     /* 223808 */     // GIR_Coverage, 7968,
     /* 223808 */     GIR_EraseRootFromParent_Done,
     /* 223809 */   // Label 4263: @223809
     /* 223809 */   GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(223886), // Rule ID 7969 //
     /* 223814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 223825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 223828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 223831 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 223834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223838 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223842 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223846 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223850 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223854 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 223858 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223862 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223866 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 223870 */     // MIs[2] Operand 1
     /* 223870 */     // No operand predicates
     /* 223870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223872 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 223872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_D),
     /* 223875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223879 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 223884 */     GIR_RootConstrainSelectedInstOperands,
     /* 223885 */     // GIR_Coverage, 7969,
     /* 223885 */     GIR_EraseRootFromParent_Done,
     /* 223886 */   // Label 4264: @223886
     /* 223886 */   GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(223963), // Rule ID 7970 //
     /* 223891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 223899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 223902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 223905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 223908 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 223911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223919 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223923 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 223927 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 223931 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 223935 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 223939 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 223943 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 223947 */     // MIs[2] Operand 1
     /* 223947 */     // No operand predicates
     /* 223947 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 223949 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1549:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 223949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_D),
     /* 223952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 223954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 223956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 223958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 223961 */     GIR_RootConstrainSelectedInstOperands,
     /* 223962 */     // GIR_Coverage, 7970,
     /* 223962 */     GIR_EraseRootFromParent_Done,
     /* 223963 */   // Label 4265: @223963
     /* 223963 */   GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(224040), // Rule ID 7971 //
     /* 223968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 223976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 223979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 223985 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 223988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 223996 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224008 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 224012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224020 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224024 */     // MIs[2] Operand 1
     /* 224024 */     // No operand predicates
     /* 224024 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224026 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 224026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_H),
     /* 224029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224031 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224033 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224038 */     GIR_RootConstrainSelectedInstOperands,
     /* 224039 */     // GIR_Coverage, 7971,
     /* 224039 */     GIR_EraseRootFromParent_Done,
     /* 224040 */   // Label 4266: @224040
     /* 224040 */   GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(224117), // Rule ID 7972 //
     /* 224045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 224053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224059 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224062 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 224065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224069 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224073 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 224089 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224093 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224097 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 224101 */     // MIs[2] Operand 1
     /* 224101 */     // No operand predicates
     /* 224101 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224103 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 224103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_H),
     /* 224106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224110 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224115 */     GIR_RootConstrainSelectedInstOperands,
     /* 224116 */     // GIR_Coverage, 7972,
     /* 224116 */     GIR_EraseRootFromParent_Done,
     /* 224117 */   // Label 4267: @224117
     /* 224117 */   GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(224194), // Rule ID 7973 //
     /* 224122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 224130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 224136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224139 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 224142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224146 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224150 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224154 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224158 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224162 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 224166 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224170 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224174 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224178 */     // MIs[2] Operand 1
     /* 224178 */     // No operand predicates
     /* 224178 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224180 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 224180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_S),
     /* 224183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224185 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224187 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224192 */     GIR_RootConstrainSelectedInstOperands,
     /* 224193 */     // GIR_Coverage, 7973,
     /* 224193 */     GIR_EraseRootFromParent_Done,
     /* 224194 */   // Label 4268: @224194
     /* 224194 */   GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(224271), // Rule ID 7974 //
     /* 224199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 224207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 224213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224216 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 224219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224223 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224227 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224231 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224235 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224239 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 224243 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224247 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224251 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 224255 */     // MIs[2] Operand 1
     /* 224255 */     // No operand predicates
     /* 224255 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224257 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 224257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_S),
     /* 224260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224269 */     GIR_RootConstrainSelectedInstOperands,
     /* 224270 */     // GIR_Coverage, 7974,
     /* 224270 */     GIR_EraseRootFromParent_Done,
     /* 224271 */   // Label 4269: @224271
     /* 224271 */   GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(224348), // Rule ID 7975 //
     /* 224276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 224284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224293 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 224296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224304 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224312 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224316 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 224320 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224324 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224328 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224332 */     // MIs[2] Operand 1
     /* 224332 */     // No operand predicates
     /* 224332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224334 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 224334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_D),
     /* 224337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224346 */     GIR_RootConstrainSelectedInstOperands,
     /* 224347 */     // GIR_Coverage, 7975,
     /* 224347 */     GIR_EraseRootFromParent_Done,
     /* 224348 */   // Label 4270: @224348
     /* 224348 */   GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(224425), // Rule ID 7976 //
     /* 224353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 224361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224370 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 224373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224377 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224381 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 224397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224405 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 224409 */     // MIs[2] Operand 1
     /* 224409 */     // No operand predicates
     /* 224409 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224411 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1487:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 224411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_D),
     /* 224414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224423 */     GIR_RootConstrainSelectedInstOperands,
     /* 224424 */     // GIR_Coverage, 7976,
     /* 224424 */     GIR_EraseRootFromParent_Done,
     /* 224425 */   // Label 4271: @224425
     /* 224425 */   GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(224502), // Rule ID 7977 //
     /* 224430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 224450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224462 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224466 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224470 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 224474 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224478 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224482 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224486 */     // MIs[2] Operand 1
     /* 224486 */     // No operand predicates
     /* 224486 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224488 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 224488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_H),
     /* 224491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224500 */     GIR_RootConstrainSelectedInstOperands,
     /* 224501 */     // GIR_Coverage, 7977,
     /* 224501 */     GIR_EraseRootFromParent_Done,
     /* 224502 */   // Label 4272: @224502
     /* 224502 */   GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(224579), // Rule ID 7978 //
     /* 224507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 224527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224535 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 224551 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224555 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224559 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 224563 */     // MIs[2] Operand 1
     /* 224563 */     // No operand predicates
     /* 224563 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224565 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 224565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_H),
     /* 224568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224577 */     GIR_RootConstrainSelectedInstOperands,
     /* 224578 */     // GIR_Coverage, 7978,
     /* 224578 */     GIR_EraseRootFromParent_Done,
     /* 224579 */   // Label 4273: @224579
     /* 224579 */   GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(224656), // Rule ID 7979 //
     /* 224584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 224598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224601 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 224604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224608 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224612 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224616 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224620 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224624 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 224628 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224632 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224636 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224640 */     // MIs[2] Operand 1
     /* 224640 */     // No operand predicates
     /* 224640 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224642 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 224642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_S),
     /* 224645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224654 */     GIR_RootConstrainSelectedInstOperands,
     /* 224655 */     // GIR_Coverage, 7979,
     /* 224655 */     GIR_EraseRootFromParent_Done,
     /* 224656 */   // Label 4274: @224656
     /* 224656 */   GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(224733), // Rule ID 7980 //
     /* 224661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 224675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224678 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 224681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224685 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224689 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224701 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 224705 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224709 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224713 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 224717 */     // MIs[2] Operand 1
     /* 224717 */     // No operand predicates
     /* 224717 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224719 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 224719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_S),
     /* 224722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224726 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224731 */     GIR_RootConstrainSelectedInstOperands,
     /* 224732 */     // GIR_Coverage, 7980,
     /* 224732 */     GIR_EraseRootFromParent_Done,
     /* 224733 */   // Label 4275: @224733
     /* 224733 */   GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(224810), // Rule ID 7981 //
     /* 224738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224755 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 224758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224766 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224778 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 224782 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224786 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224790 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 224794 */     // MIs[2] Operand 1
     /* 224794 */     // No operand predicates
     /* 224794 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224796 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 224796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_D),
     /* 224799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224808 */     GIR_RootConstrainSelectedInstOperands,
     /* 224809 */     // GIR_Coverage, 7981,
     /* 224809 */     GIR_EraseRootFromParent_Done,
     /* 224810 */   // Label 4276: @224810
     /* 224810 */   GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(224887), // Rule ID 7982 //
     /* 224815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 224823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224829 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224832 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 224835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224847 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224851 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224855 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 224859 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224863 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224867 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 224871 */     // MIs[2] Operand 1
     /* 224871 */     // No operand predicates
     /* 224871 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224873 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1551:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 224873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_D),
     /* 224876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224880 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 224885 */     GIR_RootConstrainSelectedInstOperands,
     /* 224886 */     // GIR_Coverage, 7982,
     /* 224886 */     GIR_EraseRootFromParent_Done,
     /* 224887 */   // Label 4277: @224887
     /* 224887 */   GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(224964), // Rule ID 7983 //
     /* 224892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 224900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224903 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224906 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224909 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 224912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224916 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224920 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224924 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 224928 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 224932 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 224936 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 224940 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 224944 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 224948 */     // MIs[2] Operand 1
     /* 224948 */     // No operand predicates
     /* 224948 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 224950 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 224950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_H),
     /* 224953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 224957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 224959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 224962 */     GIR_RootConstrainSelectedInstOperands,
     /* 224963 */     // GIR_Coverage, 7983,
     /* 224963 */     GIR_EraseRootFromParent_Done,
     /* 224964 */   // Label 4278: @224964
     /* 224964 */   GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(225041), // Rule ID 7984 //
     /* 224969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 224977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 224989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 224997 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 225013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225021 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225025 */     // MIs[2] Operand 1
     /* 225025 */     // No operand predicates
     /* 225025 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225027 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 225027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_H),
     /* 225030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225032 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225034 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225039 */     GIR_RootConstrainSelectedInstOperands,
     /* 225040 */     // GIR_Coverage, 7984,
     /* 225040 */     GIR_EraseRootFromParent_Done,
     /* 225041 */   // Label 4279: @225041
     /* 225041 */   GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(225118), // Rule ID 7985 //
     /* 225046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 225054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225063 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 225066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225074 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225086 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 225090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225098 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225102 */     // MIs[2] Operand 1
     /* 225102 */     // No operand predicates
     /* 225102 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225104 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 225104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_S),
     /* 225107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225116 */     GIR_RootConstrainSelectedInstOperands,
     /* 225117 */     // GIR_Coverage, 7985,
     /* 225117 */     GIR_EraseRootFromParent_Done,
     /* 225118 */   // Label 4280: @225118
     /* 225118 */   GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(225195), // Rule ID 7986 //
     /* 225123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 225131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225140 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 225143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225151 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 225167 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225171 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225175 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225179 */     // MIs[2] Operand 1
     /* 225179 */     // No operand predicates
     /* 225179 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225181 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 225181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_S),
     /* 225184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225193 */     GIR_RootConstrainSelectedInstOperands,
     /* 225194 */     // GIR_Coverage, 7986,
     /* 225194 */     GIR_EraseRootFromParent_Done,
     /* 225195 */   // Label 4281: @225195
     /* 225195 */   GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(225272), // Rule ID 7987 //
     /* 225200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 225208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225217 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 225220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225228 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225236 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225240 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 225244 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225248 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225252 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225256 */     // MIs[2] Operand 1
     /* 225256 */     // No operand predicates
     /* 225256 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225258 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 225258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_D),
     /* 225261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225265 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225270 */     GIR_RootConstrainSelectedInstOperands,
     /* 225271 */     // GIR_Coverage, 7987,
     /* 225271 */     GIR_EraseRootFromParent_Done,
     /* 225272 */   // Label 4282: @225272
     /* 225272 */   GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(225349), // Rule ID 7988 //
     /* 225277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 225285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225294 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 225297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225301 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225305 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225309 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225313 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225317 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 225321 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225325 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225329 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225333 */     // MIs[2] Operand 1
     /* 225333 */     // No operand predicates
     /* 225333 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225335 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1441:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 225335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_D),
     /* 225338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225340 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225342 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225347 */     GIR_RootConstrainSelectedInstOperands,
     /* 225348 */     // GIR_Coverage, 7988,
     /* 225348 */     GIR_EraseRootFromParent_Done,
     /* 225349 */   // Label 4283: @225349
     /* 225349 */   GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(225426), // Rule ID 7989 //
     /* 225354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225371 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 225374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225382 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225390 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225394 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 225398 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225402 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225406 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225410 */     // MIs[2] Operand 1
     /* 225410 */     // No operand predicates
     /* 225410 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225412 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 225412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_H),
     /* 225415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225424 */     GIR_RootConstrainSelectedInstOperands,
     /* 225425 */     // GIR_Coverage, 7989,
     /* 225425 */     GIR_EraseRootFromParent_Done,
     /* 225426 */   // Label 4284: @225426
     /* 225426 */   GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(225503), // Rule ID 7990 //
     /* 225431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225448 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 225451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225459 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225463 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225467 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225471 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 225475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225483 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225487 */     // MIs[2] Operand 1
     /* 225487 */     // No operand predicates
     /* 225487 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225489 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 225489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_H),
     /* 225492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225501 */     GIR_RootConstrainSelectedInstOperands,
     /* 225502 */     // GIR_Coverage, 7990,
     /* 225502 */     GIR_EraseRootFromParent_Done,
     /* 225503 */   // Label 4285: @225503
     /* 225503 */   GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(225580), // Rule ID 7991 //
     /* 225508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 225528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225532 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225536 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225540 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225544 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225548 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 225552 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225556 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225560 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225564 */     // MIs[2] Operand 1
     /* 225564 */     // No operand predicates
     /* 225564 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225566 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 225566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_S),
     /* 225569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225578 */     GIR_RootConstrainSelectedInstOperands,
     /* 225579 */     // GIR_Coverage, 7991,
     /* 225579 */     GIR_EraseRootFromParent_Done,
     /* 225580 */   // Label 4286: @225580
     /* 225580 */   GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(225657), // Rule ID 7992 //
     /* 225585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225588 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225593 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225596 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225599 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225602 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 225605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225609 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225613 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225625 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 225629 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225633 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225637 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225641 */     // MIs[2] Operand 1
     /* 225641 */     // No operand predicates
     /* 225641 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225643 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 225643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_S),
     /* 225646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225655 */     GIR_RootConstrainSelectedInstOperands,
     /* 225656 */     // GIR_Coverage, 7992,
     /* 225656 */     GIR_EraseRootFromParent_Done,
     /* 225657 */   // Label 4287: @225657
     /* 225657 */   GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(225734), // Rule ID 7993 //
     /* 225662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225679 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 225682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225690 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 225706 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225710 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225714 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225718 */     // MIs[2] Operand 1
     /* 225718 */     // No operand predicates
     /* 225718 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225720 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 225720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_D),
     /* 225723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225725 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225727 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225732 */     GIR_RootConstrainSelectedInstOperands,
     /* 225733 */     // GIR_Coverage, 7993,
     /* 225733 */     GIR_EraseRootFromParent_Done,
     /* 225734 */   // Label 4288: @225734
     /* 225734 */   GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(225811), // Rule ID 7994 //
     /* 225739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 225747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 225759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225767 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225771 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225775 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225779 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 225783 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225787 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225791 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225795 */     // MIs[2] Operand 1
     /* 225795 */     // No operand predicates
     /* 225795 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225797 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1459:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 225797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_D),
     /* 225800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225804 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225809 */     GIR_RootConstrainSelectedInstOperands,
     /* 225810 */     // GIR_Coverage, 7994,
     /* 225810 */     GIR_EraseRootFromParent_Done,
     /* 225811 */   // Label 4289: @225811
     /* 225811 */   GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(225888), // Rule ID 7995 //
     /* 225816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 225824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225833 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 225836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225848 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225852 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225856 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 225860 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225864 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225868 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 225872 */     // MIs[2] Operand 1
     /* 225872 */     // No operand predicates
     /* 225872 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225874 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 225874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_H),
     /* 225877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225879 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225881 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 225886 */     GIR_RootConstrainSelectedInstOperands,
     /* 225887 */     // GIR_Coverage, 7995,
     /* 225887 */     GIR_EraseRootFromParent_Done,
     /* 225888 */   // Label 4290: @225888
     /* 225888 */   GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(225965), // Rule ID 7996 //
     /* 225893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 225901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225910 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 225913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225917 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225921 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 225929 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 225933 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 225937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 225941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 225945 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 225949 */     // MIs[2] Operand 1
     /* 225949 */     // No operand predicates
     /* 225949 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 225951 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 225951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_H),
     /* 225954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 225956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 225958 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 225960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 225963 */     GIR_RootConstrainSelectedInstOperands,
     /* 225964 */     // GIR_Coverage, 7996,
     /* 225964 */     GIR_EraseRootFromParent_Done,
     /* 225965 */   // Label 4291: @225965
     /* 225965 */   GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(226042), // Rule ID 7997 //
     /* 225970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 225978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 225990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 225998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226002 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226006 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226010 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 226014 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226018 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226022 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 226026 */     // MIs[2] Operand 1
     /* 226026 */     // No operand predicates
     /* 226026 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226028 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 226028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_S),
     /* 226031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 226040 */     GIR_RootConstrainSelectedInstOperands,
     /* 226041 */     // GIR_Coverage, 7997,
     /* 226041 */     GIR_EraseRootFromParent_Done,
     /* 226042 */   // Label 4292: @226042
     /* 226042 */   GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(226119), // Rule ID 7998 //
     /* 226047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 226055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226058 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 226061 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226064 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 226067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226075 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 226091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226099 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 226103 */     // MIs[2] Operand 1
     /* 226103 */     // No operand predicates
     /* 226103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226105 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 226105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_S),
     /* 226108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 226117 */     GIR_RootConstrainSelectedInstOperands,
     /* 226118 */     // GIR_Coverage, 7998,
     /* 226118 */     GIR_EraseRootFromParent_Done,
     /* 226119 */   // Label 4293: @226119
     /* 226119 */   GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(226196), // Rule ID 7999 //
     /* 226124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 226132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226141 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 226144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226148 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226152 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 226168 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226172 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226176 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 226180 */     // MIs[2] Operand 1
     /* 226180 */     // No operand predicates
     /* 226180 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226182 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 226182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_D),
     /* 226185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226189 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 226194 */     GIR_RootConstrainSelectedInstOperands,
     /* 226195 */     // GIR_Coverage, 7999,
     /* 226195 */     GIR_EraseRootFromParent_Done,
     /* 226196 */   // Label 4294: @226196
     /* 226196 */   GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(226273), // Rule ID 8000 //
     /* 226201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 226209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226218 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 226221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 226245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226253 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 226257 */     // MIs[2] Operand 1
     /* 226257 */     // No operand predicates
     /* 226257 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226259 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1435:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 226259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_D),
     /* 226262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 226271 */     GIR_RootConstrainSelectedInstOperands,
     /* 226272 */     // GIR_Coverage, 8000,
     /* 226272 */     GIR_EraseRootFromParent_Done,
     /* 226273 */   // Label 4295: @226273
     /* 226273 */   GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(226350), // Rule ID 8001 //
     /* 226278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226295 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 226298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226306 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 226322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226330 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 226334 */     // MIs[2] Operand 1
     /* 226334 */     // No operand predicates
     /* 226334 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226336 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 226336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_H),
     /* 226339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226343 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 226348 */     GIR_RootConstrainSelectedInstOperands,
     /* 226349 */     // GIR_Coverage, 8001,
     /* 226349 */     GIR_EraseRootFromParent_Done,
     /* 226350 */   // Label 4296: @226350
     /* 226350 */   GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(226427), // Rule ID 8002 //
     /* 226355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226372 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 226375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226383 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 226399 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226403 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226407 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 226411 */     // MIs[2] Operand 1
     /* 226411 */     // No operand predicates
     /* 226411 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226413 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 226413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_H),
     /* 226416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 226425 */     GIR_RootConstrainSelectedInstOperands,
     /* 226426 */     // GIR_Coverage, 8002,
     /* 226426 */     GIR_EraseRootFromParent_Done,
     /* 226427 */   // Label 4297: @226427
     /* 226427 */   GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(226504), // Rule ID 8003 //
     /* 226432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 226446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226449 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 226452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226460 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 226476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226484 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 226488 */     // MIs[2] Operand 1
     /* 226488 */     // No operand predicates
     /* 226488 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226490 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 226490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_S),
     /* 226493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226497 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 226502 */     GIR_RootConstrainSelectedInstOperands,
     /* 226503 */     // GIR_Coverage, 8003,
     /* 226503 */     GIR_EraseRootFromParent_Done,
     /* 226504 */   // Label 4298: @226504
     /* 226504 */   GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(226581), // Rule ID 8004 //
     /* 226509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 226523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226526 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 226529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226537 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226549 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 226553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226561 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 226565 */     // MIs[2] Operand 1
     /* 226565 */     // No operand predicates
     /* 226565 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226567 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 226567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_S),
     /* 226570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226574 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 226579 */     GIR_RootConstrainSelectedInstOperands,
     /* 226580 */     // GIR_Coverage, 8004,
     /* 226580 */     GIR_EraseRootFromParent_Done,
     /* 226581 */   // Label 4299: @226581
     /* 226581 */   GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(226658), // Rule ID 8005 //
     /* 226586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226603 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 226606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226614 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226626 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 226630 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226634 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226638 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 226642 */     // MIs[2] Operand 1
     /* 226642 */     // No operand predicates
     /* 226642 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226644 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 226644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_D),
     /* 226647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226649 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226651 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 226656 */     GIR_RootConstrainSelectedInstOperands,
     /* 226657 */     // GIR_Coverage, 8005,
     /* 226657 */     GIR_EraseRootFromParent_Done,
     /* 226658 */   // Label 4300: @226658
     /* 226658 */   GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(226735), // Rule ID 8006 //
     /* 226663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 226671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226680 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 226683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226687 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 226691 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 226699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 226703 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 226707 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 226711 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 226715 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 226719 */     // MIs[2] Operand 1
     /* 226719 */     // No operand predicates
     /* 226719 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 226721 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1453:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 226721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_D),
     /* 226724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 226726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 226728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 226730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 226733 */     GIR_RootConstrainSelectedInstOperands,
     /* 226734 */     // GIR_Coverage, 8006,
     /* 226734 */     GIR_EraseRootFromParent_Done,
     /* 226735 */   // Label 4301: @226735
     /* 226735 */   GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(226791), // Rule ID 55 //
     /* 226740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 226743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 226748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 226751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 226754 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 226757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226765 */     // MIs[0] Operand 3
     /* 226765 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /* 226776 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 226780 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn)  =>  (PACIA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
     /* 226780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIA),
     /* 226783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 226785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 226787 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 226789 */     GIR_RootConstrainSelectedInstOperands,
     /* 226790 */     // GIR_Coverage, 55,
     /* 226790 */     GIR_EraseRootFromParent_Done,
     /* 226791 */   // Label 4302: @226791
     /* 226791 */   GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(226847), // Rule ID 56 //
     /* 226796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 226799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 226804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 226807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 226810 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 226813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226821 */     // MIs[0] Operand 3
     /* 226821 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /* 226832 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 226836 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn)  =>  (PACIB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
     /* 226836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIB),
     /* 226839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 226841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 226843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 226845 */     GIR_RootConstrainSelectedInstOperands,
     /* 226846 */     // GIR_Coverage, 56,
     /* 226846 */     GIR_EraseRootFromParent_Done,
     /* 226847 */   // Label 4303: @226847
     /* 226847 */   GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(226903), // Rule ID 57 //
     /* 226852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 226855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 226860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 226863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 226866 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 226869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226873 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226877 */     // MIs[0] Operand 3
     /* 226877 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /* 226888 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 226892 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn)  =>  (PACDA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
     /* 226892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDA),
     /* 226895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 226897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 226899 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 226901 */     GIR_RootConstrainSelectedInstOperands,
     /* 226902 */     // GIR_Coverage, 57,
     /* 226902 */     GIR_EraseRootFromParent_Done,
     /* 226903 */   // Label 4304: @226903
     /* 226903 */   GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(226959), // Rule ID 58 //
     /* 226908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 226911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 226916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 226919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 226922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 226925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 226933 */     // MIs[0] Operand 3
     /* 226933 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /* 226944 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 226948 */     // (intrinsic_wo_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn)  =>  (PACDB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
     /* 226948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDB),
     /* 226951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 226953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 226955 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 226957 */     GIR_RootConstrainSelectedInstOperands,
     /* 226958 */     // GIR_Coverage, 58,
     /* 226958 */     GIR_EraseRootFromParent_Done,
     /* 226959 */   // Label 4305: @226959
     /* 226959 */   GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(227014), // Rule ID 2799 //
     /* 226964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 226967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 226972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 226978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226989 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226993 */     // MIs[0] imm
     /* 226993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 226996 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 227001 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1552:{ *:[iPTR] }, ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_H:{ *:[nxv8f16] } ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 227001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_H),
     /* 227004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 227006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 227008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 227010 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 227012 */     GIR_RootConstrainSelectedInstOperands,
     /* 227013 */     // GIR_Coverage, 2799,
     /* 227013 */     GIR_EraseRootFromParent_Done,
     /* 227014 */   // Label 4306: @227014
     /* 227014 */   GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(227069), // Rule ID 2800 //
     /* 227019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 227027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227044 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227048 */     // MIs[0] imm
     /* 227048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227051 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 227056 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1552:{ *:[iPTR] }, ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_S:{ *:[nxv4f32] } ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 227056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_S),
     /* 227059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 227061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 227063 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 227065 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 227067 */     GIR_RootConstrainSelectedInstOperands,
     /* 227068 */     // GIR_Coverage, 2800,
     /* 227068 */     GIR_EraseRootFromParent_Done,
     /* 227069 */   // Label 4307: @227069
     /* 227069 */   GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(227124), // Rule ID 2801 //
     /* 227074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 227082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227099 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227103 */     // MIs[0] imm
     /* 227103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227106 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 227111 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1552:{ *:[iPTR] }, ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_D:{ *:[nxv2f64] } ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 227111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_D),
     /* 227114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 227116 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 227118 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 227120 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 227122 */     GIR_RootConstrainSelectedInstOperands,
     /* 227123 */     // GIR_Coverage, 2801,
     /* 227123 */     GIR_EraseRootFromParent_Done,
     /* 227124 */   // Label 4308: @227124
     /* 227124 */   GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(227179), // Rule ID 3579 //
     /* 227129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 227137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 227146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227158 */     // MIs[0] Idx
     /* 227158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227161 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_1),
     /* 227166 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1638:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zd, PPR16:{ *:[nxv8i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx)  =>  (PMOV_ZIP_H:{ *:[nxv8i16] } ZPRAny:{ *:[nxv8i16] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx, PPR16:{ *:[nxv8i1] }:$Pn)
     /* 227166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
     /* 227169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 227173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 227175 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 227177 */     GIR_RootConstrainSelectedInstOperands,
     /* 227178 */     // GIR_Coverage, 3579,
     /* 227178 */     GIR_EraseRootFromParent_Done,
     /* 227179 */   // Label 4309: @227179
     /* 227179 */   GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(227234), // Rule ID 3580 //
     /* 227184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 227192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 227201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227205 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227209 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227213 */     // MIs[0] Idx
     /* 227213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227216 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_3),
     /* 227221 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1638:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zd, PPR32:{ *:[nxv4i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx)  =>  (PMOV_ZIP_S:{ *:[nxv4i32] } ZPRAny:{ *:[nxv4i32] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx, PPR32:{ *:[nxv4i1] }:$Pn)
     /* 227221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
     /* 227224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 227228 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 227230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 227232 */     GIR_RootConstrainSelectedInstOperands,
     /* 227233 */     // GIR_Coverage, 3580,
     /* 227233 */     GIR_EraseRootFromParent_Done,
     /* 227234 */   // Label 4310: @227234
     /* 227234 */   GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(227289), // Rule ID 3581 //
     /* 227239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 227247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227253 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 227256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227264 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227268 */     // MIs[0] Idx
     /* 227268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227271 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_7),
     /* 227276 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1638:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zd, PPR64:{ *:[nxv2i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx)  =>  (PMOV_ZIP_D:{ *:[nxv2i64] } ZPRAny:{ *:[nxv2i64] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx, PPR64:{ *:[nxv2i1] }:$Pn)
     /* 227276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
     /* 227279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227281 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 227283 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 227285 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 227287 */     GIR_RootConstrainSelectedInstOperands,
     /* 227288 */     // GIR_Coverage, 3581,
     /* 227288 */     GIR_EraseRootFromParent_Done,
     /* 227289 */   // Label 4311: @227289
     /* 227289 */   GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(227344), // Rule ID 3877 //
     /* 227294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 227297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_xar),
     /* 227302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 227305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 227308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 227311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 227315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 227319 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 227323 */     // MIs[0] imm
     /* 227323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227326 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm0_63),
     /* 227331 */     // (intrinsic_wo_chain:{ *:[v2i64] } 553:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm)  =>  (XAR:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm)
     /* 227331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR),
     /* 227334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 227336 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 227338 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 227340 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 227342 */     GIR_RootConstrainSelectedInstOperands,
     /* 227343 */     // GIR_Coverage, 3877,
     /* 227343 */     GIR_EraseRootFromParent_Done,
     /* 227344 */   // Label 4312: @227344
     /* 227344 */   GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(227391), // Rule ID 2862 //
     /* 227349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 227357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227370 */     // MIs[0] idx
     /* 227370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227373 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 227378 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1488:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 227378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 227381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227385 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227387 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 227389 */     GIR_RootConstrainSelectedInstOperands,
     /* 227390 */     // GIR_Coverage, 2862,
     /* 227390 */     GIR_EraseRootFromParent_Done,
     /* 227391 */   // Label 4313: @227391
     /* 227391 */   GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(227438), // Rule ID 2866 //
     /* 227396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 227404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227417 */     // MIs[0] idx
     /* 227417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227420 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 227425 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1488:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 227425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 227428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227430 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227432 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227434 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 227436 */     GIR_RootConstrainSelectedInstOperands,
     /* 227437 */     // GIR_Coverage, 2866,
     /* 227437 */     GIR_EraseRootFromParent_Done,
     /* 227438 */   // Label 4314: @227438
     /* 227438 */   GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(227485), // Rule ID 2870 //
     /* 227443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 227451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227464 */     // MIs[0] idx
     /* 227464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227467 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 227472 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1488:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 227472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 227475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227481 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 227483 */     GIR_RootConstrainSelectedInstOperands,
     /* 227484 */     // GIR_Coverage, 2870,
     /* 227484 */     GIR_EraseRootFromParent_Done,
     /* 227485 */   // Label 4315: @227485
     /* 227485 */   GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(227532), // Rule ID 3019 //
     /* 227490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 227498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227511 */     // MIs[0] Op3
     /* 227511 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227514 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 227519 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1619:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (MUL_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 227519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_H),
     /* 227522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227528 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227530 */     GIR_RootConstrainSelectedInstOperands,
     /* 227531 */     // GIR_Coverage, 3019,
     /* 227531 */     GIR_EraseRootFromParent_Done,
     /* 227532 */   // Label 4316: @227532
     /* 227532 */   GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(227579), // Rule ID 3020 //
     /* 227537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 227545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227558 */     // MIs[0] Op3
     /* 227558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227561 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 227566 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1619:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (MUL_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 227566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_S),
     /* 227569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227575 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227577 */     GIR_RootConstrainSelectedInstOperands,
     /* 227578 */     // GIR_Coverage, 3020,
     /* 227578 */     GIR_EraseRootFromParent_Done,
     /* 227579 */   // Label 4317: @227579
     /* 227579 */   GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(227626), // Rule ID 3021 //
     /* 227584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 227592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227605 */     // MIs[0] Op3
     /* 227605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227608 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 227613 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1619:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (MUL_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 227613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_D),
     /* 227616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227622 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227624 */     GIR_RootConstrainSelectedInstOperands,
     /* 227625 */     // GIR_Coverage, 3021,
     /* 227625 */     GIR_EraseRootFromParent_Done,
     /* 227626 */   // Label 4318: @227626
     /* 227626 */   GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(227673), // Rule ID 3022 //
     /* 227631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
     /* 227639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227652 */     // MIs[0] Op3
     /* 227652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227655 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 227660 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1765:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 227660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_S),
     /* 227663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227669 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227671 */     GIR_RootConstrainSelectedInstOperands,
     /* 227672 */     // GIR_Coverage, 3022,
     /* 227672 */     GIR_EraseRootFromParent_Done,
     /* 227673 */   // Label 4319: @227673
     /* 227673 */   GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(227720), // Rule ID 3023 //
     /* 227678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
     /* 227686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227699 */     // MIs[0] Op3
     /* 227699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227702 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 227707 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1765:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 227707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_D),
     /* 227710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227716 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227718 */     GIR_RootConstrainSelectedInstOperands,
     /* 227719 */     // GIR_Coverage, 3023,
     /* 227719 */     GIR_EraseRootFromParent_Done,
     /* 227720 */   // Label 4320: @227720
     /* 227720 */   GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(227767), // Rule ID 3071 //
     /* 227725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 227733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 227736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 227739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 227742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227746 */     // MIs[0] Op3
     /* 227746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227749 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 227754 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1876:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 227754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_B),
     /* 227757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 227759 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227761 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227763 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227765 */     GIR_RootConstrainSelectedInstOperands,
     /* 227766 */     // GIR_Coverage, 3071,
     /* 227766 */     GIR_EraseRootFromParent_Done,
     /* 227767 */   // Label 4321: @227767
     /* 227767 */   GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(227814), // Rule ID 3073 //
     /* 227772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 227780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227793 */     // MIs[0] Op3
     /* 227793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227796 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 227801 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1876:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 227801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_H),
     /* 227804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 227806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227810 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227812 */     GIR_RootConstrainSelectedInstOperands,
     /* 227813 */     // GIR_Coverage, 3073,
     /* 227813 */     GIR_EraseRootFromParent_Done,
     /* 227814 */   // Label 4322: @227814
     /* 227814 */   GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(227861), // Rule ID 3075 //
     /* 227819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 227827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227840 */     // MIs[0] Op3
     /* 227840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227843 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 227848 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1876:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 227848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_S),
     /* 227851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 227853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227855 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227857 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227859 */     GIR_RootConstrainSelectedInstOperands,
     /* 227860 */     // GIR_Coverage, 3075,
     /* 227860 */     GIR_EraseRootFromParent_Done,
     /* 227861 */   // Label 4323: @227861
     /* 227861 */   GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(227908), // Rule ID 3077 //
     /* 227866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227869 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 227874 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227877 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227880 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227887 */     // MIs[0] Op3
     /* 227887 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227890 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 227895 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1876:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (SSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 227895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_D),
     /* 227898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 227900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227904 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227906 */     GIR_RootConstrainSelectedInstOperands,
     /* 227907 */     // GIR_Coverage, 3077,
     /* 227907 */     GIR_EraseRootFromParent_Done,
     /* 227908 */   // Label 4324: @227908
     /* 227908 */   GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(227955), // Rule ID 3099 //
     /* 227913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 227921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 227924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 227927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227934 */     // MIs[0] Op3
     /* 227934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227937 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 227942 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1856:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SQSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 227942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_B),
     /* 227945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227947 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227949 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227951 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 227953 */     GIR_RootConstrainSelectedInstOperands,
     /* 227954 */     // GIR_Coverage, 3099,
     /* 227954 */     GIR_EraseRootFromParent_Done,
     /* 227955 */   // Label 4325: @227955
     /* 227955 */   GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(228002), // Rule ID 3100 //
     /* 227960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 227963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 227968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227981 */     // MIs[0] Op3
     /* 227981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 227984 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 227989 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1856:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SQSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 227989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_H),
     /* 227992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227994 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227996 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227998 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228000 */     GIR_RootConstrainSelectedInstOperands,
     /* 228001 */     // GIR_Coverage, 3100,
     /* 228001 */     GIR_EraseRootFromParent_Done,
     /* 228002 */   // Label 4326: @228002
     /* 228002 */   GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(228049), // Rule ID 3101 //
     /* 228007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 228015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228028 */     // MIs[0] Op3
     /* 228028 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228031 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 228036 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1856:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SQSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 228036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_S),
     /* 228039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228041 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228043 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228045 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228047 */     GIR_RootConstrainSelectedInstOperands,
     /* 228048 */     // GIR_Coverage, 3101,
     /* 228048 */     GIR_EraseRootFromParent_Done,
     /* 228049 */   // Label 4327: @228049
     /* 228049 */   GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(228096), // Rule ID 3174 //
     /* 228054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 228062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228075 */     // MIs[0] Op3
     /* 228075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228078 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 228083 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2157:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (XAR_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 228083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_B),
     /* 228086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228092 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228094 */     GIR_RootConstrainSelectedInstOperands,
     /* 228095 */     // GIR_Coverage, 3174,
     /* 228095 */     GIR_EraseRootFromParent_Done,
     /* 228096 */   // Label 4328: @228096
     /* 228096 */   GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(228143), // Rule ID 3175 //
     /* 228101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 228109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228122 */     // MIs[0] Op3
     /* 228122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228125 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 228130 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2157:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (XAR_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 228130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_H),
     /* 228133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228135 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228137 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228139 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228141 */     GIR_RootConstrainSelectedInstOperands,
     /* 228142 */     // GIR_Coverage, 3175,
     /* 228142 */     GIR_EraseRootFromParent_Done,
     /* 228143 */   // Label 4329: @228143
     /* 228143 */   GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(228190), // Rule ID 3176 //
     /* 228148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 228156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228169 */     // MIs[0] Op3
     /* 228169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228172 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 228177 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2157:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (XAR_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 228177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_S),
     /* 228180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228186 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228188 */     GIR_RootConstrainSelectedInstOperands,
     /* 228189 */     // GIR_Coverage, 3176,
     /* 228189 */     GIR_EraseRootFromParent_Done,
     /* 228190 */   // Label 4330: @228190
     /* 228190 */   GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(228237), // Rule ID 3177 //
     /* 228195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 228203 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228206 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228216 */     // MIs[0] Op3
     /* 228216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228219 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 228224 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2157:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (XAR_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 228224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_D),
     /* 228227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228231 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228233 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228235 */     GIR_RootConstrainSelectedInstOperands,
     /* 228236 */     // GIR_Coverage, 3177,
     /* 228236 */     GIR_EraseRootFromParent_Done,
     /* 228237 */   // Label 4331: @228237
     /* 228237 */   GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(228284), // Rule ID 3564 //
     /* 228242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 228245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
     /* 228250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228263 */     // MIs[0] Op3
     /* 228263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228266 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
     /* 228271 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1367:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)  =>  (EXTQ_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
     /* 228271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
     /* 228274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228276 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228278 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228280 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228282 */     GIR_RootConstrainSelectedInstOperands,
     /* 228283 */     // GIR_Coverage, 3564,
     /* 228283 */     GIR_EraseRootFromParent_Done,
     /* 228284 */   // Label 4332: @228284
     /* 228284 */   GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(228331), // Rule ID 3612 //
     /* 228289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 228297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228310 */     // MIs[0] Op3
     /* 228310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228313 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 228318 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1606:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI2_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 228318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_B),
     /* 228321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228327 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228329 */     GIR_RootConstrainSelectedInstOperands,
     /* 228330 */     // GIR_Coverage, 3612,
     /* 228330 */     GIR_EraseRootFromParent_Done,
     /* 228331 */   // Label 4333: @228331
     /* 228331 */   GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(228378), // Rule ID 3613 //
     /* 228336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 228344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228357 */     // MIs[0] Op3
     /* 228357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228360 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 228365 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1606:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)  =>  (LUTI2_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)
     /* 228365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_H),
     /* 228368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228370 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228372 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228374 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228376 */     GIR_RootConstrainSelectedInstOperands,
     /* 228377 */     // GIR_Coverage, 3613,
     /* 228377 */     GIR_EraseRootFromParent_Done,
     /* 228378 */   // Label 4334: @228378
     /* 228378 */   GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(228425), // Rule ID 3614 //
     /* 228383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 228391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228404 */     // MIs[0] Op3
     /* 228404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228407 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 228412 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1606:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)  =>  (LUTI2_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)
     /* 228412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_H),
     /* 228415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228421 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228423 */     GIR_RootConstrainSelectedInstOperands,
     /* 228424 */     // GIR_Coverage, 3614,
     /* 228424 */     GIR_EraseRootFromParent_Done,
     /* 228425 */   // Label 4335: @228425
     /* 228425 */   GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(228472), // Rule ID 3615 //
     /* 228430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 228438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228451 */     // MIs[0] Op3
     /* 228451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228454 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 228459 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1607:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Op3)  =>  (LUTI4_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Op3)
     /* 228459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_B),
     /* 228462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228468 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228470 */     GIR_RootConstrainSelectedInstOperands,
     /* 228471 */     // GIR_Coverage, 3615,
     /* 228471 */     GIR_EraseRootFromParent_Done,
     /* 228472 */   // Label 4336: @228472
     /* 228472 */   GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(228519), // Rule ID 3616 //
     /* 228477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 228485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228498 */     // MIs[0] Op3
     /* 228498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228501 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 228506 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1607:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI4_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 228506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_H),
     /* 228509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228513 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228515 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228517 */     GIR_RootConstrainSelectedInstOperands,
     /* 228518 */     // GIR_Coverage, 3616,
     /* 228518 */     GIR_EraseRootFromParent_Done,
     /* 228519 */   // Label 4337: @228519
     /* 228519 */   GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(228566), // Rule ID 3617 //
     /* 228524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 228527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 228532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228545 */     // MIs[0] Op3
     /* 228545 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228548 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 228553 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1607:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI4_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 228553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_H),
     /* 228556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228562 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228564 */     GIR_RootConstrainSelectedInstOperands,
     /* 228565 */     // GIR_Coverage, 3617,
     /* 228565 */     GIR_EraseRootFromParent_Done,
     /* 228566 */   // Label 4338: @228566
     /* 228566 */   GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(228613), // Rule ID 11450 //
     /* 228571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 228579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228592 */     // MIs[0] Op3
     /* 228592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228595 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 228600 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1806:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 228600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_H),
     /* 228603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228607 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228609 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228611 */     GIR_RootConstrainSelectedInstOperands,
     /* 228612 */     // GIR_Coverage, 11450,
     /* 228612 */     GIR_EraseRootFromParent_Done,
     /* 228613 */   // Label 4339: @228613
     /* 228613 */   GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(228660), // Rule ID 11451 //
     /* 228618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 228626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228639 */     // MIs[0] Op3
     /* 228639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228642 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 228647 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1806:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 228647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_S),
     /* 228650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228656 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228658 */     GIR_RootConstrainSelectedInstOperands,
     /* 228659 */     // GIR_Coverage, 11451,
     /* 228659 */     GIR_EraseRootFromParent_Done,
     /* 228660 */   // Label 4340: @228660
     /* 228660 */   GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(228707), // Rule ID 11452 //
     /* 228665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 228673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228676 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228679 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228686 */     // MIs[0] Op3
     /* 228686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228689 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 228694 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1806:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 228694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_D),
     /* 228697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228701 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228703 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228705 */     GIR_RootConstrainSelectedInstOperands,
     /* 228706 */     // GIR_Coverage, 11452,
     /* 228706 */     GIR_EraseRootFromParent_Done,
     /* 228707 */   // Label 4341: @228707
     /* 228707 */   GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(228754), // Rule ID 11453 //
     /* 228712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 228720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228733 */     // MIs[0] Op3
     /* 228733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228736 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 228741 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1837:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 228741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_H),
     /* 228744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228750 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228752 */     GIR_RootConstrainSelectedInstOperands,
     /* 228753 */     // GIR_Coverage, 11453,
     /* 228753 */     GIR_EraseRootFromParent_Done,
     /* 228754 */   // Label 4342: @228754
     /* 228754 */   GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(228801), // Rule ID 11454 //
     /* 228759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 228767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228780 */     // MIs[0] Op3
     /* 228780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228783 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 228788 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1837:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 228788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_S),
     /* 228791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228797 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228799 */     GIR_RootConstrainSelectedInstOperands,
     /* 228800 */     // GIR_Coverage, 11454,
     /* 228800 */     GIR_EraseRootFromParent_Done,
     /* 228801 */   // Label 4343: @228801
     /* 228801 */   GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(228848), // Rule ID 11455 //
     /* 228806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 228814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228827 */     // MIs[0] Op3
     /* 228827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228830 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 228835 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1837:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 228835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_D),
     /* 228838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228842 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228844 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228846 */     GIR_RootConstrainSelectedInstOperands,
     /* 228847 */     // GIR_Coverage, 11455,
     /* 228847 */     GIR_EraseRootFromParent_Done,
     /* 228848 */   // Label 4344: @228848
     /* 228848 */   GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(228895), // Rule ID 11478 //
     /* 228853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
     /* 228861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228874 */     // MIs[0] Op3
     /* 228874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228877 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 228882 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1767:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 228882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_S),
     /* 228885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228889 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228891 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228893 */     GIR_RootConstrainSelectedInstOperands,
     /* 228894 */     // GIR_Coverage, 11478,
     /* 228894 */     GIR_EraseRootFromParent_Done,
     /* 228895 */   // Label 4345: @228895
     /* 228895 */   GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(228942), // Rule ID 11479 //
     /* 228900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
     /* 228908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228921 */     // MIs[0] Op3
     /* 228921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228924 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 228929 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1767:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 228929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_D),
     /* 228932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228938 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228940 */     GIR_RootConstrainSelectedInstOperands,
     /* 228941 */     // GIR_Coverage, 11479,
     /* 228941 */     GIR_EraseRootFromParent_Done,
     /* 228942 */   // Label 4346: @228942
     /* 228942 */   GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(228989), // Rule ID 11480 //
     /* 228947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
     /* 228955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228968 */     // MIs[0] Op3
     /* 228968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 228971 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 228976 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2003:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (UMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 228976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_S),
     /* 228979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228983 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228985 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 228987 */     GIR_RootConstrainSelectedInstOperands,
     /* 228988 */     // GIR_Coverage, 11480,
     /* 228988 */     GIR_EraseRootFromParent_Done,
     /* 228989 */   // Label 4347: @228989
     /* 228989 */   GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(229036), // Rule ID 11481 //
     /* 228994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 228997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
     /* 229002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229015 */     // MIs[0] Op3
     /* 229015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229018 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 229023 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2003:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (UMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 229023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_D),
     /* 229026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229032 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229034 */     GIR_RootConstrainSelectedInstOperands,
     /* 229035 */     // GIR_Coverage, 11481,
     /* 229035 */     GIR_EraseRootFromParent_Done,
     /* 229036 */   // Label 4348: @229036
     /* 229036 */   GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(229083), // Rule ID 11482 //
     /* 229041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
     /* 229049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229062 */     // MIs[0] Op3
     /* 229062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229065 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 229070 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2005:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (UMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 229070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_S),
     /* 229073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229077 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229079 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229081 */     GIR_RootConstrainSelectedInstOperands,
     /* 229082 */     // GIR_Coverage, 11482,
     /* 229082 */     GIR_EraseRootFromParent_Done,
     /* 229083 */   // Label 4349: @229083
     /* 229083 */   GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(229130), // Rule ID 11483 //
     /* 229088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
     /* 229096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229109 */     // MIs[0] Op3
     /* 229109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229112 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 229117 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2005:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (UMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 229117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_D),
     /* 229120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229126 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229128 */     GIR_RootConstrainSelectedInstOperands,
     /* 229129 */     // GIR_Coverage, 11483,
     /* 229129 */     GIR_EraseRootFromParent_Done,
     /* 229130 */   // Label 4350: @229130
     /* 229130 */   GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(229177), // Rule ID 11484 //
     /* 229135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
     /* 229143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229156 */     // MIs[0] Op3
     /* 229156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229159 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 229164 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1812:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 229164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_S),
     /* 229167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229175 */     GIR_RootConstrainSelectedInstOperands,
     /* 229176 */     // GIR_Coverage, 11484,
     /* 229176 */     GIR_EraseRootFromParent_Done,
     /* 229177 */   // Label 4351: @229177
     /* 229177 */   GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(229224), // Rule ID 11485 //
     /* 229182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
     /* 229190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229203 */     // MIs[0] Op3
     /* 229203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229206 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 229211 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1812:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 229211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_D),
     /* 229214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229220 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229222 */     GIR_RootConstrainSelectedInstOperands,
     /* 229223 */     // GIR_Coverage, 11485,
     /* 229223 */     GIR_EraseRootFromParent_Done,
     /* 229224 */   // Label 4352: @229224
     /* 229224 */   GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(229271), // Rule ID 11486 //
     /* 229229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
     /* 229237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229250 */     // MIs[0] Op3
     /* 229250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229253 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 229258 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1814:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 229258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_S),
     /* 229261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229265 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229267 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229269 */     GIR_RootConstrainSelectedInstOperands,
     /* 229270 */     // GIR_Coverage, 11486,
     /* 229270 */     GIR_EraseRootFromParent_Done,
     /* 229271 */   // Label 4353: @229271
     /* 229271 */   GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(229318), // Rule ID 11487 //
     /* 229276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
     /* 229284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229297 */     // MIs[0] Op3
     /* 229297 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229300 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 229305 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1814:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 229305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_D),
     /* 229308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229312 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229314 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229316 */     GIR_RootConstrainSelectedInstOperands,
     /* 229317 */     // GIR_Coverage, 11487,
     /* 229317 */     GIR_EraseRootFromParent_Done,
     /* 229318 */   // Label 4354: @229318
     /* 229318 */   GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(229365), // Rule ID 11731 //
     /* 229323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 229331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 229337 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229344 */     // MIs[0] Op3
     /* 229344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229347 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 229352 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1872:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SRSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 229352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_B),
     /* 229355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229359 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229361 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229363 */     GIR_RootConstrainSelectedInstOperands,
     /* 229364 */     // GIR_Coverage, 11731,
     /* 229364 */     GIR_EraseRootFromParent_Done,
     /* 229365 */   // Label 4355: @229365
     /* 229365 */   GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(229412), // Rule ID 11732 //
     /* 229370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229373 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 229378 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229381 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 229384 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229391 */     // MIs[0] Op3
     /* 229391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229394 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 229399 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1872:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SRSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 229399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_H),
     /* 229402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229408 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229410 */     GIR_RootConstrainSelectedInstOperands,
     /* 229411 */     // GIR_Coverage, 11732,
     /* 229411 */     GIR_EraseRootFromParent_Done,
     /* 229412 */   // Label 4356: @229412
     /* 229412 */   GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(229459), // Rule ID 11733 //
     /* 229417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 229425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 229431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229438 */     // MIs[0] Op3
     /* 229438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229441 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 229446 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1872:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SRSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 229446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_S),
     /* 229449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229453 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229455 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229457 */     GIR_RootConstrainSelectedInstOperands,
     /* 229458 */     // GIR_Coverage, 11733,
     /* 229458 */     GIR_EraseRootFromParent_Done,
     /* 229459 */   // Label 4357: @229459
     /* 229459 */   GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(229506), // Rule ID 11734 //
     /* 229464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 229472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 229478 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229485 */     // MIs[0] Op3
     /* 229485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229488 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 229493 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1872:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (SRSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 229493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_D),
     /* 229496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229500 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229502 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229504 */     GIR_RootConstrainSelectedInstOperands,
     /* 229505 */     // GIR_Coverage, 11734,
     /* 229505 */     GIR_EraseRootFromParent_Done,
     /* 229506 */   // Label 4358: @229506
     /* 229506 */   GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(229553), // Rule ID 11735 //
     /* 229511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 229519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 229525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229532 */     // MIs[0] Op3
     /* 229532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229535 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 229540 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2063:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (URSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 229540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_B),
     /* 229543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229549 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229551 */     GIR_RootConstrainSelectedInstOperands,
     /* 229552 */     // GIR_Coverage, 11735,
     /* 229552 */     GIR_EraseRootFromParent_Done,
     /* 229553 */   // Label 4359: @229553
     /* 229553 */   GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(229600), // Rule ID 11737 //
     /* 229558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 229566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 229572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229579 */     // MIs[0] Op3
     /* 229579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229582 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 229587 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2063:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (URSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 229587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_H),
     /* 229590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229594 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229596 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229598 */     GIR_RootConstrainSelectedInstOperands,
     /* 229599 */     // GIR_Coverage, 11737,
     /* 229599 */     GIR_EraseRootFromParent_Done,
     /* 229600 */   // Label 4360: @229600
     /* 229600 */   GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(229647), // Rule ID 11739 //
     /* 229605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 229613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 229619 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229626 */     // MIs[0] Op3
     /* 229626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229629 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 229634 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2063:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (URSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 229634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_S),
     /* 229637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229639 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229641 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229643 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229645 */     GIR_RootConstrainSelectedInstOperands,
     /* 229646 */     // GIR_Coverage, 11739,
     /* 229646 */     GIR_EraseRootFromParent_Done,
     /* 229647 */   // Label 4361: @229647
     /* 229647 */   GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(229694), // Rule ID 11741 //
     /* 229652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 229660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 229666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229673 */     // MIs[0] Op3
     /* 229673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229676 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 229681 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2063:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (URSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 229681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_D),
     /* 229684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229690 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229692 */     GIR_RootConstrainSelectedInstOperands,
     /* 229693 */     // GIR_Coverage, 11741,
     /* 229693 */     GIR_EraseRootFromParent_Done,
     /* 229694 */   // Label 4362: @229694
     /* 229694 */   GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(229741), // Rule ID 11743 //
     /* 229699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 229707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 229713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229720 */     // MIs[0] Op3
     /* 229720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229723 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
     /* 229728 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1852:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op3)  =>  (SQSHLU_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op3)
     /* 229728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_B),
     /* 229731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229733 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229735 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229737 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229739 */     GIR_RootConstrainSelectedInstOperands,
     /* 229740 */     // GIR_Coverage, 11743,
     /* 229740 */     GIR_EraseRootFromParent_Done,
     /* 229741 */   // Label 4363: @229741
     /* 229741 */   GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(229788), // Rule ID 11744 //
     /* 229746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 229754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 229760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229767 */     // MIs[0] Op3
     /* 229767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229770 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
     /* 229775 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1852:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op3)  =>  (SQSHLU_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op3)
     /* 229775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_H),
     /* 229778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229782 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229784 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229786 */     GIR_RootConstrainSelectedInstOperands,
     /* 229787 */     // GIR_Coverage, 11744,
     /* 229787 */     GIR_EraseRootFromParent_Done,
     /* 229788 */   // Label 4364: @229788
     /* 229788 */   GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(229835), // Rule ID 11745 //
     /* 229793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 229801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 229807 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229814 */     // MIs[0] Op3
     /* 229814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229817 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
     /* 229822 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1852:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op3)  =>  (SQSHLU_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op3)
     /* 229822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_S),
     /* 229825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229831 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229833 */     GIR_RootConstrainSelectedInstOperands,
     /* 229834 */     // GIR_Coverage, 11745,
     /* 229834 */     GIR_EraseRootFromParent_Done,
     /* 229835 */   // Label 4365: @229835
     /* 229835 */   GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(229882), // Rule ID 11746 //
     /* 229840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 229848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 229854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229861 */     // MIs[0] Op3
     /* 229861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229864 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL64),
     /* 229869 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1852:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL64>>:$Op3)  =>  (SQSHLU_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL64>>:$Op3)
     /* 229869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_D),
     /* 229872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 229874 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229876 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229878 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229880 */     GIR_RootConstrainSelectedInstOperands,
     /* 229881 */     // GIR_Coverage, 11746,
     /* 229881 */     GIR_EraseRootFromParent_Done,
     /* 229882 */   // Label 4366: @229882
     /* 229882 */   GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(229929), // Rule ID 11833 //
     /* 229887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229890 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 229895 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229898 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 229901 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229908 */     // MIs[0] Op3
     /* 229908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229911 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 229916 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2072:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (USRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 229916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_B),
     /* 229919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 229921 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229923 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229925 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229927 */     GIR_RootConstrainSelectedInstOperands,
     /* 229928 */     // GIR_Coverage, 11833,
     /* 229928 */     GIR_EraseRootFromParent_Done,
     /* 229929 */   // Label 4367: @229929
     /* 229929 */   GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(229976), // Rule ID 11835 //
     /* 229934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 229942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229945 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229948 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229955 */     // MIs[0] Op3
     /* 229955 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 229958 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 229963 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2072:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (USRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 229963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_H),
     /* 229966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 229968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229972 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 229974 */     GIR_RootConstrainSelectedInstOperands,
     /* 229975 */     // GIR_Coverage, 11835,
     /* 229975 */     GIR_EraseRootFromParent_Done,
     /* 229976 */   // Label 4368: @229976
     /* 229976 */   GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(230023), // Rule ID 11837 //
     /* 229981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 229989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230002 */     // MIs[0] Op3
     /* 230002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230005 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230010 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2072:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (USRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_S),
     /* 230013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230019 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230021 */     GIR_RootConstrainSelectedInstOperands,
     /* 230022 */     // GIR_Coverage, 11837,
     /* 230022 */     GIR_EraseRootFromParent_Done,
     /* 230023 */   // Label 4369: @230023
     /* 230023 */   GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(230070), // Rule ID 11839 //
     /* 230028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 230036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 230042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230049 */     // MIs[0] Op3
     /* 230049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230052 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 230057 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2072:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (USRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 230057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_D),
     /* 230060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230064 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230066 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230068 */     GIR_RootConstrainSelectedInstOperands,
     /* 230069 */     // GIR_Coverage, 11839,
     /* 230069 */     GIR_EraseRootFromParent_Done,
     /* 230070 */   // Label 4370: @230070
     /* 230070 */   GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(230117), // Rule ID 11841 //
     /* 230075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 230083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230096 */     // MIs[0] Op3
     /* 230096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230099 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230104 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1873:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SRSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_B),
     /* 230107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230113 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230115 */     GIR_RootConstrainSelectedInstOperands,
     /* 230116 */     // GIR_Coverage, 11841,
     /* 230116 */     GIR_EraseRootFromParent_Done,
     /* 230117 */   // Label 4371: @230117
     /* 230117 */   GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(230164), // Rule ID 11842 //
     /* 230122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 230130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230143 */     // MIs[0] Op3
     /* 230143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230146 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230151 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1873:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SRSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_H),
     /* 230154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230160 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230162 */     GIR_RootConstrainSelectedInstOperands,
     /* 230163 */     // GIR_Coverage, 11842,
     /* 230163 */     GIR_EraseRootFromParent_Done,
     /* 230164 */   // Label 4372: @230164
     /* 230164 */   GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(230211), // Rule ID 11843 //
     /* 230169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 230177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230190 */     // MIs[0] Op3
     /* 230190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230193 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230198 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1873:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SRSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_S),
     /* 230201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230207 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230209 */     GIR_RootConstrainSelectedInstOperands,
     /* 230210 */     // GIR_Coverage, 11843,
     /* 230210 */     GIR_EraseRootFromParent_Done,
     /* 230211 */   // Label 4373: @230211
     /* 230211 */   GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(230258), // Rule ID 11844 //
     /* 230216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 230224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 230230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230237 */     // MIs[0] Op3
     /* 230237 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230240 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 230245 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1873:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (SRSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 230245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_D),
     /* 230248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230254 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230256 */     GIR_RootConstrainSelectedInstOperands,
     /* 230257 */     // GIR_Coverage, 11844,
     /* 230257 */     GIR_EraseRootFromParent_Done,
     /* 230258 */   // Label 4374: @230258
     /* 230258 */   GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(230305), // Rule ID 11849 //
     /* 230263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 230271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230284 */     // MIs[0] Op3
     /* 230284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230287 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230292 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2065:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (URSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_B),
     /* 230295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230301 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230303 */     GIR_RootConstrainSelectedInstOperands,
     /* 230304 */     // GIR_Coverage, 11849,
     /* 230304 */     GIR_EraseRootFromParent_Done,
     /* 230305 */   // Label 4375: @230305
     /* 230305 */   GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(230352), // Rule ID 11850 //
     /* 230310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 230318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230331 */     // MIs[0] Op3
     /* 230331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230334 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230339 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2065:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (URSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_H),
     /* 230342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230346 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230348 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230350 */     GIR_RootConstrainSelectedInstOperands,
     /* 230351 */     // GIR_Coverage, 11850,
     /* 230351 */     GIR_EraseRootFromParent_Done,
     /* 230352 */   // Label 4376: @230352
     /* 230352 */   GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(230399), // Rule ID 11851 //
     /* 230357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 230365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230378 */     // MIs[0] Op3
     /* 230378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230381 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230386 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2065:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (URSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_S),
     /* 230389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230391 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230393 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230395 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230397 */     GIR_RootConstrainSelectedInstOperands,
     /* 230398 */     // GIR_Coverage, 11851,
     /* 230398 */     GIR_EraseRootFromParent_Done,
     /* 230399 */   // Label 4377: @230399
     /* 230399 */   GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(230446), // Rule ID 11852 //
     /* 230404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 230412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230415 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 230418 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230425 */     // MIs[0] Op3
     /* 230425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230428 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
     /* 230433 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2065:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)  =>  (URSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
     /* 230433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_D),
     /* 230436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 230438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230442 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230444 */     GIR_RootConstrainSelectedInstOperands,
     /* 230445 */     // GIR_Coverage, 11852,
     /* 230445 */     GIR_EraseRootFromParent_Done,
     /* 230446 */   // Label 4378: @230446
     /* 230446 */   GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(230493), // Rule ID 11912 //
     /* 230451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 230459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230472 */     // MIs[0] Op3
     /* 230472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230475 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230480 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1850:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SQRSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_B),
     /* 230483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230487 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230489 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230491 */     GIR_RootConstrainSelectedInstOperands,
     /* 230492 */     // GIR_Coverage, 11912,
     /* 230492 */     GIR_EraseRootFromParent_Done,
     /* 230493 */   // Label 4379: @230493
     /* 230493 */   GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(230540), // Rule ID 11913 //
     /* 230498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 230506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230519 */     // MIs[0] Op3
     /* 230519 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230522 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230527 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1850:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SQRSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_H),
     /* 230530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230536 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230538 */     GIR_RootConstrainSelectedInstOperands,
     /* 230539 */     // GIR_Coverage, 11913,
     /* 230539 */     GIR_EraseRootFromParent_Done,
     /* 230540 */   // Label 4380: @230540
     /* 230540 */   GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(230587), // Rule ID 11914 //
     /* 230545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 230553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230566 */     // MIs[0] Op3
     /* 230566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230569 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230574 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1850:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SQRSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_S),
     /* 230577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230579 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230581 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230583 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230585 */     GIR_RootConstrainSelectedInstOperands,
     /* 230586 */     // GIR_Coverage, 11914,
     /* 230586 */     GIR_EraseRootFromParent_Done,
     /* 230587 */   // Label 4381: @230587
     /* 230587 */   GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(230634), // Rule ID 11915 //
     /* 230592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230595 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 230600 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230603 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230606 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230613 */     // MIs[0] Op3
     /* 230613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230616 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230621 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1729:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_B),
     /* 230624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230630 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230632 */     GIR_RootConstrainSelectedInstOperands,
     /* 230633 */     // GIR_Coverage, 11915,
     /* 230633 */     GIR_EraseRootFromParent_Done,
     /* 230634 */   // Label 4382: @230634
     /* 230634 */   GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(230681), // Rule ID 11916 //
     /* 230639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 230647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230660 */     // MIs[0] Op3
     /* 230660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230663 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230668 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1729:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_H),
     /* 230671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230677 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230679 */     GIR_RootConstrainSelectedInstOperands,
     /* 230680 */     // GIR_Coverage, 11916,
     /* 230680 */     GIR_EraseRootFromParent_Done,
     /* 230681 */   // Label 4383: @230681
     /* 230681 */   GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(230728), // Rule ID 11917 //
     /* 230686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 230694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230707 */     // MIs[0] Op3
     /* 230707 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230710 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230715 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1729:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_S),
     /* 230718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230720 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230722 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230724 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230726 */     GIR_RootConstrainSelectedInstOperands,
     /* 230727 */     // GIR_Coverage, 11917,
     /* 230727 */     GIR_EraseRootFromParent_Done,
     /* 230728 */   // Label 4384: @230728
     /* 230728 */   GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(230775), // Rule ID 11918 //
     /* 230733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 230741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230754 */     // MIs[0] Op3
     /* 230754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230757 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230762 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1687:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (RSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_B),
     /* 230765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230769 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230771 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230773 */     GIR_RootConstrainSelectedInstOperands,
     /* 230774 */     // GIR_Coverage, 11918,
     /* 230774 */     GIR_EraseRootFromParent_Done,
     /* 230775 */   // Label 4385: @230775
     /* 230775 */   GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(230822), // Rule ID 11919 //
     /* 230780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 230788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230801 */     // MIs[0] Op3
     /* 230801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230804 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230809 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1687:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (RSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_H),
     /* 230812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230814 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230816 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230818 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230820 */     GIR_RootConstrainSelectedInstOperands,
     /* 230821 */     // GIR_Coverage, 11919,
     /* 230821 */     GIR_EraseRootFromParent_Done,
     /* 230822 */   // Label 4386: @230822
     /* 230822 */   GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(230869), // Rule ID 11920 //
     /* 230827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 230835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230838 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230841 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230848 */     // MIs[0] Op3
     /* 230848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230851 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230856 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1687:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (RSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_S),
     /* 230859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230863 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230865 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230867 */     GIR_RootConstrainSelectedInstOperands,
     /* 230868 */     // GIR_Coverage, 11920,
     /* 230868 */     GIR_EraseRootFromParent_Done,
     /* 230869 */   // Label 4387: @230869
     /* 230869 */   GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(230916), // Rule ID 11921 //
     /* 230874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 230882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 230885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230895 */     // MIs[0] Op3
     /* 230895 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230898 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 230903 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1854:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 230903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_B),
     /* 230906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230908 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230910 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230912 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230914 */     GIR_RootConstrainSelectedInstOperands,
     /* 230915 */     // GIR_Coverage, 11921,
     /* 230915 */     GIR_EraseRootFromParent_Done,
     /* 230916 */   // Label 4388: @230916
     /* 230916 */   GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(230963), // Rule ID 11922 //
     /* 230921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 230929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230942 */     // MIs[0] Op3
     /* 230942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230945 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 230950 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1854:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 230950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_H),
     /* 230953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230959 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 230961 */     GIR_RootConstrainSelectedInstOperands,
     /* 230962 */     // GIR_Coverage, 11922,
     /* 230962 */     GIR_EraseRootFromParent_Done,
     /* 230963 */   // Label 4389: @230963
     /* 230963 */   GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(231010), // Rule ID 11923 //
     /* 230968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 230976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230989 */     // MIs[0] Op3
     /* 230989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 230992 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 230997 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1854:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 230997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_S),
     /* 231000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231004 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231006 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231008 */     GIR_RootConstrainSelectedInstOperands,
     /* 231009 */     // GIR_Coverage, 11923,
     /* 231009 */     GIR_EraseRootFromParent_Done,
     /* 231010 */   // Label 4390: @231010
     /* 231010 */   GIM_Try, /*On fail goto*//*Label 4391*/ GIMT_Encode4(231057), // Rule ID 11924 //
     /* 231015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 231023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 231026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231036 */     // MIs[0] Op3
     /* 231036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231039 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 231044 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1844:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (SQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 231044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_B),
     /* 231047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231049 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231051 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231053 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231055 */     GIR_RootConstrainSelectedInstOperands,
     /* 231056 */     // GIR_Coverage, 11924,
     /* 231056 */     GIR_EraseRootFromParent_Done,
     /* 231057 */   // Label 4391: @231057
     /* 231057 */   GIM_Try, /*On fail goto*//*Label 4392*/ GIMT_Encode4(231104), // Rule ID 11925 //
     /* 231062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 231070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231083 */     // MIs[0] Op3
     /* 231083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231086 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 231091 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1844:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (SQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 231091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_H),
     /* 231094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231100 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231102 */     GIR_RootConstrainSelectedInstOperands,
     /* 231103 */     // GIR_Coverage, 11925,
     /* 231103 */     GIR_EraseRootFromParent_Done,
     /* 231104 */   // Label 4392: @231104
     /* 231104 */   GIM_Try, /*On fail goto*//*Label 4393*/ GIMT_Encode4(231151), // Rule ID 11926 //
     /* 231109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 231117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 231126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231130 */     // MIs[0] Op3
     /* 231130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231133 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 231138 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1844:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (SQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 231138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_S),
     /* 231141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231147 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231149 */     GIR_RootConstrainSelectedInstOperands,
     /* 231150 */     // GIR_Coverage, 11926,
     /* 231150 */     GIR_EraseRootFromParent_Done,
     /* 231151 */   // Label 4393: @231151
     /* 231151 */   GIM_Try, /*On fail goto*//*Label 4394*/ GIMT_Encode4(231198), // Rule ID 11927 //
     /* 231156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 231164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 231167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231177 */     // MIs[0] Op3
     /* 231177 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231180 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 231185 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2049:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (UQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 231185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_B),
     /* 231188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231194 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231196 */     GIR_RootConstrainSelectedInstOperands,
     /* 231197 */     // GIR_Coverage, 11927,
     /* 231197 */     GIR_EraseRootFromParent_Done,
     /* 231198 */   // Label 4394: @231198
     /* 231198 */   GIM_Try, /*On fail goto*//*Label 4395*/ GIMT_Encode4(231245), // Rule ID 11928 //
     /* 231203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 231211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231224 */     // MIs[0] Op3
     /* 231224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231227 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 231232 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2049:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (UQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 231232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_H),
     /* 231235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231241 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231243 */     GIR_RootConstrainSelectedInstOperands,
     /* 231244 */     // GIR_Coverage, 11928,
     /* 231244 */     GIR_EraseRootFromParent_Done,
     /* 231245 */   // Label 4395: @231245
     /* 231245 */   GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(231292), // Rule ID 11929 //
     /* 231250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 231258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231264 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 231267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231271 */     // MIs[0] Op3
     /* 231271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231274 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 231279 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2049:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (UQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 231279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_S),
     /* 231282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231286 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231288 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231290 */     GIR_RootConstrainSelectedInstOperands,
     /* 231291 */     // GIR_Coverage, 11929,
     /* 231291 */     GIR_EraseRootFromParent_Done,
     /* 231292 */   // Label 4396: @231292
     /* 231292 */   GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(231339), // Rule ID 11930 //
     /* 231297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 231305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 231308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231311 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231318 */     // MIs[0] Op3
     /* 231318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231321 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
     /* 231326 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2046:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)  =>  (UQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
     /* 231326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_B),
     /* 231329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231335 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231337 */     GIR_RootConstrainSelectedInstOperands,
     /* 231338 */     // GIR_Coverage, 11930,
     /* 231338 */     GIR_EraseRootFromParent_Done,
     /* 231339 */   // Label 4397: @231339
     /* 231339 */   GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(231386), // Rule ID 11931 //
     /* 231344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 231352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231365 */     // MIs[0] Op3
     /* 231365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231368 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
     /* 231373 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2046:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)  =>  (UQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
     /* 231373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_H),
     /* 231376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231378 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231382 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231384 */     GIR_RootConstrainSelectedInstOperands,
     /* 231385 */     // GIR_Coverage, 11931,
     /* 231385 */     GIR_EraseRootFromParent_Done,
     /* 231386 */   // Label 4398: @231386
     /* 231386 */   GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(231433), // Rule ID 11932 //
     /* 231391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231394 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 231399 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231402 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231405 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 231408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231412 */     // MIs[0] Op3
     /* 231412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 231415 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
     /* 231420 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2046:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)  =>  (UQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
     /* 231420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_S),
     /* 231423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231425 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231427 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231429 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 231431 */     GIR_RootConstrainSelectedInstOperands,
     /* 231432 */     // GIR_Coverage, 11932,
     /* 231432 */     GIR_EraseRootFromParent_Done,
     /* 231433 */   // Label 4399: @231433
     /* 231433 */   GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(231500), // Rule ID 2604 //
     /* 231438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
     /* 231446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 231455 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 231458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231462 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231466 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231472 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2056:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (URECPE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231472 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231475 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231479 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S_UNDEF),
     /* 231489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231491 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231494 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231496 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231498 */     GIR_RootConstrainSelectedInstOperands,
     /* 231499 */     // GIR_Coverage, 2604,
     /* 231499 */     GIR_EraseRootFromParent_Done,
     /* 231500 */   // Label 4400: @231500
     /* 231500 */   GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(231567), // Rule ID 7804 //
     /* 231505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 231513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 231516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231519 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 231522 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 231525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231537 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231539 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1320:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CLS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231539 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231542 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231546 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B_UNDEF),
     /* 231556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231558 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231561 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231563 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231565 */     GIR_RootConstrainSelectedInstOperands,
     /* 231566 */     // GIR_Coverage, 7804,
     /* 231566 */     GIR_EraseRootFromParent_Done,
     /* 231567 */   // Label 4401: @231567
     /* 231567 */   GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(231634), // Rule ID 7806 //
     /* 231572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 231580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 231589 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 231592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231600 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231604 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231606 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1320:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CLS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231609 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231613 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231618 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H_UNDEF),
     /* 231623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231625 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231630 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231632 */     GIR_RootConstrainSelectedInstOperands,
     /* 231633 */     // GIR_Coverage, 7806,
     /* 231633 */     GIR_EraseRootFromParent_Done,
     /* 231634 */   // Label 4402: @231634
     /* 231634 */   GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(231701), // Rule ID 7808 //
     /* 231639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 231647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 231656 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 231659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231671 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231673 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1320:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CLS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231673 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231676 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231680 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231685 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S_UNDEF),
     /* 231690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231692 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231695 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231697 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231699 */     GIR_RootConstrainSelectedInstOperands,
     /* 231700 */     // GIR_Coverage, 7808,
     /* 231700 */     GIR_EraseRootFromParent_Done,
     /* 231701 */   // Label 4403: @231701
     /* 231701 */   GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(231768), // Rule ID 7810 //
     /* 231706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 231714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 231723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 231726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231740 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1320:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CLS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 231740 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231743 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231747 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231752 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D_UNDEF),
     /* 231757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231759 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231762 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231764 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231766 */     GIR_RootConstrainSelectedInstOperands,
     /* 231767 */     // GIR_Coverage, 7810,
     /* 231767 */     GIR_EraseRootFromParent_Done,
     /* 231768 */   // Label 4404: @231768
     /* 231768 */   GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(231835), // Rule ID 7840 //
     /* 231773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 231781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 231784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 231790 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 231793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231797 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231801 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231805 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231807 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1340:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CNOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231807 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231810 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231814 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231819 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B_UNDEF),
     /* 231824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231826 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231831 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231833 */     GIR_RootConstrainSelectedInstOperands,
     /* 231834 */     // GIR_Coverage, 7840,
     /* 231834 */     GIR_EraseRootFromParent_Done,
     /* 231835 */   // Label 4405: @231835
     /* 231835 */   GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(231902), // Rule ID 7842 //
     /* 231840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 231848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 231857 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 231860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231872 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231874 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1340:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CNOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231874 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231877 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231881 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231886 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H_UNDEF),
     /* 231891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231893 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231898 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231900 */     GIR_RootConstrainSelectedInstOperands,
     /* 231901 */     // GIR_Coverage, 7842,
     /* 231901 */     GIR_EraseRootFromParent_Done,
     /* 231902 */   // Label 4406: @231902
     /* 231902 */   GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(231969), // Rule ID 7844 //
     /* 231907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 231915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 231924 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 231927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231931 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 231935 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 231939 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 231941 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1340:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CNOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231941 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 231944 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 231948 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 231953 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 231955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S_UNDEF),
     /* 231958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231960 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 231963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 231965 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 231967 */     GIR_RootConstrainSelectedInstOperands,
     /* 231968 */     // GIR_Coverage, 7844,
     /* 231968 */     GIR_EraseRootFromParent_Done,
     /* 231969 */   // Label 4407: @231969
     /* 231969 */   GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(232036), // Rule ID 7846 //
     /* 231974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 231977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 231982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 231991 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 231994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232006 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232008 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1340:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CNOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232008 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232011 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232015 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232020 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D_UNDEF),
     /* 232025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232027 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232032 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232034 */     GIR_RootConstrainSelectedInstOperands,
     /* 232035 */     // GIR_Coverage, 7846,
     /* 232035 */     GIR_EraseRootFromParent_Done,
     /* 232036 */   // Label 4408: @232036
     /* 232036 */   GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(232103), // Rule ID 7852 //
     /* 232041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 232044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 232049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 232058 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 232061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232073 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232075 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1626:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (NOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232075 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232078 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232082 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232087 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B_UNDEF),
     /* 232092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232094 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232099 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232101 */     GIR_RootConstrainSelectedInstOperands,
     /* 232102 */     // GIR_Coverage, 7852,
     /* 232102 */     GIR_EraseRootFromParent_Done,
     /* 232103 */   // Label 4409: @232103
     /* 232103 */   GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(232170), // Rule ID 7854 //
     /* 232108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 232111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 232116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 232125 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 232128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232140 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232142 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1626:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (NOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232142 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232145 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232149 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232154 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H_UNDEF),
     /* 232159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232161 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232166 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232168 */     GIR_RootConstrainSelectedInstOperands,
     /* 232169 */     // GIR_Coverage, 7854,
     /* 232169 */     GIR_EraseRootFromParent_Done,
     /* 232170 */   // Label 4410: @232170
     /* 232170 */   GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(232237), // Rule ID 7856 //
     /* 232175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 232178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 232183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 232192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 232195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232209 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1626:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (NOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232209 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232212 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232216 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232221 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S_UNDEF),
     /* 232226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232228 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232231 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232233 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232235 */     GIR_RootConstrainSelectedInstOperands,
     /* 232236 */     // GIR_Coverage, 7856,
     /* 232236 */     GIR_EraseRootFromParent_Done,
     /* 232237 */   // Label 4411: @232237
     /* 232237 */   GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(232304), // Rule ID 7858 //
     /* 232242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 232245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 232250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 232259 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 232262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232274 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232276 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1626:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (NOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232276 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232279 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232283 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232288 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D_UNDEF),
     /* 232293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232295 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232300 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232302 */     GIR_RootConstrainSelectedInstOperands,
     /* 232303 */     // GIR_Coverage, 7858,
     /* 232303 */     GIR_EraseRootFromParent_Done,
     /* 232304 */   // Label 4412: @232304
     /* 232304 */   GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(232371), // Rule ID 11613 //
     /* 232309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
     /* 232317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 232326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 232329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232333 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232337 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232341 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232343 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2064:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (URSQRTE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232343 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232346 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232350 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232355 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S_UNDEF),
     /* 232360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232362 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232367 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232369 */     GIR_RootConstrainSelectedInstOperands,
     /* 232370 */     // GIR_Coverage, 11613,
     /* 232370 */     GIR_EraseRootFromParent_Done,
     /* 232371 */   // Label 4413: @232371
     /* 232371 */   GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(232438), // Rule ID 11615 //
     /* 232376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 232384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232390 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 232393 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 232396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232408 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232410 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1769:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQABS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232410 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232413 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232417 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232422 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B_UNDEF),
     /* 232427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232429 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232432 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232434 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232436 */     GIR_RootConstrainSelectedInstOperands,
     /* 232437 */     // GIR_Coverage, 11615,
     /* 232437 */     GIR_EraseRootFromParent_Done,
     /* 232438 */   // Label 4414: @232438
     /* 232438 */   GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(232505), // Rule ID 11617 //
     /* 232443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 232451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 232460 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 232463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232475 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232477 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1769:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQABS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232477 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232480 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232484 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232489 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H_UNDEF),
     /* 232494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232496 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232501 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232503 */     GIR_RootConstrainSelectedInstOperands,
     /* 232504 */     // GIR_Coverage, 11617,
     /* 232504 */     GIR_EraseRootFromParent_Done,
     /* 232505 */   // Label 4415: @232505
     /* 232505 */   GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(232572), // Rule ID 11619 //
     /* 232510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 232518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 232527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 232530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232542 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232544 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1769:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQABS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232544 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232547 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232551 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232556 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S_UNDEF),
     /* 232561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232563 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232568 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232570 */     GIR_RootConstrainSelectedInstOperands,
     /* 232571 */     // GIR_Coverage, 11619,
     /* 232571 */     GIR_EraseRootFromParent_Done,
     /* 232572 */   // Label 4416: @232572
     /* 232572 */   GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(232639), // Rule ID 11621 //
     /* 232577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 232585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 232594 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 232597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232601 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232609 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232611 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1769:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQABS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232623 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D_UNDEF),
     /* 232628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232630 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232633 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232635 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232637 */     GIR_RootConstrainSelectedInstOperands,
     /* 232638 */     // GIR_Coverage, 11621,
     /* 232638 */     GIR_EraseRootFromParent_Done,
     /* 232639 */   // Label 4417: @232639
     /* 232639 */   GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(232706), // Rule ID 11627 //
     /* 232644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232647 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 232652 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 232661 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 232664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232676 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232678 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1829:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQNEG_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232678 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232681 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232685 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232690 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B_UNDEF),
     /* 232695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232697 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232702 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232704 */     GIR_RootConstrainSelectedInstOperands,
     /* 232705 */     // GIR_Coverage, 11627,
     /* 232705 */     GIR_EraseRootFromParent_Done,
     /* 232706 */   // Label 4418: @232706
     /* 232706 */   GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(232773), // Rule ID 11629 //
     /* 232711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232714 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 232719 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 232728 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 232731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232735 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232739 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232743 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232745 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1829:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQNEG_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232745 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232748 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232752 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232757 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H_UNDEF),
     /* 232762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232764 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232767 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232769 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232771 */     GIR_RootConstrainSelectedInstOperands,
     /* 232772 */     // GIR_Coverage, 11629,
     /* 232772 */     GIR_EraseRootFromParent_Done,
     /* 232773 */   // Label 4419: @232773
     /* 232773 */   GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(232840), // Rule ID 11631 //
     /* 232778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 232786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 232795 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 232798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232802 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232806 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232810 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232812 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1829:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQNEG_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232812 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232815 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232819 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232824 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S_UNDEF),
     /* 232829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232834 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232836 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232838 */     GIR_RootConstrainSelectedInstOperands,
     /* 232839 */     // GIR_Coverage, 11631,
     /* 232839 */     GIR_EraseRootFromParent_Done,
     /* 232840 */   // Label 4420: @232840
     /* 232840 */   GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(232907), // Rule ID 11633 //
     /* 232845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232848 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 232853 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232856 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232859 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 232862 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 232865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 232873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 232877 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 232879 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1829:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQNEG_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232879 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 232882 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 232886 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 232891 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 232893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D_UNDEF),
     /* 232896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232898 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 232901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 232903 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 232905 */     GIR_RootConstrainSelectedInstOperands,
     /* 232906 */     // GIR_Coverage, 11633,
     /* 232906 */     GIR_EraseRootFromParent_Done,
     /* 232907 */   // Label 4421: @232907
     /* 232907 */   GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(232961), // Rule ID 30 //
     /* 232912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 232915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smmla),
     /* 232920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 232923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 232926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 232929 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 232932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232940 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232944 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232948 */     // (intrinsic_wo_chain:{ *:[v4i32] } 686:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 232948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA),
     /* 232951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 232953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 232955 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 232957 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 232959 */     GIR_RootConstrainSelectedInstOperands,
     /* 232960 */     // GIR_Coverage, 30,
     /* 232960 */     GIR_EraseRootFromParent_Done,
     /* 232961 */   // Label 4422: @232961
     /* 232961 */   GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(233015), // Rule ID 31 //
     /* 232966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 232969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ummla),
     /* 232974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 232977 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 232980 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 232983 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 232986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232994 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 232998 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233002 */     // (intrinsic_wo_chain:{ *:[v4i32] } 747:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 233002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA),
     /* 233005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233011 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233013 */     GIR_RootConstrainSelectedInstOperands,
     /* 233014 */     // GIR_Coverage, 31,
     /* 233014 */     GIR_EraseRootFromParent_Done,
     /* 233015 */   // Label 4423: @233015
     /* 233015 */   GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(233069), // Rule ID 32 //
     /* 233020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 233023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usmmla),
     /* 233028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 233037 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 233040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233048 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233052 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233056 */     // (intrinsic_wo_chain:{ *:[v4i32] } 763:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (USMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 233056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA),
     /* 233059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233063 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233065 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233067 */     GIR_RootConstrainSelectedInstOperands,
     /* 233068 */     // GIR_Coverage, 32,
     /* 233068 */     GIR_EraseRootFromParent_Done,
     /* 233069 */   // Label 4424: @233069
     /* 233069 */   GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(233123), // Rule ID 39 //
     /* 233074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 233082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233102 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233106 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233110 */     // (intrinsic_wo_chain:{ *:[v2f32] } 616:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 233110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv4f16),
     /* 233113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233117 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233119 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233121 */     GIR_RootConstrainSelectedInstOperands,
     /* 233122 */     // GIR_Coverage, 39,
     /* 233122 */     GIR_EraseRootFromParent_Done,
     /* 233123 */   // Label 4425: @233123
     /* 233123 */   GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(233177), // Rule ID 40 //
     /* 233128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 233136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233145 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233156 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233160 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233164 */     // (intrinsic_wo_chain:{ *:[v4f32] } 616:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 233164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv8f16),
     /* 233167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233175 */     GIR_RootConstrainSelectedInstOperands,
     /* 233176 */     // GIR_Coverage, 40,
     /* 233176 */     GIR_EraseRootFromParent_Done,
     /* 233177 */   // Label 4426: @233177
     /* 233177 */   GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(233231), // Rule ID 41 //
     /* 233182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 233190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233199 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233206 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233210 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233214 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233218 */     // (intrinsic_wo_chain:{ *:[v2f32] } 618:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 233218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv4f16),
     /* 233221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233223 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233225 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233227 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233229 */     GIR_RootConstrainSelectedInstOperands,
     /* 233230 */     // GIR_Coverage, 41,
     /* 233230 */     GIR_EraseRootFromParent_Done,
     /* 233231 */   // Label 4427: @233231
     /* 233231 */   GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(233285), // Rule ID 42 //
     /* 233236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 233244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233253 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233264 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233268 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233272 */     // (intrinsic_wo_chain:{ *:[v4f32] } 618:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 233272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv8f16),
     /* 233275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233279 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233281 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233283 */     GIR_RootConstrainSelectedInstOperands,
     /* 233284 */     // GIR_Coverage, 42,
     /* 233284 */     GIR_EraseRootFromParent_Done,
     /* 233285 */   // Label 4428: @233285
     /* 233285 */   GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(233339), // Rule ID 43 //
     /* 233290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 233298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233318 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233322 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233326 */     // (intrinsic_wo_chain:{ *:[v2f32] } 617:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 233326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v4f16),
     /* 233329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233335 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233337 */     GIR_RootConstrainSelectedInstOperands,
     /* 233338 */     // GIR_Coverage, 43,
     /* 233338 */     GIR_EraseRootFromParent_Done,
     /* 233339 */   // Label 4429: @233339
     /* 233339 */   GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(233393), // Rule ID 44 //
     /* 233344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 233352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233361 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233368 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233372 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233376 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233380 */     // (intrinsic_wo_chain:{ *:[v4f32] } 617:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 233380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v8f16),
     /* 233383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233387 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233389 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233391 */     GIR_RootConstrainSelectedInstOperands,
     /* 233392 */     // GIR_Coverage, 44,
     /* 233392 */     GIR_EraseRootFromParent_Done,
     /* 233393 */   // Label 4430: @233393
     /* 233393 */   GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(233447), // Rule ID 45 //
     /* 233398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 233406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233415 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233422 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233426 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233430 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233434 */     // (intrinsic_wo_chain:{ *:[v2f32] } 619:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 233434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v4f16),
     /* 233437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233441 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233443 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233445 */     GIR_RootConstrainSelectedInstOperands,
     /* 233446 */     // GIR_Coverage, 45,
     /* 233446 */     GIR_EraseRootFromParent_Done,
     /* 233447 */   // Label 4431: @233447
     /* 233447 */   GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(233501), // Rule ID 46 //
     /* 233452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 233455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 233460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233469 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233476 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233480 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233484 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233488 */     // (intrinsic_wo_chain:{ *:[v4f32] } 619:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 233488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v8f16),
     /* 233491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233497 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233499 */     GIR_RootConstrainSelectedInstOperands,
     /* 233500 */     // GIR_Coverage, 46,
     /* 233500 */     GIR_EraseRootFromParent_Done,
     /* 233501 */   // Label 4432: @233501
     /* 233501 */   GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(233555), // Rule ID 1591 //
     /* 233506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 233514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 233517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 233520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233523 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233534 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233538 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233542 */     // (intrinsic_wo_chain:{ *:[v4i16] } 696:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 233542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16),
     /* 233545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233551 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233553 */     GIR_RootConstrainSelectedInstOperands,
     /* 233554 */     // GIR_Coverage, 1591,
     /* 233554 */     GIR_EraseRootFromParent_Done,
     /* 233555 */   // Label 4433: @233555
     /* 233555 */   GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(233609), // Rule ID 1592 //
     /* 233560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 233568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 233571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 233574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233588 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233592 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233596 */     // (intrinsic_wo_chain:{ *:[v8i16] } 696:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 233596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16),
     /* 233599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233601 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233603 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233605 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233607 */     GIR_RootConstrainSelectedInstOperands,
     /* 233608 */     // GIR_Coverage, 1592,
     /* 233608 */     GIR_EraseRootFromParent_Done,
     /* 233609 */   // Label 4434: @233609
     /* 233609 */   GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(233663), // Rule ID 1593 //
     /* 233614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 233622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 233631 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 233634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233638 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233642 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233646 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233650 */     // (intrinsic_wo_chain:{ *:[v2i32] } 696:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 233650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32),
     /* 233653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233657 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233659 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233661 */     GIR_RootConstrainSelectedInstOperands,
     /* 233662 */     // GIR_Coverage, 1593,
     /* 233662 */     GIR_EraseRootFromParent_Done,
     /* 233663 */   // Label 4435: @233663
     /* 233663 */   GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(233717), // Rule ID 1594 //
     /* 233668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 233676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 233685 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 233688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233696 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233700 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233704 */     // (intrinsic_wo_chain:{ *:[v4i32] } 696:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 233704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32),
     /* 233707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233713 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233715 */     GIR_RootConstrainSelectedInstOperands,
     /* 233716 */     // GIR_Coverage, 1594,
     /* 233716 */     GIR_EraseRootFromParent_Done,
     /* 233717 */   // Label 4436: @233717
     /* 233717 */   GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(233771), // Rule ID 1595 //
     /* 233722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 233730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 233733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 233736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 233739 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 233742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233746 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233750 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233754 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233758 */     // (intrinsic_wo_chain:{ *:[v4i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 233758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16),
     /* 233761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233767 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233769 */     GIR_RootConstrainSelectedInstOperands,
     /* 233770 */     // GIR_Coverage, 1595,
     /* 233770 */     GIR_EraseRootFromParent_Done,
     /* 233771 */   // Label 4437: @233771
     /* 233771 */   GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(233825), // Rule ID 1596 //
     /* 233776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 233784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 233787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 233790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 233793 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 233796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233804 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233808 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233812 */     // (intrinsic_wo_chain:{ *:[v8i16] } 697:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 233812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16),
     /* 233815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233817 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233819 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233821 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233823 */     GIR_RootConstrainSelectedInstOperands,
     /* 233824 */     // GIR_Coverage, 1596,
     /* 233824 */     GIR_EraseRootFromParent_Done,
     /* 233825 */   // Label 4438: @233825
     /* 233825 */   GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(233879), // Rule ID 1597 //
     /* 233830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 233838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 233841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 233844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 233847 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 233850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233854 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233858 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233862 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 233866 */     // (intrinsic_wo_chain:{ *:[v2i32] } 697:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 233866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32),
     /* 233869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233871 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233873 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233875 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233877 */     GIR_RootConstrainSelectedInstOperands,
     /* 233878 */     // GIR_Coverage, 1597,
     /* 233878 */     GIR_EraseRootFromParent_Done,
     /* 233879 */   // Label 4439: @233879
     /* 233879 */   GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(233933), // Rule ID 1598 //
     /* 233884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 233887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 233892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 233901 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 233904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233908 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233912 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233916 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233920 */     // (intrinsic_wo_chain:{ *:[v4i32] } 697:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 233920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32),
     /* 233923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233929 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233931 */     GIR_RootConstrainSelectedInstOperands,
     /* 233932 */     // GIR_Coverage, 1598,
     /* 233932 */     GIR_EraseRootFromParent_Done,
     /* 233933 */   // Label 4440: @233933
     /* 233933 */   GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(233987), // Rule ID 2311 //
     /* 233938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 233941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1c),
     /* 233946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 233949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 233952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233955 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 233958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233962 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233966 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 233970 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 233974 */     // (intrinsic_wo_chain:{ *:[v4i32] } 530:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 233974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Crrr),
     /* 233977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 233979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 233981 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 233983 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 233985 */     GIR_RootConstrainSelectedInstOperands,
     /* 233986 */     // GIR_Coverage, 2311,
     /* 233986 */     GIR_EraseRootFromParent_Done,
     /* 233987 */   // Label 4441: @233987
     /* 233987 */   GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(234041), // Rule ID 2312 //
     /* 233992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 233995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1p),
     /* 234000 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234003 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234006 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 234009 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234016 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234020 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 234024 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234028 */     // (intrinsic_wo_chain:{ *:[v4i32] } 533:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Prrr),
     /* 234031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234037 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234039 */     GIR_RootConstrainSelectedInstOperands,
     /* 234040 */     // GIR_Coverage, 2312,
     /* 234040 */     GIR_EraseRootFromParent_Done,
     /* 234041 */   // Label 4442: @234041
     /* 234041 */   GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(234095), // Rule ID 2313 //
     /* 234046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 234049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1m),
     /* 234054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 234063 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234074 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 234078 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234082 */     // (intrinsic_wo_chain:{ *:[v4i32] } 532:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Mrrr),
     /* 234085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234091 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234093 */     GIR_RootConstrainSelectedInstOperands,
     /* 234094 */     // GIR_Coverage, 2313,
     /* 234094 */     GIR_EraseRootFromParent_Done,
     /* 234095 */   // Label 4443: @234095
     /* 234095 */   GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(234149), // Rule ID 2314 //
     /* 234100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 234103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su0),
     /* 234108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 234117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234128 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234132 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234136 */     // (intrinsic_wo_chain:{ *:[v4i32] } 534:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU0rrr),
     /* 234139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234145 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234147 */     GIR_RootConstrainSelectedInstOperands,
     /* 234148 */     // GIR_Coverage, 2314,
     /* 234148 */     GIR_EraseRootFromParent_Done,
     /* 234149 */   // Label 4444: @234149
     /* 234149 */   GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(234203), // Rule ID 2315 //
     /* 234154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 234157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h),
     /* 234162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 234171 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234178 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234182 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234186 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234190 */     // (intrinsic_wo_chain:{ *:[v4i32] } 536:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256Hrrr),
     /* 234193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234195 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234197 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234199 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234201 */     GIR_RootConstrainSelectedInstOperands,
     /* 234202 */     // GIR_Coverage, 2315,
     /* 234202 */     GIR_EraseRootFromParent_Done,
     /* 234203 */   // Label 4445: @234203
     /* 234203 */   GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(234257), // Rule ID 2316 //
     /* 234208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 234211 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h2),
     /* 234216 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234219 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234222 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 234225 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234232 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234236 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234240 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234244 */     // (intrinsic_wo_chain:{ *:[v4i32] } 537:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256H2rrr),
     /* 234247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234253 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234255 */     GIR_RootConstrainSelectedInstOperands,
     /* 234256 */     // GIR_Coverage, 2316,
     /* 234256 */     GIR_EraseRootFromParent_Done,
     /* 234257 */   // Label 4446: @234257
     /* 234257 */   GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(234311), // Rule ID 2317 //
     /* 234262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 234265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su1),
     /* 234270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 234279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234286 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234290 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234294 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234298 */     // (intrinsic_wo_chain:{ *:[v4i32] } 539:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 234298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU1rrr),
     /* 234301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 234303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 234305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 234307 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 234309 */     GIR_RootConstrainSelectedInstOperands,
     /* 234310 */     // GIR_Coverage, 2317,
     /* 234310 */     GIR_EraseRootFromParent_Done,
     /* 234311 */   // Label 4447: @234311
     /* 234311 */   GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(234368), // Rule ID 3667 //
     /* 234316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 234319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 234324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 234330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 234333 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 234336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 234340 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234344 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234348 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 234352 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1661:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR8:{ *:[nxv16i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_B:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 234352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_B),
     /* 234355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 234359 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 234361 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 234363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 234366 */     GIR_RootConstrainSelectedInstOperands,
     /* 234367 */     // GIR_Coverage, 3667,
     /* 234367 */     GIR_EraseRootFromParent_Done,
     /* 234368 */   // Label 4448: @234368
     /* 234368 */   GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(234425), // Rule ID 3668 //
     /* 234373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 234376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 234381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 234387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 234390 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 234393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 234397 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234401 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234405 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 234409 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1661:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR16:{ *:[nxv8i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_H:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 234409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_H),
     /* 234412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 234416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 234418 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 234420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 234423 */     GIR_RootConstrainSelectedInstOperands,
     /* 234424 */     // GIR_Coverage, 3668,
     /* 234424 */     GIR_EraseRootFromParent_Done,
     /* 234425 */   // Label 4449: @234425
     /* 234425 */   GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(234482), // Rule ID 3669 //
     /* 234430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 234433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 234438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 234444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 234447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 234450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 234454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234462 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 234466 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1661:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR32:{ *:[nxv4i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_S:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 234466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_S),
     /* 234469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 234473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 234475 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 234477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 234480 */     GIR_RootConstrainSelectedInstOperands,
     /* 234481 */     // GIR_Coverage, 3669,
     /* 234481 */     GIR_EraseRootFromParent_Done,
     /* 234482 */   // Label 4450: @234482
     /* 234482 */   GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(234539), // Rule ID 3670 //
     /* 234487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 234490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 234495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 234501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 234504 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 234507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 234511 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234515 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234519 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 234523 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1661:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR64:{ *:[nxv2i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_D:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 234523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_D),
     /* 234526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 234530 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 234532 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 234534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 234537 */     GIR_RootConstrainSelectedInstOperands,
     /* 234538 */     // GIR_Coverage, 3670,
     /* 234538 */     GIR_EraseRootFromParent_Done,
     /* 234539 */   // Label 4451: @234539
     /* 234539 */   GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(234593), // Rule ID 3849 //
     /* 234544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h),
     /* 234552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 234555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 234558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 234561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 234564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234572 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234576 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234580 */     // (intrinsic_wo_chain:{ *:[v2i64] } 540:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512H:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 234580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H),
     /* 234583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 234585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234587 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234589 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234591 */     GIR_RootConstrainSelectedInstOperands,
     /* 234592 */     // GIR_Coverage, 3849,
     /* 234592 */     GIR_EraseRootFromParent_Done,
     /* 234593 */   // Label 4452: @234593
     /* 234593 */   GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(234647), // Rule ID 3850 //
     /* 234598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h2),
     /* 234606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 234609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 234612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 234615 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 234618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234622 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234626 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234630 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234634 */     // (intrinsic_wo_chain:{ *:[v2i64] } 541:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512H2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 234634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H2),
     /* 234637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 234639 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234641 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234643 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234645 */     GIR_RootConstrainSelectedInstOperands,
     /* 234646 */     // GIR_Coverage, 3850,
     /* 234646 */     GIR_EraseRootFromParent_Done,
     /* 234647 */   // Label 4453: @234647
     /* 234647 */   GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(234701), // Rule ID 3851 //
     /* 234652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su1),
     /* 234660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 234663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 234666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 234669 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 234672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234676 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234680 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234684 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234688 */     // (intrinsic_wo_chain:{ *:[v2i64] } 543:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512SU1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 234688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU1),
     /* 234691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 234693 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234695 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234697 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234699 */     GIR_RootConstrainSelectedInstOperands,
     /* 234700 */     // GIR_Coverage, 3851,
     /* 234700 */     GIR_EraseRootFromParent_Done,
     /* 234701 */   // Label 4454: @234701
     /* 234701 */   GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(234755), // Rule ID 3852 //
     /* 234706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 234714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 234717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 234720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 234723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 234726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234734 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234738 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234742 */     // (intrinsic_wo_chain:{ *:[v16i8] } 528:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 234742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 234745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234751 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234753 */     GIR_RootConstrainSelectedInstOperands,
     /* 234754 */     // GIR_Coverage, 3852,
     /* 234754 */     GIR_EraseRootFromParent_Done,
     /* 234755 */   // Label 4455: @234755
     /* 234755 */   GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(234809), // Rule ID 3853 //
     /* 234760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 234768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 234771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 234774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 234777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 234780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234788 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234792 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234796 */     // (intrinsic_wo_chain:{ *:[v8i16] } 528:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 234796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 234799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234805 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234807 */     GIR_RootConstrainSelectedInstOperands,
     /* 234808 */     // GIR_Coverage, 3853,
     /* 234808 */     GIR_EraseRootFromParent_Done,
     /* 234809 */   // Label 4456: @234809
     /* 234809 */   GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(234863), // Rule ID 3854 //
     /* 234814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 234822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 234825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 234828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 234831 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 234834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234838 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234842 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234846 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234850 */     // (intrinsic_wo_chain:{ *:[v4i32] } 528:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 234850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 234853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234857 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234859 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234861 */     GIR_RootConstrainSelectedInstOperands,
     /* 234862 */     // GIR_Coverage, 3854,
     /* 234862 */     GIR_EraseRootFromParent_Done,
     /* 234863 */   // Label 4457: @234863
     /* 234863 */   GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(234917), // Rule ID 3855 //
     /* 234868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 234876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 234879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 234882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 234885 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 234888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234892 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234896 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234900 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234904 */     // (intrinsic_wo_chain:{ *:[v2i64] } 528:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 234904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 234907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234913 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234915 */     GIR_RootConstrainSelectedInstOperands,
     /* 234916 */     // GIR_Coverage, 3855,
     /* 234916 */     GIR_EraseRootFromParent_Done,
     /* 234917 */   // Label 4458: @234917
     /* 234917 */   GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(234971), // Rule ID 3864 //
     /* 234922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 234930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 234933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 234936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 234939 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 234942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234946 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234950 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234954 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234958 */     // (intrinsic_wo_chain:{ *:[v16i8] } 526:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 234958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 234961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 234965 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 234967 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 234969 */     GIR_RootConstrainSelectedInstOperands,
     /* 234970 */     // GIR_Coverage, 3864,
     /* 234970 */     GIR_EraseRootFromParent_Done,
     /* 234971 */   // Label 4459: @234971
     /* 234971 */   GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(235025), // Rule ID 3865 //
     /* 234976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 234979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 234984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 234987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 234990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 234993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 234996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235004 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235008 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235012 */     // (intrinsic_wo_chain:{ *:[v8i16] } 526:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 235012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235021 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235023 */     GIR_RootConstrainSelectedInstOperands,
     /* 235024 */     // GIR_Coverage, 3865,
     /* 235024 */     GIR_EraseRootFromParent_Done,
     /* 235025 */   // Label 4460: @235025
     /* 235025 */   GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(235079), // Rule ID 3866 //
     /* 235030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 235038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235047 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235054 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235058 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235062 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235066 */     // (intrinsic_wo_chain:{ *:[v4i32] } 526:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 235066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235073 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235075 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235077 */     GIR_RootConstrainSelectedInstOperands,
     /* 235078 */     // GIR_Coverage, 3866,
     /* 235078 */     GIR_EraseRootFromParent_Done,
     /* 235079 */   // Label 4461: @235079
     /* 235079 */   GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(235133), // Rule ID 3867 //
     /* 235084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235087 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 235092 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235095 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 235098 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 235101 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 235104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235112 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235116 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235120 */     // (intrinsic_wo_chain:{ *:[v2i64] } 526:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 235120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235127 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235129 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235131 */     GIR_RootConstrainSelectedInstOperands,
     /* 235132 */     // GIR_Coverage, 3867,
     /* 235132 */     GIR_EraseRootFromParent_Done,
     /* 235133 */   // Label 4462: @235133
     /* 235133 */   GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(235187), // Rule ID 3868 //
     /* 235138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 235146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 235152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 235155 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 235158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235166 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235170 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235174 */     // (intrinsic_wo_chain:{ *:[v16i8] } 527:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 235174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 235177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235179 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235181 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235183 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235185 */     GIR_RootConstrainSelectedInstOperands,
     /* 235186 */     // GIR_Coverage, 3868,
     /* 235186 */     GIR_EraseRootFromParent_Done,
     /* 235187 */   // Label 4463: @235187
     /* 235187 */   GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(235241), // Rule ID 3869 //
     /* 235192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 235200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 235206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 235209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 235212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235216 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235220 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235224 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235228 */     // (intrinsic_wo_chain:{ *:[v8i16] } 527:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 235228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 235231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235237 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235239 */     GIR_RootConstrainSelectedInstOperands,
     /* 235240 */     // GIR_Coverage, 3869,
     /* 235240 */     GIR_EraseRootFromParent_Done,
     /* 235241 */   // Label 4464: @235241
     /* 235241 */   GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(235295), // Rule ID 3870 //
     /* 235246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 235254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235263 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235274 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235278 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235282 */     // (intrinsic_wo_chain:{ *:[v4i32] } 527:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 235282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 235285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235291 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235293 */     GIR_RootConstrainSelectedInstOperands,
     /* 235294 */     // GIR_Coverage, 3870,
     /* 235294 */     GIR_EraseRootFromParent_Done,
     /* 235295 */   // Label 4465: @235295
     /* 235295 */   GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(235349), // Rule ID 3871 //
     /* 235300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 235308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 235314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 235317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 235320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235328 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235332 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235336 */     // (intrinsic_wo_chain:{ *:[v2i64] } 527:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 235336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 235339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235343 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235345 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235347 */     GIR_RootConstrainSelectedInstOperands,
     /* 235348 */     // GIR_Coverage, 3871,
     /* 235348 */     GIR_EraseRootFromParent_Done,
     /* 235349 */   // Label 4466: @235349
     /* 235349 */   GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(235403), // Rule ID 3872 //
     /* 235354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 235362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 235368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 235371 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 235374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235382 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235386 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235390 */     // (intrinsic_wo_chain:{ *:[v16i8] } 525:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 235390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235395 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235397 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235399 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235401 */     GIR_RootConstrainSelectedInstOperands,
     /* 235402 */     // GIR_Coverage, 3872,
     /* 235402 */     GIR_EraseRootFromParent_Done,
     /* 235403 */   // Label 4467: @235403
     /* 235403 */   GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(235457), // Rule ID 3873 //
     /* 235408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 235416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 235422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 235425 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 235428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235436 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235440 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235444 */     // (intrinsic_wo_chain:{ *:[v8i16] } 525:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 235444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235451 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235453 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235455 */     GIR_RootConstrainSelectedInstOperands,
     /* 235456 */     // GIR_Coverage, 3873,
     /* 235456 */     GIR_EraseRootFromParent_Done,
     /* 235457 */   // Label 4468: @235457
     /* 235457 */   GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(235511), // Rule ID 3874 //
     /* 235462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 235470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235479 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235486 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235490 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235494 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235498 */     // (intrinsic_wo_chain:{ *:[v4i32] } 525:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 235498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235507 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235509 */     GIR_RootConstrainSelectedInstOperands,
     /* 235510 */     // GIR_Coverage, 3874,
     /* 235510 */     GIR_EraseRootFromParent_Done,
     /* 235511 */   // Label 4469: @235511
     /* 235511 */   GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(235565), // Rule ID 3875 //
     /* 235516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 235519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 235524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 235530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 235533 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 235536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235548 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235552 */     // (intrinsic_wo_chain:{ *:[v2i64] } 525:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 235552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 235555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235561 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235563 */     GIR_RootConstrainSelectedInstOperands,
     /* 235564 */     // GIR_Coverage, 3875,
     /* 235564 */     GIR_EraseRootFromParent_Done,
     /* 235565 */   // Label 4470: @235565
     /* 235565 */   GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(235619), // Rule ID 3879 //
     /* 235570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 235573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3ss1),
     /* 235578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235584 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235587 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235594 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235598 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235602 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235606 */     // (intrinsic_wo_chain:{ *:[v4i32] } 546:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)  =>  (SM3SS1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /* 235606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3SS1),
     /* 235609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 235613 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 235615 */     GIR_RootToRootCopy, /*OpIdx*/4, // Va
     /* 235617 */     GIR_RootConstrainSelectedInstOperands,
     /* 235618 */     // GIR_Coverage, 3879,
     /* 235618 */     GIR_EraseRootFromParent_Done,
     /* 235619 */   // Label 4471: @235619
     /* 235619 */   GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(235673), // Rule ID 3880 //
     /* 235624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 235627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw1),
     /* 235632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235641 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235652 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235656 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235660 */     // (intrinsic_wo_chain:{ *:[v4i32] } 544:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM3PARTW1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 235660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW1),
     /* 235663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 235665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235669 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235671 */     GIR_RootConstrainSelectedInstOperands,
     /* 235672 */     // GIR_Coverage, 3880,
     /* 235672 */     GIR_EraseRootFromParent_Done,
     /* 235673 */   // Label 4472: @235673
     /* 235673 */   GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(235727), // Rule ID 3881 //
     /* 235678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 235681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw2),
     /* 235686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 235692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 235695 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 235698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235706 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235710 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235714 */     // (intrinsic_wo_chain:{ *:[v4i32] } 545:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM3PARTW2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 235714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW2),
     /* 235717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 235719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 235721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 235723 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 235725 */     GIR_RootConstrainSelectedInstOperands,
     /* 235726 */     // GIR_Coverage, 3881,
     /* 235726 */     GIR_EraseRootFromParent_Done,
     /* 235727 */   // Label 4473: @235727
     /* 235727 */   GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(235784), // Rule ID 3898 //
     /* 235732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 235735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 235740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 235743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 235746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 235749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 235752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235756 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235760 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235764 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235768 */     // (intrinsic_wo_chain:{ *:[v4f16] } 767:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
     /* 235768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 235771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 235773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 235775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 235777 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 235779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 235782 */     GIR_RootConstrainSelectedInstOperands,
     /* 235783 */     // GIR_Coverage, 3898,
     /* 235783 */     GIR_EraseRootFromParent_Done,
     /* 235784 */   // Label 4474: @235784
     /* 235784 */   GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(235841), // Rule ID 3899 //
     /* 235789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 235792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 235797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 235800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 235803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 235806 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 235809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235813 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235817 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235821 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235825 */     // (intrinsic_wo_chain:{ *:[v4f16] } 770:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
     /* 235825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 235828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 235830 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 235832 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 235834 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 235836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 235839 */     GIR_RootConstrainSelectedInstOperands,
     /* 235840 */     // GIR_Coverage, 3899,
     /* 235840 */     GIR_EraseRootFromParent_Done,
     /* 235841 */   // Label 4475: @235841
     /* 235841 */   GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(235898), // Rule ID 3900 //
     /* 235846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 235849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 235854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 235857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 235860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 235863 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 235866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235878 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235882 */     // (intrinsic_wo_chain:{ *:[v4f16] } 768:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 2:{ *:[i32] })
     /* 235882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 235885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 235887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 235889 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 235891 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 235893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 235896 */     GIR_RootConstrainSelectedInstOperands,
     /* 235897 */     // GIR_Coverage, 3900,
     /* 235897 */     GIR_EraseRootFromParent_Done,
     /* 235898 */   // Label 4476: @235898
     /* 235898 */   GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(235955), // Rule ID 3901 //
     /* 235903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 235906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 235911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 235914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 235917 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 235920 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 235923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235927 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235931 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235935 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 235939 */     // (intrinsic_wo_chain:{ *:[v4f16] } 769:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 3:{ *:[i32] })
     /* 235939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 235942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 235944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 235946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 235948 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 235950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 235953 */     GIR_RootConstrainSelectedInstOperands,
     /* 235954 */     // GIR_Coverage, 3901,
     /* 235954 */     GIR_EraseRootFromParent_Done,
     /* 235955 */   // Label 4477: @235955
     /* 235955 */   GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(236012), // Rule ID 3906 //
     /* 235960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 235963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 235968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 235974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 235977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 235980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235988 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235992 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235996 */     // (intrinsic_wo_chain:{ *:[v8f16] } 767:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
     /* 235996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 235999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236003 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236005 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 236010 */     GIR_RootConstrainSelectedInstOperands,
     /* 236011 */     // GIR_Coverage, 3906,
     /* 236011 */     GIR_EraseRootFromParent_Done,
     /* 236012 */   // Label 4478: @236012
     /* 236012 */   GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(236069), // Rule ID 3907 //
     /* 236017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 236020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 236025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 236031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 236034 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 236037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236041 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236045 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236049 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236053 */     // (intrinsic_wo_chain:{ *:[v8f16] } 770:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
     /* 236053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 236056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236058 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236060 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236062 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 236067 */     GIR_RootConstrainSelectedInstOperands,
     /* 236068 */     // GIR_Coverage, 3907,
     /* 236068 */     GIR_EraseRootFromParent_Done,
     /* 236069 */   // Label 4479: @236069
     /* 236069 */   GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(236126), // Rule ID 3908 //
     /* 236074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 236077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 236082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 236088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 236091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 236094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236102 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236106 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236110 */     // (intrinsic_wo_chain:{ *:[v8f16] } 768:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 2:{ *:[i32] })
     /* 236110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 236113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236117 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236119 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 236124 */     GIR_RootConstrainSelectedInstOperands,
     /* 236125 */     // GIR_Coverage, 3908,
     /* 236125 */     GIR_EraseRootFromParent_Done,
     /* 236126 */   // Label 4480: @236126
     /* 236126 */   GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(236183), // Rule ID 3909 //
     /* 236131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 236134 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 236139 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236142 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 236145 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 236148 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 236151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236159 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236163 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236167 */     // (intrinsic_wo_chain:{ *:[v8f16] } 769:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 3:{ *:[i32] })
     /* 236167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 236170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236176 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 236181 */     GIR_RootConstrainSelectedInstOperands,
     /* 236182 */     // GIR_Coverage, 3909,
     /* 236182 */     GIR_EraseRootFromParent_Done,
     /* 236183 */   // Label 4481: @236183
     /* 236183 */   GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(236240), // Rule ID 3914 //
     /* 236188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 236196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 236199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 236202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 236205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 236208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236216 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236220 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236224 */     // (intrinsic_wo_chain:{ *:[v2f32] } 767:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
     /* 236224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 236227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236231 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236233 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 236238 */     GIR_RootConstrainSelectedInstOperands,
     /* 236239 */     // GIR_Coverage, 3914,
     /* 236239 */     GIR_EraseRootFromParent_Done,
     /* 236240 */   // Label 4482: @236240
     /* 236240 */   GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(236297), // Rule ID 3915 //
     /* 236245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 236253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 236256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 236259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 236262 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 236265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236273 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236277 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236281 */     // (intrinsic_wo_chain:{ *:[v2f32] } 770:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
     /* 236281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 236284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236286 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236288 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236290 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 236295 */     GIR_RootConstrainSelectedInstOperands,
     /* 236296 */     // GIR_Coverage, 3915,
     /* 236296 */     GIR_EraseRootFromParent_Done,
     /* 236297 */   // Label 4483: @236297
     /* 236297 */   GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(236354), // Rule ID 3916 //
     /* 236302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236305 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 236310 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 236313 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 236316 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 236319 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 236322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236326 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236330 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236334 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236338 */     // (intrinsic_wo_chain:{ *:[v2f32] } 768:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 2:{ *:[i32] })
     /* 236338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 236341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236347 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 236352 */     GIR_RootConstrainSelectedInstOperands,
     /* 236353 */     // GIR_Coverage, 3916,
     /* 236353 */     GIR_EraseRootFromParent_Done,
     /* 236354 */   // Label 4484: @236354
     /* 236354 */   GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(236411), // Rule ID 3917 //
     /* 236359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 236367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 236370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 236373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 236376 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 236379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236383 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236387 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236391 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 236395 */     // (intrinsic_wo_chain:{ *:[v2f32] } 769:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 3:{ *:[i32] })
     /* 236395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 236398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236402 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236404 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 236409 */     GIR_RootConstrainSelectedInstOperands,
     /* 236410 */     // GIR_Coverage, 3917,
     /* 236410 */     GIR_EraseRootFromParent_Done,
     /* 236411 */   // Label 4485: @236411
     /* 236411 */   GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(236468), // Rule ID 3918 //
     /* 236416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 236424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 236430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 236433 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 236436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236444 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236448 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236452 */     // (intrinsic_wo_chain:{ *:[v4f32] } 767:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
     /* 236452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 236455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236461 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 236466 */     GIR_RootConstrainSelectedInstOperands,
     /* 236467 */     // GIR_Coverage, 3918,
     /* 236467 */     GIR_EraseRootFromParent_Done,
     /* 236468 */   // Label 4486: @236468
     /* 236468 */   GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(236525), // Rule ID 3919 //
     /* 236473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 236481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236484 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 236487 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 236490 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 236493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236497 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236501 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236505 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236509 */     // (intrinsic_wo_chain:{ *:[v4f32] } 770:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
     /* 236509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 236512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236518 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 236523 */     GIR_RootConstrainSelectedInstOperands,
     /* 236524 */     // GIR_Coverage, 3919,
     /* 236524 */     GIR_EraseRootFromParent_Done,
     /* 236525 */   // Label 4487: @236525
     /* 236525 */   GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(236582), // Rule ID 3920 //
     /* 236530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 236538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 236544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 236547 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 236550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236558 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236562 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236566 */     // (intrinsic_wo_chain:{ *:[v4f32] } 768:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 2:{ *:[i32] })
     /* 236566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 236569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236575 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 236580 */     GIR_RootConstrainSelectedInstOperands,
     /* 236581 */     // GIR_Coverage, 3920,
     /* 236581 */     GIR_EraseRootFromParent_Done,
     /* 236582 */   // Label 4488: @236582
     /* 236582 */   GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(236639), // Rule ID 3921 //
     /* 236587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 236595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 236601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 236604 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 236607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236615 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236619 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236623 */     // (intrinsic_wo_chain:{ *:[v4f32] } 769:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 3:{ *:[i32] })
     /* 236623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 236626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236632 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 236637 */     GIR_RootConstrainSelectedInstOperands,
     /* 236638 */     // GIR_Coverage, 3921,
     /* 236638 */     GIR_EraseRootFromParent_Done,
     /* 236639 */   // Label 4489: @236639
     /* 236639 */   GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(236696), // Rule ID 3922 //
     /* 236644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236647 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 236652 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 236658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 236661 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 236664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236668 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236672 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236676 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236680 */     // (intrinsic_wo_chain:{ *:[v2f64] } 767:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
     /* 236680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 236683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236687 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236689 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 236694 */     GIR_RootConstrainSelectedInstOperands,
     /* 236695 */     // GIR_Coverage, 3922,
     /* 236695 */     GIR_EraseRootFromParent_Done,
     /* 236696 */   // Label 4490: @236696
     /* 236696 */   GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(236753), // Rule ID 3923 //
     /* 236701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 236709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 236715 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 236718 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 236721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236725 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236729 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236733 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236737 */     // (intrinsic_wo_chain:{ *:[v2f64] } 770:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
     /* 236737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 236740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236746 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 236751 */     GIR_RootConstrainSelectedInstOperands,
     /* 236752 */     // GIR_Coverage, 3923,
     /* 236752 */     GIR_EraseRootFromParent_Done,
     /* 236753 */   // Label 4491: @236753
     /* 236753 */   GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(236810), // Rule ID 3924 //
     /* 236758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 236766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 236772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 236775 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 236778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236786 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236790 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236794 */     // (intrinsic_wo_chain:{ *:[v2f64] } 768:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 2:{ *:[i32] })
     /* 236794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 236797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236803 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 236808 */     GIR_RootConstrainSelectedInstOperands,
     /* 236809 */     // GIR_Coverage, 3924,
     /* 236809 */     GIR_EraseRootFromParent_Done,
     /* 236810 */   // Label 4492: @236810
     /* 236810 */   GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(236867), // Rule ID 3925 //
     /* 236815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 236818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 236823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 236829 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 236832 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 236835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236847 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236851 */     // (intrinsic_wo_chain:{ *:[v2f64] } 769:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 3:{ *:[i32] })
     /* 236851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 236854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236860 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 236865 */     GIR_RootConstrainSelectedInstOperands,
     /* 236866 */     // GIR_Coverage, 3925,
     /* 236866 */     GIR_EraseRootFromParent_Done,
     /* 236867 */   // Label 4493: @236867
     /* 236867 */   GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(236921), // Rule ID 5280 //
     /* 236872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
     /* 236875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 236880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 236883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 236886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 236889 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 236892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236896 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236900 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236904 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236908 */     // (intrinsic_wo_chain:{ *:[i32] } 696:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 236908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32),
     /* 236911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236913 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236915 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236917 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236919 */     GIR_RootConstrainSelectedInstOperands,
     /* 236920 */     // GIR_Coverage, 5280,
     /* 236920 */     GIR_EraseRootFromParent_Done,
     /* 236921 */   // Label 4494: @236921
     /* 236921 */   GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(236975), // Rule ID 5281 //
     /* 236926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
     /* 236929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 236934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 236937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 236940 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 236943 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 236946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236950 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236954 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236958 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 236962 */     // (intrinsic_wo_chain:{ *:[i32] } 697:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 236962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32),
     /* 236965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 236967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 236969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 236971 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 236973 */     GIR_RootConstrainSelectedInstOperands,
     /* 236974 */     // GIR_Coverage, 5281,
     /* 236974 */     GIR_EraseRootFromParent_Done,
     /* 236975 */   // Label 4495: @236975
     /* 236975 */   GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(237026), // Rule ID 5634 //
     /* 236980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
     /* 236985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 236988 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 236991 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 236994 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 236997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237001 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237005 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237009 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237013 */     // (intrinsic_wo_chain:{ *:[v8i8] } 730:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)  =>  (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
     /* 237013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv8i8One),
     /* 237016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 237022 */     GIR_RootToRootCopy, /*OpIdx*/4, // Ri
     /* 237024 */     GIR_RootConstrainSelectedInstOperands,
     /* 237025 */     // GIR_Coverage, 5634,
     /* 237025 */     GIR_EraseRootFromParent_Done,
     /* 237026 */   // Label 4496: @237026
     /* 237026 */   GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(237077), // Rule ID 5635 //
     /* 237031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
     /* 237036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 237039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 237042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 237045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 237048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237052 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237056 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237060 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237064 */     // (intrinsic_wo_chain:{ *:[v16i8] } 730:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)  =>  (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
     /* 237064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv16i8One),
     /* 237067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237071 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ri
     /* 237073 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 237075 */     GIR_RootConstrainSelectedInstOperands,
     /* 237076 */     // GIR_Coverage, 5635,
     /* 237076 */     GIR_EraseRootFromParent_Done,
     /* 237077 */   // Label 4497: @237077
     /* 237077 */   GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(237119), // Rule ID 2699 //
     /* 237082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 237093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 237096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 237099 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 237102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237106 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1928:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (TBX_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 237106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_B),
     /* 237109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237111 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237113 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237115 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237117 */     GIR_RootConstrainSelectedInstOperands,
     /* 237118 */     // GIR_Coverage, 2699,
     /* 237118 */     GIR_EraseRootFromParent_Done,
     /* 237119 */   // Label 4498: @237119
     /* 237119 */   GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(237161), // Rule ID 2700 //
     /* 237124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 237138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237141 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 237144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237148 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1928:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBX_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 237148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
     /* 237151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237155 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237157 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237159 */     GIR_RootConstrainSelectedInstOperands,
     /* 237160 */     // GIR_Coverage, 2700,
     /* 237160 */     GIR_EraseRootFromParent_Done,
     /* 237161 */   // Label 4499: @237161
     /* 237161 */   GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(237203), // Rule ID 2701 //
     /* 237166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237169 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237174 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237177 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237180 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237183 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237190 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1928:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBX_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 237190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
     /* 237193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237195 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237197 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237199 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237201 */     GIR_RootConstrainSelectedInstOperands,
     /* 237202 */     // GIR_Coverage, 2701,
     /* 237202 */     GIR_EraseRootFromParent_Done,
     /* 237203 */   // Label 4500: @237203
     /* 237203 */   GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(237245), // Rule ID 2702 //
     /* 237208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237211 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237216 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237219 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 237222 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237225 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 237228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237232 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1928:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBX_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 237232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
     /* 237235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237241 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237243 */     GIR_RootConstrainSelectedInstOperands,
     /* 237244 */     // GIR_Coverage, 2702,
     /* 237244 */     GIR_EraseRootFromParent_Done,
     /* 237245 */   // Label 4501: @237245
     /* 237245 */   GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(237287), // Rule ID 2703 //
     /* 237250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 237264 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237267 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 237270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237274 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1928:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBX_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 237274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
     /* 237277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237281 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237283 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237285 */     GIR_RootConstrainSelectedInstOperands,
     /* 237286 */     // GIR_Coverage, 2703,
     /* 237286 */     GIR_EraseRootFromParent_Done,
     /* 237287 */   // Label 4502: @237287
     /* 237287 */   GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(237329), // Rule ID 2704 //
     /* 237292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237303 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237306 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237309 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237316 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1928:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBX_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 237316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
     /* 237319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237321 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237323 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237325 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237327 */     GIR_RootConstrainSelectedInstOperands,
     /* 237328 */     // GIR_Coverage, 2704,
     /* 237328 */     GIR_EraseRootFromParent_Done,
     /* 237329 */   // Label 4503: @237329
     /* 237329 */   GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(237371), // Rule ID 2705 //
     /* 237334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 237342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 237348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237351 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 237354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237358 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1928:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBX_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 237358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
     /* 237361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237367 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237369 */     GIR_RootConstrainSelectedInstOperands,
     /* 237370 */     // GIR_Coverage, 2705,
     /* 237370 */     GIR_EraseRootFromParent_Done,
     /* 237371 */   // Label 4504: @237371
     /* 237371 */   GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(237413), // Rule ID 2744 //
     /* 237376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 237384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 237387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 237390 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 237393 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 237396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 237400 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1274:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 237400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 237403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 237405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237407 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237409 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237411 */     GIR_RootConstrainSelectedInstOperands,
     /* 237412 */     // GIR_Coverage, 2744,
     /* 237412 */     GIR_EraseRootFromParent_Done,
     /* 237413 */   // Label 4505: @237413
     /* 237413 */   GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(237455), // Rule ID 2745 //
     /* 237418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 237426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 237429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 237432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 237435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 237438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 237442 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1274:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 237442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 237445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 237447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237449 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237451 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237453 */     GIR_RootConstrainSelectedInstOperands,
     /* 237454 */     // GIR_Coverage, 2745,
     /* 237454 */     GIR_EraseRootFromParent_Done,
     /* 237455 */   // Label 4506: @237455
     /* 237455 */   GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(237497), // Rule ID 2746 //
     /* 237460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 237468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 237471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 237474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 237477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 237480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 237484 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1274:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 237484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 237487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 237489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237491 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237493 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237495 */     GIR_RootConstrainSelectedInstOperands,
     /* 237496 */     // GIR_Coverage, 2746,
     /* 237496 */     GIR_EraseRootFromParent_Done,
     /* 237497 */   // Label 4507: @237497
     /* 237497 */   GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(237539), // Rule ID 2747 //
     /* 237502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 237510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 237513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 237516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 237519 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 237522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 237526 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1274:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 237526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 237529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 237531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237533 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237535 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237537 */     GIR_RootConstrainSelectedInstOperands,
     /* 237538 */     // GIR_Coverage, 2747,
     /* 237538 */     GIR_EraseRootFromParent_Done,
     /* 237539 */   // Label 4508: @237539
     /* 237539 */   GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(237581), // Rule ID 2748 //
     /* 237544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 237552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 237555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 237558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 237561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 237564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 237568 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1274:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 237568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 237571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 237573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237577 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237579 */     GIR_RootConstrainSelectedInstOperands,
     /* 237580 */     // GIR_Coverage, 2748,
     /* 237580 */     GIR_EraseRootFromParent_Done,
     /* 237581 */   // Label 4509: @237581
     /* 237581 */   GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(237623), // Rule ID 2787 //
     /* 237586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 237594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 237600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237603 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 237606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237610 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1373:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FADD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 237610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_H),
     /* 237613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237615 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237617 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237619 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237621 */     GIR_RootConstrainSelectedInstOperands,
     /* 237622 */     // GIR_Coverage, 2787,
     /* 237622 */     GIR_EraseRootFromParent_Done,
     /* 237623 */   // Label 4510: @237623
     /* 237623 */   GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(237665), // Rule ID 2789 //
     /* 237628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 237636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 237642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237645 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237652 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1373:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FADD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 237652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_S),
     /* 237655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237661 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237663 */     GIR_RootConstrainSelectedInstOperands,
     /* 237664 */     // GIR_Coverage, 2789,
     /* 237664 */     GIR_EraseRootFromParent_Done,
     /* 237665 */   // Label 4511: @237665
     /* 237665 */   GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(237707), // Rule ID 2791 //
     /* 237670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 237678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 237684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237687 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 237690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237694 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1373:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FADD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 237694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_D),
     /* 237697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237701 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237703 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237705 */     GIR_RootConstrainSelectedInstOperands,
     /* 237706 */     // GIR_Coverage, 2791,
     /* 237706 */     GIR_EraseRootFromParent_Done,
     /* 237707 */   // Label 4512: @237707
     /* 237707 */   GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(237749), // Rule ID 2793 //
     /* 237712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 237720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 237726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237729 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 237732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237736 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1547:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (FSCALE_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 237736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_H),
     /* 237739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237743 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237745 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237747 */     GIR_RootConstrainSelectedInstOperands,
     /* 237748 */     // GIR_Coverage, 2793,
     /* 237748 */     GIR_EraseRootFromParent_Done,
     /* 237749 */   // Label 4513: @237749
     /* 237749 */   GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(237791), // Rule ID 2794 //
     /* 237754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 237762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 237768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237771 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237778 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1547:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (FSCALE_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 237778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_S),
     /* 237781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237787 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237789 */     GIR_RootConstrainSelectedInstOperands,
     /* 237790 */     // GIR_Coverage, 2794,
     /* 237790 */     GIR_EraseRootFromParent_Done,
     /* 237791 */   // Label 4514: @237791
     /* 237791 */   GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(237833), // Rule ID 2795 //
     /* 237796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 237799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 237804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 237810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237813 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 237816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237820 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1547:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (FSCALE_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 237820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_D),
     /* 237823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 237825 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237827 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237829 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237831 */     GIR_RootConstrainSelectedInstOperands,
     /* 237832 */     // GIR_Coverage, 2795,
     /* 237832 */     GIR_EraseRootFromParent_Done,
     /* 237833 */   // Label 4515: @237833
     /* 237833 */   GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(237875), // Rule ID 2879 //
     /* 237838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f16f32),
     /* 237846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 237852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 237855 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237862 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1409:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTNT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 237862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_StoH),
     /* 237865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237871 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237873 */     GIR_RootConstrainSelectedInstOperands,
     /* 237874 */     // GIR_Coverage, 2879,
     /* 237874 */     GIR_EraseRootFromParent_Done,
     /* 237875 */   // Label 4516: @237875
     /* 237875 */   GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(237917), // Rule ID 2880 //
     /* 237880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f32f64),
     /* 237888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 237897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 237900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237904 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1410:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 237904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_DtoS),
     /* 237907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237913 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237915 */     GIR_RootConstrainSelectedInstOperands,
     /* 237916 */     // GIR_Coverage, 2880,
     /* 237916 */     GIR_EraseRootFromParent_Done,
     /* 237917 */   // Label 4517: @237917
     /* 237917 */   GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(237959), // Rule ID 2881 //
     /* 237922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f32f16),
     /* 237930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 237939 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 237942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237946 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1405:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTLT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 237946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_HtoS),
     /* 237949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237951 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237955 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237957 */     GIR_RootConstrainSelectedInstOperands,
     /* 237958 */     // GIR_Coverage, 2881,
     /* 237958 */     GIR_EraseRootFromParent_Done,
     /* 237959 */   // Label 4518: @237959
     /* 237959 */   GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(238001), // Rule ID 2882 //
     /* 237964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 237967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f64f32),
     /* 237972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 237978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 237981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 237984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237988 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1406:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTLT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 237988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_StoD),
     /* 237991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237997 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 237999 */     GIR_RootConstrainSelectedInstOperands,
     /* 238000 */     // GIR_Coverage, 2882,
     /* 238000 */     GIR_EraseRootFromParent_Done,
     /* 238001 */   // Label 4519: @238001
     /* 238001 */   GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(238043), // Rule ID 2883 //
     /* 238006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtxnt_f32f64),
     /* 238014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 238023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238030 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1412:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTXNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 238030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNT_ZPmZ_DtoS),
     /* 238033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238039 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238041 */     GIR_RootConstrainSelectedInstOperands,
     /* 238042 */     // GIR_Coverage, 2883,
     /* 238042 */     GIR_EraseRootFromParent_Done,
     /* 238043 */   // Label 4520: @238043
     /* 238043 */   GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(238085), // Rule ID 2884 //
     /* 238048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 238056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 238062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 238065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238072 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1376:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FADDP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 238072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_H),
     /* 238075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238079 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238081 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238083 */     GIR_RootConstrainSelectedInstOperands,
     /* 238084 */     // GIR_Coverage, 2884,
     /* 238084 */     GIR_EraseRootFromParent_Done,
     /* 238085 */   // Label 4521: @238085
     /* 238085 */   GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(238127), // Rule ID 2885 //
     /* 238090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 238098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 238104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 238107 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238114 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1376:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FADDP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 238114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_S),
     /* 238117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238121 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238123 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238125 */     GIR_RootConstrainSelectedInstOperands,
     /* 238126 */     // GIR_Coverage, 2885,
     /* 238126 */     GIR_EraseRootFromParent_Done,
     /* 238127 */   // Label 4522: @238127
     /* 238127 */   GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(238169), // Rule ID 2886 //
     /* 238132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 238140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 238146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 238149 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238156 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1376:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FADDP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 238156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_D),
     /* 238159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238165 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238167 */     GIR_RootConstrainSelectedInstOperands,
     /* 238168 */     // GIR_Coverage, 2886,
     /* 238168 */     GIR_EraseRootFromParent_Done,
     /* 238169 */   // Label 4523: @238169
     /* 238169 */   GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(238211), // Rule ID 2897 //
     /* 238174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 238177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f16),
     /* 238182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 238191 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238198 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1398:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 238198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoS),
     /* 238201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238207 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238209 */     GIR_RootConstrainSelectedInstOperands,
     /* 238210 */     // GIR_Coverage, 2897,
     /* 238210 */     GIR_EraseRootFromParent_Done,
     /* 238211 */   // Label 4524: @238211
     /* 238211 */   GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(238253), // Rule ID 2899 //
     /* 238216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 238219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f32),
     /* 238224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 238230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 238233 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238240 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1396:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 238240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoH),
     /* 238243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238247 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238249 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238251 */     GIR_RootConstrainSelectedInstOperands,
     /* 238252 */     // GIR_Coverage, 2899,
     /* 238252 */     GIR_EraseRootFromParent_Done,
     /* 238253 */   // Label 4525: @238253
     /* 238253 */   GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(238295), // Rule ID 2907 //
     /* 238258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 238266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 238272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 238275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238282 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1433:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FLOGB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 238282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_H),
     /* 238285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238291 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238293 */     GIR_RootConstrainSelectedInstOperands,
     /* 238294 */     // GIR_Coverage, 2907,
     /* 238294 */     GIR_EraseRootFromParent_Done,
     /* 238295 */   // Label 4526: @238295
     /* 238295 */   GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(238337), // Rule ID 2908 //
     /* 238300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 238308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 238317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238324 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1433:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FLOGB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 238324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_S),
     /* 238327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238329 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238331 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238333 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238335 */     GIR_RootConstrainSelectedInstOperands,
     /* 238336 */     // GIR_Coverage, 2908,
     /* 238336 */     GIR_EraseRootFromParent_Done,
     /* 238337 */   // Label 4527: @238337
     /* 238337 */   GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(238379), // Rule ID 2909 //
     /* 238342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 238350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 238356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 238359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238366 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1433:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FLOGB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 238366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_D),
     /* 238369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238371 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238375 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238377 */     GIR_RootConstrainSelectedInstOperands,
     /* 238378 */     // GIR_Coverage, 2909,
     /* 238378 */     GIR_EraseRootFromParent_Done,
     /* 238379 */   // Label 4528: @238379
     /* 238379 */   GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(238421), // Rule ID 2913 //
     /* 238384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtx_f32f64),
     /* 238392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 238401 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238408 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1411:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTX_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 238408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTX_ZPmZ_DtoS),
     /* 238411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 238413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238417 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238419 */     GIR_RootConstrainSelectedInstOperands,
     /* 238420 */     // GIR_Coverage, 2913,
     /* 238420 */     GIR_EraseRootFromParent_Done,
     /* 238421 */   // Label 4529: @238421
     /* 238421 */   GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(238463), // Rule ID 2958 //
     /* 238426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 238429 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
     /* 238434 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238437 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 238440 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 238443 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238450 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1716:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 238450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_S),
     /* 238453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238457 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238459 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238461 */     GIR_RootConstrainSelectedInstOperands,
     /* 238462 */     // GIR_Coverage, 2958,
     /* 238462 */     GIR_EraseRootFromParent_Done,
     /* 238463 */   // Label 4530: @238463
     /* 238463 */   GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(238505), // Rule ID 2959 //
     /* 238468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 238471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
     /* 238476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 238482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 238485 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238492 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1716:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 238492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_D),
     /* 238495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238501 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238503 */     GIR_RootConstrainSelectedInstOperands,
     /* 238504 */     // GIR_Coverage, 2959,
     /* 238504 */     GIR_EraseRootFromParent_Done,
     /* 238505 */   // Label 4531: @238505
     /* 238505 */   GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(238547), // Rule ID 2988 //
     /* 238510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 238518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 238521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 238524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 238527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 238530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238534 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1832:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRDMLAH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 238534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_B),
     /* 238537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238539 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238541 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238543 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238545 */     GIR_RootConstrainSelectedInstOperands,
     /* 238546 */     // GIR_Coverage, 2988,
     /* 238546 */     GIR_EraseRootFromParent_Done,
     /* 238547 */   // Label 4532: @238547
     /* 238547 */   GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(238589), // Rule ID 2989 //
     /* 238552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 238560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 238566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 238569 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238576 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1832:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRDMLAH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 238576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_H),
     /* 238579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238581 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238583 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238585 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238587 */     GIR_RootConstrainSelectedInstOperands,
     /* 238588 */     // GIR_Coverage, 2989,
     /* 238588 */     GIR_EraseRootFromParent_Done,
     /* 238589 */   // Label 4533: @238589
     /* 238589 */   GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(238631), // Rule ID 2990 //
     /* 238594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 238602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 238611 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238618 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1832:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRDMLAH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 238618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_S),
     /* 238621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238627 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238629 */     GIR_RootConstrainSelectedInstOperands,
     /* 238630 */     // GIR_Coverage, 2990,
     /* 238630 */     GIR_EraseRootFromParent_Done,
     /* 238631 */   // Label 4534: @238631
     /* 238631 */   GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(238673), // Rule ID 2991 //
     /* 238636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 238644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 238650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 238653 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238660 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1832:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRDMLAH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 238660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_D),
     /* 238663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238669 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238671 */     GIR_RootConstrainSelectedInstOperands,
     /* 238672 */     // GIR_Coverage, 2991,
     /* 238672 */     GIR_EraseRootFromParent_Done,
     /* 238673 */   // Label 4535: @238673
     /* 238673 */   GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(238715), // Rule ID 2992 //
     /* 238678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 238686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 238692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 238695 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 238698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238702 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1753:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 238702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_H),
     /* 238705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238709 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238711 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238713 */     GIR_RootConstrainSelectedInstOperands,
     /* 238714 */     // GIR_Coverage, 2992,
     /* 238714 */     GIR_EraseRootFromParent_Done,
     /* 238715 */   // Label 4536: @238715
     /* 238715 */   GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(238757), // Rule ID 2993 //
     /* 238720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 238728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 238734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 238737 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238744 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1753:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 238744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_S),
     /* 238747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238751 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238753 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238755 */     GIR_RootConstrainSelectedInstOperands,
     /* 238756 */     // GIR_Coverage, 2993,
     /* 238756 */     GIR_EraseRootFromParent_Done,
     /* 238757 */   // Label 4537: @238757
     /* 238757 */   GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(238799), // Rule ID 2994 //
     /* 238762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 238770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 238776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 238779 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238786 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1753:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 238786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_D),
     /* 238789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 238791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238793 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238795 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238797 */     GIR_RootConstrainSelectedInstOperands,
     /* 238798 */     // GIR_Coverage, 2994,
     /* 238798 */     GIR_EraseRootFromParent_Done,
     /* 238799 */   // Label 4538: @238799
     /* 238799 */   GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(238841), // Rule ID 3024 //
     /* 238804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 238812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 238815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 238818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 238821 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 238824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238828 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1727:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 238828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_B),
     /* 238831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238833 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238835 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238837 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238839 */     GIR_RootConstrainSelectedInstOperands,
     /* 238840 */     // GIR_Coverage, 3024,
     /* 238840 */     GIR_EraseRootFromParent_Done,
     /* 238841 */   // Label 4539: @238841
     /* 238841 */   GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(238883), // Rule ID 3026 //
     /* 238846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 238854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 238860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 238863 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 238866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238870 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1727:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 238870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_H),
     /* 238873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238875 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238877 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238879 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238881 */     GIR_RootConstrainSelectedInstOperands,
     /* 238882 */     // GIR_Coverage, 3026,
     /* 238882 */     GIR_EraseRootFromParent_Done,
     /* 238883 */   // Label 4540: @238883
     /* 238883 */   GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(238925), // Rule ID 3028 //
     /* 238888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 238896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 238899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 238902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 238905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 238908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238912 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1727:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 238912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_S),
     /* 238915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238921 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238923 */     GIR_RootConstrainSelectedInstOperands,
     /* 238924 */     // GIR_Coverage, 3028,
     /* 238924 */     GIR_EraseRootFromParent_Done,
     /* 238925 */   // Label 4541: @238925
     /* 238925 */   GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(238967), // Rule ID 3030 //
     /* 238930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 238938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 238941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 238944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 238947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 238950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238954 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1727:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 238954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_D),
     /* 238957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 238959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 238961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 238963 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 238965 */     GIR_RootConstrainSelectedInstOperands,
     /* 238966 */     // GIR_Coverage, 3030,
     /* 238966 */     GIR_EraseRootFromParent_Done,
     /* 238967 */   // Label 4542: @238967
     /* 238967 */   GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(239009), // Rule ID 3032 //
     /* 238972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 238975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 238980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 238983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 238986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 238989 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 238992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 238996 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1697:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 238996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_H),
     /* 238999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239003 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239005 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239007 */     GIR_RootConstrainSelectedInstOperands,
     /* 239008 */     // GIR_Coverage, 3032,
     /* 239008 */     GIR_EraseRootFromParent_Done,
     /* 239009 */   // Label 4543: @239009
     /* 239009 */   GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(239051), // Rule ID 3033 //
     /* 239014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 239022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 239028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239038 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1697:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_S),
     /* 239041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239047 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239049 */     GIR_RootConstrainSelectedInstOperands,
     /* 239050 */     // GIR_Coverage, 3033,
     /* 239050 */     GIR_EraseRootFromParent_Done,
     /* 239051 */   // Label 4544: @239051
     /* 239051 */   GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(239093), // Rule ID 3034 //
     /* 239056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 239064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 239070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 239073 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239080 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1697:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_D),
     /* 239083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239089 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239091 */     GIR_RootConstrainSelectedInstOperands,
     /* 239092 */     // GIR_Coverage, 3034,
     /* 239092 */     GIR_EraseRootFromParent_Done,
     /* 239093 */   // Label 4545: @239093
     /* 239093 */   GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(239135), // Rule ID 3035 //
     /* 239098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
     /* 239106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 239115 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239122 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2056:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URECPE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S),
     /* 239125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239127 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239129 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239131 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239133 */     GIR_RootConstrainSelectedInstOperands,
     /* 239134 */     // GIR_Coverage, 3035,
     /* 239134 */     GIR_EraseRootFromParent_Done,
     /* 239135 */   // Label 4546: @239135
     /* 239135 */   GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(239177), // Rule ID 3036 //
     /* 239140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 239148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 239151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 239154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 239157 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 239160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239164 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1769:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQABS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 239164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B),
     /* 239167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239175 */     GIR_RootConstrainSelectedInstOperands,
     /* 239176 */     // GIR_Coverage, 3036,
     /* 239176 */     GIR_EraseRootFromParent_Done,
     /* 239177 */   // Label 4547: @239177
     /* 239177 */   GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(239219), // Rule ID 3037 //
     /* 239182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 239190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 239199 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239206 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1769:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQABS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H),
     /* 239209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239211 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239213 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239215 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239217 */     GIR_RootConstrainSelectedInstOperands,
     /* 239218 */     // GIR_Coverage, 3037,
     /* 239218 */     GIR_EraseRootFromParent_Done,
     /* 239219 */   // Label 4548: @239219
     /* 239219 */   GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(239261), // Rule ID 3038 //
     /* 239224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 239232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 239241 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239248 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1769:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQABS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S),
     /* 239251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239257 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239259 */     GIR_RootConstrainSelectedInstOperands,
     /* 239260 */     // GIR_Coverage, 3038,
     /* 239260 */     GIR_EraseRootFromParent_Done,
     /* 239261 */   // Label 4549: @239261
     /* 239261 */   GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(239303), // Rule ID 3039 //
     /* 239266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 239274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 239280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 239283 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 239286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239290 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1769:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQABS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 239290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D),
     /* 239293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239297 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239299 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239301 */     GIR_RootConstrainSelectedInstOperands,
     /* 239302 */     // GIR_Coverage, 3039,
     /* 239302 */     GIR_EraseRootFromParent_Done,
     /* 239303 */   // Label 4550: @239303
     /* 239303 */   GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(239345), // Rule ID 3056 //
     /* 239308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 239316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 239319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 239322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 239325 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 239328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239332 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1362:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EORBT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 239332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_B),
     /* 239335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239337 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239339 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239341 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239343 */     GIR_RootConstrainSelectedInstOperands,
     /* 239344 */     // GIR_Coverage, 3056,
     /* 239344 */     GIR_EraseRootFromParent_Done,
     /* 239345 */   // Label 4551: @239345
     /* 239345 */   GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(239387), // Rule ID 3057 //
     /* 239350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 239358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 239367 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239374 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1362:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EORBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_H),
     /* 239377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239379 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239383 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239385 */     GIR_RootConstrainSelectedInstOperands,
     /* 239386 */     // GIR_Coverage, 3057,
     /* 239386 */     GIR_EraseRootFromParent_Done,
     /* 239387 */   // Label 4552: @239387
     /* 239387 */   GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(239429), // Rule ID 3058 //
     /* 239392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 239400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239416 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1362:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EORBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_S),
     /* 239419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239423 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239425 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239427 */     GIR_RootConstrainSelectedInstOperands,
     /* 239428 */     // GIR_Coverage, 3058,
     /* 239428 */     GIR_EraseRootFromParent_Done,
     /* 239429 */   // Label 4553: @239429
     /* 239429 */   GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(239471), // Rule ID 3059 //
     /* 239434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 239442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 239448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 239451 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 239454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239458 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1362:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EORBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 239458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_D),
     /* 239461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239465 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239467 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239469 */     GIR_RootConstrainSelectedInstOperands,
     /* 239470 */     // GIR_Coverage, 3059,
     /* 239470 */     GIR_EraseRootFromParent_Done,
     /* 239471 */   // Label 4554: @239471
     /* 239471 */   GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(239513), // Rule ID 3083 //
     /* 239476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 239484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 239487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 239490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 239493 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 239496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239500 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1690:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 239500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_B),
     /* 239503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239507 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239509 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239511 */     GIR_RootConstrainSelectedInstOperands,
     /* 239512 */     // GIR_Coverage, 3083,
     /* 239512 */     GIR_EraseRootFromParent_Done,
     /* 239513 */   // Label 4555: @239513
     /* 239513 */   GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(239555), // Rule ID 3085 //
     /* 239518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 239526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 239535 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239542 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1690:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_H),
     /* 239545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239551 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239553 */     GIR_RootConstrainSelectedInstOperands,
     /* 239554 */     // GIR_Coverage, 3085,
     /* 239554 */     GIR_EraseRootFromParent_Done,
     /* 239555 */   // Label 4556: @239555
     /* 239555 */   GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(239597), // Rule ID 3087 //
     /* 239560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 239568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239584 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1690:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_S),
     /* 239587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239589 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239591 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239593 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239595 */     GIR_RootConstrainSelectedInstOperands,
     /* 239596 */     // GIR_Coverage, 3087,
     /* 239596 */     GIR_EraseRootFromParent_Done,
     /* 239597 */   // Label 4557: @239597
     /* 239597 */   GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(239639), // Rule ID 3089 //
     /* 239602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 239610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 239616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 239619 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 239622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239626 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1690:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 239626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_D),
     /* 239629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239631 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239633 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239635 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239637 */     GIR_RootConstrainSelectedInstOperands,
     /* 239638 */     // GIR_Coverage, 3089,
     /* 239638 */     GIR_EraseRootFromParent_Done,
     /* 239639 */   // Label 4558: @239639
     /* 239639 */   GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(239681), // Rule ID 3091 //
     /* 239644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239647 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 239652 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 239661 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 239664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239668 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1691:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 239668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_H),
     /* 239671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239677 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239679 */     GIR_RootConstrainSelectedInstOperands,
     /* 239680 */     // GIR_Coverage, 3091,
     /* 239680 */     GIR_EraseRootFromParent_Done,
     /* 239681 */   // Label 4559: @239681
     /* 239681 */   GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(239723), // Rule ID 3092 //
     /* 239686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 239694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 239703 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239710 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1691:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_S),
     /* 239713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239717 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239719 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239721 */     GIR_RootConstrainSelectedInstOperands,
     /* 239722 */     // GIR_Coverage, 3092,
     /* 239722 */     GIR_EraseRootFromParent_Done,
     /* 239723 */   // Label 4560: @239723
     /* 239723 */   GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(239765), // Rule ID 3093 //
     /* 239728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 239736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 239742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239745 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239752 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1691:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_D),
     /* 239755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239759 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239761 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239763 */     GIR_RootConstrainSelectedInstOperands,
     /* 239764 */     // GIR_Coverage, 3093,
     /* 239764 */     GIR_EraseRootFromParent_Done,
     /* 239765 */   // Label 4561: @239765
     /* 239765 */   GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(239807), // Rule ID 3094 //
     /* 239770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
     /* 239778 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239781 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239784 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239787 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239794 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1254:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_S),
     /* 239797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239803 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239805 */     GIR_RootConstrainSelectedInstOperands,
     /* 239806 */     // GIR_Coverage, 3094,
     /* 239806 */     GIR_EraseRootFromParent_Done,
     /* 239807 */   // Label 4562: @239807
     /* 239807 */   GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(239849), // Rule ID 3095 //
     /* 239812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
     /* 239820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 239823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 239826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 239829 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 239832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239836 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1254:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 239836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_D),
     /* 239839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 239841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239843 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239845 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239847 */     GIR_RootConstrainSelectedInstOperands,
     /* 239848 */     // GIR_Coverage, 3095,
     /* 239848 */     GIR_EraseRootFromParent_Done,
     /* 239849 */   // Label 4563: @239849
     /* 239849 */   GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(239891), // Rule ID 3105 //
     /* 239854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 239862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 239865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 239868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 239871 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 239874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239878 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1261:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 239878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_B),
     /* 239881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239887 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239889 */     GIR_RootConstrainSelectedInstOperands,
     /* 239890 */     // GIR_Coverage, 3105,
     /* 239890 */     GIR_EraseRootFromParent_Done,
     /* 239891 */   // Label 4564: @239891
     /* 239891 */   GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(239933), // Rule ID 3106 //
     /* 239896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 239904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 239913 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 239916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239920 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1261:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 239920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_H),
     /* 239923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239929 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239931 */     GIR_RootConstrainSelectedInstOperands,
     /* 239932 */     // GIR_Coverage, 3106,
     /* 239932 */     GIR_EraseRootFromParent_Done,
     /* 239933 */   // Label 4565: @239933
     /* 239933 */   GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(239975), // Rule ID 3107 //
     /* 239938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 239941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 239946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 239949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 239952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 239955 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 239958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239962 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1261:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 239962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_S),
     /* 239965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 239967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 239969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 239971 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 239973 */     GIR_RootConstrainSelectedInstOperands,
     /* 239974 */     // GIR_Coverage, 3107,
     /* 239974 */     GIR_EraseRootFromParent_Done,
     /* 239975 */   // Label 4566: @239975
     /* 239975 */   GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(240017), // Rule ID 3124 //
     /* 239980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 239988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 239991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 239994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 239997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 240000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240004 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1320:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CLS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 240004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B),
     /* 240007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 240009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 240011 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 240013 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 240015 */     GIR_RootConstrainSelectedInstOperands,
     /* 240016 */     // GIR_Coverage, 3124,
     /* 240016 */     GIR_EraseRootFromParent_Done,
     /* 240017 */   // Label 4567: @240017
     /* 240017 */   GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(240059), // Rule ID 3125 //
     /* 240022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 240030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 240036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 240039 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 240042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240046 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1320:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CLS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 240046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H),
     /* 240049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 240051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 240053 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 240055 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 240057 */     GIR_RootConstrainSelectedInstOperands,
     /* 240058 */     // GIR_Coverage, 3125,
     /* 240058 */     GIR_EraseRootFromParent_Done,
     /* 240059 */   // Label 4568: @240059
     /* 240059 */   GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(240101), // Rule ID 3126 //
     /* 240064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240067 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 240072 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240075 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240078 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 240081 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 240084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240088 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1320:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CLS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 240088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S),
     /* 240091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 240093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 240095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 240097 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 240099 */     GIR_RootConstrainSelectedInstOperands,
     /* 240100 */     // GIR_Coverage, 3126,
     /* 240100 */     GIR_EraseRootFromParent_Done,
     /* 240101 */   // Label 4569: @240101
     /* 240101 */   GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(240143), // Rule ID 3127 //
     /* 240106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 240114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 240117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 240120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 240123 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240130 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1320:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CLS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 240130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D),
     /* 240133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 240135 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 240137 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 240139 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 240141 */     GIR_RootConstrainSelectedInstOperands,
     /* 240142 */     // GIR_Coverage, 3127,
     /* 240142 */     GIR_EraseRootFromParent_Done,
     /* 240143 */   // Label 4570: @240143
     /* 240143 */   GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(240185), // Rule ID 3162 //
     /* 240148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 240151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 240156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 240159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 240162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 240165 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 240168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240172 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1361:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 240172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 240175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240181 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240183 */     GIR_RootConstrainSelectedInstOperands,
     /* 240184 */     // GIR_Coverage, 3162,
     /* 240184 */     GIR_EraseRootFromParent_Done,
     /* 240185 */   // Label 4571: @240185
     /* 240185 */   GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(240227), // Rule ID 3164 //
     /* 240190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 240193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 240198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 240204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 240210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240214 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1361:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 240214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 240217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240223 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240225 */     GIR_RootConstrainSelectedInstOperands,
     /* 240226 */     // GIR_Coverage, 3164,
     /* 240226 */     GIR_EraseRootFromParent_Done,
     /* 240227 */   // Label 4572: @240227
     /* 240227 */   GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(240269), // Rule ID 3166 //
     /* 240232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 240235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 240240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240249 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 240252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240256 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1361:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 240256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 240259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240265 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240267 */     GIR_RootConstrainSelectedInstOperands,
     /* 240268 */     // GIR_Coverage, 3166,
     /* 240268 */     GIR_EraseRootFromParent_Done,
     /* 240269 */   // Label 4573: @240269
     /* 240269 */   GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(240311), // Rule ID 3168 //
     /* 240274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 240277 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 240282 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 240285 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 240288 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 240291 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240298 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1361:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 240301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240307 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240309 */     GIR_RootConstrainSelectedInstOperands,
     /* 240310 */     // GIR_Coverage, 3168,
     /* 240310 */     GIR_EraseRootFromParent_Done,
     /* 240311 */   // Label 4574: @240311
     /* 240311 */   GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(240356), // Rule ID 3211 //
     /* 240316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 240324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 240327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 240330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 240333 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240340 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1325:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_B),
     /* 240343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240349 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240351 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240354 */     GIR_RootConstrainSelectedInstOperands,
     /* 240355 */     // GIR_Coverage, 3211,
     /* 240355 */     GIR_EraseRootFromParent_Done,
     /* 240356 */   // Label 4575: @240356
     /* 240356 */   GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(240401), // Rule ID 3212 //
     /* 240361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 240369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 240372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 240375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240385 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1325:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_H),
     /* 240388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240392 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240394 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240396 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240399 */     GIR_RootConstrainSelectedInstOperands,
     /* 240400 */     // GIR_Coverage, 3212,
     /* 240400 */     GIR_EraseRootFromParent_Done,
     /* 240401 */   // Label 4576: @240401
     /* 240401 */   GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(240446), // Rule ID 3213 //
     /* 240406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 240414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 240417 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 240420 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240423 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240430 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1325:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_S),
     /* 240433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240437 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240439 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240441 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240444 */     GIR_RootConstrainSelectedInstOperands,
     /* 240445 */     // GIR_Coverage, 3213,
     /* 240445 */     GIR_EraseRootFromParent_Done,
     /* 240446 */   // Label 4577: @240446
     /* 240446 */   GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(240491), // Rule ID 3214 //
     /* 240451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 240459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 240462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 240465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 240468 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240475 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1327:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_B),
     /* 240478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240484 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240486 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240489 */     GIR_RootConstrainSelectedInstOperands,
     /* 240490 */     // GIR_Coverage, 3214,
     /* 240490 */     GIR_EraseRootFromParent_Done,
     /* 240491 */   // Label 4578: @240491
     /* 240491 */   GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(240536), // Rule ID 3215 //
     /* 240496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240499 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 240504 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 240507 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 240510 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240513 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240520 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1327:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_H),
     /* 240523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240525 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240527 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240529 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240531 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240534 */     GIR_RootConstrainSelectedInstOperands,
     /* 240535 */     // GIR_Coverage, 3215,
     /* 240535 */     GIR_EraseRootFromParent_Done,
     /* 240536 */   // Label 4579: @240536
     /* 240536 */   GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(240581), // Rule ID 3216 //
     /* 240541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 240549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 240552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 240555 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240558 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240565 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1327:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_S),
     /* 240568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240574 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240576 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 240579 */     GIR_RootConstrainSelectedInstOperands,
     /* 240580 */     // GIR_Coverage, 3216,
     /* 240580 */     GIR_EraseRootFromParent_Done,
     /* 240581 */   // Label 4580: @240581
     /* 240581 */   GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(240623), // Rule ID 3271 //
     /* 240586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 240594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 240597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 240600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240603 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 240606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240610 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1371:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FACGE_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 240610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_H),
     /* 240613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240615 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240617 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240619 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240621 */     GIR_RootConstrainSelectedInstOperands,
     /* 240622 */     // GIR_Coverage, 3271,
     /* 240622 */     GIR_EraseRootFromParent_Done,
     /* 240623 */   // Label 4581: @240623
     /* 240623 */   GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(240665), // Rule ID 3272 //
     /* 240628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 240636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 240639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 240642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240645 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 240648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240652 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1371:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FACGE_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 240652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_S),
     /* 240655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240661 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240663 */     GIR_RootConstrainSelectedInstOperands,
     /* 240664 */     // GIR_Coverage, 3272,
     /* 240664 */     GIR_EraseRootFromParent_Done,
     /* 240665 */   // Label 4582: @240665
     /* 240665 */   GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(240707), // Rule ID 3273 //
     /* 240670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 240678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 240681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 240684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 240687 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 240694 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1371:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FACGE_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 240694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_D),
     /* 240697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 240699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240701 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240703 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240705 */     GIR_RootConstrainSelectedInstOperands,
     /* 240706 */     // GIR_Coverage, 3273,
     /* 240706 */     GIR_EraseRootFromParent_Done,
     /* 240707 */   // Label 4583: @240707
     /* 240707 */   GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(240749), // Rule ID 3325 //
     /* 240712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 240720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 240723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 240726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 240729 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 240732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240736 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1277:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (ASR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 240736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_B),
     /* 240739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240743 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240745 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240747 */     GIR_RootConstrainSelectedInstOperands,
     /* 240748 */     // GIR_Coverage, 3325,
     /* 240748 */     GIR_EraseRootFromParent_Done,
     /* 240749 */   // Label 4584: @240749
     /* 240749 */   GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(240791), // Rule ID 3326 //
     /* 240754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 240762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 240768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240771 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 240774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240778 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1277:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ASR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 240778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_H),
     /* 240781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240787 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240789 */     GIR_RootConstrainSelectedInstOperands,
     /* 240790 */     // GIR_Coverage, 3326,
     /* 240790 */     GIR_EraseRootFromParent_Done,
     /* 240791 */   // Label 4585: @240791
     /* 240791 */   GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(240833), // Rule ID 3327 //
     /* 240796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 240804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 240810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240813 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 240816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240820 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1277:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ASR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 240820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_S),
     /* 240823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240825 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240827 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240829 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240831 */     GIR_RootConstrainSelectedInstOperands,
     /* 240832 */     // GIR_Coverage, 3327,
     /* 240832 */     GIR_EraseRootFromParent_Done,
     /* 240833 */   // Label 4586: @240833
     /* 240833 */   GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(240875), // Rule ID 3328 //
     /* 240838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 240846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 240849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 240852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 240855 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240862 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1277:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_D),
     /* 240865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240871 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240873 */     GIR_RootConstrainSelectedInstOperands,
     /* 240874 */     // GIR_Coverage, 3328,
     /* 240874 */     GIR_EraseRootFromParent_Done,
     /* 240875 */   // Label 4587: @240875
     /* 240875 */   GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(240917), // Rule ID 3337 //
     /* 240880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 240888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 240891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 240894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 240897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240904 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1279:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_B),
     /* 240907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240913 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240915 */     GIR_RootConstrainSelectedInstOperands,
     /* 240916 */     // GIR_Coverage, 3337,
     /* 240916 */     GIR_EraseRootFromParent_Done,
     /* 240917 */   // Label 4588: @240917
     /* 240917 */   GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(240959), // Rule ID 3338 //
     /* 240922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 240930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 240936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 240939 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240946 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1279:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_H),
     /* 240949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240951 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240955 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240957 */     GIR_RootConstrainSelectedInstOperands,
     /* 240958 */     // GIR_Coverage, 3338,
     /* 240958 */     GIR_EraseRootFromParent_Done,
     /* 240959 */   // Label 4589: @240959
     /* 240959 */   GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(241001), // Rule ID 3339 //
     /* 240964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 240972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 240978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 240981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 240984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240988 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1279:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 240988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_S),
     /* 240991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 240995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 240997 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 240999 */     GIR_RootConstrainSelectedInstOperands,
     /* 241000 */     // GIR_Coverage, 3339,
     /* 241000 */     GIR_EraseRootFromParent_Done,
     /* 241001 */   // Label 4590: @241001
     /* 241001 */   GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(241043), // Rule ID 3378 //
     /* 241006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 241017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 241023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 241026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241030 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1316:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (CLASTA_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 241030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_B),
     /* 241033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241039 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241041 */     GIR_RootConstrainSelectedInstOperands,
     /* 241042 */     // GIR_Coverage, 3378,
     /* 241042 */     GIR_EraseRootFromParent_Done,
     /* 241043 */   // Label 4591: @241043
     /* 241043 */   GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(241085), // Rule ID 3379 //
     /* 241048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 241059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 241062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241072 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1316:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (CLASTA_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 241072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
     /* 241075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241079 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241081 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241083 */     GIR_RootConstrainSelectedInstOperands,
     /* 241084 */     // GIR_Coverage, 3379,
     /* 241084 */     GIR_EraseRootFromParent_Done,
     /* 241085 */   // Label 4592: @241085
     /* 241085 */   GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(241127), // Rule ID 3380 //
     /* 241090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 241104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 241107 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 241110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241114 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1316:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (CLASTA_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 241114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
     /* 241117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241121 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241123 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241125 */     GIR_RootConstrainSelectedInstOperands,
     /* 241126 */     // GIR_Coverage, 3380,
     /* 241126 */     GIR_EraseRootFromParent_Done,
     /* 241127 */   // Label 4593: @241127
     /* 241127 */   GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(241169), // Rule ID 3381 //
     /* 241132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 241146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 241149 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 241152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241156 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1316:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CLASTA_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 241156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
     /* 241159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241165 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241167 */     GIR_RootConstrainSelectedInstOperands,
     /* 241168 */     // GIR_Coverage, 3381,
     /* 241168 */     GIR_EraseRootFromParent_Done,
     /* 241169 */   // Label 4594: @241169
     /* 241169 */   GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(241211), // Rule ID 3382 //
     /* 241174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 241185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 241188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241191 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241198 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1316:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (CLASTA_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 241198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
     /* 241201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241207 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241209 */     GIR_RootConstrainSelectedInstOperands,
     /* 241210 */     // GIR_Coverage, 3382,
     /* 241210 */     GIR_EraseRootFromParent_Done,
     /* 241211 */   // Label 4595: @241211
     /* 241211 */   GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(241253), // Rule ID 3383 //
     /* 241216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 241230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 241233 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 241236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241240 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1316:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (CLASTA_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 241240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
     /* 241243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241247 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241249 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241251 */     GIR_RootConstrainSelectedInstOperands,
     /* 241252 */     // GIR_Coverage, 3383,
     /* 241252 */     GIR_EraseRootFromParent_Done,
     /* 241253 */   // Label 4596: @241253
     /* 241253 */   GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(241295), // Rule ID 3384 //
     /* 241258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 241266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 241272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 241275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 241278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241282 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1316:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (CLASTA_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 241282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
     /* 241285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241291 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241293 */     GIR_RootConstrainSelectedInstOperands,
     /* 241294 */     // GIR_Coverage, 3384,
     /* 241294 */     GIR_EraseRootFromParent_Done,
     /* 241295 */   // Label 4597: @241295
     /* 241295 */   GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(241337), // Rule ID 3470 //
     /* 241300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpa_z),
     /* 241308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 241311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 241317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 241320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 241324 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1308:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKPA_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 241324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPA_PPzPP),
     /* 241327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 241329 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241331 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241333 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241335 */     GIR_RootConstrainSelectedInstOperands,
     /* 241336 */     // GIR_Coverage, 3470,
     /* 241336 */     GIR_EraseRootFromParent_Done,
     /* 241337 */   // Label 4598: @241337
     /* 241337 */   GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(241379), // Rule ID 3471 //
     /* 241342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkn_z),
     /* 241350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 241353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 241359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 241362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 241366 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1307:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKN_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 241366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKN_PPzP),
     /* 241369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdm]
     /* 241371 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241375 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241377 */     GIR_RootConstrainSelectedInstOperands,
     /* 241378 */     // GIR_Coverage, 3471,
     /* 241378 */     GIR_EraseRootFromParent_Done,
     /* 241379 */   // Label 4599: @241379
     /* 241379 */   GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(241421), // Rule ID 3472 //
     /* 241384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka),
     /* 241392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 241395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 241401 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 241404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 241408 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1303:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKA_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 241408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPmP),
     /* 241411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 241413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241417 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241419 */     GIR_RootConstrainSelectedInstOperands,
     /* 241420 */     // GIR_Coverage, 3472,
     /* 241420 */     GIR_EraseRootFromParent_Done,
     /* 241421 */   // Label 4600: @241421
     /* 241421 */   GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(241466), // Rule ID 3474 //
     /* 241426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 241429 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
     /* 241434 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 241437 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241440 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 241443 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 241446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 241450 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1610:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (MATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 241450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_B),
     /* 241453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 241455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241457 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241459 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241461 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 241464 */     GIR_RootConstrainSelectedInstOperands,
     /* 241465 */     // GIR_Coverage, 3474,
     /* 241465 */     GIR_EraseRootFromParent_Done,
     /* 241466 */   // Label 4601: @241466
     /* 241466 */   GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(241511), // Rule ID 3475 //
     /* 241471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 241474 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
     /* 241479 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 241482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 241485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241488 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 241495 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1610:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (MATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 241495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_H),
     /* 241498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 241500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241502 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241504 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241506 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 241509 */     GIR_RootConstrainSelectedInstOperands,
     /* 241510 */     // GIR_Coverage, 3475,
     /* 241510 */     GIR_EraseRootFromParent_Done,
     /* 241511 */   // Label 4602: @241511
     /* 241511 */   GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(241553), // Rule ID 3476 //
     /* 241516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 241519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
     /* 241524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 241530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 241533 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 241536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241540 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1555:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (HISTCNT_ZPzZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 241540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_S),
     /* 241543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241549 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241551 */     GIR_RootConstrainSelectedInstOperands,
     /* 241552 */     // GIR_Coverage, 3476,
     /* 241552 */     GIR_EraseRootFromParent_Done,
     /* 241553 */   // Label 4603: @241553
     /* 241553 */   GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(241595), // Rule ID 3477 //
     /* 241558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 241561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
     /* 241566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 241572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 241575 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 241578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241582 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1555:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (HISTCNT_ZPzZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 241582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_D),
     /* 241585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241587 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241589 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241591 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241593 */     GIR_RootConstrainSelectedInstOperands,
     /* 241594 */     // GIR_Coverage, 3477,
     /* 241594 */     GIR_EraseRootFromParent_Done,
     /* 241595 */   // Label 4604: @241595
     /* 241595 */   GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(241637), // Rule ID 3481 //
     /* 241600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 241603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smmla),
     /* 241608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 241614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 241617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 241620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241624 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1761:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 241624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA_ZZZ),
     /* 241627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 241629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241631 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241633 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241635 */     GIR_RootConstrainSelectedInstOperands,
     /* 241636 */     // GIR_Coverage, 3481,
     /* 241636 */     GIR_EraseRootFromParent_Done,
     /* 241637 */   // Label 4605: @241637
     /* 241637 */   GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(241679), // Rule ID 3526 //
     /* 241642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 241645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 241650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 241653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 241656 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241659 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241666 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1384:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCLAMP_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 241666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_H),
     /* 241669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241673 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241675 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241677 */     GIR_RootConstrainSelectedInstOperands,
     /* 241678 */     // GIR_Coverage, 3526,
     /* 241678 */     GIR_EraseRootFromParent_Done,
     /* 241679 */   // Label 4606: @241679
     /* 241679 */   GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(241721), // Rule ID 3528 //
     /* 241684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 241687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 241692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 241698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 241701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 241704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241708 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1384:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCLAMP_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 241708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_S),
     /* 241711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241715 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241717 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241719 */     GIR_RootConstrainSelectedInstOperands,
     /* 241720 */     // GIR_Coverage, 3528,
     /* 241720 */     GIR_EraseRootFromParent_Done,
     /* 241721 */   // Label 4607: @241721
     /* 241721 */   GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(241763), // Rule ID 3530 //
     /* 241726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 241729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 241734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 241743 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 241746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241750 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1384:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCLAMP_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 241750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_D),
     /* 241753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241757 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241759 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241761 */     GIR_RootConstrainSelectedInstOperands,
     /* 241762 */     // GIR_Coverage, 3530,
     /* 241762 */     GIR_EraseRootFromParent_Done,
     /* 241763 */   // Label 4608: @241763
     /* 241763 */   GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(241805), // Rule ID 3532 //
     /* 241768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 241771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_x2),
     /* 241776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 241782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241785 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241792 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1722:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 241792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_HtoS),
     /* 241795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 241797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241799 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241801 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241803 */     GIR_RootConstrainSelectedInstOperands,
     /* 241804 */     // GIR_Coverage, 3532,
     /* 241804 */     GIR_EraseRootFromParent_Done,
     /* 241805 */   // Label 4609: @241805
     /* 241805 */   GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(241847), // Rule ID 3659 //
     /* 241810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 241813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 241818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 241821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 241824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 241827 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 241830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241834 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1706:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 241834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_B),
     /* 241837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241845 */     GIR_RootConstrainSelectedInstOperands,
     /* 241846 */     // GIR_Coverage, 3659,
     /* 241846 */     GIR_EraseRootFromParent_Done,
     /* 241847 */   // Label 4610: @241847
     /* 241847 */   GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(241889), // Rule ID 3661 //
     /* 241852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 241855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 241860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 241863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 241866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 241869 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 241872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241876 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1706:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 241876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_H),
     /* 241879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241881 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241883 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241885 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241887 */     GIR_RootConstrainSelectedInstOperands,
     /* 241888 */     // GIR_Coverage, 3661,
     /* 241888 */     GIR_EraseRootFromParent_Done,
     /* 241889 */   // Label 4611: @241889
     /* 241889 */   GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(241931), // Rule ID 3663 //
     /* 241894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 241897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 241902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 241905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 241908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 241911 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 241914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241918 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1706:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 241918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_S),
     /* 241921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241927 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241929 */     GIR_RootConstrainSelectedInstOperands,
     /* 241930 */     // GIR_Coverage, 3663,
     /* 241930 */     GIR_EraseRootFromParent_Done,
     /* 241931 */   // Label 4612: @241931
     /* 241931 */   GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(241973), // Rule ID 3665 //
     /* 241936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 241939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 241944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 241953 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 241956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241960 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1706:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 241960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_D),
     /* 241963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 241965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 241967 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 241969 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 241971 */     GIR_RootConstrainSelectedInstOperands,
     /* 241972 */     // GIR_Coverage, 3665,
     /* 241972 */     GIR_EraseRootFromParent_Done,
     /* 241973 */   // Label 4613: @241973
     /* 241973 */   GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(242015), // Rule ID 7586 //
     /* 241978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 241986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 241989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 241992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 241995 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 241998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242002 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1915:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 242002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_B),
     /* 242005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242011 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242013 */     GIR_RootConstrainSelectedInstOperands,
     /* 242014 */     // GIR_Coverage, 7586,
     /* 242014 */     GIR_EraseRootFromParent_Done,
     /* 242015 */   // Label 4614: @242015
     /* 242015 */   GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(242057), // Rule ID 7588 //
     /* 242020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 242028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242037 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242044 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1915:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 242044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_H),
     /* 242047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242049 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242051 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242053 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242055 */     GIR_RootConstrainSelectedInstOperands,
     /* 242056 */     // GIR_Coverage, 7588,
     /* 242056 */     GIR_EraseRootFromParent_Done,
     /* 242057 */   // Label 4615: @242057
     /* 242057 */   GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(242099), // Rule ID 7590 //
     /* 242062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 242070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242079 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242086 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1915:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_S),
     /* 242089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242091 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242093 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242095 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242097 */     GIR_RootConstrainSelectedInstOperands,
     /* 242098 */     // GIR_Coverage, 7590,
     /* 242098 */     GIR_EraseRootFromParent_Done,
     /* 242099 */   // Label 4616: @242099
     /* 242099 */   GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(242141), // Rule ID 7592 //
     /* 242104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 242112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242121 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242128 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1915:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_D),
     /* 242131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242135 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242137 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242139 */     GIR_RootConstrainSelectedInstOperands,
     /* 242140 */     // GIR_Coverage, 7592,
     /* 242140 */     GIR_EraseRootFromParent_Done,
     /* 242141 */   // Label 4617: @242141
     /* 242141 */   GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(242183), // Rule ID 7610 //
     /* 242146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 242154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 242157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 242160 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 242163 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 242166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242170 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1300:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (BIC_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 242170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_B),
     /* 242173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242177 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242179 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242181 */     GIR_RootConstrainSelectedInstOperands,
     /* 242182 */     // GIR_Coverage, 7610,
     /* 242182 */     GIR_EraseRootFromParent_Done,
     /* 242183 */   // Label 4618: @242183
     /* 242183 */   GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(242225), // Rule ID 7611 //
     /* 242188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 242196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242212 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1300:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (BIC_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 242212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_H),
     /* 242215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242219 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242221 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242223 */     GIR_RootConstrainSelectedInstOperands,
     /* 242224 */     // GIR_Coverage, 7611,
     /* 242224 */     GIR_EraseRootFromParent_Done,
     /* 242225 */   // Label 4619: @242225
     /* 242225 */   GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(242267), // Rule ID 7612 //
     /* 242230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 242238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242254 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1300:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (BIC_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_S),
     /* 242257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242261 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242263 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242265 */     GIR_RootConstrainSelectedInstOperands,
     /* 242266 */     // GIR_Coverage, 7612,
     /* 242266 */     GIR_EraseRootFromParent_Done,
     /* 242267 */   // Label 4620: @242267
     /* 242267 */   GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(242309), // Rule ID 7613 //
     /* 242272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 242280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242283 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242286 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242289 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242296 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1300:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (BIC_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_D),
     /* 242299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242303 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242305 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242307 */     GIR_RootConstrainSelectedInstOperands,
     /* 242308 */     // GIR_Coverage, 7613,
     /* 242308 */     GIR_EraseRootFromParent_Done,
     /* 242309 */   // Label 4621: @242309
     /* 242309 */   GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(242351), // Rule ID 7726 //
     /* 242314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 242322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 242325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 242328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 242331 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 242334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242338 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1762:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 242338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_B),
     /* 242341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242347 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242349 */     GIR_RootConstrainSelectedInstOperands,
     /* 242350 */     // GIR_Coverage, 7726,
     /* 242350 */     GIR_EraseRootFromParent_Done,
     /* 242351 */   // Label 4622: @242351
     /* 242351 */   GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(242393), // Rule ID 7727 //
     /* 242356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 242364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242373 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242380 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1762:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 242380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_H),
     /* 242383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242387 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242389 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242391 */     GIR_RootConstrainSelectedInstOperands,
     /* 242392 */     // GIR_Coverage, 7727,
     /* 242392 */     GIR_EraseRootFromParent_Done,
     /* 242393 */   // Label 4623: @242393
     /* 242393 */   GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(242435), // Rule ID 7728 //
     /* 242398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 242406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242415 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242422 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1762:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_S),
     /* 242425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242427 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242429 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242431 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242433 */     GIR_RootConstrainSelectedInstOperands,
     /* 242434 */     // GIR_Coverage, 7728,
     /* 242434 */     GIR_EraseRootFromParent_Done,
     /* 242435 */   // Label 4624: @242435
     /* 242435 */   GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(242477), // Rule ID 7729 //
     /* 242440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 242448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242464 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1762:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_D),
     /* 242467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242471 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242473 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242475 */     GIR_RootConstrainSelectedInstOperands,
     /* 242476 */     // GIR_Coverage, 7729,
     /* 242476 */     GIR_EraseRootFromParent_Done,
     /* 242477 */   // Label 4625: @242477
     /* 242477 */   GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(242519), // Rule ID 7730 //
     /* 242482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 242490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 242493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 242496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 242499 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 242502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242506 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2000:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 242506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_B),
     /* 242509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242513 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242515 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242517 */     GIR_RootConstrainSelectedInstOperands,
     /* 242518 */     // GIR_Coverage, 7730,
     /* 242518 */     GIR_EraseRootFromParent_Done,
     /* 242519 */   // Label 4626: @242519
     /* 242519 */   GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(242561), // Rule ID 7731 //
     /* 242524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 242532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242541 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242548 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2000:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 242548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_H),
     /* 242551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242557 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242559 */     GIR_RootConstrainSelectedInstOperands,
     /* 242560 */     // GIR_Coverage, 7731,
     /* 242560 */     GIR_EraseRootFromParent_Done,
     /* 242561 */   // Label 4627: @242561
     /* 242561 */   GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(242603), // Rule ID 7732 //
     /* 242566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 242574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242583 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242590 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2000:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_S),
     /* 242593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242597 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242599 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242601 */     GIR_RootConstrainSelectedInstOperands,
     /* 242602 */     // GIR_Coverage, 7732,
     /* 242602 */     GIR_EraseRootFromParent_Done,
     /* 242603 */   // Label 4628: @242603
     /* 242603 */   GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(242645), // Rule ID 7733 //
     /* 242608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 242616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242625 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242632 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2000:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_D),
     /* 242635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242641 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242643 */     GIR_RootConstrainSelectedInstOperands,
     /* 242644 */     // GIR_Coverage, 7733,
     /* 242644 */     GIR_EraseRootFromParent_Done,
     /* 242645 */   // Label 4629: @242645
     /* 242645 */   GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(242687), // Rule ID 7742 //
     /* 242650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
     /* 242658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242674 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1963:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_S),
     /* 242677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242681 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242683 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242685 */     GIR_RootConstrainSelectedInstOperands,
     /* 242686 */     // GIR_Coverage, 7742,
     /* 242686 */     GIR_EraseRootFromParent_Done,
     /* 242687 */   // Label 4630: @242687
     /* 242687 */   GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(242729), // Rule ID 7743 //
     /* 242692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
     /* 242700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242709 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242716 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1963:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_D),
     /* 242719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242723 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242725 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242727 */     GIR_RootConstrainSelectedInstOperands,
     /* 242728 */     // GIR_Coverage, 7743,
     /* 242728 */     GIR_EraseRootFromParent_Done,
     /* 242729 */   // Label 4631: @242729
     /* 242729 */   GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(242771), // Rule ID 7744 //
     /* 242734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
     /* 242742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242751 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242758 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1718:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_S),
     /* 242761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242767 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242769 */     GIR_RootConstrainSelectedInstOperands,
     /* 242770 */     // GIR_Coverage, 7744,
     /* 242770 */     GIR_EraseRootFromParent_Done,
     /* 242771 */   // Label 4632: @242771
     /* 242771 */   GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(242813), // Rule ID 7745 //
     /* 242776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
     /* 242784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242793 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242800 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1718:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_D),
     /* 242803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242809 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242811 */     GIR_RootConstrainSelectedInstOperands,
     /* 242812 */     // GIR_Coverage, 7745,
     /* 242812 */     GIR_EraseRootFromParent_Done,
     /* 242813 */   // Label 4633: @242813
     /* 242813 */   GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(242855), // Rule ID 7746 //
     /* 242818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
     /* 242826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 242832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 242835 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 242838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242842 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1965:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 242842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_S),
     /* 242845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242847 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242851 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242853 */     GIR_RootConstrainSelectedInstOperands,
     /* 242854 */     // GIR_Coverage, 7746,
     /* 242854 */     GIR_EraseRootFromParent_Done,
     /* 242855 */   // Label 4634: @242855
     /* 242855 */   GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(242897), // Rule ID 7747 //
     /* 242860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
     /* 242868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 242871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 242874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 242877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 242880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242884 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1965:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 242884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_D),
     /* 242887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 242891 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 242893 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 242895 */     GIR_RootConstrainSelectedInstOperands,
     /* 242896 */     // GIR_Coverage, 7747,
     /* 242896 */     GIR_EraseRootFromParent_Done,
     /* 242897 */   // Label 4635: @242897
     /* 242897 */   GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(242939), // Rule ID 7836 //
     /* 242902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 242910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 242913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 242916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 242919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 242922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242926 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1340:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CNOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 242926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B),
     /* 242929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 242931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 242933 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 242935 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 242937 */     GIR_RootConstrainSelectedInstOperands,
     /* 242938 */     // GIR_Coverage, 7836,
     /* 242938 */     GIR_EraseRootFromParent_Done,
     /* 242939 */   // Label 4636: @242939
     /* 242939 */   GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(242981), // Rule ID 7837 //
     /* 242944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 242952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 242958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 242961 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242968 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1340:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CNOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 242968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H),
     /* 242971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 242973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 242975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 242977 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 242979 */     GIR_RootConstrainSelectedInstOperands,
     /* 242980 */     // GIR_Coverage, 7837,
     /* 242980 */     GIR_EraseRootFromParent_Done,
     /* 242981 */   // Label 4637: @242981
     /* 242981 */   GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(243023), // Rule ID 7838 //
     /* 242986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 242994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 242997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 243000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 243003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243010 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1340:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CNOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 243010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S),
     /* 243013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243019 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243021 */     GIR_RootConstrainSelectedInstOperands,
     /* 243022 */     // GIR_Coverage, 7838,
     /* 243022 */     GIR_EraseRootFromParent_Done,
     /* 243023 */   // Label 4638: @243023
     /* 243023 */   GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(243065), // Rule ID 7839 //
     /* 243028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 243036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 243042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 243045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243052 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1340:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CNOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 243052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D),
     /* 243055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243061 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243063 */     GIR_RootConstrainSelectedInstOperands,
     /* 243064 */     // GIR_Coverage, 7839,
     /* 243064 */     GIR_EraseRootFromParent_Done,
     /* 243065 */   // Label 4639: @243065
     /* 243065 */   GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(243107), // Rule ID 7848 //
     /* 243070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 243078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 243081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 243084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 243087 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 243090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243094 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1626:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (NOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 243094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B),
     /* 243097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243099 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243101 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243103 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243105 */     GIR_RootConstrainSelectedInstOperands,
     /* 243106 */     // GIR_Coverage, 7848,
     /* 243106 */     GIR_EraseRootFromParent_Done,
     /* 243107 */   // Label 4640: @243107
     /* 243107 */   GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(243149), // Rule ID 7849 //
     /* 243112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 243120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 243126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 243129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243136 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1626:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (NOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 243136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H),
     /* 243139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243145 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243147 */     GIR_RootConstrainSelectedInstOperands,
     /* 243148 */     // GIR_Coverage, 7849,
     /* 243148 */     GIR_EraseRootFromParent_Done,
     /* 243149 */   // Label 4641: @243149
     /* 243149 */   GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(243191), // Rule ID 7850 //
     /* 243154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 243162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 243168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 243171 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243178 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1626:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (NOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 243178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S),
     /* 243181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243185 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243187 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243189 */     GIR_RootConstrainSelectedInstOperands,
     /* 243190 */     // GIR_Coverage, 7850,
     /* 243190 */     GIR_EraseRootFromParent_Done,
     /* 243191 */   // Label 4642: @243191
     /* 243191 */   GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(243233), // Rule ID 7851 //
     /* 243196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 243204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 243210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 243213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243220 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1626:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (NOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 243220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D),
     /* 243223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 243225 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 243227 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 243229 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 243231 */     GIR_RootConstrainSelectedInstOperands,
     /* 243232 */     // GIR_Coverage, 7851,
     /* 243232 */     GIR_EraseRootFromParent_Done,
     /* 243233 */   // Label 4643: @243233
     /* 243233 */   GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(243275), // Rule ID 7930 //
     /* 243238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 243246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 243249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 243252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 243255 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 243258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243262 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1693:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 243262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_B),
     /* 243265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243271 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243273 */     GIR_RootConstrainSelectedInstOperands,
     /* 243274 */     // GIR_Coverage, 7930,
     /* 243274 */     GIR_EraseRootFromParent_Done,
     /* 243275 */   // Label 4644: @243275
     /* 243275 */   GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(243317), // Rule ID 7931 //
     /* 243280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 243288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243304 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1693:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 243304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_H),
     /* 243307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243313 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243315 */     GIR_RootConstrainSelectedInstOperands,
     /* 243316 */     // GIR_Coverage, 7931,
     /* 243316 */     GIR_EraseRootFromParent_Done,
     /* 243317 */   // Label 4645: @243317
     /* 243317 */   GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(243359), // Rule ID 7932 //
     /* 243322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 243330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243339 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243346 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1693:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 243346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_S),
     /* 243349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243351 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243353 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243355 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243357 */     GIR_RootConstrainSelectedInstOperands,
     /* 243358 */     // GIR_Coverage, 7932,
     /* 243358 */     GIR_EraseRootFromParent_Done,
     /* 243359 */   // Label 4646: @243359
     /* 243359 */   GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(243401), // Rule ID 7933 //
     /* 243364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 243372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243381 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243388 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1693:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 243388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_D),
     /* 243391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243395 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243397 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243399 */     GIR_RootConstrainSelectedInstOperands,
     /* 243400 */     // GIR_Coverage, 7933,
     /* 243400 */     GIR_EraseRootFromParent_Done,
     /* 243401 */   // Label 4647: @243401
     /* 243401 */   GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(243443), // Rule ID 7934 //
     /* 243406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 243414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 243417 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 243420 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 243423 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 243426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243430 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1943:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 243430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_B),
     /* 243433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243437 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243439 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243441 */     GIR_RootConstrainSelectedInstOperands,
     /* 243442 */     // GIR_Coverage, 7934,
     /* 243442 */     GIR_EraseRootFromParent_Done,
     /* 243443 */   // Label 4648: @243443
     /* 243443 */   GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(243485), // Rule ID 7935 //
     /* 243448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 243456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243465 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243472 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1943:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 243472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_H),
     /* 243475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243481 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243483 */     GIR_RootConstrainSelectedInstOperands,
     /* 243484 */     // GIR_Coverage, 7935,
     /* 243484 */     GIR_EraseRootFromParent_Done,
     /* 243485 */   // Label 4649: @243485
     /* 243485 */   GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(243527), // Rule ID 7936 //
     /* 243490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 243498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243507 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243514 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1943:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 243514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_S),
     /* 243517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243519 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243521 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243523 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243525 */     GIR_RootConstrainSelectedInstOperands,
     /* 243526 */     // GIR_Coverage, 7936,
     /* 243526 */     GIR_EraseRootFromParent_Done,
     /* 243527 */   // Label 4650: @243527
     /* 243527 */   GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(243569), // Rule ID 7937 //
     /* 243532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 243540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243556 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1943:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 243556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_D),
     /* 243559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243563 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243565 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243567 */     GIR_RootConstrainSelectedInstOperands,
     /* 243568 */     // GIR_Coverage, 7937,
     /* 243568 */     GIR_EraseRootFromParent_Done,
     /* 243569 */   // Label 4651: @243569
     /* 243569 */   GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(243611), // Rule ID 8133 //
     /* 243574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243591 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243598 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1549:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FSUB_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 243598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_H),
     /* 243601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243607 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243609 */     GIR_RootConstrainSelectedInstOperands,
     /* 243610 */     // GIR_Coverage, 8133,
     /* 243610 */     GIR_EraseRootFromParent_Done,
     /* 243611 */   // Label 4652: @243611
     /* 243611 */   GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(243653), // Rule ID 8135 //
     /* 243616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243633 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243640 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1549:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FSUB_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 243640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_S),
     /* 243643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243647 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243649 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243651 */     GIR_RootConstrainSelectedInstOperands,
     /* 243652 */     // GIR_Coverage, 8135,
     /* 243652 */     GIR_EraseRootFromParent_Done,
     /* 243653 */   // Label 4653: @243653
     /* 243653 */   GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(243695), // Rule ID 8137 //
     /* 243658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243675 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243682 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1549:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FSUB_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 243682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_D),
     /* 243685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243689 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243691 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243693 */     GIR_RootConstrainSelectedInstOperands,
     /* 243694 */     // GIR_Coverage, 8137,
     /* 243694 */     GIR_EraseRootFromParent_Done,
     /* 243695 */   // Label 4654: @243695
     /* 243695 */   GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(243737), // Rule ID 8145 //
     /* 243700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 243708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243717 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243724 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1551:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FSUBR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 243724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_H),
     /* 243727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243731 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243733 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243735 */     GIR_RootConstrainSelectedInstOperands,
     /* 243736 */     // GIR_Coverage, 8145,
     /* 243736 */     GIR_EraseRootFromParent_Done,
     /* 243737 */   // Label 4655: @243737
     /* 243737 */   GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(243779), // Rule ID 8147 //
     /* 243742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 243750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243766 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1551:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FSUBR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 243766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_S),
     /* 243769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243775 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243777 */     GIR_RootConstrainSelectedInstOperands,
     /* 243778 */     // GIR_Coverage, 8147,
     /* 243778 */     GIR_EraseRootFromParent_Done,
     /* 243779 */   // Label 4656: @243779
     /* 243779 */   GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(243821), // Rule ID 8149 //
     /* 243784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 243792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243808 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1551:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FSUBR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 243808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_D),
     /* 243811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243815 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243817 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243819 */     GIR_RootConstrainSelectedInstOperands,
     /* 243820 */     // GIR_Coverage, 8149,
     /* 243820 */     GIR_EraseRootFromParent_Done,
     /* 243821 */   // Label 4657: @243821
     /* 243821 */   GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(243863), // Rule ID 8187 //
     /* 243826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 243834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243843 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243850 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1368:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FABD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 243850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_H),
     /* 243853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243857 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243859 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243861 */     GIR_RootConstrainSelectedInstOperands,
     /* 243862 */     // GIR_Coverage, 8187,
     /* 243862 */     GIR_EraseRootFromParent_Done,
     /* 243863 */   // Label 4658: @243863
     /* 243863 */   GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(243905), // Rule ID 8188 //
     /* 243868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 243876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243885 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243892 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1368:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FABD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 243892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_S),
     /* 243895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243899 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243901 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243903 */     GIR_RootConstrainSelectedInstOperands,
     /* 243904 */     // GIR_Coverage, 8188,
     /* 243904 */     GIR_EraseRootFromParent_Done,
     /* 243905 */   // Label 4659: @243905
     /* 243905 */   GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(243947), // Rule ID 8189 //
     /* 243910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 243918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243927 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243934 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1368:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FABD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 243934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_D),
     /* 243937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243943 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243945 */     GIR_RootConstrainSelectedInstOperands,
     /* 243946 */     // GIR_Coverage, 8189,
     /* 243946 */     GIR_EraseRootFromParent_Done,
     /* 243947 */   // Label 4660: @243947
     /* 243947 */   GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(243989), // Rule ID 8190 //
     /* 243952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 243960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243976 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1490:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMULX_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 243976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_H),
     /* 243979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 243983 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 243985 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 243987 */     GIR_RootConstrainSelectedInstOperands,
     /* 243988 */     // GIR_Coverage, 8190,
     /* 243988 */     GIR_EraseRootFromParent_Done,
     /* 243989 */   // Label 4661: @243989
     /* 243989 */   GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(244031), // Rule ID 8191 //
     /* 243994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 244002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244011 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244018 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1490:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMULX_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 244018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_S),
     /* 244021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244025 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244027 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244029 */     GIR_RootConstrainSelectedInstOperands,
     /* 244030 */     // GIR_Coverage, 8191,
     /* 244030 */     GIR_EraseRootFromParent_Done,
     /* 244031 */   // Label 4662: @244031
     /* 244031 */   GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(244073), // Rule ID 8192 //
     /* 244036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 244044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244053 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244060 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1490:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMULX_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 244060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_D),
     /* 244063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244069 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244071 */     GIR_RootConstrainSelectedInstOperands,
     /* 244072 */     // GIR_Coverage, 8192,
     /* 244072 */     GIR_EraseRootFromParent_Done,
     /* 244073 */   // Label 4663: @244073
     /* 244073 */   GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(244115), // Rule ID 8193 //
     /* 244078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 244086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244095 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244102 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1429:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDIVR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 244102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_H),
     /* 244105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244111 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244113 */     GIR_RootConstrainSelectedInstOperands,
     /* 244114 */     // GIR_Coverage, 8193,
     /* 244114 */     GIR_EraseRootFromParent_Done,
     /* 244115 */   // Label 4664: @244115
     /* 244115 */   GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(244157), // Rule ID 8194 //
     /* 244120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 244128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244144 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1429:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FDIVR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 244144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_S),
     /* 244147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244149 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244151 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244153 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244155 */     GIR_RootConstrainSelectedInstOperands,
     /* 244156 */     // GIR_Coverage, 8194,
     /* 244156 */     GIR_EraseRootFromParent_Done,
     /* 244157 */   // Label 4665: @244157
     /* 244157 */   GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(244199), // Rule ID 8195 //
     /* 244162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 244170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244179 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244186 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1429:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FDIVR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 244186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_D),
     /* 244189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244191 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244193 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244195 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244197 */     GIR_RootConstrainSelectedInstOperands,
     /* 244198 */     // GIR_Coverage, 8195,
     /* 244198 */     GIR_EraseRootFromParent_Done,
     /* 244199 */   // Label 4666: @244199
     /* 244199 */   GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(244241), // Rule ID 8196 //
     /* 244204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 244212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244228 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1427:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDIV_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 244228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_H),
     /* 244231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244237 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244239 */     GIR_RootConstrainSelectedInstOperands,
     /* 244240 */     // GIR_Coverage, 8196,
     /* 244240 */     GIR_EraseRootFromParent_Done,
     /* 244241 */   // Label 4667: @244241
     /* 244241 */   GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(244283), // Rule ID 8197 //
     /* 244246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 244254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244263 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244270 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1427:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FDIV_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 244270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_S),
     /* 244273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244279 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244281 */     GIR_RootConstrainSelectedInstOperands,
     /* 244282 */     // GIR_Coverage, 8197,
     /* 244282 */     GIR_EraseRootFromParent_Done,
     /* 244283 */   // Label 4668: @244283
     /* 244283 */   GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(244325), // Rule ID 8198 //
     /* 244288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 244296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244312 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1427:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FDIV_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 244312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_D),
     /* 244315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244321 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244323 */     GIR_RootConstrainSelectedInstOperands,
     /* 244324 */     // GIR_Coverage, 8198,
     /* 244324 */     GIR_EraseRootFromParent_Done,
     /* 244325 */   // Label 4669: @244325
     /* 244325 */   GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(244367), // Rule ID 8235 //
     /* 244330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244354 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1369:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 244354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 244357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244361 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244363 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244365 */     GIR_RootConstrainSelectedInstOperands,
     /* 244366 */     // GIR_Coverage, 8235,
     /* 244366 */     GIR_EraseRootFromParent_Done,
     /* 244367 */   // Label 4670: @244367
     /* 244367 */   GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(244409), // Rule ID 8237 //
     /* 244372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 244383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 244389 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 244392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244396 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1369:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 244396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 244399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244403 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244405 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244407 */     GIR_RootConstrainSelectedInstOperands,
     /* 244408 */     // GIR_Coverage, 8237,
     /* 244408 */     GIR_EraseRootFromParent_Done,
     /* 244409 */   // Label 4671: @244409
     /* 244409 */   GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(244451), // Rule ID 8239 //
     /* 244414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 244425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 244431 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 244434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244438 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1369:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 244438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 244441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244445 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244447 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244449 */     GIR_RootConstrainSelectedInstOperands,
     /* 244450 */     // GIR_Coverage, 8239,
     /* 244450 */     GIR_EraseRootFromParent_Done,
     /* 244451 */   // Label 4672: @244451
     /* 244451 */   GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(244493), // Rule ID 8241 //
     /* 244456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244473 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244480 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1369:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FABD_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 244480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
     /* 244483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244487 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244489 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244491 */     GIR_RootConstrainSelectedInstOperands,
     /* 244492 */     // GIR_Coverage, 8241,
     /* 244492 */     GIR_EraseRootFromParent_Done,
     /* 244493 */   // Label 4673: @244493
     /* 244493 */   GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(244535), // Rule ID 8243 //
     /* 244498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 244509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 244515 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 244518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244522 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1369:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FABD_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 244522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
     /* 244525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244527 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244529 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244531 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244533 */     GIR_RootConstrainSelectedInstOperands,
     /* 244534 */     // GIR_Coverage, 8243,
     /* 244534 */     GIR_EraseRootFromParent_Done,
     /* 244535 */   // Label 4674: @244535
     /* 244535 */   GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(244577), // Rule ID 8245 //
     /* 244540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 244548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244564 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1369:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FABD_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 244564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_D_UNDEF),
     /* 244567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244573 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244575 */     GIR_RootConstrainSelectedInstOperands,
     /* 244576 */     // GIR_Coverage, 8245,
     /* 244576 */     GIR_EraseRootFromParent_Done,
     /* 244577 */   // Label 4675: @244577
     /* 244577 */   GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(244619), // Rule ID 8247 //
     /* 244582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244599 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244606 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1491:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 244606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 244609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244613 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244615 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244617 */     GIR_RootConstrainSelectedInstOperands,
     /* 244618 */     // GIR_Coverage, 8247,
     /* 244618 */     GIR_EraseRootFromParent_Done,
     /* 244619 */   // Label 4676: @244619
     /* 244619 */   GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(244661), // Rule ID 8248 //
     /* 244624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 244635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 244641 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 244644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244648 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1491:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 244648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 244651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244655 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244657 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244659 */     GIR_RootConstrainSelectedInstOperands,
     /* 244660 */     // GIR_Coverage, 8248,
     /* 244660 */     GIR_EraseRootFromParent_Done,
     /* 244661 */   // Label 4677: @244661
     /* 244661 */   GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(244703), // Rule ID 8249 //
     /* 244666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 244677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 244683 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 244686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244690 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1491:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 244690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 244693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244697 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244699 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244701 */     GIR_RootConstrainSelectedInstOperands,
     /* 244702 */     // GIR_Coverage, 8249,
     /* 244702 */     GIR_EraseRootFromParent_Done,
     /* 244703 */   // Label 4678: @244703
     /* 244703 */   GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(244745), // Rule ID 8250 //
     /* 244708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244732 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1491:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMULX_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 244732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
     /* 244735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244739 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244741 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244743 */     GIR_RootConstrainSelectedInstOperands,
     /* 244744 */     // GIR_Coverage, 8250,
     /* 244744 */     GIR_EraseRootFromParent_Done,
     /* 244745 */   // Label 4679: @244745
     /* 244745 */   GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(244787), // Rule ID 8251 //
     /* 244750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 244761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 244767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 244770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244774 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1491:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FMULX_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 244774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
     /* 244777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244779 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244781 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244783 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244785 */     GIR_RootConstrainSelectedInstOperands,
     /* 244786 */     // GIR_Coverage, 8251,
     /* 244786 */     GIR_EraseRootFromParent_Done,
     /* 244787 */   // Label 4680: @244787
     /* 244787 */   GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(244829), // Rule ID 8252 //
     /* 244792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 244800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244809 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244816 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1491:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMULX_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 244816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_D_UNDEF),
     /* 244819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 244821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244823 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244825 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244827 */     GIR_RootConstrainSelectedInstOperands,
     /* 244828 */     // GIR_Coverage, 8252,
     /* 244828 */     GIR_EraseRootFromParent_Done,
     /* 244829 */   // Label 4681: @244829
     /* 244829 */   GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(244871), // Rule ID 8530 //
     /* 244834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpb_z),
     /* 244842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 244845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 244848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 244851 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 244854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 244858 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1309:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKPB_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 244858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPB_PPzPP),
     /* 244861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 244863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244865 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244867 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244869 */     GIR_RootConstrainSelectedInstOperands,
     /* 244870 */     // GIR_Coverage, 8530,
     /* 244870 */     GIR_EraseRootFromParent_Done,
     /* 244871 */   // Label 4682: @244871
     /* 244871 */   GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(244913), // Rule ID 8532 //
     /* 244876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb),
     /* 244884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 244887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 244890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 244893 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 244896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 244900 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1305:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKB_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 244900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPmP),
     /* 244903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 244905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244909 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244911 */     GIR_RootConstrainSelectedInstOperands,
     /* 244912 */     // GIR_Coverage, 8532,
     /* 244912 */     GIR_EraseRootFromParent_Done,
     /* 244913 */   // Label 4683: @244913
     /* 244913 */   GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(244955), // Rule ID 8533 //
     /* 244918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 244926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 244929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 244932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 244935 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 244938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 244942 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1302:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 244942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 244945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 244947 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244949 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244951 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244953 */     GIR_RootConstrainSelectedInstOperands,
     /* 244954 */     // GIR_Coverage, 8533,
     /* 244954 */     GIR_EraseRootFromParent_Done,
     /* 244955 */   // Label 4684: @244955
     /* 244955 */   GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(244997), // Rule ID 8534 //
     /* 244960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 244968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 244971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 244977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 244980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 244984 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1302:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 244984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 244987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 244989 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 244991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 244993 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 244995 */     GIR_RootConstrainSelectedInstOperands,
     /* 244996 */     // GIR_Coverage, 8534,
     /* 244996 */     GIR_EraseRootFromParent_Done,
     /* 244997 */   // Label 4685: @244997
     /* 244997 */   GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(245039), // Rule ID 8535 //
     /* 245002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 245010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 245013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 245019 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 245022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245026 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1302:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 245026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 245029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245031 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245033 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245035 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245037 */     GIR_RootConstrainSelectedInstOperands,
     /* 245038 */     // GIR_Coverage, 8535,
     /* 245038 */     GIR_EraseRootFromParent_Done,
     /* 245039 */   // Label 4686: @245039
     /* 245039 */   GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(245081), // Rule ID 8536 //
     /* 245044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 245052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 245055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 245061 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 245064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245068 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1302:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 245068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 245071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245075 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245077 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245079 */     GIR_RootConstrainSelectedInstOperands,
     /* 245080 */     // GIR_Coverage, 8536,
     /* 245080 */     GIR_EraseRootFromParent_Done,
     /* 245081 */   // Label 4687: @245081
     /* 245081 */   GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(245123), // Rule ID 8537 //
     /* 245086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 245094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 245097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 245100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 245103 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 245106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245110 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1302:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 245110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 245113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245117 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245119 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245121 */     GIR_RootConstrainSelectedInstOperands,
     /* 245122 */     // GIR_Coverage, 8537,
     /* 245122 */     GIR_EraseRootFromParent_Done,
     /* 245123 */   // Label 4688: @245123
     /* 245123 */   GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(245165), // Rule ID 8558 //
     /* 245128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 245136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 245139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 245142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 245145 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 245148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245152 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1360:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 245152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 245155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245157 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245159 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245161 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245163 */     GIR_RootConstrainSelectedInstOperands,
     /* 245164 */     // GIR_Coverage, 8558,
     /* 245164 */     GIR_EraseRootFromParent_Done,
     /* 245165 */   // Label 4689: @245165
     /* 245165 */   GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(245207), // Rule ID 8559 //
     /* 245170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 245178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 245181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 245187 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 245190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245194 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1360:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 245194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 245197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245199 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245201 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245203 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245205 */     GIR_RootConstrainSelectedInstOperands,
     /* 245206 */     // GIR_Coverage, 8559,
     /* 245206 */     GIR_EraseRootFromParent_Done,
     /* 245207 */   // Label 4690: @245207
     /* 245207 */   GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(245249), // Rule ID 8560 //
     /* 245212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 245220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 245223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 245229 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 245232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245236 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1360:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 245236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 245239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245243 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245245 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245247 */     GIR_RootConstrainSelectedInstOperands,
     /* 245248 */     // GIR_Coverage, 8560,
     /* 245248 */     GIR_EraseRootFromParent_Done,
     /* 245249 */   // Label 4691: @245249
     /* 245249 */   GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(245291), // Rule ID 8561 //
     /* 245254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 245262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 245265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 245271 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 245274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245278 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1360:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 245278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 245281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245283 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245285 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245287 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245289 */     GIR_RootConstrainSelectedInstOperands,
     /* 245290 */     // GIR_Coverage, 8561,
     /* 245290 */     GIR_EraseRootFromParent_Done,
     /* 245291 */   // Label 4692: @245291
     /* 245291 */   GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(245333), // Rule ID 8562 //
     /* 245296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 245304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 245307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 245310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 245313 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 245316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245320 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1360:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 245320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 245323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245327 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245329 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245331 */     GIR_RootConstrainSelectedInstOperands,
     /* 245332 */     // GIR_Coverage, 8562,
     /* 245332 */     GIR_EraseRootFromParent_Done,
     /* 245333 */   // Label 4693: @245333
     /* 245333 */   GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(245375), // Rule ID 8578 //
     /* 245338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 245346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 245349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 245352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 245355 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 245358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245362 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1631:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 245362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 245365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245369 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245371 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245373 */     GIR_RootConstrainSelectedInstOperands,
     /* 245374 */     // GIR_Coverage, 8578,
     /* 245374 */     GIR_EraseRootFromParent_Done,
     /* 245375 */   // Label 4694: @245375
     /* 245375 */   GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(245417), // Rule ID 8579 //
     /* 245380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 245388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 245391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 245397 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 245400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245404 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1631:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 245404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 245407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245409 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245411 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245413 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245415 */     GIR_RootConstrainSelectedInstOperands,
     /* 245416 */     // GIR_Coverage, 8579,
     /* 245416 */     GIR_EraseRootFromParent_Done,
     /* 245417 */   // Label 4695: @245417
     /* 245417 */   GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(245459), // Rule ID 8580 //
     /* 245422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 245430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 245433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 245439 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 245442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245446 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1631:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 245446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 245449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245453 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245455 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245457 */     GIR_RootConstrainSelectedInstOperands,
     /* 245458 */     // GIR_Coverage, 8580,
     /* 245458 */     GIR_EraseRootFromParent_Done,
     /* 245459 */   // Label 4696: @245459
     /* 245459 */   GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(245501), // Rule ID 8581 //
     /* 245464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 245472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 245475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245478 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 245481 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 245484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245488 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1631:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 245488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 245491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245497 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245499 */     GIR_RootConstrainSelectedInstOperands,
     /* 245500 */     // GIR_Coverage, 8581,
     /* 245500 */     GIR_EraseRootFromParent_Done,
     /* 245501 */   // Label 4697: @245501
     /* 245501 */   GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(245543), // Rule ID 8582 //
     /* 245506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 245514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 245517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 245520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 245523 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 245526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245530 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1631:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 245530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 245533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245535 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245537 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245539 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245541 */     GIR_RootConstrainSelectedInstOperands,
     /* 245542 */     // GIR_Coverage, 8582,
     /* 245542 */     GIR_EraseRootFromParent_Done,
     /* 245543 */   // Label 4698: @245543
     /* 245543 */   GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(245585), // Rule ID 8583 //
     /* 245548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 245556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 245559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 245562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 245565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 245568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245572 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1627:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 245572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 245575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245579 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245581 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245583 */     GIR_RootConstrainSelectedInstOperands,
     /* 245584 */     // GIR_Coverage, 8583,
     /* 245584 */     GIR_EraseRootFromParent_Done,
     /* 245585 */   // Label 4699: @245585
     /* 245585 */   GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(245627), // Rule ID 8584 //
     /* 245590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 245598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 245601 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 245607 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 245610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245614 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1627:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 245614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 245617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245621 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245623 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245625 */     GIR_RootConstrainSelectedInstOperands,
     /* 245626 */     // GIR_Coverage, 8584,
     /* 245626 */     GIR_EraseRootFromParent_Done,
     /* 245627 */   // Label 4700: @245627
     /* 245627 */   GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(245669), // Rule ID 8585 //
     /* 245632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 245640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 245643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 245649 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 245652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245656 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1627:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 245656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 245659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245663 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245665 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245667 */     GIR_RootConstrainSelectedInstOperands,
     /* 245668 */     // GIR_Coverage, 8585,
     /* 245668 */     GIR_EraseRootFromParent_Done,
     /* 245669 */   // Label 4701: @245669
     /* 245669 */   GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(245711), // Rule ID 8586 //
     /* 245674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 245682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 245685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 245691 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 245694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245698 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1627:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 245698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 245701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245707 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245709 */     GIR_RootConstrainSelectedInstOperands,
     /* 245710 */     // GIR_Coverage, 8586,
     /* 245710 */     GIR_EraseRootFromParent_Done,
     /* 245711 */   // Label 4702: @245711
     /* 245711 */   GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(245753), // Rule ID 8587 //
     /* 245716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 245724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 245727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 245730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 245733 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 245736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245740 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1627:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 245740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 245743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245747 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245749 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245751 */     GIR_RootConstrainSelectedInstOperands,
     /* 245752 */     // GIR_Coverage, 8587,
     /* 245752 */     GIR_EraseRootFromParent_Done,
     /* 245753 */   // Label 4703: @245753
     /* 245753 */   GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(245795), // Rule ID 8588 //
     /* 245758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 245766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 245769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 245772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 245775 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 245778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245782 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1625:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 245782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 245785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245789 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245791 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245793 */     GIR_RootConstrainSelectedInstOperands,
     /* 245794 */     // GIR_Coverage, 8588,
     /* 245794 */     GIR_EraseRootFromParent_Done,
     /* 245795 */   // Label 4704: @245795
     /* 245795 */   GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(245837), // Rule ID 8589 //
     /* 245800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 245808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 245811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 245817 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 245820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245824 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1625:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 245824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 245827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245831 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245833 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245835 */     GIR_RootConstrainSelectedInstOperands,
     /* 245836 */     // GIR_Coverage, 8589,
     /* 245836 */     GIR_EraseRootFromParent_Done,
     /* 245837 */   // Label 4705: @245837
     /* 245837 */   GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(245879), // Rule ID 8590 //
     /* 245842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245845 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 245850 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 245853 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245856 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 245859 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 245862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245866 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1625:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 245866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 245869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245871 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245873 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245875 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245877 */     GIR_RootConstrainSelectedInstOperands,
     /* 245878 */     // GIR_Coverage, 8590,
     /* 245878 */     GIR_EraseRootFromParent_Done,
     /* 245879 */   // Label 4706: @245879
     /* 245879 */   GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(245921), // Rule ID 8591 //
     /* 245884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 245892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 245895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 245901 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 245904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245908 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1625:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 245908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 245911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245913 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245915 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245917 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245919 */     GIR_RootConstrainSelectedInstOperands,
     /* 245920 */     // GIR_Coverage, 8591,
     /* 245920 */     GIR_EraseRootFromParent_Done,
     /* 245921 */   // Label 4707: @245921
     /* 245921 */   GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(245963), // Rule ID 8592 //
     /* 245926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 245934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 245937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 245940 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 245943 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 245946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245950 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1625:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 245950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 245953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 245959 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 245961 */     GIR_RootConstrainSelectedInstOperands,
     /* 245962 */     // GIR_Coverage, 8592,
     /* 245962 */     GIR_EraseRootFromParent_Done,
     /* 245963 */   // Label 4708: @245963
     /* 245963 */   GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(246005), // Rule ID 8593 //
     /* 245968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 245976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 245979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 245982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 245985 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 245988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 245992 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1621:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 245992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 245995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 245997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 245999 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246001 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246003 */     GIR_RootConstrainSelectedInstOperands,
     /* 246004 */     // GIR_Coverage, 8593,
     /* 246004 */     GIR_EraseRootFromParent_Done,
     /* 246005 */   // Label 4709: @246005
     /* 246005 */   GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(246047), // Rule ID 8594 //
     /* 246010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 246018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 246021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 246027 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 246030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 246034 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1621:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 246034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 246037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246041 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246043 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246045 */     GIR_RootConstrainSelectedInstOperands,
     /* 246046 */     // GIR_Coverage, 8594,
     /* 246046 */     GIR_EraseRootFromParent_Done,
     /* 246047 */   // Label 4710: @246047
     /* 246047 */   GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(246089), // Rule ID 8595 //
     /* 246052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 246060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 246063 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 246069 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 246072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 246076 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1621:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 246076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 246079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246083 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246085 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246087 */     GIR_RootConstrainSelectedInstOperands,
     /* 246088 */     // GIR_Coverage, 8595,
     /* 246088 */     GIR_EraseRootFromParent_Done,
     /* 246089 */   // Label 4711: @246089
     /* 246089 */   GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(246131), // Rule ID 8596 //
     /* 246094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 246102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 246105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246108 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 246111 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 246114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 246118 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1621:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 246118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 246121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246127 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246129 */     GIR_RootConstrainSelectedInstOperands,
     /* 246130 */     // GIR_Coverage, 8596,
     /* 246130 */     GIR_EraseRootFromParent_Done,
     /* 246131 */   // Label 4712: @246131
     /* 246131 */   GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(246173), // Rule ID 8597 //
     /* 246136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 246144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 246147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 246150 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 246153 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 246156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 246160 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1621:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 246160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 246163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246167 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246169 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246171 */     GIR_RootConstrainSelectedInstOperands,
     /* 246172 */     // GIR_Coverage, 8597,
     /* 246172 */     GIR_EraseRootFromParent_Done,
     /* 246173 */   // Label 4713: @246173
     /* 246173 */   GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(246215), // Rule ID 8605 //
     /* 246178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 246189 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 246192 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 246195 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 246198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246202 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1318:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (CLASTB_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 246202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_B),
     /* 246205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246209 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246211 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246213 */     GIR_RootConstrainSelectedInstOperands,
     /* 246214 */     // GIR_Coverage, 8605,
     /* 246214 */     GIR_EraseRootFromParent_Done,
     /* 246215 */   // Label 4714: @246215
     /* 246215 */   GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(246257), // Rule ID 8606 //
     /* 246220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246234 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246237 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 246240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246244 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1318:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (CLASTB_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 246244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
     /* 246247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246253 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246255 */     GIR_RootConstrainSelectedInstOperands,
     /* 246256 */     // GIR_Coverage, 8606,
     /* 246256 */     GIR_EraseRootFromParent_Done,
     /* 246257 */   // Label 4715: @246257
     /* 246257 */   GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(246299), // Rule ID 8607 //
     /* 246262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 246282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246286 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1318:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (CLASTB_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 246286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
     /* 246289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246291 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246293 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246295 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246297 */     GIR_RootConstrainSelectedInstOperands,
     /* 246298 */     // GIR_Coverage, 8607,
     /* 246298 */     GIR_EraseRootFromParent_Done,
     /* 246299 */   // Label 4716: @246299
     /* 246299 */   GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(246341), // Rule ID 8608 //
     /* 246304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246321 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246328 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1318:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CLASTB_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
     /* 246331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246335 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246337 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246339 */     GIR_RootConstrainSelectedInstOperands,
     /* 246340 */     // GIR_Coverage, 8608,
     /* 246340 */     GIR_EraseRootFromParent_Done,
     /* 246341 */   // Label 4717: @246341
     /* 246341 */   GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(246383), // Rule ID 8609 //
     /* 246346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246349 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246354 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246357 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246360 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246363 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 246366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246370 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1318:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (CLASTB_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 246370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
     /* 246373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246375 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246377 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246379 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246381 */     GIR_RootConstrainSelectedInstOperands,
     /* 246382 */     // GIR_Coverage, 8609,
     /* 246382 */     GIR_EraseRootFromParent_Done,
     /* 246383 */   // Label 4718: @246383
     /* 246383 */   GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(246425), // Rule ID 8610 //
     /* 246388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246405 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 246408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246412 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1318:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (CLASTB_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 246412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
     /* 246415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246421 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246423 */     GIR_RootConstrainSelectedInstOperands,
     /* 246424 */     // GIR_Coverage, 8610,
     /* 246424 */     GIR_EraseRootFromParent_Done,
     /* 246425 */   // Label 4719: @246425
     /* 246425 */   GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(246467), // Rule ID 8611 //
     /* 246430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 246438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246454 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1318:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (CLASTB_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 246454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
     /* 246457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246463 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246465 */     GIR_RootConstrainSelectedInstOperands,
     /* 246466 */     // GIR_Coverage, 8611,
     /* 246466 */     GIR_EraseRootFromParent_Done,
     /* 246467 */   // Label 4720: @246467
     /* 246467 */   GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(246512), // Rule ID 9307 //
     /* 246472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 246480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 246483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 246486 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 246489 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246496 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1339:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_B),
     /* 246499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246501 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246503 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246505 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246507 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246510 */     GIR_RootConstrainSelectedInstOperands,
     /* 246511 */     // GIR_Coverage, 9307,
     /* 246511 */     GIR_EraseRootFromParent_Done,
     /* 246512 */   // Label 4721: @246512
     /* 246512 */   GIM_Try, /*On fail goto*//*Label 4722*/ GIMT_Encode4(246557), // Rule ID 9308 //
     /* 246517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 246525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 246528 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246531 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246534 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246541 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1339:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_H),
     /* 246544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246548 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246550 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246552 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246555 */     GIR_RootConstrainSelectedInstOperands,
     /* 246556 */     // GIR_Coverage, 9308,
     /* 246556 */     GIR_EraseRootFromParent_Done,
     /* 246557 */   // Label 4722: @246557
     /* 246557 */   GIM_Try, /*On fail goto*//*Label 4723*/ GIMT_Encode4(246602), // Rule ID 9309 //
     /* 246562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 246570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 246573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246586 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1339:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_S),
     /* 246589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246595 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246597 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246600 */     GIR_RootConstrainSelectedInstOperands,
     /* 246601 */     // GIR_Coverage, 9309,
     /* 246601 */     GIR_EraseRootFromParent_Done,
     /* 246602 */   // Label 4723: @246602
     /* 246602 */   GIM_Try, /*On fail goto*//*Label 4724*/ GIMT_Encode4(246647), // Rule ID 9310 //
     /* 246607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 246615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 246618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 246621 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 246624 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246631 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1329:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_B),
     /* 246634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246640 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246642 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246645 */     GIR_RootConstrainSelectedInstOperands,
     /* 246646 */     // GIR_Coverage, 9310,
     /* 246646 */     GIR_EraseRootFromParent_Done,
     /* 246647 */   // Label 4724: @246647
     /* 246647 */   GIM_Try, /*On fail goto*//*Label 4725*/ GIMT_Encode4(246692), // Rule ID 9311 //
     /* 246652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 246660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 246663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246669 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246676 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1329:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_H),
     /* 246679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246683 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246685 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246687 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246690 */     GIR_RootConstrainSelectedInstOperands,
     /* 246691 */     // GIR_Coverage, 9311,
     /* 246691 */     GIR_EraseRootFromParent_Done,
     /* 246692 */   // Label 4725: @246692
     /* 246692 */   GIM_Try, /*On fail goto*//*Label 4726*/ GIMT_Encode4(246737), // Rule ID 9312 //
     /* 246697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 246705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 246708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246721 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1329:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_S),
     /* 246724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246730 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246732 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246735 */     GIR_RootConstrainSelectedInstOperands,
     /* 246736 */     // GIR_Coverage, 9312,
     /* 246736 */     GIR_EraseRootFromParent_Done,
     /* 246737 */   // Label 4726: @246737
     /* 246737 */   GIM_Try, /*On fail goto*//*Label 4727*/ GIMT_Encode4(246782), // Rule ID 9313 //
     /* 246742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 246750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 246753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 246756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 246759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246766 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1337:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_B),
     /* 246769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246775 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246777 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246780 */     GIR_RootConstrainSelectedInstOperands,
     /* 246781 */     // GIR_Coverage, 9313,
     /* 246781 */     GIR_EraseRootFromParent_Done,
     /* 246782 */   // Label 4727: @246782
     /* 246782 */   GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(246827), // Rule ID 9314 //
     /* 246787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 246795 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 246798 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246804 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246811 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1337:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_H),
     /* 246814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246820 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246822 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246825 */     GIR_RootConstrainSelectedInstOperands,
     /* 246826 */     // GIR_Coverage, 9314,
     /* 246826 */     GIR_EraseRootFromParent_Done,
     /* 246827 */   // Label 4728: @246827
     /* 246827 */   GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(246872), // Rule ID 9315 //
     /* 246832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 246840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 246843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246849 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246856 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1337:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_S),
     /* 246859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246863 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246865 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246867 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246870 */     GIR_RootConstrainSelectedInstOperands,
     /* 246871 */     // GIR_Coverage, 9315,
     /* 246871 */     GIR_EraseRootFromParent_Done,
     /* 246872 */   // Label 4729: @246872
     /* 246872 */   GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(246917), // Rule ID 9316 //
     /* 246877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 246885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 246888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 246891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 246894 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246901 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1334:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_B),
     /* 246904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246906 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246910 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246912 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246915 */     GIR_RootConstrainSelectedInstOperands,
     /* 246916 */     // GIR_Coverage, 9316,
     /* 246916 */     GIR_EraseRootFromParent_Done,
     /* 246917 */   // Label 4730: @246917
     /* 246917 */   GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(246962), // Rule ID 9317 //
     /* 246922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 246930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 246933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246939 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246946 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1334:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_H),
     /* 246949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246951 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246955 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 246957 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 246960 */     GIR_RootConstrainSelectedInstOperands,
     /* 246961 */     // GIR_Coverage, 9317,
     /* 246961 */     GIR_EraseRootFromParent_Done,
     /* 246962 */   // Label 4731: @246962
     /* 246962 */   GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(247007), // Rule ID 9318 //
     /* 246967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 246975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 246978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246991 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1334:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 246991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_S),
     /* 246994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 246996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247000 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247002 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247005 */     GIR_RootConstrainSelectedInstOperands,
     /* 247006 */     // GIR_Coverage, 9318,
     /* 247006 */     GIR_EraseRootFromParent_Done,
     /* 247007 */   // Label 4732: @247007
     /* 247007 */   GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(247052), // Rule ID 9319 //
     /* 247012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 247020 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 247023 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247026 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247029 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247036 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1333:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_B),
     /* 247039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247041 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247043 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247045 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247047 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247050 */     GIR_RootConstrainSelectedInstOperands,
     /* 247051 */     // GIR_Coverage, 9319,
     /* 247051 */     GIR_EraseRootFromParent_Done,
     /* 247052 */   // Label 4733: @247052
     /* 247052 */   GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(247097), // Rule ID 9320 //
     /* 247057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 247065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 247068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247074 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247081 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1333:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_H),
     /* 247084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247090 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247092 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247095 */     GIR_RootConstrainSelectedInstOperands,
     /* 247096 */     // GIR_Coverage, 9320,
     /* 247096 */     GIR_EraseRootFromParent_Done,
     /* 247097 */   // Label 4734: @247097
     /* 247097 */   GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(247142), // Rule ID 9321 //
     /* 247102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 247110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 247113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247119 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247126 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1333:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_S),
     /* 247129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247131 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247133 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247135 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247137 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247140 */     GIR_RootConstrainSelectedInstOperands,
     /* 247141 */     // GIR_Coverage, 9321,
     /* 247141 */     GIR_EraseRootFromParent_Done,
     /* 247142 */   // Label 4735: @247142
     /* 247142 */   GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(247187), // Rule ID 9322 //
     /* 247147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247150 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 247155 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 247158 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247161 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247164 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247171 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1331:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_B),
     /* 247174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247178 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247180 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247182 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247185 */     GIR_RootConstrainSelectedInstOperands,
     /* 247186 */     // GIR_Coverage, 9322,
     /* 247186 */     GIR_EraseRootFromParent_Done,
     /* 247187 */   // Label 4736: @247187
     /* 247187 */   GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(247232), // Rule ID 9323 //
     /* 247192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 247200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 247203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247216 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1331:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_H),
     /* 247219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247225 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247227 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247230 */     GIR_RootConstrainSelectedInstOperands,
     /* 247231 */     // GIR_Coverage, 9323,
     /* 247231 */     GIR_EraseRootFromParent_Done,
     /* 247232 */   // Label 4737: @247232
     /* 247232 */   GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(247277), // Rule ID 9324 //
     /* 247237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 247245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 247248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247251 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247254 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247261 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1331:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_S),
     /* 247264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247268 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247270 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247272 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247275 */     GIR_RootConstrainSelectedInstOperands,
     /* 247276 */     // GIR_Coverage, 9324,
     /* 247276 */     GIR_EraseRootFromParent_Done,
     /* 247277 */   // Label 4738: @247277
     /* 247277 */   GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(247322), // Rule ID 9325 //
     /* 247282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 247290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 247293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247299 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247306 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1335:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_B),
     /* 247309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247313 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247315 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247317 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247320 */     GIR_RootConstrainSelectedInstOperands,
     /* 247321 */     // GIR_Coverage, 9325,
     /* 247321 */     GIR_EraseRootFromParent_Done,
     /* 247322 */   // Label 4739: @247322
     /* 247322 */   GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(247367), // Rule ID 9326 //
     /* 247327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247330 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 247335 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 247338 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247341 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247344 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247351 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1335:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_H),
     /* 247354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247356 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247360 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247362 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247365 */     GIR_RootConstrainSelectedInstOperands,
     /* 247366 */     // GIR_Coverage, 9326,
     /* 247366 */     GIR_EraseRootFromParent_Done,
     /* 247367 */   // Label 4740: @247367
     /* 247367 */   GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(247412), // Rule ID 9327 //
     /* 247372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 247380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 247383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247389 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247396 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1335:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_S),
     /* 247399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247403 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247405 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247407 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247410 */     GIR_RootConstrainSelectedInstOperands,
     /* 247411 */     // GIR_Coverage, 9327,
     /* 247411 */     GIR_EraseRootFromParent_Done,
     /* 247412 */   // Label 4741: @247412
     /* 247412 */   GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(247457), // Rule ID 9328 //
     /* 247417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 247425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 247428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247434 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247441 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1336:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_B),
     /* 247444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247446 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247448 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247450 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247452 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247455 */     GIR_RootConstrainSelectedInstOperands,
     /* 247456 */     // GIR_Coverage, 9328,
     /* 247456 */     GIR_EraseRootFromParent_Done,
     /* 247457 */   // Label 4742: @247457
     /* 247457 */   GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(247502), // Rule ID 9329 //
     /* 247462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 247470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 247473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247479 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247486 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1336:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_H),
     /* 247489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247491 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247493 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247495 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247497 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247500 */     GIR_RootConstrainSelectedInstOperands,
     /* 247501 */     // GIR_Coverage, 9329,
     /* 247501 */     GIR_EraseRootFromParent_Done,
     /* 247502 */   // Label 4743: @247502
     /* 247502 */   GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(247547), // Rule ID 9330 //
     /* 247507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 247515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 247518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247531 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1336:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_S),
     /* 247534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247538 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247540 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247542 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 247545 */     GIR_RootConstrainSelectedInstOperands,
     /* 247546 */     // GIR_Coverage, 9330,
     /* 247546 */     GIR_EraseRootFromParent_Done,
     /* 247547 */   // Label 4744: @247547
     /* 247547 */   GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(247589), // Rule ID 9727 //
     /* 247552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 247560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 247563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247569 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 247572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247576 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1372:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FACGT_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 247576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_H),
     /* 247579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247581 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247583 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247585 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247587 */     GIR_RootConstrainSelectedInstOperands,
     /* 247588 */     // GIR_Coverage, 9727,
     /* 247588 */     GIR_EraseRootFromParent_Done,
     /* 247589 */   // Label 4745: @247589
     /* 247589 */   GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(247631), // Rule ID 9728 //
     /* 247594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 247602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 247605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247611 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 247614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247618 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1372:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FACGT_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 247618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_S),
     /* 247621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247627 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247629 */     GIR_RootConstrainSelectedInstOperands,
     /* 247630 */     // GIR_Coverage, 9728,
     /* 247630 */     GIR_EraseRootFromParent_Done,
     /* 247631 */   // Label 4746: @247631
     /* 247631 */   GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(247673), // Rule ID 9729 //
     /* 247636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 247644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 247647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 247650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247653 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 247660 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1372:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FACGT_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 247660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_D),
     /* 247663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 247665 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247669 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247671 */     GIR_RootConstrainSelectedInstOperands,
     /* 247672 */     // GIR_Coverage, 9729,
     /* 247672 */     GIR_EraseRootFromParent_Done,
     /* 247673 */   // Label 4747: @247673
     /* 247673 */   GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(247715), // Rule ID 10267 //
     /* 247678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 247686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247695 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 247698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247702 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1603:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (LSR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 247702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_B),
     /* 247705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247709 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247711 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247713 */     GIR_RootConstrainSelectedInstOperands,
     /* 247714 */     // GIR_Coverage, 10267,
     /* 247714 */     GIR_EraseRootFromParent_Done,
     /* 247715 */   // Label 4748: @247715
     /* 247715 */   GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(247757), // Rule ID 10268 //
     /* 247720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 247728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247737 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 247740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247744 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1603:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (LSR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 247744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_H),
     /* 247747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247751 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247753 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247755 */     GIR_RootConstrainSelectedInstOperands,
     /* 247756 */     // GIR_Coverage, 10268,
     /* 247756 */     GIR_EraseRootFromParent_Done,
     /* 247757 */   // Label 4749: @247757
     /* 247757 */   GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(247799), // Rule ID 10269 //
     /* 247762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 247770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247779 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 247782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247786 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1603:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (LSR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 247786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_S),
     /* 247789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247793 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247795 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247797 */     GIR_RootConstrainSelectedInstOperands,
     /* 247798 */     // GIR_Coverage, 10269,
     /* 247798 */     GIR_EraseRootFromParent_Done,
     /* 247799 */   // Label 4750: @247799
     /* 247799 */   GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(247841), // Rule ID 10270 //
     /* 247804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 247812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 247818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247821 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247828 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1603:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_D),
     /* 247831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247833 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247835 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247837 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247839 */     GIR_RootConstrainSelectedInstOperands,
     /* 247840 */     // GIR_Coverage, 10270,
     /* 247840 */     GIR_EraseRootFromParent_Done,
     /* 247841 */   // Label 4751: @247841
     /* 247841 */   GIM_Try, /*On fail goto*//*Label 4752*/ GIMT_Encode4(247883), // Rule ID 10271 //
     /* 247846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 247854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 247860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247863 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 247866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247870 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1600:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (LSL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 247870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_B),
     /* 247873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247875 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247877 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247879 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247881 */     GIR_RootConstrainSelectedInstOperands,
     /* 247882 */     // GIR_Coverage, 10271,
     /* 247882 */     GIR_EraseRootFromParent_Done,
     /* 247883 */   // Label 4752: @247883
     /* 247883 */   GIM_Try, /*On fail goto*//*Label 4753*/ GIMT_Encode4(247925), // Rule ID 10272 //
     /* 247888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 247896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 247902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 247908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247912 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1600:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (LSL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 247912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_H),
     /* 247915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247921 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247923 */     GIR_RootConstrainSelectedInstOperands,
     /* 247924 */     // GIR_Coverage, 10272,
     /* 247924 */     GIR_EraseRootFromParent_Done,
     /* 247925 */   // Label 4753: @247925
     /* 247925 */   GIM_Try, /*On fail goto*//*Label 4754*/ GIMT_Encode4(247967), // Rule ID 10273 //
     /* 247930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 247938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 247944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 247950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247954 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1600:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (LSL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 247954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_S),
     /* 247957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247963 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247965 */     GIR_RootConstrainSelectedInstOperands,
     /* 247966 */     // GIR_Coverage, 10273,
     /* 247966 */     GIR_EraseRootFromParent_Done,
     /* 247967 */   // Label 4754: @247967
     /* 247967 */   GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(248009), // Rule ID 10274 //
     /* 247972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 247980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 247986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247989 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 247992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247996 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1600:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 247996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_D),
     /* 247999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248003 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248005 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248007 */     GIR_RootConstrainSelectedInstOperands,
     /* 248008 */     // GIR_Coverage, 10274,
     /* 248008 */     GIR_EraseRootFromParent_Done,
     /* 248009 */   // Label 4755: @248009
     /* 248009 */   GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(248051), // Rule ID 10287 //
     /* 248014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 248022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 248025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 248028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248038 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1605:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_B),
     /* 248041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248047 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248049 */     GIR_RootConstrainSelectedInstOperands,
     /* 248050 */     // GIR_Coverage, 10287,
     /* 248050 */     GIR_EraseRootFromParent_Done,
     /* 248051 */   // Label 4756: @248051
     /* 248051 */   GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(248093), // Rule ID 10288 //
     /* 248056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 248064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 248070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248073 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248080 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1605:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_H),
     /* 248083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248089 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248091 */     GIR_RootConstrainSelectedInstOperands,
     /* 248092 */     // GIR_Coverage, 10288,
     /* 248092 */     GIR_EraseRootFromParent_Done,
     /* 248093 */   // Label 4757: @248093
     /* 248093 */   GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(248135), // Rule ID 10289 //
     /* 248098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 248106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 248112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248115 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248122 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1605:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_S),
     /* 248125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248127 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248129 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248131 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248133 */     GIR_RootConstrainSelectedInstOperands,
     /* 248134 */     // GIR_Coverage, 10289,
     /* 248134 */     GIR_EraseRootFromParent_Done,
     /* 248135 */   // Label 4758: @248135
     /* 248135 */   GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(248177), // Rule ID 10290 //
     /* 248140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 248148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 248151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 248154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248157 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248164 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1602:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_B),
     /* 248167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248175 */     GIR_RootConstrainSelectedInstOperands,
     /* 248176 */     // GIR_Coverage, 10290,
     /* 248176 */     GIR_EraseRootFromParent_Done,
     /* 248177 */   // Label 4759: @248177
     /* 248177 */   GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(248219), // Rule ID 10291 //
     /* 248182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 248190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 248196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248199 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248206 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1602:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_H),
     /* 248209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248211 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248213 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248215 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248217 */     GIR_RootConstrainSelectedInstOperands,
     /* 248218 */     // GIR_Coverage, 10291,
     /* 248218 */     GIR_EraseRootFromParent_Done,
     /* 248219 */   // Label 4760: @248219
     /* 248219 */   GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(248261), // Rule ID 10292 //
     /* 248224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 248232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 248238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248241 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248248 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1602:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_S),
     /* 248251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248257 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248259 */     GIR_RootConstrainSelectedInstOperands,
     /* 248260 */     // GIR_Coverage, 10292,
     /* 248260 */     GIR_EraseRootFromParent_Done,
     /* 248261 */   // Label 4761: @248261
     /* 248261 */   GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(248303), // Rule ID 10319 //
     /* 248266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f64),
     /* 248274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248283 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248290 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1397:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVT_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 248290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoH),
     /* 248293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248297 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248299 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248301 */     GIR_RootConstrainSelectedInstOperands,
     /* 248302 */     // GIR_Coverage, 10319,
     /* 248302 */     GIR_EraseRootFromParent_Done,
     /* 248303 */   // Label 4762: @248303
     /* 248303 */   GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(248345), // Rule ID 10323 //
     /* 248308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f16),
     /* 248316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248325 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 248328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248332 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1400:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVT_ZPmZ_HtoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 248332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoD),
     /* 248335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248337 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248339 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248341 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248343 */     GIR_RootConstrainSelectedInstOperands,
     /* 248344 */     // GIR_Coverage, 10323,
     /* 248344 */     GIR_EraseRootFromParent_Done,
     /* 248345 */   // Label 4763: @248345
     /* 248345 */   GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(248387), // Rule ID 10327 //
     /* 248350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f64),
     /* 248358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248367 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248374 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1399:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 248374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoS),
     /* 248377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248379 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248383 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248385 */     GIR_RootConstrainSelectedInstOperands,
     /* 248386 */     // GIR_Coverage, 10327,
     /* 248386 */     GIR_EraseRootFromParent_Done,
     /* 248387 */   // Label 4764: @248387
     /* 248387 */   GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(248429), // Rule ID 10331 //
     /* 248392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f32),
     /* 248400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248416 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1401:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 248416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoD),
     /* 248419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248423 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248425 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248427 */     GIR_RootConstrainSelectedInstOperands,
     /* 248428 */     // GIR_Coverage, 10331,
     /* 248428 */     GIR_EraseRootFromParent_Done,
     /* 248429 */   // Label 4765: @248429
     /* 248429 */   GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(248471), // Rule ID 10335 //
     /* 248434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f64i32),
     /* 248442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248451 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248458 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1713:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 248458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoD),
     /* 248461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248465 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248467 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248469 */     GIR_RootConstrainSelectedInstOperands,
     /* 248470 */     // GIR_Coverage, 10335,
     /* 248470 */     GIR_EraseRootFromParent_Done,
     /* 248471 */   // Label 4766: @248471
     /* 248471 */   GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(248513), // Rule ID 10336 //
     /* 248476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f64i32),
     /* 248484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248493 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248500 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1960:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 248500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoD),
     /* 248503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248507 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248509 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248511 */     GIR_RootConstrainSelectedInstOperands,
     /* 248512 */     // GIR_Coverage, 10336,
     /* 248512 */     GIR_EraseRootFromParent_Done,
     /* 248513 */   // Label 4767: @248513
     /* 248513 */   GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(248555), // Rule ID 10337 //
     /* 248518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i32),
     /* 248526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 248535 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248542 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1957:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 248542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoH),
     /* 248545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248551 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248553 */     GIR_RootConstrainSelectedInstOperands,
     /* 248554 */     // GIR_Coverage, 10337,
     /* 248554 */     GIR_EraseRootFromParent_Done,
     /* 248555 */   // Label 4768: @248555
     /* 248555 */   GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(248597), // Rule ID 10341 //
     /* 248560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f32i64),
     /* 248568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248584 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1712:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoS),
     /* 248587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248589 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248591 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248593 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248595 */     GIR_RootConstrainSelectedInstOperands,
     /* 248596 */     // GIR_Coverage, 10341,
     /* 248596 */     GIR_EraseRootFromParent_Done,
     /* 248597 */   // Label 4769: @248597
     /* 248597 */   GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(248639), // Rule ID 10345 //
     /* 248602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i32),
     /* 248610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 248619 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248626 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1710:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 248626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoH),
     /* 248629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248631 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248633 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248635 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248637 */     GIR_RootConstrainSelectedInstOperands,
     /* 248638 */     // GIR_Coverage, 10345,
     /* 248638 */     GIR_EraseRootFromParent_Done,
     /* 248639 */   // Label 4770: @248639
     /* 248639 */   GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(248681), // Rule ID 10349 //
     /* 248644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248647 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i64),
     /* 248652 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248661 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248668 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1711:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoH),
     /* 248671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248677 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248679 */     GIR_RootConstrainSelectedInstOperands,
     /* 248680 */     // GIR_Coverage, 10349,
     /* 248680 */     GIR_EraseRootFromParent_Done,
     /* 248681 */   // Label 4771: @248681
     /* 248681 */   GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(248723), // Rule ID 10353 //
     /* 248686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f32i64),
     /* 248694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248703 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248710 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1959:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoS),
     /* 248713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248717 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248719 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248721 */     GIR_RootConstrainSelectedInstOperands,
     /* 248722 */     // GIR_Coverage, 10353,
     /* 248722 */     GIR_EraseRootFromParent_Done,
     /* 248723 */   // Label 4772: @248723
     /* 248723 */   GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(248765), // Rule ID 10357 //
     /* 248728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i64),
     /* 248736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248745 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248752 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1958:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 248752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoH),
     /* 248755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248759 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248761 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248763 */     GIR_RootConstrainSelectedInstOperands,
     /* 248764 */     // GIR_Coverage, 10357,
     /* 248764 */     GIR_EraseRootFromParent_Done,
     /* 248765 */   // Label 4773: @248765
     /* 248765 */   GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(248807), // Rule ID 10367 //
     /* 248770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f64),
     /* 248778 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248781 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248784 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248787 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248794 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1415:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTZS_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 248794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_DtoS),
     /* 248797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248803 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248805 */     GIR_RootConstrainSelectedInstOperands,
     /* 248806 */     // GIR_Coverage, 10367,
     /* 248806 */     GIR_EraseRootFromParent_Done,
     /* 248807 */   // Label 4774: @248807
     /* 248807 */   GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(248849), // Rule ID 10368 //
     /* 248812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f64),
     /* 248820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248829 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 248832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248836 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1422:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTZU_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 248836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_DtoS),
     /* 248839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248843 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248845 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248847 */     GIR_RootConstrainSelectedInstOperands,
     /* 248848 */     // GIR_Coverage, 10368,
     /* 248848 */     GIR_EraseRootFromParent_Done,
     /* 248849 */   // Label 4775: @248849
     /* 248849 */   GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(248891), // Rule ID 10369 //
     /* 248854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f32),
     /* 248862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248871 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 248874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248878 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1417:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTZS_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 248878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_StoD),
     /* 248881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248887 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248889 */     GIR_RootConstrainSelectedInstOperands,
     /* 248890 */     // GIR_Coverage, 10369,
     /* 248890 */     GIR_EraseRootFromParent_Done,
     /* 248891 */   // Label 4776: @248891
     /* 248891 */   GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(248933), // Rule ID 10373 //
     /* 248896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f16),
     /* 248904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 248913 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 248916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248920 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1414:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZS_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 248920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoS),
     /* 248923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248929 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248931 */     GIR_RootConstrainSelectedInstOperands,
     /* 248932 */     // GIR_Coverage, 10373,
     /* 248932 */     GIR_EraseRootFromParent_Done,
     /* 248933 */   // Label 4777: @248933
     /* 248933 */   GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(248975), // Rule ID 10377 //
     /* 248938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f16),
     /* 248946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 248955 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 248958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248962 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1416:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZS_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 248962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoD),
     /* 248965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248971 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248973 */     GIR_RootConstrainSelectedInstOperands,
     /* 248974 */     // GIR_Coverage, 10377,
     /* 248974 */     GIR_EraseRootFromParent_Done,
     /* 248975 */   // Label 4778: @248975
     /* 248975 */   GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(249017), // Rule ID 10381 //
     /* 248980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 248983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f16),
     /* 248988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 248997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249004 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1421:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZU_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 249004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoS),
     /* 249007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 249009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249011 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249013 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249015 */     GIR_RootConstrainSelectedInstOperands,
     /* 249016 */     // GIR_Coverage, 10381,
     /* 249016 */     GIR_EraseRootFromParent_Done,
     /* 249017 */   // Label 4779: @249017
     /* 249017 */   GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(249059), // Rule ID 10385 //
     /* 249022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 249025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f16),
     /* 249030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 249039 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249046 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1423:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZU_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 249046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoD),
     /* 249049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 249051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249053 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249055 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249057 */     GIR_RootConstrainSelectedInstOperands,
     /* 249058 */     // GIR_Coverage, 10385,
     /* 249058 */     GIR_EraseRootFromParent_Done,
     /* 249059 */   // Label 4780: @249059
     /* 249059 */   GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(249101), // Rule ID 10389 //
     /* 249064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 249067 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f32),
     /* 249072 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249075 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249078 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 249081 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249088 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1424:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTZU_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 249088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_StoD),
     /* 249091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 249093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249097 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249099 */     GIR_RootConstrainSelectedInstOperands,
     /* 249100 */     // GIR_Coverage, 10389,
     /* 249100 */     GIR_EraseRootFromParent_Done,
     /* 249101 */   // Label 4781: @249101
     /* 249101 */   GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(249143), // Rule ID 11388 //
     /* 249106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 249109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ummla),
     /* 249114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249123 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249130 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1999:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA_ZZZ),
     /* 249133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249135 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249137 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249139 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249141 */     GIR_RootConstrainSelectedInstOperands,
     /* 249142 */     // GIR_Coverage, 11388,
     /* 249142 */     GIR_EraseRootFromParent_Done,
     /* 249143 */   // Label 4782: @249143
     /* 249143 */   GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(249185), // Rule ID 11389 //
     /* 249148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 249151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usmmla),
     /* 249156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249165 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249172 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2070:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (USMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA_ZZZ),
     /* 249175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249181 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249183 */     GIR_RootConstrainSelectedInstOperands,
     /* 249184 */     // GIR_Coverage, 11389,
     /* 249184 */     GIR_EraseRootFromParent_Done,
     /* 249185 */   // Label 4783: @249185
     /* 249185 */   GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(249227), // Rule ID 11391 //
     /* 249190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP32_HasSVE),
     /* 249193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
     /* 249198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249214 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1485:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMMLA_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 249214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_S),
     /* 249217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249223 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249225 */     GIR_RootConstrainSelectedInstOperands,
     /* 249226 */     // GIR_Coverage, 11391,
     /* 249226 */     GIR_EraseRootFromParent_Done,
     /* 249227 */   // Label 4784: @249227
     /* 249227 */   GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(249269), // Rule ID 11392 //
     /* 249232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE),
     /* 249235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
     /* 249240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249249 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 249252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249256 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1485:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMMLA_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 249256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_D),
     /* 249259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249265 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249267 */     GIR_RootConstrainSelectedInstOperands,
     /* 249268 */     // GIR_Coverage, 11392,
     /* 249268 */     GIR_EraseRootFromParent_Done,
     /* 249269 */   // Label 4785: @249269
     /* 249269 */   GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(249311), // Rule ID 11446 //
     /* 249274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249277 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 249282 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249285 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 249288 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249291 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249298 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1834:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRDMLSH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_B),
     /* 249301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249307 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249309 */     GIR_RootConstrainSelectedInstOperands,
     /* 249310 */     // GIR_Coverage, 11446,
     /* 249310 */     GIR_EraseRootFromParent_Done,
     /* 249311 */   // Label 4786: @249311
     /* 249311 */   GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(249353), // Rule ID 11447 //
     /* 249316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 249324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249333 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249340 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1834:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRDMLSH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 249340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_H),
     /* 249343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249349 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249351 */     GIR_RootConstrainSelectedInstOperands,
     /* 249352 */     // GIR_Coverage, 11447,
     /* 249352 */     GIR_EraseRootFromParent_Done,
     /* 249353 */   // Label 4787: @249353
     /* 249353 */   GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(249395), // Rule ID 11448 //
     /* 249358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 249366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249375 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249382 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1834:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRDMLSH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 249382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_S),
     /* 249385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249387 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249389 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249391 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249393 */     GIR_RootConstrainSelectedInstOperands,
     /* 249394 */     // GIR_Coverage, 11448,
     /* 249394 */     GIR_EraseRootFromParent_Done,
     /* 249395 */   // Label 4788: @249395
     /* 249395 */   GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(249437), // Rule ID 11449 //
     /* 249400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 249408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 249420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249424 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1834:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRDMLSH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 249424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_D),
     /* 249427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249433 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249435 */     GIR_RootConstrainSelectedInstOperands,
     /* 249436 */     // GIR_Coverage, 11449,
     /* 249436 */     GIR_EraseRootFromParent_Done,
     /* 249437 */   // Label 4789: @249437
     /* 249437 */   GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(249479), // Rule ID 11502 //
     /* 249442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 249450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249459 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249466 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1755:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_H),
     /* 249469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249475 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249477 */     GIR_RootConstrainSelectedInstOperands,
     /* 249478 */     // GIR_Coverage, 11502,
     /* 249478 */     GIR_EraseRootFromParent_Done,
     /* 249479 */   // Label 4790: @249479
     /* 249479 */   GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(249521), // Rule ID 11503 //
     /* 249484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 249492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249501 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249508 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1755:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 249508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_S),
     /* 249511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249513 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249515 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249517 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249519 */     GIR_RootConstrainSelectedInstOperands,
     /* 249520 */     // GIR_Coverage, 11503,
     /* 249520 */     GIR_EraseRootFromParent_Done,
     /* 249521 */   // Label 4791: @249521
     /* 249521 */   GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(249563), // Rule ID 11504 //
     /* 249526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 249534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249540 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249543 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249550 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1755:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 249550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_D),
     /* 249553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249557 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249559 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249561 */     GIR_RootConstrainSelectedInstOperands,
     /* 249562 */     // GIR_Coverage, 11504,
     /* 249562 */     GIR_EraseRootFromParent_Done,
     /* 249563 */   // Label 4792: @249563
     /* 249563 */   GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(249605), // Rule ID 11505 //
     /* 249568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 249576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249585 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249592 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1991:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_H),
     /* 249595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249601 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249603 */     GIR_RootConstrainSelectedInstOperands,
     /* 249604 */     // GIR_Coverage, 11505,
     /* 249604 */     GIR_EraseRootFromParent_Done,
     /* 249605 */   // Label 4793: @249605
     /* 249605 */   GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(249647), // Rule ID 11506 //
     /* 249610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 249618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249634 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1991:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 249634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_S),
     /* 249637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249639 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249641 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249643 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249645 */     GIR_RootConstrainSelectedInstOperands,
     /* 249646 */     // GIR_Coverage, 11506,
     /* 249646 */     GIR_EraseRootFromParent_Done,
     /* 249647 */   // Label 4794: @249647
     /* 249647 */   GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(249689), // Rule ID 11507 //
     /* 249652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 249660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249669 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249676 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1991:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 249676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_D),
     /* 249679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249683 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249685 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249687 */     GIR_RootConstrainSelectedInstOperands,
     /* 249688 */     // GIR_Coverage, 11507,
     /* 249688 */     GIR_EraseRootFromParent_Done,
     /* 249689 */   // Label 4795: @249689
     /* 249689 */   GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(249731), // Rule ID 11508 //
     /* 249694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 249702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249711 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249718 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1993:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_H),
     /* 249721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249727 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249729 */     GIR_RootConstrainSelectedInstOperands,
     /* 249730 */     // GIR_Coverage, 11508,
     /* 249730 */     GIR_EraseRootFromParent_Done,
     /* 249731 */   // Label 4796: @249731
     /* 249731 */   GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(249773), // Rule ID 11509 //
     /* 249736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 249744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249750 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249753 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249760 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1993:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 249760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_S),
     /* 249763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249767 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249769 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249771 */     GIR_RootConstrainSelectedInstOperands,
     /* 249772 */     // GIR_Coverage, 11509,
     /* 249772 */     GIR_EraseRootFromParent_Done,
     /* 249773 */   // Label 4797: @249773
     /* 249773 */   GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(249815), // Rule ID 11510 //
     /* 249778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 249786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249795 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249802 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1993:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 249802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_D),
     /* 249805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249809 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249811 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249813 */     GIR_RootConstrainSelectedInstOperands,
     /* 249814 */     // GIR_Coverage, 11510,
     /* 249814 */     GIR_EraseRootFromParent_Done,
     /* 249815 */   // Label 4798: @249815
     /* 249815 */   GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(249857), // Rule ID 11511 //
     /* 249820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 249828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249844 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1757:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_H),
     /* 249847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249851 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249853 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249855 */     GIR_RootConstrainSelectedInstOperands,
     /* 249856 */     // GIR_Coverage, 11511,
     /* 249856 */     GIR_EraseRootFromParent_Done,
     /* 249857 */   // Label 4799: @249857
     /* 249857 */   GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(249899), // Rule ID 11512 //
     /* 249862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 249870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249879 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 249882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249886 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1757:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 249886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_S),
     /* 249889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249893 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249895 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249897 */     GIR_RootConstrainSelectedInstOperands,
     /* 249898 */     // GIR_Coverage, 11512,
     /* 249898 */     GIR_EraseRootFromParent_Done,
     /* 249899 */   // Label 4800: @249899
     /* 249899 */   GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(249941), // Rule ID 11513 //
     /* 249904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 249912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249921 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 249924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249928 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1757:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 249928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_D),
     /* 249931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249937 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249939 */     GIR_RootConstrainSelectedInstOperands,
     /* 249940 */     // GIR_Coverage, 11513,
     /* 249940 */     GIR_EraseRootFromParent_Done,
     /* 249941 */   // Label 4801: @249941
     /* 249941 */   GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(249983), // Rule ID 11514 //
     /* 249946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 249954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249963 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 249966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249970 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1759:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 249970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_H),
     /* 249973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249977 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249979 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249981 */     GIR_RootConstrainSelectedInstOperands,
     /* 249982 */     // GIR_Coverage, 11514,
     /* 249982 */     GIR_EraseRootFromParent_Done,
     /* 249983 */   // Label 4802: @249983
     /* 249983 */   GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(250025), // Rule ID 11515 //
     /* 249988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 249996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250005 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250012 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1759:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_S),
     /* 250015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250021 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250023 */     GIR_RootConstrainSelectedInstOperands,
     /* 250024 */     // GIR_Coverage, 11515,
     /* 250024 */     GIR_EraseRootFromParent_Done,
     /* 250025 */   // Label 4803: @250025
     /* 250025 */   GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(250067), // Rule ID 11516 //
     /* 250030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 250038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250047 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250054 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1759:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_D),
     /* 250057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250061 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250063 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250065 */     GIR_RootConstrainSelectedInstOperands,
     /* 250066 */     // GIR_Coverage, 11516,
     /* 250066 */     GIR_EraseRootFromParent_Done,
     /* 250067 */   // Label 4804: @250067
     /* 250067 */   GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(250109), // Rule ID 11517 //
     /* 250072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250075 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 250080 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250089 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250096 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1995:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_H),
     /* 250099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250101 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250103 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250105 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250107 */     GIR_RootConstrainSelectedInstOperands,
     /* 250108 */     // GIR_Coverage, 11517,
     /* 250108 */     GIR_EraseRootFromParent_Done,
     /* 250109 */   // Label 4805: @250109
     /* 250109 */   GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(250151), // Rule ID 11518 //
     /* 250114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 250122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250128 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250131 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250138 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1995:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_S),
     /* 250141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250147 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250149 */     GIR_RootConstrainSelectedInstOperands,
     /* 250150 */     // GIR_Coverage, 11518,
     /* 250150 */     GIR_EraseRootFromParent_Done,
     /* 250151 */   // Label 4806: @250151
     /* 250151 */   GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(250193), // Rule ID 11519 //
     /* 250156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 250164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250173 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250180 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1995:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_D),
     /* 250183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250185 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250187 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250189 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250191 */     GIR_RootConstrainSelectedInstOperands,
     /* 250192 */     // GIR_Coverage, 11519,
     /* 250192 */     GIR_EraseRootFromParent_Done,
     /* 250193 */   // Label 4807: @250193
     /* 250193 */   GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(250235), // Rule ID 11520 //
     /* 250198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 250206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250215 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250222 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1997:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_H),
     /* 250225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250227 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250231 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250233 */     GIR_RootConstrainSelectedInstOperands,
     /* 250234 */     // GIR_Coverage, 11520,
     /* 250234 */     GIR_EraseRootFromParent_Done,
     /* 250235 */   // Label 4808: @250235
     /* 250235 */   GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(250277), // Rule ID 11521 //
     /* 250240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 250248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250257 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250264 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1997:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_S),
     /* 250267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250271 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250273 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250275 */     GIR_RootConstrainSelectedInstOperands,
     /* 250276 */     // GIR_Coverage, 11521,
     /* 250276 */     GIR_EraseRootFromParent_Done,
     /* 250277 */   // Label 4809: @250277
     /* 250277 */   GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(250319), // Rule ID 11522 //
     /* 250282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 250290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250299 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250306 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1997:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_D),
     /* 250309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250313 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250315 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250317 */     GIR_RootConstrainSelectedInstOperands,
     /* 250318 */     // GIR_Coverage, 11522,
     /* 250318 */     GIR_EraseRootFromParent_Done,
     /* 250319 */   // Label 4810: @250319
     /* 250319 */   GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(250361), // Rule ID 11531 //
     /* 250324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 250332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250348 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1795:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_H),
     /* 250351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250353 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250355 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250357 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250359 */     GIR_RootConstrainSelectedInstOperands,
     /* 250360 */     // GIR_Coverage, 11531,
     /* 250360 */     GIR_EraseRootFromParent_Done,
     /* 250361 */   // Label 4811: @250361
     /* 250361 */   GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(250403), // Rule ID 11532 //
     /* 250366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 250374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250390 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1795:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_S),
     /* 250393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250395 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250397 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250399 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250401 */     GIR_RootConstrainSelectedInstOperands,
     /* 250402 */     // GIR_Coverage, 11532,
     /* 250402 */     GIR_EraseRootFromParent_Done,
     /* 250403 */   // Label 4812: @250403
     /* 250403 */   GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(250445), // Rule ID 11533 //
     /* 250408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 250416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250425 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250432 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1795:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_D),
     /* 250435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250441 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250443 */     GIR_RootConstrainSelectedInstOperands,
     /* 250444 */     // GIR_Coverage, 11533,
     /* 250444 */     GIR_EraseRootFromParent_Done,
     /* 250445 */   // Label 4813: @250445
     /* 250445 */   GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(250487), // Rule ID 11534 //
     /* 250450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 250458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250474 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1798:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_H),
     /* 250477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250481 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250483 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250485 */     GIR_RootConstrainSelectedInstOperands,
     /* 250486 */     // GIR_Coverage, 11534,
     /* 250486 */     GIR_EraseRootFromParent_Done,
     /* 250487 */   // Label 4814: @250487
     /* 250487 */   GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(250529), // Rule ID 11535 //
     /* 250492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250495 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 250500 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250509 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250516 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1798:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_S),
     /* 250519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250523 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250525 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250527 */     GIR_RootConstrainSelectedInstOperands,
     /* 250528 */     // GIR_Coverage, 11535,
     /* 250528 */     GIR_EraseRootFromParent_Done,
     /* 250529 */   // Label 4815: @250529
     /* 250529 */   GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(250571), // Rule ID 11536 //
     /* 250534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 250542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250551 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250558 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1798:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_D),
     /* 250561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250567 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250569 */     GIR_RootConstrainSelectedInstOperands,
     /* 250570 */     // GIR_Coverage, 11536,
     /* 250570 */     GIR_EraseRootFromParent_Done,
     /* 250571 */   // Label 4816: @250571
     /* 250571 */   GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(250613), // Rule ID 11537 //
     /* 250576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 250584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250593 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250600 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1800:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_H),
     /* 250603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250607 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250609 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250611 */     GIR_RootConstrainSelectedInstOperands,
     /* 250612 */     // GIR_Coverage, 11537,
     /* 250612 */     GIR_EraseRootFromParent_Done,
     /* 250613 */   // Label 4817: @250613
     /* 250613 */   GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(250655), // Rule ID 11538 //
     /* 250618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 250626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250635 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250642 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1800:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_S),
     /* 250645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250651 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250653 */     GIR_RootConstrainSelectedInstOperands,
     /* 250654 */     // GIR_Coverage, 11538,
     /* 250654 */     GIR_EraseRootFromParent_Done,
     /* 250655 */   // Label 4818: @250655
     /* 250655 */   GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(250697), // Rule ID 11539 //
     /* 250660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 250668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250677 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250684 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1800:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_D),
     /* 250687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250693 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250695 */     GIR_RootConstrainSelectedInstOperands,
     /* 250696 */     // GIR_Coverage, 11539,
     /* 250696 */     GIR_EraseRootFromParent_Done,
     /* 250697 */   // Label 4819: @250697
     /* 250697 */   GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(250739), // Rule ID 11540 //
     /* 250702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 250710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250719 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250726 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1803:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_H),
     /* 250729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250731 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250733 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250735 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250737 */     GIR_RootConstrainSelectedInstOperands,
     /* 250738 */     // GIR_Coverage, 11540,
     /* 250738 */     GIR_EraseRootFromParent_Done,
     /* 250739 */   // Label 4820: @250739
     /* 250739 */   GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(250781), // Rule ID 11541 //
     /* 250744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 250752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250761 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250768 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1803:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_S),
     /* 250771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250777 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250779 */     GIR_RootConstrainSelectedInstOperands,
     /* 250780 */     // GIR_Coverage, 11541,
     /* 250780 */     GIR_EraseRootFromParent_Done,
     /* 250781 */   // Label 4821: @250781
     /* 250781 */   GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(250823), // Rule ID 11542 //
     /* 250786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 250794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250803 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250810 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1803:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_D),
     /* 250813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250819 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250821 */     GIR_RootConstrainSelectedInstOperands,
     /* 250822 */     // GIR_Coverage, 11542,
     /* 250822 */     GIR_EraseRootFromParent_Done,
     /* 250823 */   // Label 4822: @250823
     /* 250823 */   GIM_Try, /*On fail goto*//*Label 4823*/ GIMT_Encode4(250865), // Rule ID 11543 //
     /* 250828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 250836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250845 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250852 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1797:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_H),
     /* 250855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250859 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250861 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250863 */     GIR_RootConstrainSelectedInstOperands,
     /* 250864 */     // GIR_Coverage, 11543,
     /* 250864 */     GIR_EraseRootFromParent_Done,
     /* 250865 */   // Label 4823: @250865
     /* 250865 */   GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(250907), // Rule ID 11544 //
     /* 250870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 250878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250887 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 250890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250894 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1797:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 250894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_S),
     /* 250897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250903 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250905 */     GIR_RootConstrainSelectedInstOperands,
     /* 250906 */     // GIR_Coverage, 11544,
     /* 250906 */     GIR_EraseRootFromParent_Done,
     /* 250907 */   // Label 4824: @250907
     /* 250907 */   GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(250949), // Rule ID 11545 //
     /* 250912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 250920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250929 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 250932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250936 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1797:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 250936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_D),
     /* 250939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250945 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250947 */     GIR_RootConstrainSelectedInstOperands,
     /* 250948 */     // GIR_Coverage, 11545,
     /* 250948 */     GIR_EraseRootFromParent_Done,
     /* 250949 */   // Label 4825: @250949
     /* 250949 */   GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(250991), // Rule ID 11546 //
     /* 250954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 250962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 250971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 250974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250978 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1802:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 250978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_H),
     /* 250981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250985 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250987 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250989 */     GIR_RootConstrainSelectedInstOperands,
     /* 250990 */     // GIR_Coverage, 11546,
     /* 250990 */     GIR_EraseRootFromParent_Done,
     /* 250991 */   // Label 4826: @250991
     /* 250991 */   GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(251033), // Rule ID 11547 //
     /* 250996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250999 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 251004 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251007 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251010 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251013 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251020 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1802:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_S),
     /* 251023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 251025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251027 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251029 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251031 */     GIR_RootConstrainSelectedInstOperands,
     /* 251032 */     // GIR_Coverage, 11547,
     /* 251032 */     GIR_EraseRootFromParent_Done,
     /* 251033 */   // Label 4827: @251033
     /* 251033 */   GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(251075), // Rule ID 11548 //
     /* 251038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 251046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 251052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251055 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251062 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1802:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_D),
     /* 251065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 251067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251071 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251073 */     GIR_RootConstrainSelectedInstOperands,
     /* 251074 */     // GIR_Coverage, 11548,
     /* 251074 */     GIR_EraseRootFromParent_Done,
     /* 251075 */   // Label 4828: @251075
     /* 251075 */   GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(251117), // Rule ID 11549 //
     /* 251080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 251088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251097 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251104 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1970:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_B),
     /* 251107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251113 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251115 */     GIR_RootConstrainSelectedInstOperands,
     /* 251116 */     // GIR_Coverage, 11549,
     /* 251116 */     GIR_EraseRootFromParent_Done,
     /* 251117 */   // Label 4829: @251117
     /* 251117 */   GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(251159), // Rule ID 11551 //
     /* 251122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 251130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251139 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251146 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1970:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_H),
     /* 251149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251151 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251155 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251157 */     GIR_RootConstrainSelectedInstOperands,
     /* 251158 */     // GIR_Coverage, 11551,
     /* 251158 */     GIR_EraseRootFromParent_Done,
     /* 251159 */   // Label 4830: @251159
     /* 251159 */   GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(251201), // Rule ID 11553 //
     /* 251164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 251172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 251178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251181 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251188 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1970:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_S),
     /* 251191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251195 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251197 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251199 */     GIR_RootConstrainSelectedInstOperands,
     /* 251200 */     // GIR_Coverage, 11553,
     /* 251200 */     GIR_EraseRootFromParent_Done,
     /* 251201 */   // Label 4831: @251201
     /* 251201 */   GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(251243), // Rule ID 11555 //
     /* 251206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 251214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 251220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251223 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251230 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1970:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 251230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_D),
     /* 251233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251237 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251239 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251241 */     GIR_RootConstrainSelectedInstOperands,
     /* 251242 */     // GIR_Coverage, 11555,
     /* 251242 */     GIR_EraseRootFromParent_Done,
     /* 251243 */   // Label 4832: @251243
     /* 251243 */   GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(251285), // Rule ID 11557 //
     /* 251248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 251256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251265 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251272 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1730:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_B),
     /* 251275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251279 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251281 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251283 */     GIR_RootConstrainSelectedInstOperands,
     /* 251284 */     // GIR_Coverage, 11557,
     /* 251284 */     GIR_EraseRootFromParent_Done,
     /* 251285 */   // Label 4833: @251285
     /* 251285 */   GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(251327), // Rule ID 11558 //
     /* 251290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 251298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251314 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1730:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_H),
     /* 251317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251321 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251323 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251325 */     GIR_RootConstrainSelectedInstOperands,
     /* 251326 */     // GIR_Coverage, 11558,
     /* 251326 */     GIR_EraseRootFromParent_Done,
     /* 251327 */   // Label 4834: @251327
     /* 251327 */   GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(251369), // Rule ID 11559 //
     /* 251332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251335 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 251340 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251343 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 251346 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251349 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251356 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1730:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_S),
     /* 251359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251363 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251365 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251367 */     GIR_RootConstrainSelectedInstOperands,
     /* 251368 */     // GIR_Coverage, 11559,
     /* 251368 */     GIR_EraseRootFromParent_Done,
     /* 251369 */   // Label 4835: @251369
     /* 251369 */   GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(251411), // Rule ID 11560 //
     /* 251374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 251382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 251388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251391 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251398 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1730:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 251398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_D),
     /* 251401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251407 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251409 */     GIR_RootConstrainSelectedInstOperands,
     /* 251410 */     // GIR_Coverage, 11560,
     /* 251410 */     GIR_EraseRootFromParent_Done,
     /* 251411 */   // Label 4836: @251411
     /* 251411 */   GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(251453), // Rule ID 11561 //
     /* 251416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 251424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251433 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251440 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1971:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_B),
     /* 251443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251445 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251447 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251449 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251451 */     GIR_RootConstrainSelectedInstOperands,
     /* 251452 */     // GIR_Coverage, 11561,
     /* 251452 */     GIR_EraseRootFromParent_Done,
     /* 251453 */   // Label 4837: @251453
     /* 251453 */   GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(251495), // Rule ID 11562 //
     /* 251458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 251466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251475 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251482 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1971:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_H),
     /* 251485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251491 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251493 */     GIR_RootConstrainSelectedInstOperands,
     /* 251494 */     // GIR_Coverage, 11562,
     /* 251494 */     GIR_EraseRootFromParent_Done,
     /* 251495 */   // Label 4838: @251495
     /* 251495 */   GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(251537), // Rule ID 11563 //
     /* 251500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 251508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 251514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251517 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251524 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1971:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_S),
     /* 251527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251531 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251533 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251535 */     GIR_RootConstrainSelectedInstOperands,
     /* 251536 */     // GIR_Coverage, 11563,
     /* 251536 */     GIR_EraseRootFromParent_Done,
     /* 251537 */   // Label 4839: @251537
     /* 251537 */   GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(251579), // Rule ID 11564 //
     /* 251542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 251550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 251556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251559 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251566 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1971:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 251566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_D),
     /* 251569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251575 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251577 */     GIR_RootConstrainSelectedInstOperands,
     /* 251578 */     // GIR_Coverage, 11564,
     /* 251578 */     GIR_EraseRootFromParent_Done,
     /* 251579 */   // Label 4840: @251579
     /* 251579 */   GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(251621), // Rule ID 11565 //
     /* 251584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 251592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251601 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251608 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1865:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SRHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_B),
     /* 251611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251615 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251617 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251619 */     GIR_RootConstrainSelectedInstOperands,
     /* 251620 */     // GIR_Coverage, 11565,
     /* 251620 */     GIR_EraseRootFromParent_Done,
     /* 251621 */   // Label 4841: @251621
     /* 251621 */   GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(251663), // Rule ID 11567 //
     /* 251626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251629 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 251634 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251637 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251640 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251643 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251650 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1865:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SRHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_H),
     /* 251653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251657 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251659 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251661 */     GIR_RootConstrainSelectedInstOperands,
     /* 251662 */     // GIR_Coverage, 11567,
     /* 251662 */     GIR_EraseRootFromParent_Done,
     /* 251663 */   // Label 4842: @251663
     /* 251663 */   GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(251705), // Rule ID 11569 //
     /* 251668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 251676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 251682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251685 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251692 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1865:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SRHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_S),
     /* 251695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251697 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251699 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251701 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251703 */     GIR_RootConstrainSelectedInstOperands,
     /* 251704 */     // GIR_Coverage, 11569,
     /* 251704 */     GIR_EraseRootFromParent_Done,
     /* 251705 */   // Label 4843: @251705
     /* 251705 */   GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(251747), // Rule ID 11571 //
     /* 251710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 251718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 251724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251734 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1865:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SRHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 251734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_D),
     /* 251737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251743 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251745 */     GIR_RootConstrainSelectedInstOperands,
     /* 251746 */     // GIR_Coverage, 11571,
     /* 251746 */     GIR_EraseRootFromParent_Done,
     /* 251747 */   // Label 4844: @251747
     /* 251747 */   GIM_Try, /*On fail goto*//*Label 4845*/ GIMT_Encode4(251789), // Rule ID 11573 //
     /* 251752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 251760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251766 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251769 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251776 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2057:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (URHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_B),
     /* 251779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251781 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251783 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251785 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251787 */     GIR_RootConstrainSelectedInstOperands,
     /* 251788 */     // GIR_Coverage, 11573,
     /* 251788 */     GIR_EraseRootFromParent_Done,
     /* 251789 */   // Label 4845: @251789
     /* 251789 */   GIM_Try, /*On fail goto*//*Label 4846*/ GIMT_Encode4(251831), // Rule ID 11575 //
     /* 251794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 251802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251811 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251818 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2057:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (URHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_H),
     /* 251821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251823 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251825 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251827 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251829 */     GIR_RootConstrainSelectedInstOperands,
     /* 251830 */     // GIR_Coverage, 11575,
     /* 251830 */     GIR_EraseRootFromParent_Done,
     /* 251831 */   // Label 4846: @251831
     /* 251831 */   GIM_Try, /*On fail goto*//*Label 4847*/ GIMT_Encode4(251873), // Rule ID 11577 //
     /* 251836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251839 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 251844 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 251850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 251853 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251860 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2057:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 251860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_S),
     /* 251863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251869 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251871 */     GIR_RootConstrainSelectedInstOperands,
     /* 251872 */     // GIR_Coverage, 11577,
     /* 251872 */     GIR_EraseRootFromParent_Done,
     /* 251873 */   // Label 4847: @251873
     /* 251873 */   GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(251915), // Rule ID 11579 //
     /* 251878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 251886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 251892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251902 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2057:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (URHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 251902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_D),
     /* 251905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251909 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251911 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251913 */     GIR_RootConstrainSelectedInstOperands,
     /* 251914 */     // GIR_Coverage, 11579,
     /* 251914 */     GIR_EraseRootFromParent_Done,
     /* 251915 */   // Label 4848: @251915
     /* 251915 */   GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(251957), // Rule ID 11581 //
     /* 251920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 251928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 251934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 251937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251944 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1731:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 251944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_B),
     /* 251947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251951 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251953 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251955 */     GIR_RootConstrainSelectedInstOperands,
     /* 251956 */     // GIR_Coverage, 11581,
     /* 251956 */     GIR_EraseRootFromParent_Done,
     /* 251957 */   // Label 4849: @251957
     /* 251957 */   GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(251999), // Rule ID 11582 //
     /* 251962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 251970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 251976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 251979 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251986 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1731:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 251986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_H),
     /* 251989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 251991 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251993 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251995 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251997 */     GIR_RootConstrainSelectedInstOperands,
     /* 251998 */     // GIR_Coverage, 11582,
     /* 251998 */     GIR_EraseRootFromParent_Done,
     /* 251999 */   // Label 4850: @251999
     /* 251999 */   GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(252041), // Rule ID 11583 //
     /* 252004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 252012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252021 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252028 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1731:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_S),
     /* 252031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252037 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252039 */     GIR_RootConstrainSelectedInstOperands,
     /* 252040 */     // GIR_Coverage, 11583,
     /* 252040 */     GIR_EraseRootFromParent_Done,
     /* 252041 */   // Label 4851: @252041
     /* 252041 */   GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(252083), // Rule ID 11584 //
     /* 252046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 252054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252063 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252070 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1731:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 252070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_D),
     /* 252073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252077 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252079 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252081 */     GIR_RootConstrainSelectedInstOperands,
     /* 252082 */     // GIR_Coverage, 11584,
     /* 252082 */     GIR_EraseRootFromParent_Done,
     /* 252083 */   // Label 4852: @252083
     /* 252083 */   GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(252125), // Rule ID 11585 //
     /* 252088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 252096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 252102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 252105 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252112 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1972:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_B),
     /* 252115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252121 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252123 */     GIR_RootConstrainSelectedInstOperands,
     /* 252124 */     // GIR_Coverage, 11585,
     /* 252124 */     GIR_EraseRootFromParent_Done,
     /* 252125 */   // Label 4853: @252125
     /* 252125 */   GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(252167), // Rule ID 11586 //
     /* 252130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 252138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252147 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252154 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1972:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_H),
     /* 252157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252159 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252161 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252163 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252165 */     GIR_RootConstrainSelectedInstOperands,
     /* 252166 */     // GIR_Coverage, 11586,
     /* 252166 */     GIR_EraseRootFromParent_Done,
     /* 252167 */   // Label 4854: @252167
     /* 252167 */   GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(252209), // Rule ID 11587 //
     /* 252172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 252180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252189 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252196 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1972:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_S),
     /* 252199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252201 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252203 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252205 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252207 */     GIR_RootConstrainSelectedInstOperands,
     /* 252208 */     // GIR_Coverage, 11587,
     /* 252208 */     GIR_EraseRootFromParent_Done,
     /* 252209 */   // Label 4855: @252209
     /* 252209 */   GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(252251), // Rule ID 11588 //
     /* 252214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 252222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252238 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1972:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 252238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_D),
     /* 252241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252247 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252249 */     GIR_RootConstrainSelectedInstOperands,
     /* 252250 */     // GIR_Coverage, 11588,
     /* 252250 */     GIR_EraseRootFromParent_Done,
     /* 252251 */   // Label 4856: @252251
     /* 252251 */   GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(252293), // Rule ID 11589 //
     /* 252256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 252264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252273 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252280 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1947:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_H),
     /* 252283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 252285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252287 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252289 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252291 */     GIR_RootConstrainSelectedInstOperands,
     /* 252292 */     // GIR_Coverage, 11589,
     /* 252292 */     GIR_EraseRootFromParent_Done,
     /* 252293 */   // Label 4857: @252293
     /* 252293 */   GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(252335), // Rule ID 11590 //
     /* 252298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 252306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252315 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252322 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1947:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_S),
     /* 252325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 252327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252329 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252331 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252333 */     GIR_RootConstrainSelectedInstOperands,
     /* 252334 */     // GIR_Coverage, 11590,
     /* 252334 */     GIR_EraseRootFromParent_Done,
     /* 252335 */   // Label 4858: @252335
     /* 252335 */   GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(252377), // Rule ID 11591 //
     /* 252340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 252348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252364 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1947:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_D),
     /* 252367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 252369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252371 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252373 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252375 */     GIR_RootConstrainSelectedInstOperands,
     /* 252376 */     // GIR_Coverage, 11591,
     /* 252376 */     GIR_EraseRootFromParent_Done,
     /* 252377 */   // Label 4859: @252377
     /* 252377 */   GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(252419), // Rule ID 11592 //
     /* 252382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 252390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 252396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 252399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252406 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1262:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (ADDP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_B),
     /* 252409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252411 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252413 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252415 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252417 */     GIR_RootConstrainSelectedInstOperands,
     /* 252418 */     // GIR_Coverage, 11592,
     /* 252418 */     GIR_EraseRootFromParent_Done,
     /* 252419 */   // Label 4860: @252419
     /* 252419 */   GIM_Try, /*On fail goto*//*Label 4861*/ GIMT_Encode4(252461), // Rule ID 11593 //
     /* 252424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 252432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252441 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252448 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1262:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ADDP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_H),
     /* 252451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252455 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252457 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252459 */     GIR_RootConstrainSelectedInstOperands,
     /* 252460 */     // GIR_Coverage, 11593,
     /* 252460 */     GIR_EraseRootFromParent_Done,
     /* 252461 */   // Label 4861: @252461
     /* 252461 */   GIM_Try, /*On fail goto*//*Label 4862*/ GIMT_Encode4(252503), // Rule ID 11594 //
     /* 252466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 252474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252483 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252490 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1262:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADDP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_S),
     /* 252493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252497 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252499 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252501 */     GIR_RootConstrainSelectedInstOperands,
     /* 252502 */     // GIR_Coverage, 11594,
     /* 252502 */     GIR_EraseRootFromParent_Done,
     /* 252503 */   // Label 4862: @252503
     /* 252503 */   GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(252545), // Rule ID 11595 //
     /* 252508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 252516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252532 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1262:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADDP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 252532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_D),
     /* 252535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252539 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252541 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252543 */     GIR_RootConstrainSelectedInstOperands,
     /* 252544 */     // GIR_Coverage, 11595,
     /* 252544 */     GIR_EraseRootFromParent_Done,
     /* 252545 */   // Label 4863: @252545
     /* 252545 */   GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(252587), // Rule ID 11596 //
     /* 252550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252553 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 252558 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252561 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 252564 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 252567 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252574 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1741:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_B),
     /* 252577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252579 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252581 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252583 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252585 */     GIR_RootConstrainSelectedInstOperands,
     /* 252586 */     // GIR_Coverage, 11596,
     /* 252586 */     GIR_EraseRootFromParent_Done,
     /* 252587 */   // Label 4864: @252587
     /* 252587 */   GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(252629), // Rule ID 11597 //
     /* 252592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252595 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 252600 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252603 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252606 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252609 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252616 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1741:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_H),
     /* 252619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252621 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252623 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252625 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252627 */     GIR_RootConstrainSelectedInstOperands,
     /* 252628 */     // GIR_Coverage, 11597,
     /* 252628 */     GIR_EraseRootFromParent_Done,
     /* 252629 */   // Label 4865: @252629
     /* 252629 */   GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(252671), // Rule ID 11598 //
     /* 252634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 252642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252651 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252658 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1741:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_S),
     /* 252661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252667 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252669 */     GIR_RootConstrainSelectedInstOperands,
     /* 252670 */     // GIR_Coverage, 11598,
     /* 252670 */     GIR_EraseRootFromParent_Done,
     /* 252671 */   // Label 4866: @252671
     /* 252671 */   GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(252713), // Rule ID 11599 //
     /* 252676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 252684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252693 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252700 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1741:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 252700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_D),
     /* 252703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252707 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252709 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252711 */     GIR_RootConstrainSelectedInstOperands,
     /* 252712 */     // GIR_Coverage, 11599,
     /* 252712 */     GIR_EraseRootFromParent_Done,
     /* 252713 */   // Label 4867: @252713
     /* 252713 */   GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(252755), // Rule ID 11600 //
     /* 252718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 252726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 252732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 252735 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252742 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1979:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_B),
     /* 252745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252751 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252753 */     GIR_RootConstrainSelectedInstOperands,
     /* 252754 */     // GIR_Coverage, 11600,
     /* 252754 */     GIR_EraseRootFromParent_Done,
     /* 252755 */   // Label 4868: @252755
     /* 252755 */   GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(252797), // Rule ID 11601 //
     /* 252760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 252768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252784 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1979:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_H),
     /* 252787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252791 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252793 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252795 */     GIR_RootConstrainSelectedInstOperands,
     /* 252796 */     // GIR_Coverage, 11601,
     /* 252796 */     GIR_EraseRootFromParent_Done,
     /* 252797 */   // Label 4869: @252797
     /* 252797 */   GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(252839), // Rule ID 11602 //
     /* 252802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 252810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252819 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252826 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1979:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_S),
     /* 252829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252833 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252835 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252837 */     GIR_RootConstrainSelectedInstOperands,
     /* 252838 */     // GIR_Coverage, 11602,
     /* 252838 */     GIR_EraseRootFromParent_Done,
     /* 252839 */   // Label 4870: @252839
     /* 252839 */   GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(252881), // Rule ID 11603 //
     /* 252844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 252852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 252858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 252861 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252868 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1979:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 252868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_D),
     /* 252871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252877 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252879 */     GIR_RootConstrainSelectedInstOperands,
     /* 252880 */     // GIR_Coverage, 11603,
     /* 252880 */     GIR_EraseRootFromParent_Done,
     /* 252881 */   // Label 4871: @252881
     /* 252881 */   GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(252923), // Rule ID 11604 //
     /* 252886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 252894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252897 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 252900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 252903 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252910 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1750:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 252910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_B),
     /* 252913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252915 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252917 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252919 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252921 */     GIR_RootConstrainSelectedInstOperands,
     /* 252922 */     // GIR_Coverage, 11604,
     /* 252922 */     GIR_EraseRootFromParent_Done,
     /* 252923 */   // Label 4872: @252923
     /* 252923 */   GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(252965), // Rule ID 11605 //
     /* 252928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 252936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 252942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 252945 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252952 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1750:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 252952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_H),
     /* 252955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 252959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 252961 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 252963 */     GIR_RootConstrainSelectedInstOperands,
     /* 252964 */     // GIR_Coverage, 11605,
     /* 252964 */     GIR_EraseRootFromParent_Done,
     /* 252965 */   // Label 4873: @252965
     /* 252965 */   GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(253007), // Rule ID 11606 //
     /* 252970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 252978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 252984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 252987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252994 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1750:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 252994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_S),
     /* 252997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 252999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253001 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253003 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253005 */     GIR_RootConstrainSelectedInstOperands,
     /* 253006 */     // GIR_Coverage, 11606,
     /* 253006 */     GIR_EraseRootFromParent_Done,
     /* 253007 */   // Label 4874: @253007
     /* 253007 */   GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(253049), // Rule ID 11607 //
     /* 253012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 253020 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253023 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 253026 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 253029 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253036 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1750:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_D),
     /* 253039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253041 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253043 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253045 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253047 */     GIR_RootConstrainSelectedInstOperands,
     /* 253048 */     // GIR_Coverage, 11607,
     /* 253048 */     GIR_EraseRootFromParent_Done,
     /* 253049 */   // Label 4875: @253049
     /* 253049 */   GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(253091), // Rule ID 11608 //
     /* 253054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 253062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 253068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 253071 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253078 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1988:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_B),
     /* 253081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253083 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253085 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253087 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253089 */     GIR_RootConstrainSelectedInstOperands,
     /* 253090 */     // GIR_Coverage, 11608,
     /* 253090 */     GIR_EraseRootFromParent_Done,
     /* 253091 */   // Label 4876: @253091
     /* 253091 */   GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(253133), // Rule ID 11609 //
     /* 253096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 253104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 253110 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 253113 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253120 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1988:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 253120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_H),
     /* 253123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253127 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253129 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253131 */     GIR_RootConstrainSelectedInstOperands,
     /* 253132 */     // GIR_Coverage, 11609,
     /* 253132 */     GIR_EraseRootFromParent_Done,
     /* 253133 */   // Label 4877: @253133
     /* 253133 */   GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(253175), // Rule ID 11610 //
     /* 253138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 253146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 253152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 253155 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253162 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1988:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_S),
     /* 253165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253167 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253169 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253171 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253173 */     GIR_RootConstrainSelectedInstOperands,
     /* 253174 */     // GIR_Coverage, 11610,
     /* 253174 */     GIR_EraseRootFromParent_Done,
     /* 253175 */   // Label 4878: @253175
     /* 253175 */   GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(253217), // Rule ID 11611 //
     /* 253180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 253188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 253194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 253197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253204 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1988:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_D),
     /* 253207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253209 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253211 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253213 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253215 */     GIR_RootConstrainSelectedInstOperands,
     /* 253216 */     // GIR_Coverage, 11611,
     /* 253216 */     GIR_EraseRootFromParent_Done,
     /* 253217 */   // Label 4879: @253217
     /* 253217 */   GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(253259), // Rule ID 11612 //
     /* 253222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253225 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
     /* 253230 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253233 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 253236 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 253239 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253246 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2064:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URSQRTE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S),
     /* 253249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 253251 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253253 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253255 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253257 */     GIR_RootConstrainSelectedInstOperands,
     /* 253258 */     // GIR_Coverage, 11612,
     /* 253258 */     GIR_EraseRootFromParent_Done,
     /* 253259 */   // Label 4880: @253259
     /* 253259 */   GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(253301), // Rule ID 11623 //
     /* 253264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 253272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 253278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 253281 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253288 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1829:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQNEG_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B),
     /* 253291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 253293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253297 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253299 */     GIR_RootConstrainSelectedInstOperands,
     /* 253300 */     // GIR_Coverage, 11623,
     /* 253300 */     GIR_EraseRootFromParent_Done,
     /* 253301 */   // Label 4881: @253301
     /* 253301 */   GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(253343), // Rule ID 11624 //
     /* 253306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 253314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 253320 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 253323 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253330 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1829:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQNEG_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 253330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H),
     /* 253333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 253335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253337 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253339 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253341 */     GIR_RootConstrainSelectedInstOperands,
     /* 253342 */     // GIR_Coverage, 11624,
     /* 253342 */     GIR_EraseRootFromParent_Done,
     /* 253343 */   // Label 4882: @253343
     /* 253343 */   GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(253385), // Rule ID 11625 //
     /* 253348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 253356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 253362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 253365 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253372 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1829:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQNEG_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S),
     /* 253375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 253377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253381 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253383 */     GIR_RootConstrainSelectedInstOperands,
     /* 253384 */     // GIR_Coverage, 11625,
     /* 253384 */     GIR_EraseRootFromParent_Done,
     /* 253385 */   // Label 4883: @253385
     /* 253385 */   GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(253427), // Rule ID 11626 //
     /* 253390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 253398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 253404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 253407 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253414 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1829:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQNEG_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D),
     /* 253417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 253419 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253421 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253423 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253425 */     GIR_RootConstrainSelectedInstOperands,
     /* 253426 */     // GIR_Coverage, 11626,
     /* 253426 */     GIR_EraseRootFromParent_Done,
     /* 253427 */   // Label 4884: @253427
     /* 253427 */   GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(253469), // Rule ID 11635 //
     /* 253432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 253440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 253446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 253449 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253456 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1770:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_B),
     /* 253459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253461 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253463 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253465 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253467 */     GIR_RootConstrainSelectedInstOperands,
     /* 253468 */     // GIR_Coverage, 11635,
     /* 253468 */     GIR_EraseRootFromParent_Done,
     /* 253469 */   // Label 4885: @253469
     /* 253469 */   GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(253511), // Rule ID 11636 //
     /* 253474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 253482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 253488 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 253491 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253498 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1770:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 253498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_H),
     /* 253501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253507 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253509 */     GIR_RootConstrainSelectedInstOperands,
     /* 253510 */     // GIR_Coverage, 11636,
     /* 253510 */     GIR_EraseRootFromParent_Done,
     /* 253511 */   // Label 4886: @253511
     /* 253511 */   GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(253553), // Rule ID 11637 //
     /* 253516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 253524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 253530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 253533 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253540 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1770:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_S),
     /* 253543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253549 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253551 */     GIR_RootConstrainSelectedInstOperands,
     /* 253552 */     // GIR_Coverage, 11637,
     /* 253552 */     GIR_EraseRootFromParent_Done,
     /* 253553 */   // Label 4887: @253553
     /* 253553 */   GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(253595), // Rule ID 11638 //
     /* 253558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 253566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 253572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 253575 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253582 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1770:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_D),
     /* 253585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253587 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253589 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253591 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253593 */     GIR_RootConstrainSelectedInstOperands,
     /* 253594 */     // GIR_Coverage, 11638,
     /* 253594 */     GIR_EraseRootFromParent_Done,
     /* 253595 */   // Label 4888: @253595
     /* 253595 */   GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(253637), // Rule ID 11639 //
     /* 253600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 253608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 253614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 253617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253624 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2006:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_B),
     /* 253627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253631 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253633 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253635 */     GIR_RootConstrainSelectedInstOperands,
     /* 253636 */     // GIR_Coverage, 11639,
     /* 253636 */     GIR_EraseRootFromParent_Done,
     /* 253637 */   // Label 4889: @253637
     /* 253637 */   GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(253679), // Rule ID 11640 //
     /* 253642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 253650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 253656 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 253659 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253666 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2006:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 253666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_H),
     /* 253669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253673 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253675 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253677 */     GIR_RootConstrainSelectedInstOperands,
     /* 253678 */     // GIR_Coverage, 11640,
     /* 253678 */     GIR_EraseRootFromParent_Done,
     /* 253679 */   // Label 4890: @253679
     /* 253679 */   GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(253721), // Rule ID 11641 //
     /* 253684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 253692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 253698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 253701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253708 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2006:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_S),
     /* 253711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253715 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253717 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253719 */     GIR_RootConstrainSelectedInstOperands,
     /* 253720 */     // GIR_Coverage, 11641,
     /* 253720 */     GIR_EraseRootFromParent_Done,
     /* 253721 */   // Label 4891: @253721
     /* 253721 */   GIM_Try, /*On fail goto*//*Label 4892*/ GIMT_Encode4(253763), // Rule ID 11642 //
     /* 253726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 253734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 253740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 253743 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253750 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2006:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_D),
     /* 253753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253757 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253759 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253761 */     GIR_RootConstrainSelectedInstOperands,
     /* 253762 */     // GIR_Coverage, 11642,
     /* 253762 */     GIR_EraseRootFromParent_Done,
     /* 253763 */   // Label 4892: @253763
     /* 253763 */   GIM_Try, /*On fail goto*//*Label 4893*/ GIMT_Encode4(253805), // Rule ID 11643 //
     /* 253768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 253776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 253782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 253785 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253792 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1857:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_B),
     /* 253795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253799 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253801 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253803 */     GIR_RootConstrainSelectedInstOperands,
     /* 253804 */     // GIR_Coverage, 11643,
     /* 253804 */     GIR_EraseRootFromParent_Done,
     /* 253805 */   // Label 4893: @253805
     /* 253805 */   GIM_Try, /*On fail goto*//*Label 4894*/ GIMT_Encode4(253847), // Rule ID 11644 //
     /* 253810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 253818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 253824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 253827 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253834 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1857:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 253834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_H),
     /* 253837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253845 */     GIR_RootConstrainSelectedInstOperands,
     /* 253846 */     // GIR_Coverage, 11644,
     /* 253846 */     GIR_EraseRootFromParent_Done,
     /* 253847 */   // Label 4894: @253847
     /* 253847 */   GIM_Try, /*On fail goto*//*Label 4895*/ GIMT_Encode4(253889), // Rule ID 11645 //
     /* 253852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 253860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 253863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 253866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 253869 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 253872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253876 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1857:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 253876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_S),
     /* 253879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253881 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253883 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253885 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253887 */     GIR_RootConstrainSelectedInstOperands,
     /* 253888 */     // GIR_Coverage, 11645,
     /* 253888 */     GIR_EraseRootFromParent_Done,
     /* 253889 */   // Label 4895: @253889
     /* 253889 */   GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(253931), // Rule ID 11646 //
     /* 253894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 253902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 253905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 253908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 253911 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 253914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253918 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1857:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 253918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_D),
     /* 253921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253927 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253929 */     GIR_RootConstrainSelectedInstOperands,
     /* 253930 */     // GIR_Coverage, 11646,
     /* 253930 */     GIR_EraseRootFromParent_Done,
     /* 253931 */   // Label 4896: @253931
     /* 253931 */   GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(253973), // Rule ID 11647 //
     /* 253936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 253944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 253947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 253950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 253953 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 253956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 253960 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2050:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 253960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_B),
     /* 253963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 253965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 253967 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 253969 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 253971 */     GIR_RootConstrainSelectedInstOperands,
     /* 253972 */     // GIR_Coverage, 11647,
     /* 253972 */     GIR_EraseRootFromParent_Done,
     /* 253973 */   // Label 4897: @253973
     /* 253973 */   GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(254015), // Rule ID 11648 //
     /* 253978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 253981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 253986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 253989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 253992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 253995 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 253998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254002 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2050:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_H),
     /* 254005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254011 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254013 */     GIR_RootConstrainSelectedInstOperands,
     /* 254014 */     // GIR_Coverage, 11648,
     /* 254014 */     GIR_EraseRootFromParent_Done,
     /* 254015 */   // Label 4898: @254015
     /* 254015 */   GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(254057), // Rule ID 11649 //
     /* 254020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 254028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254037 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254044 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2050:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_S),
     /* 254047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254049 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254051 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254053 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254055 */     GIR_RootConstrainSelectedInstOperands,
     /* 254056 */     // GIR_Coverage, 11649,
     /* 254056 */     GIR_EraseRootFromParent_Done,
     /* 254057 */   // Label 4899: @254057
     /* 254057 */   GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(254099), // Rule ID 11650 //
     /* 254062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 254070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254079 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254086 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2050:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_D),
     /* 254089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254091 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254093 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254095 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254097 */     GIR_RootConstrainSelectedInstOperands,
     /* 254098 */     // GIR_Coverage, 11650,
     /* 254098 */     GIR_EraseRootFromParent_Done,
     /* 254099 */   // Label 4900: @254099
     /* 254099 */   GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(254141), // Rule ID 11651 //
     /* 254104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 254112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254121 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254128 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1921:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SUQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_B),
     /* 254131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254135 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254137 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254139 */     GIR_RootConstrainSelectedInstOperands,
     /* 254140 */     // GIR_Coverage, 11651,
     /* 254140 */     GIR_EraseRootFromParent_Done,
     /* 254141 */   // Label 4901: @254141
     /* 254141 */   GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(254183), // Rule ID 11652 //
     /* 254146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 254154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 254160 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 254163 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 254166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254170 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1921:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_H),
     /* 254173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254177 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254179 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254181 */     GIR_RootConstrainSelectedInstOperands,
     /* 254182 */     // GIR_Coverage, 11652,
     /* 254182 */     GIR_EraseRootFromParent_Done,
     /* 254183 */   // Label 4902: @254183
     /* 254183 */   GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(254225), // Rule ID 11653 //
     /* 254188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 254196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254212 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1921:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_S),
     /* 254215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254219 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254221 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254223 */     GIR_RootConstrainSelectedInstOperands,
     /* 254224 */     // GIR_Coverage, 11653,
     /* 254224 */     GIR_EraseRootFromParent_Done,
     /* 254225 */   // Label 4903: @254225
     /* 254225 */   GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(254267), // Rule ID 11654 //
     /* 254230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 254238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254254 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1921:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_D),
     /* 254257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254261 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254263 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254265 */     GIR_RootConstrainSelectedInstOperands,
     /* 254266 */     // GIR_Coverage, 11654,
     /* 254266 */     GIR_EraseRootFromParent_Done,
     /* 254267 */   // Label 4904: @254267
     /* 254267 */   GIM_Try, /*On fail goto*//*Label 4905*/ GIMT_Encode4(254309), // Rule ID 11655 //
     /* 254272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 254280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254283 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254286 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254289 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254296 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2071:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (USQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_B),
     /* 254299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254303 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254305 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254307 */     GIR_RootConstrainSelectedInstOperands,
     /* 254308 */     // GIR_Coverage, 11655,
     /* 254308 */     GIR_EraseRootFromParent_Done,
     /* 254309 */   // Label 4905: @254309
     /* 254309 */   GIM_Try, /*On fail goto*//*Label 4906*/ GIMT_Encode4(254351), // Rule ID 11656 //
     /* 254314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 254322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 254328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 254331 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 254334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254338 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2071:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (USQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_H),
     /* 254341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254347 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254349 */     GIR_RootConstrainSelectedInstOperands,
     /* 254350 */     // GIR_Coverage, 11656,
     /* 254350 */     GIR_EraseRootFromParent_Done,
     /* 254351 */   // Label 4906: @254351
     /* 254351 */   GIM_Try, /*On fail goto*//*Label 4907*/ GIMT_Encode4(254393), // Rule ID 11657 //
     /* 254356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 254364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254373 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254380 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2071:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (USQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_S),
     /* 254383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254387 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254389 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254391 */     GIR_RootConstrainSelectedInstOperands,
     /* 254392 */     // GIR_Coverage, 11657,
     /* 254392 */     GIR_EraseRootFromParent_Done,
     /* 254393 */   // Label 4907: @254393
     /* 254393 */   GIM_Try, /*On fail goto*//*Label 4908*/ GIMT_Encode4(254435), // Rule ID 11658 //
     /* 254398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 254406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254415 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254422 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2071:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (USQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_D),
     /* 254425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254427 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254429 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254431 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254433 */     GIR_RootConstrainSelectedInstOperands,
     /* 254434 */     // GIR_Coverage, 11658,
     /* 254434 */     GIR_EraseRootFromParent_Done,
     /* 254435 */   // Label 4908: @254435
     /* 254435 */   GIM_Try, /*On fail goto*//*Label 4909*/ GIMT_Encode4(254477), // Rule ID 11659 //
     /* 254440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 254448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254464 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1860:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_B),
     /* 254467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254471 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254473 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254475 */     GIR_RootConstrainSelectedInstOperands,
     /* 254476 */     // GIR_Coverage, 11659,
     /* 254476 */     GIR_EraseRootFromParent_Done,
     /* 254477 */   // Label 4909: @254477
     /* 254477 */   GIM_Try, /*On fail goto*//*Label 4910*/ GIMT_Encode4(254519), // Rule ID 11660 //
     /* 254482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 254490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 254496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 254499 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 254502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254506 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1860:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_H),
     /* 254509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254513 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254515 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254517 */     GIR_RootConstrainSelectedInstOperands,
     /* 254518 */     // GIR_Coverage, 11660,
     /* 254518 */     GIR_EraseRootFromParent_Done,
     /* 254519 */   // Label 4910: @254519
     /* 254519 */   GIM_Try, /*On fail goto*//*Label 4911*/ GIMT_Encode4(254561), // Rule ID 11661 //
     /* 254524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 254532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254541 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254548 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1860:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_S),
     /* 254551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254557 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254559 */     GIR_RootConstrainSelectedInstOperands,
     /* 254560 */     // GIR_Coverage, 11661,
     /* 254560 */     GIR_EraseRootFromParent_Done,
     /* 254561 */   // Label 4911: @254561
     /* 254561 */   GIM_Try, /*On fail goto*//*Label 4912*/ GIMT_Encode4(254603), // Rule ID 11662 //
     /* 254566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 254574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254583 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254590 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1860:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_D),
     /* 254593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254597 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254599 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254601 */     GIR_RootConstrainSelectedInstOperands,
     /* 254602 */     // GIR_Coverage, 11662,
     /* 254602 */     GIR_EraseRootFromParent_Done,
     /* 254603 */   // Label 4912: @254603
     /* 254603 */   GIM_Try, /*On fail goto*//*Label 4913*/ GIMT_Encode4(254645), // Rule ID 11663 //
     /* 254608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 254616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254625 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254632 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2053:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_B),
     /* 254635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254641 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254643 */     GIR_RootConstrainSelectedInstOperands,
     /* 254644 */     // GIR_Coverage, 11663,
     /* 254644 */     GIR_EraseRootFromParent_Done,
     /* 254645 */   // Label 4913: @254645
     /* 254645 */   GIM_Try, /*On fail goto*//*Label 4914*/ GIMT_Encode4(254687), // Rule ID 11664 //
     /* 254650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 254658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 254664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 254667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 254670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254674 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2053:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_H),
     /* 254677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254681 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254683 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254685 */     GIR_RootConstrainSelectedInstOperands,
     /* 254686 */     // GIR_Coverage, 11664,
     /* 254686 */     GIR_EraseRootFromParent_Done,
     /* 254687 */   // Label 4914: @254687
     /* 254687 */   GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(254729), // Rule ID 11665 //
     /* 254692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 254700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254709 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254716 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2053:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_S),
     /* 254719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254723 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254725 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254727 */     GIR_RootConstrainSelectedInstOperands,
     /* 254728 */     // GIR_Coverage, 11665,
     /* 254728 */     GIR_EraseRootFromParent_Done,
     /* 254729 */   // Label 4915: @254729
     /* 254729 */   GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(254771), // Rule ID 11666 //
     /* 254734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 254742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254751 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254758 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2053:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_D),
     /* 254761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254767 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254769 */     GIR_RootConstrainSelectedInstOperands,
     /* 254770 */     // GIR_Coverage, 11666,
     /* 254770 */     GIR_EraseRootFromParent_Done,
     /* 254771 */   // Label 4916: @254771
     /* 254771 */   GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(254813), // Rule ID 11667 //
     /* 254776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 254784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254793 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254800 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1867:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_B),
     /* 254803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254809 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254811 */     GIR_RootConstrainSelectedInstOperands,
     /* 254812 */     // GIR_Coverage, 11667,
     /* 254812 */     GIR_EraseRootFromParent_Done,
     /* 254813 */   // Label 4917: @254813
     /* 254813 */   GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(254855), // Rule ID 11668 //
     /* 254818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 254826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 254832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 254835 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 254838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254842 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1867:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 254842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_H),
     /* 254845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254847 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254851 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254853 */     GIR_RootConstrainSelectedInstOperands,
     /* 254854 */     // GIR_Coverage, 11668,
     /* 254854 */     GIR_EraseRootFromParent_Done,
     /* 254855 */   // Label 4918: @254855
     /* 254855 */   GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(254897), // Rule ID 11669 //
     /* 254860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 254868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 254871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 254874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 254877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 254880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254884 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1867:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 254884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_S),
     /* 254887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254891 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254893 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254895 */     GIR_RootConstrainSelectedInstOperands,
     /* 254896 */     // GIR_Coverage, 11669,
     /* 254896 */     GIR_EraseRootFromParent_Done,
     /* 254897 */   // Label 4919: @254897
     /* 254897 */   GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(254939), // Rule ID 11670 //
     /* 254902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 254910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 254913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 254916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 254919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 254922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254926 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1867:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 254926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_D),
     /* 254929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254933 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254935 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254937 */     GIR_RootConstrainSelectedInstOperands,
     /* 254938 */     // GIR_Coverage, 11670,
     /* 254938 */     GIR_EraseRootFromParent_Done,
     /* 254939 */   // Label 4920: @254939
     /* 254939 */   GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(254981), // Rule ID 11671 //
     /* 254944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 254952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 254955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 254961 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 254964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 254968 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2058:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (URSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 254968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_B),
     /* 254971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 254973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 254975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 254977 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 254979 */     GIR_RootConstrainSelectedInstOperands,
     /* 254980 */     // GIR_Coverage, 11671,
     /* 254980 */     GIR_EraseRootFromParent_Done,
     /* 254981 */   // Label 4921: @254981
     /* 254981 */   GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(255023), // Rule ID 11672 //
     /* 254986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 254989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 254994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 254997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 255000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255010 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2058:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (URSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_H),
     /* 255013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255019 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255021 */     GIR_RootConstrainSelectedInstOperands,
     /* 255022 */     // GIR_Coverage, 11672,
     /* 255022 */     GIR_EraseRootFromParent_Done,
     /* 255023 */   // Label 4922: @255023
     /* 255023 */   GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(255065), // Rule ID 11673 //
     /* 255028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 255036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 255042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255052 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2058:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_S),
     /* 255055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255061 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255063 */     GIR_RootConstrainSelectedInstOperands,
     /* 255064 */     // GIR_Coverage, 11673,
     /* 255064 */     GIR_EraseRootFromParent_Done,
     /* 255065 */   // Label 4923: @255065
     /* 255065 */   GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(255107), // Rule ID 11674 //
     /* 255070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 255078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 255084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255087 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255094 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2058:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (URSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_D),
     /* 255097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255099 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255101 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255103 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255105 */     GIR_RootConstrainSelectedInstOperands,
     /* 255106 */     // GIR_Coverage, 11674,
     /* 255106 */     GIR_EraseRootFromParent_Done,
     /* 255107 */   // Label 4924: @255107
     /* 255107 */   GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(255149), // Rule ID 11675 //
     /* 255112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 255120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 255123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 255126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255136 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1851:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_B),
     /* 255139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255145 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255147 */     GIR_RootConstrainSelectedInstOperands,
     /* 255148 */     // GIR_Coverage, 11675,
     /* 255148 */     GIR_EraseRootFromParent_Done,
     /* 255149 */   // Label 4925: @255149
     /* 255149 */   GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(255191), // Rule ID 11676 //
     /* 255154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 255162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 255168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255171 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255178 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1851:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_H),
     /* 255181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255185 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255187 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255189 */     GIR_RootConstrainSelectedInstOperands,
     /* 255190 */     // GIR_Coverage, 11676,
     /* 255190 */     GIR_EraseRootFromParent_Done,
     /* 255191 */   // Label 4926: @255191
     /* 255191 */   GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(255233), // Rule ID 11677 //
     /* 255196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 255204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 255210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255220 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1851:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_S),
     /* 255223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255225 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255227 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255229 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255231 */     GIR_RootConstrainSelectedInstOperands,
     /* 255232 */     // GIR_Coverage, 11677,
     /* 255232 */     GIR_EraseRootFromParent_Done,
     /* 255233 */   // Label 4927: @255233
     /* 255233 */   GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(255275), // Rule ID 11678 //
     /* 255238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 255246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 255252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255255 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255262 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1851:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_D),
     /* 255265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255271 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255273 */     GIR_RootConstrainSelectedInstOperands,
     /* 255274 */     // GIR_Coverage, 11678,
     /* 255274 */     GIR_EraseRootFromParent_Done,
     /* 255275 */   // Label 4928: @255275
     /* 255275 */   GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(255317), // Rule ID 11679 //
     /* 255280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 255288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 255291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 255294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255304 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2047:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_B),
     /* 255307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255313 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255315 */     GIR_RootConstrainSelectedInstOperands,
     /* 255316 */     // GIR_Coverage, 11679,
     /* 255316 */     GIR_EraseRootFromParent_Done,
     /* 255317 */   // Label 4929: @255317
     /* 255317 */   GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(255359), // Rule ID 11680 //
     /* 255322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 255330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 255336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255339 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255346 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2047:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_H),
     /* 255349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255351 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255353 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255355 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255357 */     GIR_RootConstrainSelectedInstOperands,
     /* 255358 */     // GIR_Coverage, 11680,
     /* 255358 */     GIR_EraseRootFromParent_Done,
     /* 255359 */   // Label 4930: @255359
     /* 255359 */   GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(255401), // Rule ID 11681 //
     /* 255364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 255372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 255378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255381 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255388 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2047:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_S),
     /* 255391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255395 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255397 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255399 */     GIR_RootConstrainSelectedInstOperands,
     /* 255400 */     // GIR_Coverage, 11681,
     /* 255400 */     GIR_EraseRootFromParent_Done,
     /* 255401 */   // Label 4931: @255401
     /* 255401 */   GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(255443), // Rule ID 11682 //
     /* 255406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 255414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255417 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 255420 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255423 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255430 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2047:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_D),
     /* 255433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255437 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255439 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255441 */     GIR_RootConstrainSelectedInstOperands,
     /* 255442 */     // GIR_Coverage, 11682,
     /* 255442 */     GIR_EraseRootFromParent_Done,
     /* 255443 */   // Label 4932: @255443
     /* 255443 */   GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(255485), // Rule ID 11683 //
     /* 255448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 255456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 255459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 255462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255465 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255472 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1838:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_B),
     /* 255475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255481 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255483 */     GIR_RootConstrainSelectedInstOperands,
     /* 255484 */     // GIR_Coverage, 11683,
     /* 255484 */     GIR_EraseRootFromParent_Done,
     /* 255485 */   // Label 4933: @255485
     /* 255485 */   GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(255527), // Rule ID 11684 //
     /* 255490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 255498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 255504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255507 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255514 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1838:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_H),
     /* 255517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255519 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255521 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255523 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255525 */     GIR_RootConstrainSelectedInstOperands,
     /* 255526 */     // GIR_Coverage, 11684,
     /* 255526 */     GIR_EraseRootFromParent_Done,
     /* 255527 */   // Label 4934: @255527
     /* 255527 */   GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(255569), // Rule ID 11685 //
     /* 255532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 255540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 255546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255556 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1838:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_S),
     /* 255559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255563 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255565 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255567 */     GIR_RootConstrainSelectedInstOperands,
     /* 255568 */     // GIR_Coverage, 11685,
     /* 255568 */     GIR_EraseRootFromParent_Done,
     /* 255569 */   // Label 4935: @255569
     /* 255569 */   GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(255611), // Rule ID 11686 //
     /* 255574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 255582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 255588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255591 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255598 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1838:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_D),
     /* 255601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255607 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255609 */     GIR_RootConstrainSelectedInstOperands,
     /* 255610 */     // GIR_Coverage, 11686,
     /* 255610 */     GIR_EraseRootFromParent_Done,
     /* 255611 */   // Label 4936: @255611
     /* 255611 */   GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(255653), // Rule ID 11687 //
     /* 255616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 255624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 255627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 255630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255633 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255640 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2040:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_B),
     /* 255643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255647 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255649 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255651 */     GIR_RootConstrainSelectedInstOperands,
     /* 255652 */     // GIR_Coverage, 11687,
     /* 255652 */     GIR_EraseRootFromParent_Done,
     /* 255653 */   // Label 4937: @255653
     /* 255653 */   GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(255695), // Rule ID 11688 //
     /* 255658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 255666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 255672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255675 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255682 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2040:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_H),
     /* 255685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255689 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255691 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255693 */     GIR_RootConstrainSelectedInstOperands,
     /* 255694 */     // GIR_Coverage, 11688,
     /* 255694 */     GIR_EraseRootFromParent_Done,
     /* 255695 */   // Label 4938: @255695
     /* 255695 */   GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(255737), // Rule ID 11689 //
     /* 255700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 255708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 255714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255717 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255724 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2040:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_S),
     /* 255727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255731 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255733 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255735 */     GIR_RootConstrainSelectedInstOperands,
     /* 255736 */     // GIR_Coverage, 11689,
     /* 255736 */     GIR_EraseRootFromParent_Done,
     /* 255737 */   // Label 4939: @255737
     /* 255737 */   GIM_Try, /*On fail goto*//*Label 4940*/ GIMT_Encode4(255779), // Rule ID 11690 //
     /* 255742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 255750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 255756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255766 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2040:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_D),
     /* 255769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 255771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255775 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255777 */     GIR_RootConstrainSelectedInstOperands,
     /* 255778 */     // GIR_Coverage, 11690,
     /* 255778 */     GIR_EraseRootFromParent_Done,
     /* 255779 */   // Label 4940: @255779
     /* 255779 */   GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(255821), // Rule ID 11865 //
     /* 255784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 255792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 255795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 255798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255808 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1940:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_B),
     /* 255811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 255813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255815 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255817 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255819 */     GIR_RootConstrainSelectedInstOperands,
     /* 255820 */     // GIR_Coverage, 11865,
     /* 255820 */     GIR_EraseRootFromParent_Done,
     /* 255821 */   // Label 4941: @255821
     /* 255821 */   GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(255863), // Rule ID 11867 //
     /* 255826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 255834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 255840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 255843 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 255846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255850 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1940:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 255850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_H),
     /* 255853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 255855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255857 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255859 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255861 */     GIR_RootConstrainSelectedInstOperands,
     /* 255862 */     // GIR_Coverage, 11867,
     /* 255862 */     GIR_EraseRootFromParent_Done,
     /* 255863 */   // Label 4942: @255863
     /* 255863 */   GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(255905), // Rule ID 11869 //
     /* 255868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 255876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 255879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 255882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 255885 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 255888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255892 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1940:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 255892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_S),
     /* 255895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 255897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255899 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255901 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255903 */     GIR_RootConstrainSelectedInstOperands,
     /* 255904 */     // GIR_Coverage, 11869,
     /* 255904 */     GIR_EraseRootFromParent_Done,
     /* 255905 */   // Label 4943: @255905
     /* 255905 */   GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(255947), // Rule ID 11871 //
     /* 255910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 255918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 255921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 255924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 255927 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 255930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255934 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1940:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 255934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_D),
     /* 255937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 255939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255943 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255945 */     GIR_RootConstrainSelectedInstOperands,
     /* 255946 */     // GIR_Coverage, 11871,
     /* 255946 */     GIR_EraseRootFromParent_Done,
     /* 255947 */   // Label 4944: @255947
     /* 255947 */   GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(255989), // Rule ID 11873 //
     /* 255952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 255960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 255963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 255966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 255969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 255972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 255976 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1692:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 255976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_H),
     /* 255979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 255981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 255983 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 255985 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 255987 */     GIR_RootConstrainSelectedInstOperands,
     /* 255988 */     // GIR_Coverage, 11873,
     /* 255988 */     GIR_EraseRootFromParent_Done,
     /* 255989 */   // Label 4945: @255989
     /* 255989 */   GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(256031), // Rule ID 11874 //
     /* 255994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 255997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 256002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256011 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256018 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1692:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_S),
     /* 256021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256025 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256027 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256029 */     GIR_RootConstrainSelectedInstOperands,
     /* 256030 */     // GIR_Coverage, 11874,
     /* 256030 */     GIR_EraseRootFromParent_Done,
     /* 256031 */   // Label 4946: @256031
     /* 256031 */   GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(256073), // Rule ID 11875 //
     /* 256036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 256044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256053 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256060 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1692:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_D),
     /* 256063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256069 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256071 */     GIR_RootConstrainSelectedInstOperands,
     /* 256072 */     // GIR_Coverage, 11875,
     /* 256072 */     GIR_EraseRootFromParent_Done,
     /* 256073 */   // Label 4947: @256073
     /* 256073 */   GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(256115), // Rule ID 11876 //
     /* 256078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 256086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 256095 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 256098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256102 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1941:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 256102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_H),
     /* 256105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256111 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256113 */     GIR_RootConstrainSelectedInstOperands,
     /* 256114 */     // GIR_Coverage, 11876,
     /* 256114 */     GIR_EraseRootFromParent_Done,
     /* 256115 */   // Label 4948: @256115
     /* 256115 */   GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(256157), // Rule ID 11877 //
     /* 256120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 256128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256144 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1941:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_S),
     /* 256147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256149 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256151 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256153 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256155 */     GIR_RootConstrainSelectedInstOperands,
     /* 256156 */     // GIR_Coverage, 11877,
     /* 256156 */     GIR_EraseRootFromParent_Done,
     /* 256157 */   // Label 4949: @256157
     /* 256157 */   GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(256199), // Rule ID 11878 //
     /* 256162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 256170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256179 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256186 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1941:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_D),
     /* 256189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256191 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256193 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256195 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256197 */     GIR_RootConstrainSelectedInstOperands,
     /* 256198 */     // GIR_Coverage, 11878,
     /* 256198 */     GIR_EraseRootFromParent_Done,
     /* 256199 */   // Label 4950: @256199
     /* 256199 */   GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(256241), // Rule ID 11879 //
     /* 256204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 256212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 256221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 256224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256228 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1942:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 256228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_H),
     /* 256231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256237 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256239 */     GIR_RootConstrainSelectedInstOperands,
     /* 256240 */     // GIR_Coverage, 11879,
     /* 256240 */     GIR_EraseRootFromParent_Done,
     /* 256241 */   // Label 4951: @256241
     /* 256241 */   GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(256283), // Rule ID 11880 //
     /* 256246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 256254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256263 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256270 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1942:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_S),
     /* 256273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256279 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256281 */     GIR_RootConstrainSelectedInstOperands,
     /* 256282 */     // GIR_Coverage, 11880,
     /* 256282 */     GIR_EraseRootFromParent_Done,
     /* 256283 */   // Label 4952: @256283
     /* 256283 */   GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(256325), // Rule ID 11881 //
     /* 256288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 256296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256312 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1942:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_D),
     /* 256315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256321 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256323 */     GIR_RootConstrainSelectedInstOperands,
     /* 256324 */     // GIR_Coverage, 11881,
     /* 256324 */     GIR_EraseRootFromParent_Done,
     /* 256325 */   // Label 4953: @256325
     /* 256325 */   GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(256367), // Rule ID 11882 //
     /* 256330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
     /* 256338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256354 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1255:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_S),
     /* 256357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256361 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256363 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256365 */     GIR_RootConstrainSelectedInstOperands,
     /* 256366 */     // GIR_Coverage, 11882,
     /* 256366 */     GIR_EraseRootFromParent_Done,
     /* 256367 */   // Label 4954: @256367
     /* 256367 */   GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(256409), // Rule ID 11883 //
     /* 256372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
     /* 256380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256389 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256396 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1255:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_D),
     /* 256399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256403 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256405 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256407 */     GIR_RootConstrainSelectedInstOperands,
     /* 256408 */     // GIR_Coverage, 11883,
     /* 256408 */     GIR_EraseRootFromParent_Done,
     /* 256409 */   // Label 4955: @256409
     /* 256409 */   GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(256451), // Rule ID 11884 //
     /* 256414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
     /* 256422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256431 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256438 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1704:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SBCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_S),
     /* 256441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256445 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256447 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256449 */     GIR_RootConstrainSelectedInstOperands,
     /* 256450 */     // GIR_Coverage, 11884,
     /* 256450 */     GIR_EraseRootFromParent_Done,
     /* 256451 */   // Label 4956: @256451
     /* 256451 */   GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(256493), // Rule ID 11885 //
     /* 256456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
     /* 256464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256473 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256480 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1704:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SBCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_D),
     /* 256483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256487 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256489 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256491 */     GIR_RootConstrainSelectedInstOperands,
     /* 256492 */     // GIR_Coverage, 11885,
     /* 256492 */     GIR_EraseRootFromParent_Done,
     /* 256493 */   // Label 4957: @256493
     /* 256493 */   GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(256535), // Rule ID 11886 //
     /* 256498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
     /* 256506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256515 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256522 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1705:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SBCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_S),
     /* 256525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256527 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256529 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256531 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256533 */     GIR_RootConstrainSelectedInstOperands,
     /* 256534 */     // GIR_Coverage, 11886,
     /* 256534 */     GIR_EraseRootFromParent_Done,
     /* 256535 */   // Label 4958: @256535
     /* 256535 */   GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(256577), // Rule ID 11887 //
     /* 256540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
     /* 256548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256564 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1705:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SBCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_D),
     /* 256567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 256569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256573 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256575 */     GIR_RootConstrainSelectedInstOperands,
     /* 256576 */     // GIR_Coverage, 11887,
     /* 256576 */     GIR_EraseRootFromParent_Done,
     /* 256577 */   // Label 4959: @256577
     /* 256577 */   GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(256619), // Rule ID 11942 //
     /* 256582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 256590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 256593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 256596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256599 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256606 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1673:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (RADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_B),
     /* 256609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256613 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256615 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256617 */     GIR_RootConstrainSelectedInstOperands,
     /* 256618 */     // GIR_Coverage, 11942,
     /* 256618 */     GIR_EraseRootFromParent_Done,
     /* 256619 */   // Label 4960: @256619
     /* 256619 */   GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(256661), // Rule ID 11943 //
     /* 256624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 256632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256641 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256648 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1673:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (RADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_H),
     /* 256651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256655 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256657 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256659 */     GIR_RootConstrainSelectedInstOperands,
     /* 256660 */     // GIR_Coverage, 11943,
     /* 256660 */     GIR_EraseRootFromParent_Done,
     /* 256661 */   // Label 4961: @256661
     /* 256661 */   GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(256703), // Rule ID 11944 //
     /* 256666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 256674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256683 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256690 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1673:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (RADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_S),
     /* 256693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256697 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256699 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256701 */     GIR_RootConstrainSelectedInstOperands,
     /* 256702 */     // GIR_Coverage, 11944,
     /* 256702 */     GIR_EraseRootFromParent_Done,
     /* 256703 */   // Label 4962: @256703
     /* 256703 */   GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(256745), // Rule ID 11945 //
     /* 256708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 256716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 256719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 256722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256732 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1914:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_B),
     /* 256735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256739 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256741 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256743 */     GIR_RootConstrainSelectedInstOperands,
     /* 256744 */     // GIR_Coverage, 11945,
     /* 256744 */     GIR_EraseRootFromParent_Done,
     /* 256745 */   // Label 4963: @256745
     /* 256745 */   GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(256787), // Rule ID 11946 //
     /* 256750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 256758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256774 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1914:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_H),
     /* 256777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256779 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256781 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256783 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256785 */     GIR_RootConstrainSelectedInstOperands,
     /* 256786 */     // GIR_Coverage, 11946,
     /* 256786 */     GIR_EraseRootFromParent_Done,
     /* 256787 */   // Label 4964: @256787
     /* 256787 */   GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(256829), // Rule ID 11947 //
     /* 256792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 256800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256809 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256816 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1914:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_S),
     /* 256819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256823 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256825 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256827 */     GIR_RootConstrainSelectedInstOperands,
     /* 256828 */     // GIR_Coverage, 11947,
     /* 256828 */     GIR_EraseRootFromParent_Done,
     /* 256829 */   // Label 4965: @256829
     /* 256829 */   GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(256871), // Rule ID 11948 //
     /* 256834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 256842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 256845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 256848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256851 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256858 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1689:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (RSUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_B),
     /* 256861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256865 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256867 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256869 */     GIR_RootConstrainSelectedInstOperands,
     /* 256870 */     // GIR_Coverage, 11948,
     /* 256870 */     GIR_EraseRootFromParent_Done,
     /* 256871 */   // Label 4966: @256871
     /* 256871 */   GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(256913), // Rule ID 11949 //
     /* 256876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 256884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256893 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256900 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1689:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (RSUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_H),
     /* 256903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256909 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256911 */     GIR_RootConstrainSelectedInstOperands,
     /* 256912 */     // GIR_Coverage, 11949,
     /* 256912 */     GIR_EraseRootFromParent_Done,
     /* 256913 */   // Label 4967: @256913
     /* 256913 */   GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(256955), // Rule ID 11950 //
     /* 256918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 256926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 256935 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 256938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256942 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1689:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (RSUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 256942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_S),
     /* 256945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256947 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256949 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256951 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256953 */     GIR_RootConstrainSelectedInstOperands,
     /* 256954 */     // GIR_Coverage, 11950,
     /* 256954 */     GIR_EraseRootFromParent_Done,
     /* 256955 */   // Label 4968: @256955
     /* 256955 */   GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(257000), // Rule ID 11963 //
     /* 256960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 256963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
     /* 256968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 256971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 256974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 256977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 256980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 256984 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1624:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (NMATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 256984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_B),
     /* 256987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 256989 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256993 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256995 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 256998 */     GIR_RootConstrainSelectedInstOperands,
     /* 256999 */     // GIR_Coverage, 11963,
     /* 256999 */     GIR_EraseRootFromParent_Done,
     /* 257000 */   // Label 4969: @257000
     /* 257000 */   GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(257045), // Rule ID 11964 //
     /* 257005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 257008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
     /* 257013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 257016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257022 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 257029 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1624:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (NMATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 257029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_H),
     /* 257032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257036 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257038 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257040 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 257043 */     GIR_RootConstrainSelectedInstOperands,
     /* 257044 */     // GIR_Coverage, 11964,
     /* 257044 */     GIR_EraseRootFromParent_Done,
     /* 257045 */   // Label 4970: @257045
     /* 257045 */   GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(257087), // Rule ID 11965 //
     /* 257050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 257058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 257061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 257064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 257067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 257070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257074 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1364:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EORTB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 257074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_B),
     /* 257077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257079 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257081 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257083 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257085 */     GIR_RootConstrainSelectedInstOperands,
     /* 257086 */     // GIR_Coverage, 11965,
     /* 257086 */     GIR_EraseRootFromParent_Done,
     /* 257087 */   // Label 4971: @257087
     /* 257087 */   GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(257129), // Rule ID 11966 //
     /* 257092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 257100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 257106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257116 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1364:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EORTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 257116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_H),
     /* 257119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257125 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257127 */     GIR_RootConstrainSelectedInstOperands,
     /* 257128 */     // GIR_Coverage, 11966,
     /* 257128 */     GIR_EraseRootFromParent_Done,
     /* 257129 */   // Label 4972: @257129
     /* 257129 */   GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(257171), // Rule ID 11967 //
     /* 257134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 257142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257151 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257158 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1364:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EORTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 257158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_S),
     /* 257161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257167 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257169 */     GIR_RootConstrainSelectedInstOperands,
     /* 257170 */     // GIR_Coverage, 11967,
     /* 257170 */     GIR_EraseRootFromParent_Done,
     /* 257171 */   // Label 4973: @257171
     /* 257171 */   GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(257213), // Rule ID 11968 //
     /* 257176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257179 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 257184 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257187 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 257190 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257193 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257200 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1364:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EORTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 257200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_D),
     /* 257203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257207 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257209 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257211 */     GIR_RootConstrainSelectedInstOperands,
     /* 257212 */     // GIR_Coverage, 11968,
     /* 257212 */     GIR_EraseRootFromParent_Done,
     /* 257213 */   // Label 4974: @257213
     /* 257213 */   GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(257255), // Rule ID 11984 //
     /* 257218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 257226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257235 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257242 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1447:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMAXNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_H),
     /* 257245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257247 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257249 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257251 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257253 */     GIR_RootConstrainSelectedInstOperands,
     /* 257254 */     // GIR_Coverage, 11984,
     /* 257254 */     GIR_EraseRootFromParent_Done,
     /* 257255 */   // Label 4975: @257255
     /* 257255 */   GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(257297), // Rule ID 11985 //
     /* 257260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 257268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257277 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257284 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1447:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMAXNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_S),
     /* 257287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257289 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257291 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257293 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257295 */     GIR_RootConstrainSelectedInstOperands,
     /* 257296 */     // GIR_Coverage, 11985,
     /* 257296 */     GIR_EraseRootFromParent_Done,
     /* 257297 */   // Label 4976: @257297
     /* 257297 */   GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(257339), // Rule ID 11986 //
     /* 257302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257305 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 257310 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257313 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257316 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257319 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257326 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1447:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMAXNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_D),
     /* 257329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257335 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257337 */     GIR_RootConstrainSelectedInstOperands,
     /* 257338 */     // GIR_Coverage, 11986,
     /* 257338 */     GIR_EraseRootFromParent_Done,
     /* 257339 */   // Label 4977: @257339
     /* 257339 */   GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(257381), // Rule ID 11987 //
     /* 257344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 257352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257361 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257368 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1465:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMINNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_H),
     /* 257371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257373 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257375 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257377 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257379 */     GIR_RootConstrainSelectedInstOperands,
     /* 257380 */     // GIR_Coverage, 11987,
     /* 257380 */     GIR_EraseRootFromParent_Done,
     /* 257381 */   // Label 4978: @257381
     /* 257381 */   GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(257423), // Rule ID 11988 //
     /* 257386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 257394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257403 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257410 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1465:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMINNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_S),
     /* 257413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257417 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257419 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257421 */     GIR_RootConstrainSelectedInstOperands,
     /* 257422 */     // GIR_Coverage, 11988,
     /* 257422 */     GIR_EraseRootFromParent_Done,
     /* 257423 */   // Label 4979: @257423
     /* 257423 */   GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(257465), // Rule ID 11989 //
     /* 257428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 257436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257445 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257452 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1465:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMINNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_D),
     /* 257455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257461 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257463 */     GIR_RootConstrainSelectedInstOperands,
     /* 257464 */     // GIR_Coverage, 11989,
     /* 257464 */     GIR_EraseRootFromParent_Done,
     /* 257465 */   // Label 4980: @257465
     /* 257465 */   GIM_Try, /*On fail goto*//*Label 4981*/ GIMT_Encode4(257507), // Rule ID 11990 //
     /* 257470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 257478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257487 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257494 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1450:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMAXP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_H),
     /* 257497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257499 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257501 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257503 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257505 */     GIR_RootConstrainSelectedInstOperands,
     /* 257506 */     // GIR_Coverage, 11990,
     /* 257506 */     GIR_EraseRootFromParent_Done,
     /* 257507 */   // Label 4981: @257507
     /* 257507 */   GIM_Try, /*On fail goto*//*Label 4982*/ GIMT_Encode4(257549), // Rule ID 11991 //
     /* 257512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 257520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257529 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257536 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1450:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMAXP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_S),
     /* 257539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257541 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257543 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257545 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257547 */     GIR_RootConstrainSelectedInstOperands,
     /* 257548 */     // GIR_Coverage, 11991,
     /* 257548 */     GIR_EraseRootFromParent_Done,
     /* 257549 */   // Label 4982: @257549
     /* 257549 */   GIM_Try, /*On fail goto*//*Label 4983*/ GIMT_Encode4(257591), // Rule ID 11992 //
     /* 257554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257557 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 257562 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257565 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257568 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257571 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257578 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1450:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMAXP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_D),
     /* 257581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257583 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257585 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257587 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257589 */     GIR_RootConstrainSelectedInstOperands,
     /* 257590 */     // GIR_Coverage, 11992,
     /* 257590 */     GIR_EraseRootFromParent_Done,
     /* 257591 */   // Label 4983: @257591
     /* 257591 */   GIM_Try, /*On fail goto*//*Label 4984*/ GIMT_Encode4(257633), // Rule ID 11993 //
     /* 257596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 257604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257613 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257620 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1468:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMINP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_H),
     /* 257623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257629 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257631 */     GIR_RootConstrainSelectedInstOperands,
     /* 257632 */     // GIR_Coverage, 11993,
     /* 257632 */     GIR_EraseRootFromParent_Done,
     /* 257633 */   // Label 4984: @257633
     /* 257633 */   GIM_Try, /*On fail goto*//*Label 4985*/ GIMT_Encode4(257675), // Rule ID 11994 //
     /* 257638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 257646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257655 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257662 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1468:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMINP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_S),
     /* 257665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257667 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257669 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257671 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257673 */     GIR_RootConstrainSelectedInstOperands,
     /* 257674 */     // GIR_Coverage, 11994,
     /* 257674 */     GIR_EraseRootFromParent_Done,
     /* 257675 */   // Label 4985: @257675
     /* 257675 */   GIM_Try, /*On fail goto*//*Label 4986*/ GIMT_Encode4(257717), // Rule ID 11995 //
     /* 257680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 257688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257697 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257704 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1468:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMINP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_D),
     /* 257707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257713 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257715 */     GIR_RootConstrainSelectedInstOperands,
     /* 257716 */     // GIR_Coverage, 11995,
     /* 257716 */     GIR_EraseRootFromParent_Done,
     /* 257717 */   // Label 4986: @257717
     /* 257717 */   GIM_Try, /*On fail goto*//*Label 4987*/ GIMT_Encode4(257759), // Rule ID 12000 //
     /* 257722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb),
     /* 257730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257739 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257746 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1474:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLALB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZ_SHH),
     /* 257749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 257751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257753 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257755 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257757 */     GIR_RootConstrainSelectedInstOperands,
     /* 257758 */     // GIR_Coverage, 12000,
     /* 257758 */     GIR_EraseRootFromParent_Done,
     /* 257759 */   // Label 4987: @257759
     /* 257759 */   GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(257801), // Rule ID 12001 //
     /* 257764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt),
     /* 257772 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257775 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257778 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257781 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257788 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1476:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLALT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZ_SHH),
     /* 257791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 257793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257797 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257799 */     GIR_RootConstrainSelectedInstOperands,
     /* 257800 */     // GIR_Coverage, 12001,
     /* 257800 */     GIR_EraseRootFromParent_Done,
     /* 257801 */   // Label 4988: @257801
     /* 257801 */   GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(257843), // Rule ID 12002 //
     /* 257806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb),
     /* 257814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257823 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257830 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1481:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLSLB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZ_SHH),
     /* 257833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 257835 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257837 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257839 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257841 */     GIR_RootConstrainSelectedInstOperands,
     /* 257842 */     // GIR_Coverage, 12002,
     /* 257842 */     GIR_EraseRootFromParent_Done,
     /* 257843 */   // Label 4989: @257843
     /* 257843 */   GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(257885), // Rule ID 12003 //
     /* 257848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt),
     /* 257856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257865 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257872 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1483:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLSLT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZ_SHH),
     /* 257875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 257877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257879 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257881 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257883 */     GIR_RootConstrainSelectedInstOperands,
     /* 257884 */     // GIR_Coverage, 12003,
     /* 257884 */     GIR_EraseRootFromParent_Done,
     /* 257885 */   // Label 4990: @257885
     /* 257885 */   GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(257927), // Rule ID 12016 //
     /* 257890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 257898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 257901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 257904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 257907 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 257910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257914 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1281:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 257914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 257917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257919 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257921 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257923 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257925 */     GIR_RootConstrainSelectedInstOperands,
     /* 257926 */     // GIR_Coverage, 12016,
     /* 257926 */     GIR_EraseRootFromParent_Done,
     /* 257927 */   // Label 4991: @257927
     /* 257927 */   GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(257969), // Rule ID 12018 //
     /* 257932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 257940 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257943 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 257946 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257949 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257956 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1281:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 257956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 257959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257965 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257967 */     GIR_RootConstrainSelectedInstOperands,
     /* 257968 */     // GIR_Coverage, 12018,
     /* 257968 */     GIR_EraseRootFromParent_Done,
     /* 257969 */   // Label 4992: @257969
     /* 257969 */   GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(258011), // Rule ID 12020 //
     /* 257974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 257982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257991 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257998 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1281:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 257998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 258001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258007 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258009 */     GIR_RootConstrainSelectedInstOperands,
     /* 258010 */     // GIR_Coverage, 12020,
     /* 258010 */     GIR_EraseRootFromParent_Done,
     /* 258011 */   // Label 4993: @258011
     /* 258011 */   GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(258053), // Rule ID 12022 //
     /* 258016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 258024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258033 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258040 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1281:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 258043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258045 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258047 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258049 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258051 */     GIR_RootConstrainSelectedInstOperands,
     /* 258052 */     // GIR_Coverage, 12022,
     /* 258052 */     GIR_EraseRootFromParent_Done,
     /* 258053 */   // Label 4994: @258053
     /* 258053 */   GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(258095), // Rule ID 12282 //
     /* 258058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 258061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 258066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 258069 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 258072 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 258075 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258082 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1953:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_B),
     /* 258085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258091 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258093 */     GIR_RootConstrainSelectedInstOperands,
     /* 258094 */     // GIR_Coverage, 12282,
     /* 258094 */     GIR_EraseRootFromParent_Done,
     /* 258095 */   // Label 4995: @258095
     /* 258095 */   GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(258137), // Rule ID 12284 //
     /* 258100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 258103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 258108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258124 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1953:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_H),
     /* 258127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258131 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258133 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258135 */     GIR_RootConstrainSelectedInstOperands,
     /* 258136 */     // GIR_Coverage, 12284,
     /* 258136 */     GIR_EraseRootFromParent_Done,
     /* 258137 */   // Label 4996: @258137
     /* 258137 */   GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(258179), // Rule ID 12286 //
     /* 258142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 258145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 258150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258159 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258166 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1953:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_S),
     /* 258169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258173 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258175 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258177 */     GIR_RootConstrainSelectedInstOperands,
     /* 258178 */     // GIR_Coverage, 12286,
     /* 258178 */     GIR_EraseRootFromParent_Done,
     /* 258179 */   // Label 4997: @258179
     /* 258179 */   GIM_Try, /*On fail goto*//*Label 4998*/ GIMT_Encode4(258221), // Rule ID 12288 //
     /* 258184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 258187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 258192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258201 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258208 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1953:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_D),
     /* 258211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258215 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258217 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258219 */     GIR_RootConstrainSelectedInstOperands,
     /* 258220 */     // GIR_Coverage, 12288,
     /* 258220 */     GIR_EraseRootFromParent_Done,
     /* 258221 */   // Label 4998: @258221
     /* 258221 */   GIM_Try, /*On fail goto*//*Label 4999*/ GIMT_Encode4(258263), // Rule ID 12290 //
     /* 258226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 258229 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_x2),
     /* 258234 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258237 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258240 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258243 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258250 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1431:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDOT_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_S),
     /* 258253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258259 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258261 */     GIR_RootConstrainSelectedInstOperands,
     /* 258262 */     // GIR_Coverage, 12290,
     /* 258262 */     GIR_EraseRootFromParent_Done,
     /* 258263 */   // Label 4999: @258263
     /* 258263 */   GIM_Try, /*On fail goto*//*Label 5000*/ GIMT_Encode4(258305), // Rule ID 12292 //
     /* 258268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 258271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_x2),
     /* 258276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258285 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258292 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1969:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_HtoS),
     /* 258295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258301 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258303 */     GIR_RootConstrainSelectedInstOperands,
     /* 258304 */     // GIR_Coverage, 12292,
     /* 258304 */     GIR_EraseRootFromParent_Done,
     /* 258305 */   // Label 5000: @258305
     /* 258305 */   GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(258347), // Rule ID 12455 //
     /* 258310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 258321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 258324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 258327 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258334 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1929:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (TBXQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_B),
     /* 258337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258343 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258345 */     GIR_RootConstrainSelectedInstOperands,
     /* 258346 */     // GIR_Coverage, 12455,
     /* 258346 */     GIR_EraseRootFromParent_Done,
     /* 258347 */   // Label 5001: @258347
     /* 258347 */   GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(258389), // Rule ID 12456 //
     /* 258352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258369 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258376 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1929:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBXQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
     /* 258379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258381 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258383 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258385 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258387 */     GIR_RootConstrainSelectedInstOperands,
     /* 258388 */     // GIR_Coverage, 12456,
     /* 258388 */     GIR_EraseRootFromParent_Done,
     /* 258389 */   // Label 5002: @258389
     /* 258389 */   GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(258431), // Rule ID 12457 //
     /* 258394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258408 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258411 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258418 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1929:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBXQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
     /* 258421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258427 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258429 */     GIR_RootConstrainSelectedInstOperands,
     /* 258430 */     // GIR_Coverage, 12457,
     /* 258430 */     GIR_EraseRootFromParent_Done,
     /* 258431 */   // Label 5003: @258431
     /* 258431 */   GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(258473), // Rule ID 12458 //
     /* 258436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258439 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258444 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258450 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258453 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258460 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1929:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBXQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
     /* 258463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258465 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258467 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258469 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258471 */     GIR_RootConstrainSelectedInstOperands,
     /* 258472 */     // GIR_Coverage, 12458,
     /* 258472 */     GIR_EraseRootFromParent_Done,
     /* 258473 */   // Label 5004: @258473
     /* 258473 */   GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(258515), // Rule ID 12459 //
     /* 258478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258495 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258502 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1929:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBXQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
     /* 258505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258509 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258511 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258513 */     GIR_RootConstrainSelectedInstOperands,
     /* 258514 */     // GIR_Coverage, 12459,
     /* 258514 */     GIR_EraseRootFromParent_Done,
     /* 258515 */   // Label 5005: @258515
     /* 258515 */   GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(258557), // Rule ID 12460 //
     /* 258520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258537 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258544 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1929:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBXQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
     /* 258547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258549 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258551 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258553 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258555 */     GIR_RootConstrainSelectedInstOperands,
     /* 258556 */     // GIR_Coverage, 12460,
     /* 258556 */     GIR_EraseRootFromParent_Done,
     /* 258557 */   // Label 5006: @258557
     /* 258557 */   GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(258599), // Rule ID 12461 //
     /* 258562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 258565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 258570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258586 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1929:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBXQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
     /* 258589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258595 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258597 */     GIR_RootConstrainSelectedInstOperands,
     /* 258598 */     // GIR_Coverage, 12461,
     /* 258598 */     GIR_EraseRootFromParent_Done,
     /* 258599 */   // Label 5007: @258599
     /* 258599 */   GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(258641), // Rule ID 12806 //
     /* 258604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 258612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 258618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258621 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258628 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1381:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMIN_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_H),
     /* 258631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258635 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258637 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258639 */     GIR_RootConstrainSelectedInstOperands,
     /* 258640 */     // GIR_Coverage, 12806,
     /* 258640 */     GIR_EraseRootFromParent_Done,
     /* 258641 */   // Label 5008: @258641
     /* 258641 */   GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(258683), // Rule ID 12807 //
     /* 258646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 258654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258663 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258670 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1381:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMIN_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 258670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_S),
     /* 258673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258675 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258677 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258679 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258681 */     GIR_RootConstrainSelectedInstOperands,
     /* 258682 */     // GIR_Coverage, 12807,
     /* 258682 */     GIR_EraseRootFromParent_Done,
     /* 258683 */   // Label 5009: @258683
     /* 258683 */   GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(258725), // Rule ID 12808 //
     /* 258688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 258696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258705 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258712 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1381:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMIN_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 258712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_D),
     /* 258715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258721 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258723 */     GIR_RootConstrainSelectedInstOperands,
     /* 258724 */     // GIR_Coverage, 12808,
     /* 258724 */     GIR_EraseRootFromParent_Done,
     /* 258725 */   // Label 5010: @258725
     /* 258725 */   GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(258767), // Rule ID 12809 //
     /* 258730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 258738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 258744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258747 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258754 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1379:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMAX_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_H),
     /* 258757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258759 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258761 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258763 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258765 */     GIR_RootConstrainSelectedInstOperands,
     /* 258766 */     // GIR_Coverage, 12809,
     /* 258766 */     GIR_EraseRootFromParent_Done,
     /* 258767 */   // Label 5011: @258767
     /* 258767 */   GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(258809), // Rule ID 12810 //
     /* 258772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 258780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258789 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258796 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1379:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMAX_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 258796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_S),
     /* 258799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258805 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258807 */     GIR_RootConstrainSelectedInstOperands,
     /* 258808 */     // GIR_Coverage, 12810,
     /* 258808 */     GIR_EraseRootFromParent_Done,
     /* 258809 */   // Label 5012: @258809
     /* 258809 */   GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(258851), // Rule ID 12811 //
     /* 258814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 258822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258831 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258838 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1379:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMAX_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 258838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_D),
     /* 258841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258847 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258849 */     GIR_RootConstrainSelectedInstOperands,
     /* 258850 */     // GIR_Coverage, 12811,
     /* 258850 */     GIR_EraseRootFromParent_Done,
     /* 258851 */   // Label 5013: @258851
     /* 258851 */   GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(258893), // Rule ID 12812 //
     /* 258856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 258864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258867 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 258870 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258873 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258880 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1380:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 258883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258885 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258887 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258889 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258891 */     GIR_RootConstrainSelectedInstOperands,
     /* 258892 */     // GIR_Coverage, 12812,
     /* 258892 */     GIR_EraseRootFromParent_Done,
     /* 258893 */   // Label 5014: @258893
     /* 258893 */   GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(258935), // Rule ID 12815 //
     /* 258898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 258906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 258909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258912 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 258915 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 258918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258922 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1380:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 258922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 258925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258929 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258931 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258933 */     GIR_RootConstrainSelectedInstOperands,
     /* 258934 */     // GIR_Coverage, 12815,
     /* 258934 */     GIR_EraseRootFromParent_Done,
     /* 258935 */   // Label 5015: @258935
     /* 258935 */   GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(258977), // Rule ID 12818 //
     /* 258940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 258948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 258951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 258957 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 258960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258964 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1380:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 258964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 258967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258969 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258971 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258973 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258975 */     GIR_RootConstrainSelectedInstOperands,
     /* 258976 */     // GIR_Coverage, 12818,
     /* 258976 */     GIR_EraseRootFromParent_Done,
     /* 258977 */   // Label 5016: @258977
     /* 258977 */   GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(259019), // Rule ID 12821 //
     /* 258982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 258985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 258990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258999 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259006 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1380:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMAX_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 259006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_S_UNDEF),
     /* 259009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259013 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259015 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259017 */     GIR_RootConstrainSelectedInstOperands,
     /* 259018 */     // GIR_Coverage, 12821,
     /* 259018 */     GIR_EraseRootFromParent_Done,
     /* 259019 */   // Label 5017: @259019
     /* 259019 */   GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(259061), // Rule ID 12824 //
     /* 259024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 259032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 259035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 259038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 259041 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 259044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259048 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1380:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FAMAX_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 259048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_S_UNDEF),
     /* 259051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259057 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259059 */     GIR_RootConstrainSelectedInstOperands,
     /* 259060 */     // GIR_Coverage, 12824,
     /* 259060 */     GIR_EraseRootFromParent_Done,
     /* 259061 */   // Label 5018: @259061
     /* 259061 */   GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(259103), // Rule ID 12827 //
     /* 259066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 259074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 259080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259083 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259090 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1380:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMAX_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 259090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_D_UNDEF),
     /* 259093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259099 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259101 */     GIR_RootConstrainSelectedInstOperands,
     /* 259102 */     // GIR_Coverage, 12827,
     /* 259102 */     GIR_EraseRootFromParent_Done,
     /* 259103 */   // Label 5019: @259103
     /* 259103 */   GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(259145), // Rule ID 12830 //
     /* 259108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 259122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 259125 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259132 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1382:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 259132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 259135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259141 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259143 */     GIR_RootConstrainSelectedInstOperands,
     /* 259144 */     // GIR_Coverage, 12830,
     /* 259144 */     GIR_EraseRootFromParent_Done,
     /* 259145 */   // Label 5020: @259145
     /* 259145 */   GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(259187), // Rule ID 12833 //
     /* 259150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 259161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 259164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 259167 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 259170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259174 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1382:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 259174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 259177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259179 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259181 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259183 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259185 */     GIR_RootConstrainSelectedInstOperands,
     /* 259186 */     // GIR_Coverage, 12833,
     /* 259186 */     GIR_EraseRootFromParent_Done,
     /* 259187 */   // Label 5021: @259187
     /* 259187 */   GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(259229), // Rule ID 12836 //
     /* 259192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 259203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 259206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 259209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 259212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259216 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1382:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 259216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 259219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259225 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259227 */     GIR_RootConstrainSelectedInstOperands,
     /* 259228 */     // GIR_Coverage, 12836,
     /* 259228 */     GIR_EraseRootFromParent_Done,
     /* 259229 */   // Label 5022: @259229
     /* 259229 */   GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(259271), // Rule ID 12839 //
     /* 259234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 259248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259251 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259258 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1382:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMIN_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 259258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_S_UNDEF),
     /* 259261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259265 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259267 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259269 */     GIR_RootConstrainSelectedInstOperands,
     /* 259270 */     // GIR_Coverage, 12839,
     /* 259270 */     GIR_EraseRootFromParent_Done,
     /* 259271 */   // Label 5023: @259271
     /* 259271 */   GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(259313), // Rule ID 12842 //
     /* 259276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 259287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 259290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 259293 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 259296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259300 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1382:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FAMIN_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 259300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_S_UNDEF),
     /* 259303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259305 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259307 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259309 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259311 */     GIR_RootConstrainSelectedInstOperands,
     /* 259312 */     // GIR_Coverage, 12842,
     /* 259312 */     GIR_EraseRootFromParent_Done,
     /* 259313 */   // Label 5024: @259313
     /* 259313 */   GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(259355), // Rule ID 12845 //
     /* 259318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 259321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 259326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 259332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259342 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1382:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMIN_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 259342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_D_UNDEF),
     /* 259345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259349 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259351 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259353 */     GIR_RootConstrainSelectedInstOperands,
     /* 259354 */     // GIR_Coverage, 12845,
     /* 259354 */     GIR_EraseRootFromParent_Done,
     /* 259355 */   // Label 5025: @259355
     /* 259355 */   GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(259498), // Rule ID 5636 //
     /* 259360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 259368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 259371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 259374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 259377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259381 */     // MIs[0] idx
     /* 259381 */     // No operand predicates
     /* 259381 */     // (intrinsic_wo_chain:{ *:[v16i8] } 778:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259381 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 259384 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259388 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259393 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 259395 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 259398 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259402 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259407 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 259410 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 259414 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 259417 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259422 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259427 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259432 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259435 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259439 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259444 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259446 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259449 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259453 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259458 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 259461 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 259465 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 259468 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259473 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259478 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 259486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259488 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 259491 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 259494 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259496 */     GIR_RootConstrainSelectedInstOperands,
     /* 259497 */     // GIR_Coverage, 5636,
     /* 259497 */     GIR_EraseRootFromParent_Done,
     /* 259498 */   // Label 5026: @259498
     /* 259498 */   GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(259589), // Rule ID 5637 //
     /* 259503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 259511 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 259514 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 259517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 259520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259524 */     // MIs[0] idx
     /* 259524 */     // No operand predicates
     /* 259524 */     // (intrinsic_wo_chain:{ *:[v16i8] } 779:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259524 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259527 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259531 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259536 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259538 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259541 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259545 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259550 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 259553 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 259557 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 259560 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259565 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259570 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 259578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259580 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 259583 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 259585 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259587 */     GIR_RootConstrainSelectedInstOperands,
     /* 259588 */     // GIR_Coverage, 5637,
     /* 259588 */     GIR_EraseRootFromParent_Done,
     /* 259589 */   // Label 5027: @259589
     /* 259589 */   GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(259680), // Rule ID 5638 //
     /* 259594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 259602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 259605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 259608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 259611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259615 */     // MIs[0] idx
     /* 259615 */     // No operand predicates
     /* 259615 */     // (intrinsic_wo_chain:{ *:[v16i8] } 778:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259615 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259618 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259622 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259627 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259629 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259632 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259636 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259641 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 259644 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 259648 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 259651 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259656 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259661 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 259669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 259673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 259676 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259678 */     GIR_RootConstrainSelectedInstOperands,
     /* 259679 */     // GIR_Coverage, 5638,
     /* 259679 */     GIR_EraseRootFromParent_Done,
     /* 259680 */   // Label 5028: @259680
     /* 259680 */   GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(259719), // Rule ID 5639 //
     /* 259685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 259693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 259696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 259699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 259702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259706 */     // MIs[0] idx
     /* 259706 */     // No operand predicates
     /* 259706 */     // (intrinsic_wo_chain:{ *:[v16i8] } 779:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 259709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 259713 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 259715 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259717 */     GIR_RootConstrainSelectedInstOperands,
     /* 259718 */     // GIR_Coverage, 5639,
     /* 259718 */     GIR_EraseRootFromParent_Done,
     /* 259719 */   // Label 5029: @259719
     /* 259719 */   GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(259862), // Rule ID 5640 //
     /* 259724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 259732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 259735 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 259738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 259741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259745 */     // MIs[0] idx
     /* 259745 */     // No operand predicates
     /* 259745 */     // (intrinsic_wo_chain:{ *:[v8i16] } 778:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259745 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 259748 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259752 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259757 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 259759 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 259762 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259766 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259771 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 259774 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 259778 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 259781 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259786 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259791 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259796 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259799 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259803 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259810 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259813 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259817 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259822 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 259825 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 259829 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 259832 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259837 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259842 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 259850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259852 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 259855 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 259858 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259860 */     GIR_RootConstrainSelectedInstOperands,
     /* 259861 */     // GIR_Coverage, 5640,
     /* 259861 */     GIR_EraseRootFromParent_Done,
     /* 259862 */   // Label 5030: @259862
     /* 259862 */   GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(259953), // Rule ID 5641 //
     /* 259867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 259875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 259878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 259881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 259884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259888 */     // MIs[0] idx
     /* 259888 */     // No operand predicates
     /* 259888 */     // (intrinsic_wo_chain:{ *:[v8i16] } 779:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259888 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259891 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259895 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259900 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259902 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259905 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 259909 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259914 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 259917 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 259921 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 259924 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259929 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259934 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 259939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 259942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 259944 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 259947 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 259949 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 259951 */     GIR_RootConstrainSelectedInstOperands,
     /* 259952 */     // GIR_Coverage, 5641,
     /* 259952 */     GIR_EraseRootFromParent_Done,
     /* 259953 */   // Label 5031: @259953
     /* 259953 */   GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(260044), // Rule ID 5642 //
     /* 259958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 259961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 259966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 259969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 259972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 259975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 259979 */     // MIs[0] idx
     /* 259979 */     // No operand predicates
     /* 259979 */     // (intrinsic_wo_chain:{ *:[v8i16] } 778:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 259979 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 259982 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 259986 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 259991 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 259993 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 259996 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260005 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 260008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 260012 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 260015 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260020 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260025 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260037 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 260040 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260042 */     GIR_RootConstrainSelectedInstOperands,
     /* 260043 */     // GIR_Coverage, 5642,
     /* 260043 */     GIR_EraseRootFromParent_Done,
     /* 260044 */   // Label 5032: @260044
     /* 260044 */   GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(260083), // Rule ID 5643 //
     /* 260049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 260057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 260060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 260063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 260066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260070 */     // MIs[0] idx
     /* 260070 */     // No operand predicates
     /* 260070 */     // (intrinsic_wo_chain:{ *:[v8i16] } 779:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 260070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260077 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 260079 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260081 */     GIR_RootConstrainSelectedInstOperands,
     /* 260082 */     // GIR_Coverage, 5643,
     /* 260082 */     GIR_EraseRootFromParent_Done,
     /* 260083 */   // Label 5033: @260083
     /* 260083 */   GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(260226), // Rule ID 5644 //
     /* 260088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 260096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 260099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 260102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 260105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260109 */     // MIs[0] idx
     /* 260109 */     // No operand predicates
     /* 260109 */     // (intrinsic_wo_chain:{ *:[v8f16] } 778:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 260109 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 260112 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 260116 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260121 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 260123 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 260126 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260130 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260135 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 260138 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 260142 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 260145 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260150 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260155 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260160 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 260163 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 260167 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260172 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 260174 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 260177 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260181 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260186 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 260189 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 260193 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 260196 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260201 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260206 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260216 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 260219 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 260222 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260224 */     GIR_RootConstrainSelectedInstOperands,
     /* 260225 */     // GIR_Coverage, 5644,
     /* 260225 */     GIR_EraseRootFromParent_Done,
     /* 260226 */   // Label 5034: @260226
     /* 260226 */   GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(260317), // Rule ID 5645 //
     /* 260231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260234 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 260239 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 260242 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 260245 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 260248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260252 */     // MIs[0] idx
     /* 260252 */     // No operand predicates
     /* 260252 */     // (intrinsic_wo_chain:{ *:[v8f16] } 779:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 260252 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 260255 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 260259 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260264 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 260266 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 260269 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260273 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260278 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 260281 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 260285 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 260288 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260293 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260298 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260308 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 260311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 260313 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260315 */     GIR_RootConstrainSelectedInstOperands,
     /* 260316 */     // GIR_Coverage, 5645,
     /* 260316 */     GIR_EraseRootFromParent_Done,
     /* 260317 */   // Label 5035: @260317
     /* 260317 */   GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(260408), // Rule ID 5646 //
     /* 260322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 260330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 260333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 260336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 260339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260343 */     // MIs[0] idx
     /* 260343 */     // No operand predicates
     /* 260343 */     // (intrinsic_wo_chain:{ *:[v8f16] } 778:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 260343 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 260346 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 260350 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260355 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 260357 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 260360 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260364 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260369 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 260372 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 260376 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 260379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260389 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260401 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 260404 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260406 */     GIR_RootConstrainSelectedInstOperands,
     /* 260407 */     // GIR_Coverage, 5646,
     /* 260407 */     GIR_EraseRootFromParent_Done,
     /* 260408 */   // Label 5036: @260408
     /* 260408 */   GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(260447), // Rule ID 5647 //
     /* 260413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 260421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 260424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 260427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 260430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260434 */     // MIs[0] idx
     /* 260434 */     // No operand predicates
     /* 260434 */     // (intrinsic_wo_chain:{ *:[v8f16] } 779:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 260434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 260437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260441 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 260443 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260445 */     GIR_RootConstrainSelectedInstOperands,
     /* 260446 */     // GIR_Coverage, 5647,
     /* 260446 */     GIR_EraseRootFromParent_Done,
     /* 260447 */   // Label 5037: @260447
     /* 260447 */   GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(260486), // Rule ID 5648 //
     /* 260452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti4q_laneq),
     /* 260460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 260463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 260466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 260469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260473 */     // MIs[0] idx
     /* 260473 */     // No operand predicates
     /* 260473 */     // (intrinsic_wo_chain:{ *:[v16i8] } 782:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT4_B:{ *:[v16i8] } VecListOne16b:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 260473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT4_B),
     /* 260476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260480 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 260482 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260484 */     GIR_RootConstrainSelectedInstOperands,
     /* 260485 */     // GIR_Coverage, 5648,
     /* 260485 */     GIR_EraseRootFromParent_Done,
     /* 260486 */   // Label 5038: @260486
     /* 260486 */   GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(260577), // Rule ID 5649 //
     /* 260491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 260494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti4q_lane),
     /* 260499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 260502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 260505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 260508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260512 */     // MIs[0] idx
     /* 260512 */     // No operand predicates
     /* 260512 */     // (intrinsic_wo_chain:{ *:[v16i8] } 780:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT4_B:{ *:[v16i8] } VecListOne16b:{ *:[v16i8] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 260512 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 260515 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 260519 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260524 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 260526 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 260529 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 260533 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 260538 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 260541 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 260545 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 260548 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260553 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260558 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 260563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT4_B),
     /* 260566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 260568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 260570 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 260573 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 260575 */     GIR_RootConstrainSelectedInstOperands,
     /* 260576 */     // GIR_Coverage, 5649,
     /* 260576 */     GIR_EraseRootFromParent_Done,
     /* 260577 */   // Label 5039: @260577
     /* 260577 */   GIM_Reject,
     /* 260578 */ // Label 4179: @260578
     /* 260578 */ GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(267689),
     /* 260583 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /* 260586 */   GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(260633), // Rule ID 2980 //
     /* 260591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 260599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260608 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 260611 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 260614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260618 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1613:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLA_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 260618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_B_UNDEF),
     /* 260621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260627 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260629 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260631 */     GIR_RootConstrainSelectedInstOperands,
     /* 260632 */     // GIR_Coverage, 2980,
     /* 260632 */     GIR_EraseRootFromParent_Done,
     /* 260633 */   // Label 5041: @260633
     /* 260633 */   GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(260680), // Rule ID 2982 //
     /* 260638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 260646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260655 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260658 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 260661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260665 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1613:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLA_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 260665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_H_UNDEF),
     /* 260668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260672 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260674 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260676 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260678 */     GIR_RootConstrainSelectedInstOperands,
     /* 260679 */     // GIR_Coverage, 2982,
     /* 260679 */     GIR_EraseRootFromParent_Done,
     /* 260680 */   // Label 5042: @260680
     /* 260680 */   GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(260727), // Rule ID 2984 //
     /* 260685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 260693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 260696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260702 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 260705 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 260708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260712 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1613:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLA_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 260712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_S_UNDEF),
     /* 260715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260721 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260723 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260725 */     GIR_RootConstrainSelectedInstOperands,
     /* 260726 */     // GIR_Coverage, 2984,
     /* 260726 */     GIR_EraseRootFromParent_Done,
     /* 260727 */   // Label 5043: @260727
     /* 260727 */   GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(260774), // Rule ID 2986 //
     /* 260732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 260740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 260743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 260746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 260749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260752 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 260755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260759 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1613:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLA_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 260759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_D_UNDEF),
     /* 260762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260768 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260770 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260772 */     GIR_RootConstrainSelectedInstOperands,
     /* 260773 */     // GIR_Coverage, 2986,
     /* 260773 */     GIR_EraseRootFromParent_Done,
     /* 260774 */   // Label 5044: @260774
     /* 260774 */   GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(260821), // Rule ID 7682 //
     /* 260779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 260787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260796 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 260799 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 260802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260806 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1616:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLS_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 260806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_B_UNDEF),
     /* 260809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260811 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260813 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260815 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260817 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260819 */     GIR_RootConstrainSelectedInstOperands,
     /* 260820 */     // GIR_Coverage, 7682,
     /* 260820 */     GIR_EraseRootFromParent_Done,
     /* 260821 */   // Label 5045: @260821
     /* 260821 */   GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(260868), // Rule ID 7684 //
     /* 260826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 260834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260843 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260846 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 260849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260853 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1616:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLS_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 260853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_H_UNDEF),
     /* 260856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260862 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260864 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260866 */     GIR_RootConstrainSelectedInstOperands,
     /* 260867 */     // GIR_Coverage, 7684,
     /* 260867 */     GIR_EraseRootFromParent_Done,
     /* 260868 */   // Label 5046: @260868
     /* 260868 */   GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(260915), // Rule ID 7686 //
     /* 260873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 260881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 260884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260890 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 260893 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 260896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260900 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1616:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLS_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 260900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_S_UNDEF),
     /* 260903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260909 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260911 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260913 */     GIR_RootConstrainSelectedInstOperands,
     /* 260914 */     // GIR_Coverage, 7686,
     /* 260914 */     GIR_EraseRootFromParent_Done,
     /* 260915 */   // Label 5047: @260915
     /* 260915 */   GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(260962), // Rule ID 7688 //
     /* 260920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 260928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 260931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 260934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 260937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260940 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 260943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260947 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1616:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLS_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 260947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_D_UNDEF),
     /* 260950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260956 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260958 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 260960 */     GIR_RootConstrainSelectedInstOperands,
     /* 260961 */     // GIR_Coverage, 7688,
     /* 260961 */     GIR_EraseRootFromParent_Done,
     /* 260962 */   // Label 5048: @260962
     /* 260962 */   GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(261042), // Rule ID 5758 //
     /* 260967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 260972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 260975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 260978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 260981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 260984 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 260987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260991 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 260995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 260999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261003 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 261007 */     // MIs[1] Operand 1
     /* 261007 */     // No operand predicates
     /* 261007 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261011 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 261015 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261019 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 261023 */     // MIs[2] Operand 1
     /* 261023 */     // No operand predicates
     /* 261023 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 261025 */     // (intrinsic_wo_chain:{ *:[v16i8] } 771:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)
     /* 261025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 261028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 261030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261032 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 261035 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 261037 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 261040 */     GIR_RootConstrainSelectedInstOperands,
     /* 261041 */     // GIR_Coverage, 5758,
     /* 261041 */     GIR_EraseRootFromParent_Done,
     /* 261042 */   // Label 5049: @261042
     /* 261042 */   GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(261122), // Rule ID 5759 //
     /* 261047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 261052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 261055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 261058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 261061 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 261064 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 261067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 261079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261083 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 261087 */     // MIs[1] Operand 1
     /* 261087 */     // No operand predicates
     /* 261087 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 261095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261099 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 261103 */     // MIs[2] Operand 1
     /* 261103 */     // No operand predicates
     /* 261103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 261105 */     // (intrinsic_wo_chain:{ *:[v8i16] } 771:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)
     /* 261105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 261108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 261110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261112 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 261115 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 261117 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 261120 */     GIR_RootConstrainSelectedInstOperands,
     /* 261121 */     // GIR_Coverage, 5759,
     /* 261121 */     GIR_EraseRootFromParent_Done,
     /* 261122 */   // Label 5050: @261122
     /* 261122 */   GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(261202), // Rule ID 5760 //
     /* 261127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 261132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 261135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 261138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 261141 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 261144 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 261147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261151 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 261159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261163 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 261167 */     // MIs[1] Operand 1
     /* 261167 */     // No operand predicates
     /* 261167 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261171 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 261175 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261179 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 261183 */     // MIs[2] Operand 1
     /* 261183 */     // No operand predicates
     /* 261183 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 261185 */     // (intrinsic_wo_chain:{ *:[v4i32] } 771:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)
     /* 261185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 261188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 261190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261192 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 261195 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 261197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 261200 */     GIR_RootConstrainSelectedInstOperands,
     /* 261201 */     // GIR_Coverage, 5760,
     /* 261201 */     GIR_EraseRootFromParent_Done,
     /* 261202 */   // Label 5051: @261202
     /* 261202 */   GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(261282), // Rule ID 5761 //
     /* 261207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 261212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 261215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 261218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 261221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 261224 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 261227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 261239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261243 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 261247 */     // MIs[1] Operand 1
     /* 261247 */     // No operand predicates
     /* 261247 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261251 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 261255 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 261259 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 261263 */     // MIs[2] Operand 1
     /* 261263 */     // No operand predicates
     /* 261263 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 261265 */     // (intrinsic_wo_chain:{ *:[v2i64] } 771:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)
     /* 261265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 261268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 261270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261272 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 261275 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 261277 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 261280 */     GIR_RootConstrainSelectedInstOperands,
     /* 261281 */     // GIR_Coverage, 5761,
     /* 261281 */     GIR_EraseRootFromParent_Done,
     /* 261282 */   // Label 5052: @261282
     /* 261282 */   GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(261346), // Rule ID 3882 //
     /* 261287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 261290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1a),
     /* 261295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 261298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 261301 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 261304 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 261307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261311 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261315 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261319 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261323 */     // MIs[0] imm
     /* 261323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261326 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 261331 */     // (intrinsic_wo_chain:{ *:[v4i32] } 547:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT1A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 261331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1A),
     /* 261334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 261336 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261338 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 261340 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 261342 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 261344 */     GIR_RootConstrainSelectedInstOperands,
     /* 261345 */     // GIR_Coverage, 3882,
     /* 261345 */     GIR_EraseRootFromParent_Done,
     /* 261346 */   // Label 5053: @261346
     /* 261346 */   GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(261410), // Rule ID 3883 //
     /* 261351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 261354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1b),
     /* 261359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 261362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 261365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 261368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 261371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261383 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261387 */     // MIs[0] imm
     /* 261387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261390 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 261395 */     // (intrinsic_wo_chain:{ *:[v4i32] } 548:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT1B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 261395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1B),
     /* 261398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 261400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261402 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 261404 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 261406 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 261408 */     GIR_RootConstrainSelectedInstOperands,
     /* 261409 */     // GIR_Coverage, 3883,
     /* 261409 */     GIR_EraseRootFromParent_Done,
     /* 261410 */   // Label 5054: @261410
     /* 261410 */   GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(261474), // Rule ID 3884 //
     /* 261415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 261418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2a),
     /* 261423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 261426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 261429 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 261432 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 261435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261439 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261443 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261447 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261451 */     // MIs[0] imm
     /* 261451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261454 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 261459 */     // (intrinsic_wo_chain:{ *:[v4i32] } 549:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT2A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 261459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2A),
     /* 261462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 261464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 261468 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 261470 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 261472 */     GIR_RootConstrainSelectedInstOperands,
     /* 261473 */     // GIR_Coverage, 3884,
     /* 261473 */     GIR_EraseRootFromParent_Done,
     /* 261474 */   // Label 5055: @261474
     /* 261474 */   GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(261538), // Rule ID 3885 //
     /* 261479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 261482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2b),
     /* 261487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 261490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 261493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 261496 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 261499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261507 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261511 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 261515 */     // MIs[0] imm
     /* 261515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261518 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 261523 */     // (intrinsic_wo_chain:{ *:[v4i32] } 550:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT2B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 261523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2B),
     /* 261526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 261528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 261530 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 261532 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 261534 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 261536 */     GIR_RootConstrainSelectedInstOperands,
     /* 261537 */     // GIR_Coverage, 3885,
     /* 261537 */     GIR_EraseRootFromParent_Done,
     /* 261538 */   // Label 5056: @261538
     /* 261538 */   GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(261590), // Rule ID 2852 //
     /* 261543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 261551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 261557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261560 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261567 */     // MIs[0] idx
     /* 261567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261570 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 261575 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1472:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMLA_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 261575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_H),
     /* 261578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261580 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261582 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261584 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261586 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 261588 */     GIR_RootConstrainSelectedInstOperands,
     /* 261589 */     // GIR_Coverage, 2852,
     /* 261589 */     GIR_EraseRootFromParent_Done,
     /* 261590 */   // Label 5057: @261590
     /* 261590 */   GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(261642), // Rule ID 2855 //
     /* 261595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 261603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261612 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261619 */     // MIs[0] idx
     /* 261619 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261622 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 261627 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1472:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMLA_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 261627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_S),
     /* 261630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261636 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261638 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 261640 */     GIR_RootConstrainSelectedInstOperands,
     /* 261641 */     // GIR_Coverage, 2855,
     /* 261641 */     GIR_EraseRootFromParent_Done,
     /* 261642 */   // Label 5058: @261642
     /* 261642 */   GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(261694), // Rule ID 2858 //
     /* 261647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 261655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 261661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261664 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261671 */     // MIs[0] idx
     /* 261671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261674 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 261679 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1472:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMLA_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 261679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_D),
     /* 261682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261684 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261686 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261688 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261690 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 261692 */     GIR_RootConstrainSelectedInstOperands,
     /* 261693 */     // GIR_Coverage, 2858,
     /* 261693 */     GIR_EraseRootFromParent_Done,
     /* 261694 */   // Label 5059: @261694
     /* 261694 */   GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(261746), // Rule ID 2995 //
     /* 261699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 261702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 261707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 261713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261716 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261723 */     // MIs[0] Op4
     /* 261723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261726 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 261731 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1612:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (MLA_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 261731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_H),
     /* 261734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261740 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261742 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 261744 */     GIR_RootConstrainSelectedInstOperands,
     /* 261745 */     // GIR_Coverage, 2995,
     /* 261745 */     GIR_EraseRootFromParent_Done,
     /* 261746 */   // Label 5060: @261746
     /* 261746 */   GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(261798), // Rule ID 2996 //
     /* 261751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 261754 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 261759 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261762 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261765 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261768 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261775 */     // MIs[0] Op4
     /* 261775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261778 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 261783 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1612:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (MLA_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 261783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_S),
     /* 261786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261790 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261792 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261794 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 261796 */     GIR_RootConstrainSelectedInstOperands,
     /* 261797 */     // GIR_Coverage, 2996,
     /* 261797 */     GIR_EraseRootFromParent_Done,
     /* 261798 */   // Label 5061: @261798
     /* 261798 */   GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(261850), // Rule ID 2997 //
     /* 261803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 261806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 261811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 261817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261820 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261827 */     // MIs[0] Op4
     /* 261827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261830 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 261835 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1612:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (MLA_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 261835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_D),
     /* 261838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261842 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261844 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261846 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 261848 */     GIR_RootConstrainSelectedInstOperands,
     /* 261849 */     // GIR_Coverage, 2997,
     /* 261849 */     GIR_EraseRootFromParent_Done,
     /* 261850 */   // Label 5062: @261850
     /* 261850 */   GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(261902), // Rule ID 2998 //
     /* 261855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 261858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
     /* 261863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261872 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261879 */     // MIs[0] Op4
     /* 261879 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261882 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 261887 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1754:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 261887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_S),
     /* 261890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261896 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261898 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 261900 */     GIR_RootConstrainSelectedInstOperands,
     /* 261901 */     // GIR_Coverage, 2998,
     /* 261901 */     GIR_EraseRootFromParent_Done,
     /* 261902 */   // Label 5063: @261902
     /* 261902 */   GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(261954), // Rule ID 2999 //
     /* 261907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 261910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
     /* 261915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 261921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261924 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261931 */     // MIs[0] Op4
     /* 261931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261934 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 261939 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1754:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 261939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_D),
     /* 261942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261948 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261950 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 261952 */     GIR_RootConstrainSelectedInstOperands,
     /* 261953 */     // GIR_Coverage, 2999,
     /* 261953 */     GIR_EraseRootFromParent_Done,
     /* 261954 */   // Label 5064: @261954
     /* 261954 */   GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(262006), // Rule ID 3002 //
     /* 261959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
     /* 261967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 261976 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 261979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261983 */     // MIs[0] Op4
     /* 261983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 261986 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 261991 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1720:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SDOT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 261991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_S),
     /* 261994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262000 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262002 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262004 */     GIR_RootConstrainSelectedInstOperands,
     /* 262005 */     // GIR_Coverage, 3002,
     /* 262005 */     GIR_EraseRootFromParent_Done,
     /* 262006 */   // Label 5065: @262006
     /* 262006 */   GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(262058), // Rule ID 3003 //
     /* 262011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262014 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
     /* 262019 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262028 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262035 */     // MIs[0] Op4
     /* 262035 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262038 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262043 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1720:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SDOT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 262043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_D),
     /* 262046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262050 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262052 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262054 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262056 */     GIR_RootConstrainSelectedInstOperands,
     /* 262057 */     // GIR_Coverage, 3003,
     /* 262057 */     GIR_EraseRootFromParent_Done,
     /* 262058 */   // Label 5066: @262058
     /* 262058 */   GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(262110), // Rule ID 3483 //
     /* 262063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE_or_SME),
     /* 262066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usdot_lane),
     /* 262071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262080 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262087 */     // MIs[0] Op4
     /* 262087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262090 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262095 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2067:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (USDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOT_ZZZI),
     /* 262098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262102 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262104 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262106 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262108 */     GIR_RootConstrainSelectedInstOperands,
     /* 262109 */     // GIR_Coverage, 3483,
     /* 262109 */     GIR_EraseRootFromParent_Done,
     /* 262110 */   // Label 5067: @262110
     /* 262110 */   GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(262162), // Rule ID 3533 //
     /* 262115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 262118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane_x2),
     /* 262123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262139 */     // MIs[0] Op4
     /* 262139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262142 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262147 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1721:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_HtoS),
     /* 262150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262156 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262158 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262160 */     GIR_RootConstrainSelectedInstOperands,
     /* 262161 */     // GIR_Coverage, 3533,
     /* 262161 */     GIR_EraseRootFromParent_Done,
     /* 262162 */   // Label 5068: @262162
     /* 262162 */   GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(262214), // Rule ID 7756 //
     /* 262167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
     /* 262175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262184 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262191 */     // MIs[0] Op4
     /* 262191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262194 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262199 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1967:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UDOT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_S),
     /* 262202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262206 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262208 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262210 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262212 */     GIR_RootConstrainSelectedInstOperands,
     /* 262213 */     // GIR_Coverage, 7756,
     /* 262213 */     GIR_EraseRootFromParent_Done,
     /* 262214 */   // Label 5069: @262214
     /* 262214 */   GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(262266), // Rule ID 7757 //
     /* 262219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
     /* 262227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262233 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262236 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262243 */     // MIs[0] Op4
     /* 262243 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262246 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262251 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1967:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (UDOT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 262251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_D),
     /* 262254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262256 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262258 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262260 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262262 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262264 */     GIR_RootConstrainSelectedInstOperands,
     /* 262265 */     // GIR_Coverage, 7757,
     /* 262265 */     GIR_EraseRootFromParent_Done,
     /* 262266 */   // Label 5070: @262266
     /* 262266 */   GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(262318), // Rule ID 8402 //
     /* 262271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 262279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 262285 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262288 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262295 */     // MIs[0] idx
     /* 262295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262298 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 262303 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1479:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMLS_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 262303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_H),
     /* 262306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262312 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262314 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 262316 */     GIR_RootConstrainSelectedInstOperands,
     /* 262317 */     // GIR_Coverage, 8402,
     /* 262317 */     GIR_EraseRootFromParent_Done,
     /* 262318 */   // Label 5071: @262318
     /* 262318 */   GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(262370), // Rule ID 8405 //
     /* 262323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 262331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262337 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262340 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262347 */     // MIs[0] idx
     /* 262347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262350 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262355 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1479:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMLS_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 262355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_S),
     /* 262358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262364 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262366 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 262368 */     GIR_RootConstrainSelectedInstOperands,
     /* 262369 */     // GIR_Coverage, 8405,
     /* 262369 */     GIR_EraseRootFromParent_Done,
     /* 262370 */   // Label 5072: @262370
     /* 262370 */   GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(262422), // Rule ID 8408 //
     /* 262375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 262383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262392 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262399 */     // MIs[0] idx
     /* 262399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262402 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262407 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1479:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMLS_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 262407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_D),
     /* 262410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262412 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262414 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262416 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262418 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 262420 */     GIR_RootConstrainSelectedInstOperands,
     /* 262421 */     // GIR_Coverage, 8408,
     /* 262421 */     GIR_EraseRootFromParent_Done,
     /* 262422 */   // Label 5073: @262422
     /* 262422 */   GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(262474), // Rule ID 11390 //
     /* 262427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE_or_SME),
     /* 262430 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sudot_lane),
     /* 262435 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262444 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262451 */     // MIs[0] Op4
     /* 262451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262454 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262459 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1916:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SUDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOT_ZZZI),
     /* 262462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262468 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262470 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262472 */     GIR_RootConstrainSelectedInstOperands,
     /* 262473 */     // GIR_Coverage, 11390,
     /* 262473 */     GIR_EraseRootFromParent_Done,
     /* 262474 */   // Label 5074: @262474
     /* 262474 */   GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(262526), // Rule ID 11437 //
     /* 262479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 262487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 262493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262496 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262503 */     // MIs[0] Op4
     /* 262503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262506 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 262511 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1615:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (MLS_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 262511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_H),
     /* 262514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262520 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262522 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262524 */     GIR_RootConstrainSelectedInstOperands,
     /* 262525 */     // GIR_Coverage, 11437,
     /* 262525 */     GIR_EraseRootFromParent_Done,
     /* 262526 */   // Label 5075: @262526
     /* 262526 */   GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(262578), // Rule ID 11438 //
     /* 262531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 262539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262548 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262555 */     // MIs[0] Op4
     /* 262555 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262558 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262563 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1615:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (MLS_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_S),
     /* 262566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262572 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262574 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262576 */     GIR_RootConstrainSelectedInstOperands,
     /* 262577 */     // GIR_Coverage, 11438,
     /* 262577 */     GIR_EraseRootFromParent_Done,
     /* 262578 */   // Label 5076: @262578
     /* 262578 */   GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(262630), // Rule ID 11439 //
     /* 262583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 262591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262594 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262597 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262600 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262603 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262607 */     // MIs[0] Op4
     /* 262607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262610 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262615 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1615:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (MLS_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 262615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_D),
     /* 262618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262620 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262622 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262624 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262626 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262628 */     GIR_RootConstrainSelectedInstOperands,
     /* 262629 */     // GIR_Coverage, 11439,
     /* 262629 */     GIR_EraseRootFromParent_Done,
     /* 262630 */   // Label 5077: @262630
     /* 262630 */   GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(262682), // Rule ID 11440 //
     /* 262635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262638 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 262643 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262646 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 262649 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262652 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262659 */     // MIs[0] Op4
     /* 262659 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262662 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 262667 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1833:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 262667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_H),
     /* 262670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262676 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262678 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262680 */     GIR_RootConstrainSelectedInstOperands,
     /* 262681 */     // GIR_Coverage, 11440,
     /* 262681 */     GIR_EraseRootFromParent_Done,
     /* 262682 */   // Label 5078: @262682
     /* 262682 */   GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(262734), // Rule ID 11441 //
     /* 262687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 262695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262704 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262711 */     // MIs[0] Op4
     /* 262711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262714 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262719 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1833:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_S),
     /* 262722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262726 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262728 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262730 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262732 */     GIR_RootConstrainSelectedInstOperands,
     /* 262733 */     // GIR_Coverage, 11441,
     /* 262733 */     GIR_EraseRootFromParent_Done,
     /* 262734 */   // Label 5079: @262734
     /* 262734 */   GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(262786), // Rule ID 11442 //
     /* 262739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 262747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262763 */     // MIs[0] Op4
     /* 262763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262766 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262771 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1833:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 262771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_D),
     /* 262774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262778 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262780 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262782 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262784 */     GIR_RootConstrainSelectedInstOperands,
     /* 262785 */     // GIR_Coverage, 11442,
     /* 262785 */     GIR_EraseRootFromParent_Done,
     /* 262786 */   // Label 5080: @262786
     /* 262786 */   GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(262838), // Rule ID 11443 //
     /* 262791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 262799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 262805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262815 */     // MIs[0] Op4
     /* 262815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262818 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 262823 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1835:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 262823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_H),
     /* 262826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262832 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262834 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262836 */     GIR_RootConstrainSelectedInstOperands,
     /* 262837 */     // GIR_Coverage, 11443,
     /* 262837 */     GIR_EraseRootFromParent_Done,
     /* 262838 */   // Label 5081: @262838
     /* 262838 */   GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(262890), // Rule ID 11444 //
     /* 262843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 262851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262860 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262867 */     // MIs[0] Op4
     /* 262867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262870 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 262875 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1835:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 262875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_S),
     /* 262878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262882 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262884 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262886 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262888 */     GIR_RootConstrainSelectedInstOperands,
     /* 262889 */     // GIR_Coverage, 11444,
     /* 262889 */     GIR_EraseRootFromParent_Done,
     /* 262890 */   // Label 5082: @262890
     /* 262890 */   GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(262942), // Rule ID 11445 //
     /* 262895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 262903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262912 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262919 */     // MIs[0] Op4
     /* 262919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262922 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 262927 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1835:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 262927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_D),
     /* 262930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262932 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262934 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262936 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262938 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262940 */     GIR_RootConstrainSelectedInstOperands,
     /* 262941 */     // GIR_Coverage, 11445,
     /* 262941 */     GIR_EraseRootFromParent_Done,
     /* 262942 */   // Label 5083: @262942
     /* 262942 */   GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(262994), // Rule ID 11488 //
     /* 262947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 262950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
     /* 262955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262964 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262971 */     // MIs[0] Op4
     /* 262971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 262974 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 262979 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1756:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 262979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_S),
     /* 262982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 262984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262988 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262990 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 262992 */     GIR_RootConstrainSelectedInstOperands,
     /* 262993 */     // GIR_Coverage, 11488,
     /* 262993 */     GIR_EraseRootFromParent_Done,
     /* 262994 */   // Label 5084: @262994
     /* 262994 */   GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(263046), // Rule ID 11489 //
     /* 262999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
     /* 263007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263016 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263023 */     // MIs[0] Op4
     /* 263023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263026 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263031 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1756:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_D),
     /* 263034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263040 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263042 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263044 */     GIR_RootConstrainSelectedInstOperands,
     /* 263045 */     // GIR_Coverage, 11489,
     /* 263045 */     GIR_EraseRootFromParent_Done,
     /* 263046 */   // Label 5085: @263046
     /* 263046 */   GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(263098), // Rule ID 11490 //
     /* 263051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
     /* 263059 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263062 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263068 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263075 */     // MIs[0] Op4
     /* 263075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263078 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263083 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1992:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_S),
     /* 263086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263092 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263094 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263096 */     GIR_RootConstrainSelectedInstOperands,
     /* 263097 */     // GIR_Coverage, 11490,
     /* 263097 */     GIR_EraseRootFromParent_Done,
     /* 263098 */   // Label 5086: @263098
     /* 263098 */   GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(263150), // Rule ID 11491 //
     /* 263103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
     /* 263111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263120 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263127 */     // MIs[0] Op4
     /* 263127 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263130 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263135 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1992:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_D),
     /* 263138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263144 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263146 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263148 */     GIR_RootConstrainSelectedInstOperands,
     /* 263149 */     // GIR_Coverage, 11491,
     /* 263149 */     GIR_EraseRootFromParent_Done,
     /* 263150 */   // Label 5087: @263150
     /* 263150 */   GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(263202), // Rule ID 11492 //
     /* 263155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
     /* 263163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263172 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263179 */     // MIs[0] Op4
     /* 263179 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263182 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263187 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1994:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_S),
     /* 263190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263194 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263196 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263198 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263200 */     GIR_RootConstrainSelectedInstOperands,
     /* 263201 */     // GIR_Coverage, 11492,
     /* 263201 */     GIR_EraseRootFromParent_Done,
     /* 263202 */   // Label 5088: @263202
     /* 263202 */   GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(263254), // Rule ID 11493 //
     /* 263207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
     /* 263215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263224 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263231 */     // MIs[0] Op4
     /* 263231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263234 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263239 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1994:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_D),
     /* 263242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263244 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263246 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263248 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263250 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263252 */     GIR_RootConstrainSelectedInstOperands,
     /* 263253 */     // GIR_Coverage, 11493,
     /* 263253 */     GIR_EraseRootFromParent_Done,
     /* 263254 */   // Label 5089: @263254
     /* 263254 */   GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(263306), // Rule ID 11494 //
     /* 263259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
     /* 263267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263276 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263283 */     // MIs[0] Op4
     /* 263283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263286 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263291 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1758:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_S),
     /* 263294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263300 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263302 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263304 */     GIR_RootConstrainSelectedInstOperands,
     /* 263305 */     // GIR_Coverage, 11494,
     /* 263305 */     GIR_EraseRootFromParent_Done,
     /* 263306 */   // Label 5090: @263306
     /* 263306 */   GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(263358), // Rule ID 11495 //
     /* 263311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
     /* 263319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263328 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263335 */     // MIs[0] Op4
     /* 263335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263338 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263343 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1758:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_D),
     /* 263346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263352 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263354 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263356 */     GIR_RootConstrainSelectedInstOperands,
     /* 263357 */     // GIR_Coverage, 11495,
     /* 263357 */     GIR_EraseRootFromParent_Done,
     /* 263358 */   // Label 5091: @263358
     /* 263358 */   GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(263410), // Rule ID 11496 //
     /* 263363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
     /* 263371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263380 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263387 */     // MIs[0] Op4
     /* 263387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263390 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263395 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1760:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_S),
     /* 263398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263402 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263404 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263406 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263408 */     GIR_RootConstrainSelectedInstOperands,
     /* 263409 */     // GIR_Coverage, 11496,
     /* 263409 */     GIR_EraseRootFromParent_Done,
     /* 263410 */   // Label 5092: @263410
     /* 263410 */   GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(263462), // Rule ID 11497 //
     /* 263415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
     /* 263423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263429 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263432 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263439 */     // MIs[0] Op4
     /* 263439 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263442 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263447 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1760:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_D),
     /* 263450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263454 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263456 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263458 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263460 */     GIR_RootConstrainSelectedInstOperands,
     /* 263461 */     // GIR_Coverage, 11497,
     /* 263461 */     GIR_EraseRootFromParent_Done,
     /* 263462 */   // Label 5093: @263462
     /* 263462 */   GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(263514), // Rule ID 11498 //
     /* 263467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263470 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
     /* 263475 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263478 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263481 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263484 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263491 */     // MIs[0] Op4
     /* 263491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263494 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263499 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1996:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_S),
     /* 263502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263508 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263510 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263512 */     GIR_RootConstrainSelectedInstOperands,
     /* 263513 */     // GIR_Coverage, 11498,
     /* 263513 */     GIR_EraseRootFromParent_Done,
     /* 263514 */   // Label 5094: @263514
     /* 263514 */   GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(263566), // Rule ID 11499 //
     /* 263519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
     /* 263527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263543 */     // MIs[0] Op4
     /* 263543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263546 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263551 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1996:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_D),
     /* 263554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263558 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263560 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263562 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263564 */     GIR_RootConstrainSelectedInstOperands,
     /* 263565 */     // GIR_Coverage, 11499,
     /* 263565 */     GIR_EraseRootFromParent_Done,
     /* 263566 */   // Label 5095: @263566
     /* 263566 */   GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(263618), // Rule ID 11500 //
     /* 263571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
     /* 263579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263588 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263595 */     // MIs[0] Op4
     /* 263595 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263598 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263603 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1998:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_S),
     /* 263606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263612 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263614 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263616 */     GIR_RootConstrainSelectedInstOperands,
     /* 263617 */     // GIR_Coverage, 11500,
     /* 263617 */     GIR_EraseRootFromParent_Done,
     /* 263618 */   // Label 5096: @263618
     /* 263618 */   GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(263670), // Rule ID 11501 //
     /* 263623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
     /* 263631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263647 */     // MIs[0] Op4
     /* 263647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263650 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263655 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1998:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_D),
     /* 263658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263664 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263666 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263668 */     GIR_RootConstrainSelectedInstOperands,
     /* 263669 */     // GIR_Coverage, 11501,
     /* 263669 */     GIR_EraseRootFromParent_Done,
     /* 263670 */   // Label 5097: @263670
     /* 263670 */   GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(263722), // Rule ID 11523 //
     /* 263675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
     /* 263683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263689 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263692 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263699 */     // MIs[0] Op4
     /* 263699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263702 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263707 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1796:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_S),
     /* 263710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263716 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263718 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263720 */     GIR_RootConstrainSelectedInstOperands,
     /* 263721 */     // GIR_Coverage, 11523,
     /* 263721 */     GIR_EraseRootFromParent_Done,
     /* 263722 */   // Label 5098: @263722
     /* 263722 */   GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(263774), // Rule ID 11524 //
     /* 263727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
     /* 263735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263744 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263751 */     // MIs[0] Op4
     /* 263751 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263754 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263759 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1796:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_D),
     /* 263762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263768 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263770 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263772 */     GIR_RootConstrainSelectedInstOperands,
     /* 263773 */     // GIR_Coverage, 11524,
     /* 263773 */     GIR_EraseRootFromParent_Done,
     /* 263774 */   // Label 5099: @263774
     /* 263774 */   GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(263826), // Rule ID 11525 //
     /* 263779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
     /* 263787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263796 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263803 */     // MIs[0] Op4
     /* 263803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263806 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263811 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1799:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_S),
     /* 263814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263820 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263822 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263824 */     GIR_RootConstrainSelectedInstOperands,
     /* 263825 */     // GIR_Coverage, 11525,
     /* 263825 */     GIR_EraseRootFromParent_Done,
     /* 263826 */   // Label 5100: @263826
     /* 263826 */   GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(263878), // Rule ID 11526 //
     /* 263831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
     /* 263839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263842 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263845 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263848 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263855 */     // MIs[0] Op4
     /* 263855 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263858 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263863 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1799:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_D),
     /* 263866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263870 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263872 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263874 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263876 */     GIR_RootConstrainSelectedInstOperands,
     /* 263877 */     // GIR_Coverage, 11526,
     /* 263877 */     GIR_EraseRootFromParent_Done,
     /* 263878 */   // Label 5101: @263878
     /* 263878 */   GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(263930), // Rule ID 11527 //
     /* 263883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
     /* 263891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263900 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263907 */     // MIs[0] Op4
     /* 263907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263910 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 263915 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1801:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 263915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_S),
     /* 263918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263924 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263926 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263928 */     GIR_RootConstrainSelectedInstOperands,
     /* 263929 */     // GIR_Coverage, 11527,
     /* 263929 */     GIR_EraseRootFromParent_Done,
     /* 263930 */   // Label 5102: @263930
     /* 263930 */   GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(263982), // Rule ID 11528 //
     /* 263935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263938 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
     /* 263943 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263949 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263952 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263959 */     // MIs[0] Op4
     /* 263959 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 263962 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 263967 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1801:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 263967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_D),
     /* 263970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 263972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263976 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263978 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 263980 */     GIR_RootConstrainSelectedInstOperands,
     /* 263981 */     // GIR_Coverage, 11528,
     /* 263981 */     GIR_EraseRootFromParent_Done,
     /* 263982 */   // Label 5103: @263982
     /* 263982 */   GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(264034), // Rule ID 11529 //
     /* 263987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 263990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
     /* 263995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264001 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264004 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264011 */     // MIs[0] Op4
     /* 264011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264014 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 264019 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1804:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 264019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_S),
     /* 264022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264024 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264026 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264028 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264030 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264032 */     GIR_RootConstrainSelectedInstOperands,
     /* 264033 */     // GIR_Coverage, 11529,
     /* 264033 */     GIR_EraseRootFromParent_Done,
     /* 264034 */   // Label 5104: @264034
     /* 264034 */   GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(264086), // Rule ID 11530 //
     /* 264039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 264042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
     /* 264047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 264053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264056 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264063 */     // MIs[0] Op4
     /* 264063 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264066 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 264071 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1804:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 264071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_D),
     /* 264074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264076 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264078 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264080 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264082 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264084 */     GIR_RootConstrainSelectedInstOperands,
     /* 264085 */     // GIR_Coverage, 11530,
     /* 264085 */     GIR_EraseRootFromParent_Done,
     /* 264086 */   // Label 5105: @264086
     /* 264086 */   GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(264138), // Rule ID 11996 //
     /* 264091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 264094 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb_lane),
     /* 264099 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264102 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264105 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264108 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264115 */     // MIs[0] Op4
     /* 264115 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264118 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 264123 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1475:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLALB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 264123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZI_SHH),
     /* 264126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264130 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264132 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264134 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264136 */     GIR_RootConstrainSelectedInstOperands,
     /* 264137 */     // GIR_Coverage, 11996,
     /* 264137 */     GIR_EraseRootFromParent_Done,
     /* 264138 */   // Label 5106: @264138
     /* 264138 */   GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(264190), // Rule ID 11997 //
     /* 264143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 264146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt_lane),
     /* 264151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264160 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264167 */     // MIs[0] Op4
     /* 264167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264170 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 264175 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1477:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLALT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 264175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZI_SHH),
     /* 264178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264182 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264184 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264186 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264188 */     GIR_RootConstrainSelectedInstOperands,
     /* 264189 */     // GIR_Coverage, 11997,
     /* 264189 */     GIR_EraseRootFromParent_Done,
     /* 264190 */   // Label 5107: @264190
     /* 264190 */   GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(264242), // Rule ID 11998 //
     /* 264195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 264198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb_lane),
     /* 264203 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264206 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264212 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264219 */     // MIs[0] Op4
     /* 264219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264222 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 264227 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1482:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLSLB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 264227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZI_SHH),
     /* 264230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264234 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264236 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264238 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264240 */     GIR_RootConstrainSelectedInstOperands,
     /* 264241 */     // GIR_Coverage, 11998,
     /* 264241 */     GIR_EraseRootFromParent_Done,
     /* 264242 */   // Label 5108: @264242
     /* 264242 */   GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(264294), // Rule ID 11999 //
     /* 264247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 264250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt_lane),
     /* 264255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264264 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264271 */     // MIs[0] Op4
     /* 264271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264274 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 264279 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1484:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLSLT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 264279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZI_SHH),
     /* 264282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264286 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264288 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264290 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264292 */     GIR_RootConstrainSelectedInstOperands,
     /* 264293 */     // GIR_Coverage, 11999,
     /* 264293 */     GIR_EraseRootFromParent_Done,
     /* 264294 */   // Label 5109: @264294
     /* 264294 */   GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(264346), // Rule ID 12291 //
     /* 264299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 264302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_lane_x2),
     /* 264307 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264316 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264323 */     // MIs[0] Op4
     /* 264323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264326 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 264331 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1430:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (FDOT_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 264331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_S),
     /* 264334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264336 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264338 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264340 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264342 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264344 */     GIR_RootConstrainSelectedInstOperands,
     /* 264345 */     // GIR_Coverage, 12291,
     /* 264345 */     GIR_EraseRootFromParent_Done,
     /* 264346 */   // Label 5110: @264346
     /* 264346 */   GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(264398), // Rule ID 12293 //
     /* 264351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 264354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane_x2),
     /* 264359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 264365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264375 */     // MIs[0] Op4
     /* 264375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 264378 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 264383 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1968:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 264383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_HtoS),
     /* 264386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264392 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264394 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264396 */     GIR_RootConstrainSelectedInstOperands,
     /* 264397 */     // GIR_Coverage, 12293,
     /* 264397 */     GIR_EraseRootFromParent_Done,
     /* 264398 */   // Label 5111: @264398
     /* 264398 */   GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(264445), // Rule ID 2829 //
     /* 264403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264420 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264423 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 264426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264430 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1471:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 264430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 264433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264437 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264439 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264441 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264443 */     GIR_RootConstrainSelectedInstOperands,
     /* 264444 */     // GIR_Coverage, 2829,
     /* 264444 */     GIR_EraseRootFromParent_Done,
     /* 264445 */   // Label 5112: @264445
     /* 264445 */   GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(264492), // Rule ID 2832 //
     /* 264450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 264461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 264467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 264470 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 264473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264477 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1471:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 264477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 264480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264482 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264486 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264488 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264490 */     GIR_RootConstrainSelectedInstOperands,
     /* 264491 */     // GIR_Coverage, 2832,
     /* 264491 */     GIR_EraseRootFromParent_Done,
     /* 264492 */   // Label 5113: @264492
     /* 264492 */   GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(264539), // Rule ID 2835 //
     /* 264497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 264508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 264514 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 264517 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 264520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264524 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1471:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 264524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 264527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264531 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264533 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264535 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264537 */     GIR_RootConstrainSelectedInstOperands,
     /* 264538 */     // GIR_Coverage, 2835,
     /* 264538 */     GIR_EraseRootFromParent_Done,
     /* 264539 */   // Label 5114: @264539
     /* 264539 */   GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(264586), // Rule ID 2838 //
     /* 264544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264564 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 264567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264571 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1471:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 264571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
     /* 264574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264578 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264580 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264582 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264584 */     GIR_RootConstrainSelectedInstOperands,
     /* 264585 */     // GIR_Coverage, 2838,
     /* 264585 */     GIR_EraseRootFromParent_Done,
     /* 264586 */   // Label 5115: @264586
     /* 264586 */   GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(264633), // Rule ID 2841 //
     /* 264591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 264602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 264608 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 264611 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 264614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264618 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1471:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 264618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
     /* 264621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264627 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264629 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264631 */     GIR_RootConstrainSelectedInstOperands,
     /* 264632 */     // GIR_Coverage, 2841,
     /* 264632 */     GIR_EraseRootFromParent_Done,
     /* 264633 */   // Label 5116: @264633
     /* 264633 */   GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(264680), // Rule ID 2844 //
     /* 264638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 264646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264655 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264658 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 264661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264665 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1471:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 264665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_D),
     /* 264668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 264670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264672 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264674 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264676 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264678 */     GIR_RootConstrainSelectedInstOperands,
     /* 264679 */     // GIR_Coverage, 2844,
     /* 264679 */     GIR_EraseRootFromParent_Done,
     /* 264680 */   // Label 5117: @264680
     /* 264680 */   GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(264727), // Rule ID 2847 //
     /* 264685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 264693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264702 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264705 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 264708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264712 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1434:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 264712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_H),
     /* 264715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264721 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264723 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264725 */     GIR_RootConstrainSelectedInstOperands,
     /* 264726 */     // GIR_Coverage, 2847,
     /* 264726 */     GIR_EraseRootFromParent_Done,
     /* 264727 */   // Label 5118: @264727
     /* 264727 */   GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(264774), // Rule ID 2848 //
     /* 264732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 264740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264752 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 264755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264759 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1434:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 264759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_S),
     /* 264762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264768 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264770 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264772 */     GIR_RootConstrainSelectedInstOperands,
     /* 264773 */     // GIR_Coverage, 2848,
     /* 264773 */     GIR_EraseRootFromParent_Done,
     /* 264774 */   // Label 5119: @264774
     /* 264774 */   GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(264821), // Rule ID 2849 //
     /* 264779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 264787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264796 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264799 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 264802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264806 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1434:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 264806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_D),
     /* 264809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264811 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264813 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264815 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264817 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264819 */     GIR_RootConstrainSelectedInstOperands,
     /* 264820 */     // GIR_Coverage, 2849,
     /* 264820 */     GIR_EraseRootFromParent_Done,
     /* 264821 */   // Label 5120: @264821
     /* 264821 */   GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(264868), // Rule ID 2960 //
     /* 264826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 264834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 264837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 264840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 264843 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 264846 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 264849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264853 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1609:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MAD_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 264853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_B),
     /* 264856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264862 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264864 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264866 */     GIR_RootConstrainSelectedInstOperands,
     /* 264867 */     // GIR_Coverage, 2960,
     /* 264867 */     GIR_EraseRootFromParent_Done,
     /* 264868 */   // Label 5121: @264868
     /* 264868 */   GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(264915), // Rule ID 2963 //
     /* 264873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 264881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264890 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264893 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 264896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264900 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1609:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MAD_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 264900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_H),
     /* 264903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264909 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264911 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264913 */     GIR_RootConstrainSelectedInstOperands,
     /* 264914 */     // GIR_Coverage, 2963,
     /* 264914 */     GIR_EraseRootFromParent_Done,
     /* 264915 */   // Label 5122: @264915
     /* 264915 */   GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(264962), // Rule ID 2966 //
     /* 264920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 264928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264940 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 264943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264947 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1609:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MAD_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 264947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_S),
     /* 264950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264956 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264958 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 264960 */     GIR_RootConstrainSelectedInstOperands,
     /* 264961 */     // GIR_Coverage, 2966,
     /* 264961 */     GIR_EraseRootFromParent_Done,
     /* 264962 */   // Label 5123: @264962
     /* 264962 */   GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(265009), // Rule ID 2969 //
     /* 264967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 264975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264987 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 264990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264994 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1609:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MAD_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 264994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_D),
     /* 264997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265001 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265003 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265005 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265007 */     GIR_RootConstrainSelectedInstOperands,
     /* 265008 */     // GIR_Coverage, 2969,
     /* 265008 */     GIR_EraseRootFromParent_Done,
     /* 265009 */   // Label 5124: @265009
     /* 265009 */   GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(265056), // Rule ID 2972 //
     /* 265014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 265022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 265025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 265031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 265034 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 265037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265041 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1611:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLA_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 265041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_B),
     /* 265044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265046 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265048 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265050 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265052 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265054 */     GIR_RootConstrainSelectedInstOperands,
     /* 265055 */     // GIR_Coverage, 2972,
     /* 265055 */     GIR_EraseRootFromParent_Done,
     /* 265056 */   // Label 5125: @265056
     /* 265056 */   GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(265103), // Rule ID 2974 //
     /* 265061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 265069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 265072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 265078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 265081 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 265084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265088 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1611:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLA_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 265088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_H),
     /* 265091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265097 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265099 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265101 */     GIR_RootConstrainSelectedInstOperands,
     /* 265102 */     // GIR_Coverage, 2974,
     /* 265102 */     GIR_EraseRootFromParent_Done,
     /* 265103 */   // Label 5126: @265103
     /* 265103 */   GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(265150), // Rule ID 2976 //
     /* 265108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 265116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 265119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 265125 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 265128 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 265131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265135 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1611:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLA_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 265135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_S),
     /* 265138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265144 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265146 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265148 */     GIR_RootConstrainSelectedInstOperands,
     /* 265149 */     // GIR_Coverage, 2976,
     /* 265149 */     GIR_EraseRootFromParent_Done,
     /* 265150 */   // Label 5127: @265150
     /* 265150 */   GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(265197), // Rule ID 2978 //
     /* 265155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 265163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 265166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 265172 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 265175 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 265178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265182 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1611:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLA_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 265182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_D),
     /* 265185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265189 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265191 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265193 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265195 */     GIR_RootConstrainSelectedInstOperands,
     /* 265196 */     // GIR_Coverage, 2978,
     /* 265196 */     GIR_EraseRootFromParent_Done,
     /* 265197 */   // Label 5128: @265197
     /* 265197 */   GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(265244), // Rule ID 7662 //
     /* 265202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 265210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 265213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 265219 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 265222 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 265225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265229 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1617:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MSB_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 265229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_B),
     /* 265232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 265234 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265238 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265240 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265242 */     GIR_RootConstrainSelectedInstOperands,
     /* 265243 */     // GIR_Coverage, 7662,
     /* 265243 */     GIR_EraseRootFromParent_Done,
     /* 265244 */   // Label 5129: @265244
     /* 265244 */   GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(265291), // Rule ID 7665 //
     /* 265249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 265257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 265260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 265266 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 265269 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 265272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265276 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1617:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MSB_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 265276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_H),
     /* 265279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 265281 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265283 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265285 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265287 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265289 */     GIR_RootConstrainSelectedInstOperands,
     /* 265290 */     // GIR_Coverage, 7665,
     /* 265290 */     GIR_EraseRootFromParent_Done,
     /* 265291 */   // Label 5130: @265291
     /* 265291 */   GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(265338), // Rule ID 7668 //
     /* 265296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 265304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 265307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 265313 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 265316 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 265319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265323 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1617:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MSB_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 265323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_S),
     /* 265326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 265328 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265330 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265332 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265334 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265336 */     GIR_RootConstrainSelectedInstOperands,
     /* 265337 */     // GIR_Coverage, 7668,
     /* 265337 */     GIR_EraseRootFromParent_Done,
     /* 265338 */   // Label 5131: @265338
     /* 265338 */   GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(265385), // Rule ID 7671 //
     /* 265343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 265351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 265354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 265360 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 265363 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 265366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265370 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1617:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MSB_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 265370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_D),
     /* 265373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 265375 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265377 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265379 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265381 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265383 */     GIR_RootConstrainSelectedInstOperands,
     /* 265384 */     // GIR_Coverage, 7671,
     /* 265384 */     GIR_EraseRootFromParent_Done,
     /* 265385 */   // Label 5132: @265385
     /* 265385 */   GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(265432), // Rule ID 7674 //
     /* 265390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 265398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 265401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 265407 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 265410 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 265413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265417 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1614:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLS_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 265417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_B),
     /* 265420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265426 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265428 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265430 */     GIR_RootConstrainSelectedInstOperands,
     /* 265431 */     // GIR_Coverage, 7674,
     /* 265431 */     GIR_EraseRootFromParent_Done,
     /* 265432 */   // Label 5133: @265432
     /* 265432 */   GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(265479), // Rule ID 7676 //
     /* 265437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 265445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 265448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 265454 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 265457 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 265460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265464 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1614:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLS_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 265464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_H),
     /* 265467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265471 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265473 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265475 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265477 */     GIR_RootConstrainSelectedInstOperands,
     /* 265478 */     // GIR_Coverage, 7676,
     /* 265478 */     GIR_EraseRootFromParent_Done,
     /* 265479 */   // Label 5134: @265479
     /* 265479 */   GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(265526), // Rule ID 7678 //
     /* 265484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 265492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 265495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 265501 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 265504 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 265507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265511 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1614:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLS_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 265511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_S),
     /* 265514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265520 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265522 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265524 */     GIR_RootConstrainSelectedInstOperands,
     /* 265525 */     // GIR_Coverage, 7678,
     /* 265525 */     GIR_EraseRootFromParent_Done,
     /* 265526 */   // Label 5135: @265526
     /* 265526 */   GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(265573), // Rule ID 7680 //
     /* 265531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 265539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 265542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 265548 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 265551 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 265554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265558 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1614:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLS_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 265558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_D),
     /* 265561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265567 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265569 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265571 */     GIR_RootConstrainSelectedInstOperands,
     /* 265572 */     // GIR_Coverage, 7680,
     /* 265572 */     GIR_EraseRootFromParent_Done,
     /* 265573 */   // Label 5136: @265573
     /* 265573 */   GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(265620), // Rule ID 8313 //
     /* 265578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 265589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 265595 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 265598 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 265601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265605 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1478:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 265605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 265608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265610 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265612 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265614 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265616 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265618 */     GIR_RootConstrainSelectedInstOperands,
     /* 265619 */     // GIR_Coverage, 8313,
     /* 265619 */     GIR_EraseRootFromParent_Done,
     /* 265620 */   // Label 5137: @265620
     /* 265620 */   GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(265667), // Rule ID 8316 //
     /* 265625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 265636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 265642 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 265645 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 265648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265652 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1478:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 265652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 265655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265661 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265663 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265665 */     GIR_RootConstrainSelectedInstOperands,
     /* 265666 */     // GIR_Coverage, 8316,
     /* 265666 */     GIR_EraseRootFromParent_Done,
     /* 265667 */   // Label 5138: @265667
     /* 265667 */   GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(265714), // Rule ID 8319 //
     /* 265672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 265683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 265689 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 265692 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 265695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265699 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1478:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 265699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 265702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265704 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265706 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265708 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265710 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265712 */     GIR_RootConstrainSelectedInstOperands,
     /* 265713 */     // GIR_Coverage, 8319,
     /* 265713 */     GIR_EraseRootFromParent_Done,
     /* 265714 */   // Label 5139: @265714
     /* 265714 */   GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(265761), // Rule ID 8322 //
     /* 265719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 265730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 265736 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 265739 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 265742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265746 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1478:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 265746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
     /* 265749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265753 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265755 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265757 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265759 */     GIR_RootConstrainSelectedInstOperands,
     /* 265760 */     // GIR_Coverage, 8322,
     /* 265760 */     GIR_EraseRootFromParent_Done,
     /* 265761 */   // Label 5140: @265761
     /* 265761 */   GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(265808), // Rule ID 8325 //
     /* 265766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 265777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 265783 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 265786 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 265789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265793 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1478:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 265793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
     /* 265796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265798 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265800 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265802 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265804 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265806 */     GIR_RootConstrainSelectedInstOperands,
     /* 265807 */     // GIR_Coverage, 8325,
     /* 265807 */     GIR_EraseRootFromParent_Done,
     /* 265808 */   // Label 5141: @265808
     /* 265808 */   GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(265855), // Rule ID 8328 //
     /* 265813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 265821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 265824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 265830 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 265833 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 265836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265840 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1478:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 265840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_D),
     /* 265843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265847 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265849 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265851 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265853 */     GIR_RootConstrainSelectedInstOperands,
     /* 265854 */     // GIR_Coverage, 8328,
     /* 265854 */     GIR_EraseRootFromParent_Done,
     /* 265855 */   // Label 5142: @265855
     /* 265855 */   GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(265902), // Rule ID 8331 //
     /* 265860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 265868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 265871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 265877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 265880 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 265883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265887 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1494:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 265887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 265890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265896 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265898 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265900 */     GIR_RootConstrainSelectedInstOperands,
     /* 265901 */     // GIR_Coverage, 8331,
     /* 265901 */     GIR_EraseRootFromParent_Done,
     /* 265902 */   // Label 5143: @265902
     /* 265902 */   GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(265949), // Rule ID 8332 //
     /* 265907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 265915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 265918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 265924 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 265927 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 265930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265934 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1494:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 265934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 265937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265943 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265945 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265947 */     GIR_RootConstrainSelectedInstOperands,
     /* 265948 */     // GIR_Coverage, 8332,
     /* 265948 */     GIR_EraseRootFromParent_Done,
     /* 265949 */   // Label 5144: @265949
     /* 265949 */   GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(265996), // Rule ID 8333 //
     /* 265954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 265962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 265965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 265971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 265974 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 265977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 265981 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1494:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 265981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 265984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 265986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265988 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265990 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265992 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 265994 */     GIR_RootConstrainSelectedInstOperands,
     /* 265995 */     // GIR_Coverage, 8333,
     /* 265995 */     GIR_EraseRootFromParent_Done,
     /* 265996 */   // Label 5145: @265996
     /* 265996 */   GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(266043), // Rule ID 8334 //
     /* 266001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 266009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266018 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266021 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 266024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266028 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1494:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 266028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
     /* 266031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266037 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266039 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266041 */     GIR_RootConstrainSelectedInstOperands,
     /* 266042 */     // GIR_Coverage, 8334,
     /* 266042 */     GIR_EraseRootFromParent_Done,
     /* 266043 */   // Label 5146: @266043
     /* 266043 */   GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(266090), // Rule ID 8335 //
     /* 266048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 266056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 266059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 266065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 266068 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 266071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266075 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1494:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 266075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
     /* 266078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266084 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266086 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266088 */     GIR_RootConstrainSelectedInstOperands,
     /* 266089 */     // GIR_Coverage, 8335,
     /* 266089 */     GIR_EraseRootFromParent_Done,
     /* 266090 */   // Label 5147: @266090
     /* 266090 */   GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(266137), // Rule ID 8336 //
     /* 266095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266098 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 266103 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266106 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266109 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266112 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266115 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 266118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266122 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1494:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 266122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_D),
     /* 266125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266127 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266129 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266131 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266133 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266135 */     GIR_RootConstrainSelectedInstOperands,
     /* 266136 */     // GIR_Coverage, 8336,
     /* 266136 */     GIR_EraseRootFromParent_Done,
     /* 266137 */   // Label 5148: @266137
     /* 266137 */   GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(266184), // Rule ID 8337 //
     /* 266142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266159 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266162 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 266165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266169 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1496:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 266169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 266172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266178 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266180 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266182 */     GIR_RootConstrainSelectedInstOperands,
     /* 266183 */     // GIR_Coverage, 8337,
     /* 266183 */     GIR_EraseRootFromParent_Done,
     /* 266184 */   // Label 5149: @266184
     /* 266184 */   GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(266231), // Rule ID 8338 //
     /* 266189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 266200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 266206 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 266209 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 266212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266216 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1496:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 266216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 266219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266225 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266227 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266229 */     GIR_RootConstrainSelectedInstOperands,
     /* 266230 */     // GIR_Coverage, 8338,
     /* 266230 */     GIR_EraseRootFromParent_Done,
     /* 266231 */   // Label 5150: @266231
     /* 266231 */   GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(266278), // Rule ID 8339 //
     /* 266236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 266247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 266253 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 266256 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 266259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266263 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1496:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 266263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 266266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266270 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266272 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266274 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266276 */     GIR_RootConstrainSelectedInstOperands,
     /* 266277 */     // GIR_Coverage, 8339,
     /* 266277 */     GIR_EraseRootFromParent_Done,
     /* 266278 */   // Label 5151: @266278
     /* 266278 */   GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(266325), // Rule ID 8340 //
     /* 266283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266303 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 266306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266310 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1496:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 266310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
     /* 266313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266315 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266317 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266319 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266321 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266323 */     GIR_RootConstrainSelectedInstOperands,
     /* 266324 */     // GIR_Coverage, 8340,
     /* 266324 */     GIR_EraseRootFromParent_Done,
     /* 266325 */   // Label 5152: @266325
     /* 266325 */   GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(266372), // Rule ID 8341 //
     /* 266330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 266341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 266347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 266350 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 266353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266357 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1496:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 266357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
     /* 266360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266366 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266368 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266370 */     GIR_RootConstrainSelectedInstOperands,
     /* 266371 */     // GIR_Coverage, 8341,
     /* 266371 */     GIR_EraseRootFromParent_Done,
     /* 266372 */   // Label 5153: @266372
     /* 266372 */   GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(266419), // Rule ID 8342 //
     /* 266377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 266385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266394 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266397 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 266400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266404 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1496:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 266404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_D),
     /* 266407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 266409 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266411 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266413 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266415 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266417 */     GIR_RootConstrainSelectedInstOperands,
     /* 266418 */     // GIR_Coverage, 8342,
     /* 266418 */     GIR_EraseRootFromParent_Done,
     /* 266419 */   // Label 5154: @266419
     /* 266419 */   GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(266466), // Rule ID 8343 //
     /* 266424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 266432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266441 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266444 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 266447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266451 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1486:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 266451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_H),
     /* 266454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266460 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266462 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266464 */     GIR_RootConstrainSelectedInstOperands,
     /* 266465 */     // GIR_Coverage, 8343,
     /* 266465 */     GIR_EraseRootFromParent_Done,
     /* 266466 */   // Label 5155: @266466
     /* 266466 */   GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(266513), // Rule ID 8344 //
     /* 266471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266474 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 266479 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266488 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266491 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 266494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266498 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1486:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 266498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_S),
     /* 266501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266507 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266509 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266511 */     GIR_RootConstrainSelectedInstOperands,
     /* 266512 */     // GIR_Coverage, 8344,
     /* 266512 */     GIR_EraseRootFromParent_Done,
     /* 266513 */   // Label 5156: @266513
     /* 266513 */   GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(266560), // Rule ID 8345 //
     /* 266518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 266526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266535 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266538 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 266541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266545 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1486:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 266545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_D),
     /* 266548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266550 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266552 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266554 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266556 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266558 */     GIR_RootConstrainSelectedInstOperands,
     /* 266559 */     // GIR_Coverage, 8345,
     /* 266559 */     GIR_EraseRootFromParent_Done,
     /* 266560 */   // Label 5157: @266560
     /* 266560 */   GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(266607), // Rule ID 8346 //
     /* 266565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 266573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266585 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 266588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266592 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1493:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 266592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_H),
     /* 266595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266601 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266603 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266605 */     GIR_RootConstrainSelectedInstOperands,
     /* 266606 */     // GIR_Coverage, 8346,
     /* 266606 */     GIR_EraseRootFromParent_Done,
     /* 266607 */   // Label 5158: @266607
     /* 266607 */   GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(266654), // Rule ID 8347 //
     /* 266612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 266620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266629 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266632 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 266635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266639 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1493:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 266639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_S),
     /* 266642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266648 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266650 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266652 */     GIR_RootConstrainSelectedInstOperands,
     /* 266653 */     // GIR_Coverage, 8347,
     /* 266653 */     GIR_EraseRootFromParent_Done,
     /* 266654 */   // Label 5159: @266654
     /* 266654 */   GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(266701), // Rule ID 8348 //
     /* 266659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 266667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266673 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266676 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266679 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 266682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266686 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1493:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 266686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_D),
     /* 266689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266691 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266693 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266695 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266697 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266699 */     GIR_RootConstrainSelectedInstOperands,
     /* 266700 */     // GIR_Coverage, 8348,
     /* 266700 */     GIR_EraseRootFromParent_Done,
     /* 266701 */   // Label 5160: @266701
     /* 266701 */   GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(266748), // Rule ID 8349 //
     /* 266706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 266714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266726 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 266729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266733 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1498:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 266733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_H),
     /* 266736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266740 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266742 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266744 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266746 */     GIR_RootConstrainSelectedInstOperands,
     /* 266747 */     // GIR_Coverage, 8349,
     /* 266747 */     GIR_EraseRootFromParent_Done,
     /* 266748 */   // Label 5161: @266748
     /* 266748 */   GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(266795), // Rule ID 8350 //
     /* 266753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266756 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 266761 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266764 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266767 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266770 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266773 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 266776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266780 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1498:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 266780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_S),
     /* 266783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266787 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266789 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266791 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266793 */     GIR_RootConstrainSelectedInstOperands,
     /* 266794 */     // GIR_Coverage, 8350,
     /* 266794 */     GIR_EraseRootFromParent_Done,
     /* 266795 */   // Label 5162: @266795
     /* 266795 */   GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(266842), // Rule ID 8351 //
     /* 266800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 266808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266817 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266820 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 266823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266827 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1498:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 266827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_D),
     /* 266830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266832 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266834 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266836 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266838 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266840 */     GIR_RootConstrainSelectedInstOperands,
     /* 266841 */     // GIR_Coverage, 8351,
     /* 266841 */     GIR_EraseRootFromParent_Done,
     /* 266842 */   // Label 5163: @266842
     /* 266842 */   GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(266889), // Rule ID 8352 //
     /* 266847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 266855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266864 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266867 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 266870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266874 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1480:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 266874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 266877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 266879 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266881 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266883 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266885 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266887 */     GIR_RootConstrainSelectedInstOperands,
     /* 266888 */     // GIR_Coverage, 8352,
     /* 266888 */     GIR_EraseRootFromParent_Done,
     /* 266889 */   // Label 5164: @266889
     /* 266889 */   GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(266936), // Rule ID 8355 //
     /* 266894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 266902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 266905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 266911 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 266914 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 266917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266921 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1480:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 266921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 266924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 266926 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266928 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266930 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266932 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266934 */     GIR_RootConstrainSelectedInstOperands,
     /* 266935 */     // GIR_Coverage, 8355,
     /* 266935 */     GIR_EraseRootFromParent_Done,
     /* 266936 */   // Label 5165: @266936
     /* 266936 */   GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(266983), // Rule ID 8358 //
     /* 266941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 266949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 266952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 266958 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 266961 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 266964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266968 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1480:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 266968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 266971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 266973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266977 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266979 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 266981 */     GIR_RootConstrainSelectedInstOperands,
     /* 266982 */     // GIR_Coverage, 8358,
     /* 266982 */     GIR_EraseRootFromParent_Done,
     /* 266983 */   // Label 5166: @266983
     /* 266983 */   GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(267030), // Rule ID 8361 //
     /* 266988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 266996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267005 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267008 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 267011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267015 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1480:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 267015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
     /* 267018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267020 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267022 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267024 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267026 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267028 */     GIR_RootConstrainSelectedInstOperands,
     /* 267029 */     // GIR_Coverage, 8361,
     /* 267029 */     GIR_EraseRootFromParent_Done,
     /* 267030 */   // Label 5167: @267030
     /* 267030 */   GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(267077), // Rule ID 8364 //
     /* 267035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 267043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 267046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 267052 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 267055 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 267058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267062 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1480:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 267062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
     /* 267065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267071 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267073 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267075 */     GIR_RootConstrainSelectedInstOperands,
     /* 267076 */     // GIR_Coverage, 8364,
     /* 267076 */     GIR_EraseRootFromParent_Done,
     /* 267077 */   // Label 5168: @267077
     /* 267077 */   GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(267124), // Rule ID 8367 //
     /* 267082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 267090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 267093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267099 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267102 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 267105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267109 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1480:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 267109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_D_UNDEF),
     /* 267112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267116 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267118 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267120 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267122 */     GIR_RootConstrainSelectedInstOperands,
     /* 267123 */     // GIR_Coverage, 8367,
     /* 267123 */     GIR_EraseRootFromParent_Done,
     /* 267124 */   // Label 5169: @267124
     /* 267124 */   GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(267171), // Rule ID 8370 //
     /* 267129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 267140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267146 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 267149 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 267152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267156 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1495:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 267156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 267159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267165 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267167 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267169 */     GIR_RootConstrainSelectedInstOperands,
     /* 267170 */     // GIR_Coverage, 8370,
     /* 267170 */     GIR_EraseRootFromParent_Done,
     /* 267171 */   // Label 5170: @267171
     /* 267171 */   GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(267218), // Rule ID 8373 //
     /* 267176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267179 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267184 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 267187 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267190 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 267193 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 267196 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 267199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267203 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1495:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 267203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 267206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267210 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267212 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267214 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267216 */     GIR_RootConstrainSelectedInstOperands,
     /* 267217 */     // GIR_Coverage, 8373,
     /* 267217 */     GIR_EraseRootFromParent_Done,
     /* 267218 */   // Label 5171: @267218
     /* 267218 */   GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(267265), // Rule ID 8376 //
     /* 267223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267226 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267231 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 267234 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267237 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 267240 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 267243 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 267246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267250 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1495:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 267250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 267253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267259 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267261 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267263 */     GIR_RootConstrainSelectedInstOperands,
     /* 267264 */     // GIR_Coverage, 8376,
     /* 267264 */     GIR_EraseRootFromParent_Done,
     /* 267265 */   // Label 5172: @267265
     /* 267265 */   GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(267312), // Rule ID 8379 //
     /* 267270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 267281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267287 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267290 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 267293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267297 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1495:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 267297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
     /* 267300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267306 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267308 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267310 */     GIR_RootConstrainSelectedInstOperands,
     /* 267311 */     // GIR_Coverage, 8379,
     /* 267311 */     GIR_EraseRootFromParent_Done,
     /* 267312 */   // Label 5173: @267312
     /* 267312 */   GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(267359), // Rule ID 8382 //
     /* 267317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 267328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267331 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 267334 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 267337 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 267340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267344 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1495:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 267344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
     /* 267347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267351 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267353 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267355 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267357 */     GIR_RootConstrainSelectedInstOperands,
     /* 267358 */     // GIR_Coverage, 8382,
     /* 267358 */     GIR_EraseRootFromParent_Done,
     /* 267359 */   // Label 5174: @267359
     /* 267359 */   GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(267406), // Rule ID 8385 //
     /* 267364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 267372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 267375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267381 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267384 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 267387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267391 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1495:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLA_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 267391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_D_UNDEF),
     /* 267394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267400 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267402 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267404 */     GIR_RootConstrainSelectedInstOperands,
     /* 267405 */     // GIR_Coverage, 8385,
     /* 267405 */     GIR_EraseRootFromParent_Done,
     /* 267406 */   // Label 5175: @267406
     /* 267406 */   GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(267453), // Rule ID 8388 //
     /* 267411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 267422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267428 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 267431 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 267434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267438 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1497:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 267438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 267441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267445 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267447 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267449 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267451 */     GIR_RootConstrainSelectedInstOperands,
     /* 267452 */     // GIR_Coverage, 8388,
     /* 267452 */     GIR_EraseRootFromParent_Done,
     /* 267453 */   // Label 5176: @267453
     /* 267453 */   GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(267500), // Rule ID 8390 //
     /* 267458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 267469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 267475 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 267478 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 267481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267485 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1497:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 267485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 267488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267492 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267494 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267496 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267498 */     GIR_RootConstrainSelectedInstOperands,
     /* 267499 */     // GIR_Coverage, 8390,
     /* 267499 */     GIR_EraseRootFromParent_Done,
     /* 267500 */   // Label 5177: @267500
     /* 267500 */   GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(267547), // Rule ID 8392 //
     /* 267505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 267516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267519 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 267522 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 267525 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 267528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267532 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1497:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 267532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 267535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267539 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267541 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267543 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267545 */     GIR_RootConstrainSelectedInstOperands,
     /* 267546 */     // GIR_Coverage, 8392,
     /* 267546 */     GIR_EraseRootFromParent_Done,
     /* 267547 */   // Label 5178: @267547
     /* 267547 */   GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(267594), // Rule ID 8394 //
     /* 267552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 267563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267569 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267572 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 267575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267579 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1497:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 267579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
     /* 267582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267588 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267590 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267592 */     GIR_RootConstrainSelectedInstOperands,
     /* 267593 */     // GIR_Coverage, 8394,
     /* 267593 */     GIR_EraseRootFromParent_Done,
     /* 267594 */   // Label 5179: @267594
     /* 267594 */   GIM_Try, /*On fail goto*//*Label 5180*/ GIMT_Encode4(267641), // Rule ID 8396 //
     /* 267599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 267610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 267616 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 267619 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 267622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267626 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1497:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 267626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
     /* 267629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267631 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267633 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267635 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267637 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267639 */     GIR_RootConstrainSelectedInstOperands,
     /* 267640 */     // GIR_Coverage, 8396,
     /* 267640 */     GIR_EraseRootFromParent_Done,
     /* 267641 */   // Label 5180: @267641
     /* 267641 */   GIM_Try, /*On fail goto*//*Label 5181*/ GIMT_Encode4(267688), // Rule ID 8398 //
     /* 267646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 267654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 267657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267663 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267666 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 267669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267673 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1497:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 267673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_D_UNDEF),
     /* 267676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 267678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267682 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267684 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 267686 */     GIR_RootConstrainSelectedInstOperands,
     /* 267687 */     // GIR_Coverage, 8398,
     /* 267687 */     GIR_EraseRootFromParent_Done,
     /* 267688 */   // Label 5181: @267688
     /* 267688 */   GIM_Reject,
     /* 267689 */ // Label 5040: @267689
     /* 267689 */ GIM_Reject,
     /* 267690 */ // Label 38: @267690
     /* 267690 */ GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(267768),
     /* 267695 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
     /* 267698 */   GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(267720), // Rule ID 78 //
     /* 267703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
     /* 267706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_tcommit),
     /* 267711 */     // (intrinsic_void 2176:{ *:[iPTR] })  =>  (TCOMMIT)
     /* 267711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TCOMMIT),
     /* 267714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 267718 */     GIR_RootConstrainSelectedInstOperands,
     /* 267719 */     // GIR_Coverage, 78,
     /* 267719 */     GIR_EraseRootFromParent_Done,
     /* 267720 */   // Label 5183: @267720
     /* 267720 */   GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(267745), // Rule ID 2390 //
     /* 267725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 267728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_setffr),
     /* 267733 */     // (intrinsic_void 1726:{ *:[iPTR] })  =>  (SETFFR:{ *:[i64] })
     /* 267733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SETFFR),
     /* 267736 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
     /* 267739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 267743 */     GIR_RootConstrainSelectedInstOperands,
     /* 267744 */     // GIR_Coverage, 2390,
     /* 267744 */     GIR_EraseRootFromParent_Done,
     /* 267745 */   // Label 5184: @267745
     /* 267745 */   GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(267767), // Rule ID 7216 //
     /* 267750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_clrex),
     /* 267755 */     // (intrinsic_void 510:{ *:[iPTR] })  =>  (CLREX 15:{ *:[i64] })
     /* 267755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLREX),
     /* 267758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 267761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 267765 */     GIR_RootConstrainSelectedInstOperands,
     /* 267766 */     // GIR_Coverage, 7216,
     /* 267766 */     GIR_EraseRootFromParent_Done,
     /* 267767 */   // Label 5185: @267767
     /* 267767 */   GIM_Reject,
     /* 267768 */ // Label 5182: @267768
     /* 267768 */ GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(268368),
     /* 267773 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /* 267776 */   GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(267808), // Rule ID 79 //
     /* 267781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
     /* 267784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_tcancel),
     /* 267789 */     // MIs[0] imm
     /* 267789 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 267792 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm64_0_65535),
     /* 267797 */     // (intrinsic_void 2175:{ *:[iPTR] }, (timm:{ *:[i64] })<<P:Predicate_timm64_0_65535>>:$imm)  =>  (TCANCEL (timm:{ *:[i64] }):$imm)
     /* 267797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TCANCEL),
     /* 267800 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 267802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 267806 */     GIR_RootConstrainSelectedInstOperands,
     /* 267807 */     // GIR_Coverage, 79,
     /* 267807 */     GIR_EraseRootFromParent_Done,
     /* 267808 */   // Label 5187: @267808
     /* 267808 */   GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(267833), // Rule ID 231 //
     /* 267813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_break),
     /* 267818 */     // MIs[0] imm
     /* 267818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 267821 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
     /* 267826 */     // (intrinsic_void 508:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm)  =>  (BRK (timm:{ *:[i32] }):$imm)
     /* 267826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 267829 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 267831 */     GIR_RootConstrainSelectedInstOperands,
     /* 267832 */     // GIR_Coverage, 231,
     /* 267832 */     GIR_EraseRootFromParent_Done,
     /* 267833 */   // Label 5188: @267833
     /* 267833 */   GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(267858), // Rule ID 232 //
     /* 267838 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hlt),
     /* 267843 */     // MIs[0] imm
     /* 267843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 267846 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
     /* 267851 */     // (intrinsic_void 567:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm)  =>  (HLT (timm:{ *:[i32] }):$imm)
     /* 267851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HLT),
     /* 267854 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 267856 */     GIR_RootConstrainSelectedInstOperands,
     /* 267857 */     // GIR_Coverage, 232,
     /* 267857 */     GIR_EraseRootFromParent_Done,
     /* 267858 */   // Label 5189: @267858
     /* 267858 */   GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(267890), // Rule ID 3651 //
     /* 267863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 267866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_zero),
     /* 267871 */     // MIs[0] imm
     /* 267871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 267874 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_255),
     /* 267879 */     // (intrinsic_void 1232:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm)  =>  (ZERO_M_PSEUDO (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm)
     /* 267879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZERO_M_PSEUDO),
     /* 267882 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 267884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 267888 */     GIR_RootConstrainSelectedInstOperands,
     /* 267889 */     // GIR_Coverage, 3651,
     /* 267889 */     GIR_EraseRootFromParent_Done,
     /* 267890 */   // Label 5190: @267890
     /* 267890 */   GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(267930), // Rule ID 16 //
     /* 267895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hint),
     /* 267900 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 267903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 267907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 267911 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_127),
     /* 267915 */     // MIs[1] Operand 1
     /* 267915 */     // No operand predicates
     /* 267915 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 267917 */     // (intrinsic_void 566:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
     /* 267917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HINT),
     /* 267920 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 267923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 267928 */     GIR_RootConstrainSelectedInstOperands,
     /* 267929 */     // GIR_Coverage, 16,
     /* 267929 */     GIR_EraseRootFromParent_Done,
     /* 267930 */   // Label 5191: @267930
     /* 267930 */   GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(267970), // Rule ID 17 //
     /* 267935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dmb),
     /* 267940 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 267943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 267947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 267951 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 267955 */     // MIs[1] Operand 1
     /* 267955 */     // No operand predicates
     /* 267955 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 267957 */     // (intrinsic_void 554:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DMB (imm:{ *:[i32] }):$CRm)
     /* 267957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 267960 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 267963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 267968 */     GIR_RootConstrainSelectedInstOperands,
     /* 267969 */     // GIR_Coverage, 17,
     /* 267969 */     GIR_EraseRootFromParent_Done,
     /* 267970 */   // Label 5192: @267970
     /* 267970 */   GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(268010), // Rule ID 18 //
     /* 267975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dsb),
     /* 267980 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 267983 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 267987 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 267991 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 267995 */     // MIs[1] Operand 1
     /* 267995 */     // No operand predicates
     /* 267995 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 267997 */     // (intrinsic_void 555:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DSB (imm:{ *:[i32] }):$CRm)
     /* 267997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DSB),
     /* 268000 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 268003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 268008 */     GIR_RootConstrainSelectedInstOperands,
     /* 268009 */     // GIR_Coverage, 18,
     /* 268009 */     GIR_EraseRootFromParent_Done,
     /* 268010 */   // Label 5193: @268010
     /* 268010 */   GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(268050), // Rule ID 19 //
     /* 268015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_isb),
     /* 268020 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 268023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 268027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 268031 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 268035 */     // MIs[1] Operand 1
     /* 268035 */     // No operand predicates
     /* 268035 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 268037 */     // (intrinsic_void 570:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (ISB (imm:{ *:[i32] }):$CRm)
     /* 268037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ISB),
     /* 268040 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 268043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 268048 */     GIR_RootConstrainSelectedInstOperands,
     /* 268049 */     // GIR_Coverage, 19,
     /* 268049 */     GIR_EraseRootFromParent_Done,
     /* 268050 */   // Label 5194: @268050
     /* 268050 */   GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(268074), // Rule ID 72 //
     /* 268055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpcr),
     /* 268060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268067 */     // (intrinsic_w_chain:{ *:[i64] } 563:{ *:[iPTR] })  =>  (MRS_FPCR:{ *:[i64] })
     /* 268067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPCR),
     /* 268070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268072 */     GIR_RootConstrainSelectedInstOperands,
     /* 268073 */     // GIR_Coverage, 72,
     /* 268073 */     GIR_EraseRootFromParent_Done,
     /* 268074 */   // Label 5195: @268074
     /* 268074 */   GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(268098), // Rule ID 74 //
     /* 268079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpsr),
     /* 268084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268091 */     // (intrinsic_w_chain:{ *:[i64] } 564:{ *:[iPTR] })  =>  (MRS_FPSR:{ *:[i64] })
     /* 268091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPSR),
     /* 268094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268096 */     GIR_RootConstrainSelectedInstOperands,
     /* 268097 */     // GIR_Coverage, 74,
     /* 268097 */     GIR_EraseRootFromParent_Done,
     /* 268098 */   // Label 5196: @268098
     /* 268098 */   GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(268129), // Rule ID 77 //
     /* 268103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
     /* 268106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_tstart),
     /* 268111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268118 */     // (intrinsic_w_chain:{ *:[i64] } 2177:{ *:[iPTR] })  =>  (TSTART:{ *:[i64] })
     /* 268118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TSTART),
     /* 268121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268123 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268127 */     GIR_RootConstrainSelectedInstOperands,
     /* 268128 */     // GIR_Coverage, 77,
     /* 268128 */     GIR_EraseRootFromParent_Done,
     /* 268129 */   // Label 5197: @268129
     /* 268129 */   GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(268156), // Rule ID 80 //
     /* 268134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
     /* 268137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ttest),
     /* 268142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268149 */     // (intrinsic_w_chain:{ *:[i64] } 2178:{ *:[iPTR] })  =>  (TTEST:{ *:[i64] })
     /* 268149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TTEST),
     /* 268152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268154 */     GIR_RootConstrainSelectedInstOperands,
     /* 268155 */     // GIR_Coverage, 80,
     /* 268155 */     GIR_EraseRootFromParent_Done,
     /* 268156 */   // Label 5198: @268156
     /* 268156 */   GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(268187), // Rule ID 2389 //
     /* 268161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 268164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr),
     /* 268169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 268172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 268176 */     // (intrinsic_w_chain:{ *:[nxv16i1] } 1676:{ *:[iPTR] })  =>  (RDFFR_P:{ *:[nxv16i1] })
     /* 268176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_P),
     /* 268179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 268181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268185 */     GIR_RootConstrainSelectedInstOperands,
     /* 268186 */     // GIR_Coverage, 2389,
     /* 268186 */     GIR_EraseRootFromParent_Done,
     /* 268187 */   // Label 5199: @268187
     /* 268187 */   GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(268227), // Rule ID 13077 //
     /* 268192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 268195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sme_get_tpidr2),
     /* 268200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268207 */     // (intrinsic_w_chain:{ *:[i64] } 901:{ *:[iPTR] })  =>  (MRS:{ *:[i64] }:{ *:[i32] } 56965:{ *:[i32] })
     /* 268207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
     /* 268210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268212 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
     /* 268222 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 268225 */     GIR_RootConstrainSelectedInstOperands,
     /* 268226 */     // GIR_Coverage, 13077,
     /* 268226 */     GIR_EraseRootFromParent_Done,
     /* 268227 */   // Label 5200: @268227
     /* 268227 */   GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(268261), // Rule ID 2391 //
     /* 268232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 268235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_wrffr),
     /* 268240 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 268243 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 268247 */     // (intrinsic_void 2156:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn)  =>  (WRFFR:{ *:[i64] } PPR8:{ *:[nxv16i1] }:$Pn)
     /* 268247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WRFFR),
     /* 268250 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pn
     /* 268252 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
     /* 268255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268259 */     GIR_RootConstrainSelectedInstOperands,
     /* 268260 */     // GIR_Coverage, 2391,
     /* 268260 */     GIR_EraseRootFromParent_Done,
     /* 268261 */   // Label 5201: @268261
     /* 268261 */   GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(268284), // Rule ID 73 //
     /* 268266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpcr),
     /* 268271 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 268274 */     // (intrinsic_void 790:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPCR i64:{ *:[i64] }:$val)
     /* 268274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPCR),
     /* 268277 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 268279 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPCR*/0,
     /* 268282 */     GIR_RootConstrainSelectedInstOperands,
     /* 268283 */     // GIR_Coverage, 73,
     /* 268283 */     GIR_EraseRootFromParent_Done,
     /* 268284 */   // Label 5202: @268284
     /* 268284 */   GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(268307), // Rule ID 75 //
     /* 268289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpsr),
     /* 268294 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 268297 */     // (intrinsic_void 792:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPSR i64:{ *:[i64] }:$val)
     /* 268297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPSR),
     /* 268300 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 268302 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPSR*/0,
     /* 268305 */     GIR_RootConstrainSelectedInstOperands,
     /* 268306 */     // GIR_Coverage, 75,
     /* 268306 */     GIR_EraseRootFromParent_Done,
     /* 268307 */   // Label 5203: @268307
     /* 268307 */   GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(268334), // Rule ID 76 //
     /* 268312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpmr),
     /* 268317 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 268320 */     // (intrinsic_void 791:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPMR i64:{ *:[i64] }:$val)
     /* 268320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPMR),
     /* 268323 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 268325 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPMR*/0,
     /* 268328 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268332 */     GIR_RootConstrainSelectedInstOperands,
     /* 268333 */     // GIR_Coverage, 76,
     /* 268333 */     GIR_EraseRootFromParent_Done,
     /* 268334 */   // Label 5204: @268334
     /* 268334 */   GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(268367), // Rule ID 13076 //
     /* 268339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 268342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_set_tpidr2),
     /* 268347 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 268350 */     // (intrinsic_void 976:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR 56965:{ *:[i32] }, GPR64:{ *:[i64] }:$val)
     /* 268350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR),
     /* 268353 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
     /* 268363 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 268365 */     GIR_RootConstrainSelectedInstOperands,
     /* 268366 */     // GIR_Coverage, 13076,
     /* 268366 */     GIR_EraseRootFromParent_Done,
     /* 268367 */   // Label 5205: @268367
     /* 268367 */   GIM_Reject,
     /* 268368 */ // Label 5186: @268368
     /* 268368 */ GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(269339),
     /* 268373 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 268376 */   GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(268452), // Rule ID 7182 //
     /* 268381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 268386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268393 */     // MIs[0] addr
     /* 268393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268397 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268401 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
     /* 268405 */     // (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268405 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268408 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
     /* 268412 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268417 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268421 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268425 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268435 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268441 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268446 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268451 */     // GIR_Coverage, 7182,
     /* 268451 */     GIR_EraseRootFromParent_Done,
     /* 268452 */   // Label 5207: @268452
     /* 268452 */   GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(268528), // Rule ID 7183 //
     /* 268457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 268462 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268469 */     // MIs[0] addr
     /* 268469 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268477 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
     /* 268481 */     // (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268481 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268484 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
     /* 268488 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268493 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268497 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268501 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268511 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268517 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268522 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268527 */     // GIR_Coverage, 7183,
     /* 268527 */     GIR_EraseRootFromParent_Done,
     /* 268528 */   // Label 5208: @268528
     /* 268528 */   GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(268604), // Rule ID 7184 //
     /* 268533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 268538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268545 */     // MIs[0] addr
     /* 268545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268553 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
     /* 268557 */     // (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268557 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268560 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
     /* 268564 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268569 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268573 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268577 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268587 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268593 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268598 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268603 */     // GIR_Coverage, 7184,
     /* 268603 */     GIR_EraseRootFromParent_Done,
     /* 268604 */   // Label 5209: @268604
     /* 268604 */   GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(268646), // Rule ID 7185 //
     /* 268609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 268614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268621 */     // MIs[0] addr
     /* 268621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268629 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_8),
     /* 268633 */     // (intrinsic_w_chain:{ *:[i64] } 576:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_8>>  =>  (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
     /* 268633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDXRX),
     /* 268636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268638 */     GIR_RootToRootCopy, /*OpIdx*/2, // addr
     /* 268640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268644 */     GIR_RootConstrainSelectedInstOperands,
     /* 268645 */     // GIR_Coverage, 7185,
     /* 268645 */     GIR_EraseRootFromParent_Done,
     /* 268646 */   // Label 5210: @268646
     /* 268646 */   GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(268722), // Rule ID 7189 //
     /* 268651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 268656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268663 */     // MIs[0] addr
     /* 268663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268667 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268671 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
     /* 268675 */     // (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268675 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268678 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
     /* 268682 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268687 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268691 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268695 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268705 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268711 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268716 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268721 */     // GIR_Coverage, 7189,
     /* 268721 */     GIR_EraseRootFromParent_Done,
     /* 268722 */   // Label 5211: @268722
     /* 268722 */   GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(268798), // Rule ID 7190 //
     /* 268727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 268732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268739 */     // MIs[0] addr
     /* 268739 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268747 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
     /* 268751 */     // (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268751 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268754 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
     /* 268758 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268763 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268767 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268771 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268781 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268787 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268792 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268797 */     // GIR_Coverage, 7190,
     /* 268797 */     GIR_EraseRootFromParent_Done,
     /* 268798 */   // Label 5212: @268798
     /* 268798 */   GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(268874), // Rule ID 7191 //
     /* 268803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 268808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268815 */     // MIs[0] addr
     /* 268815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268823 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
     /* 268827 */     // (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 268827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 268830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
     /* 268834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 268839 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 268843 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268847 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 268849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 268852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 268854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 268857 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 268860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 268863 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 268868 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 268873 */     // GIR_Coverage, 7191,
     /* 268873 */     GIR_EraseRootFromParent_Done,
     /* 268874 */   // Label 5213: @268874
     /* 268874 */   GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(268916), // Rule ID 7192 //
     /* 268879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 268884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268891 */     // MIs[0] addr
     /* 268891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 268895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 268899 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_8),
     /* 268903 */     // (intrinsic_w_chain:{ *:[i64] } 573:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_8>>  =>  (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
     /* 268903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAXRX),
     /* 268906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268908 */     GIR_RootToRootCopy, /*OpIdx*/2, // addr
     /* 268910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268914 */     GIR_RootConstrainSelectedInstOperands,
     /* 268915 */     // GIR_Coverage, 7192,
     /* 268915 */     GIR_EraseRootFromParent_Done,
     /* 268916 */   // Label 5214: @268916
     /* 268916 */   GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(268956), // Rule ID 20 //
     /* 268921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGCS),
     /* 268924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gcspopm),
     /* 268929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 268932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 268935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 268943 */     // (intrinsic_w_chain:{ *:[i64] } 561:{ *:[iPTR] }, GPR64:{ *:[i64] }:$src)  =>  (GCSPOPM:{ *:[i64] } GPR64:{ *:[i64] }:$src)
     /* 268943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GCSPOPM),
     /* 268946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 268948 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 268950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268954 */     GIR_RootConstrainSelectedInstOperands,
     /* 268955 */     // GIR_Coverage, 20,
     /* 268955 */     GIR_EraseRootFromParent_Done,
     /* 268956 */   // Label 5215: @268956
     /* 268956 */   GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(268996), // Rule ID 2388 //
     /* 268961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 268964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr_z),
     /* 268969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 268972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 268975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 268979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 268983 */     // (intrinsic_w_chain:{ *:[nxv16i1] } 1677:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (RDFFR_PPz:{ *:[nxv16i1] } PPRAny:{ *:[nxv16i1] }:$Pg)
     /* 268983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_PPz),
     /* 268986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 268988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 268990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 268994 */     GIR_RootConstrainSelectedInstOperands,
     /* 268995 */     // GIR_Coverage, 2388,
     /* 268995 */     GIR_EraseRootFromParent_Done,
     /* 268996 */   // Label 5216: @268996
     /* 268996 */   GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(269036), // Rule ID 2495 //
     /* 269001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 269004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl1),
     /* 269009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 269012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 269015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269019 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 269023 */     // (intrinsic_w_chain:{ *:[v8f16] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (F1CVTL:{ *:[v8f16] } V64:{ *:[v8i8] }:$Rn)
     /* 269023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTL),
     /* 269026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 269028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 269030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269034 */     GIR_RootConstrainSelectedInstOperands,
     /* 269035 */     // GIR_Coverage, 2495,
     /* 269035 */     GIR_EraseRootFromParent_Done,
     /* 269036 */   // Label 5217: @269036
     /* 269036 */   GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(269076), // Rule ID 2496 //
     /* 269041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 269044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl1),
     /* 269049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 269052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 269055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269063 */     // (intrinsic_w_chain:{ *:[v8f16] } 621:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (F1CVTL2:{ *:[v8f16] } V128:{ *:[v16i8] }:$Rn)
     /* 269063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTL2),
     /* 269066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 269068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 269070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269074 */     GIR_RootConstrainSelectedInstOperands,
     /* 269075 */     // GIR_Coverage, 2496,
     /* 269075 */     GIR_EraseRootFromParent_Done,
     /* 269076 */   // Label 5218: @269076
     /* 269076 */   GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(269116), // Rule ID 7063 //
     /* 269081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 269084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl2),
     /* 269089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 269092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 269095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269099 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 269103 */     // (intrinsic_w_chain:{ *:[v8f16] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (F2CVTL:{ *:[v8f16] } V64:{ *:[v8i8] }:$Rn)
     /* 269103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTL),
     /* 269106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 269108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 269110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269114 */     GIR_RootConstrainSelectedInstOperands,
     /* 269115 */     // GIR_Coverage, 7063,
     /* 269115 */     GIR_EraseRootFromParent_Done,
     /* 269116 */   // Label 5219: @269116
     /* 269116 */   GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(269156), // Rule ID 7064 //
     /* 269121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 269124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl2),
     /* 269129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 269132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 269135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 269143 */     // (intrinsic_w_chain:{ *:[v8f16] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (F2CVTL2:{ *:[v8f16] } V128:{ *:[v16i8] }:$Rn)
     /* 269143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTL2),
     /* 269146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 269148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 269150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269154 */     GIR_RootConstrainSelectedInstOperands,
     /* 269155 */     // GIR_Coverage, 7064,
     /* 269155 */     GIR_EraseRootFromParent_Done,
     /* 269156 */   // Label 5220: @269156
     /* 269156 */   GIM_Try, /*On fail goto*//*Label 5221*/ GIMT_Encode4(269192), // Rule ID 3604 //
     /* 269161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 269164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvt1),
     /* 269169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 269175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269179 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1501:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F1CVT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 269179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVT_ZZ_BtoH),
     /* 269182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 269184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269190 */     GIR_RootConstrainSelectedInstOperands,
     /* 269191 */     // GIR_Coverage, 3604,
     /* 269191 */     GIR_EraseRootFromParent_Done,
     /* 269192 */   // Label 5221: @269192
     /* 269192 */   GIM_Try, /*On fail goto*//*Label 5222*/ GIMT_Encode4(269230), // Rule ID 4034 //
     /* 269197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 269200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg_sp),
     /* 269205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 269208 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269215 */     // (intrinsic_w_chain:{ *:[i64] } 569:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm)  =>  (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm)
     /* 269215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRGstack),
     /* 269218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 269220 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::SP), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 269226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 269228 */     GIR_RootConstrainSelectedInstOperands,
     /* 269229 */     // GIR_Coverage, 4034,
     /* 269229 */     GIR_EraseRootFromParent_Done,
     /* 269230 */   // Label 5222: @269230
     /* 269230 */   GIM_Try, /*On fail goto*//*Label 5223*/ GIMT_Encode4(269266), // Rule ID 12802 //
     /* 269235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 269238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvt2),
     /* 269243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 269249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269253 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1503:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F2CVT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 269253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVT_ZZ_BtoH),
     /* 269256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 269258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269264 */     GIR_RootConstrainSelectedInstOperands,
     /* 269265 */     // GIR_Coverage, 12802,
     /* 269265 */     GIR_EraseRootFromParent_Done,
     /* 269266 */   // Label 5223: @269266
     /* 269266 */   GIM_Try, /*On fail goto*//*Label 5224*/ GIMT_Encode4(269302), // Rule ID 12803 //
     /* 269271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 269274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvtlt1),
     /* 269279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 269285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269289 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1507:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F1CVTLT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 269289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTLT_ZZ_BtoH),
     /* 269292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 269294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269300 */     GIR_RootConstrainSelectedInstOperands,
     /* 269301 */     // GIR_Coverage, 12803,
     /* 269301 */     GIR_EraseRootFromParent_Done,
     /* 269302 */   // Label 5224: @269302
     /* 269302 */   GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(269338), // Rule ID 12804 //
     /* 269307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 269310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvtlt2),
     /* 269315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 269321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269325 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1508:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F2CVTLT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 269325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTLT_ZZ_BtoH),
     /* 269328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 269330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 269336 */     GIR_RootConstrainSelectedInstOperands,
     /* 269337 */     // GIR_Coverage, 12804,
     /* 269337 */     GIR_EraseRootFromParent_Done,
     /* 269338 */   // Label 5225: @269338
     /* 269338 */   GIM_Reject,
     /* 269339 */ // Label 5206: @269339
     /* 269339 */ GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(273507),
     /* 269344 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 269347 */   GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(269444), // Rule ID 7200 //
     /* 269352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 269357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 269375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 269379 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 269383 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269387 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 269391 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 269395 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269400 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
     /* 269411 */     // MIs[0] addr
     /* 269411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269415 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269419 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 269423 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 269425 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 269425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 269428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 269434 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 269442 */     GIR_RootConstrainSelectedInstOperands,
     /* 269443 */     // GIR_Coverage, 7200,
     /* 269443 */     GIR_EraseRootFromParent_Done,
     /* 269444 */   // Label 5227: @269444
     /* 269444 */   GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(269541), // Rule ID 7201 //
     /* 269449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 269454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 269472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 269476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 269480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269484 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 269488 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 269492 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269497 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /* 269508 */     // MIs[0] addr
     /* 269508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269512 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269516 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 269520 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 269522 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 269522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 269525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 269531 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 269539 */     GIR_RootConstrainSelectedInstOperands,
     /* 269540 */     // GIR_Coverage, 7201,
     /* 269540 */     GIR_EraseRootFromParent_Done,
     /* 269541 */   // Label 5228: @269541
     /* 269541 */   GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(269638), // Rule ID 7210 //
     /* 269546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 269551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 269569 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 269573 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 269577 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269581 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 269585 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 269589 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269594 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
     /* 269605 */     // MIs[0] addr
     /* 269605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269609 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269613 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 269617 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 269619 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 269619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 269622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 269628 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 269636 */     GIR_RootConstrainSelectedInstOperands,
     /* 269637 */     // GIR_Coverage, 7210,
     /* 269637 */     GIR_EraseRootFromParent_Done,
     /* 269638 */   // Label 5229: @269638
     /* 269638 */   GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(269735), // Rule ID 7211 //
     /* 269643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 269648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 269666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 269670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 269674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269678 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 269682 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 269686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269691 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /* 269702 */     // MIs[0] addr
     /* 269702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269706 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269710 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 269714 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 269716 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 269716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 269719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269721 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 269725 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 269733 */     GIR_RootConstrainSelectedInstOperands,
     /* 269734 */     // GIR_Coverage, 7211,
     /* 269734 */     GIR_EraseRootFromParent_Done,
     /* 269735 */   // Label 5230: @269735
     /* 269735 */   GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(269846), // Rule ID 7203 //
     /* 269740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 269745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269755 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269759 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269763 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 269767 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 269771 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 269776 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
     /* 269787 */     // MIs[0] addr
     /* 269787 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269791 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269795 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 269799 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 269801 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 269801 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 269804 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 269808 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 269813 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 269819 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269824 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 269829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 269832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269834 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 269837 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 269844 */     GIR_RootConstrainSelectedInstOperands,
     /* 269845 */     // GIR_Coverage, 7203,
     /* 269845 */     GIR_EraseRootFromParent_Done,
     /* 269846 */   // Label 5231: @269846
     /* 269846 */   GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(269957), // Rule ID 7204 //
     /* 269851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 269856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 269878 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 269882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 269887 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 269898 */     // MIs[0] addr
     /* 269898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 269902 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 269906 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 269910 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 269912 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 269912 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 269915 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 269919 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 269924 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 269930 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269935 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 269940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 269943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 269945 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 269948 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 269950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 269955 */     GIR_RootConstrainSelectedInstOperands,
     /* 269956 */     // GIR_Coverage, 7204,
     /* 269956 */     GIR_EraseRootFromParent_Done,
     /* 269957 */   // Label 5232: @269957
     /* 269957 */   GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(270068), // Rule ID 7205 //
     /* 269962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 269967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 269970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 269973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 269977 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 269981 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 269985 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 269989 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 269993 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 269998 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /* 270009 */     // MIs[0] addr
     /* 270009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270013 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270017 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 270021 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270023 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 270023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 270026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 270030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 270035 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 270041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 270054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 270059 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270066 */     GIR_RootConstrainSelectedInstOperands,
     /* 270067 */     // GIR_Coverage, 7205,
     /* 270067 */     GIR_EraseRootFromParent_Done,
     /* 270068 */   // Label 5233: @270068
     /* 270068 */   GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(270179), // Rule ID 7213 //
     /* 270073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 270078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 270081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 270084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 270092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 270096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 270100 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 270104 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270109 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
     /* 270120 */     // MIs[0] addr
     /* 270120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270124 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270128 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 270132 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270134 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 270134 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 270137 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 270141 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 270146 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 270152 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270157 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 270165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270167 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 270170 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270177 */     GIR_RootConstrainSelectedInstOperands,
     /* 270178 */     // GIR_Coverage, 7213,
     /* 270178 */     GIR_EraseRootFromParent_Done,
     /* 270179 */   // Label 5234: @270179
     /* 270179 */   GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(270290), // Rule ID 7214 //
     /* 270184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 270189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 270192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 270195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 270203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 270207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 270211 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 270215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270220 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 270231 */     // MIs[0] addr
     /* 270231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270235 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270239 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 270243 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270245 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 270245 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 270248 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 270252 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 270257 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 270263 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270268 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 270276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270278 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 270281 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270288 */     GIR_RootConstrainSelectedInstOperands,
     /* 270289 */     // GIR_Coverage, 7214,
     /* 270289 */     GIR_EraseRootFromParent_Done,
     /* 270290 */   // Label 5235: @270290
     /* 270290 */   GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(270401), // Rule ID 7215 //
     /* 270295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 270300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 270303 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 270306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 270314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 270318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 270322 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 270326 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270331 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /* 270342 */     // MIs[0] addr
     /* 270342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270346 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270350 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 270354 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270356 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 270356 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 270359 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 270363 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 270368 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 270374 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 270384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 270387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270389 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 270392 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270399 */     GIR_RootConstrainSelectedInstOperands,
     /* 270400 */     // GIR_Coverage, 7215,
     /* 270400 */     GIR_EraseRootFromParent_Done,
     /* 270401 */   // Label 5236: @270401
     /* 270401 */   GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(270452), // Rule ID 70 //
     /* 270406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_fixedshadow),
     /* 270411 */     // MIs[0] ptr
     /* 270411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 270415 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 270419 */     // MIs[0] accessinfo
     /* 270419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 270422 */     // MIs[0] fixed_shadow
     /* 270422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 270425 */     // (intrinsic_void 194:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)  =>  (HWASAN_CHECK_MEMACCESS_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
     /* 270425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_FIXEDSHADOW),
     /* 270428 */     GIR_RootToRootCopy, /*OpIdx*/1, // ptr
     /* 270430 */     GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
     /* 270432 */     GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
     /* 270434 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 270437 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 270440 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 270443 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 270446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270450 */     GIR_RootConstrainSelectedInstOperands,
     /* 270451 */     // GIR_Coverage, 70,
     /* 270451 */     GIR_EraseRootFromParent_Done,
     /* 270452 */   // Label 5237: @270452
     /* 270452 */   GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(270503), // Rule ID 71 //
     /* 270457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules_fixedshadow),
     /* 270462 */     // MIs[0] ptr
     /* 270462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 270466 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 270470 */     // MIs[0] accessinfo
     /* 270470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 270473 */     // MIs[0] fixed_shadow
     /* 270473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 270476 */     // (intrinsic_void 196:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
     /* 270476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW),
     /* 270479 */     GIR_RootToRootCopy, /*OpIdx*/1, // ptr
     /* 270481 */     GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
     /* 270483 */     GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
     /* 270485 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 270488 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 270491 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 270494 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 270497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270501 */     GIR_RootConstrainSelectedInstOperands,
     /* 270502 */     // GIR_Coverage, 71,
     /* 270502 */     GIR_EraseRootFromParent_Done,
     /* 270503 */   // Label 5238: @270503
     /* 270503 */   GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(270572), // Rule ID 7202 //
     /* 270508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 270513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 270516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 270519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 270527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 270531 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 270535 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270540 */     // MIs[0] addr
     /* 270540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270548 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 270552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270554 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 270554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 270557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 270563 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270570 */     GIR_RootConstrainSelectedInstOperands,
     /* 270571 */     // GIR_Coverage, 7202,
     /* 270571 */     GIR_EraseRootFromParent_Done,
     /* 270572 */   // Label 5239: @270572
     /* 270572 */   GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(270641), // Rule ID 7212 //
     /* 270577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 270582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 270585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 270588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 270596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 270600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 270604 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 270609 */     // MIs[0] addr
     /* 270609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 270613 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 270617 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 270621 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 270623 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 270623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 270626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 270628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 270632 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 270634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 270639 */     GIR_RootConstrainSelectedInstOperands,
     /* 270640 */     // GIR_Coverage, 7212,
     /* 270640 */     GIR_EraseRootFromParent_Done,
     /* 270641 */   // Label 5240: @270641
     /* 270641 */   GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(270683), // Rule ID 3628 //
     /* 270646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 270649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_wide_1x1),
     /* 270654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 270657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270660 */     // MIs[0] tile
     /* 270660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270663 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 270668 */     // (intrinsic_void 1025:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 270668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_BToS_PSEUDO),
     /* 270671 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270681 */     GIR_RootConstrainSelectedInstOperands,
     /* 270682 */     // GIR_Coverage, 3628,
     /* 270682 */     GIR_EraseRootFromParent_Done,
     /* 270683 */   // Label 5241: @270683
     /* 270683 */   GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(270725), // Rule ID 3632 //
     /* 270688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 270691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_wide_1x1),
     /* 270696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270702 */     // MIs[0] tile
     /* 270702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270705 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 270710 */     // (intrinsic_void 1025:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4A_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 270710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_HToS_PSEUDO),
     /* 270713 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270717 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270723 */     GIR_RootConstrainSelectedInstOperands,
     /* 270724 */     // GIR_Coverage, 3632,
     /* 270724 */     GIR_EraseRootFromParent_Done,
     /* 270725 */   // Label 5242: @270725
     /* 270725 */   GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(270767), // Rule ID 3636 //
     /* 270730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 270733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_za64_wide_1x1),
     /* 270738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270744 */     // MIs[0] tile
     /* 270744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270747 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 270752 */     // (intrinsic_void 1029:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 270752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_HtoD_PSEUDO),
     /* 270755 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270759 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270765 */     GIR_RootConstrainSelectedInstOperands,
     /* 270766 */     // GIR_Coverage, 3636,
     /* 270766 */     GIR_EraseRootFromParent_Done,
     /* 270767 */   // Label 5243: @270767
     /* 270767 */   GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(270809), // Rule ID 3806 //
     /* 270772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16_HasSME_MOP4),
     /* 270775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 270780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270786 */     // MIs[0] tile
     /* 270786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270789 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 270794 */     // (intrinsic_void 922:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4A_MZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 270794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_H_PSEUDO),
     /* 270797 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270807 */     GIR_RootConstrainSelectedInstOperands,
     /* 270808 */     // GIR_Coverage, 3806,
     /* 270808 */     GIR_EraseRootFromParent_Done,
     /* 270809 */   // Label 5244: @270809
     /* 270809 */   GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(270851), // Rule ID 3810 //
     /* 270814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F32_HasSME_MOP4),
     /* 270817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmop4a_za32_1x1),
     /* 270822 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 270825 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270828 */     // MIs[0] tile
     /* 270828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270831 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 270836 */     // (intrinsic_void 885:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOP4A_MZZ_BtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 270836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_BtoS_PSEUDO),
     /* 270839 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270843 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270849 */     GIR_RootConstrainSelectedInstOperands,
     /* 270850 */     // GIR_Coverage, 3810,
     /* 270850 */     GIR_EraseRootFromParent_Done,
     /* 270851 */   // Label 5245: @270851
     /* 270851 */   GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(270893), // Rule ID 3814 //
     /* 270856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 270859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 270864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270870 */     // MIs[0] tile
     /* 270870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270873 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 270878 */     // (intrinsic_void 922:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOP4A_MZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 270878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_S_PSEUDO),
     /* 270881 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270891 */     GIR_RootConstrainSelectedInstOperands,
     /* 270892 */     // GIR_Coverage, 3814,
     /* 270892 */     GIR_EraseRootFromParent_Done,
     /* 270893 */   // Label 5246: @270893
     /* 270893 */   GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(270935), // Rule ID 3818 //
     /* 270898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64_HasSME_MOP4),
     /* 270901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 270906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 270912 */     // MIs[0] tile
     /* 270912 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270915 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 270920 */     // (intrinsic_void 922:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOP4A_MZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 270920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_D_PSEUDO),
     /* 270923 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270933 */     GIR_RootConstrainSelectedInstOperands,
     /* 270934 */     // GIR_Coverage, 3818,
     /* 270934 */     GIR_EraseRootFromParent_Done,
     /* 270935 */   // Label 5247: @270935
     /* 270935 */   GIM_Try, /*On fail goto*//*Label 5248*/ GIMT_Encode4(270977), // Rule ID 3822 //
     /* 270940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 270943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_wide_1x1),
     /* 270948 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270951 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270954 */     // MIs[0] tile
     /* 270954 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270957 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 270962 */     // (intrinsic_void 926:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4A_MZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 270962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_HtoS_PSEUDO),
     /* 270965 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 270967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 270969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 270971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 270975 */     GIR_RootConstrainSelectedInstOperands,
     /* 270976 */     // GIR_Coverage, 3822,
     /* 270976 */     GIR_EraseRootFromParent_Done,
     /* 270977 */   // Label 5248: @270977
     /* 270977 */   GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(271019), // Rule ID 3826 //
     /* 270982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F16_HasSME_MOP4),
     /* 270985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmop4a_za16_1x1),
     /* 270990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 270993 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270996 */     // MIs[0] tile
     /* 270996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 270999 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 271004 */     // (intrinsic_void 881:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOP4A_MZZ_BtoH_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_BtoH_PSEUDO),
     /* 271007 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271011 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271017 */     GIR_RootConstrainSelectedInstOperands,
     /* 271018 */     // GIR_Coverage, 3826,
     /* 271018 */     GIR_EraseRootFromParent_Done,
     /* 271019 */   // Label 5249: @271019
     /* 271019 */   GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(271061), // Rule ID 12881 //
     /* 271024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_wide_1x1),
     /* 271032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271035 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271038 */     // MIs[0] tile
     /* 271038 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271041 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271046 */     // (intrinsic_void 1033:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_BToS_PSEUDO),
     /* 271049 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271053 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271059 */     GIR_RootConstrainSelectedInstOperands,
     /* 271060 */     // GIR_Coverage, 12881,
     /* 271060 */     GIR_EraseRootFromParent_Done,
     /* 271061 */   // Label 5250: @271061
     /* 271061 */   GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(271103), // Rule ID 12885 //
     /* 271066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4a_wide_1x1),
     /* 271074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271080 */     // MIs[0] tile
     /* 271080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271083 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271088 */     // (intrinsic_void 1077:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4A_MZZ_BToS_PSEUDO),
     /* 271091 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271093 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271095 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271101 */     GIR_RootConstrainSelectedInstOperands,
     /* 271102 */     // GIR_Coverage, 12885,
     /* 271102 */     GIR_EraseRootFromParent_Done,
     /* 271103 */   // Label 5251: @271103
     /* 271103 */   GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(271145), // Rule ID 12889 //
     /* 271108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4s_wide_1x1),
     /* 271116 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271119 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271122 */     // MIs[0] tile
     /* 271122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271125 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271130 */     // (intrinsic_void 1085:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4S_MZZ_BToS_PSEUDO),
     /* 271133 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271135 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271137 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271143 */     GIR_RootConstrainSelectedInstOperands,
     /* 271144 */     // GIR_Coverage, 12889,
     /* 271144 */     GIR_EraseRootFromParent_Done,
     /* 271145 */   // Label 5252: @271145
     /* 271145 */   GIM_Try, /*On fail goto*//*Label 5253*/ GIMT_Encode4(271187), // Rule ID 12893 //
     /* 271150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4a_wide_1x1),
     /* 271158 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271161 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271164 */     // MIs[0] tile
     /* 271164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271167 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271172 */     // (intrinsic_void 1194:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4A_MZZ_BToS_PSEUDO),
     /* 271175 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271185 */     GIR_RootConstrainSelectedInstOperands,
     /* 271186 */     // GIR_Coverage, 12893,
     /* 271186 */     GIR_EraseRootFromParent_Done,
     /* 271187 */   // Label 5253: @271187
     /* 271187 */   GIM_Try, /*On fail goto*//*Label 5254*/ GIMT_Encode4(271229), // Rule ID 12897 //
     /* 271192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4s_wide_1x1),
     /* 271200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271206 */     // MIs[0] tile
     /* 271206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271209 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271214 */     // (intrinsic_void 1202:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4S_MZZ_BToS_PSEUDO),
     /* 271217 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271227 */     GIR_RootConstrainSelectedInstOperands,
     /* 271228 */     // GIR_Coverage, 12897,
     /* 271228 */     GIR_EraseRootFromParent_Done,
     /* 271229 */   // Label 5254: @271229
     /* 271229 */   GIM_Try, /*On fail goto*//*Label 5255*/ GIMT_Encode4(271271), // Rule ID 12901 //
     /* 271234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_wide_1x1),
     /* 271242 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271245 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271248 */     // MIs[0] tile
     /* 271248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271251 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271256 */     // (intrinsic_void 1160:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_BToS_PSEUDO),
     /* 271259 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271269 */     GIR_RootConstrainSelectedInstOperands,
     /* 271270 */     // GIR_Coverage, 12901,
     /* 271270 */     GIR_EraseRootFromParent_Done,
     /* 271271 */   // Label 5255: @271271
     /* 271271 */   GIM_Try, /*On fail goto*//*Label 5256*/ GIMT_Encode4(271313), // Rule ID 12905 //
     /* 271276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_wide_1x1),
     /* 271284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 271287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271290 */     // MIs[0] tile
     /* 271290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271293 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271298 */     // (intrinsic_void 1168:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 271298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_BToS_PSEUDO),
     /* 271301 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271311 */     GIR_RootConstrainSelectedInstOperands,
     /* 271312 */     // GIR_Coverage, 12905,
     /* 271312 */     GIR_EraseRootFromParent_Done,
     /* 271313 */   // Label 5256: @271313
     /* 271313 */   GIM_Try, /*On fail goto*//*Label 5257*/ GIMT_Encode4(271355), // Rule ID 12909 //
     /* 271318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_wide_1x1),
     /* 271326 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271329 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271332 */     // MIs[0] tile
     /* 271332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271335 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271340 */     // (intrinsic_void 1033:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4S_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_HToS_PSEUDO),
     /* 271343 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271353 */     GIR_RootConstrainSelectedInstOperands,
     /* 271354 */     // GIR_Coverage, 12909,
     /* 271354 */     GIR_EraseRootFromParent_Done,
     /* 271355 */   // Label 5257: @271355
     /* 271355 */   GIM_Try, /*On fail goto*//*Label 5258*/ GIMT_Encode4(271397), // Rule ID 12913 //
     /* 271360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_wide_1x1),
     /* 271368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271374 */     // MIs[0] tile
     /* 271374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271377 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271382 */     // (intrinsic_void 1160:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4A_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_HToS_PSEUDO),
     /* 271385 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271387 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271389 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271395 */     GIR_RootConstrainSelectedInstOperands,
     /* 271396 */     // GIR_Coverage, 12913,
     /* 271396 */     GIR_EraseRootFromParent_Done,
     /* 271397 */   // Label 5258: @271397
     /* 271397 */   GIM_Try, /*On fail goto*//*Label 5259*/ GIMT_Encode4(271439), // Rule ID 12917 //
     /* 271402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_wide_1x1),
     /* 271410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271416 */     // MIs[0] tile
     /* 271416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271419 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271424 */     // (intrinsic_void 1168:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4S_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_HToS_PSEUDO),
     /* 271427 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271437 */     GIR_RootConstrainSelectedInstOperands,
     /* 271438 */     // GIR_Coverage, 12917,
     /* 271438 */     GIR_EraseRootFromParent_Done,
     /* 271439 */   // Label 5259: @271439
     /* 271439 */   GIM_Try, /*On fail goto*//*Label 5260*/ GIMT_Encode4(271481), // Rule ID 12921 //
     /* 271444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_za64_wide_1x1),
     /* 271452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271455 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271458 */     // MIs[0] tile
     /* 271458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271461 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271466 */     // (intrinsic_void 1037:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_HtoD_PSEUDO),
     /* 271469 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271475 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271479 */     GIR_RootConstrainSelectedInstOperands,
     /* 271480 */     // GIR_Coverage, 12921,
     /* 271480 */     GIR_EraseRootFromParent_Done,
     /* 271481 */   // Label 5260: @271481
     /* 271481 */   GIM_Try, /*On fail goto*//*Label 5261*/ GIMT_Encode4(271523), // Rule ID 12925 //
     /* 271486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4a_za64_wide_1x1),
     /* 271494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271497 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271500 */     // MIs[0] tile
     /* 271500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271503 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271508 */     // (intrinsic_void 1081:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4A_MZZ_HtoD_PSEUDO),
     /* 271511 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271513 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271515 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271521 */     GIR_RootConstrainSelectedInstOperands,
     /* 271522 */     // GIR_Coverage, 12925,
     /* 271522 */     GIR_EraseRootFromParent_Done,
     /* 271523 */   // Label 5261: @271523
     /* 271523 */   GIM_Try, /*On fail goto*//*Label 5262*/ GIMT_Encode4(271565), // Rule ID 12929 //
     /* 271528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4s_za64_wide_1x1),
     /* 271536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271542 */     // MIs[0] tile
     /* 271542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271545 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271550 */     // (intrinsic_void 1089:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4S_MZZ_HtoD_PSEUDO),
     /* 271553 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271557 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271563 */     GIR_RootConstrainSelectedInstOperands,
     /* 271564 */     // GIR_Coverage, 12929,
     /* 271564 */     GIR_EraseRootFromParent_Done,
     /* 271565 */   // Label 5262: @271565
     /* 271565 */   GIM_Try, /*On fail goto*//*Label 5263*/ GIMT_Encode4(271607), // Rule ID 12933 //
     /* 271570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_za64_wide_1x1),
     /* 271578 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271581 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271584 */     // MIs[0] tile
     /* 271584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271587 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271592 */     // (intrinsic_void 1164:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_HtoD_PSEUDO),
     /* 271595 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271605 */     GIR_RootConstrainSelectedInstOperands,
     /* 271606 */     // GIR_Coverage, 12933,
     /* 271606 */     GIR_EraseRootFromParent_Done,
     /* 271607 */   // Label 5263: @271607
     /* 271607 */   GIM_Try, /*On fail goto*//*Label 5264*/ GIMT_Encode4(271649), // Rule ID 12937 //
     /* 271612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_za64_wide_1x1),
     /* 271620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271626 */     // MIs[0] tile
     /* 271626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271629 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271634 */     // (intrinsic_void 1172:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_HtoD_PSEUDO),
     /* 271637 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271639 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271641 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271647 */     GIR_RootConstrainSelectedInstOperands,
     /* 271648 */     // GIR_Coverage, 12937,
     /* 271648 */     GIR_EraseRootFromParent_Done,
     /* 271649 */   // Label 5264: @271649
     /* 271649 */   GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(271691), // Rule ID 12941 //
     /* 271654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4a_za64_wide_1x1),
     /* 271662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271668 */     // MIs[0] tile
     /* 271668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271671 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271676 */     // (intrinsic_void 1198:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4A_MZZ_HtoD_PSEUDO),
     /* 271679 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271683 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271689 */     GIR_RootConstrainSelectedInstOperands,
     /* 271690 */     // GIR_Coverage, 12941,
     /* 271690 */     GIR_EraseRootFromParent_Done,
     /* 271691 */   // Label 5265: @271691
     /* 271691 */   GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(271733), // Rule ID 12945 //
     /* 271696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 271699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4s_za64_wide_1x1),
     /* 271704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271710 */     // MIs[0] tile
     /* 271710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271713 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271718 */     // (intrinsic_void 1206:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 271718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4S_MZZ_HtoD_PSEUDO),
     /* 271721 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271731 */     GIR_RootConstrainSelectedInstOperands,
     /* 271732 */     // GIR_Coverage, 12945,
     /* 271732 */     GIR_EraseRootFromParent_Done,
     /* 271733 */   // Label 5266: @271733
     /* 271733 */   GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(271775), // Rule ID 13400 //
     /* 271738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_wide_1x1),
     /* 271746 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271752 */     // MIs[0] tile
     /* 271752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271755 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271760 */     // (intrinsic_void 934:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4S_MZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 271760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_HtoS_PSEUDO),
     /* 271763 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271767 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271773 */     GIR_RootConstrainSelectedInstOperands,
     /* 271774 */     // GIR_Coverage, 13400,
     /* 271774 */     GIR_EraseRootFromParent_Done,
     /* 271775 */   // Label 5267: @271775
     /* 271775 */   GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(271817), // Rule ID 13404 //
     /* 271780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 271783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 271788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 271791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271794 */     // MIs[0] tile
     /* 271794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 271802 */     // (intrinsic_void 930:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOP4S_MZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 271802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_S_PSEUDO),
     /* 271805 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271809 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271815 */     GIR_RootConstrainSelectedInstOperands,
     /* 271816 */     // GIR_Coverage, 13404,
     /* 271816 */     GIR_EraseRootFromParent_Done,
     /* 271817 */   // Label 5268: @271817
     /* 271817 */   GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(271859), // Rule ID 13408 //
     /* 271822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16_HasSME_MOP4),
     /* 271825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 271830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 271833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271836 */     // MIs[0] tile
     /* 271836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271839 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 271844 */     // (intrinsic_void 930:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4S_MZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 271844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_H_PSEUDO),
     /* 271847 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271851 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271857 */     GIR_RootConstrainSelectedInstOperands,
     /* 271858 */     // GIR_Coverage, 13408,
     /* 271858 */     GIR_EraseRootFromParent_Done,
     /* 271859 */   // Label 5269: @271859
     /* 271859 */   GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(271901), // Rule ID 13412 //
     /* 271864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64_HasSME_MOP4),
     /* 271867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 271872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 271875 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271878 */     // MIs[0] tile
     /* 271878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 271881 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 271886 */     // (intrinsic_void 930:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOP4S_MZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 271886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_D_PSEUDO),
     /* 271889 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 271891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 271893 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 271895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271899 */     GIR_RootConstrainSelectedInstOperands,
     /* 271900 */     // GIR_Coverage, 13412,
     /* 271900 */     GIR_EraseRootFromParent_Done,
     /* 271901 */   // Label 5270: @271901
     /* 271901 */   GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(271955), // Rule ID 8974 //
     /* 271906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 271909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 271914 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 271917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 271921 */     // MIs[0] base
     /* 271921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 271925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 271929 */     // MIs[0] prfop
     /* 271929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 271932 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 271937 */     // (intrinsic_void 1644:{ *:[iPTR] }, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 271937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_PRI),
     /* 271940 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 271942 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 271944 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 271946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 271949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 271953 */     GIR_RootConstrainSelectedInstOperands,
     /* 271954 */     // GIR_Coverage, 8974,
     /* 271954 */     GIR_EraseRootFromParent_Done,
     /* 271955 */   // Label 5271: @271955
     /* 271955 */   GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(272009), // Rule ID 8977 //
     /* 271960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 271963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 271968 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 271971 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 271975 */     // MIs[0] base
     /* 271975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 271979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 271983 */     // MIs[0] prfop
     /* 271983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 271986 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 271991 */     // (intrinsic_void 1644:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 271991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_PRI),
     /* 271994 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 271996 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 271998 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 272000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 272003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272007 */     GIR_RootConstrainSelectedInstOperands,
     /* 272008 */     // GIR_Coverage, 8977,
     /* 272008 */     GIR_EraseRootFromParent_Done,
     /* 272009 */   // Label 5272: @272009
     /* 272009 */   GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(272063), // Rule ID 8980 //
     /* 272014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 272017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 272022 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 272025 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 272029 */     // MIs[0] base
     /* 272029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 272033 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272037 */     // MIs[0] prfop
     /* 272037 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 272040 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 272045 */     // (intrinsic_void 1644:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 272045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_PRI),
     /* 272048 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 272050 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 272052 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 272054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 272057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272061 */     GIR_RootConstrainSelectedInstOperands,
     /* 272062 */     // GIR_Coverage, 8980,
     /* 272062 */     GIR_EraseRootFromParent_Done,
     /* 272063 */   // Label 5273: @272063
     /* 272063 */   GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(272117), // Rule ID 8983 //
     /* 272068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 272071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 272076 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 272079 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 272083 */     // MIs[0] base
     /* 272083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 272087 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272091 */     // MIs[0] prfop
     /* 272091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 272094 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 272099 */     // (intrinsic_void 1644:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 272099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_PRI),
     /* 272102 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 272104 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 272106 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 272108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 272111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272115 */     GIR_RootConstrainSelectedInstOperands,
     /* 272116 */     // GIR_Coverage, 8983,
     /* 272116 */     GIR_EraseRootFromParent_Done,
     /* 272117 */   // Label 5274: @272117
     /* 272117 */   GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(272171), // Rule ID 15 //
     /* 272122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_space),
     /* 272127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 272130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 272133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 272136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272140 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 272144 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 272148 */     // MIs[1] Operand 1
     /* 272148 */     // No operand predicates
     /* 272148 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272152 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 272154 */     // (intrinsic_w_chain:{ *:[i64] } 1242:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn)  =>  (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn)
     /* 272154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SPACE),
     /* 272157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 272159 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size
     /* 272162 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 272164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 272169 */     GIR_RootConstrainSelectedInstOperands,
     /* 272170 */     // GIR_Coverage, 15,
     /* 272170 */     GIR_EraseRootFromParent_Done,
     /* 272171 */   // Label 5275: @272171
     /* 272171 */   GIM_Try, /*On fail goto*//*Label 5276*/ GIMT_Encode4(272239), // Rule ID 68 //
     /* 272176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess),
     /* 272181 */     // MIs[0] Operand 1
     /* 272181 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 272185 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID),
     /* 272189 */     // MIs[0] ptr
     /* 272189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 272193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 272197 */     // MIs[0] accessinfo
     /* 272197 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 272200 */     // (intrinsic_void 193:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
     /* 272200 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272204 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X9), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272210 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9
     /* 272214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS),
     /* 272217 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 272219 */     GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
     /* 272221 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 272224 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 272227 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 272230 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 272233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272237 */     GIR_RootConstrainSelectedInstOperands,
     /* 272238 */     // GIR_Coverage, 68,
     /* 272238 */     GIR_EraseRootFromParent_Done,
     /* 272239 */   // Label 5276: @272239
     /* 272239 */   GIM_Try, /*On fail goto*//*Label 5277*/ GIMT_Encode4(272307), // Rule ID 69 //
     /* 272244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules),
     /* 272249 */     // MIs[0] Operand 1
     /* 272249 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 272253 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64common_and_GPR64noipRegClassID),
     /* 272257 */     // MIs[0] ptr
     /* 272257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 272261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 272265 */     // MIs[0] accessinfo
     /* 272265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 272268 */     // (intrinsic_void 195:{ *:[iPTR] }, X20:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
     /* 272268 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272272 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X20), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272278 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X20
     /* 272282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES),
     /* 272285 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 272287 */     GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
     /* 272289 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 272292 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 272295 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 272298 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 272301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272305 */     GIR_RootConstrainSelectedInstOperands,
     /* 272306 */     // GIR_Coverage, 69,
     /* 272306 */     GIR_EraseRootFromParent_Done,
     /* 272307 */   // Label 5277: @272307
     /* 272307 */   GIM_Try, /*On fail goto*//*Label 5278*/ GIMT_Encode4(272387), // Rule ID 7196 //
     /* 272312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 272317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272327 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272331 */     // MIs[0] addr
     /* 272331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272335 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272339 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 272343 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272343 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272346 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272350 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272355 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272361 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272366 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 272374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272376 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272379 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272381 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272385 */     GIR_RootConstrainSelectedInstOperands,
     /* 272386 */     // GIR_Coverage, 7196,
     /* 272386 */     GIR_EraseRootFromParent_Done,
     /* 272387 */   // Label 5278: @272387
     /* 272387 */   GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(272467), // Rule ID 7197 //
     /* 272392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 272397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272411 */     // MIs[0] addr
     /* 272411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272415 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272419 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 272423 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272423 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272426 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272430 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272435 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272441 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272446 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 272454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272456 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272459 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272465 */     GIR_RootConstrainSelectedInstOperands,
     /* 272466 */     // GIR_Coverage, 7197,
     /* 272466 */     GIR_EraseRootFromParent_Done,
     /* 272467 */   // Label 5279: @272467
     /* 272467 */   GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(272547), // Rule ID 7198 //
     /* 272472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 272477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272487 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272491 */     // MIs[0] addr
     /* 272491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272495 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272499 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 272503 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272503 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272506 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272510 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272515 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272521 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 272534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272536 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272539 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272545 */     GIR_RootConstrainSelectedInstOperands,
     /* 272546 */     // GIR_Coverage, 7198,
     /* 272546 */     GIR_EraseRootFromParent_Done,
     /* 272547 */   // Label 5280: @272547
     /* 272547 */   GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(272598), // Rule ID 7199 //
     /* 272552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 272557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272567 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272571 */     // MIs[0] addr
     /* 272571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272575 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272579 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_8),
     /* 272583 */     // (intrinsic_w_chain:{ *:[i32] } 1251:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_8>>  =>  (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 272583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRX),
     /* 272586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272588 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /* 272590 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272596 */     GIR_RootConstrainSelectedInstOperands,
     /* 272597 */     // GIR_Coverage, 7199,
     /* 272597 */     GIR_EraseRootFromParent_Done,
     /* 272598 */   // Label 5281: @272598
     /* 272598 */   GIM_Try, /*On fail goto*//*Label 5282*/ GIMT_Encode4(272678), // Rule ID 7206 //
     /* 272603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 272608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272622 */     // MIs[0] addr
     /* 272622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272626 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272630 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 272634 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272634 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272637 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272641 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272646 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272652 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272657 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 272665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272667 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272670 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272676 */     GIR_RootConstrainSelectedInstOperands,
     /* 272677 */     // GIR_Coverage, 7206,
     /* 272677 */     GIR_EraseRootFromParent_Done,
     /* 272678 */   // Label 5282: @272678
     /* 272678 */   GIM_Try, /*On fail goto*//*Label 5283*/ GIMT_Encode4(272758), // Rule ID 7207 //
     /* 272683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 272688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272702 */     // MIs[0] addr
     /* 272702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272706 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272710 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 272714 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272714 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272717 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272721 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272726 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272732 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272737 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 272745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272747 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272750 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272756 */     GIR_RootConstrainSelectedInstOperands,
     /* 272757 */     // GIR_Coverage, 7207,
     /* 272757 */     GIR_EraseRootFromParent_Done,
     /* 272758 */   // Label 5283: @272758
     /* 272758 */   GIM_Try, /*On fail goto*//*Label 5284*/ GIMT_Encode4(272838), // Rule ID 7208 //
     /* 272763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 272768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272778 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272782 */     // MIs[0] addr
     /* 272782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272786 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272790 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 272794 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 272794 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 272797 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 272801 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 272806 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 272812 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272817 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 272825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272827 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 272830 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272836 */     GIR_RootConstrainSelectedInstOperands,
     /* 272837 */     // GIR_Coverage, 7208,
     /* 272837 */     GIR_EraseRootFromParent_Done,
     /* 272838 */   // Label 5284: @272838
     /* 272838 */   GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(272889), // Rule ID 7209 //
     /* 272843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 272848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 272851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 272854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 272858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 272862 */     // MIs[0] addr
     /* 272862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 272866 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 272870 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_8),
     /* 272874 */     // (intrinsic_w_chain:{ *:[i32] } 1249:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_8>>  =>  (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 272874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRX),
     /* 272877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 272879 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /* 272881 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 272883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272887 */     GIR_RootConstrainSelectedInstOperands,
     /* 272888 */     // GIR_Coverage, 7209,
     /* 272888 */     GIR_EraseRootFromParent_Done,
     /* 272889 */   // Label 5285: @272889
     /* 272889 */   GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(272938), // Rule ID 2488 //
     /* 272894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 272897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 272902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 272905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 272908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 272911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 272915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 272919 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 272923 */     // (intrinsic_w_chain:{ *:[v8i8] } 623:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCVTN_F16v8f8:{ *:[v8i8] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 272923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F16v8f8),
     /* 272926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 272928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 272930 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 272932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272936 */     GIR_RootConstrainSelectedInstOperands,
     /* 272937 */     // GIR_Coverage, 2488,
     /* 272937 */     GIR_EraseRootFromParent_Done,
     /* 272938 */   // Label 5286: @272938
     /* 272938 */   GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(272987), // Rule ID 2489 //
     /* 272943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 272946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 272951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 272954 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 272957 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 272960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 272964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 272968 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 272972 */     // (intrinsic_w_chain:{ *:[v16i8] } 623:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTN_F16v16f8:{ *:[v16i8] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 272972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F16v16f8),
     /* 272975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 272977 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 272979 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 272981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 272985 */     GIR_RootConstrainSelectedInstOperands,
     /* 272986 */     // GIR_Coverage, 2489,
     /* 272986 */     GIR_EraseRootFromParent_Done,
     /* 272987 */   // Label 5287: @272987
     /* 272987 */   GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(273036), // Rule ID 2490 //
     /* 272992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 272995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 273000 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 273003 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 273006 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 273009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 273013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 273017 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 273021 */     // (intrinsic_w_chain:{ *:[v8i8] } 623:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCVTN_F32v8f8:{ *:[v8i8] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 273021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F32v8f8),
     /* 273024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 273026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 273028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 273030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273034 */     GIR_RootConstrainSelectedInstOperands,
     /* 273035 */     // GIR_Coverage, 2490,
     /* 273035 */     GIR_EraseRootFromParent_Done,
     /* 273036 */   // Label 5288: @273036
     /* 273036 */   GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(273089), // Rule ID 8860 //
     /* 273041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
     /* 273049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273063 */     // MIs[0] base
     /* 273063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273071 */     // (intrinsic_w_chain:{ *:[nxv4i32] } 1577:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1W_Q_IMM:{ *:[nxv4i32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
     /* 273074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 273076 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273078 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273087 */     GIR_RootConstrainSelectedInstOperands,
     /* 273088 */     // GIR_Coverage, 8860,
     /* 273088 */     GIR_EraseRootFromParent_Done,
     /* 273089 */   // Label 5289: @273089
     /* 273089 */   GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(273142), // Rule ID 8863 //
     /* 273094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
     /* 273102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273112 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273116 */     // MIs[0] base
     /* 273116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273120 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273124 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1577:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1W_Q_IMM:{ *:[nxv4f32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
     /* 273127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 273129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273131 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273140 */     GIR_RootConstrainSelectedInstOperands,
     /* 273141 */     // GIR_Coverage, 8863,
     /* 273141 */     GIR_EraseRootFromParent_Done,
     /* 273142 */   // Label 5290: @273142
     /* 273142 */   GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(273195), // Rule ID 8872 //
     /* 273147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273150 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
     /* 273155 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273158 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273169 */     // MIs[0] base
     /* 273169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273173 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273177 */     // (intrinsic_w_chain:{ *:[nxv2i64] } 1576:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1D_Q_IMM:{ *:[nxv2i64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
     /* 273180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 273182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273184 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273189 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273193 */     GIR_RootConstrainSelectedInstOperands,
     /* 273194 */     // GIR_Coverage, 8872,
     /* 273194 */     GIR_EraseRootFromParent_Done,
     /* 273195 */   // Label 5291: @273195
     /* 273195 */   GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(273248), // Rule ID 8875 //
     /* 273200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
     /* 273208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273218 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273222 */     // MIs[0] base
     /* 273222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273226 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273230 */     // (intrinsic_w_chain:{ *:[nxv2f64] } 1576:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1D_Q_IMM:{ *:[nxv2f64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
     /* 273233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 273235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273237 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273246 */     GIR_RootConstrainSelectedInstOperands,
     /* 273247 */     // GIR_Coverage, 8875,
     /* 273247 */     GIR_EraseRootFromParent_Done,
     /* 273248 */   // Label 5292: @273248
     /* 273248 */   GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(273294), // Rule ID 137 //
     /* 273253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 273256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg),
     /* 273261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 273264 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 273267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273271 */     // MIs[0] Rn
     /* 273271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 273275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273279 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 273283 */     // (intrinsic_w_chain:{ *:[i64] } 568:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 273283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRG),
     /* 273286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 273288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 273290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 273292 */     GIR_RootConstrainSelectedInstOperands,
     /* 273293 */     // GIR_Coverage, 137,
     /* 273293 */     GIR_EraseRootFromParent_Done,
     /* 273294 */   // Label 5293: @273294
     /* 273294 */   GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(273347), // Rule ID 8866 //
     /* 273299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
     /* 273307 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 273310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273313 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273317 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273321 */     // MIs[0] base
     /* 273321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273329 */     // (intrinsic_void 1897:{ *:[iPTR] }, ZPR128:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1W_Q_IMM Z_q:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
     /* 273332 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 273334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273336 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273345 */     GIR_RootConstrainSelectedInstOperands,
     /* 273346 */     // GIR_Coverage, 8866,
     /* 273346 */     GIR_EraseRootFromParent_Done,
     /* 273347 */   // Label 5294: @273347
     /* 273347 */   GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(273400), // Rule ID 8869 //
     /* 273352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
     /* 273360 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 273363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273366 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273370 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273374 */     // MIs[0] base
     /* 273374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273378 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273382 */     // (intrinsic_void 1897:{ *:[iPTR] }, ZPR128:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1W_Q_IMM Z_q:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
     /* 273385 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 273387 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273389 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273398 */     GIR_RootConstrainSelectedInstOperands,
     /* 273399 */     // GIR_Coverage, 8869,
     /* 273399 */     GIR_EraseRootFromParent_Done,
     /* 273400 */   // Label 5295: @273400
     /* 273400 */   GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(273453), // Rule ID 8878 //
     /* 273405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
     /* 273413 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 273416 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273427 */     // MIs[0] base
     /* 273427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273431 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273435 */     // (intrinsic_void 1893:{ *:[iPTR] }, ZPR128:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1D_Q_IMM Z_q:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
     /* 273438 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 273440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273442 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273451 */     GIR_RootConstrainSelectedInstOperands,
     /* 273452 */     // GIR_Coverage, 8878,
     /* 273452 */     GIR_EraseRootFromParent_Done,
     /* 273453 */   // Label 5296: @273453
     /* 273453 */   GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(273506), // Rule ID 8881 //
     /* 273458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 273461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
     /* 273466 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 273469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 273472 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273476 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273480 */     // MIs[0] base
     /* 273480 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 273484 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273488 */     // (intrinsic_void 1893:{ *:[iPTR] }, ZPR128:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1D_Q_IMM Z_q:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 273488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
     /* 273491 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 273493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 273495 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 273497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 273500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273504 */     GIR_RootConstrainSelectedInstOperands,
     /* 273505 */     // GIR_Coverage, 8881,
     /* 273505 */     GIR_EraseRootFromParent_Done,
     /* 273506 */   // Label 5297: @273506
     /* 273506 */   GIM_Reject,
     /* 273507 */ // Label 5226: @273507
     /* 273507 */ GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(276212),
     /* 273512 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /* 273515 */   GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(273586), // Rule ID 3435 //
     /* 273520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 273523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
     /* 273528 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 273531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 273534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 273537 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273541 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273545 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 273549 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 273553 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 273557 */     // MIs[1] Operand 1
     /* 273557 */     // No operand predicates
     /* 273557 */     // MIs[0] prfop
     /* 273557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 273560 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 273565 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 273567 */     // (intrinsic_void 1646:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 273567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_PZI),
     /* 273570 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 273572 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 273574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 273576 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 273579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 273584 */     GIR_RootConstrainSelectedInstOperands,
     /* 273585 */     // GIR_Coverage, 3435,
     /* 273585 */     GIR_EraseRootFromParent_Done,
     /* 273586 */   // Label 5299: @273586
     /* 273586 */   GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(273657), // Rule ID 3448 //
     /* 273591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 273594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
     /* 273599 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 273602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 273605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 273608 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273612 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273616 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 273620 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 273624 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 273628 */     // MIs[1] Operand 1
     /* 273628 */     // No operand predicates
     /* 273628 */     // MIs[0] prfop
     /* 273628 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 273631 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 273636 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 273638 */     // (intrinsic_void 1646:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 273638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_PZI),
     /* 273641 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 273643 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 273645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 273647 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 273650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 273655 */     GIR_RootConstrainSelectedInstOperands,
     /* 273656 */     // GIR_Coverage, 3448,
     /* 273656 */     GIR_EraseRootFromParent_Done,
     /* 273657 */   // Label 5300: @273657
     /* 273657 */   GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(273716), // Rule ID 3640 //
     /* 273662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 273665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
     /* 273670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273673 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 273676 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273679 */     // MIs[0] tile
     /* 273679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 273682 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 273687 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273691 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273695 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273699 */     // (intrinsic_void 807:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn)  =>  (ADDHA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
     /* 273699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_S_PSEUDO_S),
     /* 273702 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 273704 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 273706 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 273708 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 273710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273714 */     GIR_RootConstrainSelectedInstOperands,
     /* 273715 */     // GIR_Coverage, 3640,
     /* 273715 */     GIR_EraseRootFromParent_Done,
     /* 273716 */   // Label 5301: @273716
     /* 273716 */   GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(273775), // Rule ID 3641 //
     /* 273721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 273724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
     /* 273729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 273735 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273738 */     // MIs[0] tile
     /* 273738 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 273741 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 273746 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273750 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273754 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273758 */     // (intrinsic_void 807:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn)  =>  (ADDHA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
     /* 273758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_D_PSEUDO_D),
     /* 273761 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 273763 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 273765 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 273767 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 273769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273773 */     GIR_RootConstrainSelectedInstOperands,
     /* 273774 */     // GIR_Coverage, 3641,
     /* 273774 */     GIR_EraseRootFromParent_Done,
     /* 273775 */   // Label 5302: @273775
     /* 273775 */   GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(273834), // Rule ID 12862 //
     /* 273780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 273783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
     /* 273788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 273794 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273797 */     // MIs[0] tile
     /* 273797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 273800 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 273805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273809 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273813 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273817 */     // (intrinsic_void 808:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn)  =>  (ADDVA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
     /* 273817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_S_PSEUDO_S),
     /* 273820 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 273822 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 273824 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 273826 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 273828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273832 */     GIR_RootConstrainSelectedInstOperands,
     /* 273833 */     // GIR_Coverage, 12862,
     /* 273833 */     GIR_EraseRootFromParent_Done,
     /* 273834 */   // Label 5303: @273834
     /* 273834 */   GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(273893), // Rule ID 12863 //
     /* 273839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 273842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
     /* 273847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 273853 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273856 */     // MIs[0] tile
     /* 273856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 273859 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 273864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273868 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273872 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273876 */     // (intrinsic_void 808:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn)  =>  (ADDVA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
     /* 273876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_D_PSEUDO_D),
     /* 273879 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 273881 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 273883 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 273885 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 273887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273891 */     GIR_RootConstrainSelectedInstOperands,
     /* 273892 */     // GIR_Coverage, 12863,
     /* 273892 */     GIR_EraseRootFromParent_Done,
     /* 273893 */   // Label 5304: @273893
     /* 273893 */   GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(273953), // Rule ID 3433 //
     /* 273898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 273901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
     /* 273906 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 273909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273912 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273916 */     // MIs[0] Rn
     /* 273916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 273920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273924 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273928 */     // MIs[0] prfop
     /* 273928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 273931 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 273936 */     // (intrinsic_void 1648:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm)
     /* 273936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_UXTW_SCALED),
     /* 273939 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 273941 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 273943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 273945 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 273947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 273951 */     GIR_RootConstrainSelectedInstOperands,
     /* 273952 */     // GIR_Coverage, 3433,
     /* 273952 */     GIR_EraseRootFromParent_Done,
     /* 273953 */   // Label 5305: @273953
     /* 273953 */   GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(274013), // Rule ID 3434 //
     /* 273958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 273961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
     /* 273966 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 273969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273972 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 273976 */     // MIs[0] Rn
     /* 273976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 273980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 273984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273988 */     // MIs[0] prfop
     /* 273988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 273991 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 273996 */     // (intrinsic_void 1647:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm)
     /* 273996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_SXTW_SCALED),
     /* 273999 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274001 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274011 */     GIR_RootConstrainSelectedInstOperands,
     /* 274012 */     // GIR_Coverage, 3434,
     /* 274012 */     GIR_EraseRootFromParent_Done,
     /* 274013 */   // Label 5306: @274013
     /* 274013 */   GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(274073), // Rule ID 3445 //
     /* 274018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
     /* 274026 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274032 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274036 */     // MIs[0] Rn
     /* 274036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274044 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274048 */     // MIs[0] prfop
     /* 274048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274051 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274056 */     // (intrinsic_void 1648:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm)
     /* 274056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_UXTW_SCALED),
     /* 274059 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274061 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274063 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274065 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274071 */     GIR_RootConstrainSelectedInstOperands,
     /* 274072 */     // GIR_Coverage, 3445,
     /* 274072 */     GIR_EraseRootFromParent_Done,
     /* 274073 */   // Label 5307: @274073
     /* 274073 */   GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(274133), // Rule ID 3446 //
     /* 274078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
     /* 274086 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274092 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274096 */     // MIs[0] Rn
     /* 274096 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274108 */     // MIs[0] prfop
     /* 274108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274111 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274116 */     // (intrinsic_void 1647:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm)
     /* 274116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SXTW_SCALED),
     /* 274119 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274121 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274131 */     GIR_RootConstrainSelectedInstOperands,
     /* 274132 */     // GIR_Coverage, 3446,
     /* 274132 */     GIR_EraseRootFromParent_Done,
     /* 274133 */   // Label 5308: @274133
     /* 274133 */   GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(274193), // Rule ID 3447 //
     /* 274138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_index),
     /* 274146 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274156 */     // MIs[0] Rn
     /* 274156 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274160 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274164 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274168 */     // MIs[0] prfop
     /* 274168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274171 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274176 */     // (intrinsic_void 1645:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm)
     /* 274176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SCALED),
     /* 274179 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274181 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274185 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274191 */     GIR_RootConstrainSelectedInstOperands,
     /* 274192 */     // GIR_Coverage, 3447,
     /* 274192 */     GIR_EraseRootFromParent_Done,
     /* 274193 */   // Label 5309: @274193
     /* 274193 */   GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(274253), // Rule ID 8986 //
     /* 274198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
     /* 274206 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274212 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274216 */     // MIs[0] Rn
     /* 274216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274224 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274228 */     // MIs[0] prfop
     /* 274228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274231 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274236 */     // (intrinsic_void 1656:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm)
     /* 274236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_UXTW_SCALED),
     /* 274239 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274241 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274251 */     GIR_RootConstrainSelectedInstOperands,
     /* 274252 */     // GIR_Coverage, 8986,
     /* 274252 */     GIR_EraseRootFromParent_Done,
     /* 274253 */   // Label 5310: @274253
     /* 274253 */   GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(274313), // Rule ID 8987 //
     /* 274258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
     /* 274266 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274272 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274276 */     // MIs[0] Rn
     /* 274276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274284 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274288 */     // MIs[0] prfop
     /* 274288 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274291 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274296 */     // (intrinsic_void 1655:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm)
     /* 274296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_SXTW_SCALED),
     /* 274299 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274301 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274311 */     GIR_RootConstrainSelectedInstOperands,
     /* 274312 */     // GIR_Coverage, 8987,
     /* 274312 */     GIR_EraseRootFromParent_Done,
     /* 274313 */   // Label 5311: @274313
     /* 274313 */   GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(274373), // Rule ID 8988 //
     /* 274318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
     /* 274326 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274329 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274332 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274336 */     // MIs[0] Rn
     /* 274336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274340 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274344 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274348 */     // MIs[0] prfop
     /* 274348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274351 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274356 */     // (intrinsic_void 1660:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm)
     /* 274356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_UXTW_SCALED),
     /* 274359 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274361 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274371 */     GIR_RootConstrainSelectedInstOperands,
     /* 274372 */     // GIR_Coverage, 8988,
     /* 274372 */     GIR_EraseRootFromParent_Done,
     /* 274373 */   // Label 5312: @274373
     /* 274373 */   GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(274433), // Rule ID 8989 //
     /* 274378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
     /* 274386 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274392 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274396 */     // MIs[0] Rn
     /* 274396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274400 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274404 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274408 */     // MIs[0] prfop
     /* 274408 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274411 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274416 */     // (intrinsic_void 1659:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm)
     /* 274416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_SXTW_SCALED),
     /* 274419 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274421 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274431 */     GIR_RootConstrainSelectedInstOperands,
     /* 274432 */     // GIR_Coverage, 8989,
     /* 274432 */     GIR_EraseRootFromParent_Done,
     /* 274433 */   // Label 5313: @274433
     /* 274433 */   GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(274493), // Rule ID 8990 //
     /* 274438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
     /* 274446 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274452 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274456 */     // MIs[0] Rn
     /* 274456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274460 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274464 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274468 */     // MIs[0] prfop
     /* 274468 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274471 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274476 */     // (intrinsic_void 1652:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm)
     /* 274476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_UXTW_SCALED),
     /* 274479 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274481 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274483 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274485 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274491 */     GIR_RootConstrainSelectedInstOperands,
     /* 274492 */     // GIR_Coverage, 8990,
     /* 274492 */     GIR_EraseRootFromParent_Done,
     /* 274493 */   // Label 5314: @274493
     /* 274493 */   GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(274553), // Rule ID 8991 //
     /* 274498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
     /* 274506 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 274509 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274512 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274516 */     // MIs[0] Rn
     /* 274516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274524 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274528 */     // MIs[0] prfop
     /* 274528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274531 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274536 */     // (intrinsic_void 1651:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm)
     /* 274536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_SXTW_SCALED),
     /* 274539 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274541 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274543 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274545 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274551 */     GIR_RootConstrainSelectedInstOperands,
     /* 274552 */     // GIR_Coverage, 8991,
     /* 274552 */     GIR_EraseRootFromParent_Done,
     /* 274553 */   // Label 5315: @274553
     /* 274553 */   GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(274613), // Rule ID 8992 //
     /* 274558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
     /* 274566 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274569 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274576 */     // MIs[0] Rn
     /* 274576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274584 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274588 */     // MIs[0] prfop
     /* 274588 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274591 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274596 */     // (intrinsic_void 1656:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm)
     /* 274596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_UXTW_SCALED),
     /* 274599 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274601 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274611 */     GIR_RootConstrainSelectedInstOperands,
     /* 274612 */     // GIR_Coverage, 8992,
     /* 274612 */     GIR_EraseRootFromParent_Done,
     /* 274613 */   // Label 5316: @274613
     /* 274613 */   GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(274673), // Rule ID 8993 //
     /* 274618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
     /* 274626 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274629 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274632 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274636 */     // MIs[0] Rn
     /* 274636 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274644 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274648 */     // MIs[0] prfop
     /* 274648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274651 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274656 */     // (intrinsic_void 1655:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm)
     /* 274656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SXTW_SCALED),
     /* 274659 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274661 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274671 */     GIR_RootConstrainSelectedInstOperands,
     /* 274672 */     // GIR_Coverage, 8993,
     /* 274672 */     GIR_EraseRootFromParent_Done,
     /* 274673 */   // Label 5317: @274673
     /* 274673 */   GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(274733), // Rule ID 8994 //
     /* 274678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
     /* 274686 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274689 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274692 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274696 */     // MIs[0] Rn
     /* 274696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274700 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274704 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274708 */     // MIs[0] prfop
     /* 274708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274711 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274716 */     // (intrinsic_void 1660:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm)
     /* 274716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_UXTW_SCALED),
     /* 274719 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274721 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274731 */     GIR_RootConstrainSelectedInstOperands,
     /* 274732 */     // GIR_Coverage, 8994,
     /* 274732 */     GIR_EraseRootFromParent_Done,
     /* 274733 */   // Label 5318: @274733
     /* 274733 */   GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(274793), // Rule ID 8995 //
     /* 274738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
     /* 274746 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274752 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274756 */     // MIs[0] Rn
     /* 274756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274764 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274768 */     // MIs[0] prfop
     /* 274768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274776 */     // (intrinsic_void 1659:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm)
     /* 274776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SXTW_SCALED),
     /* 274779 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274791 */     GIR_RootConstrainSelectedInstOperands,
     /* 274792 */     // GIR_Coverage, 8995,
     /* 274792 */     GIR_EraseRootFromParent_Done,
     /* 274793 */   // Label 5319: @274793
     /* 274793 */   GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(274853), // Rule ID 8996 //
     /* 274798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
     /* 274806 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274812 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274816 */     // MIs[0] Rn
     /* 274816 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274824 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274828 */     // MIs[0] prfop
     /* 274828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274831 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274836 */     // (intrinsic_void 1652:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm)
     /* 274836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_UXTW_SCALED),
     /* 274839 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274841 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274851 */     GIR_RootConstrainSelectedInstOperands,
     /* 274852 */     // GIR_Coverage, 8996,
     /* 274852 */     GIR_EraseRootFromParent_Done,
     /* 274853 */   // Label 5320: @274853
     /* 274853 */   GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(274913), // Rule ID 8997 //
     /* 274858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
     /* 274866 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274872 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274876 */     // MIs[0] Rn
     /* 274876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274884 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274888 */     // MIs[0] prfop
     /* 274888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274891 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274896 */     // (intrinsic_void 1651:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm)
     /* 274896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SXTW_SCALED),
     /* 274899 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274901 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274911 */     GIR_RootConstrainSelectedInstOperands,
     /* 274912 */     // GIR_Coverage, 8997,
     /* 274912 */     GIR_EraseRootFromParent_Done,
     /* 274913 */   // Label 5321: @274913
     /* 274913 */   GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(274973), // Rule ID 8998 //
     /* 274918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_index),
     /* 274926 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274936 */     // MIs[0] Rn
     /* 274936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 274940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 274944 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274948 */     // MIs[0] prfop
     /* 274948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 274951 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 274956 */     // (intrinsic_void 1653:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm)
     /* 274956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SCALED),
     /* 274959 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 274961 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 274963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 274965 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 274967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 274971 */     GIR_RootConstrainSelectedInstOperands,
     /* 274972 */     // GIR_Coverage, 8998,
     /* 274972 */     GIR_EraseRootFromParent_Done,
     /* 274973 */   // Label 5322: @274973
     /* 274973 */   GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(275033), // Rule ID 8999 //
     /* 274978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 274981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_index),
     /* 274986 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 274989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 274996 */     // MIs[0] Rn
     /* 274996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 275000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 275004 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275008 */     // MIs[0] prfop
     /* 275008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 275011 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 275016 */     // (intrinsic_void 1657:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm)
     /* 275016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SCALED),
     /* 275019 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 275021 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 275023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 275025 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 275027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275031 */     GIR_RootConstrainSelectedInstOperands,
     /* 275032 */     // GIR_Coverage, 8999,
     /* 275032 */     GIR_EraseRootFromParent_Done,
     /* 275033 */   // Label 5323: @275033
     /* 275033 */   GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(275093), // Rule ID 9000 //
     /* 275038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 275041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_index),
     /* 275046 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 275049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275052 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 275056 */     // MIs[0] Rn
     /* 275056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 275060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 275064 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275068 */     // MIs[0] prfop
     /* 275068 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 275071 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 275076 */     // (intrinsic_void 1649:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm)
     /* 275076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SCALED),
     /* 275079 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 275081 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 275083 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 275085 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 275087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275091 */     GIR_RootConstrainSelectedInstOperands,
     /* 275092 */     // GIR_Coverage, 9000,
     /* 275092 */     GIR_EraseRootFromParent_Done,
     /* 275093 */   // Label 5324: @275093
     /* 275093 */   GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(275151), // Rule ID 2378 //
     /* 275098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalb),
     /* 275106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 275109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 275112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275115 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275122 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275126 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275130 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275134 */     // (intrinsic_w_chain:{ *:[v8f16] } 629:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALBv8f16),
     /* 275137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275139 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275141 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275143 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275149 */     GIR_RootConstrainSelectedInstOperands,
     /* 275150 */     // GIR_Coverage, 2378,
     /* 275150 */     GIR_EraseRootFromParent_Done,
     /* 275151 */   // Label 5325: @275151
     /* 275151 */   GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(275209), // Rule ID 2379 //
     /* 275156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalt),
     /* 275164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 275167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 275170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275173 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275184 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275188 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275192 */     // (intrinsic_w_chain:{ *:[v8f16] } 639:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALTv8f16),
     /* 275195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275199 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275201 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275207 */     GIR_RootConstrainSelectedInstOperands,
     /* 275208 */     // GIR_Coverage, 2379,
     /* 275208 */     GIR_EraseRootFromParent_Done,
     /* 275209 */   // Label 5326: @275209
     /* 275209 */   GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(275267), // Rule ID 2380 //
     /* 275214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbb),
     /* 275222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 275225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 275228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275238 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275242 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275246 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275250 */     // (intrinsic_w_chain:{ *:[v4f32] } 631:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLBBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBBv4f32),
     /* 275253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275259 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275265 */     GIR_RootConstrainSelectedInstOperands,
     /* 275266 */     // GIR_Coverage, 2380,
     /* 275266 */     GIR_EraseRootFromParent_Done,
     /* 275267 */   // Label 5327: @275267
     /* 275267 */   GIM_Try, /*On fail goto*//*Label 5328*/ GIMT_Encode4(275325), // Rule ID 2381 //
     /* 275272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbt),
     /* 275280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 275283 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 275286 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275289 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275300 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275304 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275308 */     // (intrinsic_w_chain:{ *:[v4f32] } 633:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLBTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBTv4f32),
     /* 275311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275317 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275323 */     GIR_RootConstrainSelectedInstOperands,
     /* 275324 */     // GIR_Coverage, 2381,
     /* 275324 */     GIR_EraseRootFromParent_Done,
     /* 275325 */   // Label 5328: @275325
     /* 275325 */   GIM_Try, /*On fail goto*//*Label 5329*/ GIMT_Encode4(275383), // Rule ID 2382 //
     /* 275330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltb),
     /* 275338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 275341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 275344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275358 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275362 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275366 */     // (intrinsic_w_chain:{ *:[v4f32] } 635:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLTBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTBv4f32),
     /* 275369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275371 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275375 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275381 */     GIR_RootConstrainSelectedInstOperands,
     /* 275382 */     // GIR_Coverage, 2382,
     /* 275382 */     GIR_EraseRootFromParent_Done,
     /* 275383 */   // Label 5329: @275383
     /* 275383 */   GIM_Try, /*On fail goto*//*Label 5330*/ GIMT_Encode4(275441), // Rule ID 2383 //
     /* 275388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 275391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltt),
     /* 275396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 275399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 275402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275405 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275412 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275416 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275420 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275424 */     // (intrinsic_w_chain:{ *:[v4f32] } 637:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLTTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTTv4f32),
     /* 275427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275433 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275439 */     GIR_RootConstrainSelectedInstOperands,
     /* 275440 */     // GIR_Coverage, 2383,
     /* 275440 */     GIR_EraseRootFromParent_Done,
     /* 275441 */   // Label 5330: @275441
     /* 275441 */   GIM_Try, /*On fail goto*//*Label 5331*/ GIMT_Encode4(275499), // Rule ID 2384 //
     /* 275446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 275449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2),
     /* 275454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 275457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 275460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 275463 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 275466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275470 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275474 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275478 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275482 */     // (intrinsic_w_chain:{ *:[v4f16] } 625:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (FDOTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 275482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv4f16),
     /* 275485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275491 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275497 */     GIR_RootConstrainSelectedInstOperands,
     /* 275498 */     // GIR_Coverage, 2384,
     /* 275498 */     GIR_EraseRootFromParent_Done,
     /* 275499 */   // Label 5331: @275499
     /* 275499 */   GIM_Try, /*On fail goto*//*Label 5332*/ GIMT_Encode4(275557), // Rule ID 2385 //
     /* 275504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 275507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2),
     /* 275512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 275515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 275518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275521 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275528 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275532 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275536 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275540 */     // (intrinsic_w_chain:{ *:[v8f16] } 625:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FDOTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv8f16),
     /* 275543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275549 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275555 */     GIR_RootConstrainSelectedInstOperands,
     /* 275556 */     // GIR_Coverage, 2385,
     /* 275556 */     GIR_EraseRootFromParent_Done,
     /* 275557 */   // Label 5332: @275557
     /* 275557 */   GIM_Try, /*On fail goto*//*Label 5333*/ GIMT_Encode4(275615), // Rule ID 2386 //
     /* 275562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 275565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4),
     /* 275570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 275573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 275576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 275579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 275582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275586 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275590 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275594 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 275598 */     // (intrinsic_w_chain:{ *:[v2f32] } 627:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (FDOTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 275598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv2f32),
     /* 275601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275605 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275607 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275613 */     GIR_RootConstrainSelectedInstOperands,
     /* 275614 */     // GIR_Coverage, 2386,
     /* 275614 */     GIR_EraseRootFromParent_Done,
     /* 275615 */   // Label 5333: @275615
     /* 275615 */   GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(275673), // Rule ID 2387 //
     /* 275620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 275623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4),
     /* 275628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 275631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 275634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 275637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 275640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275652 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275656 */     // (intrinsic_w_chain:{ *:[v4f32] } 627:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FDOTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 275656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv4f32),
     /* 275659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 275663 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275665 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275671 */     GIR_RootConstrainSelectedInstOperands,
     /* 275672 */     // GIR_Coverage, 2387,
     /* 275672 */     GIR_EraseRootFromParent_Done,
     /* 275673 */   // Label 5334: @275673
     /* 275673 */   GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(275731), // Rule ID 2491 //
     /* 275678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 275681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn2),
     /* 275686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 275689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 275692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 275695 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 275698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275706 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275710 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 275714 */     // (intrinsic_w_chain:{ *:[v16i8] } 624:{ *:[iPTR] }, V128:{ *:[v16i8] }:$_Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCVTN_F322v16f8:{ *:[v16i8] } V128:{ *:[v16i8] }:$_Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 275714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F322v16f8),
     /* 275717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 275719 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Rd
     /* 275721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 275723 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 275725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275729 */     GIR_RootConstrainSelectedInstOperands,
     /* 275730 */     // GIR_Coverage, 2491,
     /* 275730 */     GIR_EraseRootFromParent_Done,
     /* 275731 */   // Label 5335: @275731
     /* 275731 */   GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(275787), // Rule ID 13421 //
     /* 275736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxp),
     /* 275741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 275744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 275747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 275750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 275754 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275758 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275762 */     // MIs[0] addr
     /* 275762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
     /* 275766 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275770 */     // (intrinsic_w_chain:{ *:[i32] } 1248:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)  =>  (STLXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
     /* 275770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXPX),
     /* 275773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 275775 */     GIR_RootToRootCopy, /*OpIdx*/2, // lo
     /* 275777 */     GIR_RootToRootCopy, /*OpIdx*/3, // hi
     /* 275779 */     GIR_RootToRootCopy, /*OpIdx*/4, // addr
     /* 275781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275785 */     GIR_RootConstrainSelectedInstOperands,
     /* 275786 */     // GIR_Coverage, 13421,
     /* 275786 */     GIR_EraseRootFromParent_Done,
     /* 275787 */   // Label 5336: @275787
     /* 275787 */   GIM_Try, /*On fail goto*//*Label 5337*/ GIMT_Encode4(275843), // Rule ID 13422 //
     /* 275792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxp),
     /* 275797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 275800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 275803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 275806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 275810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275814 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275818 */     // MIs[0] addr
     /* 275818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
     /* 275822 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 275826 */     // (intrinsic_w_chain:{ *:[i32] } 1250:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)  =>  (STXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
     /* 275826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXPX),
     /* 275829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 275831 */     GIR_RootToRootCopy, /*OpIdx*/2, // lo
     /* 275833 */     GIR_RootToRootCopy, /*OpIdx*/3, // hi
     /* 275835 */     GIR_RootToRootCopy, /*OpIdx*/4, // addr
     /* 275837 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275841 */     GIR_RootConstrainSelectedInstOperands,
     /* 275842 */     // GIR_Coverage, 13422,
     /* 275842 */     GIR_EraseRootFromParent_Done,
     /* 275843 */   // Label 5337: @275843
     /* 275843 */   GIM_Try, /*On fail goto*//*Label 5338*/ GIMT_Encode4(275889), // Rule ID 3480 //
     /* 275848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT2),
     /* 275851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot),
     /* 275856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 275862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275865 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275872 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1513:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FDOT_ZZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_BtoH),
     /* 275875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 275877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275879 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275881 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275887 */     GIR_RootConstrainSelectedInstOperands,
     /* 275888 */     // GIR_Coverage, 3480,
     /* 275888 */     GIR_EraseRootFromParent_Done,
     /* 275889 */   // Label 5338: @275889
     /* 275889 */   GIM_Try, /*On fail goto*//*Label 5339*/ GIMT_Encode4(275935), // Rule ID 3608 //
     /* 275894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 275897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalb),
     /* 275902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 275908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275911 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275918 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1515:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALB_ZZZ:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZ),
     /* 275921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 275923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275927 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275933 */     GIR_RootConstrainSelectedInstOperands,
     /* 275934 */     // GIR_Coverage, 3608,
     /* 275934 */     GIR_EraseRootFromParent_Done,
     /* 275935 */   // Label 5339: @275935
     /* 275935 */   GIM_Try, /*On fail goto*//*Label 5340*/ GIMT_Encode4(275981), // Rule ID 12849 //
     /* 275940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 275943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalt),
     /* 275948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 275954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275957 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275964 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1525:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALT_ZZZ:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZ),
     /* 275967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 275969 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275971 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275973 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275975 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 275979 */     GIR_RootConstrainSelectedInstOperands,
     /* 275980 */     // GIR_Coverage, 12849,
     /* 275980 */     GIR_EraseRootFromParent_Done,
     /* 275981 */   // Label 5340: @275981
     /* 275981 */   GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(276027), // Rule ID 12853 //
     /* 275986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 275989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbb),
     /* 275994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 276000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276010 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1517:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLBB_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBB_ZZZ),
     /* 276013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 276015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276019 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276025 */     GIR_RootConstrainSelectedInstOperands,
     /* 276026 */     // GIR_Coverage, 12853,
     /* 276026 */     GIR_EraseRootFromParent_Done,
     /* 276027 */   // Label 5341: @276027
     /* 276027 */   GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(276073), // Rule ID 12854 //
     /* 276032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 276035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbt),
     /* 276040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 276046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276049 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276056 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1519:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLBT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBT_ZZZ),
     /* 276059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 276061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276063 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276065 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276071 */     GIR_RootConstrainSelectedInstOperands,
     /* 276072 */     // GIR_Coverage, 12854,
     /* 276072 */     GIR_EraseRootFromParent_Done,
     /* 276073 */   // Label 5342: @276073
     /* 276073 */   GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(276119), // Rule ID 12855 //
     /* 276078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 276081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltb),
     /* 276086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 276092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276095 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276102 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1521:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLTB_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTB_ZZZ),
     /* 276105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 276107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276111 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276113 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276117 */     GIR_RootConstrainSelectedInstOperands,
     /* 276118 */     // GIR_Coverage, 12855,
     /* 276118 */     GIR_EraseRootFromParent_Done,
     /* 276119 */   // Label 5343: @276119
     /* 276119 */   GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(276165), // Rule ID 12856 //
     /* 276124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 276127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltt),
     /* 276132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 276138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276141 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276148 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1523:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLTT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTT_ZZZ),
     /* 276151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 276153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276155 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276157 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276163 */     GIR_RootConstrainSelectedInstOperands,
     /* 276164 */     // GIR_Coverage, 12856,
     /* 276164 */     GIR_EraseRootFromParent_Done,
     /* 276165 */   // Label 5344: @276165
     /* 276165 */   GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(276211), // Rule ID 12857 //
     /* 276170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT4),
     /* 276173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot),
     /* 276178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 276184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276187 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276194 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1513:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FDOT_ZZZ_BtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_BtoS),
     /* 276197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 276199 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276201 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276203 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276209 */     GIR_RootConstrainSelectedInstOperands,
     /* 276210 */     // GIR_Coverage, 12857,
     /* 276210 */     GIR_EraseRootFromParent_Done,
     /* 276211 */   // Label 5345: @276211
     /* 276211 */   GIM_Reject,
     /* 276212 */ // Label 5298: @276212
     /* 276212 */ GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(279205),
     /* 276217 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /* 276220 */   GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(276288), // Rule ID 2518 //
     /* 276225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalb_lane),
     /* 276233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 276236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 276239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276242 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276249 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276253 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276257 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276261 */     // MIs[0] Idx
     /* 276261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276264 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276269 */     // (intrinsic_w_chain:{ *:[v8f16] } 630:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALBlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALBlanev8f16),
     /* 276272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276278 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276280 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276286 */     GIR_RootConstrainSelectedInstOperands,
     /* 276287 */     // GIR_Coverage, 2518,
     /* 276287 */     GIR_EraseRootFromParent_Done,
     /* 276288 */   // Label 5347: @276288
     /* 276288 */   GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(276356), // Rule ID 2519 //
     /* 276293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbb_lane),
     /* 276301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 276304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 276307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276310 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276317 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276321 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276325 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276329 */     // MIs[0] Idx
     /* 276329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276332 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276337 */     // (intrinsic_w_chain:{ *:[v4f32] } 632:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLBBlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBBlanev4f32),
     /* 276340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276342 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276346 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276348 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276354 */     GIR_RootConstrainSelectedInstOperands,
     /* 276355 */     // GIR_Coverage, 2519,
     /* 276355 */     GIR_EraseRootFromParent_Done,
     /* 276356 */   // Label 5348: @276356
     /* 276356 */   GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(276424), // Rule ID 2520 //
     /* 276361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 276364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4_lane),
     /* 276369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 276372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 276375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 276378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276389 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276393 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276397 */     // MIs[0] Idx
     /* 276397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276400 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 276405 */     // (intrinsic_w_chain:{ *:[v2f32] } 628:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Idx)  =>  (FDOTlanev2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v8i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev2f32),
     /* 276408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276410 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276412 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276414 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276416 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276422 */     GIR_RootConstrainSelectedInstOperands,
     /* 276423 */     // GIR_Coverage, 2520,
     /* 276423 */     GIR_EraseRootFromParent_Done,
     /* 276424 */   // Label 5349: @276424
     /* 276424 */   GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(276492), // Rule ID 2521 //
     /* 276429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 276432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4_lane),
     /* 276437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 276440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 276443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276457 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276461 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276465 */     // MIs[0] Idx
     /* 276465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276468 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 276473 */     // (intrinsic_w_chain:{ *:[v4f32] } 628:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Idx)  =>  (FDOTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev4f32),
     /* 276476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276480 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276482 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276484 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276490 */     GIR_RootConstrainSelectedInstOperands,
     /* 276491 */     // GIR_Coverage, 2521,
     /* 276491 */     GIR_EraseRootFromParent_Done,
     /* 276492 */   // Label 5350: @276492
     /* 276492 */   GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(276560), // Rule ID 2522 //
     /* 276497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 276500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2_lane),
     /* 276505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 276508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 276511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 276514 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276521 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276525 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 276529 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 276533 */     // MIs[0] Idx
     /* 276533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276536 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 276541 */     // (intrinsic_w_chain:{ *:[v4f16] } 626:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128_lo:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Idx)  =>  (FDOTlanev4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v8i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev4f16),
     /* 276544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276548 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276550 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276552 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276558 */     GIR_RootConstrainSelectedInstOperands,
     /* 276559 */     // GIR_Coverage, 2522,
     /* 276559 */     GIR_EraseRootFromParent_Done,
     /* 276560 */   // Label 5351: @276560
     /* 276560 */   GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(276628), // Rule ID 2523 //
     /* 276565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 276568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2_lane),
     /* 276573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 276576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 276579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276597 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 276601 */     // MIs[0] Idx
     /* 276601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276604 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 276609 */     // (intrinsic_w_chain:{ *:[v8f16] } 626:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_lo:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Idx)  =>  (FDOTlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev8f16),
     /* 276612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276618 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276620 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276626 */     GIR_RootConstrainSelectedInstOperands,
     /* 276627 */     // GIR_Coverage, 2523,
     /* 276627 */     GIR_EraseRootFromParent_Done,
     /* 276628 */   // Label 5352: @276628
     /* 276628 */   GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(276696), // Rule ID 7065 //
     /* 276633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalt_lane),
     /* 276641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 276644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 276647 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276650 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276657 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276661 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276665 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276669 */     // MIs[0] Idx
     /* 276669 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276672 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276677 */     // (intrinsic_w_chain:{ *:[v8f16] } 640:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALTlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALTlanev8f16),
     /* 276680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276686 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276688 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276694 */     GIR_RootConstrainSelectedInstOperands,
     /* 276695 */     // GIR_Coverage, 7065,
     /* 276695 */     GIR_EraseRootFromParent_Done,
     /* 276696 */   // Label 5353: @276696
     /* 276696 */   GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(276764), // Rule ID 7066 //
     /* 276701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbt_lane),
     /* 276709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 276712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 276715 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276718 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276725 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276729 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276733 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276737 */     // MIs[0] Idx
     /* 276737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276740 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276745 */     // (intrinsic_w_chain:{ *:[v4f32] } 634:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLBTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBTlanev4f32),
     /* 276748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276752 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276754 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276756 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276762 */     GIR_RootConstrainSelectedInstOperands,
     /* 276763 */     // GIR_Coverage, 7066,
     /* 276763 */     GIR_EraseRootFromParent_Done,
     /* 276764 */   // Label 5354: @276764
     /* 276764 */   GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(276832), // Rule ID 7067 //
     /* 276769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltb_lane),
     /* 276777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 276780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 276783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276786 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276801 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276805 */     // MIs[0] Idx
     /* 276805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276808 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276813 */     // (intrinsic_w_chain:{ *:[v4f32] } 636:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLTBlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTBlanev4f32),
     /* 276816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276822 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276824 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276830 */     GIR_RootConstrainSelectedInstOperands,
     /* 276831 */     // GIR_Coverage, 7067,
     /* 276831 */     GIR_EraseRootFromParent_Done,
     /* 276832 */   // Label 5355: @276832
     /* 276832 */   GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(276900), // Rule ID 7068 //
     /* 276837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 276840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltt_lane),
     /* 276845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 276848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 276851 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 276854 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 276857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276865 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 276869 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 276873 */     // MIs[0] Idx
     /* 276873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 276876 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 276881 */     // (intrinsic_w_chain:{ *:[v4f32] } 638:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLTTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 276881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTTlanev4f32),
     /* 276884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 276886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 276888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 276890 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 276892 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 276894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276898 */     GIR_RootConstrainSelectedInstOperands,
     /* 276899 */     // GIR_Coverage, 7068,
     /* 276899 */     GIR_EraseRootFromParent_Done,
     /* 276900 */   // Label 5356: @276900
     /* 276900 */   GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(276960), // Rule ID 3620 //
     /* 276905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 276908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 276913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 276919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276922 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 276925 */     // MIs[0] tile
     /* 276925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 276928 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 276933 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 276937 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 276941 */     // (intrinsic_void 938:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 276941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_S_PSEUDO),
     /* 276944 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 276946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 276948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 276950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 276952 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 276954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 276958 */     GIR_RootConstrainSelectedInstOperands,
     /* 276959 */     // GIR_Coverage, 3620,
     /* 276959 */     GIR_EraseRootFromParent_Done,
     /* 276960 */   // Label 5357: @276960
     /* 276960 */   GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(277020), // Rule ID 3621 //
     /* 276965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F32),
     /* 276968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmopa_za32),
     /* 276973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 276979 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276982 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 276985 */     // MIs[0] tile
     /* 276985 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 276988 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 276993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 276997 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277001 */     // (intrinsic_void 890:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOPA_MPPZZ_BtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_BtoS_PSEUDO),
     /* 277004 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277010 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277012 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277018 */     GIR_RootConstrainSelectedInstOperands,
     /* 277019 */     // GIR_Coverage, 3621,
     /* 277019 */     GIR_EraseRootFromParent_Done,
     /* 277020 */   // Label 5358: @277020
     /* 277020 */   GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(277080), // Rule ID 3622 //
     /* 277025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
     /* 277028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 277033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 277036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 277039 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277042 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 277045 */     // MIs[0] tile
     /* 277045 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277048 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 277053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277057 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277061 */     // (intrinsic_void 938:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 277061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_D_PSEUDO),
     /* 277064 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277070 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277072 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277078 */     GIR_RootConstrainSelectedInstOperands,
     /* 277079 */     // GIR_Coverage, 3622,
     /* 277079 */     GIR_EraseRootFromParent_Done,
     /* 277080 */   // Label 5359: @277080
     /* 277080 */   GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(277140), // Rule ID 3623 //
     /* 277085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F16),
     /* 277088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmopa_za16),
     /* 277093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277099 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277102 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277105 */     // MIs[0] tile
     /* 277105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277108 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 277113 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277117 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277121 */     // (intrinsic_void 889:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOPA_MPPZZ_BtoH_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_BtoH_PSEUDO),
     /* 277124 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277130 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277132 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277138 */     GIR_RootConstrainSelectedInstOperands,
     /* 277139 */     // GIR_Coverage, 3623,
     /* 277139 */     GIR_EraseRootFromParent_Done,
     /* 277140 */   // Label 5360: @277140
     /* 277140 */   GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(277200), // Rule ID 3624 //
     /* 277145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16),
     /* 277148 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 277153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 277156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 277159 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277162 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 277165 */     // MIs[0] tile
     /* 277165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277168 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 277173 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277177 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277181 */     // (intrinsic_void 938:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPA_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 277181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_H_PSEUDO),
     /* 277184 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277190 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277192 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277198 */     GIR_RootConstrainSelectedInstOperands,
     /* 277199 */     // GIR_Coverage, 3624,
     /* 277199 */     GIR_EraseRootFromParent_Done,
     /* 277200 */   // Label 5361: @277200
     /* 277200 */   GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(277260), // Rule ID 3625 //
     /* 277205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
     /* 277213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277219 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277222 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277225 */     // MIs[0] tile
     /* 277225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277228 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277233 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277237 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277241 */     // (intrinsic_void 1041:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_S_PSEUDO),
     /* 277244 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277248 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277250 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277252 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277258 */     GIR_RootConstrainSelectedInstOperands,
     /* 277259 */     // GIR_Coverage, 3625,
     /* 277259 */     GIR_EraseRootFromParent_Done,
     /* 277260 */   // Label 5362: @277260
     /* 277260 */   GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(277320), // Rule ID 3626 //
     /* 277265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 277268 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
     /* 277273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 277276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 277279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277282 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 277285 */     // MIs[0] tile
     /* 277285 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277288 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 277293 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277297 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277301 */     // (intrinsic_void 1041:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 277301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_D_PSEUDO),
     /* 277304 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277308 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277310 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277312 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277318 */     GIR_RootConstrainSelectedInstOperands,
     /* 277319 */     // GIR_Coverage, 3626,
     /* 277319 */     GIR_EraseRootFromParent_Done,
     /* 277320 */   // Label 5363: @277320
     /* 277320 */   GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(277380), // Rule ID 3627 //
     /* 277325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa_wide),
     /* 277333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 277336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 277339 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277342 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 277345 */     // MIs[0] tile
     /* 277345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277348 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277353 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277357 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277361 */     // (intrinsic_void 940:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPAL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 277361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPAL_MPPZZ_PSEUDO),
     /* 277364 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277368 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277370 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277372 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277378 */     GIR_RootConstrainSelectedInstOperands,
     /* 277379 */     // GIR_Coverage, 3627,
     /* 277379 */     GIR_EraseRootFromParent_Done,
     /* 277380 */   // Label 5364: @277380
     /* 277380 */   GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(277440), // Rule ID 3721 //
     /* 277385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 277388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_za32),
     /* 277393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 277396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 277399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277402 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 277405 */     // MIs[0] tile
     /* 277405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277408 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277417 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277421 */     // (intrinsic_void 1042:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 277421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_HtoS_PSEUDO),
     /* 277424 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277426 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277428 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277430 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277432 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277438 */     GIR_RootConstrainSelectedInstOperands,
     /* 277439 */     // GIR_Coverage, 3721,
     /* 277439 */     GIR_EraseRootFromParent_Done,
     /* 277440 */   // Label 5365: @277440
     /* 277440 */   GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(277500), // Rule ID 3722 //
     /* 277445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 277448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmopa_za32),
     /* 277453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 277456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 277459 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277462 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 277465 */     // MIs[0] tile
     /* 277465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277468 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277481 */     // (intrinsic_void 809:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm)  =>  (BMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
     /* 277481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPA_MPPZZ_S_PSEUDO),
     /* 277484 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277490 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277492 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277498 */     GIR_RootConstrainSelectedInstOperands,
     /* 277499 */     // GIR_Coverage, 3722,
     /* 277499 */     GIR_EraseRootFromParent_Done,
     /* 277500 */   // Label 5366: @277500
     /* 277500 */   GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(277560), // Rule ID 12864 //
     /* 277505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 277513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 277516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 277519 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277522 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 277525 */     // MIs[0] tile
     /* 277525 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277528 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277537 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277541 */     // (intrinsic_void 941:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 277541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_S_PSEUDO),
     /* 277544 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277548 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277550 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277552 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277558 */     GIR_RootConstrainSelectedInstOperands,
     /* 277559 */     // GIR_Coverage, 12864,
     /* 277559 */     GIR_EraseRootFromParent_Done,
     /* 277560 */   // Label 5367: @277560
     /* 277560 */   GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(277620), // Rule ID 12865 //
     /* 277565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
     /* 277568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 277573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 277576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 277579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277582 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 277585 */     // MIs[0] tile
     /* 277585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277588 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 277593 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277597 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277601 */     // (intrinsic_void 941:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 277601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_D_PSEUDO),
     /* 277604 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277610 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277612 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277618 */     GIR_RootConstrainSelectedInstOperands,
     /* 277619 */     // GIR_Coverage, 12865,
     /* 277619 */     GIR_EraseRootFromParent_Done,
     /* 277620 */   // Label 5368: @277620
     /* 277620 */   GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(277680), // Rule ID 12866 //
     /* 277625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops_wide),
     /* 277633 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 277636 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 277639 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277642 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 277645 */     // MIs[0] tile
     /* 277645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277648 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277657 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277661 */     // (intrinsic_void 943:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPSL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 277661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPSL_MPPZZ_PSEUDO),
     /* 277664 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277668 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277670 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277672 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277678 */     GIR_RootConstrainSelectedInstOperands,
     /* 277679 */     // GIR_Coverage, 12866,
     /* 277679 */     GIR_EraseRootFromParent_Done,
     /* 277680 */   // Label 5369: @277680
     /* 277680 */   GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(277740), // Rule ID 12867 //
     /* 277685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
     /* 277693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277699 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277702 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277705 */     // MIs[0] tile
     /* 277705 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277708 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277721 */     // (intrinsic_void 1043:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_S_PSEUDO),
     /* 277724 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277730 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277732 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277738 */     GIR_RootConstrainSelectedInstOperands,
     /* 277739 */     // GIR_Coverage, 12867,
     /* 277739 */     GIR_EraseRootFromParent_Done,
     /* 277740 */   // Label 5370: @277740
     /* 277740 */   GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(277800), // Rule ID 12868 //
     /* 277745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
     /* 277753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277762 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277765 */     // MIs[0] tile
     /* 277765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277768 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277777 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277781 */     // (intrinsic_void 1176:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_S_PSEUDO),
     /* 277784 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277788 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277790 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277792 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277798 */     GIR_RootConstrainSelectedInstOperands,
     /* 277799 */     // GIR_Coverage, 12868,
     /* 277799 */     GIR_EraseRootFromParent_Done,
     /* 277800 */   // Label 5371: @277800
     /* 277800 */   GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(277860), // Rule ID 12869 //
     /* 277805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
     /* 277813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277819 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277822 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277825 */     // MIs[0] tile
     /* 277825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277828 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277837 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277841 */     // (intrinsic_void 1178:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_S_PSEUDO),
     /* 277844 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277846 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277850 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277852 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277858 */     GIR_RootConstrainSelectedInstOperands,
     /* 277859 */     // GIR_Coverage, 12869,
     /* 277859 */     GIR_EraseRootFromParent_Done,
     /* 277860 */   // Label 5372: @277860
     /* 277860 */   GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(277920), // Rule ID 12870 //
     /* 277865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
     /* 277873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277879 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277882 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277885 */     // MIs[0] tile
     /* 277885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277888 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277901 */     // (intrinsic_void 1093:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_S_PSEUDO),
     /* 277904 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277906 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277910 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277912 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277918 */     GIR_RootConstrainSelectedInstOperands,
     /* 277919 */     // GIR_Coverage, 12870,
     /* 277919 */     GIR_EraseRootFromParent_Done,
     /* 277920 */   // Label 5373: @277920
     /* 277920 */   GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(277980), // Rule ID 12871 //
     /* 277925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
     /* 277933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277939 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277942 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 277945 */     // MIs[0] tile
     /* 277945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 277948 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 277953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277957 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 277961 */     // (intrinsic_void 1094:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 277961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_S_PSEUDO),
     /* 277964 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 277966 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 277968 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 277970 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 277972 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 277974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 277978 */     GIR_RootConstrainSelectedInstOperands,
     /* 277979 */     // GIR_Coverage, 12871,
     /* 277979 */     GIR_EraseRootFromParent_Done,
     /* 277980 */   // Label 5374: @277980
     /* 277980 */   GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(278040), // Rule ID 12872 //
     /* 277985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 277988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
     /* 277993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 277996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 277999 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278002 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 278005 */     // MIs[0] tile
     /* 278005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278008 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278017 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278021 */     // (intrinsic_void 1210:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 278021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_S_PSEUDO),
     /* 278024 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278030 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278032 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278038 */     GIR_RootConstrainSelectedInstOperands,
     /* 278039 */     // GIR_Coverage, 12872,
     /* 278039 */     GIR_EraseRootFromParent_Done,
     /* 278040 */   // Label 5375: @278040
     /* 278040 */   GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(278100), // Rule ID 12873 //
     /* 278045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 278048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
     /* 278053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 278056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 278059 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278062 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 278065 */     // MIs[0] tile
     /* 278065 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278068 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278077 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278081 */     // (intrinsic_void 1211:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 278081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_S_PSEUDO),
     /* 278084 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278090 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278092 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278098 */     GIR_RootConstrainSelectedInstOperands,
     /* 278099 */     // GIR_Coverage, 12873,
     /* 278099 */     GIR_EraseRootFromParent_Done,
     /* 278100 */   // Label 5376: @278100
     /* 278100 */   GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(278160), // Rule ID 12874 //
     /* 278105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278108 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
     /* 278113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278119 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278122 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278125 */     // MIs[0] tile
     /* 278125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278128 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278133 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278137 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278141 */     // (intrinsic_void 1043:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_D_PSEUDO),
     /* 278144 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278148 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278150 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278152 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278158 */     GIR_RootConstrainSelectedInstOperands,
     /* 278159 */     // GIR_Coverage, 12874,
     /* 278159 */     GIR_EraseRootFromParent_Done,
     /* 278160 */   // Label 5377: @278160
     /* 278160 */   GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(278220), // Rule ID 12875 //
     /* 278165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
     /* 278173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278179 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278182 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278185 */     // MIs[0] tile
     /* 278185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278188 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278197 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278201 */     // (intrinsic_void 1176:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_D_PSEUDO),
     /* 278204 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278210 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278212 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278218 */     GIR_RootConstrainSelectedInstOperands,
     /* 278219 */     // GIR_Coverage, 12875,
     /* 278219 */     GIR_EraseRootFromParent_Done,
     /* 278220 */   // Label 5378: @278220
     /* 278220 */   GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(278280), // Rule ID 12876 //
     /* 278225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
     /* 278233 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278236 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278239 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278242 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278245 */     // MIs[0] tile
     /* 278245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278248 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278257 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278261 */     // (intrinsic_void 1178:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_D_PSEUDO),
     /* 278264 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278268 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278270 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278272 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278278 */     GIR_RootConstrainSelectedInstOperands,
     /* 278279 */     // GIR_Coverage, 12876,
     /* 278279 */     GIR_EraseRootFromParent_Done,
     /* 278280 */   // Label 5379: @278280
     /* 278280 */   GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(278340), // Rule ID 12877 //
     /* 278285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
     /* 278293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278299 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278302 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278305 */     // MIs[0] tile
     /* 278305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278308 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278313 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278317 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278321 */     // (intrinsic_void 1093:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_D_PSEUDO),
     /* 278324 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278326 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278328 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278330 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278332 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278338 */     GIR_RootConstrainSelectedInstOperands,
     /* 278339 */     // GIR_Coverage, 12877,
     /* 278339 */     GIR_EraseRootFromParent_Done,
     /* 278340 */   // Label 5380: @278340
     /* 278340 */   GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(278400), // Rule ID 12878 //
     /* 278345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
     /* 278353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278362 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278365 */     // MIs[0] tile
     /* 278365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278368 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278377 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278381 */     // (intrinsic_void 1094:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_D_PSEUDO),
     /* 278384 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278386 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278388 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278390 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278392 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278398 */     GIR_RootConstrainSelectedInstOperands,
     /* 278399 */     // GIR_Coverage, 12878,
     /* 278399 */     GIR_EraseRootFromParent_Done,
     /* 278400 */   // Label 5381: @278400
     /* 278400 */   GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(278460), // Rule ID 12879 //
     /* 278405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
     /* 278413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278419 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278422 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278425 */     // MIs[0] tile
     /* 278425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278428 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278433 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278437 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278441 */     // (intrinsic_void 1210:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_D_PSEUDO),
     /* 278444 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278446 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278448 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278450 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278452 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278458 */     GIR_RootConstrainSelectedInstOperands,
     /* 278459 */     // GIR_Coverage, 12879,
     /* 278459 */     GIR_EraseRootFromParent_Done,
     /* 278460 */   // Label 5382: @278460
     /* 278460 */   GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(278520), // Rule ID 12880 //
     /* 278465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 278468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
     /* 278473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278479 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278482 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278485 */     // MIs[0] tile
     /* 278485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278488 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 278493 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278497 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278501 */     // (intrinsic_void 1211:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_D_PSEUDO),
     /* 278504 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278508 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278510 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278512 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278518 */     GIR_RootConstrainSelectedInstOperands,
     /* 278519 */     // GIR_Coverage, 12880,
     /* 278519 */     GIR_EraseRootFromParent_Done,
     /* 278520 */   // Label 5383: @278520
     /* 278520 */   GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(278580), // Rule ID 13254 //
     /* 278525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 278528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmops_za32),
     /* 278533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 278536 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 278539 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278542 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 278545 */     // MIs[0] tile
     /* 278545 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278548 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278553 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278557 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278561 */     // (intrinsic_void 810:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm)  =>  (BMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
     /* 278561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPS_MPPZZ_S_PSEUDO),
     /* 278564 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278566 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278568 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278570 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278572 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278578 */     GIR_RootConstrainSelectedInstOperands,
     /* 278579 */     // GIR_Coverage, 13254,
     /* 278579 */     GIR_EraseRootFromParent_Done,
     /* 278580 */   // Label 5384: @278580
     /* 278580 */   GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(278640), // Rule ID 13255 //
     /* 278585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 278588 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_za32),
     /* 278593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278599 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278602 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278605 */     // MIs[0] tile
     /* 278605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278608 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278617 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278621 */     // (intrinsic_void 1044:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_HtoS_PSEUDO),
     /* 278624 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278630 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278632 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278638 */     GIR_RootConstrainSelectedInstOperands,
     /* 278639 */     // GIR_Coverage, 13255,
     /* 278639 */     GIR_EraseRootFromParent_Done,
     /* 278640 */   // Label 5385: @278640
     /* 278640 */   GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(278700), // Rule ID 13256 //
     /* 278645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 278648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_za32),
     /* 278653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278656 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278659 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278662 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278665 */     // MIs[0] tile
     /* 278665 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278668 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278673 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278677 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278681 */     // (intrinsic_void 1177:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_HtoS_PSEUDO),
     /* 278684 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278690 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278692 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278698 */     GIR_RootConstrainSelectedInstOperands,
     /* 278699 */     // GIR_Coverage, 13256,
     /* 278699 */     GIR_EraseRootFromParent_Done,
     /* 278700 */   // Label 5386: @278700
     /* 278700 */   GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(278760), // Rule ID 13257 //
     /* 278705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 278708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_za32),
     /* 278713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278719 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278722 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278725 */     // MIs[0] tile
     /* 278725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278728 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 278733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278737 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278741 */     // (intrinsic_void 1179:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 278741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_HtoS_PSEUDO),
     /* 278744 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278750 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278752 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278758 */     GIR_RootConstrainSelectedInstOperands,
     /* 278759 */     // GIR_Coverage, 13257,
     /* 278759 */     GIR_EraseRootFromParent_Done,
     /* 278760 */   // Label 5387: @278760
     /* 278760 */   GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(278820), // Rule ID 13368 //
     /* 278765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16),
     /* 278768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 278773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 278779 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278782 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 278785 */     // MIs[0] tile
     /* 278785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 278788 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 278793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 278801 */     // (intrinsic_void 941:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPS_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 278801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_H_PSEUDO),
     /* 278804 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 278806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 278808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 278810 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 278812 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 278814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278818 */     GIR_RootConstrainSelectedInstOperands,
     /* 278819 */     // GIR_Coverage, 13368,
     /* 278819 */     GIR_EraseRootFromParent_Done,
     /* 278820 */   // Label 5388: @278820
     /* 278820 */   GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(278868), // Rule ID 3607 //
     /* 278825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 278828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalb_lane),
     /* 278833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 278839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278849 */     // MIs[0] Op4
     /* 278849 */     // No operand predicates
     /* 278849 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1516:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALB_ZZZI:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 278849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZI),
     /* 278852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 278854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278858 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278860 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 278862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278866 */     GIR_RootConstrainSelectedInstOperands,
     /* 278867 */     // GIR_Coverage, 3607,
     /* 278867 */     GIR_EraseRootFromParent_Done,
     /* 278868 */   // Label 5389: @278868
     /* 278868 */   GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(278916), // Rule ID 3609 //
     /* 278873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 278876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbb_lane),
     /* 278881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 278887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278890 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278897 */     // MIs[0] Op4
     /* 278897 */     // No operand predicates
     /* 278897 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1518:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLBB_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 278897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBB_ZZZI),
     /* 278900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 278902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278906 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278908 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 278910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278914 */     GIR_RootConstrainSelectedInstOperands,
     /* 278915 */     // GIR_Coverage, 3609,
     /* 278915 */     GIR_EraseRootFromParent_Done,
     /* 278916 */   // Label 5390: @278916
     /* 278916 */   GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(278964), // Rule ID 3610 //
     /* 278921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT2),
     /* 278924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot_lane),
     /* 278929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 278935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278938 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278945 */     // MIs[0] Op4
     /* 278945 */     // No operand predicates
     /* 278945 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1514:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FDOT_ZZZI_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 278945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_BtoH),
     /* 278948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 278950 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278952 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278954 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278956 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 278958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 278962 */     GIR_RootConstrainSelectedInstOperands,
     /* 278963 */     // GIR_Coverage, 3610,
     /* 278963 */     GIR_EraseRootFromParent_Done,
     /* 278964 */   // Label 5391: @278964
     /* 278964 */   GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(279012), // Rule ID 3611 //
     /* 278969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT4),
     /* 278972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot_lane),
     /* 278977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 278983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278993 */     // MIs[0] Op4
     /* 278993 */     // No operand predicates
     /* 278993 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1514:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FDOT_ZZZI_BtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 278993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_BtoS),
     /* 278996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 278998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279002 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279004 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 279006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 279010 */     GIR_RootConstrainSelectedInstOperands,
     /* 279011 */     // GIR_Coverage, 3611,
     /* 279011 */     GIR_EraseRootFromParent_Done,
     /* 279012 */   // Label 5392: @279012
     /* 279012 */   GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(279060), // Rule ID 12848 //
     /* 279017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 279020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalt_lane),
     /* 279025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 279031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279034 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279041 */     // MIs[0] Op4
     /* 279041 */     // No operand predicates
     /* 279041 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1526:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALT_ZZZI:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 279041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZI),
     /* 279044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279046 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279048 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279050 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279052 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 279054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 279058 */     GIR_RootConstrainSelectedInstOperands,
     /* 279059 */     // GIR_Coverage, 12848,
     /* 279059 */     GIR_EraseRootFromParent_Done,
     /* 279060 */   // Label 5393: @279060
     /* 279060 */   GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(279108), // Rule ID 12850 //
     /* 279065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 279068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbt_lane),
     /* 279073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279079 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279082 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279089 */     // MIs[0] Op4
     /* 279089 */     // No operand predicates
     /* 279089 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1520:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLBT_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 279089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBT_ZZZI),
     /* 279092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279098 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279100 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 279102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 279106 */     GIR_RootConstrainSelectedInstOperands,
     /* 279107 */     // GIR_Coverage, 12850,
     /* 279107 */     GIR_EraseRootFromParent_Done,
     /* 279108 */   // Label 5394: @279108
     /* 279108 */   GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(279156), // Rule ID 12851 //
     /* 279113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 279116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltb_lane),
     /* 279121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279130 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279137 */     // MIs[0] Op4
     /* 279137 */     // No operand predicates
     /* 279137 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1522:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLTB_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 279137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTB_ZZZI),
     /* 279140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279146 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279148 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 279150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 279154 */     GIR_RootConstrainSelectedInstOperands,
     /* 279155 */     // GIR_Coverage, 12851,
     /* 279155 */     GIR_EraseRootFromParent_Done,
     /* 279156 */   // Label 5395: @279156
     /* 279156 */   GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(279204), // Rule ID 12852 //
     /* 279161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 279164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltt_lane),
     /* 279169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279178 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279185 */     // MIs[0] Op4
     /* 279185 */     // No operand predicates
     /* 279185 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1524:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLTT_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 279185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTT_ZZZI),
     /* 279188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279194 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279196 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 279198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 279202 */     GIR_RootConstrainSelectedInstOperands,
     /* 279203 */     // GIR_Coverage, 12852,
     /* 279203 */     GIR_EraseRootFromParent_Done,
     /* 279204 */   // Label 5396: @279204
     /* 279204 */   GIM_Reject,
     /* 279205 */ // Label 5346: @279205
     /* 279205 */ GIM_Reject,
     /* 279206 */ // Label 39: @279206
     /* 279206 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 5401*/ GIMT_Encode4(279495),
     /* 279217 */ /*GILLT_s64*//*Label 5397*/ GIMT_Encode4(279249), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 279229 */ /*GILLT_v2s64*//*Label 5398*/ GIMT_Encode4(279309), GIMT_Encode4(0),
     /* 279237 */ /*GILLT_v4s32*//*Label 5399*/ GIMT_Encode4(279371), GIMT_Encode4(0),
     /* 279245 */ /*GILLT_v8s16*//*Label 5400*/ GIMT_Encode4(279433),
     /* 279249 */ // Label 5397: @279249
     /* 279249 */ GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(279308), // Rule ID 6577 //
     /* 279254 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 279257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 279261 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 279265 */   // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
     /* 279265 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 279268 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 279272 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 279277 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 279279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 279282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 279284 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 279287 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 279289 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 279292 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 279297 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 279302 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 279307 */   // GIR_Coverage, 6577,
     /* 279307 */   GIR_EraseRootFromParent_Done,
     /* 279308 */ // Label 5402: @279308
     /* 279308 */ GIM_Reject,
     /* 279309 */ // Label 5398: @279309
     /* 279309 */ GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(279370),
     /* 279314 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 279317 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279321 */   GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(279348), // Rule ID 6439 //
     /* 279326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 279333 */     // (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 279333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
     /* 279336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 279343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279346 */     GIR_RootConstrainSelectedInstOperands,
     /* 279347 */     // GIR_Coverage, 6439,
     /* 279347 */     GIR_EraseRootFromParent_Done,
     /* 279348 */   // Label 5404: @279348
     /* 279348 */   GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(279369), // Rule ID 6432 //
     /* 279353 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 279357 */     // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 279357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 279360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279362 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 279364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279367 */     GIR_RootConstrainSelectedInstOperands,
     /* 279368 */     // GIR_Coverage, 6432,
     /* 279368 */     GIR_EraseRootFromParent_Done,
     /* 279369 */   // Label 5405: @279369
     /* 279369 */   GIM_Reject,
     /* 279370 */ // Label 5403: @279370
     /* 279370 */ GIM_Reject,
     /* 279371 */ // Label 5399: @279371
     /* 279371 */ GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(279432),
     /* 279376 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 279379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279383 */   GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(279410), // Rule ID 6436 //
     /* 279388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 279395 */     // (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 279395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
     /* 279398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 279405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279408 */     GIR_RootConstrainSelectedInstOperands,
     /* 279409 */     // GIR_Coverage, 6436,
     /* 279409 */     GIR_EraseRootFromParent_Done,
     /* 279410 */   // Label 5407: @279410
     /* 279410 */   GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(279431), // Rule ID 6429 //
     /* 279415 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 279419 */     // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 279419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 279422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279424 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 279426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279429 */     GIR_RootConstrainSelectedInstOperands,
     /* 279430 */     // GIR_Coverage, 6429,
     /* 279430 */     GIR_EraseRootFromParent_Done,
     /* 279431 */   // Label 5408: @279431
     /* 279431 */   GIM_Reject,
     /* 279432 */ // Label 5406: @279432
     /* 279432 */ GIM_Reject,
     /* 279433 */ // Label 5400: @279433
     /* 279433 */ GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(279494),
     /* 279438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 279441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279445 */   GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(279472), // Rule ID 6433 //
     /* 279450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 279457 */     // (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 279457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
     /* 279460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 279467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279470 */     GIR_RootConstrainSelectedInstOperands,
     /* 279471 */     // GIR_Coverage, 6433,
     /* 279471 */     GIR_EraseRootFromParent_Done,
     /* 279472 */   // Label 5410: @279472
     /* 279472 */   GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(279493), // Rule ID 6426 //
     /* 279477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 279481 */     // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 279481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 279484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279486 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 279488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 279491 */     GIR_RootConstrainSelectedInstOperands,
     /* 279492 */     // GIR_Coverage, 6426,
     /* 279492 */     GIR_EraseRootFromParent_Done,
     /* 279493 */   // Label 5411: @279493
     /* 279493 */   GIM_Reject,
     /* 279494 */ // Label 5409: @279494
     /* 279494 */ GIM_Reject,
     /* 279495 */ // Label 5401: @279495
     /* 279495 */ GIM_Reject,
     /* 279496 */ // Label 40: @279496
     /* 279496 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(10), /*)*//*default:*//*Label 5416*/ GIMT_Encode4(280932),
     /* 279507 */ /*GILLT_s32*//*Label 5412*/ GIMT_Encode4(279539), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 279519 */ /*GILLT_v2s32*//*Label 5413*/ GIMT_Encode4(279578), GIMT_Encode4(0),
     /* 279527 */ /*GILLT_v4s16*//*Label 5414*/ GIMT_Encode4(279934), GIMT_Encode4(0),
     /* 279535 */ /*GILLT_v8s8*//*Label 5415*/ GIMT_Encode4(280433),
     /* 279539 */ // Label 5412: @279539
     /* 279539 */ GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(279577), // Rule ID 6598 //
     /* 279544 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 279547 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 279551 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 279555 */   // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src)  =>  (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] })
     /* 279555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 279558 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 279560 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // src
     /* 279566 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 279571 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 279576 */   // GIR_Coverage, 6598,
     /* 279576 */   GIR_EraseRootFromParent_Done,
     /* 279577 */ // Label 5417: @279577
     /* 279577 */ GIM_Reject,
     /* 279578 */ // Label 5413: @279578
     /* 279578 */ GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(279933),
     /* 279583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 279590 */   GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(279668), // Rule ID 5478 //
     /* 279595 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279599 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 279603 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 279611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 279615 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279619 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 279623 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279628 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 279632 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 279638 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 279640 */     // MIs[1] Operand 2
     /* 279640 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 279651 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 279653 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 279653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 279656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 279662 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 279666 */     GIR_RootConstrainSelectedInstOperands,
     /* 279667 */     // GIR_Coverage, 5478,
     /* 279667 */     GIR_EraseRootFromParent_Done,
     /* 279668 */   // Label 5419: @279668
     /* 279668 */   GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(279739), // Rule ID 5474 //
     /* 279673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 279681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279685 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 279689 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 279693 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279697 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 279701 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279706 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279711 */     // MIs[1] Operand 2
     /* 279711 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 279722 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 279724 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 279724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
     /* 279727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 279733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 279737 */     GIR_RootConstrainSelectedInstOperands,
     /* 279738 */     // GIR_Coverage, 5474,
     /* 279738 */     GIR_EraseRootFromParent_Done,
     /* 279739 */   // Label 5420: @279739
     /* 279739 */   GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(279810), // Rule ID 5476 //
     /* 279744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 279752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279756 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 279760 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 279764 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279768 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 279772 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279777 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279782 */     // MIs[1] Operand 2
     /* 279782 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 279793 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 279795 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 279795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 279798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279800 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 279804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 279808 */     GIR_RootConstrainSelectedInstOperands,
     /* 279809 */     // GIR_Coverage, 5476,
     /* 279809 */     GIR_EraseRootFromParent_Done,
     /* 279810 */   // Label 5421: @279810
     /* 279810 */   GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(279863), // Rule ID 2166 //
     /* 279815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 279818 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279822 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 279826 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279830 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279835 */     // MIs[1] imm
     /* 279835 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 279839 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 279843 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 279847 */     // MIs[2] Operand 1
     /* 279847 */     // No operand predicates
     /* 279847 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 279849 */     // (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 279849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
     /* 279852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279854 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 279858 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 279861 */     GIR_RootConstrainSelectedInstOperands,
     /* 279862 */     // GIR_Coverage, 2166,
     /* 279862 */     GIR_EraseRootFromParent_Done,
     /* 279863 */   // Label 5422: @279863
     /* 279863 */   GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(279913), // Rule ID 6414 //
     /* 279868 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279872 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 279876 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 279880 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279885 */     // MIs[1] imm
     /* 279885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 279889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 279893 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 279897 */     // MIs[2] Operand 1
     /* 279897 */     // No operand predicates
     /* 279897 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 279899 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 279899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
     /* 279902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 279904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 279908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 279911 */     GIR_RootConstrainSelectedInstOperands,
     /* 279912 */     // GIR_Coverage, 6414,
     /* 279912 */     GIR_EraseRootFromParent_Done,
     /* 279913 */   // Label 5423: @279913
     /* 279913 */   GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(279932), // Rule ID 1103 //
     /* 279918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 279921 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279925 */     // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)  =>  (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
     /* 279925 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv2i32),
     /* 279930 */     GIR_RootConstrainSelectedInstOperands,
     /* 279931 */     // GIR_Coverage, 1103,
     /* 279931 */     GIR_Done,
     /* 279932 */   // Label 5424: @279932
     /* 279932 */   GIM_Reject,
     /* 279933 */ // Label 5418: @279933
     /* 279933 */ GIM_Reject,
     /* 279934 */ // Label 5414: @279934
     /* 279934 */ GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(280432),
     /* 279939 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 279942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 279946 */   GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(280024), // Rule ID 5472 //
     /* 279951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 279955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 279959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 279963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 279967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 279971 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 279975 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 279979 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 279984 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 279988 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 279994 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 279996 */     // MIs[1] Operand 2
     /* 279996 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 280007 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 280009 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 280009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 280012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280022 */     GIR_RootConstrainSelectedInstOperands,
     /* 280023 */     // GIR_Coverage, 5472,
     /* 280023 */     GIR_EraseRootFromParent_Done,
     /* 280024 */   // Label 5426: @280024
     /* 280024 */   GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(280095), // Rule ID 5468 //
     /* 280029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280041 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280045 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 280049 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280053 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 280057 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280062 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280067 */     // MIs[1] Operand 2
     /* 280067 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 280078 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280080 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 280080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
     /* 280083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280089 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280093 */     GIR_RootConstrainSelectedInstOperands,
     /* 280094 */     // GIR_Coverage, 5468,
     /* 280094 */     GIR_EraseRootFromParent_Done,
     /* 280095 */   // Label 5427: @280095
     /* 280095 */   GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(280166), // Rule ID 5470 //
     /* 280100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280112 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280116 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 280120 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280124 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 280128 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280133 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280138 */     // MIs[1] Operand 2
     /* 280138 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 280149 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280151 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 280151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 280154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280164 */     GIR_RootConstrainSelectedInstOperands,
     /* 280165 */     // GIR_Coverage, 5470,
     /* 280165 */     GIR_EraseRootFromParent_Done,
     /* 280166 */   // Label 5428: @280166
     /* 280166 */   GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(280258), // Rule ID 5594 //
     /* 280171 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280175 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 280179 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 280182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 280186 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 280190 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280194 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 280198 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 280202 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280207 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 280211 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 280215 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 280219 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280224 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 280226 */     // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm)))  =>  (XTNv4i16:{ *:[v4i16] } (UZP1v4i32:{ *:[f128] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm))
     /* 280226 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 280229 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 280233 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280238 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 280242 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
     /* 280246 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 280248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
     /* 280251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280253 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 280256 */     GIR_RootConstrainSelectedInstOperands,
     /* 280257 */     // GIR_Coverage, 5594,
     /* 280257 */     GIR_EraseRootFromParent_Done,
     /* 280258 */   // Label 5429: @280258
     /* 280258 */   GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(280311), // Rule ID 2165 //
     /* 280263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 280266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 280274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280283 */     // MIs[1] imm
     /* 280283 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 280287 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 280291 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 280295 */     // MIs[2] Operand 1
     /* 280295 */     // No operand predicates
     /* 280295 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280297 */     // (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 280297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
     /* 280300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280302 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 280306 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 280309 */     GIR_RootConstrainSelectedInstOperands,
     /* 280310 */     // GIR_Coverage, 2165,
     /* 280310 */     GIR_EraseRootFromParent_Done,
     /* 280311 */   // Label 5430: @280311
     /* 280311 */   GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(280361), // Rule ID 6413 //
     /* 280316 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280320 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280324 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280328 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280333 */     // MIs[1] imm
     /* 280333 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 280337 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 280341 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 280345 */     // MIs[2] Operand 1
     /* 280345 */     // No operand predicates
     /* 280345 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280347 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 280347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
     /* 280350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280352 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 280356 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 280359 */     GIR_RootConstrainSelectedInstOperands,
     /* 280360 */     // GIR_Coverage, 6413,
     /* 280360 */     GIR_EraseRootFromParent_Done,
     /* 280361 */   // Label 5431: @280361
     /* 280361 */   GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(280412), // Rule ID 5622 //
     /* 280366 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280370 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 280374 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 280377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 280381 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 280385 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280390 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280395 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 280397 */     // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm))  =>  (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm)
     /* 280397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 280400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 280406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /* 280410 */     GIR_RootConstrainSelectedInstOperands,
     /* 280411 */     // GIR_Coverage, 5622,
     /* 280411 */     GIR_EraseRootFromParent_Done,
     /* 280412 */   // Label 5432: @280412
     /* 280412 */   GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(280431), // Rule ID 1102 //
     /* 280417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 280420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280424 */     // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)  =>  (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
     /* 280424 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
     /* 280429 */     GIR_RootConstrainSelectedInstOperands,
     /* 280430 */     // GIR_Coverage, 1102,
     /* 280430 */     GIR_Done,
     /* 280431 */   // Label 5433: @280431
     /* 280431 */   GIM_Reject,
     /* 280432 */ // Label 5425: @280432
     /* 280432 */ GIM_Reject,
     /* 280433 */ // Label 5415: @280433
     /* 280433 */ GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(280931),
     /* 280438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280445 */   GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(280523), // Rule ID 5466 //
     /* 280450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 280470 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280474 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 280478 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280483 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 280487 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 280493 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 280495 */     // MIs[1] Operand 2
     /* 280495 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 280506 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 280508 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 280508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 280511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280513 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280517 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280521 */     GIR_RootConstrainSelectedInstOperands,
     /* 280522 */     // GIR_Coverage, 5466,
     /* 280522 */     GIR_EraseRootFromParent_Done,
     /* 280523 */   // Label 5435: @280523
     /* 280523 */   GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(280594), // Rule ID 5462 //
     /* 280528 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280532 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280536 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280540 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280544 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 280548 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280552 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 280556 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280561 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280566 */     // MIs[1] Operand 2
     /* 280566 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 280577 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280579 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 280579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
     /* 280582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280584 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280588 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280592 */     GIR_RootConstrainSelectedInstOperands,
     /* 280593 */     // GIR_Coverage, 5462,
     /* 280593 */     GIR_EraseRootFromParent_Done,
     /* 280594 */   // Label 5436: @280594
     /* 280594 */   GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(280665), // Rule ID 5464 //
     /* 280599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280611 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280615 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 280619 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280623 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 280627 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280632 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280637 */     // MIs[1] Operand 2
     /* 280637 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 280648 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280650 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 280650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 280653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280655 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 280659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 280663 */     GIR_RootConstrainSelectedInstOperands,
     /* 280664 */     // GIR_Coverage, 5464,
     /* 280664 */     GIR_EraseRootFromParent_Done,
     /* 280665 */   // Label 5437: @280665
     /* 280665 */   GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(280757), // Rule ID 5567 //
     /* 280670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 280678 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 280681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 280685 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 280689 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 280693 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 280697 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280701 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280706 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 280710 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 280714 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 280718 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280723 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 280725 */     // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm)))  =>  (XTNv8i8:{ *:[v8i8] } (UZP1v8i16:{ *:[f128] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm))
     /* 280725 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 280728 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 280732 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280737 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 280741 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
     /* 280745 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 280747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
     /* 280750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280752 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 280755 */     GIR_RootConstrainSelectedInstOperands,
     /* 280756 */     // GIR_Coverage, 5567,
     /* 280756 */     GIR_EraseRootFromParent_Done,
     /* 280757 */   // Label 5438: @280757
     /* 280757 */   GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(280810), // Rule ID 2164 //
     /* 280762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 280765 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 280773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280777 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280782 */     // MIs[1] imm
     /* 280782 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 280786 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 280790 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 280794 */     // MIs[2] Operand 1
     /* 280794 */     // No operand predicates
     /* 280794 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280796 */     // (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 280796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
     /* 280799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 280805 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 280808 */     GIR_RootConstrainSelectedInstOperands,
     /* 280809 */     // GIR_Coverage, 2164,
     /* 280809 */     GIR_EraseRootFromParent_Done,
     /* 280810 */   // Label 5439: @280810
     /* 280810 */   GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(280860), // Rule ID 6412 //
     /* 280815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 280823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 280827 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280832 */     // MIs[1] imm
     /* 280832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 280836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 280840 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 280844 */     // MIs[2] Operand 1
     /* 280844 */     // No operand predicates
     /* 280844 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 280846 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 280846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
     /* 280849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 280855 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 280858 */     GIR_RootConstrainSelectedInstOperands,
     /* 280859 */     // GIR_Coverage, 6412,
     /* 280859 */     GIR_EraseRootFromParent_Done,
     /* 280860 */   // Label 5440: @280860
     /* 280860 */   GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(280911), // Rule ID 5621 //
     /* 280865 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 280869 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 280873 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 280876 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 280880 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 280884 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280889 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280894 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 280896 */     // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm))  =>  (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm)
     /* 280896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
     /* 280899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280901 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 280905 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /* 280909 */     GIR_RootConstrainSelectedInstOperands,
     /* 280910 */     // GIR_Coverage, 5621,
     /* 280910 */     GIR_EraseRootFromParent_Done,
     /* 280911 */   // Label 5441: @280911
     /* 280911 */   GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(280930), // Rule ID 1101 //
     /* 280916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 280919 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280923 */     // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)  =>  (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
     /* 280923 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
     /* 280928 */     GIR_RootConstrainSelectedInstOperands,
     /* 280929 */     // GIR_Coverage, 1101,
     /* 280929 */     GIR_Done,
     /* 280930 */   // Label 5442: @280930
     /* 280930 */   GIM_Reject,
     /* 280931 */ // Label 5434: @280931
     /* 280931 */ GIM_Reject,
     /* 280932 */ // Label 5416: @280932
     /* 280932 */ GIM_Reject,
     /* 280933 */ // Label 41: @280933
     /* 280933 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5445*/ GIMT_Encode4(281052),
     /* 280944 */ /*GILLT_s32*//*Label 5443*/ GIMT_Encode4(280952),
     /* 280948 */ /*GILLT_s64*//*Label 5444*/ GIMT_Encode4(280972),
     /* 280952 */ // Label 5443: @280952
     /* 280952 */ GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(280971), // Rule ID 81 //
     /* 280957 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 280961 */   // MIs[0] Operand 1
     /* 280961 */   // No operand predicates
     /* 280961 */   // (imm:{ *:[i32] }):$src  =>  (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
     /* 280961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /* 280964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 280966 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
     /* 280969 */   GIR_RootConstrainSelectedInstOperands,
     /* 280970 */   // GIR_Coverage, 81,
     /* 280970 */   GIR_EraseRootFromParent_Done,
     /* 280971 */ // Label 5446: @280971
     /* 280971 */ GIM_Reject,
     /* 280972 */ // Label 5444: @280972
     /* 280972 */ GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(281032), // Rule ID 3938 //
     /* 280977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_OptimizedGISelOrOtherSelector),
     /* 280980 */   GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /* 280984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 280988 */   // MIs[0] Operand 1
     /* 280988 */   // No operand predicates
     /* 280988 */   // (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$src  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] })
     /* 280988 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 280991 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /* 280995 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281000 */   GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // src
     /* 281005 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 281007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 281010 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 281012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281015 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 281021 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 281026 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281031 */   // GIR_Coverage, 3938,
     /* 281031 */   GIR_EraseRootFromParent_Done,
     /* 281032 */ // Label 5447: @281032
     /* 281032 */ GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(281051), // Rule ID 82 //
     /* 281037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 281041 */   // MIs[0] Operand 1
     /* 281041 */   // No operand predicates
     /* 281041 */   // (imm:{ *:[i64] }):$src  =>  (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src)
     /* 281041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi64imm),
     /* 281044 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 281046 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
     /* 281049 */   GIR_RootConstrainSelectedInstOperands,
     /* 281050 */   // GIR_Coverage, 82,
     /* 281050 */   GIR_EraseRootFromParent_Done,
     /* 281051 */ // Label 5448: @281051
     /* 281051 */ GIM_Reject,
     /* 281052 */ // Label 5445: @281052
     /* 281052 */ GIM_Reject,
     /* 281053 */ // Label 42: @281053
     /* 281053 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 5452*/ GIMT_Encode4(281293),
     /* 281064 */ /*GILLT_s16*//*Label 5449*/ GIMT_Encode4(281076),
     /* 281068 */ /*GILLT_s32*//*Label 5450*/ GIMT_Encode4(281128),
     /* 281072 */ /*GILLT_s64*//*Label 5451*/ GIMT_Encode4(281241),
     /* 281076 */ // Label 5449: @281076
     /* 281076 */ GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(281099), // Rule ID 510 //
     /* 281081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 281084 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 281088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 281092 */   // MIs[0] Operand 1
     /* 281092 */   // No operand predicates
     /* 281092 */   // (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>  =>  (FMOVH0:{ *:[f16] })
     /* 281092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVH0),
     /* 281095 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281097 */   GIR_RootConstrainSelectedInstOperands,
     /* 281098 */   // GIR_Coverage, 510,
     /* 281098 */   GIR_EraseRootFromParent_Done,
     /* 281099 */ // Label 5453: @281099
     /* 281099 */ GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(281127), // Rule ID 692 //
     /* 281104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 281107 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 281111 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 281115 */   // MIs[0] Operand 1
     /* 281115 */   // No operand predicates
     /* 281115 */   // (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm  =>  (FMOVHi:{ *:[f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] }):$imm))
     /* 281115 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVHi),
     /* 281118 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281120 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm
     /* 281125 */   GIR_RootConstrainSelectedInstOperands,
     /* 281126 */   // GIR_Coverage, 692,
     /* 281126 */   GIR_EraseRootFromParent_Done,
     /* 281127 */ // Label 5454: @281127
     /* 281127 */ GIM_Reject,
     /* 281128 */ // Label 5450: @281128
     /* 281128 */ GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(281151), // Rule ID 511 //
     /* 281133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 281136 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 281140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 281144 */   // MIs[0] Operand 1
     /* 281144 */   // No operand predicates
     /* 281144 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>  =>  (FMOVS0:{ *:[f32] })
     /* 281144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVS0),
     /* 281147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281149 */   GIR_RootConstrainSelectedInstOperands,
     /* 281150 */   // GIR_Coverage, 511,
     /* 281150 */   GIR_EraseRootFromParent_Done,
     /* 281151 */ // Label 5455: @281151
     /* 281151 */ GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(281179), // Rule ID 693 //
     /* 281156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 281159 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 281163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 281167 */   // MIs[0] Operand 1
     /* 281167 */   // No operand predicates
     /* 281167 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm  =>  (FMOVSi:{ *:[f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
     /* 281167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVSi),
     /* 281170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281172 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm
     /* 281177 */   GIR_RootConstrainSelectedInstOperands,
     /* 281178 */   // GIR_Coverage, 693,
     /* 281178 */   GIR_EraseRootFromParent_Done,
     /* 281179 */ // Label 5456: @281179
     /* 281179 */ GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(281240), // Rule ID 6101 //
     /* 281184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 281187 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4),
     /* 281191 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 281195 */   // MIs[0] Operand 1
     /* 281195 */   // No operand predicates
     /* 281195 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32SIMDModImmType4>><<X:fpimm32SIMDModImmType4XForm>>:$in  =>  (EXTRACT_SUBREG:{ *:[f32] } (MOVIv2i32:{ *:[i64] } (fpimm32SIMDModImmType4XForm:{ *:[i32] } f32:{ *:[f32] }:$in), 24:{ *:[i32] }), ssub:{ *:[i32] })
     /* 281195 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 281198 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2i32),
     /* 281202 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281207 */   GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32SIMDModImmType4), // in
     /* 281212 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/24,
     /* 281215 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 281217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 281220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 281222 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 281229 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 281234 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281239 */   // GIR_Coverage, 6101,
     /* 281239 */   GIR_EraseRootFromParent_Done,
     /* 281240 */ // Label 5457: @281240
     /* 281240 */ GIM_Reject,
     /* 281241 */ // Label 5451: @281241
     /* 281241 */ GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(281264), // Rule ID 512 //
     /* 281246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 281249 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 281253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281257 */   // MIs[0] Operand 1
     /* 281257 */   // No operand predicates
     /* 281257 */   // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>  =>  (FMOVD0:{ *:[f64] })
     /* 281257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVD0),
     /* 281260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281262 */   GIR_RootConstrainSelectedInstOperands,
     /* 281263 */   // GIR_Coverage, 512,
     /* 281263 */   GIR_EraseRootFromParent_Done,
     /* 281264 */ // Label 5458: @281264
     /* 281264 */ GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(281292), // Rule ID 694 //
     /* 281269 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 281272 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 281276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281280 */   // MIs[0] Operand 1
     /* 281280 */   // No operand predicates
     /* 281280 */   // (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm  =>  (FMOVDi:{ *:[f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
     /* 281280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVDi),
     /* 281283 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281285 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm
     /* 281290 */   GIR_RootConstrainSelectedInstOperands,
     /* 281291 */   // GIR_Coverage, 694,
     /* 281291 */   GIR_EraseRootFromParent_Done,
     /* 281292 */ // Label 5459: @281292
     /* 281292 */ GIM_Reject,
     /* 281293 */ // Label 5452: @281293
     /* 281293 */ GIM_Reject,
     /* 281294 */ // Label 43: @281294
     /* 281294 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5465*/ GIMT_Encode4(283191),
     /* 281305 */ /*GILLT_s32*//*Label 5460*/ GIMT_Encode4(281341),
     /* 281309 */ /*GILLT_s64*//*Label 5461*/ GIMT_Encode4(282782), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 281321 */ /*GILLT_v2s64*//*Label 5462*/ GIMT_Encode4(283005), GIMT_Encode4(0),
     /* 281329 */ /*GILLT_v4s32*//*Label 5463*/ GIMT_Encode4(283067), GIMT_Encode4(0),
     /* 281337 */ /*GILLT_v8s16*//*Label 5464*/ GIMT_Encode4(283129),
     /* 281341 */ // Label 5460: @281341
     /* 281341 */ GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(281461), // Rule ID 13423 //
     /* 281346 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 281349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281353 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281357 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281361 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281364 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 281369 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 281373 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281378 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281380 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 672:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281380 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 281383 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 281387 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281392 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281396 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281398 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 281401 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281405 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281410 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281412 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 281415 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281419 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281424 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281427 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 281430 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 281433 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281438 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281443 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 281448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 281451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281453 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281459 */   GIR_RootConstrainSelectedInstOperands,
     /* 281460 */   // GIR_Coverage, 13423,
     /* 281460 */   GIR_EraseRootFromParent_Done,
     /* 281461 */ // Label 5466: @281461
     /* 281461 */ GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(281581), // Rule ID 13425 //
     /* 281466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 281469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281473 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281477 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281481 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281484 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 281489 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 281493 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281498 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281500 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 672:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281500 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 281503 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 281507 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281512 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281516 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281518 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 281521 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281525 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281530 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281532 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 281535 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281539 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281544 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281547 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 281550 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 281553 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281558 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281563 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 281568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 281571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281573 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281579 */   GIR_RootConstrainSelectedInstOperands,
     /* 281580 */   // GIR_Coverage, 13425,
     /* 281580 */   GIR_EraseRootFromParent_Done,
     /* 281581 */ // Label 5467: @281581
     /* 281581 */ GIM_Try, /*On fail goto*//*Label 5468*/ GIMT_Encode4(281701), // Rule ID 13427 //
     /* 281586 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 281589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281593 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281597 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281601 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281604 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 281609 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 281613 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281618 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281620 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 672:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281620 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 281623 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 281627 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281632 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281636 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281638 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 281641 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281645 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281650 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281652 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 281655 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281659 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281664 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281667 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 281670 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 281673 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281678 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281683 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 281688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 281691 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281693 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281699 */   GIR_RootConstrainSelectedInstOperands,
     /* 281700 */   // GIR_Coverage, 13427,
     /* 281700 */   GIR_EraseRootFromParent_Done,
     /* 281701 */ // Label 5468: @281701
     /* 281701 */ GIM_Try, /*On fail goto*//*Label 5469*/ GIMT_Encode4(281821), // Rule ID 13429 //
     /* 281706 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 281709 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281713 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281717 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281721 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281724 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 281729 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 281733 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281738 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281740 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 672:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281740 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 281743 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 281747 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281752 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281756 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281758 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 281761 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281765 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281770 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281772 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 281775 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281779 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281784 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281787 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 281790 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 281793 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281798 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281803 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 281808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 281811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281813 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281816 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281819 */   GIR_RootConstrainSelectedInstOperands,
     /* 281820 */   // GIR_Coverage, 13429,
     /* 281820 */   GIR_EraseRootFromParent_Done,
     /* 281821 */ // Label 5469: @281821
     /* 281821 */ GIM_Try, /*On fail goto*//*Label 5470*/ GIMT_Encode4(281941), // Rule ID 13445 //
     /* 281826 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 281829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281833 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281837 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281841 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281844 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 281849 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 281853 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281858 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281860 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 682:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281860 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 281863 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 281867 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281872 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281876 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281878 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 281881 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281885 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281890 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281892 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 281895 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281899 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281904 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281907 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 281910 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 281913 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281918 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281923 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 281928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 281931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281933 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281936 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 281939 */   GIR_RootConstrainSelectedInstOperands,
     /* 281940 */   // GIR_Coverage, 13445,
     /* 281940 */   GIR_EraseRootFromParent_Done,
     /* 281941 */ // Label 5470: @281941
     /* 281941 */ GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(282061), // Rule ID 13447 //
     /* 281946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 281949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 281953 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 281957 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 281961 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 281964 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 281969 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 281973 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281978 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 281980 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 682:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 281980 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 281983 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 281987 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281992 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 281996 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 281998 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282001 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282005 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282010 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282012 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282015 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282019 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282024 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282027 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282030 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 282033 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282038 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282043 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 282048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 282051 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282053 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282059 */   GIR_RootConstrainSelectedInstOperands,
     /* 282060 */   // GIR_Coverage, 13447,
     /* 282060 */   GIR_EraseRootFromParent_Done,
     /* 282061 */ // Label 5471: @282061
     /* 282061 */ GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(282181), // Rule ID 13449 //
     /* 282066 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 282069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282073 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282077 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282081 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282084 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 282089 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 282093 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 282098 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282100 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 682:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282100 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 282103 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 282107 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282112 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282116 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282118 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282121 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282125 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282130 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282132 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282135 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282139 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282144 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282147 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282150 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 282153 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282158 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282163 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 282168 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 282171 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282173 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282176 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282179 */   GIR_RootConstrainSelectedInstOperands,
     /* 282180 */   // GIR_Coverage, 13449,
     /* 282180 */   GIR_EraseRootFromParent_Done,
     /* 282181 */ // Label 5472: @282181
     /* 282181 */ GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(282301), // Rule ID 13451 //
     /* 282186 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 282189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282193 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282197 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282201 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282204 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 282209 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 282213 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282218 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282220 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282220 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 282223 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 282227 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282232 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282236 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282238 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282241 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282245 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282250 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282252 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282255 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282259 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282264 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282267 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282270 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 282273 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282278 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282283 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 282288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 282291 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282293 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282299 */   GIR_RootConstrainSelectedInstOperands,
     /* 282300 */   // GIR_Coverage, 13451,
     /* 282300 */   GIR_EraseRootFromParent_Done,
     /* 282301 */ // Label 5473: @282301
     /* 282301 */ GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(282421), // Rule ID 13455 //
     /* 282306 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 282309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282313 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282317 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282321 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282324 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 282329 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 282333 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 282338 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282340 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282340 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 282343 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 282347 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282352 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282356 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282358 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282361 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282365 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282370 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282372 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282375 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282379 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282384 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282387 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282390 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 282393 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282398 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282403 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 282408 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 282411 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282413 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282419 */   GIR_RootConstrainSelectedInstOperands,
     /* 282420 */   // GIR_Coverage, 13455,
     /* 282420 */   GIR_EraseRootFromParent_Done,
     /* 282421 */ // Label 5474: @282421
     /* 282421 */ GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(282541), // Rule ID 13457 //
     /* 282426 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 282429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282433 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282437 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282441 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282444 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 282449 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 282453 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282458 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282460 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282460 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 282463 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 282467 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282472 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282476 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282478 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282481 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282485 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282490 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282492 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282495 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282499 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282504 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282507 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282510 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 282513 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282518 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282523 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 282528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 282531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282533 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282539 */   GIR_RootConstrainSelectedInstOperands,
     /* 282540 */   // GIR_Coverage, 13457,
     /* 282540 */   GIR_EraseRootFromParent_Done,
     /* 282541 */ // Label 5475: @282541
     /* 282541 */ GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(282661), // Rule ID 13459 //
     /* 282546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 282549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282553 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282557 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282561 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282564 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 282569 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 282573 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 282578 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282580 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282580 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 282583 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 282587 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282592 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282596 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282598 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282601 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282605 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282610 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282612 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282615 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282619 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282624 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282627 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282630 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 282633 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282638 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282643 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 282648 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 282651 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282653 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282656 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282659 */   GIR_RootConstrainSelectedInstOperands,
     /* 282660 */   // GIR_Coverage, 13459,
     /* 282660 */   GIR_EraseRootFromParent_Done,
     /* 282661 */ // Label 5476: @282661
     /* 282661 */ GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(282781), // Rule ID 13461 //
     /* 282666 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 282669 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282673 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282677 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 282681 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 282684 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 282689 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 282693 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282698 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 282700 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 282700 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 282703 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 282707 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282712 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 282716 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 282718 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 282721 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282725 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282730 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282732 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 282735 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282739 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282744 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282747 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 282750 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 282753 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282758 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282763 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 282768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 282771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282773 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282779 */   GIR_RootConstrainSelectedInstOperands,
     /* 282780 */   // GIR_Coverage, 13461,
     /* 282780 */   GIR_EraseRootFromParent_Done,
     /* 282781 */ // Label 5477: @282781
     /* 282781 */ GIM_Reject,
     /* 282782 */ // Label 5461: @282782
     /* 282782 */ GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(283004),
     /* 282787 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 282790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 282794 */   GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(282848), // Rule ID 5707 //
     /* 282799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 282807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 282811 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 282815 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 282824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282828 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 282832 */     // MIs[2] Operand 1
     /* 282832 */     // No operand predicates
     /* 282832 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282834 */     // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 282834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
     /* 282837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 282843 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 282846 */     GIR_RootConstrainSelectedInstOperands,
     /* 282847 */     // GIR_Coverage, 5707,
     /* 282847 */     GIR_EraseRootFromParent_Done,
     /* 282848 */   // Label 5479: @282848
     /* 282848 */   GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(282927), // Rule ID 11357 //
     /* 282853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 282856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 282860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 282864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 282868 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 282872 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 282876 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282880 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 282884 */     // MIs[2] Operand 1
     /* 282884 */     // No operand predicates
     /* 282884 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282886 */     // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index))  =>  (SMOVvi32to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
     /* 282886 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 282889 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 282893 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282898 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 282904 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282909 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
     /* 282917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282919 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282922 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 282925 */     GIR_RootConstrainSelectedInstOperands,
     /* 282926 */     // GIR_Coverage, 11357,
     /* 282926 */     GIR_EraseRootFromParent_Done,
     /* 282927 */   // Label 5480: @282927
     /* 282927 */   GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(283003), // Rule ID 6579 //
     /* 282932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282936 */     // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] })
     /* 282936 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 282939 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 282943 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282948 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 282950 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 282953 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 282957 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 282962 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 282965 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 282969 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 282972 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 282977 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 282982 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 282987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 282990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 282992 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 282995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 282998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 283001 */     GIR_RootConstrainSelectedInstOperands,
     /* 283002 */     // GIR_Coverage, 6579,
     /* 283002 */     GIR_EraseRootFromParent_Done,
     /* 283003 */   // Label 5481: @283003
     /* 283003 */   GIM_Reject,
     /* 283004 */ // Label 5478: @283004
     /* 283004 */ GIM_Reject,
     /* 283005 */ // Label 5462: @283005
     /* 283005 */ GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(283066),
     /* 283010 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 283013 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283017 */   GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(283044), // Rule ID 6441 //
     /* 283022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 283029 */     // (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (SSHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 283029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i32_shift),
     /* 283032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 283039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283042 */     GIR_RootConstrainSelectedInstOperands,
     /* 283043 */     // GIR_Coverage, 6441,
     /* 283043 */     GIR_EraseRootFromParent_Done,
     /* 283044 */   // Label 5483: @283044
     /* 283044 */   GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(283065), // Rule ID 6430 //
     /* 283049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 283053 */     // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 283053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 283056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283058 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 283060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283063 */     GIR_RootConstrainSelectedInstOperands,
     /* 283064 */     // GIR_Coverage, 6430,
     /* 283064 */     GIR_EraseRootFromParent_Done,
     /* 283065 */   // Label 5484: @283065
     /* 283065 */   GIM_Reject,
     /* 283066 */ // Label 5482: @283066
     /* 283066 */ GIM_Reject,
     /* 283067 */ // Label 5463: @283067
     /* 283067 */ GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(283128),
     /* 283072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 283075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283079 */   GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(283106), // Rule ID 6438 //
     /* 283084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 283091 */     // (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (SSHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 283091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i16_shift),
     /* 283094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 283101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283104 */     GIR_RootConstrainSelectedInstOperands,
     /* 283105 */     // GIR_Coverage, 6438,
     /* 283105 */     GIR_EraseRootFromParent_Done,
     /* 283106 */   // Label 5486: @283106
     /* 283106 */   GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(283127), // Rule ID 6427 //
     /* 283111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 283115 */     // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 283115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 283118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283120 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 283122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283125 */     GIR_RootConstrainSelectedInstOperands,
     /* 283126 */     // GIR_Coverage, 6427,
     /* 283126 */     GIR_EraseRootFromParent_Done,
     /* 283127 */   // Label 5487: @283127
     /* 283127 */   GIM_Reject,
     /* 283128 */ // Label 5485: @283128
     /* 283128 */ GIM_Reject,
     /* 283129 */ // Label 5464: @283129
     /* 283129 */ GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(283190),
     /* 283134 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 283137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283141 */   GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(283168), // Rule ID 6435 //
     /* 283146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 283153 */     // (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (SSHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 283153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv16i8_shift),
     /* 283156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 283163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283166 */     GIR_RootConstrainSelectedInstOperands,
     /* 283167 */     // GIR_Coverage, 6435,
     /* 283167 */     GIR_EraseRootFromParent_Done,
     /* 283168 */   // Label 5489: @283168
     /* 283168 */   GIM_Try, /*On fail goto*//*Label 5490*/ GIMT_Encode4(283189), // Rule ID 6424 //
     /* 283173 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 283177 */     // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 283177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 283180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283182 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 283184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283187 */     GIR_RootConstrainSelectedInstOperands,
     /* 283188 */     // GIR_Coverage, 6424,
     /* 283188 */     GIR_EraseRootFromParent_Done,
     /* 283189 */   // Label 5490: @283189
     /* 283189 */   GIM_Reject,
     /* 283190 */ // Label 5488: @283190
     /* 283190 */ GIM_Reject,
     /* 283191 */ // Label 5465: @283191
     /* 283191 */ GIM_Reject,
     /* 283192 */ // Label 44: @283192
     /* 283192 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(22), /*)*//*default:*//*Label 5496*/ GIMT_Encode4(284845),
     /* 283203 */ /*GILLT_s32*//*Label 5491*/ GIMT_Encode4(283283),
     /* 283207 */ /*GILLT_s64*//*Label 5492*/ GIMT_Encode4(283777), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 283259 */ /*GILLT_nxv2s64*//*Label 5493*/ GIMT_Encode4(284419), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 283271 */ /*GILLT_nxv4s32*//*Label 5494*/ GIMT_Encode4(284628), GIMT_Encode4(0),
     /* 283279 */ /*GILLT_nxv8s16*//*Label 5495*/ GIMT_Encode4(284772),
     /* 283283 */ // Label 5491: @283283
     /* 283283 */ GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(283776),
     /* 283288 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 283291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 283295 */   GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(283360), // Rule ID 5702 //
     /* 283300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283308 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 283312 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 283316 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283321 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 283325 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283329 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 283333 */     // MIs[2] Operand 1
     /* 283333 */     // No operand predicates
     /* 283333 */     // MIs[0] Operand 2
     /* 283333 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 283344 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 283346 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), i8:{ *:[Other] })  =>  (SMOVvi8to32:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 283346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 283349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 283355 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 283358 */     GIR_RootConstrainSelectedInstOperands,
     /* 283359 */     // GIR_Coverage, 5702,
     /* 283359 */     GIR_EraseRootFromParent_Done,
     /* 283360 */   // Label 5498: @283360
     /* 283360 */   GIM_Try, /*On fail goto*//*Label 5499*/ GIMT_Encode4(283425), // Rule ID 5704 //
     /* 283365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 283377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 283381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 283390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283394 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 283398 */     // MIs[2] Operand 1
     /* 283398 */     // No operand predicates
     /* 283398 */     // MIs[0] Operand 2
     /* 283398 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 283409 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 283411 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 283411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 283414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283416 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 283420 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 283423 */     GIR_RootConstrainSelectedInstOperands,
     /* 283424 */     // GIR_Coverage, 5704,
     /* 283424 */     GIR_EraseRootFromParent_Done,
     /* 283425 */   // Label 5499: @283425
     /* 283425 */   GIM_Try, /*On fail goto*//*Label 5500*/ GIMT_Encode4(283490), // Rule ID 5706 //
     /* 283430 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283434 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283438 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 283442 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 283446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283451 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 283455 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283459 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 283463 */     // MIs[2] Operand 1
     /* 283463 */     // No operand predicates
     /* 283463 */     // MIs[0] Operand 2
     /* 283463 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 283474 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 283476 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 283476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 283479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 283485 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 283488 */     GIR_RootConstrainSelectedInstOperands,
     /* 283489 */     // GIR_Coverage, 5706,
     /* 283489 */     GIR_EraseRootFromParent_Done,
     /* 283490 */   // Label 5500: @283490
     /* 283490 */   GIM_Try, /*On fail goto*//*Label 5501*/ GIMT_Encode4(283580), // Rule ID 11353 //
     /* 283495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 283498 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283502 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283506 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 283510 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 283514 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 283518 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283522 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 283526 */     // MIs[2] Operand 1
     /* 283526 */     // No operand predicates
     /* 283526 */     // MIs[0] Operand 2
     /* 283526 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 283537 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 283539 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index), i8:{ *:[Other] })  =>  (SMOVvi8to32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 283539 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 283542 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 283546 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 283551 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 283557 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283562 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 283570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283572 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 283575 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 283578 */     GIR_RootConstrainSelectedInstOperands,
     /* 283579 */     // GIR_Coverage, 11353,
     /* 283579 */     GIR_EraseRootFromParent_Done,
     /* 283580 */   // Label 5501: @283580
     /* 283580 */   GIM_Try, /*On fail goto*//*Label 5502*/ GIMT_Encode4(283670), // Rule ID 11355 //
     /* 283585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 283588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 283600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 283604 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 283608 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283612 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 283616 */     // MIs[2] Operand 1
     /* 283616 */     // No operand predicates
     /* 283616 */     // MIs[0] Operand 2
     /* 283616 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 283627 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 283629 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 283629 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 283632 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 283636 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 283641 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 283647 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283652 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 283660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283662 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 283665 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 283668 */     GIR_RootConstrainSelectedInstOperands,
     /* 283669 */     // GIR_Coverage, 11355,
     /* 283669 */     GIR_EraseRootFromParent_Done,
     /* 283670 */   // Label 5502: @283670
     /* 283670 */   GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(283705), // Rule ID 6584 //
     /* 283675 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 283679 */     // MIs[0] Operand 2
     /* 283679 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 283690 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i16:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 15:{ *:[i64] })
     /* 283690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 283693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283695 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 283697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 283703 */     GIR_RootConstrainSelectedInstOperands,
     /* 283704 */     // GIR_Coverage, 6584,
     /* 283704 */     GIR_EraseRootFromParent_Done,
     /* 283705 */   // Label 5503: @283705
     /* 283705 */   GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(283740), // Rule ID 6585 //
     /* 283710 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 283714 */     // MIs[0] Operand 2
     /* 283714 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 283725 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i8:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 7:{ *:[i64] })
     /* 283725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 283728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283730 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 283732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 283738 */     GIR_RootConstrainSelectedInstOperands,
     /* 283739 */     // GIR_Coverage, 6585,
     /* 283739 */     GIR_EraseRootFromParent_Done,
     /* 283740 */   // Label 5504: @283740
     /* 283740 */   GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(283775), // Rule ID 6586 //
     /* 283745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 283749 */     // MIs[0] Operand 2
     /* 283749 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 283760 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i1:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 0:{ *:[i64] })
     /* 283760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 283763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283765 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 283767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 283773 */     GIR_RootConstrainSelectedInstOperands,
     /* 283774 */     // GIR_Coverage, 6586,
     /* 283774 */     GIR_EraseRootFromParent_Done,
     /* 283775 */   // Label 5505: @283775
     /* 283775 */   GIM_Reject,
     /* 283776 */ // Label 5497: @283776
     /* 283776 */ GIM_Reject,
     /* 283777 */ // Label 5492: @283777
     /* 283777 */ GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(284418),
     /* 283782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 283785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 283789 */   GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(283866), // Rule ID 5708 //
     /* 283794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 283802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 283806 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 283810 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283814 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 283818 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 283822 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283827 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 283831 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283835 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 283839 */     // MIs[3] Operand 1
     /* 283839 */     // No operand predicates
     /* 283839 */     // MIs[0] Operand 2
     /* 283839 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 283850 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 283852 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 283852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 283855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283857 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 283861 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 283864 */     GIR_RootConstrainSelectedInstOperands,
     /* 283865 */     // GIR_Coverage, 5708,
     /* 283865 */     GIR_EraseRootFromParent_Done,
     /* 283866 */   // Label 5507: @283866
     /* 283866 */   GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(283943), // Rule ID 5709 //
     /* 283871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 283879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 283883 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 283887 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283891 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 283895 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 283899 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 283904 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 283908 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283912 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 283916 */     // MIs[3] Operand 1
     /* 283916 */     // No operand predicates
     /* 283916 */     // MIs[0] Operand 2
     /* 283916 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 283927 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 283929 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 283929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 283932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 283934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 283938 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 283941 */     GIR_RootConstrainSelectedInstOperands,
     /* 283942 */     // GIR_Coverage, 5709,
     /* 283942 */     GIR_EraseRootFromParent_Done,
     /* 283943 */   // Label 5508: @283943
     /* 283943 */   GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(284045), // Rule ID 11354 //
     /* 283948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 283951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 283955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 283959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 283963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 283967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 283971 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 283975 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 283979 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 283983 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 283987 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 283991 */     // MIs[3] Operand 1
     /* 283991 */     // No operand predicates
     /* 283991 */     // MIs[0] Operand 2
     /* 283991 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284002 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 284004 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 284004 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 284007 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 284011 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284016 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 284022 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284027 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 284035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284037 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284040 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // index
     /* 284043 */     GIR_RootConstrainSelectedInstOperands,
     /* 284044 */     // GIR_Coverage, 11354,
     /* 284044 */     GIR_EraseRootFromParent_Done,
     /* 284045 */   // Label 5509: @284045
     /* 284045 */   GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(284147), // Rule ID 11356 //
     /* 284050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 284053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 284057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 284061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 284065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 284069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 284073 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 284077 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 284081 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 284085 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 284089 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 284093 */     // MIs[3] Operand 1
     /* 284093 */     // No operand predicates
     /* 284093 */     // MIs[0] Operand 2
     /* 284093 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 284104 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 284106 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 284106 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 284109 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 284113 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284118 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 284124 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284129 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 284137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284139 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284142 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // index
     /* 284145 */     GIR_RootConstrainSelectedInstOperands,
     /* 284146 */     // GIR_Coverage, 11356,
     /* 284146 */     GIR_EraseRootFromParent_Done,
     /* 284147 */   // Label 5510: @284147
     /* 284147 */   GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(284212), // Rule ID 5703 //
     /* 284152 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 284156 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 284160 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 284164 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 284168 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284173 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 284177 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 284181 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 284185 */     // MIs[2] Operand 1
     /* 284185 */     // No operand predicates
     /* 284185 */     // MIs[0] Operand 2
     /* 284185 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284196 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 284198 */     // (sext_inreg:{ *:[i64] } (vector_extract:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 284198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 284201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284203 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 284207 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 284210 */     GIR_RootConstrainSelectedInstOperands,
     /* 284211 */     // GIR_Coverage, 5703,
     /* 284211 */     GIR_EraseRootFromParent_Done,
     /* 284212 */   // Label 5511: @284212
     /* 284212 */   GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(284277), // Rule ID 5705 //
     /* 284217 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 284221 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 284225 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 284229 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 284233 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284238 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 284242 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 284246 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 284250 */     // MIs[2] Operand 1
     /* 284250 */     // No operand predicates
     /* 284250 */     // MIs[0] Operand 2
     /* 284250 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 284261 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 284263 */     // (sext_inreg:{ *:[i64] } (vector_extract:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 284263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 284266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284268 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 284272 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 284275 */     GIR_RootConstrainSelectedInstOperands,
     /* 284276 */     // GIR_Coverage, 5705,
     /* 284276 */     GIR_EraseRootFromParent_Done,
     /* 284277 */   // Label 5512: @284277
     /* 284277 */   GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(284312), // Rule ID 6580 //
     /* 284282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 284286 */     // MIs[0] Operand 2
     /* 284286 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
     /* 284297 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 31:{ *:[i64] })
     /* 284297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 284300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284302 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 284304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 284307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 284310 */     GIR_RootConstrainSelectedInstOperands,
     /* 284311 */     // GIR_Coverage, 6580,
     /* 284311 */     GIR_EraseRootFromParent_Done,
     /* 284312 */   // Label 5513: @284312
     /* 284312 */   GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(284347), // Rule ID 6581 //
     /* 284317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 284321 */     // MIs[0] Operand 2
     /* 284321 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 284332 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i16:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 15:{ *:[i64] })
     /* 284332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 284335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284337 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 284339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 284342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 284345 */     GIR_RootConstrainSelectedInstOperands,
     /* 284346 */     // GIR_Coverage, 6581,
     /* 284346 */     GIR_EraseRootFromParent_Done,
     /* 284347 */   // Label 5514: @284347
     /* 284347 */   GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(284382), // Rule ID 6582 //
     /* 284352 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 284356 */     // MIs[0] Operand 2
     /* 284356 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284367 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i8:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 7:{ *:[i64] })
     /* 284367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 284370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284372 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 284374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 284377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 284380 */     GIR_RootConstrainSelectedInstOperands,
     /* 284381 */     // GIR_Coverage, 6582,
     /* 284381 */     GIR_EraseRootFromParent_Done,
     /* 284382 */   // Label 5515: @284382
     /* 284382 */   GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(284417), // Rule ID 6583 //
     /* 284387 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 284391 */     // MIs[0] Operand 2
     /* 284391 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 284402 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i1:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 0:{ *:[i64] })
     /* 284402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 284405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 284407 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 284409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 284412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 284415 */     GIR_RootConstrainSelectedInstOperands,
     /* 284416 */     // GIR_Coverage, 6583,
     /* 284416 */     GIR_EraseRootFromParent_Done,
     /* 284417 */   // Label 5516: @284417
     /* 284417 */   GIM_Reject,
     /* 284418 */ // Label 5506: @284418
     /* 284418 */ GIM_Reject,
     /* 284419 */ // Label 5493: @284419
     /* 284419 */ GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(284627),
     /* 284424 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 284427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284431 */   GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(284496), // Rule ID 10625 //
     /* 284436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284439 */     // MIs[0] Operand 2
     /* 284439 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
     /* 284450 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i32:{ *:[Other] })  =>  (SXTW_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 284450 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284453 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 284457 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284462 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284465 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284467 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284470 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284474 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284479 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTW_ZPmZ_D_UNDEF),
     /* 284484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284486 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284489 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284492 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284494 */     GIR_RootConstrainSelectedInstOperands,
     /* 284495 */     // GIR_Coverage, 10625,
     /* 284495 */     GIR_EraseRootFromParent_Done,
     /* 284496 */   // Label 5518: @284496
     /* 284496 */   GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(284561), // Rule ID 10626 //
     /* 284501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284504 */     // MIs[0] Operand 2
     /* 284504 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 284515 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i16:{ *:[Other] })  =>  (SXTH_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 284515 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284518 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 284522 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284527 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284530 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284532 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284535 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284539 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284544 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTH_ZPmZ_D_UNDEF),
     /* 284549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284551 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284554 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284559 */     GIR_RootConstrainSelectedInstOperands,
     /* 284560 */     // GIR_Coverage, 10626,
     /* 284560 */     GIR_EraseRootFromParent_Done,
     /* 284561 */   // Label 5519: @284561
     /* 284561 */   GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(284626), // Rule ID 10627 //
     /* 284566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284569 */     // MIs[0] Operand 2
     /* 284569 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284580 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i8:{ *:[Other] })  =>  (SXTB_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 284580 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284583 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 284587 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284592 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284595 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284597 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284600 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284604 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284609 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_D_UNDEF),
     /* 284614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284616 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284619 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284622 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284624 */     GIR_RootConstrainSelectedInstOperands,
     /* 284625 */     // GIR_Coverage, 10627,
     /* 284625 */     GIR_EraseRootFromParent_Done,
     /* 284626 */   // Label 5520: @284626
     /* 284626 */   GIM_Reject,
     /* 284627 */ // Label 5517: @284627
     /* 284627 */ GIM_Reject,
     /* 284628 */ // Label 5494: @284628
     /* 284628 */ GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(284771),
     /* 284633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 284636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284640 */   GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(284705), // Rule ID 10628 //
     /* 284645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284648 */     // MIs[0] Operand 2
     /* 284648 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 284659 */     // (sext_inreg:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, nxv4i16:{ *:[Other] })  =>  (SXTH_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv4i32] }:$Zs)
     /* 284659 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284662 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 284666 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284671 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284674 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284676 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284679 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284683 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284688 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTH_ZPmZ_S_UNDEF),
     /* 284693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284695 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284698 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284701 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284703 */     GIR_RootConstrainSelectedInstOperands,
     /* 284704 */     // GIR_Coverage, 10628,
     /* 284704 */     GIR_EraseRootFromParent_Done,
     /* 284705 */   // Label 5522: @284705
     /* 284705 */   GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(284770), // Rule ID 10629 //
     /* 284710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284713 */     // MIs[0] Operand 2
     /* 284713 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284724 */     // (sext_inreg:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, nxv4i8:{ *:[Other] })  =>  (SXTB_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv4i32] }:$Zs)
     /* 284724 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284727 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 284731 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284736 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284739 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284741 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284744 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284748 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284753 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_S_UNDEF),
     /* 284758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284760 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284763 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284766 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284768 */     GIR_RootConstrainSelectedInstOperands,
     /* 284769 */     // GIR_Coverage, 10629,
     /* 284769 */     GIR_EraseRootFromParent_Done,
     /* 284770 */   // Label 5523: @284770
     /* 284770 */   GIM_Reject,
     /* 284771 */ // Label 5521: @284771
     /* 284771 */ GIM_Reject,
     /* 284772 */ // Label 5495: @284772
     /* 284772 */ GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(284844), // Rule ID 10630 //
     /* 284777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 284780 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 284783 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284787 */   // MIs[0] Operand 2
     /* 284787 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 284798 */   // (sext_inreg:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Zs, nxv8i8:{ *:[Other] })  =>  (SXTB_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv8i16] }:$Zs)
     /* 284798 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 284801 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 284805 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284810 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 284813 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 284815 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 284818 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284822 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284827 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 284829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_H_UNDEF),
     /* 284832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 284834 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 284837 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 284840 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 284842 */   GIR_RootConstrainSelectedInstOperands,
     /* 284843 */   // GIR_Coverage, 10630,
     /* 284843 */   GIR_EraseRootFromParent_Done,
     /* 284844 */ // Label 5524: @284844
     /* 284844 */ GIM_Reject,
     /* 284845 */ // Label 5496: @284845
     /* 284845 */ GIM_Reject,
     /* 284846 */ // Label 45: @284846
     /* 284846 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5529*/ GIMT_Encode4(287624),
     /* 284857 */ /*GILLT_s32*//*Label 5525*/ GIMT_Encode4(284893), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 284873 */ /*GILLT_v2s64*//*Label 5526*/ GIMT_Encode4(286694), GIMT_Encode4(0),
     /* 284881 */ /*GILLT_v4s32*//*Label 5527*/ GIMT_Encode4(287004), GIMT_Encode4(0),
     /* 284889 */ /*GILLT_v8s16*//*Label 5528*/ GIMT_Encode4(287314),
     /* 284893 */ // Label 5525: @284893
     /* 284893 */ GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(285043), // Rule ID 13432 //
     /* 284898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 284901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 284905 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 284909 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 284913 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 284916 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 284921 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 284925 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 284930 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 284932 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 737:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 284932 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 284935 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 284939 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284944 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 284948 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 284950 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 284953 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 284957 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284962 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 284964 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 284967 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 284971 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 284976 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 284979 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 284982 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 284985 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284990 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 284995 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 285000 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285003 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285007 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285012 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285019 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285024 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285032 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285034 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285037 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285042 */   // GIR_Coverage, 13432,
     /* 285042 */   GIR_EraseRootFromParent_Done,
     /* 285043 */ // Label 5530: @285043
     /* 285043 */ GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(285193), // Rule ID 13434 //
     /* 285048 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 285051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285055 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285059 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285063 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285066 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 285071 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 285075 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285080 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285082 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 737:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285082 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 285085 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 285089 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285094 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285098 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285100 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285103 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285107 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285112 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285114 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285117 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285121 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285126 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285129 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285132 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 285135 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285140 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285145 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 285150 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285153 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285157 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285162 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285169 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285174 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285179 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285182 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285184 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285187 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285192 */   // GIR_Coverage, 13434,
     /* 285192 */   GIR_EraseRootFromParent_Done,
     /* 285193 */ // Label 5531: @285193
     /* 285193 */ GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(285343), // Rule ID 13436 //
     /* 285198 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 285201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285205 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285209 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285213 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285216 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 285221 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 285225 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 285230 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285232 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 737:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285232 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 285235 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 285239 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285244 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285248 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285250 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285253 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285257 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285262 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285264 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285267 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285271 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285276 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285279 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285282 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 285285 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285290 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285295 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 285300 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285303 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285307 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285312 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285319 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285324 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285334 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285337 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285342 */   // GIR_Coverage, 13436,
     /* 285342 */   GIR_EraseRootFromParent_Done,
     /* 285343 */ // Label 5532: @285343
     /* 285343 */ GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(285493), // Rule ID 13438 //
     /* 285348 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 285351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285355 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285359 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285363 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285366 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 285371 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 285375 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285380 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285382 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 737:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285382 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 285385 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 285389 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285394 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285398 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285400 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285403 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285407 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285412 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285414 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285417 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285421 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285426 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285429 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285432 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 285435 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285440 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285445 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 285450 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285453 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285457 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285462 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285469 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285474 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285482 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285484 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285487 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285492 */   // GIR_Coverage, 13438,
     /* 285492 */   GIR_EraseRootFromParent_Done,
     /* 285493 */ // Label 5533: @285493
     /* 285493 */ GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(285643), // Rule ID 13465 //
     /* 285498 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 285501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285505 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285509 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285513 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285516 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 285521 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 285525 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 285530 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285532 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 743:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285532 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 285535 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 285539 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285544 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285548 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285550 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285553 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285557 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285562 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285564 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285567 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285571 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285576 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285579 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285582 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 285585 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285590 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285595 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 285600 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285603 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285607 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285612 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285619 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285624 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285629 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285632 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285634 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285637 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285642 */   // GIR_Coverage, 13465,
     /* 285642 */   GIR_EraseRootFromParent_Done,
     /* 285643 */ // Label 5534: @285643
     /* 285643 */ GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(285793), // Rule ID 13467 //
     /* 285648 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 285651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285655 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285659 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285663 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285666 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 285671 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 285675 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285680 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285682 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 743:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285682 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 285685 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 285689 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285694 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285698 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285700 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285703 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285707 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285712 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285714 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285717 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285721 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285726 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285729 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285732 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 285735 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285740 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285745 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 285750 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285753 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285757 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285762 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285769 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285774 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285784 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285787 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285792 */   // GIR_Coverage, 13467,
     /* 285792 */   GIR_EraseRootFromParent_Done,
     /* 285793 */ // Label 5535: @285793
     /* 285793 */ GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(285943), // Rule ID 13469 //
     /* 285798 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 285801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285805 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285809 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285813 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285816 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 285821 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 285825 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 285830 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285832 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 743:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285832 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 285835 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 285839 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285844 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285848 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 285850 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 285853 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 285857 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285862 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 285864 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 285867 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 285871 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285876 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 285879 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 285882 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 285885 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285890 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285895 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 285900 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 285903 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285907 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285912 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 285919 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 285924 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 285932 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 285934 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 285937 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285942 */   // GIR_Coverage, 13469,
     /* 285942 */   GIR_EraseRootFromParent_Done,
     /* 285943 */ // Label 5536: @285943
     /* 285943 */ GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(286093), // Rule ID 13471 //
     /* 285948 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 285951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 285955 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 285959 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 285963 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 285966 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 285971 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 285975 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 285980 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 285982 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 743:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 285982 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 285985 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 285989 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 285994 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 285998 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 286000 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 286003 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 286007 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286012 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 286014 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 286017 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 286021 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286026 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 286029 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 286032 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 286035 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286040 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286045 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 286050 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 286053 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286057 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286062 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 286069 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 286074 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286082 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 286084 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 286087 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286092 */   // GIR_Coverage, 13471,
     /* 286092 */   GIR_EraseRootFromParent_Done,
     /* 286093 */ // Label 5537: @286093
     /* 286093 */ GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(286243), // Rule ID 13475 //
     /* 286098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 286101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286105 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286109 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286113 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 286116 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 286121 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 286125 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286130 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286132 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 746:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 286132 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 286135 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 286139 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286144 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286148 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 286150 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 286153 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 286157 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286162 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 286164 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 286167 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 286171 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286176 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 286179 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 286182 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 286185 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286190 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286195 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 286200 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 286203 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286207 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286212 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 286219 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 286224 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 286234 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 286237 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286242 */   // GIR_Coverage, 13475,
     /* 286242 */   GIR_EraseRootFromParent_Done,
     /* 286243 */ // Label 5538: @286243
     /* 286243 */ GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(286393), // Rule ID 13477 //
     /* 286248 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 286251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286255 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286259 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286263 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 286266 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 286271 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 286275 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286280 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286282 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 746:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 286282 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 286285 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 286289 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286294 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286298 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 286300 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 286303 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 286307 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286312 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 286314 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 286317 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 286321 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286326 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 286329 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 286332 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 286335 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286340 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286345 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 286350 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 286353 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286357 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286362 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 286369 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 286374 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286382 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 286384 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 286387 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286392 */   // GIR_Coverage, 13477,
     /* 286392 */   GIR_EraseRootFromParent_Done,
     /* 286393 */ // Label 5539: @286393
     /* 286393 */ GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(286543), // Rule ID 13479 //
     /* 286398 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 286401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286405 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286409 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286413 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 286416 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 286421 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 286425 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286430 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286432 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 746:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 286432 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 286435 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 286439 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286444 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286448 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 286450 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 286453 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 286457 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286462 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 286464 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 286467 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 286471 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286476 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 286479 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 286482 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 286485 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286490 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286495 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 286500 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 286503 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286507 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286512 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 286519 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 286524 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 286534 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 286537 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286542 */   // GIR_Coverage, 13479,
     /* 286542 */   GIR_EraseRootFromParent_Done,
     /* 286543 */ // Label 5540: @286543
     /* 286543 */ GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(286693), // Rule ID 13481 //
     /* 286548 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 286551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286555 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286559 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286563 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 286566 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 286571 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 286575 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286580 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286582 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 746:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 286582 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 286585 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 286589 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286594 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286598 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 286600 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 286603 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 286607 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286612 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 286614 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 286617 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 286621 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286626 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 286629 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 286632 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 286635 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286640 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286645 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 286650 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 286653 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286657 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 286662 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 286669 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 286674 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 286682 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 286684 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 286687 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 286692 */   // GIR_Coverage, 13481,
     /* 286692 */   GIR_EraseRootFromParent_Done,
     /* 286693 */ // Label 5541: @286693
     /* 286693 */ GIM_Reject,
     /* 286694 */ // Label 5526: @286694
     /* 286694 */ GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(287003),
     /* 286699 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 286702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 286706 */   GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(286771), // Rule ID 706 //
     /* 286711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 286714 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286718 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286722 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 286725 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 286730 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 286734 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 286738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286740 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 286747 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 286754 */     // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 286754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i32_v2i64),
     /* 286757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 286764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 286769 */     GIR_RootConstrainSelectedInstOperands,
     /* 286770 */     // GIR_Coverage, 706,
     /* 286770 */     GIR_EraseRootFromParent_Done,
     /* 286771 */   // Label 5543: @286771
     /* 286771 */   GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(286836), // Rule ID 1715 //
     /* 286776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 286779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286787 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 286790 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 286795 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 286799 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 286803 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286805 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 286812 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 286819 */     // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 286819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i32_v2i64),
     /* 286822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 286829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 286834 */     GIR_RootConstrainSelectedInstOperands,
     /* 286835 */     // GIR_Coverage, 1715,
     /* 286835 */     GIR_EraseRootFromParent_Done,
     /* 286836 */   // Label 5544: @286836
     /* 286836 */   GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(286895), // Rule ID 704 //
     /* 286841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 286844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286852 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 286855 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 286860 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 286864 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 286868 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286878 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286880 */     // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 734:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 286880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv2i32_v2i64),
     /* 286883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286885 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 286893 */     GIR_RootConstrainSelectedInstOperands,
     /* 286894 */     // GIR_Coverage, 704,
     /* 286894 */     GIR_EraseRootFromParent_Done,
     /* 286895 */   // Label 5545: @286895
     /* 286895 */   GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(286954), // Rule ID 1713 //
     /* 286900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 286903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 286907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 286911 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 286914 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 286919 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 286923 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 286927 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286932 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286937 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 286939 */     // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 669:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 286939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv2i32_v2i64),
     /* 286942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 286948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 286952 */     GIR_RootConstrainSelectedInstOperands,
     /* 286953 */     // GIR_Coverage, 1713,
     /* 286953 */     GIR_EraseRootFromParent_Done,
     /* 286954 */   // Label 5546: @286954
     /* 286954 */   GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(286981), // Rule ID 6440 //
     /* 286959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 286966 */     // (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 286966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
     /* 286969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 286976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 286979 */     GIR_RootConstrainSelectedInstOperands,
     /* 286980 */     // GIR_Coverage, 6440,
     /* 286980 */     GIR_EraseRootFromParent_Done,
     /* 286981 */   // Label 5547: @286981
     /* 286981 */   GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(287002), // Rule ID 6431 //
     /* 286986 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 286990 */     // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 286990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 286993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 286995 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 286997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 287000 */     GIR_RootConstrainSelectedInstOperands,
     /* 287001 */     // GIR_Coverage, 6431,
     /* 287001 */     GIR_EraseRootFromParent_Done,
     /* 287002 */   // Label 5548: @287002
     /* 287002 */   GIM_Reject,
     /* 287003 */ // Label 5542: @287003
     /* 287003 */ GIM_Reject,
     /* 287004 */ // Label 5527: @287004
     /* 287004 */ GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(287313),
     /* 287009 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 287012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 287016 */   GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(287081), // Rule ID 702 //
     /* 287021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287032 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287035 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 287040 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 287044 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 287048 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287050 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 287057 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 287064 */     // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 287064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i16_v4i32),
     /* 287067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 287079 */     GIR_RootConstrainSelectedInstOperands,
     /* 287080 */     // GIR_Coverage, 702,
     /* 287080 */     GIR_EraseRootFromParent_Done,
     /* 287081 */   // Label 5550: @287081
     /* 287081 */   GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(287146), // Rule ID 1711 //
     /* 287086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287093 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287097 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287100 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 287105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 287109 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 287113 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287115 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 287122 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 287129 */     // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 287129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i16_v4i32),
     /* 287132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 287144 */     GIR_RootConstrainSelectedInstOperands,
     /* 287145 */     // GIR_Coverage, 1711,
     /* 287145 */     GIR_EraseRootFromParent_Done,
     /* 287146 */   // Label 5551: @287146
     /* 287146 */   GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(287205), // Rule ID 700 //
     /* 287151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287154 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287158 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287162 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287165 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 287170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 287174 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 287178 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287183 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287188 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287190 */     // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 734:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 287190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i16_v4i32),
     /* 287193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 287199 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 287203 */     GIR_RootConstrainSelectedInstOperands,
     /* 287204 */     // GIR_Coverage, 700,
     /* 287204 */     GIR_EraseRootFromParent_Done,
     /* 287205 */   // Label 5552: @287205
     /* 287205 */   GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(287264), // Rule ID 1709 //
     /* 287210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287213 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287217 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287221 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287224 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 287229 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 287233 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 287237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287242 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287247 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287249 */     // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 669:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 287249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i16_v4i32),
     /* 287252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 287258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 287262 */     GIR_RootConstrainSelectedInstOperands,
     /* 287263 */     // GIR_Coverage, 1709,
     /* 287263 */     GIR_EraseRootFromParent_Done,
     /* 287264 */   // Label 5553: @287264
     /* 287264 */   GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(287291), // Rule ID 6437 //
     /* 287269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 287276 */     // (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 287276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
     /* 287279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 287289 */     GIR_RootConstrainSelectedInstOperands,
     /* 287290 */     // GIR_Coverage, 6437,
     /* 287290 */     GIR_EraseRootFromParent_Done,
     /* 287291 */   // Label 5554: @287291
     /* 287291 */   GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(287312), // Rule ID 6428 //
     /* 287296 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287300 */     // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 287300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 287303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287305 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 287310 */     GIR_RootConstrainSelectedInstOperands,
     /* 287311 */     // GIR_Coverage, 6428,
     /* 287311 */     GIR_EraseRootFromParent_Done,
     /* 287312 */   // Label 5555: @287312
     /* 287312 */   GIM_Reject,
     /* 287313 */ // Label 5549: @287313
     /* 287313 */ GIM_Reject,
     /* 287314 */ // Label 5528: @287314
     /* 287314 */ GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(287623),
     /* 287319 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 287322 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 287326 */   GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(287391), // Rule ID 698 //
     /* 287331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287334 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287338 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287342 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287345 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 287350 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 287354 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 287358 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287360 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 287367 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 287374 */     // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 287374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv16i8_v8i16),
     /* 287377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 287389 */     GIR_RootConstrainSelectedInstOperands,
     /* 287390 */     // GIR_Coverage, 698,
     /* 287390 */     GIR_EraseRootFromParent_Done,
     /* 287391 */   // Label 5557: @287391
     /* 287391 */   GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(287456), // Rule ID 1707 //
     /* 287396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287399 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287403 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287407 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287410 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 287415 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 287419 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 287423 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287425 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 287432 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 287439 */     // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 287439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv16i8_v8i16),
     /* 287442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 287454 */     GIR_RootConstrainSelectedInstOperands,
     /* 287455 */     // GIR_Coverage, 1707,
     /* 287455 */     GIR_EraseRootFromParent_Done,
     /* 287456 */   // Label 5558: @287456
     /* 287456 */   GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(287515), // Rule ID 696 //
     /* 287461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287472 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287475 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
     /* 287480 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 287484 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 287488 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287498 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287500 */     // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 734:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 287500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i8_v8i16),
     /* 287503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 287509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 287513 */     GIR_RootConstrainSelectedInstOperands,
     /* 287514 */     // GIR_Coverage, 696,
     /* 287514 */     GIR_EraseRootFromParent_Done,
     /* 287515 */   // Label 5559: @287515
     /* 287515 */   GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(287574), // Rule ID 1705 //
     /* 287520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 287523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 287527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 287531 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 287534 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
     /* 287539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 287543 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 287547 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287552 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287557 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287559 */     // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 669:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 287559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i8_v8i16),
     /* 287562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287564 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 287568 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 287572 */     GIR_RootConstrainSelectedInstOperands,
     /* 287573 */     // GIR_Coverage, 1705,
     /* 287573 */     GIR_EraseRootFromParent_Done,
     /* 287574 */   // Label 5560: @287574
     /* 287574 */   GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(287601), // Rule ID 6434 //
     /* 287579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 287586 */     // (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 287586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
     /* 287589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 287596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 287599 */     GIR_RootConstrainSelectedInstOperands,
     /* 287600 */     // GIR_Coverage, 6434,
     /* 287600 */     GIR_EraseRootFromParent_Done,
     /* 287601 */   // Label 5561: @287601
     /* 287601 */   GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(287622), // Rule ID 6425 //
     /* 287606 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 287610 */     // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 287610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 287613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287615 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 287620 */     GIR_RootConstrainSelectedInstOperands,
     /* 287621 */     // GIR_Coverage, 6425,
     /* 287621 */     GIR_EraseRootFromParent_Done,
     /* 287622 */   // Label 5562: @287622
     /* 287622 */   GIM_Reject,
     /* 287623 */ // Label 5556: @287623
     /* 287623 */ GIM_Reject,
     /* 287624 */ // Label 5529: @287624
     /* 287624 */ GIM_Reject,
     /* 287625 */ // Label 46: @287625
     /* 287625 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5568*/ GIMT_Encode4(288449),
     /* 287636 */ /*GILLT_s32*//*Label 5563*/ GIMT_Encode4(287672),
     /* 287640 */ /*GILLT_s64*//*Label 5564*/ GIMT_Encode4(287849), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 287652 */ /*GILLT_v2s64*//*Label 5565*/ GIMT_Encode4(288022), GIMT_Encode4(0),
     /* 287660 */ /*GILLT_v4s32*//*Label 5566*/ GIMT_Encode4(288167), GIMT_Encode4(0),
     /* 287668 */ /*GILLT_v8s16*//*Label 5567*/ GIMT_Encode4(288308),
     /* 287672 */ // Label 5563: @287672
     /* 287672 */ GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(287848),
     /* 287677 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 287680 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 287683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287687 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287691 */   GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(287728), // Rule ID 3968 //
     /* 287696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 287700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 287704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 287708 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287713 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287715 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 287715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 287718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287720 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 287726 */     GIR_RootConstrainSelectedInstOperands,
     /* 287727 */     // GIR_Coverage, 3968,
     /* 287727 */     GIR_EraseRootFromParent_Done,
     /* 287728 */   // Label 5570: @287728
     /* 287728 */   GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(287765), // Rule ID 3969 //
     /* 287733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 287737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 287741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 287745 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287752 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 287752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 287755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287757 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 287763 */     GIR_RootConstrainSelectedInstOperands,
     /* 287764 */     // GIR_Coverage, 3969,
     /* 287764 */     GIR_EraseRootFromParent_Done,
     /* 287765 */   // Label 5571: @287765
     /* 287765 */   GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(287802), // Rule ID 3967 //
     /* 287770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 287774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 287778 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 287782 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287787 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287789 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 287789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 287792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287794 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 287800 */     GIR_RootConstrainSelectedInstOperands,
     /* 287801 */     // GIR_Coverage, 3967,
     /* 287801 */     GIR_EraseRootFromParent_Done,
     /* 287802 */   // Label 5572: @287802
     /* 287802 */   GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(287847), // Rule ID 3966 //
     /* 287807 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 287807 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 287810 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 287814 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 287819 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 287825 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287830 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 287835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 287838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287840 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287842 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 287845 */     GIR_RootConstrainSelectedInstOperands,
     /* 287846 */     // GIR_Coverage, 3966,
     /* 287846 */     GIR_EraseRootFromParent_Done,
     /* 287847 */   // Label 5573: @287847
     /* 287847 */   GIM_Reject,
     /* 287848 */ // Label 5569: @287848
     /* 287848 */ GIM_Reject,
     /* 287849 */ // Label 5564: @287849
     /* 287849 */ GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(288021),
     /* 287854 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 287857 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 287860 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 287864 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 287868 */   GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(287936), // Rule ID 3970 //
     /* 287873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 287877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 287881 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 287885 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287890 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287892 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 287892 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 287895 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 287899 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 287904 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 287907 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 287911 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 287914 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 287919 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 287927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287929 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287931 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 287934 */     GIR_RootConstrainSelectedInstOperands,
     /* 287935 */     // GIR_Coverage, 3970,
     /* 287935 */     GIR_EraseRootFromParent_Done,
     /* 287936 */   // Label 5575: @287936
     /* 287936 */   GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(288004), // Rule ID 3971 //
     /* 287941 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 287945 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 287949 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 287953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287958 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 287960 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 287960 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 287963 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 287967 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 287972 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 287975 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 287979 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 287982 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 287987 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 287992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 287995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 287997 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 287999 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 288002 */     GIR_RootConstrainSelectedInstOperands,
     /* 288003 */     // GIR_Coverage, 3971,
     /* 288003 */     GIR_EraseRootFromParent_Done,
     /* 288004 */   // Label 5576: @288004
     /* 288004 */   GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(288020), // Rule ID 120 //
     /* 288009 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288013 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 288013 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 288018 */     GIR_RootConstrainSelectedInstOperands,
     /* 288019 */     // GIR_Coverage, 120,
     /* 288019 */     GIR_Done,
     /* 288020 */   // Label 5577: @288020
     /* 288020 */   GIM_Reject,
     /* 288021 */ // Label 5574: @288021
     /* 288021 */ GIM_Reject,
     /* 288022 */ // Label 5565: @288022
     /* 288022 */ GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(288166),
     /* 288027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 288030 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 288033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 288037 */   GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(288101), // Rule ID 6423 //
     /* 288042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 288050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 288054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288059 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288063 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288067 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 288071 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288075 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288079 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 288083 */     // MIs[3] Operand 1
     /* 288083 */     // No operand predicates
     /* 288083 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288085 */     // (shl:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), (AArch64dup:{ *:[v2i64] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))  =>  (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))
     /* 288085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 288088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288090 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288094 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // size
     /* 288099 */     GIR_RootConstrainSelectedInstOperands,
     /* 288100 */     // GIR_Coverage, 6423,
     /* 288100 */     GIR_EraseRootFromParent_Done,
     /* 288101 */   // Label 5579: @288101
     /* 288101 */   GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(288165), // Rule ID 6420 //
     /* 288106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 288114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 288118 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288127 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288131 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 288135 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288139 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288143 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 288147 */     // MIs[3] Operand 1
     /* 288147 */     // No operand predicates
     /* 288147 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288149 */     // (shl:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), (AArch64dup:{ *:[v2i64] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))
     /* 288149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 288152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288154 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288158 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // size
     /* 288163 */     GIR_RootConstrainSelectedInstOperands,
     /* 288164 */     // GIR_Coverage, 6420,
     /* 288164 */     GIR_EraseRootFromParent_Done,
     /* 288165 */   // Label 5580: @288165
     /* 288165 */   GIM_Reject,
     /* 288166 */ // Label 5578: @288166
     /* 288166 */ GIM_Reject,
     /* 288167 */ // Label 5566: @288167
     /* 288167 */ GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(288307),
     /* 288172 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 288175 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 288178 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 288182 */   GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(288244), // Rule ID 6422 //
     /* 288187 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288191 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 288195 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 288199 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288204 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288208 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288212 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 288216 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288220 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288224 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 288228 */     // MIs[3] Operand 1
     /* 288228 */     // No operand predicates
     /* 288228 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288230 */     // (shl:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), (AArch64dup:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size))  =>  (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size)
     /* 288230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 288233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288239 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 288242 */     GIR_RootConstrainSelectedInstOperands,
     /* 288243 */     // GIR_Coverage, 6422,
     /* 288243 */     GIR_EraseRootFromParent_Done,
     /* 288244 */   // Label 5582: @288244
     /* 288244 */   GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(288306), // Rule ID 6419 //
     /* 288249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 288257 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 288261 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288266 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288270 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288274 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 288278 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288282 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288286 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 288290 */     // MIs[3] Operand 1
     /* 288290 */     // No operand predicates
     /* 288290 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288292 */     // (shl:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), (AArch64dup:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size))  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size)
     /* 288292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 288295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288301 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 288304 */     GIR_RootConstrainSelectedInstOperands,
     /* 288305 */     // GIR_Coverage, 6419,
     /* 288305 */     GIR_EraseRootFromParent_Done,
     /* 288306 */   // Label 5583: @288306
     /* 288306 */   GIM_Reject,
     /* 288307 */ // Label 5581: @288307
     /* 288307 */ GIM_Reject,
     /* 288308 */ // Label 5567: @288308
     /* 288308 */ GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(288448),
     /* 288313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 288316 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 288319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 288323 */   GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(288385), // Rule ID 6421 //
     /* 288328 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288332 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 288336 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 288340 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288345 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288349 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288353 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 288357 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288361 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288365 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_7),
     /* 288369 */     // MIs[3] Operand 1
     /* 288369 */     // No operand predicates
     /* 288369 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288371 */     // (shl:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), (AArch64dup:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size))  =>  (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size)
     /* 288371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 288374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288380 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 288383 */     GIR_RootConstrainSelectedInstOperands,
     /* 288384 */     // GIR_Coverage, 6421,
     /* 288384 */     GIR_EraseRootFromParent_Done,
     /* 288385 */   // Label 5585: @288385
     /* 288385 */   GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(288447), // Rule ID 6418 //
     /* 288390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 288398 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 288402 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 288407 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 288411 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 288415 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 288419 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 288423 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288427 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_7),
     /* 288431 */     // MIs[3] Operand 1
     /* 288431 */     // No operand predicates
     /* 288431 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 288433 */     // (shl:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), (AArch64dup:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size))  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size)
     /* 288433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 288436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288442 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 288445 */     GIR_RootConstrainSelectedInstOperands,
     /* 288446 */     // GIR_Coverage, 6418,
     /* 288446 */     GIR_EraseRootFromParent_Done,
     /* 288447 */   // Label 5586: @288447
     /* 288447 */   GIM_Reject,
     /* 288448 */ // Label 5584: @288448
     /* 288448 */ GIM_Reject,
     /* 288449 */ // Label 5568: @288449
     /* 288449 */ GIM_Reject,
     /* 288450 */ // Label 47: @288450
     /* 288450 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5589*/ GIMT_Encode4(288993),
     /* 288461 */ /*GILLT_s32*//*Label 5587*/ GIMT_Encode4(288469),
     /* 288465 */ /*GILLT_s64*//*Label 5588*/ GIMT_Encode4(288735),
     /* 288469 */ // Label 5587: @288469
     /* 288469 */ GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(288734),
     /* 288474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 288477 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 288480 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288484 */   GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(288523), // Rule ID 4046 //
     /* 288489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 288497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288501 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top16Zero),
     /* 288506 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
     /* 288510 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288512 */     // (srl:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_top16Zero>>:$Rn), 16:{ *:[i64] })  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 288512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 288515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288517 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 288521 */     GIR_RootConstrainSelectedInstOperands,
     /* 288522 */     // GIR_Coverage, 4046,
     /* 288522 */     GIR_EraseRootFromParent_Done,
     /* 288523 */   // Label 5591: @288523
     /* 288523 */   GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(288561), // Rule ID 4057 //
     /* 288528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288540 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 288544 */     // MIs[1] Operand 1
     /* 288544 */     // No operand predicates
     /* 288544 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288546 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 288546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMWri),
     /* 288549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288551 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288553 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 288556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 288559 */     GIR_RootConstrainSelectedInstOperands,
     /* 288560 */     // GIR_Coverage, 4057,
     /* 288560 */     GIR_EraseRootFromParent_Done,
     /* 288561 */   // Label 5592: @288561
     /* 288561 */   GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(288602), // Rule ID 3974 //
     /* 288566 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288574 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 288578 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288582 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288587 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288589 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 288589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 288592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288594 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288596 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288600 */     GIR_RootConstrainSelectedInstOperands,
     /* 288601 */     // GIR_Coverage, 3974,
     /* 288601 */     GIR_EraseRootFromParent_Done,
     /* 288602 */   // Label 5593: @288602
     /* 288602 */   GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(288643), // Rule ID 3975 //
     /* 288607 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288611 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288615 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 288619 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288623 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288628 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288630 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 288630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 288633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288635 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288641 */     GIR_RootConstrainSelectedInstOperands,
     /* 288642 */     // GIR_Coverage, 3975,
     /* 288642 */     GIR_EraseRootFromParent_Done,
     /* 288643 */   // Label 5594: @288643
     /* 288643 */   GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(288684), // Rule ID 3973 //
     /* 288648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 288660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288664 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288669 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288671 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 288671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 288674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288676 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288682 */     GIR_RootConstrainSelectedInstOperands,
     /* 288683 */     // GIR_Coverage, 3973,
     /* 288683 */     GIR_EraseRootFromParent_Done,
     /* 288684 */   // Label 5595: @288684
     /* 288684 */   GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(288733), // Rule ID 3972 //
     /* 288689 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288693 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 288693 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 288696 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 288700 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 288705 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 288711 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288716 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 288724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288726 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288728 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 288731 */     GIR_RootConstrainSelectedInstOperands,
     /* 288732 */     // GIR_Coverage, 3972,
     /* 288732 */     GIR_EraseRootFromParent_Done,
     /* 288733 */   // Label 5596: @288733
     /* 288733 */   GIM_Reject,
     /* 288734 */ // Label 5590: @288734
     /* 288734 */ GIM_Reject,
     /* 288735 */ // Label 5588: @288735
     /* 288735 */ GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(288992),
     /* 288740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 288743 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 288746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288750 */   GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(288789), // Rule ID 4047 //
     /* 288755 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 288759 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 288763 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 288767 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /* 288772 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32,
     /* 288776 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288778 */     // (srl:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn), 32:{ *:[i64] })  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 288778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 288781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288783 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 288787 */     GIR_RootConstrainSelectedInstOperands,
     /* 288788 */     // GIR_Coverage, 4047,
     /* 288788 */     GIR_EraseRootFromParent_Done,
     /* 288789 */   // Label 5598: @288789
     /* 288789 */   GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(288827), // Rule ID 4058 //
     /* 288794 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288802 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 288806 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 288810 */     // MIs[1] Operand 1
     /* 288810 */     // No operand predicates
     /* 288810 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288812 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
     /* 288812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMXri),
     /* 288815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288817 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288819 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 288822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
     /* 288825 */     GIR_RootConstrainSelectedInstOperands,
     /* 288826 */     // GIR_Coverage, 4058,
     /* 288826 */     GIR_EraseRootFromParent_Done,
     /* 288827 */   // Label 5599: @288827
     /* 288827 */   GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(288899), // Rule ID 3976 //
     /* 288832 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 288844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288848 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288853 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288855 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 288855 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 288858 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 288862 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 288867 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 288870 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288874 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 288877 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 288882 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 288890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288892 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 288897 */     GIR_RootConstrainSelectedInstOperands,
     /* 288898 */     // GIR_Coverage, 3976,
     /* 288898 */     GIR_EraseRootFromParent_Done,
     /* 288899 */   // Label 5600: @288899
     /* 288899 */   GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(288971), // Rule ID 3977 //
     /* 288904 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 288912 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 288916 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 288920 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288925 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 288927 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 288927 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 288930 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 288934 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 288939 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 288942 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 288946 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 288949 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 288954 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 288959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 288962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 288964 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 288966 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 288969 */     GIR_RootConstrainSelectedInstOperands,
     /* 288970 */     // GIR_Coverage, 3977,
     /* 288970 */     GIR_EraseRootFromParent_Done,
     /* 288971 */   // Label 5601: @288971
     /* 288971 */   GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(288991), // Rule ID 121 //
     /* 288976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 288984 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 288984 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 288989 */     GIR_RootConstrainSelectedInstOperands,
     /* 288990 */     // GIR_Coverage, 121,
     /* 288990 */     GIR_Done,
     /* 288991 */   // Label 5602: @288991
     /* 288991 */   GIM_Reject,
     /* 288992 */ // Label 5597: @288992
     /* 288992 */ GIM_Reject,
     /* 288993 */ // Label 5589: @288993
     /* 288993 */ GIM_Reject,
     /* 288994 */ // Label 48: @288994
     /* 288994 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5605*/ GIMT_Encode4(289818),
     /* 289005 */ /*GILLT_s32*//*Label 5603*/ GIMT_Encode4(289013),
     /* 289009 */ /*GILLT_s64*//*Label 5604*/ GIMT_Encode4(289368),
     /* 289013 */ // Label 5603: @289013
     /* 289013 */ GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(289367),
     /* 289018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289021 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 289024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289028 */   GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(289092), // Rule ID 6593 //
     /* 289033 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289037 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 289041 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289045 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289050 */     // MIs[1] Operand 2
     /* 289050 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 289061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 289065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289069 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 289073 */     // MIs[2] Operand 1
     /* 289073 */     // No operand predicates
     /* 289073 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 289075 */     // (sra:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i8:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm, 7:{ *:[i64] })
     /* 289075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 289078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289080 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 289084 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 289087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 289090 */     GIR_RootConstrainSelectedInstOperands,
     /* 289091 */     // GIR_Coverage, 6593,
     /* 289091 */     GIR_EraseRootFromParent_Done,
     /* 289092 */   // Label 5607: @289092
     /* 289092 */   GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(289156), // Rule ID 6595 //
     /* 289097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 289105 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289109 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289114 */     // MIs[1] Operand 2
     /* 289114 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 289125 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 289129 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289133 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
     /* 289137 */     // MIs[2] Operand 1
     /* 289137 */     // No operand predicates
     /* 289137 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 289139 */     // (sra:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm, 15:{ *:[i64] })
     /* 289139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 289142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 289148 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 289151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 289154 */     GIR_RootConstrainSelectedInstOperands,
     /* 289155 */     // GIR_Coverage, 6595,
     /* 289155 */     GIR_EraseRootFromParent_Done,
     /* 289156 */   // Label 5608: @289156
     /* 289156 */   GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(289194), // Rule ID 4055 //
     /* 289161 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289173 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 289177 */     // MIs[1] Operand 1
     /* 289177 */     // No operand predicates
     /* 289177 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289179 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 289179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 289182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289184 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289186 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 289189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 289192 */     GIR_RootConstrainSelectedInstOperands,
     /* 289193 */     // GIR_Coverage, 4055,
     /* 289193 */     GIR_EraseRootFromParent_Done,
     /* 289194 */   // Label 5609: @289194
     /* 289194 */   GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(289235), // Rule ID 2442 //
     /* 289199 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 289211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289220 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289222 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 289222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 289225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289227 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289229 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 289233 */     GIR_RootConstrainSelectedInstOperands,
     /* 289234 */     // GIR_Coverage, 2442,
     /* 289234 */     GIR_EraseRootFromParent_Done,
     /* 289235 */   // Label 5610: @289235
     /* 289235 */   GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(289276), // Rule ID 2443 //
     /* 289240 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289244 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289248 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 289252 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289256 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289261 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289263 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 289263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 289266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289268 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 289274 */     GIR_RootConstrainSelectedInstOperands,
     /* 289275 */     // GIR_Coverage, 2443,
     /* 289275 */     GIR_EraseRootFromParent_Done,
     /* 289276 */   // Label 5611: @289276
     /* 289276 */   GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(289317), // Rule ID 2441 //
     /* 289281 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 289293 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289297 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289302 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289304 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 289304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 289307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289309 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289311 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 289315 */     GIR_RootConstrainSelectedInstOperands,
     /* 289316 */     // GIR_Coverage, 2441,
     /* 289316 */     GIR_EraseRootFromParent_Done,
     /* 289317 */   // Label 5612: @289317
     /* 289317 */   GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(289366), // Rule ID 2440 //
     /* 289322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289326 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 289326 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289329 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 289333 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289338 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 289344 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289349 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 289357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289359 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289361 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289364 */     GIR_RootConstrainSelectedInstOperands,
     /* 289365 */     // GIR_Coverage, 2440,
     /* 289365 */     GIR_EraseRootFromParent_Done,
     /* 289366 */   // Label 5613: @289366
     /* 289366 */   GIM_Reject,
     /* 289367 */ // Label 5606: @289367
     /* 289367 */ GIM_Reject,
     /* 289368 */ // Label 5604: @289368
     /* 289368 */ GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(289817),
     /* 289373 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289376 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 289379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289383 */   GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(289447), // Rule ID 6594 //
     /* 289388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 289396 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 289400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289405 */     // MIs[1] Operand 2
     /* 289405 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 289416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 289420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289424 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 289428 */     // MIs[2] Operand 1
     /* 289428 */     // No operand predicates
     /* 289428 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 289430 */     // (sra:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i8:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm, 7:{ *:[i64] })
     /* 289430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 289433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289435 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 289439 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 289442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 289445 */     GIR_RootConstrainSelectedInstOperands,
     /* 289446 */     // GIR_Coverage, 6594,
     /* 289446 */     GIR_EraseRootFromParent_Done,
     /* 289447 */   // Label 5615: @289447
     /* 289447 */   GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(289511), // Rule ID 6596 //
     /* 289452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 289460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 289464 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289469 */     // MIs[1] Operand 2
     /* 289469 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 289480 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 289484 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289488 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
     /* 289492 */     // MIs[2] Operand 1
     /* 289492 */     // No operand predicates
     /* 289492 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 289494 */     // (sra:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i16:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm, 15:{ *:[i64] })
     /* 289494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 289497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 289503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 289506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 289509 */     GIR_RootConstrainSelectedInstOperands,
     /* 289510 */     // GIR_Coverage, 6596,
     /* 289510 */     GIR_EraseRootFromParent_Done,
     /* 289511 */   // Label 5616: @289511
     /* 289511 */   GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(289614), // Rule ID 6597 //
     /* 289516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 289524 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289528 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289533 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 289537 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289541 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 289545 */     // MIs[2] Operand 1
     /* 289545 */     // No operand predicates
     /* 289545 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 289547 */     // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 289547 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 289550 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 289554 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289559 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 289561 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 289564 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 289568 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289573 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 289576 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 289580 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 289583 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289588 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289593 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 289601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289603 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289606 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 289609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 289612 */     GIR_RootConstrainSelectedInstOperands,
     /* 289613 */     // GIR_Coverage, 6597,
     /* 289613 */     GIR_EraseRootFromParent_Done,
     /* 289614 */   // Label 5617: @289614
     /* 289614 */   GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(289652), // Rule ID 4056 //
     /* 289619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289631 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 289635 */     // MIs[1] Operand 1
     /* 289635 */     // No operand predicates
     /* 289635 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289637 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
     /* 289637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 289640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289642 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289644 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 289647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
     /* 289650 */     GIR_RootConstrainSelectedInstOperands,
     /* 289651 */     // GIR_Coverage, 4056,
     /* 289651 */     GIR_EraseRootFromParent_Done,
     /* 289652 */   // Label 5618: @289652
     /* 289652 */   GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(289724), // Rule ID 2444 //
     /* 289657 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 289669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289678 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289680 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 289680 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 289683 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289687 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289692 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 289695 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 289699 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 289702 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289707 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 289715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289717 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289719 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289722 */     GIR_RootConstrainSelectedInstOperands,
     /* 289723 */     // GIR_Coverage, 2444,
     /* 289723 */     GIR_EraseRootFromParent_Done,
     /* 289724 */   // Label 5619: @289724
     /* 289724 */   GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(289796), // Rule ID 2445 //
     /* 289729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 289737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 289741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 289745 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289752 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 289752 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 289755 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289759 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289764 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 289767 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 289771 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 289774 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289779 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 289787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289789 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289791 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289794 */     GIR_RootConstrainSelectedInstOperands,
     /* 289795 */     // GIR_Coverage, 2445,
     /* 289795 */     GIR_EraseRootFromParent_Done,
     /* 289796 */   // Label 5620: @289796
     /* 289796 */   GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(289816), // Rule ID 119 //
     /* 289801 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289809 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 289809 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 289814 */     GIR_RootConstrainSelectedInstOperands,
     /* 289815 */     // GIR_Coverage, 119,
     /* 289815 */     GIR_Done,
     /* 289816 */   // Label 5621: @289816
     /* 289816 */   GIM_Reject,
     /* 289817 */ // Label 5614: @289817
     /* 289817 */ GIM_Reject,
     /* 289818 */ // Label 5605: @289818
     /* 289818 */ GIM_Reject,
     /* 289819 */ // Label 49: @289819
     /* 289819 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5624*/ GIMT_Encode4(289948),
     /* 289830 */ /*GILLT_s32*//*Label 5622*/ GIMT_Encode4(289838),
     /* 289834 */ /*GILLT_s64*//*Label 5623*/ GIMT_Encode4(289893),
     /* 289838 */ // Label 5622: @289838
     /* 289838 */ GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(289892), // Rule ID 192 //
     /* 289843 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289846 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 289849 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 289852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289856 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289860 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289864 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 289868 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289872 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 289876 */   // MIs[1] Operand 1
     /* 289876 */   // No operand predicates
     /* 289876 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289878 */   // (fshr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] }):$imm)
     /* 289878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
     /* 289881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289883 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289885 */   GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 289887 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 289890 */   GIR_RootConstrainSelectedInstOperands,
     /* 289891 */   // GIR_Coverage, 192,
     /* 289891 */   GIR_EraseRootFromParent_Done,
     /* 289892 */ // Label 5625: @289892
     /* 289892 */ GIM_Reject,
     /* 289893 */ // Label 5623: @289893
     /* 289893 */ GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(289947), // Rule ID 193 //
     /* 289898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289901 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 289904 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 289907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289911 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289915 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289919 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 289923 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289927 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 289931 */   // MIs[1] Operand 1
     /* 289931 */   // No operand predicates
     /* 289931 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289933 */   // (fshr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] }):$imm)
     /* 289933 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
     /* 289936 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 289938 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 289940 */   GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 289942 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 289945 */   GIR_RootConstrainSelectedInstOperands,
     /* 289946 */   // GIR_Coverage, 193,
     /* 289946 */   GIR_EraseRootFromParent_Done,
     /* 289947 */ // Label 5626: @289947
     /* 289947 */ GIM_Reject,
     /* 289948 */ // Label 5624: @289948
     /* 289948 */ GIM_Reject,
     /* 289949 */ // Label 50: @289949
     /* 289949 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5629*/ GIMT_Encode4(290490),
     /* 289960 */ /*GILLT_s32*//*Label 5627*/ GIMT_Encode4(289968),
     /* 289964 */ /*GILLT_s64*//*Label 5628*/ GIMT_Encode4(290233),
     /* 289968 */ // Label 5627: @289968
     /* 289968 */ GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(290232),
     /* 289973 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289976 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 289979 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289983 */   GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(290022), // Rule ID 188 //
     /* 289988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 289996 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290000 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290005 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
     /* 290009 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290011 */     // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn), 16:{ *:[i64] })  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 290011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 290014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290016 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 290020 */     GIR_RootConstrainSelectedInstOperands,
     /* 290021 */     // GIR_Coverage, 188,
     /* 290021 */     GIR_EraseRootFromParent_Done,
     /* 290022 */   // Label 5631: @290022
     /* 290022 */   GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(290059), // Rule ID 4051 //
     /* 290027 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 290039 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 290043 */     // MIs[1] Operand 1
     /* 290043 */     // No operand predicates
     /* 290043 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290045 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 290045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
     /* 290048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290050 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290052 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290054 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 290057 */     GIR_RootConstrainSelectedInstOperands,
     /* 290058 */     // GIR_Coverage, 4051,
     /* 290058 */     GIR_EraseRootFromParent_Done,
     /* 290059 */   // Label 5632: @290059
     /* 290059 */   GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(290100), // Rule ID 3980 //
     /* 290064 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 290076 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290087 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 290087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 290090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290092 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 290098 */     GIR_RootConstrainSelectedInstOperands,
     /* 290099 */     // GIR_Coverage, 3980,
     /* 290099 */     GIR_EraseRootFromParent_Done,
     /* 290100 */   // Label 5633: @290100
     /* 290100 */   GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(290141), // Rule ID 3981 //
     /* 290105 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290113 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 290117 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290121 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290126 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290128 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 290128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 290131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290133 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 290139 */     GIR_RootConstrainSelectedInstOperands,
     /* 290140 */     // GIR_Coverage, 3981,
     /* 290140 */     GIR_EraseRootFromParent_Done,
     /* 290141 */   // Label 5634: @290141
     /* 290141 */   GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(290182), // Rule ID 3979 //
     /* 290146 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290158 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290162 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290167 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290169 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 290169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 290172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290174 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 290180 */     GIR_RootConstrainSelectedInstOperands,
     /* 290181 */     // GIR_Coverage, 3979,
     /* 290181 */     GIR_EraseRootFromParent_Done,
     /* 290182 */   // Label 5635: @290182
     /* 290182 */   GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(290231), // Rule ID 3978 //
     /* 290187 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290191 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 290191 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 290194 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 290198 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 290203 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 290209 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290214 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 290222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290224 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290226 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 290229 */     GIR_RootConstrainSelectedInstOperands,
     /* 290230 */     // GIR_Coverage, 3978,
     /* 290230 */     GIR_EraseRootFromParent_Done,
     /* 290231 */   // Label 5636: @290231
     /* 290231 */   GIM_Reject,
     /* 290232 */ // Label 5630: @290232
     /* 290232 */ GIM_Reject,
     /* 290233 */ // Label 5628: @290233
     /* 290233 */ GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(290489),
     /* 290238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 290241 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290248 */   GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(290287), // Rule ID 191 //
     /* 290253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 290257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 290261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 290265 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290270 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32,
     /* 290274 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290276 */     // (rotr:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn), 32:{ *:[i64] })  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 290276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 290279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290281 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 290285 */     GIR_RootConstrainSelectedInstOperands,
     /* 290286 */     // GIR_Coverage, 191,
     /* 290286 */     GIR_EraseRootFromParent_Done,
     /* 290287 */   // Label 5638: @290287
     /* 290287 */   GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(290324), // Rule ID 4052 //
     /* 290292 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 290304 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 290308 */     // MIs[1] Operand 1
     /* 290308 */     // No operand predicates
     /* 290308 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290310 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)
     /* 290310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
     /* 290313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290315 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290317 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290319 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 290322 */     GIR_RootConstrainSelectedInstOperands,
     /* 290323 */     // GIR_Coverage, 4052,
     /* 290323 */     GIR_EraseRootFromParent_Done,
     /* 290324 */   // Label 5639: @290324
     /* 290324 */   GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(290396), // Rule ID 3982 //
     /* 290329 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290333 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290337 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 290341 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290345 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290350 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290352 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 290352 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 290355 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 290359 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 290364 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 290367 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 290371 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 290374 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 290379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 290387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290389 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290391 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 290394 */     GIR_RootConstrainSelectedInstOperands,
     /* 290395 */     // GIR_Coverage, 3982,
     /* 290395 */     GIR_EraseRootFromParent_Done,
     /* 290396 */   // Label 5640: @290396
     /* 290396 */   GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(290468), // Rule ID 3983 //
     /* 290401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290417 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290422 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290424 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 290424 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 290427 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 290431 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 290436 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 290439 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 290443 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 290446 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 290451 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 290459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290461 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 290463 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 290466 */     GIR_RootConstrainSelectedInstOperands,
     /* 290467 */     // GIR_Coverage, 3983,
     /* 290467 */     GIR_EraseRootFromParent_Done,
     /* 290468 */   // Label 5641: @290468
     /* 290468 */   GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(290488), // Rule ID 122 //
     /* 290473 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290477 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290481 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 290481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 290486 */     GIR_RootConstrainSelectedInstOperands,
     /* 290487 */     // GIR_Coverage, 122,
     /* 290487 */     GIR_Done,
     /* 290488 */   // Label 5642: @290488
     /* 290488 */   GIM_Reject,
     /* 290489 */ // Label 5637: @290489
     /* 290489 */ GIM_Reject,
     /* 290490 */ // Label 5629: @290490
     /* 290490 */ GIM_Reject,
     /* 290491 */ // Label 51: @290491
     /* 290491 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 5651*/ GIMT_Encode4(298267),
     /* 290502 */ /*GILLT_s64*//*Label 5643*/ GIMT_Encode4(290538), GIMT_Encode4(0),
     /* 290510 */ /*GILLT_v2s32*//*Label 5644*/ GIMT_Encode4(290931),
     /* 290514 */ /*GILLT_v2s64*//*Label 5645*/ GIMT_Encode4(291979),
     /* 290518 */ /*GILLT_v4s16*//*Label 5646*/ GIMT_Encode4(293027),
     /* 290522 */ /*GILLT_v4s32*//*Label 5647*/ GIMT_Encode4(294075),
     /* 290526 */ /*GILLT_v8s8*//*Label 5648*/ GIMT_Encode4(295123),
     /* 290530 */ /*GILLT_v8s16*//*Label 5649*/ GIMT_Encode4(296171),
     /* 290534 */ /*GILLT_v16s8*//*Label 5650*/ GIMT_Encode4(297219),
     /* 290538 */ // Label 5643: @290538
     /* 290538 */ GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(290930),
     /* 290543 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290546 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 290549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290553 */   GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(290589), // Rule ID 5290 //
     /* 290558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290561 */     // MIs[0] Operand 1
     /* 290561 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 290566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290570 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290576 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290578 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290580 */     // (setcc:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, v1i64:{ *:[v1i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv1i64rz),
     /* 290583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290585 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 290587 */     GIR_RootConstrainSelectedInstOperands,
     /* 290588 */     // GIR_Coverage, 5290,
     /* 290588 */     GIR_EraseRootFromParent_Done,
     /* 290589 */   // Label 5653: @290589
     /* 290589 */   GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(290625), // Rule ID 5291 //
     /* 290594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290597 */     // MIs[0] Operand 1
     /* 290597 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 290602 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290606 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290612 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290614 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290616 */     // (setcc:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, v1i64:{ *:[v1i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv1i64rz),
     /* 290619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290621 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 290623 */     GIR_RootConstrainSelectedInstOperands,
     /* 290624 */     // GIR_Coverage, 5291,
     /* 290624 */     GIR_EraseRootFromParent_Done,
     /* 290625 */   // Label 5654: @290625
     /* 290625 */   GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(290661), // Rule ID 2512 //
     /* 290630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290633 */     // MIs[0] Operand 1
     /* 290633 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 290638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 290642 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290648 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290652 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv1i64rz),
     /* 290655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290659 */     GIR_RootConstrainSelectedInstOperands,
     /* 290660 */     // GIR_Coverage, 2512,
     /* 290660 */     GIR_EraseRootFromParent_Done,
     /* 290661 */   // Label 5655: @290661
     /* 290661 */   GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(290697), // Rule ID 5287 //
     /* 290666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290669 */     // MIs[0] Operand 1
     /* 290669 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 290674 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 290678 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290684 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290686 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290688 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETGE:{ *:[Other] })  =>  (CMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64rz),
     /* 290691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290693 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290695 */     GIR_RootConstrainSelectedInstOperands,
     /* 290696 */     // GIR_Coverage, 5287,
     /* 290696 */     GIR_EraseRootFromParent_Done,
     /* 290697 */   // Label 5656: @290697
     /* 290697 */   GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(290733), // Rule ID 5288 //
     /* 290702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290705 */     // MIs[0] Operand 1
     /* 290705 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 290710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 290714 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290720 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 290722 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290724 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] }, SETGT:{ *:[Other] })  =>  (CMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64rz),
     /* 290727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290731 */     GIR_RootConstrainSelectedInstOperands,
     /* 290732 */     // GIR_Coverage, 5288,
     /* 290732 */     GIR_EraseRootFromParent_Done,
     /* 290733 */   // Label 5657: @290733
     /* 290733 */   GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(290769), // Rule ID 5289 //
     /* 290738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290741 */     // MIs[0] Operand 1
     /* 290741 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 290746 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 290750 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290756 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290758 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290760 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETGT:{ *:[Other] })  =>  (CMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 290760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv1i64rz),
     /* 290763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290767 */     GIR_RootConstrainSelectedInstOperands,
     /* 290768 */     // GIR_Coverage, 5289,
     /* 290768 */     GIR_EraseRootFromParent_Done,
     /* 290769 */   // Label 5658: @290769
     /* 290769 */   GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(290801), // Rule ID 1612 //
     /* 290774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290777 */     // MIs[0] Operand 1
     /* 290777 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 290782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290786 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290790 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 290790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv1i64),
     /* 290793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290797 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 290799 */     GIR_RootConstrainSelectedInstOperands,
     /* 290800 */     // GIR_Coverage, 1612,
     /* 290800 */     GIR_EraseRootFromParent_Done,
     /* 290801 */   // Label 5659: @290801
     /* 290801 */   GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(290833), // Rule ID 1613 //
     /* 290806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290809 */     // MIs[0] Operand 1
     /* 290809 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 290814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290822 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 290822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64),
     /* 290825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 290831 */     GIR_RootConstrainSelectedInstOperands,
     /* 290832 */     // GIR_Coverage, 1613,
     /* 290832 */     GIR_EraseRootFromParent_Done,
     /* 290833 */   // Label 5660: @290833
     /* 290833 */   GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(290865), // Rule ID 1614 //
     /* 290838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290841 */     // MIs[0] Operand 1
     /* 290841 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 290846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290850 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290854 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 290854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv1i64),
     /* 290857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290861 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 290863 */     GIR_RootConstrainSelectedInstOperands,
     /* 290864 */     // GIR_Coverage, 1614,
     /* 290864 */     GIR_EraseRootFromParent_Done,
     /* 290865 */   // Label 5661: @290865
     /* 290865 */   GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(290897), // Rule ID 1615 //
     /* 290870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290873 */     // MIs[0] Operand 1
     /* 290873 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 290878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290882 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290886 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 290886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv1i64),
     /* 290889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290893 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 290895 */     GIR_RootConstrainSelectedInstOperands,
     /* 290896 */     // GIR_Coverage, 1615,
     /* 290896 */     GIR_EraseRootFromParent_Done,
     /* 290897 */   // Label 5662: @290897
     /* 290897 */   GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(290929), // Rule ID 1616 //
     /* 290902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290905 */     // MIs[0] Operand 1
     /* 290905 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 290910 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290914 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290918 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 290918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv1i64),
     /* 290921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290923 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 290927 */     GIR_RootConstrainSelectedInstOperands,
     /* 290928 */     // GIR_Coverage, 1616,
     /* 290928 */     GIR_EraseRootFromParent_Done,
     /* 290929 */   // Label 5663: @290929
     /* 290929 */   GIM_Reject,
     /* 290930 */ // Label 5652: @290930
     /* 290930 */ GIM_Reject,
     /* 290931 */ // Label 5644: @290931
     /* 290931 */ GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(291978),
     /* 290936 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 290939 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 290942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290946 */   GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(290986), // Rule ID 758 //
     /* 290951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290954 */     // MIs[0] Operand 1
     /* 290954 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 290959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290963 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 290969 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 290971 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290975 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290977 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 290977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 290980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 290984 */     GIR_RootConstrainSelectedInstOperands,
     /* 290985 */     // GIR_Coverage, 758,
     /* 290985 */     GIR_EraseRootFromParent_Done,
     /* 290986 */   // Label 5665: @290986
     /* 290986 */   GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(291026), // Rule ID 765 //
     /* 290991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 290994 */     // MIs[0] Operand 1
     /* 290994 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 290999 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291003 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291009 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291011 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291015 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291017 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 291020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291022 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291024 */     GIR_RootConstrainSelectedInstOperands,
     /* 291025 */     // GIR_Coverage, 765,
     /* 291025 */     GIR_EraseRootFromParent_Done,
     /* 291026 */   // Label 5666: @291026
     /* 291026 */   GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(291063), // Rule ID 5224 //
     /* 291031 */     // MIs[0] Operand 1
     /* 291031 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 291036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291040 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291046 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291048 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291052 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291054 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 291057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291061 */     GIR_RootConstrainSelectedInstOperands,
     /* 291062 */     // GIR_Coverage, 5224,
     /* 291062 */     GIR_EraseRootFromParent_Done,
     /* 291063 */   // Label 5667: @291063
     /* 291063 */   GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(291100), // Rule ID 5231 //
     /* 291068 */     // MIs[0] Operand 1
     /* 291068 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291077 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291083 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291085 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291089 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291091 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 291094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291098 */     GIR_RootConstrainSelectedInstOperands,
     /* 291099 */     // GIR_Coverage, 5231,
     /* 291099 */     GIR_EraseRootFromParent_Done,
     /* 291100 */   // Label 5668: @291100
     /* 291100 */   GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(291137), // Rule ID 5238 //
     /* 291105 */     // MIs[0] Operand 1
     /* 291105 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 291110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291114 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291120 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291122 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291126 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291128 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 291131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291133 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291135 */     GIR_RootConstrainSelectedInstOperands,
     /* 291136 */     // GIR_Coverage, 5238,
     /* 291136 */     GIR_EraseRootFromParent_Done,
     /* 291137 */   // Label 5669: @291137
     /* 291137 */   GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(291174), // Rule ID 5245 //
     /* 291142 */     // MIs[0] Operand 1
     /* 291142 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 291147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291151 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291157 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291159 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291163 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291165 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 291168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291172 */     GIR_RootConstrainSelectedInstOperands,
     /* 291173 */     // GIR_Coverage, 5245,
     /* 291173 */     GIR_EraseRootFromParent_Done,
     /* 291174 */   // Label 5670: @291174
     /* 291174 */   GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(291211), // Rule ID 5252 //
     /* 291179 */     // MIs[0] Operand 1
     /* 291179 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 291184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291188 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291194 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291196 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291200 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291202 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 291205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291207 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 291209 */     GIR_RootConstrainSelectedInstOperands,
     /* 291210 */     // GIR_Coverage, 5252,
     /* 291210 */     GIR_EraseRootFromParent_Done,
     /* 291211 */   // Label 5671: @291211
     /* 291211 */   GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(291251), // Rule ID 730 //
     /* 291216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291219 */     // MIs[0] Operand 1
     /* 291219 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 291224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291232 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291238 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291240 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291242 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 291245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291247 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291249 */     GIR_RootConstrainSelectedInstOperands,
     /* 291250 */     // GIR_Coverage, 730,
     /* 291250 */     GIR_EraseRootFromParent_Done,
     /* 291251 */   // Label 5672: @291251
     /* 291251 */   GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(291291), // Rule ID 741 //
     /* 291256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291259 */     // MIs[0] Operand 1
     /* 291259 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 291264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291272 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291278 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291280 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291282 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 291285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291289 */     GIR_RootConstrainSelectedInstOperands,
     /* 291290 */     // GIR_Coverage, 741,
     /* 291290 */     GIR_EraseRootFromParent_Done,
     /* 291291 */   // Label 5673: @291291
     /* 291291 */   GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(291331), // Rule ID 742 //
     /* 291296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291299 */     // MIs[0] Operand 1
     /* 291299 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291312 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291318 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 291320 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291322 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 291325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291329 */     GIR_RootConstrainSelectedInstOperands,
     /* 291330 */     // GIR_Coverage, 742,
     /* 291330 */     GIR_EraseRootFromParent_Done,
     /* 291331 */   // Label 5674: @291331
     /* 291331 */   GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(291371), // Rule ID 751 //
     /* 291336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291339 */     // MIs[0] Operand 1
     /* 291339 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291344 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291348 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291352 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291358 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291360 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291362 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 291365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291369 */     GIR_RootConstrainSelectedInstOperands,
     /* 291370 */     // GIR_Coverage, 751,
     /* 291370 */     GIR_EraseRootFromParent_Done,
     /* 291371 */   // Label 5675: @291371
     /* 291371 */   GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(291408), // Rule ID 5189 //
     /* 291376 */     // MIs[0] Operand 1
     /* 291376 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 291381 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291389 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291395 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291397 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291399 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 291402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291406 */     GIR_RootConstrainSelectedInstOperands,
     /* 291407 */     // GIR_Coverage, 5189,
     /* 291407 */     GIR_EraseRootFromParent_Done,
     /* 291408 */   // Label 5676: @291408
     /* 291408 */   GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(291445), // Rule ID 5196 //
     /* 291413 */     // MIs[0] Operand 1
     /* 291413 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291418 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291426 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291432 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291434 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291436 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 291439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291443 */     GIR_RootConstrainSelectedInstOperands,
     /* 291444 */     // GIR_Coverage, 5196,
     /* 291444 */     GIR_EraseRootFromParent_Done,
     /* 291445 */   // Label 5677: @291445
     /* 291445 */   GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(291482), // Rule ID 5203 //
     /* 291450 */     // MIs[0] Operand 1
     /* 291450 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 291455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291463 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291469 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291471 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291473 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 291476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291480 */     GIR_RootConstrainSelectedInstOperands,
     /* 291481 */     // GIR_Coverage, 5203,
     /* 291481 */     GIR_EraseRootFromParent_Done,
     /* 291482 */   // Label 5678: @291482
     /* 291482 */   GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(291519), // Rule ID 5210 //
     /* 291487 */     // MIs[0] Operand 1
     /* 291487 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 291492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291500 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291506 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291508 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291510 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 291513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291517 */     GIR_RootConstrainSelectedInstOperands,
     /* 291518 */     // GIR_Coverage, 5210,
     /* 291518 */     GIR_EraseRootFromParent_Done,
     /* 291519 */   // Label 5679: @291519
     /* 291519 */   GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(291556), // Rule ID 5217 //
     /* 291524 */     // MIs[0] Operand 1
     /* 291524 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 291529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291533 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 291537 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 291543 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 291545 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291547 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 291547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 291550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291554 */     GIR_RootConstrainSelectedInstOperands,
     /* 291555 */     // GIR_Coverage, 5217,
     /* 291555 */     GIR_EraseRootFromParent_Done,
     /* 291556 */   // Label 5680: @291556
     /* 291556 */   GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(291588), // Rule ID 1129 //
     /* 291561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291564 */     // MIs[0] Operand 1
     /* 291564 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 291569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291573 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291577 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32),
     /* 291580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291582 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291584 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291586 */     GIR_RootConstrainSelectedInstOperands,
     /* 291587 */     // GIR_Coverage, 1129,
     /* 291587 */     GIR_EraseRootFromParent_Done,
     /* 291588 */   // Label 5681: @291588
     /* 291588 */   GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(291620), // Rule ID 1136 //
     /* 291593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291596 */     // MIs[0] Operand 1
     /* 291596 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 291601 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291605 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291609 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 291612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291618 */     GIR_RootConstrainSelectedInstOperands,
     /* 291619 */     // GIR_Coverage, 1136,
     /* 291619 */     GIR_EraseRootFromParent_Done,
     /* 291620 */   // Label 5682: @291620
     /* 291620 */   GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(291652), // Rule ID 1143 //
     /* 291625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291628 */     // MIs[0] Operand 1
     /* 291628 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291633 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291637 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291641 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 291644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291646 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291648 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291650 */     GIR_RootConstrainSelectedInstOperands,
     /* 291651 */     // GIR_Coverage, 1143,
     /* 291651 */     GIR_EraseRootFromParent_Done,
     /* 291652 */   // Label 5683: @291652
     /* 291652 */   GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(291684), // Rule ID 1150 //
     /* 291657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291660 */     // MIs[0] Operand 1
     /* 291660 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 291665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291673 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 291676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291682 */     GIR_RootConstrainSelectedInstOperands,
     /* 291683 */     // GIR_Coverage, 1150,
     /* 291683 */     GIR_EraseRootFromParent_Done,
     /* 291684 */   // Label 5684: @291684
     /* 291684 */   GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(291716), // Rule ID 1157 //
     /* 291689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 291692 */     // MIs[0] Operand 1
     /* 291692 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 291697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291701 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291705 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 291708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291712 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291714 */     GIR_RootConstrainSelectedInstOperands,
     /* 291715 */     // GIR_Coverage, 1157,
     /* 291715 */     GIR_EraseRootFromParent_Done,
     /* 291716 */   // Label 5685: @291716
     /* 291716 */   GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(291745), // Rule ID 5126 //
     /* 291721 */     // MIs[0] Operand 1
     /* 291721 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 291726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291730 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291734 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32),
     /* 291737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291743 */     GIR_RootConstrainSelectedInstOperands,
     /* 291744 */     // GIR_Coverage, 5126,
     /* 291744 */     GIR_EraseRootFromParent_Done,
     /* 291745 */   // Label 5686: @291745
     /* 291745 */   GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(291774), // Rule ID 5133 //
     /* 291750 */     // MIs[0] Operand 1
     /* 291750 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 291755 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291759 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291763 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 291766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291770 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291772 */     GIR_RootConstrainSelectedInstOperands,
     /* 291773 */     // GIR_Coverage, 5133,
     /* 291773 */     GIR_EraseRootFromParent_Done,
     /* 291774 */   // Label 5687: @291774
     /* 291774 */   GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(291803), // Rule ID 5140 //
     /* 291779 */     // MIs[0] Operand 1
     /* 291779 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 291784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291788 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291792 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 291795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291799 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291801 */     GIR_RootConstrainSelectedInstOperands,
     /* 291802 */     // GIR_Coverage, 5140,
     /* 291802 */     GIR_EraseRootFromParent_Done,
     /* 291803 */   // Label 5688: @291803
     /* 291803 */   GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(291832), // Rule ID 5147 //
     /* 291808 */     // MIs[0] Operand 1
     /* 291808 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 291813 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291817 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291821 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 291824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291830 */     GIR_RootConstrainSelectedInstOperands,
     /* 291831 */     // GIR_Coverage, 5147,
     /* 291831 */     GIR_EraseRootFromParent_Done,
     /* 291832 */   // Label 5689: @291832
     /* 291832 */   GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(291861), // Rule ID 5154 //
     /* 291837 */     // MIs[0] Operand 1
     /* 291837 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 291842 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291846 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291850 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 291850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 291853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291857 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291859 */     GIR_RootConstrainSelectedInstOperands,
     /* 291860 */     // GIR_Coverage, 5154,
     /* 291860 */     GIR_EraseRootFromParent_Done,
     /* 291861 */   // Label 5690: @291861
     /* 291861 */   GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(291890), // Rule ID 5161 //
     /* 291866 */     // MIs[0] Operand 1
     /* 291866 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 291871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291875 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291879 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 291879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 291882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291884 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291888 */     GIR_RootConstrainSelectedInstOperands,
     /* 291889 */     // GIR_Coverage, 5161,
     /* 291889 */     GIR_EraseRootFromParent_Done,
     /* 291890 */   // Label 5691: @291890
     /* 291890 */   GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(291919), // Rule ID 5168 //
     /* 291895 */     // MIs[0] Operand 1
     /* 291895 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 291900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291904 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291908 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 291908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 291911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291913 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291915 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291917 */     GIR_RootConstrainSelectedInstOperands,
     /* 291918 */     // GIR_Coverage, 5168,
     /* 291918 */     GIR_EraseRootFromParent_Done,
     /* 291919 */   // Label 5692: @291919
     /* 291919 */   GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(291948), // Rule ID 5175 //
     /* 291924 */     // MIs[0] Operand 1
     /* 291924 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 291929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291937 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 291937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 291940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291946 */     GIR_RootConstrainSelectedInstOperands,
     /* 291947 */     // GIR_Coverage, 5175,
     /* 291947 */     GIR_EraseRootFromParent_Done,
     /* 291948 */   // Label 5693: @291948
     /* 291948 */   GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(291977), // Rule ID 5182 //
     /* 291953 */     // MIs[0] Operand 1
     /* 291953 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 291958 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291962 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 291966 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 291966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 291969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 291971 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 291973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 291975 */     GIR_RootConstrainSelectedInstOperands,
     /* 291976 */     // GIR_Coverage, 5182,
     /* 291976 */     GIR_EraseRootFromParent_Done,
     /* 291977 */   // Label 5694: @291977
     /* 291977 */   GIM_Reject,
     /* 291978 */ // Label 5664: @291978
     /* 291978 */ GIM_Reject,
     /* 291979 */ // Label 5645: @291979
     /* 291979 */ GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(293026),
     /* 291984 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 291987 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 291990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 291994 */   GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(292034), // Rule ID 760 //
     /* 291999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292002 */     // MIs[0] Operand 1
     /* 292002 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292007 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292011 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292017 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292019 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292023 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292025 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 292028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292032 */     GIR_RootConstrainSelectedInstOperands,
     /* 292033 */     // GIR_Coverage, 760,
     /* 292033 */     GIR_EraseRootFromParent_Done,
     /* 292034 */   // Label 5696: @292034
     /* 292034 */   GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(292074), // Rule ID 767 //
     /* 292039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292042 */     // MIs[0] Operand 1
     /* 292042 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292047 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292051 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292057 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292059 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292063 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292065 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 292068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292072 */     GIR_RootConstrainSelectedInstOperands,
     /* 292073 */     // GIR_Coverage, 767,
     /* 292073 */     GIR_EraseRootFromParent_Done,
     /* 292074 */   // Label 5697: @292074
     /* 292074 */   GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(292111), // Rule ID 5226 //
     /* 292079 */     // MIs[0] Operand 1
     /* 292079 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 292084 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292088 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292094 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292100 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292102 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 292105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292109 */     GIR_RootConstrainSelectedInstOperands,
     /* 292110 */     // GIR_Coverage, 5226,
     /* 292110 */     GIR_EraseRootFromParent_Done,
     /* 292111 */   // Label 5698: @292111
     /* 292111 */   GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(292148), // Rule ID 5233 //
     /* 292116 */     // MIs[0] Operand 1
     /* 292116 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292121 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292125 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292131 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292133 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292137 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292139 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 292142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292146 */     GIR_RootConstrainSelectedInstOperands,
     /* 292147 */     // GIR_Coverage, 5233,
     /* 292147 */     GIR_EraseRootFromParent_Done,
     /* 292148 */   // Label 5699: @292148
     /* 292148 */   GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(292185), // Rule ID 5240 //
     /* 292153 */     // MIs[0] Operand 1
     /* 292153 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292162 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292168 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292170 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292174 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292176 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 292179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292181 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292183 */     GIR_RootConstrainSelectedInstOperands,
     /* 292184 */     // GIR_Coverage, 5240,
     /* 292184 */     GIR_EraseRootFromParent_Done,
     /* 292185 */   // Label 5700: @292185
     /* 292185 */   GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(292222), // Rule ID 5247 //
     /* 292190 */     // MIs[0] Operand 1
     /* 292190 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 292195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292199 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292205 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292211 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292213 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 292216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292220 */     GIR_RootConstrainSelectedInstOperands,
     /* 292221 */     // GIR_Coverage, 5247,
     /* 292221 */     GIR_EraseRootFromParent_Done,
     /* 292222 */   // Label 5701: @292222
     /* 292222 */   GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(292259), // Rule ID 5254 //
     /* 292227 */     // MIs[0] Operand 1
     /* 292227 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 292232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 292236 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292242 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292244 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292248 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292250 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 292253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 292257 */     GIR_RootConstrainSelectedInstOperands,
     /* 292258 */     // GIR_Coverage, 5254,
     /* 292258 */     GIR_EraseRootFromParent_Done,
     /* 292259 */   // Label 5702: @292259
     /* 292259 */   GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(292299), // Rule ID 732 //
     /* 292264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292267 */     // MIs[0] Operand 1
     /* 292267 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 292272 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292280 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292286 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292288 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292290 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 292293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292297 */     GIR_RootConstrainSelectedInstOperands,
     /* 292298 */     // GIR_Coverage, 732,
     /* 292298 */     GIR_EraseRootFromParent_Done,
     /* 292299 */   // Label 5703: @292299
     /* 292299 */   GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(292339), // Rule ID 745 //
     /* 292304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292307 */     // MIs[0] Operand 1
     /* 292307 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292312 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292316 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292320 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292326 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292328 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292330 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 292333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292337 */     GIR_RootConstrainSelectedInstOperands,
     /* 292338 */     // GIR_Coverage, 745,
     /* 292338 */     GIR_EraseRootFromParent_Done,
     /* 292339 */   // Label 5704: @292339
     /* 292339 */   GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(292379), // Rule ID 746 //
     /* 292344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292347 */     // MIs[0] Operand 1
     /* 292347 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292352 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292360 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292366 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 292368 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292370 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 292373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292375 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292377 */     GIR_RootConstrainSelectedInstOperands,
     /* 292378 */     // GIR_Coverage, 746,
     /* 292378 */     GIR_EraseRootFromParent_Done,
     /* 292379 */   // Label 5705: @292379
     /* 292379 */   GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(292419), // Rule ID 753 //
     /* 292384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292387 */     // MIs[0] Operand 1
     /* 292387 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292396 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292400 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292406 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292408 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292410 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 292413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292417 */     GIR_RootConstrainSelectedInstOperands,
     /* 292418 */     // GIR_Coverage, 753,
     /* 292418 */     GIR_EraseRootFromParent_Done,
     /* 292419 */   // Label 5706: @292419
     /* 292419 */   GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(292456), // Rule ID 5191 //
     /* 292424 */     // MIs[0] Operand 1
     /* 292424 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 292429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292437 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292443 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292445 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292447 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 292450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292454 */     GIR_RootConstrainSelectedInstOperands,
     /* 292455 */     // GIR_Coverage, 5191,
     /* 292455 */     GIR_EraseRootFromParent_Done,
     /* 292456 */   // Label 5707: @292456
     /* 292456 */   GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(292493), // Rule ID 5198 //
     /* 292461 */     // MIs[0] Operand 1
     /* 292461 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292466 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292474 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292480 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292482 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292484 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 292487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292491 */     GIR_RootConstrainSelectedInstOperands,
     /* 292492 */     // GIR_Coverage, 5198,
     /* 292492 */     GIR_EraseRootFromParent_Done,
     /* 292493 */   // Label 5708: @292493
     /* 292493 */   GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(292530), // Rule ID 5205 //
     /* 292498 */     // MIs[0] Operand 1
     /* 292498 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292507 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292511 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292517 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292519 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292521 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 292524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292528 */     GIR_RootConstrainSelectedInstOperands,
     /* 292529 */     // GIR_Coverage, 5205,
     /* 292529 */     GIR_EraseRootFromParent_Done,
     /* 292530 */   // Label 5709: @292530
     /* 292530 */   GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(292567), // Rule ID 5212 //
     /* 292535 */     // MIs[0] Operand 1
     /* 292535 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 292540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292548 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292554 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292556 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292558 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 292561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292565 */     GIR_RootConstrainSelectedInstOperands,
     /* 292566 */     // GIR_Coverage, 5212,
     /* 292566 */     GIR_EraseRootFromParent_Done,
     /* 292567 */   // Label 5710: @292567
     /* 292567 */   GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(292604), // Rule ID 5219 //
     /* 292572 */     // MIs[0] Operand 1
     /* 292572 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 292577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 292585 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 292591 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 292593 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 292595 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 292595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 292598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292602 */     GIR_RootConstrainSelectedInstOperands,
     /* 292603 */     // GIR_Coverage, 5219,
     /* 292603 */     GIR_EraseRootFromParent_Done,
     /* 292604 */   // Label 5711: @292604
     /* 292604 */   GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(292636), // Rule ID 1131 //
     /* 292609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292612 */     // MIs[0] Operand 1
     /* 292612 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 292617 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292621 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292625 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64),
     /* 292628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292630 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292632 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292634 */     GIR_RootConstrainSelectedInstOperands,
     /* 292635 */     // GIR_Coverage, 1131,
     /* 292635 */     GIR_EraseRootFromParent_Done,
     /* 292636 */   // Label 5712: @292636
     /* 292636 */   GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(292668), // Rule ID 1138 //
     /* 292641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292644 */     // MIs[0] Operand 1
     /* 292644 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292649 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292653 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292657 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 292660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292666 */     GIR_RootConstrainSelectedInstOperands,
     /* 292667 */     // GIR_Coverage, 1138,
     /* 292667 */     GIR_EraseRootFromParent_Done,
     /* 292668 */   // Label 5713: @292668
     /* 292668 */   GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(292700), // Rule ID 1145 //
     /* 292673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292676 */     // MIs[0] Operand 1
     /* 292676 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292681 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292685 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292689 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 292692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292696 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292698 */     GIR_RootConstrainSelectedInstOperands,
     /* 292699 */     // GIR_Coverage, 1145,
     /* 292699 */     GIR_EraseRootFromParent_Done,
     /* 292700 */   // Label 5714: @292700
     /* 292700 */   GIM_Try, /*On fail goto*//*Label 5715*/ GIMT_Encode4(292732), // Rule ID 1152 //
     /* 292705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292708 */     // MIs[0] Operand 1
     /* 292708 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 292713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292721 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 292724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292730 */     GIR_RootConstrainSelectedInstOperands,
     /* 292731 */     // GIR_Coverage, 1152,
     /* 292731 */     GIR_EraseRootFromParent_Done,
     /* 292732 */   // Label 5715: @292732
     /* 292732 */   GIM_Try, /*On fail goto*//*Label 5716*/ GIMT_Encode4(292764), // Rule ID 1159 //
     /* 292737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 292740 */     // MIs[0] Operand 1
     /* 292740 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 292745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292749 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292753 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 292756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292762 */     GIR_RootConstrainSelectedInstOperands,
     /* 292763 */     // GIR_Coverage, 1159,
     /* 292763 */     GIR_EraseRootFromParent_Done,
     /* 292764 */   // Label 5716: @292764
     /* 292764 */   GIM_Try, /*On fail goto*//*Label 5717*/ GIMT_Encode4(292793), // Rule ID 5128 //
     /* 292769 */     // MIs[0] Operand 1
     /* 292769 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 292774 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292778 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292782 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64),
     /* 292785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292789 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292791 */     GIR_RootConstrainSelectedInstOperands,
     /* 292792 */     // GIR_Coverage, 5128,
     /* 292792 */     GIR_EraseRootFromParent_Done,
     /* 292793 */   // Label 5717: @292793
     /* 292793 */   GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(292822), // Rule ID 5135 //
     /* 292798 */     // MIs[0] Operand 1
     /* 292798 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 292803 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292807 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292811 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 292814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292820 */     GIR_RootConstrainSelectedInstOperands,
     /* 292821 */     // GIR_Coverage, 5135,
     /* 292821 */     GIR_EraseRootFromParent_Done,
     /* 292822 */   // Label 5718: @292822
     /* 292822 */   GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(292851), // Rule ID 5142 //
     /* 292827 */     // MIs[0] Operand 1
     /* 292827 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 292832 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292836 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292840 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 292843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292847 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292849 */     GIR_RootConstrainSelectedInstOperands,
     /* 292850 */     // GIR_Coverage, 5142,
     /* 292850 */     GIR_EraseRootFromParent_Done,
     /* 292851 */   // Label 5719: @292851
     /* 292851 */   GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(292880), // Rule ID 5149 //
     /* 292856 */     // MIs[0] Operand 1
     /* 292856 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 292861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292865 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292869 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 292872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292874 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292876 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292878 */     GIR_RootConstrainSelectedInstOperands,
     /* 292879 */     // GIR_Coverage, 5149,
     /* 292879 */     GIR_EraseRootFromParent_Done,
     /* 292880 */   // Label 5720: @292880
     /* 292880 */   GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(292909), // Rule ID 5156 //
     /* 292885 */     // MIs[0] Operand 1
     /* 292885 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 292890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292894 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292898 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 292898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 292901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292907 */     GIR_RootConstrainSelectedInstOperands,
     /* 292908 */     // GIR_Coverage, 5156,
     /* 292908 */     GIR_EraseRootFromParent_Done,
     /* 292909 */   // Label 5721: @292909
     /* 292909 */   GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(292938), // Rule ID 5163 //
     /* 292914 */     // MIs[0] Operand 1
     /* 292914 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 292919 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292923 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292927 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 292927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 292930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292932 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292936 */     GIR_RootConstrainSelectedInstOperands,
     /* 292937 */     // GIR_Coverage, 5163,
     /* 292937 */     GIR_EraseRootFromParent_Done,
     /* 292938 */   // Label 5722: @292938
     /* 292938 */   GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(292967), // Rule ID 5170 //
     /* 292943 */     // MIs[0] Operand 1
     /* 292943 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 292948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292952 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292956 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 292956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 292959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292965 */     GIR_RootConstrainSelectedInstOperands,
     /* 292966 */     // GIR_Coverage, 5170,
     /* 292966 */     GIR_EraseRootFromParent_Done,
     /* 292967 */   // Label 5723: @292967
     /* 292967 */   GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(292996), // Rule ID 5177 //
     /* 292972 */     // MIs[0] Operand 1
     /* 292972 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 292977 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292981 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 292985 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 292985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 292988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 292990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 292992 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 292994 */     GIR_RootConstrainSelectedInstOperands,
     /* 292995 */     // GIR_Coverage, 5177,
     /* 292995 */     GIR_EraseRootFromParent_Done,
     /* 292996 */   // Label 5724: @292996
     /* 292996 */   GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(293025), // Rule ID 5184 //
     /* 293001 */     // MIs[0] Operand 1
     /* 293001 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 293006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 293010 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 293014 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 293014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 293017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293021 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293023 */     GIR_RootConstrainSelectedInstOperands,
     /* 293024 */     // GIR_Coverage, 5184,
     /* 293024 */     GIR_EraseRootFromParent_Done,
     /* 293025 */   // Label 5725: @293025
     /* 293025 */   GIM_Reject,
     /* 293026 */ // Label 5695: @293026
     /* 293026 */ GIM_Reject,
     /* 293027 */ // Label 5646: @293027
     /* 293027 */ GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(294074),
     /* 293032 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 293035 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 293038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293042 */   GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(293082), // Rule ID 756 //
     /* 293047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293050 */     // MIs[0] Operand 1
     /* 293050 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293055 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293059 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293065 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293071 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293073 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 293076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293078 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293080 */     GIR_RootConstrainSelectedInstOperands,
     /* 293081 */     // GIR_Coverage, 756,
     /* 293081 */     GIR_EraseRootFromParent_Done,
     /* 293082 */   // Label 5727: @293082
     /* 293082 */   GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(293122), // Rule ID 763 //
     /* 293087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293090 */     // MIs[0] Operand 1
     /* 293090 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293095 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293099 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293105 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293107 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293111 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293113 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 293116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293118 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293120 */     GIR_RootConstrainSelectedInstOperands,
     /* 293121 */     // GIR_Coverage, 763,
     /* 293121 */     GIR_EraseRootFromParent_Done,
     /* 293122 */   // Label 5728: @293122
     /* 293122 */   GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(293159), // Rule ID 5222 //
     /* 293127 */     // MIs[0] Operand 1
     /* 293127 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 293132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293136 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293142 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293144 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293148 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293150 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 293153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293155 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293157 */     GIR_RootConstrainSelectedInstOperands,
     /* 293158 */     // GIR_Coverage, 5222,
     /* 293158 */     GIR_EraseRootFromParent_Done,
     /* 293159 */   // Label 5729: @293159
     /* 293159 */   GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(293196), // Rule ID 5229 //
     /* 293164 */     // MIs[0] Operand 1
     /* 293164 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293173 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293179 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293181 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293185 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293187 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 293190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293194 */     GIR_RootConstrainSelectedInstOperands,
     /* 293195 */     // GIR_Coverage, 5229,
     /* 293195 */     GIR_EraseRootFromParent_Done,
     /* 293196 */   // Label 5730: @293196
     /* 293196 */   GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(293233), // Rule ID 5236 //
     /* 293201 */     // MIs[0] Operand 1
     /* 293201 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293210 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293216 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293218 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293222 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293224 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 293227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293231 */     GIR_RootConstrainSelectedInstOperands,
     /* 293232 */     // GIR_Coverage, 5236,
     /* 293232 */     GIR_EraseRootFromParent_Done,
     /* 293233 */   // Label 5731: @293233
     /* 293233 */   GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(293270), // Rule ID 5243 //
     /* 293238 */     // MIs[0] Operand 1
     /* 293238 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 293243 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293247 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293253 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293255 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293259 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293261 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 293264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293268 */     GIR_RootConstrainSelectedInstOperands,
     /* 293269 */     // GIR_Coverage, 5243,
     /* 293269 */     GIR_EraseRootFromParent_Done,
     /* 293270 */   // Label 5732: @293270
     /* 293270 */   GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(293307), // Rule ID 5250 //
     /* 293275 */     // MIs[0] Operand 1
     /* 293275 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 293280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293284 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293290 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293292 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293298 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 293301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293303 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293305 */     GIR_RootConstrainSelectedInstOperands,
     /* 293306 */     // GIR_Coverage, 5250,
     /* 293306 */     GIR_EraseRootFromParent_Done,
     /* 293307 */   // Label 5733: @293307
     /* 293307 */   GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(293347), // Rule ID 728 //
     /* 293312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293315 */     // MIs[0] Operand 1
     /* 293315 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 293320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293328 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293334 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293336 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293338 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 293341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293345 */     GIR_RootConstrainSelectedInstOperands,
     /* 293346 */     // GIR_Coverage, 728,
     /* 293346 */     GIR_EraseRootFromParent_Done,
     /* 293347 */   // Label 5734: @293347
     /* 293347 */   GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(293387), // Rule ID 737 //
     /* 293352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293355 */     // MIs[0] Operand 1
     /* 293355 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293368 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293374 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293376 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293378 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 293381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293385 */     GIR_RootConstrainSelectedInstOperands,
     /* 293386 */     // GIR_Coverage, 737,
     /* 293386 */     GIR_EraseRootFromParent_Done,
     /* 293387 */   // Label 5735: @293387
     /* 293387 */   GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(293427), // Rule ID 738 //
     /* 293392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293395 */     // MIs[0] Operand 1
     /* 293395 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293400 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293404 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293408 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293414 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 293416 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293418 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 293421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293425 */     GIR_RootConstrainSelectedInstOperands,
     /* 293426 */     // GIR_Coverage, 738,
     /* 293426 */     GIR_EraseRootFromParent_Done,
     /* 293427 */   // Label 5736: @293427
     /* 293427 */   GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(293467), // Rule ID 749 //
     /* 293432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293435 */     // MIs[0] Operand 1
     /* 293435 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293448 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293454 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293456 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293458 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 293461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293465 */     GIR_RootConstrainSelectedInstOperands,
     /* 293466 */     // GIR_Coverage, 749,
     /* 293466 */     GIR_EraseRootFromParent_Done,
     /* 293467 */   // Label 5737: @293467
     /* 293467 */   GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(293504), // Rule ID 5187 //
     /* 293472 */     // MIs[0] Operand 1
     /* 293472 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 293477 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293485 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293491 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293493 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293495 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 293498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293502 */     GIR_RootConstrainSelectedInstOperands,
     /* 293503 */     // GIR_Coverage, 5187,
     /* 293503 */     GIR_EraseRootFromParent_Done,
     /* 293504 */   // Label 5738: @293504
     /* 293504 */   GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(293541), // Rule ID 5194 //
     /* 293509 */     // MIs[0] Operand 1
     /* 293509 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293514 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293518 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293522 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293528 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293530 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293532 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 293535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293539 */     GIR_RootConstrainSelectedInstOperands,
     /* 293540 */     // GIR_Coverage, 5194,
     /* 293540 */     GIR_EraseRootFromParent_Done,
     /* 293541 */   // Label 5739: @293541
     /* 293541 */   GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(293578), // Rule ID 5201 //
     /* 293546 */     // MIs[0] Operand 1
     /* 293546 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293555 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293559 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293565 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293567 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293569 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 293572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293576 */     GIR_RootConstrainSelectedInstOperands,
     /* 293577 */     // GIR_Coverage, 5201,
     /* 293577 */     GIR_EraseRootFromParent_Done,
     /* 293578 */   // Label 5740: @293578
     /* 293578 */   GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(293615), // Rule ID 5208 //
     /* 293583 */     // MIs[0] Operand 1
     /* 293583 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 293588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293596 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293602 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293604 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293606 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 293609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293613 */     GIR_RootConstrainSelectedInstOperands,
     /* 293614 */     // GIR_Coverage, 5208,
     /* 293614 */     GIR_EraseRootFromParent_Done,
     /* 293615 */   // Label 5741: @293615
     /* 293615 */   GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(293652), // Rule ID 5215 //
     /* 293620 */     // MIs[0] Operand 1
     /* 293620 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 293625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 293633 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 293639 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 293641 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293643 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 293643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 293646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293650 */     GIR_RootConstrainSelectedInstOperands,
     /* 293651 */     // GIR_Coverage, 5215,
     /* 293651 */     GIR_EraseRootFromParent_Done,
     /* 293652 */   // Label 5742: @293652
     /* 293652 */   GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(293684), // Rule ID 1127 //
     /* 293657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293660 */     // MIs[0] Operand 1
     /* 293660 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 293665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293673 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16),
     /* 293676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293682 */     GIR_RootConstrainSelectedInstOperands,
     /* 293683 */     // GIR_Coverage, 1127,
     /* 293683 */     GIR_EraseRootFromParent_Done,
     /* 293684 */   // Label 5743: @293684
     /* 293684 */   GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(293716), // Rule ID 1134 //
     /* 293689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293692 */     // MIs[0] Operand 1
     /* 293692 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293701 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293705 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 293708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293712 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293714 */     GIR_RootConstrainSelectedInstOperands,
     /* 293715 */     // GIR_Coverage, 1134,
     /* 293715 */     GIR_EraseRootFromParent_Done,
     /* 293716 */   // Label 5744: @293716
     /* 293716 */   GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(293748), // Rule ID 1141 //
     /* 293721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293724 */     // MIs[0] Operand 1
     /* 293724 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293729 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293733 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293737 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 293740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293746 */     GIR_RootConstrainSelectedInstOperands,
     /* 293747 */     // GIR_Coverage, 1141,
     /* 293747 */     GIR_EraseRootFromParent_Done,
     /* 293748 */   // Label 5745: @293748
     /* 293748 */   GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(293780), // Rule ID 1148 //
     /* 293753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293756 */     // MIs[0] Operand 1
     /* 293756 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 293761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293765 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293769 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 293772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293778 */     GIR_RootConstrainSelectedInstOperands,
     /* 293779 */     // GIR_Coverage, 1148,
     /* 293779 */     GIR_EraseRootFromParent_Done,
     /* 293780 */   // Label 5746: @293780
     /* 293780 */   GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(293812), // Rule ID 1155 //
     /* 293785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 293788 */     // MIs[0] Operand 1
     /* 293788 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 293793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293801 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 293804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293810 */     GIR_RootConstrainSelectedInstOperands,
     /* 293811 */     // GIR_Coverage, 1155,
     /* 293811 */     GIR_EraseRootFromParent_Done,
     /* 293812 */   // Label 5747: @293812
     /* 293812 */   GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(293841), // Rule ID 5124 //
     /* 293817 */     // MIs[0] Operand 1
     /* 293817 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 293822 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293826 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293830 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16),
     /* 293833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293835 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293837 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293839 */     GIR_RootConstrainSelectedInstOperands,
     /* 293840 */     // GIR_Coverage, 5124,
     /* 293840 */     GIR_EraseRootFromParent_Done,
     /* 293841 */   // Label 5748: @293841
     /* 293841 */   GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(293870), // Rule ID 5131 //
     /* 293846 */     // MIs[0] Operand 1
     /* 293846 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 293851 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293855 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293859 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 293862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293866 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293868 */     GIR_RootConstrainSelectedInstOperands,
     /* 293869 */     // GIR_Coverage, 5131,
     /* 293869 */     GIR_EraseRootFromParent_Done,
     /* 293870 */   // Label 5749: @293870
     /* 293870 */   GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(293899), // Rule ID 5138 //
     /* 293875 */     // MIs[0] Operand 1
     /* 293875 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 293880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293884 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293888 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 293891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293893 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293895 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293897 */     GIR_RootConstrainSelectedInstOperands,
     /* 293898 */     // GIR_Coverage, 5138,
     /* 293898 */     GIR_EraseRootFromParent_Done,
     /* 293899 */   // Label 5750: @293899
     /* 293899 */   GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(293928), // Rule ID 5145 //
     /* 293904 */     // MIs[0] Operand 1
     /* 293904 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 293909 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293913 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293917 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 293920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293924 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293926 */     GIR_RootConstrainSelectedInstOperands,
     /* 293927 */     // GIR_Coverage, 5145,
     /* 293927 */     GIR_EraseRootFromParent_Done,
     /* 293928 */   // Label 5751: @293928
     /* 293928 */   GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(293957), // Rule ID 5152 //
     /* 293933 */     // MIs[0] Operand 1
     /* 293933 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 293938 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293942 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293946 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 293946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 293949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293951 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293955 */     GIR_RootConstrainSelectedInstOperands,
     /* 293956 */     // GIR_Coverage, 5152,
     /* 293956 */     GIR_EraseRootFromParent_Done,
     /* 293957 */   // Label 5752: @293957
     /* 293957 */   GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(293986), // Rule ID 5159 //
     /* 293962 */     // MIs[0] Operand 1
     /* 293962 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 293967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293971 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 293975 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 293975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 293978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 293982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 293984 */     GIR_RootConstrainSelectedInstOperands,
     /* 293985 */     // GIR_Coverage, 5159,
     /* 293985 */     GIR_EraseRootFromParent_Done,
     /* 293986 */   // Label 5753: @293986
     /* 293986 */   GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(294015), // Rule ID 5166 //
     /* 293991 */     // MIs[0] Operand 1
     /* 293991 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 293996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294000 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294004 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 294004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 294007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294013 */     GIR_RootConstrainSelectedInstOperands,
     /* 294014 */     // GIR_Coverage, 5166,
     /* 294014 */     GIR_EraseRootFromParent_Done,
     /* 294015 */   // Label 5754: @294015
     /* 294015 */   GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(294044), // Rule ID 5173 //
     /* 294020 */     // MIs[0] Operand 1
     /* 294020 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 294025 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294029 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294033 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 294033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 294036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294040 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294042 */     GIR_RootConstrainSelectedInstOperands,
     /* 294043 */     // GIR_Coverage, 5173,
     /* 294043 */     GIR_EraseRootFromParent_Done,
     /* 294044 */   // Label 5755: @294044
     /* 294044 */   GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(294073), // Rule ID 5180 //
     /* 294049 */     // MIs[0] Operand 1
     /* 294049 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 294054 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294058 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294062 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 294062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 294065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294071 */     GIR_RootConstrainSelectedInstOperands,
     /* 294072 */     // GIR_Coverage, 5180,
     /* 294072 */     GIR_EraseRootFromParent_Done,
     /* 294073 */   // Label 5756: @294073
     /* 294073 */   GIM_Reject,
     /* 294074 */ // Label 5726: @294074
     /* 294074 */ GIM_Reject,
     /* 294075 */ // Label 5647: @294075
     /* 294075 */ GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(295122),
     /* 294080 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 294083 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 294086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294090 */   GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(294130), // Rule ID 759 //
     /* 294095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294098 */     // MIs[0] Operand 1
     /* 294098 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294103 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294107 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294113 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294115 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294119 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294121 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 294124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294128 */     GIR_RootConstrainSelectedInstOperands,
     /* 294129 */     // GIR_Coverage, 759,
     /* 294129 */     GIR_EraseRootFromParent_Done,
     /* 294130 */   // Label 5758: @294130
     /* 294130 */   GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(294170), // Rule ID 766 //
     /* 294135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294138 */     // MIs[0] Operand 1
     /* 294138 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294147 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294153 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294155 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294159 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294161 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 294164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294168 */     GIR_RootConstrainSelectedInstOperands,
     /* 294169 */     // GIR_Coverage, 766,
     /* 294169 */     GIR_EraseRootFromParent_Done,
     /* 294170 */   // Label 5759: @294170
     /* 294170 */   GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(294207), // Rule ID 5225 //
     /* 294175 */     // MIs[0] Operand 1
     /* 294175 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 294180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294184 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294190 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294192 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294196 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294198 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 294201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294203 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294205 */     GIR_RootConstrainSelectedInstOperands,
     /* 294206 */     // GIR_Coverage, 5225,
     /* 294206 */     GIR_EraseRootFromParent_Done,
     /* 294207 */   // Label 5760: @294207
     /* 294207 */   GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(294244), // Rule ID 5232 //
     /* 294212 */     // MIs[0] Operand 1
     /* 294212 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294217 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294221 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294227 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294233 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294235 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 294238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294242 */     GIR_RootConstrainSelectedInstOperands,
     /* 294243 */     // GIR_Coverage, 5232,
     /* 294243 */     GIR_EraseRootFromParent_Done,
     /* 294244 */   // Label 5761: @294244
     /* 294244 */   GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(294281), // Rule ID 5239 //
     /* 294249 */     // MIs[0] Operand 1
     /* 294249 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294258 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294264 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294266 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294270 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294272 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 294275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294279 */     GIR_RootConstrainSelectedInstOperands,
     /* 294280 */     // GIR_Coverage, 5239,
     /* 294280 */     GIR_EraseRootFromParent_Done,
     /* 294281 */   // Label 5762: @294281
     /* 294281 */   GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(294318), // Rule ID 5246 //
     /* 294286 */     // MIs[0] Operand 1
     /* 294286 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 294291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294295 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294301 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294307 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294309 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 294312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294316 */     GIR_RootConstrainSelectedInstOperands,
     /* 294317 */     // GIR_Coverage, 5246,
     /* 294317 */     GIR_EraseRootFromParent_Done,
     /* 294318 */   // Label 5763: @294318
     /* 294318 */   GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(294355), // Rule ID 5253 //
     /* 294323 */     // MIs[0] Operand 1
     /* 294323 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 294328 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 294332 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294338 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294340 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294344 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294346 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 294349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294351 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 294353 */     GIR_RootConstrainSelectedInstOperands,
     /* 294354 */     // GIR_Coverage, 5253,
     /* 294354 */     GIR_EraseRootFromParent_Done,
     /* 294355 */   // Label 5764: @294355
     /* 294355 */   GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(294395), // Rule ID 731 //
     /* 294360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294363 */     // MIs[0] Operand 1
     /* 294363 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 294368 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294376 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294382 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294384 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294386 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 294389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294391 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294393 */     GIR_RootConstrainSelectedInstOperands,
     /* 294394 */     // GIR_Coverage, 731,
     /* 294394 */     GIR_EraseRootFromParent_Done,
     /* 294395 */   // Label 5765: @294395
     /* 294395 */   GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(294435), // Rule ID 743 //
     /* 294400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294403 */     // MIs[0] Operand 1
     /* 294403 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294412 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294416 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294422 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294424 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294426 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 294429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294431 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294433 */     GIR_RootConstrainSelectedInstOperands,
     /* 294434 */     // GIR_Coverage, 743,
     /* 294434 */     GIR_EraseRootFromParent_Done,
     /* 294435 */   // Label 5766: @294435
     /* 294435 */   GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(294475), // Rule ID 744 //
     /* 294440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294443 */     // MIs[0] Operand 1
     /* 294443 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294448 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294456 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294462 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 294464 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294466 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 294469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294473 */     GIR_RootConstrainSelectedInstOperands,
     /* 294474 */     // GIR_Coverage, 744,
     /* 294474 */     GIR_EraseRootFromParent_Done,
     /* 294475 */   // Label 5767: @294475
     /* 294475 */   GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(294515), // Rule ID 752 //
     /* 294480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294483 */     // MIs[0] Operand 1
     /* 294483 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294492 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294496 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294502 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294504 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294506 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 294509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294513 */     GIR_RootConstrainSelectedInstOperands,
     /* 294514 */     // GIR_Coverage, 752,
     /* 294514 */     GIR_EraseRootFromParent_Done,
     /* 294515 */   // Label 5768: @294515
     /* 294515 */   GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(294552), // Rule ID 5190 //
     /* 294520 */     // MIs[0] Operand 1
     /* 294520 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 294525 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294533 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294539 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294541 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294543 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 294546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294550 */     GIR_RootConstrainSelectedInstOperands,
     /* 294551 */     // GIR_Coverage, 5190,
     /* 294551 */     GIR_EraseRootFromParent_Done,
     /* 294552 */   // Label 5769: @294552
     /* 294552 */   GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(294589), // Rule ID 5197 //
     /* 294557 */     // MIs[0] Operand 1
     /* 294557 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294570 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294576 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294578 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294580 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 294583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294587 */     GIR_RootConstrainSelectedInstOperands,
     /* 294588 */     // GIR_Coverage, 5197,
     /* 294588 */     GIR_EraseRootFromParent_Done,
     /* 294589 */   // Label 5770: @294589
     /* 294589 */   GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(294626), // Rule ID 5204 //
     /* 294594 */     // MIs[0] Operand 1
     /* 294594 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294607 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294613 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294617 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 294620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294624 */     GIR_RootConstrainSelectedInstOperands,
     /* 294625 */     // GIR_Coverage, 5204,
     /* 294625 */     GIR_EraseRootFromParent_Done,
     /* 294626 */   // Label 5771: @294626
     /* 294626 */   GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(294663), // Rule ID 5211 //
     /* 294631 */     // MIs[0] Operand 1
     /* 294631 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 294636 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294644 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294650 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294652 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294654 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 294657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294659 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294661 */     GIR_RootConstrainSelectedInstOperands,
     /* 294662 */     // GIR_Coverage, 5211,
     /* 294662 */     GIR_EraseRootFromParent_Done,
     /* 294663 */   // Label 5772: @294663
     /* 294663 */   GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(294700), // Rule ID 5218 //
     /* 294668 */     // MIs[0] Operand 1
     /* 294668 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 294673 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294677 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294681 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 294687 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 294689 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294691 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 294691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 294694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294698 */     GIR_RootConstrainSelectedInstOperands,
     /* 294699 */     // GIR_Coverage, 5218,
     /* 294699 */     GIR_EraseRootFromParent_Done,
     /* 294700 */   // Label 5773: @294700
     /* 294700 */   GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(294732), // Rule ID 1130 //
     /* 294705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294708 */     // MIs[0] Operand 1
     /* 294708 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 294713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294721 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32),
     /* 294724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294730 */     GIR_RootConstrainSelectedInstOperands,
     /* 294731 */     // GIR_Coverage, 1130,
     /* 294731 */     GIR_EraseRootFromParent_Done,
     /* 294732 */   // Label 5774: @294732
     /* 294732 */   GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(294764), // Rule ID 1137 //
     /* 294737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294740 */     // MIs[0] Operand 1
     /* 294740 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294749 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294753 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 294756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294762 */     GIR_RootConstrainSelectedInstOperands,
     /* 294763 */     // GIR_Coverage, 1137,
     /* 294763 */     GIR_EraseRootFromParent_Done,
     /* 294764 */   // Label 5775: @294764
     /* 294764 */   GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(294796), // Rule ID 1144 //
     /* 294769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294772 */     // MIs[0] Operand 1
     /* 294772 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294781 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294785 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 294788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294790 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294792 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294794 */     GIR_RootConstrainSelectedInstOperands,
     /* 294795 */     // GIR_Coverage, 1144,
     /* 294795 */     GIR_EraseRootFromParent_Done,
     /* 294796 */   // Label 5776: @294796
     /* 294796 */   GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(294828), // Rule ID 1151 //
     /* 294801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294804 */     // MIs[0] Operand 1
     /* 294804 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 294809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294817 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 294820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294826 */     GIR_RootConstrainSelectedInstOperands,
     /* 294827 */     // GIR_Coverage, 1151,
     /* 294827 */     GIR_EraseRootFromParent_Done,
     /* 294828 */   // Label 5777: @294828
     /* 294828 */   GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(294860), // Rule ID 1158 //
     /* 294833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 294836 */     // MIs[0] Operand 1
     /* 294836 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 294841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294845 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294849 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 294852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294858 */     GIR_RootConstrainSelectedInstOperands,
     /* 294859 */     // GIR_Coverage, 1158,
     /* 294859 */     GIR_EraseRootFromParent_Done,
     /* 294860 */   // Label 5778: @294860
     /* 294860 */   GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(294889), // Rule ID 5127 //
     /* 294865 */     // MIs[0] Operand 1
     /* 294865 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 294870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294878 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32),
     /* 294881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294887 */     GIR_RootConstrainSelectedInstOperands,
     /* 294888 */     // GIR_Coverage, 5127,
     /* 294888 */     GIR_EraseRootFromParent_Done,
     /* 294889 */   // Label 5779: @294889
     /* 294889 */   GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(294918), // Rule ID 5134 //
     /* 294894 */     // MIs[0] Operand 1
     /* 294894 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 294899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294903 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294907 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 294910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294916 */     GIR_RootConstrainSelectedInstOperands,
     /* 294917 */     // GIR_Coverage, 5134,
     /* 294917 */     GIR_EraseRootFromParent_Done,
     /* 294918 */   // Label 5780: @294918
     /* 294918 */   GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(294947), // Rule ID 5141 //
     /* 294923 */     // MIs[0] Operand 1
     /* 294923 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 294928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294932 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294936 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 294939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294945 */     GIR_RootConstrainSelectedInstOperands,
     /* 294946 */     // GIR_Coverage, 5141,
     /* 294946 */     GIR_EraseRootFromParent_Done,
     /* 294947 */   // Label 5781: @294947
     /* 294947 */   GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(294976), // Rule ID 5148 //
     /* 294952 */     // MIs[0] Operand 1
     /* 294952 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 294957 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294961 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294965 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 294968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294970 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294972 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294974 */     GIR_RootConstrainSelectedInstOperands,
     /* 294975 */     // GIR_Coverage, 5148,
     /* 294975 */     GIR_EraseRootFromParent_Done,
     /* 294976 */   // Label 5782: @294976
     /* 294976 */   GIM_Try, /*On fail goto*//*Label 5783*/ GIMT_Encode4(295005), // Rule ID 5155 //
     /* 294981 */     // MIs[0] Operand 1
     /* 294981 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 294986 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294990 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294994 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 294994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 294997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295001 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295003 */     GIR_RootConstrainSelectedInstOperands,
     /* 295004 */     // GIR_Coverage, 5155,
     /* 295004 */     GIR_EraseRootFromParent_Done,
     /* 295005 */   // Label 5783: @295005
     /* 295005 */   GIM_Try, /*On fail goto*//*Label 5784*/ GIMT_Encode4(295034), // Rule ID 5162 //
     /* 295010 */     // MIs[0] Operand 1
     /* 295010 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 295015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295019 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295023 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 295023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 295026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295032 */     GIR_RootConstrainSelectedInstOperands,
     /* 295033 */     // GIR_Coverage, 5162,
     /* 295033 */     GIR_EraseRootFromParent_Done,
     /* 295034 */   // Label 5784: @295034
     /* 295034 */   GIM_Try, /*On fail goto*//*Label 5785*/ GIMT_Encode4(295063), // Rule ID 5169 //
     /* 295039 */     // MIs[0] Operand 1
     /* 295039 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 295044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295048 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295052 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 295052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 295055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295057 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295061 */     GIR_RootConstrainSelectedInstOperands,
     /* 295062 */     // GIR_Coverage, 5169,
     /* 295062 */     GIR_EraseRootFromParent_Done,
     /* 295063 */   // Label 5785: @295063
     /* 295063 */   GIM_Try, /*On fail goto*//*Label 5786*/ GIMT_Encode4(295092), // Rule ID 5176 //
     /* 295068 */     // MIs[0] Operand 1
     /* 295068 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 295073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295077 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295081 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 295081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 295084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295086 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295090 */     GIR_RootConstrainSelectedInstOperands,
     /* 295091 */     // GIR_Coverage, 5176,
     /* 295091 */     GIR_EraseRootFromParent_Done,
     /* 295092 */   // Label 5786: @295092
     /* 295092 */   GIM_Try, /*On fail goto*//*Label 5787*/ GIMT_Encode4(295121), // Rule ID 5183 //
     /* 295097 */     // MIs[0] Operand 1
     /* 295097 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 295102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295106 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 295110 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 295110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 295113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295115 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295119 */     GIR_RootConstrainSelectedInstOperands,
     /* 295120 */     // GIR_Coverage, 5183,
     /* 295120 */     GIR_EraseRootFromParent_Done,
     /* 295121 */   // Label 5787: @295121
     /* 295121 */   GIM_Reject,
     /* 295122 */ // Label 5757: @295122
     /* 295122 */ GIM_Reject,
     /* 295123 */ // Label 5648: @295123
     /* 295123 */ GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(296170),
     /* 295128 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 295131 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 295134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295138 */   GIM_Try, /*On fail goto*//*Label 5789*/ GIMT_Encode4(295178), // Rule ID 754 //
     /* 295143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295146 */     // MIs[0] Operand 1
     /* 295146 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295151 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295155 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295161 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295163 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295167 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295169 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 295172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295176 */     GIR_RootConstrainSelectedInstOperands,
     /* 295177 */     // GIR_Coverage, 754,
     /* 295177 */     GIR_EraseRootFromParent_Done,
     /* 295178 */   // Label 5789: @295178
     /* 295178 */   GIM_Try, /*On fail goto*//*Label 5790*/ GIMT_Encode4(295218), // Rule ID 761 //
     /* 295183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295186 */     // MIs[0] Operand 1
     /* 295186 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295191 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295195 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295201 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295203 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295209 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 295212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295214 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295216 */     GIR_RootConstrainSelectedInstOperands,
     /* 295217 */     // GIR_Coverage, 761,
     /* 295217 */     GIR_EraseRootFromParent_Done,
     /* 295218 */   // Label 5790: @295218
     /* 295218 */   GIM_Try, /*On fail goto*//*Label 5791*/ GIMT_Encode4(295255), // Rule ID 5220 //
     /* 295223 */     // MIs[0] Operand 1
     /* 295223 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 295228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295232 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295238 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295240 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295244 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295246 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 295249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295253 */     GIR_RootConstrainSelectedInstOperands,
     /* 295254 */     // GIR_Coverage, 5220,
     /* 295254 */     GIR_EraseRootFromParent_Done,
     /* 295255 */   // Label 5791: @295255
     /* 295255 */   GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(295292), // Rule ID 5227 //
     /* 295260 */     // MIs[0] Operand 1
     /* 295260 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295269 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295275 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295277 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295281 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295283 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 295286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295288 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295290 */     GIR_RootConstrainSelectedInstOperands,
     /* 295291 */     // GIR_Coverage, 5227,
     /* 295291 */     GIR_EraseRootFromParent_Done,
     /* 295292 */   // Label 5792: @295292
     /* 295292 */   GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(295329), // Rule ID 5234 //
     /* 295297 */     // MIs[0] Operand 1
     /* 295297 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295302 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295306 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295312 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295314 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295318 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295320 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 295323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295327 */     GIR_RootConstrainSelectedInstOperands,
     /* 295328 */     // GIR_Coverage, 5234,
     /* 295328 */     GIR_EraseRootFromParent_Done,
     /* 295329 */   // Label 5793: @295329
     /* 295329 */   GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(295366), // Rule ID 5241 //
     /* 295334 */     // MIs[0] Operand 1
     /* 295334 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 295339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295343 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295349 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295351 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295355 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295357 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 295360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295364 */     GIR_RootConstrainSelectedInstOperands,
     /* 295365 */     // GIR_Coverage, 5241,
     /* 295365 */     GIR_EraseRootFromParent_Done,
     /* 295366 */   // Label 5794: @295366
     /* 295366 */   GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(295403), // Rule ID 5248 //
     /* 295371 */     // MIs[0] Operand 1
     /* 295371 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 295376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 295380 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295386 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295388 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295392 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295394 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 295397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 295401 */     GIR_RootConstrainSelectedInstOperands,
     /* 295402 */     // GIR_Coverage, 5248,
     /* 295402 */     GIR_EraseRootFromParent_Done,
     /* 295403 */   // Label 5795: @295403
     /* 295403 */   GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(295443), // Rule ID 726 //
     /* 295408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295411 */     // MIs[0] Operand 1
     /* 295411 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 295416 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295424 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295430 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295432 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295434 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 295437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295441 */     GIR_RootConstrainSelectedInstOperands,
     /* 295442 */     // GIR_Coverage, 726,
     /* 295442 */     GIR_EraseRootFromParent_Done,
     /* 295443 */   // Label 5796: @295443
     /* 295443 */   GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(295483), // Rule ID 733 //
     /* 295448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295451 */     // MIs[0] Operand 1
     /* 295451 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295464 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295470 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295472 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295474 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 295477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295481 */     GIR_RootConstrainSelectedInstOperands,
     /* 295482 */     // GIR_Coverage, 733,
     /* 295482 */     GIR_EraseRootFromParent_Done,
     /* 295483 */   // Label 5797: @295483
     /* 295483 */   GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(295523), // Rule ID 734 //
     /* 295488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295491 */     // MIs[0] Operand 1
     /* 295491 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295496 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295500 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295504 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295510 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 295512 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295514 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 295517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295519 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295521 */     GIR_RootConstrainSelectedInstOperands,
     /* 295522 */     // GIR_Coverage, 734,
     /* 295522 */     GIR_EraseRootFromParent_Done,
     /* 295523 */   // Label 5798: @295523
     /* 295523 */   GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(295563), // Rule ID 747 //
     /* 295528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295531 */     // MIs[0] Operand 1
     /* 295531 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295540 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295544 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295550 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295554 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 295557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295561 */     GIR_RootConstrainSelectedInstOperands,
     /* 295562 */     // GIR_Coverage, 747,
     /* 295562 */     GIR_EraseRootFromParent_Done,
     /* 295563 */   // Label 5799: @295563
     /* 295563 */   GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(295600), // Rule ID 5185 //
     /* 295568 */     // MIs[0] Operand 1
     /* 295568 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 295573 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295581 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295587 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295589 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295591 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 295594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295596 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295598 */     GIR_RootConstrainSelectedInstOperands,
     /* 295599 */     // GIR_Coverage, 5185,
     /* 295599 */     GIR_EraseRootFromParent_Done,
     /* 295600 */   // Label 5800: @295600
     /* 295600 */   GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(295637), // Rule ID 5192 //
     /* 295605 */     // MIs[0] Operand 1
     /* 295605 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295614 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295618 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295624 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295626 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295628 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 295631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295635 */     GIR_RootConstrainSelectedInstOperands,
     /* 295636 */     // GIR_Coverage, 5192,
     /* 295636 */     GIR_EraseRootFromParent_Done,
     /* 295637 */   // Label 5801: @295637
     /* 295637 */   GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(295674), // Rule ID 5199 //
     /* 295642 */     // MIs[0] Operand 1
     /* 295642 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295647 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295655 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295661 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295663 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295665 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 295668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295672 */     GIR_RootConstrainSelectedInstOperands,
     /* 295673 */     // GIR_Coverage, 5199,
     /* 295673 */     GIR_EraseRootFromParent_Done,
     /* 295674 */   // Label 5802: @295674
     /* 295674 */   GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(295711), // Rule ID 5206 //
     /* 295679 */     // MIs[0] Operand 1
     /* 295679 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 295684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295692 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295698 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295700 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295702 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 295705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295709 */     GIR_RootConstrainSelectedInstOperands,
     /* 295710 */     // GIR_Coverage, 5206,
     /* 295710 */     GIR_EraseRootFromParent_Done,
     /* 295711 */   // Label 5803: @295711
     /* 295711 */   GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(295748), // Rule ID 5213 //
     /* 295716 */     // MIs[0] Operand 1
     /* 295716 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 295721 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295725 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 295729 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 295735 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 295737 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 295739 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 295739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 295742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295746 */     GIR_RootConstrainSelectedInstOperands,
     /* 295747 */     // GIR_Coverage, 5213,
     /* 295747 */     GIR_EraseRootFromParent_Done,
     /* 295748 */   // Label 5804: @295748
     /* 295748 */   GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(295780), // Rule ID 1125 //
     /* 295753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295756 */     // MIs[0] Operand 1
     /* 295756 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 295761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295765 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295769 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8),
     /* 295772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295778 */     GIR_RootConstrainSelectedInstOperands,
     /* 295779 */     // GIR_Coverage, 1125,
     /* 295779 */     GIR_EraseRootFromParent_Done,
     /* 295780 */   // Label 5805: @295780
     /* 295780 */   GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(295812), // Rule ID 1132 //
     /* 295785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295788 */     // MIs[0] Operand 1
     /* 295788 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295801 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 295804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295806 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295810 */     GIR_RootConstrainSelectedInstOperands,
     /* 295811 */     // GIR_Coverage, 1132,
     /* 295811 */     GIR_EraseRootFromParent_Done,
     /* 295812 */   // Label 5806: @295812
     /* 295812 */   GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(295844), // Rule ID 1139 //
     /* 295817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295820 */     // MIs[0] Operand 1
     /* 295820 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295825 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295829 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295833 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 295836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295842 */     GIR_RootConstrainSelectedInstOperands,
     /* 295843 */     // GIR_Coverage, 1139,
     /* 295843 */     GIR_EraseRootFromParent_Done,
     /* 295844 */   // Label 5807: @295844
     /* 295844 */   GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(295876), // Rule ID 1146 //
     /* 295849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295852 */     // MIs[0] Operand 1
     /* 295852 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 295857 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295861 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295865 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 295868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295874 */     GIR_RootConstrainSelectedInstOperands,
     /* 295875 */     // GIR_Coverage, 1146,
     /* 295875 */     GIR_EraseRootFromParent_Done,
     /* 295876 */   // Label 5808: @295876
     /* 295876 */   GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(295908), // Rule ID 1153 //
     /* 295881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 295884 */     // MIs[0] Operand 1
     /* 295884 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 295889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295893 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295897 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 295900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295906 */     GIR_RootConstrainSelectedInstOperands,
     /* 295907 */     // GIR_Coverage, 1153,
     /* 295907 */     GIR_EraseRootFromParent_Done,
     /* 295908 */   // Label 5809: @295908
     /* 295908 */   GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(295937), // Rule ID 5122 //
     /* 295913 */     // MIs[0] Operand 1
     /* 295913 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 295918 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295922 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295926 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8),
     /* 295929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295933 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295935 */     GIR_RootConstrainSelectedInstOperands,
     /* 295936 */     // GIR_Coverage, 5122,
     /* 295936 */     GIR_EraseRootFromParent_Done,
     /* 295937 */   // Label 5810: @295937
     /* 295937 */   GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(295966), // Rule ID 5129 //
     /* 295942 */     // MIs[0] Operand 1
     /* 295942 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 295947 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295951 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295955 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 295958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295964 */     GIR_RootConstrainSelectedInstOperands,
     /* 295965 */     // GIR_Coverage, 5129,
     /* 295965 */     GIR_EraseRootFromParent_Done,
     /* 295966 */   // Label 5811: @295966
     /* 295966 */   GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(295995), // Rule ID 5136 //
     /* 295971 */     // MIs[0] Operand 1
     /* 295971 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 295976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295980 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 295984 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 295984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 295987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 295989 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 295993 */     GIR_RootConstrainSelectedInstOperands,
     /* 295994 */     // GIR_Coverage, 5136,
     /* 295994 */     GIR_EraseRootFromParent_Done,
     /* 295995 */   // Label 5812: @295995
     /* 295995 */   GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(296024), // Rule ID 5143 //
     /* 296000 */     // MIs[0] Operand 1
     /* 296000 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 296005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296009 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296013 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 296013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 296016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296022 */     GIR_RootConstrainSelectedInstOperands,
     /* 296023 */     // GIR_Coverage, 5143,
     /* 296023 */     GIR_EraseRootFromParent_Done,
     /* 296024 */   // Label 5813: @296024
     /* 296024 */   GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(296053), // Rule ID 5150 //
     /* 296029 */     // MIs[0] Operand 1
     /* 296029 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 296034 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296038 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296042 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 296042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 296045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296047 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296049 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296051 */     GIR_RootConstrainSelectedInstOperands,
     /* 296052 */     // GIR_Coverage, 5150,
     /* 296052 */     GIR_EraseRootFromParent_Done,
     /* 296053 */   // Label 5814: @296053
     /* 296053 */   GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(296082), // Rule ID 5157 //
     /* 296058 */     // MIs[0] Operand 1
     /* 296058 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 296063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296071 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 296071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 296074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296076 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296080 */     GIR_RootConstrainSelectedInstOperands,
     /* 296081 */     // GIR_Coverage, 5157,
     /* 296081 */     GIR_EraseRootFromParent_Done,
     /* 296082 */   // Label 5815: @296082
     /* 296082 */   GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(296111), // Rule ID 5164 //
     /* 296087 */     // MIs[0] Operand 1
     /* 296087 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 296092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296100 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 296100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 296103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296105 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296109 */     GIR_RootConstrainSelectedInstOperands,
     /* 296110 */     // GIR_Coverage, 5164,
     /* 296110 */     GIR_EraseRootFromParent_Done,
     /* 296111 */   // Label 5816: @296111
     /* 296111 */   GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(296140), // Rule ID 5171 //
     /* 296116 */     // MIs[0] Operand 1
     /* 296116 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 296121 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296125 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296129 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 296129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 296132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296138 */     GIR_RootConstrainSelectedInstOperands,
     /* 296139 */     // GIR_Coverage, 5171,
     /* 296139 */     GIR_EraseRootFromParent_Done,
     /* 296140 */   // Label 5817: @296140
     /* 296140 */   GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(296169), // Rule ID 5178 //
     /* 296145 */     // MIs[0] Operand 1
     /* 296145 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 296150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296158 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 296158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 296161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296167 */     GIR_RootConstrainSelectedInstOperands,
     /* 296168 */     // GIR_Coverage, 5178,
     /* 296168 */     GIR_EraseRootFromParent_Done,
     /* 296169 */   // Label 5818: @296169
     /* 296169 */   GIM_Reject,
     /* 296170 */ // Label 5788: @296170
     /* 296170 */ GIM_Reject,
     /* 296171 */ // Label 5649: @296171
     /* 296171 */ GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(297218),
     /* 296176 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 296179 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 296182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296186 */   GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(296226), // Rule ID 757 //
     /* 296191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296194 */     // MIs[0] Operand 1
     /* 296194 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 296199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296203 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296209 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296211 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296215 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296217 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 296220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296222 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296224 */     GIR_RootConstrainSelectedInstOperands,
     /* 296225 */     // GIR_Coverage, 757,
     /* 296225 */     GIR_EraseRootFromParent_Done,
     /* 296226 */   // Label 5820: @296226
     /* 296226 */   GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(296266), // Rule ID 764 //
     /* 296231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296234 */     // MIs[0] Operand 1
     /* 296234 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296243 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296249 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296251 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296255 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296257 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 296260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296262 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296264 */     GIR_RootConstrainSelectedInstOperands,
     /* 296265 */     // GIR_Coverage, 764,
     /* 296265 */     GIR_EraseRootFromParent_Done,
     /* 296266 */   // Label 5821: @296266
     /* 296266 */   GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(296303), // Rule ID 5223 //
     /* 296271 */     // MIs[0] Operand 1
     /* 296271 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 296276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296280 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296286 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296294 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 296297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296301 */     GIR_RootConstrainSelectedInstOperands,
     /* 296302 */     // GIR_Coverage, 5223,
     /* 296302 */     GIR_EraseRootFromParent_Done,
     /* 296303 */   // Label 5822: @296303
     /* 296303 */   GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(296340), // Rule ID 5230 //
     /* 296308 */     // MIs[0] Operand 1
     /* 296308 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296317 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296323 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296329 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296331 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 296334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296338 */     GIR_RootConstrainSelectedInstOperands,
     /* 296339 */     // GIR_Coverage, 5230,
     /* 296339 */     GIR_EraseRootFromParent_Done,
     /* 296340 */   // Label 5823: @296340
     /* 296340 */   GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(296377), // Rule ID 5237 //
     /* 296345 */     // MIs[0] Operand 1
     /* 296345 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 296350 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296354 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296360 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296362 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296366 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296368 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 296371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296375 */     GIR_RootConstrainSelectedInstOperands,
     /* 296376 */     // GIR_Coverage, 5237,
     /* 296376 */     GIR_EraseRootFromParent_Done,
     /* 296377 */   // Label 5824: @296377
     /* 296377 */   GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(296414), // Rule ID 5244 //
     /* 296382 */     // MIs[0] Operand 1
     /* 296382 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 296387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296391 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296397 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296399 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296403 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296405 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 296408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296412 */     GIR_RootConstrainSelectedInstOperands,
     /* 296413 */     // GIR_Coverage, 5244,
     /* 296413 */     GIR_EraseRootFromParent_Done,
     /* 296414 */   // Label 5825: @296414
     /* 296414 */   GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(296451), // Rule ID 5251 //
     /* 296419 */     // MIs[0] Operand 1
     /* 296419 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 296424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 296428 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296434 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296436 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296440 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296442 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 296445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296447 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296449 */     GIR_RootConstrainSelectedInstOperands,
     /* 296450 */     // GIR_Coverage, 5251,
     /* 296450 */     GIR_EraseRootFromParent_Done,
     /* 296451 */   // Label 5826: @296451
     /* 296451 */   GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(296491), // Rule ID 729 //
     /* 296456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296459 */     // MIs[0] Operand 1
     /* 296459 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 296464 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296468 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296472 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296478 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296480 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296482 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 296485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296489 */     GIR_RootConstrainSelectedInstOperands,
     /* 296490 */     // GIR_Coverage, 729,
     /* 296490 */     GIR_EraseRootFromParent_Done,
     /* 296491 */   // Label 5827: @296491
     /* 296491 */   GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(296531), // Rule ID 739 //
     /* 296496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296499 */     // MIs[0] Operand 1
     /* 296499 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 296504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296508 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296512 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296518 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296520 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296522 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 296525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296527 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296529 */     GIR_RootConstrainSelectedInstOperands,
     /* 296530 */     // GIR_Coverage, 739,
     /* 296530 */     GIR_EraseRootFromParent_Done,
     /* 296531 */   // Label 5828: @296531
     /* 296531 */   GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(296571), // Rule ID 740 //
     /* 296536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296539 */     // MIs[0] Operand 1
     /* 296539 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296548 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296552 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296558 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 296560 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296562 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 296565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296569 */     GIR_RootConstrainSelectedInstOperands,
     /* 296570 */     // GIR_Coverage, 740,
     /* 296570 */     GIR_EraseRootFromParent_Done,
     /* 296571 */   // Label 5829: @296571
     /* 296571 */   GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(296611), // Rule ID 750 //
     /* 296576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296579 */     // MIs[0] Operand 1
     /* 296579 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296592 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296598 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296600 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296602 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 296605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296607 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296609 */     GIR_RootConstrainSelectedInstOperands,
     /* 296610 */     // GIR_Coverage, 750,
     /* 296610 */     GIR_EraseRootFromParent_Done,
     /* 296611 */   // Label 5830: @296611
     /* 296611 */   GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(296648), // Rule ID 5188 //
     /* 296616 */     // MIs[0] Operand 1
     /* 296616 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 296621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296629 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296635 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296637 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296639 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 296642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296646 */     GIR_RootConstrainSelectedInstOperands,
     /* 296647 */     // GIR_Coverage, 5188,
     /* 296647 */     GIR_EraseRootFromParent_Done,
     /* 296648 */   // Label 5831: @296648
     /* 296648 */   GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(296685), // Rule ID 5195 //
     /* 296653 */     // MIs[0] Operand 1
     /* 296653 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296666 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296672 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296674 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296676 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 296679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296683 */     GIR_RootConstrainSelectedInstOperands,
     /* 296684 */     // GIR_Coverage, 5195,
     /* 296684 */     GIR_EraseRootFromParent_Done,
     /* 296685 */   // Label 5832: @296685
     /* 296685 */   GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(296722), // Rule ID 5202 //
     /* 296690 */     // MIs[0] Operand 1
     /* 296690 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 296695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296703 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296709 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296711 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296713 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 296716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296720 */     GIR_RootConstrainSelectedInstOperands,
     /* 296721 */     // GIR_Coverage, 5202,
     /* 296721 */     GIR_EraseRootFromParent_Done,
     /* 296722 */   // Label 5833: @296722
     /* 296722 */   GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(296759), // Rule ID 5209 //
     /* 296727 */     // MIs[0] Operand 1
     /* 296727 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 296732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296736 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296740 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296746 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296748 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296750 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 296753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296757 */     GIR_RootConstrainSelectedInstOperands,
     /* 296758 */     // GIR_Coverage, 5209,
     /* 296758 */     GIR_EraseRootFromParent_Done,
     /* 296759 */   // Label 5834: @296759
     /* 296759 */   GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(296796), // Rule ID 5216 //
     /* 296764 */     // MIs[0] Operand 1
     /* 296764 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 296769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 296777 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 296783 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 296785 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 296787 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 296787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 296790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296794 */     GIR_RootConstrainSelectedInstOperands,
     /* 296795 */     // GIR_Coverage, 5216,
     /* 296795 */     GIR_EraseRootFromParent_Done,
     /* 296796 */   // Label 5835: @296796
     /* 296796 */   GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(296828), // Rule ID 1128 //
     /* 296801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296804 */     // MIs[0] Operand 1
     /* 296804 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 296809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296817 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16),
     /* 296820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296826 */     GIR_RootConstrainSelectedInstOperands,
     /* 296827 */     // GIR_Coverage, 1128,
     /* 296827 */     GIR_EraseRootFromParent_Done,
     /* 296828 */   // Label 5836: @296828
     /* 296828 */   GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(296860), // Rule ID 1135 //
     /* 296833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296836 */     // MIs[0] Operand 1
     /* 296836 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 296841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296845 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296849 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 296852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296858 */     GIR_RootConstrainSelectedInstOperands,
     /* 296859 */     // GIR_Coverage, 1135,
     /* 296859 */     GIR_EraseRootFromParent_Done,
     /* 296860 */   // Label 5837: @296860
     /* 296860 */   GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(296892), // Rule ID 1142 //
     /* 296865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296868 */     // MIs[0] Operand 1
     /* 296868 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296873 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296877 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296881 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 296884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296890 */     GIR_RootConstrainSelectedInstOperands,
     /* 296891 */     // GIR_Coverage, 1142,
     /* 296891 */     GIR_EraseRootFromParent_Done,
     /* 296892 */   // Label 5838: @296892
     /* 296892 */   GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(296924), // Rule ID 1149 //
     /* 296897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296900 */     // MIs[0] Operand 1
     /* 296900 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 296905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296909 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296913 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 296916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296922 */     GIR_RootConstrainSelectedInstOperands,
     /* 296923 */     // GIR_Coverage, 1149,
     /* 296923 */     GIR_EraseRootFromParent_Done,
     /* 296924 */   // Label 5839: @296924
     /* 296924 */   GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(296956), // Rule ID 1156 //
     /* 296929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 296932 */     // MIs[0] Operand 1
     /* 296932 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 296937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296941 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296945 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 296948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296950 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296952 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296954 */     GIR_RootConstrainSelectedInstOperands,
     /* 296955 */     // GIR_Coverage, 1156,
     /* 296955 */     GIR_EraseRootFromParent_Done,
     /* 296956 */   // Label 5840: @296956
     /* 296956 */   GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(296985), // Rule ID 5125 //
     /* 296961 */     // MIs[0] Operand 1
     /* 296961 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 296966 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296970 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296974 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 296974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16),
     /* 296977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 296979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296981 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 296983 */     GIR_RootConstrainSelectedInstOperands,
     /* 296984 */     // GIR_Coverage, 5125,
     /* 296984 */     GIR_EraseRootFromParent_Done,
     /* 296985 */   // Label 5841: @296985
     /* 296985 */   GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(297014), // Rule ID 5132 //
     /* 296990 */     // MIs[0] Operand 1
     /* 296990 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 296995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296999 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297003 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 297003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 297006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297008 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297010 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297012 */     GIR_RootConstrainSelectedInstOperands,
     /* 297013 */     // GIR_Coverage, 5132,
     /* 297013 */     GIR_EraseRootFromParent_Done,
     /* 297014 */   // Label 5842: @297014
     /* 297014 */   GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(297043), // Rule ID 5139 //
     /* 297019 */     // MIs[0] Operand 1
     /* 297019 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297028 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297032 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 297032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 297035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297039 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297041 */     GIR_RootConstrainSelectedInstOperands,
     /* 297042 */     // GIR_Coverage, 5139,
     /* 297042 */     GIR_EraseRootFromParent_Done,
     /* 297043 */   // Label 5843: @297043
     /* 297043 */   GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(297072), // Rule ID 5146 //
     /* 297048 */     // MIs[0] Operand 1
     /* 297048 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 297053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297057 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297061 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 297061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 297064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297070 */     GIR_RootConstrainSelectedInstOperands,
     /* 297071 */     // GIR_Coverage, 5146,
     /* 297071 */     GIR_EraseRootFromParent_Done,
     /* 297072 */   // Label 5844: @297072
     /* 297072 */   GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(297101), // Rule ID 5153 //
     /* 297077 */     // MIs[0] Operand 1
     /* 297077 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 297082 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297086 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297090 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 297090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 297093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297099 */     GIR_RootConstrainSelectedInstOperands,
     /* 297100 */     // GIR_Coverage, 5153,
     /* 297100 */     GIR_EraseRootFromParent_Done,
     /* 297101 */   // Label 5845: @297101
     /* 297101 */   GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(297130), // Rule ID 5160 //
     /* 297106 */     // MIs[0] Operand 1
     /* 297106 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 297111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297115 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297119 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 297119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 297122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297128 */     GIR_RootConstrainSelectedInstOperands,
     /* 297129 */     // GIR_Coverage, 5160,
     /* 297129 */     GIR_EraseRootFromParent_Done,
     /* 297130 */   // Label 5846: @297130
     /* 297130 */   GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(297159), // Rule ID 5167 //
     /* 297135 */     // MIs[0] Operand 1
     /* 297135 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 297140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297144 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297148 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 297148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 297151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297157 */     GIR_RootConstrainSelectedInstOperands,
     /* 297158 */     // GIR_Coverage, 5167,
     /* 297158 */     GIR_EraseRootFromParent_Done,
     /* 297159 */   // Label 5847: @297159
     /* 297159 */   GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(297188), // Rule ID 5174 //
     /* 297164 */     // MIs[0] Operand 1
     /* 297164 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 297169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297173 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297177 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 297177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 297180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297182 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297186 */     GIR_RootConstrainSelectedInstOperands,
     /* 297187 */     // GIR_Coverage, 5174,
     /* 297187 */     GIR_EraseRootFromParent_Done,
     /* 297188 */   // Label 5848: @297188
     /* 297188 */   GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(297217), // Rule ID 5181 //
     /* 297193 */     // MIs[0] Operand 1
     /* 297193 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 297198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297202 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297206 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 297206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 297209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297211 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297215 */     GIR_RootConstrainSelectedInstOperands,
     /* 297216 */     // GIR_Coverage, 5181,
     /* 297216 */     GIR_EraseRootFromParent_Done,
     /* 297217 */   // Label 5849: @297217
     /* 297217 */   GIM_Reject,
     /* 297218 */ // Label 5819: @297218
     /* 297218 */ GIM_Reject,
     /* 297219 */ // Label 5650: @297219
     /* 297219 */ GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(298266),
     /* 297224 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 297227 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297230 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297234 */   GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(297274), // Rule ID 755 //
     /* 297239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297242 */     // MIs[0] Operand 1
     /* 297242 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297247 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297251 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297257 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297259 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297263 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297265 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 297268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297270 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297272 */     GIR_RootConstrainSelectedInstOperands,
     /* 297273 */     // GIR_Coverage, 755,
     /* 297273 */     GIR_EraseRootFromParent_Done,
     /* 297274 */   // Label 5851: @297274
     /* 297274 */   GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(297314), // Rule ID 762 //
     /* 297279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297282 */     // MIs[0] Operand 1
     /* 297282 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297287 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297291 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297297 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297299 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297303 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297305 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 297308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297312 */     GIR_RootConstrainSelectedInstOperands,
     /* 297313 */     // GIR_Coverage, 762,
     /* 297313 */     GIR_EraseRootFromParent_Done,
     /* 297314 */   // Label 5852: @297314
     /* 297314 */   GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(297351), // Rule ID 5221 //
     /* 297319 */     // MIs[0] Operand 1
     /* 297319 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 297324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297328 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297334 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297336 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297340 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297342 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 297345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297349 */     GIR_RootConstrainSelectedInstOperands,
     /* 297350 */     // GIR_Coverage, 5221,
     /* 297350 */     GIR_EraseRootFromParent_Done,
     /* 297351 */   // Label 5853: @297351
     /* 297351 */   GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(297388), // Rule ID 5228 //
     /* 297356 */     // MIs[0] Operand 1
     /* 297356 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297365 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297371 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297377 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297379 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 297382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297386 */     GIR_RootConstrainSelectedInstOperands,
     /* 297387 */     // GIR_Coverage, 5228,
     /* 297387 */     GIR_EraseRootFromParent_Done,
     /* 297388 */   // Label 5854: @297388
     /* 297388 */   GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(297425), // Rule ID 5235 //
     /* 297393 */     // MIs[0] Operand 1
     /* 297393 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297402 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297408 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297410 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297414 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297416 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 297419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297421 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297423 */     GIR_RootConstrainSelectedInstOperands,
     /* 297424 */     // GIR_Coverage, 5235,
     /* 297424 */     GIR_EraseRootFromParent_Done,
     /* 297425 */   // Label 5855: @297425
     /* 297425 */   GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(297462), // Rule ID 5242 //
     /* 297430 */     // MIs[0] Operand 1
     /* 297430 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 297435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297439 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297445 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297453 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 297456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297460 */     GIR_RootConstrainSelectedInstOperands,
     /* 297461 */     // GIR_Coverage, 5242,
     /* 297461 */     GIR_EraseRootFromParent_Done,
     /* 297462 */   // Label 5856: @297462
     /* 297462 */   GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(297499), // Rule ID 5249 //
     /* 297467 */     // MIs[0] Operand 1
     /* 297467 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 297472 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 297476 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297482 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297484 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297488 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297490 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 297493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297497 */     GIR_RootConstrainSelectedInstOperands,
     /* 297498 */     // GIR_Coverage, 5249,
     /* 297498 */     GIR_EraseRootFromParent_Done,
     /* 297499 */   // Label 5857: @297499
     /* 297499 */   GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(297539), // Rule ID 727 //
     /* 297504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297507 */     // MIs[0] Operand 1
     /* 297507 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 297512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297520 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297526 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297528 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297530 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 297533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297535 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297537 */     GIR_RootConstrainSelectedInstOperands,
     /* 297538 */     // GIR_Coverage, 727,
     /* 297538 */     GIR_EraseRootFromParent_Done,
     /* 297539 */   // Label 5858: @297539
     /* 297539 */   GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(297579), // Rule ID 735 //
     /* 297544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297547 */     // MIs[0] Operand 1
     /* 297547 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297552 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297560 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297566 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297568 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297570 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 297573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297577 */     GIR_RootConstrainSelectedInstOperands,
     /* 297578 */     // GIR_Coverage, 735,
     /* 297578 */     GIR_EraseRootFromParent_Done,
     /* 297579 */   // Label 5859: @297579
     /* 297579 */   GIM_Try, /*On fail goto*//*Label 5860*/ GIMT_Encode4(297619), // Rule ID 736 //
     /* 297584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297587 */     // MIs[0] Operand 1
     /* 297587 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297592 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297600 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297606 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 297608 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297610 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 297613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297615 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297617 */     GIR_RootConstrainSelectedInstOperands,
     /* 297618 */     // GIR_Coverage, 736,
     /* 297618 */     GIR_EraseRootFromParent_Done,
     /* 297619 */   // Label 5860: @297619
     /* 297619 */   GIM_Try, /*On fail goto*//*Label 5861*/ GIMT_Encode4(297659), // Rule ID 748 //
     /* 297624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297627 */     // MIs[0] Operand 1
     /* 297627 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297640 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297646 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297648 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297650 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 297653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297657 */     GIR_RootConstrainSelectedInstOperands,
     /* 297658 */     // GIR_Coverage, 748,
     /* 297658 */     GIR_EraseRootFromParent_Done,
     /* 297659 */   // Label 5861: @297659
     /* 297659 */   GIM_Try, /*On fail goto*//*Label 5862*/ GIMT_Encode4(297696), // Rule ID 5186 //
     /* 297664 */     // MIs[0] Operand 1
     /* 297664 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 297669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297677 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297683 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297685 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297687 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 297690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297694 */     GIR_RootConstrainSelectedInstOperands,
     /* 297695 */     // GIR_Coverage, 5186,
     /* 297695 */     GIR_EraseRootFromParent_Done,
     /* 297696 */   // Label 5862: @297696
     /* 297696 */   GIM_Try, /*On fail goto*//*Label 5863*/ GIMT_Encode4(297733), // Rule ID 5193 //
     /* 297701 */     // MIs[0] Operand 1
     /* 297701 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297714 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297720 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297722 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297724 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 297727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297731 */     GIR_RootConstrainSelectedInstOperands,
     /* 297732 */     // GIR_Coverage, 5193,
     /* 297732 */     GIR_EraseRootFromParent_Done,
     /* 297733 */   // Label 5863: @297733
     /* 297733 */   GIM_Try, /*On fail goto*//*Label 5864*/ GIMT_Encode4(297770), // Rule ID 5200 //
     /* 297738 */     // MIs[0] Operand 1
     /* 297738 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297751 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297757 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297759 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297761 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 297764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297768 */     GIR_RootConstrainSelectedInstOperands,
     /* 297769 */     // GIR_Coverage, 5200,
     /* 297769 */     GIR_EraseRootFromParent_Done,
     /* 297770 */   // Label 5864: @297770
     /* 297770 */   GIM_Try, /*On fail goto*//*Label 5865*/ GIMT_Encode4(297807), // Rule ID 5207 //
     /* 297775 */     // MIs[0] Operand 1
     /* 297775 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 297780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297788 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297794 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297796 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297798 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 297801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297803 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297805 */     GIR_RootConstrainSelectedInstOperands,
     /* 297806 */     // GIR_Coverage, 5207,
     /* 297806 */     GIR_EraseRootFromParent_Done,
     /* 297807 */   // Label 5865: @297807
     /* 297807 */   GIM_Try, /*On fail goto*//*Label 5866*/ GIMT_Encode4(297844), // Rule ID 5214 //
     /* 297812 */     // MIs[0] Operand 1
     /* 297812 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 297817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 297825 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 297831 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 297833 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 297835 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 297835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 297838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297842 */     GIR_RootConstrainSelectedInstOperands,
     /* 297843 */     // GIR_Coverage, 5214,
     /* 297843 */     GIR_EraseRootFromParent_Done,
     /* 297844 */   // Label 5866: @297844
     /* 297844 */   GIM_Try, /*On fail goto*//*Label 5867*/ GIMT_Encode4(297876), // Rule ID 1126 //
     /* 297849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297852 */     // MIs[0] Operand 1
     /* 297852 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 297857 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297861 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297865 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 297865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8),
     /* 297868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297874 */     GIR_RootConstrainSelectedInstOperands,
     /* 297875 */     // GIR_Coverage, 1126,
     /* 297875 */     GIR_EraseRootFromParent_Done,
     /* 297876 */   // Label 5867: @297876
     /* 297876 */   GIM_Try, /*On fail goto*//*Label 5868*/ GIMT_Encode4(297908), // Rule ID 1133 //
     /* 297881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297884 */     // MIs[0] Operand 1
     /* 297884 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 297889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297893 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297897 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 297897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 297900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297906 */     GIR_RootConstrainSelectedInstOperands,
     /* 297907 */     // GIR_Coverage, 1133,
     /* 297907 */     GIR_EraseRootFromParent_Done,
     /* 297908 */   // Label 5868: @297908
     /* 297908 */   GIM_Try, /*On fail goto*//*Label 5869*/ GIMT_Encode4(297940), // Rule ID 1140 //
     /* 297913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297916 */     // MIs[0] Operand 1
     /* 297916 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 297921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297929 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 297929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 297932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297938 */     GIR_RootConstrainSelectedInstOperands,
     /* 297939 */     // GIR_Coverage, 1140,
     /* 297939 */     GIR_EraseRootFromParent_Done,
     /* 297940 */   // Label 5869: @297940
     /* 297940 */   GIM_Try, /*On fail goto*//*Label 5870*/ GIMT_Encode4(297972), // Rule ID 1147 //
     /* 297945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297948 */     // MIs[0] Operand 1
     /* 297948 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 297953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297957 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297961 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 297961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 297964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297966 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 297968 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 297970 */     GIR_RootConstrainSelectedInstOperands,
     /* 297971 */     // GIR_Coverage, 1147,
     /* 297971 */     GIR_EraseRootFromParent_Done,
     /* 297972 */   // Label 5870: @297972
     /* 297972 */   GIM_Try, /*On fail goto*//*Label 5871*/ GIMT_Encode4(298004), // Rule ID 1154 //
     /* 297977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 297980 */     // MIs[0] Operand 1
     /* 297980 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 297985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297989 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297993 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 297993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 297996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 297998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298002 */     GIR_RootConstrainSelectedInstOperands,
     /* 298003 */     // GIR_Coverage, 1154,
     /* 298003 */     GIR_EraseRootFromParent_Done,
     /* 298004 */   // Label 5871: @298004
     /* 298004 */   GIM_Try, /*On fail goto*//*Label 5872*/ GIMT_Encode4(298033), // Rule ID 5123 //
     /* 298009 */     // MIs[0] Operand 1
     /* 298009 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 298014 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298018 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298022 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 298022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8),
     /* 298025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298031 */     GIR_RootConstrainSelectedInstOperands,
     /* 298032 */     // GIR_Coverage, 5123,
     /* 298032 */     GIR_EraseRootFromParent_Done,
     /* 298033 */   // Label 5872: @298033
     /* 298033 */   GIM_Try, /*On fail goto*//*Label 5873*/ GIMT_Encode4(298062), // Rule ID 5130 //
     /* 298038 */     // MIs[0] Operand 1
     /* 298038 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 298043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298047 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298051 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 298051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 298054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298058 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298060 */     GIR_RootConstrainSelectedInstOperands,
     /* 298061 */     // GIR_Coverage, 5130,
     /* 298061 */     GIR_EraseRootFromParent_Done,
     /* 298062 */   // Label 5873: @298062
     /* 298062 */   GIM_Try, /*On fail goto*//*Label 5874*/ GIMT_Encode4(298091), // Rule ID 5137 //
     /* 298067 */     // MIs[0] Operand 1
     /* 298067 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 298072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298076 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298080 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 298080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 298083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298089 */     GIR_RootConstrainSelectedInstOperands,
     /* 298090 */     // GIR_Coverage, 5137,
     /* 298090 */     GIR_EraseRootFromParent_Done,
     /* 298091 */   // Label 5874: @298091
     /* 298091 */   GIM_Try, /*On fail goto*//*Label 5875*/ GIMT_Encode4(298120), // Rule ID 5144 //
     /* 298096 */     // MIs[0] Operand 1
     /* 298096 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 298101 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298105 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298109 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 298109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 298112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298116 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298118 */     GIR_RootConstrainSelectedInstOperands,
     /* 298119 */     // GIR_Coverage, 5144,
     /* 298119 */     GIR_EraseRootFromParent_Done,
     /* 298120 */   // Label 5875: @298120
     /* 298120 */   GIM_Try, /*On fail goto*//*Label 5876*/ GIMT_Encode4(298149), // Rule ID 5151 //
     /* 298125 */     // MIs[0] Operand 1
     /* 298125 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 298130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298134 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298138 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 298138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 298141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298147 */     GIR_RootConstrainSelectedInstOperands,
     /* 298148 */     // GIR_Coverage, 5151,
     /* 298148 */     GIR_EraseRootFromParent_Done,
     /* 298149 */   // Label 5876: @298149
     /* 298149 */   GIM_Try, /*On fail goto*//*Label 5877*/ GIMT_Encode4(298178), // Rule ID 5158 //
     /* 298154 */     // MIs[0] Operand 1
     /* 298154 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 298159 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298163 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298167 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 298167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 298170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298172 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298176 */     GIR_RootConstrainSelectedInstOperands,
     /* 298177 */     // GIR_Coverage, 5158,
     /* 298177 */     GIR_EraseRootFromParent_Done,
     /* 298178 */   // Label 5877: @298178
     /* 298178 */   GIM_Try, /*On fail goto*//*Label 5878*/ GIMT_Encode4(298207), // Rule ID 5165 //
     /* 298183 */     // MIs[0] Operand 1
     /* 298183 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 298188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298192 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298196 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 298196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 298199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298201 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298205 */     GIR_RootConstrainSelectedInstOperands,
     /* 298206 */     // GIR_Coverage, 5165,
     /* 298206 */     GIR_EraseRootFromParent_Done,
     /* 298207 */   // Label 5878: @298207
     /* 298207 */   GIM_Try, /*On fail goto*//*Label 5879*/ GIMT_Encode4(298236), // Rule ID 5172 //
     /* 298212 */     // MIs[0] Operand 1
     /* 298212 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 298217 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298221 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298225 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 298225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 298228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298234 */     GIR_RootConstrainSelectedInstOperands,
     /* 298235 */     // GIR_Coverage, 5172,
     /* 298235 */     GIR_EraseRootFromParent_Done,
     /* 298236 */   // Label 5879: @298236
     /* 298236 */   GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(298265), // Rule ID 5179 //
     /* 298241 */     // MIs[0] Operand 1
     /* 298241 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 298246 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298250 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298254 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 298254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 298257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 298259 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 298261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 298263 */     GIR_RootConstrainSelectedInstOperands,
     /* 298264 */     // GIR_Coverage, 5179,
     /* 298264 */     GIR_EraseRootFromParent_Done,
     /* 298265 */   // Label 5880: @298265
     /* 298265 */   GIM_Reject,
     /* 298266 */ // Label 5850: @298266
     /* 298266 */ GIM_Reject,
     /* 298267 */ // Label 5651: @298267
     /* 298267 */ GIM_Reject,
     /* 298268 */ // Label 52: @298268
     /* 298268 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(24), /*)*//*default:*//*Label 5893*/ GIMT_Encode4(299312),
     /* 298279 */ /*GILLT_nxv1s1*//*Label 5881*/ GIMT_Encode4(298327),
     /* 298283 */ /*GILLT_nxv2s1*//*Label 5882*/ GIMT_Encode4(298356),
     /* 298287 */ /*GILLT_nxv2s16*//*Label 5883*/ GIMT_Encode4(298385),
     /* 298291 */ /*GILLT_nxv2s32*//*Label 5884*/ GIMT_Encode4(298470),
     /* 298295 */ /*GILLT_nxv2s64*//*Label 5885*/ GIMT_Encode4(298555),
     /* 298299 */ /*GILLT_nxv4s1*//*Label 5886*/ GIMT_Encode4(298721),
     /* 298303 */ /*GILLT_nxv4s16*//*Label 5887*/ GIMT_Encode4(298750),
     /* 298307 */ /*GILLT_nxv4s32*//*Label 5888*/ GIMT_Encode4(298835),
     /* 298311 */ /*GILLT_nxv8s1*//*Label 5889*/ GIMT_Encode4(299001),
     /* 298315 */ /*GILLT_nxv8s16*//*Label 5890*/ GIMT_Encode4(299030),
     /* 298319 */ /*GILLT_nxv16s1*//*Label 5891*/ GIMT_Encode4(299196),
     /* 298323 */ /*GILLT_nxv16s8*//*Label 5892*/ GIMT_Encode4(299225),
     /* 298327 */ // Label 5881: @298327
     /* 298327 */ GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(298355), // Rule ID 8572 //
     /* 298332 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298335 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /* 298338 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 298341 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 298344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 298348 */   // (vselect:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 298348 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 298353 */   GIR_RootConstrainSelectedInstOperands,
     /* 298354 */   // GIR_Coverage, 8572,
     /* 298354 */   GIR_Done,
     /* 298355 */ // Label 5894: @298355
     /* 298355 */ GIM_Reject,
     /* 298356 */ // Label 5882: @298356
     /* 298356 */ GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(298384), // Rule ID 8571 //
     /* 298361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 298367 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 298370 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 298373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 298377 */   // (vselect:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 298377 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 298382 */   GIR_RootConstrainSelectedInstOperands,
     /* 298383 */   // GIR_Coverage, 8571,
     /* 298383 */   GIR_Done,
     /* 298384 */ // Label 5895: @298384
     /* 298384 */ GIM_Reject,
     /* 298385 */ // Label 5883: @298385
     /* 298385 */ GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(298469),
     /* 298390 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 298393 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 298396 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 298399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298403 */   GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(298453), // Rule ID 3180 //
     /* 298408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298415 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 298419 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 298423 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 298427 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 298431 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 298435 */     // MIs[2] Operand 1
     /* 298435 */     // No operand predicates
     /* 298435 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 298437 */     // (vselect:{ *:[nxv2f16] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv2f16:{ *:[nxv2f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 298437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 298440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 298442 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 298444 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 298446 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 298451 */     GIR_RootConstrainSelectedInstOperands,
     /* 298452 */     // GIR_Coverage, 3180,
     /* 298452 */     GIR_EraseRootFromParent_Done,
     /* 298453 */   // Label 5897: @298453
     /* 298453 */   GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(298468), // Rule ID 2741 //
     /* 298458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298461 */     // (vselect:{ *:[nxv2f16] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 298461 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 298466 */     GIR_RootConstrainSelectedInstOperands,
     /* 298467 */     // GIR_Coverage, 2741,
     /* 298467 */     GIR_Done,
     /* 298468 */   // Label 5898: @298468
     /* 298468 */   GIM_Reject,
     /* 298469 */ // Label 5896: @298469
     /* 298469 */ GIM_Reject,
     /* 298470 */ // Label 5884: @298470
     /* 298470 */ GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(298554),
     /* 298475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 298478 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 298481 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 298484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298488 */   GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(298538), // Rule ID 3182 //
     /* 298493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298500 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 298504 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 298508 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 298512 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 298516 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 298520 */     // MIs[2] Operand 1
     /* 298520 */     // No operand predicates
     /* 298520 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 298522 */     // (vselect:{ *:[nxv2f32] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8), nxv2f32:{ *:[nxv2f32] }:$zd)  =>  (FCPY_ZPmI_S:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 298522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_S),
     /* 298525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 298527 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 298529 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 298531 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 298536 */     GIR_RootConstrainSelectedInstOperands,
     /* 298537 */     // GIR_Coverage, 3182,
     /* 298537 */     GIR_EraseRootFromParent_Done,
     /* 298538 */   // Label 5900: @298538
     /* 298538 */   GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(298553), // Rule ID 2742 //
     /* 298543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298546 */     // (vselect:{ *:[nxv2f32] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 298546 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 298551 */     GIR_RootConstrainSelectedInstOperands,
     /* 298552 */     // GIR_Coverage, 2742,
     /* 298552 */     GIR_Done,
     /* 298553 */   // Label 5901: @298553
     /* 298553 */   GIM_Reject,
     /* 298554 */ // Label 5899: @298554
     /* 298554 */ GIM_Reject,
     /* 298555 */ // Label 5885: @298555
     /* 298555 */ GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(298720),
     /* 298560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 298563 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 298566 */   GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(298623), // Rule ID 3183 //
     /* 298571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 298577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 298589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 298593 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 298597 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 298601 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 298605 */     // MIs[2] Operand 1
     /* 298605 */     // No operand predicates
     /* 298605 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 298607 */     // (vselect:{ *:[nxv2f64] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm8), nxv2f64:{ *:[nxv2f64] }:$zd)  =>  (FCPY_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>>:$imm8))
     /* 298607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_D),
     /* 298610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 298612 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 298614 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 298616 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm8
     /* 298621 */     GIR_RootConstrainSelectedInstOperands,
     /* 298622 */     // GIR_Coverage, 3183,
     /* 298622 */     GIR_EraseRootFromParent_Done,
     /* 298623 */   // Label 5903: @298623
     /* 298623 */   GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(298675), // Rule ID 7593 //
     /* 298628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 298643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 298647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 298651 */     // MIs[0] Op2
     /* 298651 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 298656 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 298658 */     // (vselect:{ *:[nxv2i64] } nxv2i1:{ *:[nxv2i1] }:$Op1, (sub:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 298658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_D),
     /* 298661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 298663 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 298665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 298669 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 298673 */     GIR_RootConstrainSelectedInstOperands,
     /* 298674 */     // GIR_Coverage, 7593,
     /* 298674 */     GIR_EraseRootFromParent_Done,
     /* 298675 */   // Label 5904: @298675
     /* 298675 */   GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(298697), // Rule ID 2737 //
     /* 298680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 298686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298690 */     // (vselect:{ *:[nxv2i64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 298690 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 298695 */     GIR_RootConstrainSelectedInstOperands,
     /* 298696 */     // GIR_Coverage, 2737,
     /* 298696 */     GIR_Done,
     /* 298697 */   // Label 5905: @298697
     /* 298697 */   GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(298719), // Rule ID 2743 //
     /* 298702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298705 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 298708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298712 */     // (vselect:{ *:[nxv2f64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 298712 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 298717 */     GIR_RootConstrainSelectedInstOperands,
     /* 298718 */     // GIR_Coverage, 2743,
     /* 298718 */     GIR_Done,
     /* 298719 */   // Label 5906: @298719
     /* 298719 */   GIM_Reject,
     /* 298720 */ // Label 5902: @298720
     /* 298720 */ GIM_Reject,
     /* 298721 */ // Label 5886: @298721
     /* 298721 */ GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(298749), // Rule ID 8570 //
     /* 298726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298729 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 298732 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 298735 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 298738 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 298742 */   // (vselect:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 298742 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 298747 */   GIR_RootConstrainSelectedInstOperands,
     /* 298748 */   // GIR_Coverage, 8570,
     /* 298748 */   GIR_Done,
     /* 298749 */ // Label 5907: @298749
     /* 298749 */ GIM_Reject,
     /* 298750 */ // Label 5887: @298750
     /* 298750 */ GIM_Try, /*On fail goto*//*Label 5908*/ GIMT_Encode4(298834),
     /* 298755 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 298758 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 298761 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 298764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298768 */   GIM_Try, /*On fail goto*//*Label 5909*/ GIMT_Encode4(298818), // Rule ID 3179 //
     /* 298773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 298784 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 298788 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 298792 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 298796 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 298800 */     // MIs[2] Operand 1
     /* 298800 */     // No operand predicates
     /* 298800 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 298802 */     // (vselect:{ *:[nxv4f16] } nxv4i1:{ *:[nxv4i1] }:$pg, (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv4f16:{ *:[nxv4f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$zd, ?:{ *:[nxv4i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 298802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 298805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 298807 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 298809 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 298811 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 298816 */     GIR_RootConstrainSelectedInstOperands,
     /* 298817 */     // GIR_Coverage, 3179,
     /* 298817 */     GIR_EraseRootFromParent_Done,
     /* 298818 */   // Label 5909: @298818
     /* 298818 */   GIM_Try, /*On fail goto*//*Label 5910*/ GIMT_Encode4(298833), // Rule ID 2739 //
     /* 298823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298826 */     // (vselect:{ *:[nxv4f16] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 298826 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 298831 */     GIR_RootConstrainSelectedInstOperands,
     /* 298832 */     // GIR_Coverage, 2739,
     /* 298832 */     GIR_Done,
     /* 298833 */   // Label 5910: @298833
     /* 298833 */   GIM_Reject,
     /* 298834 */ // Label 5908: @298834
     /* 298834 */ GIM_Reject,
     /* 298835 */ // Label 5888: @298835
     /* 298835 */ GIM_Try, /*On fail goto*//*Label 5911*/ GIMT_Encode4(299000),
     /* 298840 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 298843 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 298846 */   GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(298903), // Rule ID 3181 //
     /* 298851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 298857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298861 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298865 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 298869 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 298873 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 298877 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 298881 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 298885 */     // MIs[2] Operand 1
     /* 298885 */     // No operand predicates
     /* 298885 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 298887 */     // (vselect:{ *:[nxv4f32] } nxv4i1:{ *:[nxv4i1] }:$pg, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8), nxv4f32:{ *:[nxv4f32] }:$zd)  =>  (FCPY_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$zd, ?:{ *:[nxv4i1] }:$pg, (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 298887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_S),
     /* 298890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 298892 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 298894 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 298896 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 298901 */     GIR_RootConstrainSelectedInstOperands,
     /* 298902 */     // GIR_Coverage, 3181,
     /* 298902 */     GIR_EraseRootFromParent_Done,
     /* 298903 */   // Label 5912: @298903
     /* 298903 */   GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(298955), // Rule ID 7591 //
     /* 298908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 298919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 298923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 298927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 298931 */     // MIs[0] Op2
     /* 298931 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 298936 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 298938 */     // (vselect:{ *:[nxv4i32] } nxv4i1:{ *:[nxv4i1] }:$Op1, (sub:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 298938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_S),
     /* 298941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 298943 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 298945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 298949 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 298953 */     GIR_RootConstrainSelectedInstOperands,
     /* 298954 */     // GIR_Coverage, 7591,
     /* 298954 */     GIR_EraseRootFromParent_Done,
     /* 298955 */   // Label 5913: @298955
     /* 298955 */   GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(298977), // Rule ID 2736 //
     /* 298960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 298966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298970 */     // (vselect:{ *:[nxv4i32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 298970 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 298975 */     GIR_RootConstrainSelectedInstOperands,
     /* 298976 */     // GIR_Coverage, 2736,
     /* 298976 */     GIR_Done,
     /* 298977 */   // Label 5914: @298977
     /* 298977 */   GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(298999), // Rule ID 2740 //
     /* 298982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 298985 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 298988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 298992 */     // (vselect:{ *:[nxv4f32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 298992 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 298997 */     GIR_RootConstrainSelectedInstOperands,
     /* 298998 */     // GIR_Coverage, 2740,
     /* 298998 */     GIR_Done,
     /* 298999 */   // Label 5915: @298999
     /* 298999 */   GIM_Reject,
     /* 299000 */ // Label 5911: @299000
     /* 299000 */ GIM_Reject,
     /* 299001 */ // Label 5889: @299001
     /* 299001 */ GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(299029), // Rule ID 8569 //
     /* 299006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299009 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 299012 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299015 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 299022 */   // (vselect:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 299022 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 299027 */   GIR_RootConstrainSelectedInstOperands,
     /* 299028 */   // GIR_Coverage, 8569,
     /* 299028 */   GIR_Done,
     /* 299029 */ // Label 5916: @299029
     /* 299029 */ GIM_Reject,
     /* 299030 */ // Label 5890: @299030
     /* 299030 */ GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(299195),
     /* 299035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 299038 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 299041 */   GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(299098), // Rule ID 3178 //
     /* 299046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 299052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 299060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 299064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 299068 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 299072 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 299076 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 299080 */     // MIs[2] Operand 1
     /* 299080 */     // No operand predicates
     /* 299080 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 299082 */     // (vselect:{ *:[nxv8f16] } nxv8i1:{ *:[nxv8i1] }:$pg, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv8f16:{ *:[nxv8f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$zd, ?:{ *:[nxv8i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 299082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 299085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 299087 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 299089 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 299091 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 299096 */     GIR_RootConstrainSelectedInstOperands,
     /* 299097 */     // GIR_Coverage, 3178,
     /* 299097 */     GIR_EraseRootFromParent_Done,
     /* 299098 */   // Label 5918: @299098
     /* 299098 */   GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(299150), // Rule ID 7589 //
     /* 299103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 299114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 299118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 299122 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 299126 */     // MIs[0] Op2
     /* 299126 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 299131 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 299133 */     // (vselect:{ *:[nxv8i16] } nxv8i1:{ *:[nxv8i1] }:$Op1, (sub:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 299133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_H),
     /* 299136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 299138 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 299140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 299144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 299148 */     GIR_RootConstrainSelectedInstOperands,
     /* 299149 */     // GIR_Coverage, 7589,
     /* 299149 */     GIR_EraseRootFromParent_Done,
     /* 299150 */   // Label 5919: @299150
     /* 299150 */   GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(299172), // Rule ID 2735 //
     /* 299155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 299161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299165 */     // (vselect:{ *:[nxv8i16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SEL_ZPZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 299165 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
     /* 299170 */     GIR_RootConstrainSelectedInstOperands,
     /* 299171 */     // GIR_Coverage, 2735,
     /* 299171 */     GIR_Done,
     /* 299172 */   // Label 5920: @299172
     /* 299172 */   GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(299194), // Rule ID 2738 //
     /* 299177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299180 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 299183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299187 */     // (vselect:{ *:[nxv8f16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (SEL_ZPZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 299187 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
     /* 299192 */     GIR_RootConstrainSelectedInstOperands,
     /* 299193 */     // GIR_Coverage, 2738,
     /* 299193 */     GIR_Done,
     /* 299194 */   // Label 5921: @299194
     /* 299194 */   GIM_Reject,
     /* 299195 */ // Label 5917: @299195
     /* 299195 */ GIM_Reject,
     /* 299196 */ // Label 5891: @299196
     /* 299196 */ GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(299224), // Rule ID 8568 //
     /* 299201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299204 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 299207 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299210 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 299217 */   // (vselect:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 299217 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 299222 */   GIR_RootConstrainSelectedInstOperands,
     /* 299223 */   // GIR_Coverage, 8568,
     /* 299223 */   GIR_Done,
     /* 299224 */ // Label 5922: @299224
     /* 299224 */ GIM_Reject,
     /* 299225 */ // Label 5892: @299225
     /* 299225 */ GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(299311),
     /* 299230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 299233 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 299236 */   GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(299288), // Rule ID 7587 //
     /* 299241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299248 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 299252 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 299256 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 299260 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 299264 */     // MIs[0] Op2
     /* 299264 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 299269 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 299271 */     // (vselect:{ *:[nxv16i8] } nxv16i1:{ *:[nxv16i1] }:$Op1, (sub:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 299271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_B),
     /* 299274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 299276 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 299278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 299282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 299286 */     GIR_RootConstrainSelectedInstOperands,
     /* 299287 */     // GIR_Coverage, 7587,
     /* 299287 */     GIR_EraseRootFromParent_Done,
     /* 299288 */   // Label 5924: @299288
     /* 299288 */   GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(299310), // Rule ID 2734 //
     /* 299293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 299296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 299299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 299303 */     // (vselect:{ *:[nxv16i8] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SEL_ZPZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 299303 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_B),
     /* 299308 */     GIR_RootConstrainSelectedInstOperands,
     /* 299309 */     // GIR_Coverage, 2734,
     /* 299309 */     GIR_Done,
     /* 299310 */   // Label 5925: @299310
     /* 299310 */   GIM_Reject,
     /* 299311 */ // Label 5923: @299311
     /* 299311 */ GIM_Reject,
     /* 299312 */ // Label 5893: @299312
     /* 299312 */ GIM_Reject,
     /* 299313 */ // Label 53: @299313
     /* 299313 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 5930*/ GIMT_Encode4(299796),
     /* 299324 */ /*GILLT_s64*//*Label 5926*/ GIMT_Encode4(299360), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 299344 */ /*GILLT_v4s32*//*Label 5927*/ GIMT_Encode4(299391), GIMT_Encode4(0),
     /* 299352 */ /*GILLT_v8s16*//*Label 5928*/ GIMT_Encode4(299526),
     /* 299356 */ /*GILLT_v16s8*//*Label 5929*/ GIMT_Encode4(299661),
     /* 299360 */ // Label 5926: @299360
     /* 299360 */ GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(299390), // Rule ID 128 //
     /* 299365 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 299368 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 299371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299375 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299379 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299383 */   // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 299383 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULHrr),
     /* 299388 */   GIR_RootConstrainSelectedInstOperands,
     /* 299389 */   // GIR_Coverage, 128,
     /* 299389 */   GIR_Done,
     /* 299390 */ // Label 5931: @299390
     /* 299390 */ GIM_Reject,
     /* 299391 */ // Label 5927: @299391
     /* 299391 */ GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(299525), // Rule ID 6607 //
     /* 299396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 299399 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 299402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299406 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299410 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299414 */   // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
     /* 299414 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 299417 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
     /* 299421 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299426 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 299430 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 299434 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 299436 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 299439 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299443 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299448 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 299454 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299459 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299464 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 299467 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299471 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299476 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 299482 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299487 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299492 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 299495 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
     /* 299499 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299504 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 299507 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 299510 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 299512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 299515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 299517 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 299520 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 299523 */   GIR_RootConstrainSelectedInstOperands,
     /* 299524 */   // GIR_Coverage, 6607,
     /* 299524 */   GIR_EraseRootFromParent_Done,
     /* 299525 */ // Label 5932: @299525
     /* 299525 */ GIM_Reject,
     /* 299526 */ // Label 5928: @299526
     /* 299526 */ GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(299660), // Rule ID 6606 //
     /* 299531 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 299534 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 299537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299541 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299545 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299549 */   // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
     /* 299549 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 299552 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
     /* 299556 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299561 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 299565 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 299569 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 299571 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 299574 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299578 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299583 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 299589 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299594 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299599 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 299602 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299606 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299611 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 299617 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299622 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299627 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 299630 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
     /* 299634 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299639 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 299642 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 299645 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 299647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 299650 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 299652 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 299655 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 299658 */   GIR_RootConstrainSelectedInstOperands,
     /* 299659 */   // GIR_Coverage, 6606,
     /* 299659 */   GIR_EraseRootFromParent_Done,
     /* 299660 */ // Label 5933: @299660
     /* 299660 */ GIM_Reject,
     /* 299661 */ // Label 5929: @299661
     /* 299661 */ GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(299795), // Rule ID 6605 //
     /* 299666 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 299669 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 299672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299676 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299680 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299684 */   // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
     /* 299684 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 299687 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
     /* 299691 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299696 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 299700 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 299704 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 299706 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 299709 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299713 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299718 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 299724 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299729 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299734 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 299737 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299741 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299746 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 299752 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299757 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299762 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 299765 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
     /* 299769 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299774 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 299777 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 299780 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 299782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 299785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 299787 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 299790 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 299793 */   GIR_RootConstrainSelectedInstOperands,
     /* 299794 */   // GIR_Coverage, 6605,
     /* 299794 */   GIR_EraseRootFromParent_Done,
     /* 299795 */ // Label 5934: @299795
     /* 299795 */ GIM_Reject,
     /* 299796 */ // Label 5930: @299796
     /* 299796 */ GIM_Reject,
     /* 299797 */ // Label 54: @299797
     /* 299797 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 5939*/ GIMT_Encode4(300280),
     /* 299808 */ /*GILLT_s64*//*Label 5935*/ GIMT_Encode4(299844), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 299828 */ /*GILLT_v4s32*//*Label 5936*/ GIMT_Encode4(299875), GIMT_Encode4(0),
     /* 299836 */ /*GILLT_v8s16*//*Label 5937*/ GIMT_Encode4(300010),
     /* 299840 */ /*GILLT_v16s8*//*Label 5938*/ GIMT_Encode4(300145),
     /* 299844 */ // Label 5935: @299844
     /* 299844 */ GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(299874), // Rule ID 127 //
     /* 299849 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 299852 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 299855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299859 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299863 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 299867 */   // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 299867 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULHrr),
     /* 299872 */   GIR_RootConstrainSelectedInstOperands,
     /* 299873 */   // GIR_Coverage, 127,
     /* 299873 */   GIR_Done,
     /* 299874 */ // Label 5940: @299874
     /* 299874 */ GIM_Reject,
     /* 299875 */ // Label 5936: @299875
     /* 299875 */ GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(300009), // Rule ID 6604 //
     /* 299880 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 299883 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 299886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299890 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299894 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299898 */   // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
     /* 299898 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 299901 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
     /* 299905 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299910 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 299914 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 299918 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 299920 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 299923 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299927 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299932 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 299938 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299943 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299948 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 299951 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 299955 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299960 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 299966 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 299971 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 299976 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 299979 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
     /* 299983 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 299988 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 299991 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 299994 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 299996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 299999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300001 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 300004 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 300007 */   GIR_RootConstrainSelectedInstOperands,
     /* 300008 */   // GIR_Coverage, 6604,
     /* 300008 */   GIR_EraseRootFromParent_Done,
     /* 300009 */ // Label 5941: @300009
     /* 300009 */ GIM_Reject,
     /* 300010 */ // Label 5937: @300010
     /* 300010 */ GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(300144), // Rule ID 6603 //
     /* 300015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 300018 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 300021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300025 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300029 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300033 */   // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
     /* 300033 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 300036 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
     /* 300040 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300045 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 300049 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 300053 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 300055 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 300058 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 300062 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300067 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 300073 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300078 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300083 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 300086 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 300090 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300095 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 300101 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300106 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300111 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 300114 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
     /* 300118 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300123 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 300126 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 300129 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 300131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 300134 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300136 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 300139 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 300142 */   GIR_RootConstrainSelectedInstOperands,
     /* 300143 */   // GIR_Coverage, 6603,
     /* 300143 */   GIR_EraseRootFromParent_Done,
     /* 300144 */ // Label 5942: @300144
     /* 300144 */ GIM_Reject,
     /* 300145 */ // Label 5938: @300145
     /* 300145 */ GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(300279), // Rule ID 6602 //
     /* 300150 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 300153 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 300156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300160 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300164 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300168 */   // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
     /* 300168 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 300171 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
     /* 300175 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300180 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 300184 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 300188 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 300190 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 300193 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 300197 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300202 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 300208 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300213 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300218 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 300221 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 300225 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300230 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 300236 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300241 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300246 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 300249 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
     /* 300253 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300258 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 300261 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 300264 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 300266 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 300269 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300271 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 300274 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 300277 */   GIR_RootConstrainSelectedInstOperands,
     /* 300278 */   // GIR_Coverage, 6602,
     /* 300278 */   GIR_EraseRootFromParent_Done,
     /* 300279 */ // Label 5943: @300279
     /* 300279 */ GIM_Reject,
     /* 300280 */ // Label 5939: @300280
     /* 300280 */ GIM_Reject,
     /* 300281 */ // Label 55: @300281
     /* 300281 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 5956*/ GIMT_Encode4(300752),
     /* 300292 */ /*GILLT_s64*//*Label 5944*/ GIMT_Encode4(300376), GIMT_Encode4(0),
     /* 300300 */ /*GILLT_v2s32*//*Label 5945*/ GIMT_Encode4(300410),
     /* 300304 */ /*GILLT_v2s64*//*Label 5946*/ GIMT_Encode4(300444),
     /* 300308 */ /*GILLT_v4s16*//*Label 5947*/ GIMT_Encode4(300478),
     /* 300312 */ /*GILLT_v4s32*//*Label 5948*/ GIMT_Encode4(300512),
     /* 300316 */ /*GILLT_v8s8*//*Label 5949*/ GIMT_Encode4(300546),
     /* 300320 */ /*GILLT_v8s16*//*Label 5950*/ GIMT_Encode4(300580),
     /* 300324 */ /*GILLT_v16s8*//*Label 5951*/ GIMT_Encode4(300614), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300344 */ /*GILLT_nxv2s64*//*Label 5952*/ GIMT_Encode4(300648), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300356 */ /*GILLT_nxv4s32*//*Label 5953*/ GIMT_Encode4(300674), GIMT_Encode4(0),
     /* 300364 */ /*GILLT_nxv8s16*//*Label 5954*/ GIMT_Encode4(300700), GIMT_Encode4(0),
     /* 300372 */ /*GILLT_nxv16s8*//*Label 5955*/ GIMT_Encode4(300726),
     /* 300376 */ // Label 5944: @300376
     /* 300376 */ GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(300409), // Rule ID 1649 //
     /* 300381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 300387 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 300390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300394 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300398 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300402 */   // (uaddsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 300402 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
     /* 300407 */   GIR_RootConstrainSelectedInstOperands,
     /* 300408 */   // GIR_Coverage, 1649,
     /* 300408 */   GIR_Done,
     /* 300409 */ // Label 5957: @300409
     /* 300409 */ GIM_Reject,
     /* 300410 */ // Label 5945: @300410
     /* 300410 */ GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(300443), // Rule ID 1547 //
     /* 300415 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300418 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 300421 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 300424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300428 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300432 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300436 */   // (uaddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 300436 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i32),
     /* 300441 */   GIR_RootConstrainSelectedInstOperands,
     /* 300442 */   // GIR_Coverage, 1547,
     /* 300442 */   GIR_Done,
     /* 300443 */ // Label 5958: @300443
     /* 300443 */ GIM_Reject,
     /* 300444 */ // Label 5946: @300444
     /* 300444 */ GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(300477), // Rule ID 1549 //
     /* 300449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300452 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300455 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 300458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300462 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300466 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300470 */   // (uaddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 300470 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i64),
     /* 300475 */   GIR_RootConstrainSelectedInstOperands,
     /* 300476 */   // GIR_Coverage, 1549,
     /* 300476 */   GIR_Done,
     /* 300477 */ // Label 5959: @300477
     /* 300477 */ GIM_Reject,
     /* 300478 */ // Label 5947: @300478
     /* 300478 */ GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(300511), // Rule ID 1545 //
     /* 300483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 300489 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 300492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300496 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300500 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300504 */   // (uaddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 300504 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i16),
     /* 300509 */   GIR_RootConstrainSelectedInstOperands,
     /* 300510 */   // GIR_Coverage, 1545,
     /* 300510 */   GIR_Done,
     /* 300511 */ // Label 5960: @300511
     /* 300511 */ GIM_Reject,
     /* 300512 */ // Label 5948: @300512
     /* 300512 */ GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(300545), // Rule ID 1548 //
     /* 300517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300520 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 300523 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 300526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300534 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300538 */   // (uaddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 300538 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i32),
     /* 300543 */   GIR_RootConstrainSelectedInstOperands,
     /* 300544 */   // GIR_Coverage, 1548,
     /* 300544 */   GIR_Done,
     /* 300545 */ // Label 5961: @300545
     /* 300545 */ GIM_Reject,
     /* 300546 */ // Label 5949: @300546
     /* 300546 */ GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(300579), // Rule ID 1543 //
     /* 300551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 300557 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 300560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300564 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300568 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300572 */   // (uaddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 300572 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i8),
     /* 300577 */   GIR_RootConstrainSelectedInstOperands,
     /* 300578 */   // GIR_Coverage, 1543,
     /* 300578 */   GIR_Done,
     /* 300579 */ // Label 5962: @300579
     /* 300579 */ GIM_Reject,
     /* 300580 */ // Label 5950: @300580
     /* 300580 */ GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(300613), // Rule ID 1546 //
     /* 300585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300588 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 300591 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 300594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300598 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300602 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300606 */   // (uaddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 300606 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i16),
     /* 300611 */   GIR_RootConstrainSelectedInstOperands,
     /* 300612 */   // GIR_Coverage, 1546,
     /* 300612 */   GIR_Done,
     /* 300613 */ // Label 5963: @300613
     /* 300613 */ GIM_Reject,
     /* 300614 */ // Label 5951: @300614
     /* 300614 */ GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(300647), // Rule ID 1544 //
     /* 300619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300622 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 300625 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 300628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300632 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300636 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300640 */   // (uaddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 300640 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv16i8),
     /* 300645 */   GIR_RootConstrainSelectedInstOperands,
     /* 300646 */   // GIR_Coverage, 1544,
     /* 300646 */   GIR_Done,
     /* 300647 */ // Label 5964: @300647
     /* 300647 */ GIM_Reject,
     /* 300648 */ // Label 5952: @300648
     /* 300648 */ GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(300673), // Rule ID 7545 //
     /* 300653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 300656 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 300659 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 300662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300666 */   // (uaddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 300666 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_D),
     /* 300671 */   GIR_RootConstrainSelectedInstOperands,
     /* 300672 */   // GIR_Coverage, 7545,
     /* 300672 */   GIR_Done,
     /* 300673 */ // Label 5965: @300673
     /* 300673 */ GIM_Reject,
     /* 300674 */ // Label 5953: @300674
     /* 300674 */ GIM_Try, /*On fail goto*//*Label 5966*/ GIMT_Encode4(300699), // Rule ID 7544 //
     /* 300679 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 300682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 300685 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300692 */   // (uaddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 300692 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_S),
     /* 300697 */   GIR_RootConstrainSelectedInstOperands,
     /* 300698 */   // GIR_Coverage, 7544,
     /* 300698 */   GIR_Done,
     /* 300699 */ // Label 5966: @300699
     /* 300699 */ GIM_Reject,
     /* 300700 */ // Label 5954: @300700
     /* 300700 */ GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(300725), // Rule ID 7543 //
     /* 300705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 300708 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 300711 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 300714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300718 */   // (uaddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 300718 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_H),
     /* 300723 */   GIR_RootConstrainSelectedInstOperands,
     /* 300724 */   // GIR_Coverage, 7543,
     /* 300724 */   GIR_Done,
     /* 300725 */ // Label 5967: @300725
     /* 300725 */ GIM_Reject,
     /* 300726 */ // Label 5955: @300726
     /* 300726 */ GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(300751), // Rule ID 7542 //
     /* 300731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 300734 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 300737 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 300740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300744 */   // (uaddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 300744 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_B),
     /* 300749 */   GIR_RootConstrainSelectedInstOperands,
     /* 300750 */   // GIR_Coverage, 7542,
     /* 300750 */   GIR_Done,
     /* 300751 */ // Label 5968: @300751
     /* 300751 */ GIM_Reject,
     /* 300752 */ // Label 5956: @300752
     /* 300752 */ GIM_Reject,
     /* 300753 */ // Label 56: @300753
     /* 300753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 5981*/ GIMT_Encode4(303128),
     /* 300764 */ /*GILLT_s64*//*Label 5969*/ GIMT_Encode4(300848), GIMT_Encode4(0),
     /* 300772 */ /*GILLT_v2s32*//*Label 5970*/ GIMT_Encode4(300882),
     /* 300776 */ /*GILLT_v2s64*//*Label 5971*/ GIMT_Encode4(300916),
     /* 300780 */ /*GILLT_v4s16*//*Label 5972*/ GIMT_Encode4(301902),
     /* 300784 */ /*GILLT_v4s32*//*Label 5973*/ GIMT_Encode4(301936),
     /* 300788 */ /*GILLT_v8s8*//*Label 5974*/ GIMT_Encode4(302922),
     /* 300792 */ /*GILLT_v8s16*//*Label 5975*/ GIMT_Encode4(302956),
     /* 300796 */ /*GILLT_v16s8*//*Label 5976*/ GIMT_Encode4(302990), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300816 */ /*GILLT_nxv2s64*//*Label 5977*/ GIMT_Encode4(303024), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300828 */ /*GILLT_nxv4s32*//*Label 5978*/ GIMT_Encode4(303050), GIMT_Encode4(0),
     /* 300836 */ /*GILLT_nxv8s16*//*Label 5979*/ GIMT_Encode4(303076), GIMT_Encode4(0),
     /* 300844 */ /*GILLT_nxv16s8*//*Label 5980*/ GIMT_Encode4(303102),
     /* 300848 */ // Label 5969: @300848
     /* 300848 */ GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(300881), // Rule ID 1640 //
     /* 300853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300856 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 300859 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 300862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300866 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300870 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300874 */   // (saddsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 300874 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
     /* 300879 */   GIR_RootConstrainSelectedInstOperands,
     /* 300880 */   // GIR_Coverage, 1640,
     /* 300880 */   GIR_Done,
     /* 300881 */ // Label 5982: @300881
     /* 300881 */ GIM_Reject,
     /* 300882 */ // Label 5970: @300882
     /* 300882 */ GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(300915), // Rule ID 1424 //
     /* 300887 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300890 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 300893 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 300896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300900 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300904 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300908 */   // (saddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 300908 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i32),
     /* 300913 */   GIR_RootConstrainSelectedInstOperands,
     /* 300914 */   // GIR_Coverage, 1424,
     /* 300914 */   GIR_Done,
     /* 300915 */ // Label 5983: @300915
     /* 300915 */ GIM_Reject,
     /* 300916 */ // Label 5971: @300916
     /* 300916 */ GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(301901),
     /* 300921 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300924 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 300927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300931 */   GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(301053), // Rule ID 13812 //
     /* 300936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 300939 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 300943 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 300947 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 300950 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 300955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 300959 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 300963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 300967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 300971 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 300975 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 300979 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 300983 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 300987 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 300991 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300996 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 301000 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301004 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301008 */     // MIs[4] Operand 1
     /* 301008 */     // No operand predicates
     /* 301008 */     // MIs[2] Operand 2
     /* 301008 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 301019 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301023 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 301025 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301032 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_indexed),
     /* 301035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 301039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 301044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 301048 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 301051 */     GIR_RootConstrainSelectedInstOperands,
     /* 301052 */     // GIR_Coverage, 13812,
     /* 301052 */     GIR_EraseRootFromParent_Done,
     /* 301053 */   // Label 5985: @301053
     /* 301053 */   GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(301175), // Rule ID 2064 //
     /* 301058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301061 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 301069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301073 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301076 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301081 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301085 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301089 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301093 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 301097 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301101 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 301105 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 301109 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301113 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 301117 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301122 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 301126 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301130 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301134 */     // MIs[4] Operand 1
     /* 301134 */     // No operand predicates
     /* 301134 */     // MIs[2] Operand 2
     /* 301134 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 301145 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 301147 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301154 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SQDMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_indexed),
     /* 301157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301159 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 301161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 301166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 301170 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 301173 */     GIR_RootConstrainSelectedInstOperands,
     /* 301174 */     // GIR_Coverage, 2064,
     /* 301174 */     GIR_EraseRootFromParent_Done,
     /* 301175 */   // Label 5986: @301175
     /* 301175 */   GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(301294), // Rule ID 13810 //
     /* 301180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301191 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301194 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301199 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301203 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301207 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301212 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301216 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 301220 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301224 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 301228 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 301232 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301236 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 301240 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301245 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 301249 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301253 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301257 */     // MIs[4] Operand 1
     /* 301257 */     // No operand predicates
     /* 301257 */     // MIs[2] Operand 2
     /* 301257 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 301268 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301272 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 301274 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 301277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 301281 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301285 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 301289 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 301292 */     GIR_RootConstrainSelectedInstOperands,
     /* 301293 */     // GIR_Coverage, 13810,
     /* 301293 */     GIR_EraseRootFromParent_Done,
     /* 301294 */   // Label 5987: @301294
     /* 301294 */   GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(301413), // Rule ID 2062 //
     /* 301299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 301310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301314 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301317 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301322 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301326 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301330 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301335 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301339 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 301343 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301347 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 301351 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 301355 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301359 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 301363 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301368 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 301372 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301376 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301380 */     // MIs[4] Operand 1
     /* 301380 */     // No operand predicates
     /* 301380 */     // MIs[2] Operand 2
     /* 301380 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 301391 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 301393 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 301396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301398 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 301400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 301408 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 301411 */     GIR_RootConstrainSelectedInstOperands,
     /* 301412 */     // GIR_Coverage, 2062,
     /* 301412 */     GIR_EraseRootFromParent_Done,
     /* 301413 */   // Label 5988: @301413
     /* 301413 */   GIM_Try, /*On fail goto*//*Label 5989*/ GIMT_Encode4(301484), // Rule ID 13710 //
     /* 301418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301429 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301432 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301437 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301441 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301445 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301449 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301451 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301458 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301465 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 301465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_v2i64),
     /* 301468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301470 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 301472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 301477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 301482 */     GIR_RootConstrainSelectedInstOperands,
     /* 301483 */     // GIR_Coverage, 13710,
     /* 301483 */     GIR_EraseRootFromParent_Done,
     /* 301484 */   // Label 5989: @301484
     /* 301484 */   GIM_Try, /*On fail goto*//*Label 5990*/ GIMT_Encode4(301555), // Rule ID 1749 //
     /* 301489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301492 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 301500 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301504 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301507 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301512 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301516 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301520 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301522 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301529 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 301536 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SQDMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 301536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_v2i64),
     /* 301539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301541 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 301543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 301548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 301553 */     GIR_RootConstrainSelectedInstOperands,
     /* 301554 */     // GIR_Coverage, 1749,
     /* 301554 */     GIR_EraseRootFromParent_Done,
     /* 301555 */   // Label 5990: @301555
     /* 301555 */   GIM_Try, /*On fail goto*//*Label 5991*/ GIMT_Encode4(301651), // Rule ID 13811 //
     /* 301560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301563 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301567 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301571 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301574 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301579 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301583 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301587 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301592 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301596 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 301600 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301604 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 301608 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301613 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 301617 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301621 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301625 */     // MIs[3] Operand 1
     /* 301625 */     // No operand predicates
     /* 301625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301629 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301631 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 301634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 301638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 301646 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 301649 */     GIR_RootConstrainSelectedInstOperands,
     /* 301650 */     // GIR_Coverage, 13811,
     /* 301650 */     GIR_EraseRootFromParent_Done,
     /* 301651 */   // Label 5991: @301651
     /* 301651 */   GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(301747), // Rule ID 2063 //
     /* 301656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301659 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 301667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301671 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301674 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301679 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301683 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301687 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 301700 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301704 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 301708 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301713 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 301717 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 301721 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 301725 */     // MIs[3] Operand 1
     /* 301725 */     // No operand predicates
     /* 301725 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301727 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 301727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 301730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301732 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 301734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 301742 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 301745 */     GIR_RootConstrainSelectedInstOperands,
     /* 301746 */     // GIR_Coverage, 2063,
     /* 301746 */     GIR_EraseRootFromParent_Done,
     /* 301747 */   // Label 5992: @301747
     /* 301747 */   GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(301812), // Rule ID 13709 //
     /* 301752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301755 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301759 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301763 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301766 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301771 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301775 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301779 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301784 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301789 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301793 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301795 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 301795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_v2i64),
     /* 301798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 301802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 301810 */     GIR_RootConstrainSelectedInstOperands,
     /* 301811 */     // GIR_Coverage, 13709,
     /* 301811 */     GIR_EraseRootFromParent_Done,
     /* 301812 */   // Label 5993: @301812
     /* 301812 */   GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(301877), // Rule ID 1748 //
     /* 301817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301820 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 301828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301832 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301835 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301840 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301844 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 301848 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301853 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301858 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301860 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 301860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_v2i64),
     /* 301863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 301865 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 301867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 301871 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 301875 */     GIR_RootConstrainSelectedInstOperands,
     /* 301876 */     // GIR_Coverage, 1748,
     /* 301876 */     GIR_EraseRootFromParent_Done,
     /* 301877 */   // Label 5994: @301877
     /* 301877 */   GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(301900), // Rule ID 1426 //
     /* 301882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301885 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301893 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 301893 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i64),
     /* 301898 */     GIR_RootConstrainSelectedInstOperands,
     /* 301899 */     // GIR_Coverage, 1426,
     /* 301899 */     GIR_Done,
     /* 301900 */   // Label 5995: @301900
     /* 301900 */   GIM_Reject,
     /* 301901 */ // Label 5984: @301901
     /* 301901 */ GIM_Reject,
     /* 301902 */ // Label 5972: @301902
     /* 301902 */ GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(301935), // Rule ID 1422 //
     /* 301907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301910 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 301913 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 301916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301920 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301924 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301928 */   // (saddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 301928 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i16),
     /* 301933 */   GIR_RootConstrainSelectedInstOperands,
     /* 301934 */   // GIR_Coverage, 1422,
     /* 301934 */   GIR_Done,
     /* 301935 */ // Label 5996: @301935
     /* 301935 */ GIM_Reject,
     /* 301936 */ // Label 5973: @301936
     /* 301936 */ GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(302921),
     /* 301941 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301944 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 301947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301951 */   GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(302073), // Rule ID 13809 //
     /* 301956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 301967 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 301970 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 301975 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 301979 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 301983 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 301987 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 301991 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301995 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 301999 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302003 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302007 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 302011 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302016 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 302020 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302024 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302028 */     // MIs[4] Operand 1
     /* 302028 */     // No operand predicates
     /* 302028 */     // MIs[2] Operand 2
     /* 302028 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 302039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302043 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 302045 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302052 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_indexed),
     /* 302055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 302059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 302064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 302068 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 302071 */     GIR_RootConstrainSelectedInstOperands,
     /* 302072 */     // GIR_Coverage, 13809,
     /* 302072 */     GIR_EraseRootFromParent_Done,
     /* 302073 */   // Label 5998: @302073
     /* 302073 */   GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(302195), // Rule ID 2061 //
     /* 302078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302081 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 302089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302093 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302096 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302101 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302105 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 302113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 302117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302121 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 302125 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302129 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302133 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 302137 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302142 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 302146 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302150 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302154 */     // MIs[4] Operand 1
     /* 302154 */     // No operand predicates
     /* 302154 */     // MIs[2] Operand 2
     /* 302154 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 302165 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 302167 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302174 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SQDMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_indexed),
     /* 302177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302179 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 302181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 302186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 302190 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 302193 */     GIR_RootConstrainSelectedInstOperands,
     /* 302194 */     // GIR_Coverage, 2061,
     /* 302194 */     GIR_EraseRootFromParent_Done,
     /* 302195 */   // Label 5999: @302195
     /* 302195 */   GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(302314), // Rule ID 13807 //
     /* 302200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302211 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302214 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302219 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302223 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302227 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302232 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 302236 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 302240 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302244 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 302248 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302252 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302256 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 302260 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302265 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 302269 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302273 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302277 */     // MIs[4] Operand 1
     /* 302277 */     // No operand predicates
     /* 302277 */     // MIs[2] Operand 2
     /* 302277 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 302288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302292 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 302294 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 302297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302299 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 302301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 302309 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 302312 */     GIR_RootConstrainSelectedInstOperands,
     /* 302313 */     // GIR_Coverage, 13807,
     /* 302313 */     GIR_EraseRootFromParent_Done,
     /* 302314 */   // Label 6000: @302314
     /* 302314 */   GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(302433), // Rule ID 2059 //
     /* 302319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 302330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302334 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302337 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302342 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302346 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302350 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302355 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 302359 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 302363 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302367 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 302371 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302375 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302379 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 302383 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302388 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 302392 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302396 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302400 */     // MIs[4] Operand 1
     /* 302400 */     // No operand predicates
     /* 302400 */     // MIs[2] Operand 2
     /* 302400 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 302411 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 302413 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 302416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302418 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 302420 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 302428 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 302431 */     GIR_RootConstrainSelectedInstOperands,
     /* 302432 */     // GIR_Coverage, 2059,
     /* 302432 */     GIR_EraseRootFromParent_Done,
     /* 302433 */   // Label 6001: @302433
     /* 302433 */   GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(302504), // Rule ID 13708 //
     /* 302438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302441 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302445 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302449 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302452 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302457 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302461 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302469 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302471 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302478 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302485 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 302485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_v4i32),
     /* 302488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 302492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 302497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 302502 */     GIR_RootConstrainSelectedInstOperands,
     /* 302503 */     // GIR_Coverage, 13708,
     /* 302503 */     GIR_EraseRootFromParent_Done,
     /* 302504 */   // Label 6002: @302504
     /* 302504 */   GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(302575), // Rule ID 1747 //
     /* 302509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302512 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 302520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302524 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302527 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302532 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302536 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302540 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302542 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302549 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 302556 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SQDMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 302556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_v4i32),
     /* 302559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302561 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 302563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 302568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 302573 */     GIR_RootConstrainSelectedInstOperands,
     /* 302574 */     // GIR_Coverage, 1747,
     /* 302574 */     GIR_EraseRootFromParent_Done,
     /* 302575 */   // Label 6003: @302575
     /* 302575 */   GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(302671), // Rule ID 13808 //
     /* 302580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302591 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302594 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302599 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302603 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302607 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302612 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 302616 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302620 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302624 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 302628 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302633 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 302637 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302641 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302645 */     // MIs[3] Operand 1
     /* 302645 */     // No operand predicates
     /* 302645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302649 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 302651 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 302654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302656 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 302658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302662 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 302666 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 302669 */     GIR_RootConstrainSelectedInstOperands,
     /* 302670 */     // GIR_Coverage, 13808,
     /* 302670 */     GIR_EraseRootFromParent_Done,
     /* 302671 */   // Label 6004: @302671
     /* 302671 */   GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(302767), // Rule ID 2060 //
     /* 302676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302679 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 302687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302691 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302694 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302699 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302703 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302707 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302712 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 302716 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 302720 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302724 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 302728 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 302733 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 302737 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 302741 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 302745 */     // MIs[3] Operand 1
     /* 302745 */     // No operand predicates
     /* 302745 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 302747 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 302747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 302750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302752 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 302754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 302762 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 302765 */     GIR_RootConstrainSelectedInstOperands,
     /* 302766 */     // GIR_Coverage, 2060,
     /* 302766 */     GIR_EraseRootFromParent_Done,
     /* 302767 */   // Label 6005: @302767
     /* 302767 */   GIM_Try, /*On fail goto*//*Label 6006*/ GIMT_Encode4(302832), // Rule ID 13707 //
     /* 302772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302783 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302786 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302791 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302795 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302799 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302804 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302813 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302815 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 302815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_v4i32),
     /* 302818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 302822 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 302830 */     GIR_RootConstrainSelectedInstOperands,
     /* 302831 */     // GIR_Coverage, 13707,
     /* 302831 */     GIR_EraseRootFromParent_Done,
     /* 302832 */   // Label 6006: @302832
     /* 302832 */   GIM_Try, /*On fail goto*//*Label 6007*/ GIMT_Encode4(302897), // Rule ID 1746 //
     /* 302837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302840 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 302848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 302852 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 302855 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 302860 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302864 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 302868 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302878 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302880 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 302880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_v4i32),
     /* 302883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 302885 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 302887 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 302891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 302895 */     GIR_RootConstrainSelectedInstOperands,
     /* 302896 */     // GIR_Coverage, 1746,
     /* 302896 */     GIR_EraseRootFromParent_Done,
     /* 302897 */   // Label 6007: @302897
     /* 302897 */   GIM_Try, /*On fail goto*//*Label 6008*/ GIMT_Encode4(302920), // Rule ID 1425 //
     /* 302902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302905 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302909 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302913 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 302913 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i32),
     /* 302918 */     GIR_RootConstrainSelectedInstOperands,
     /* 302919 */     // GIR_Coverage, 1425,
     /* 302919 */     GIR_Done,
     /* 302920 */   // Label 6008: @302920
     /* 302920 */   GIM_Reject,
     /* 302921 */ // Label 5997: @302921
     /* 302921 */ GIM_Reject,
     /* 302922 */ // Label 5974: @302922
     /* 302922 */ GIM_Try, /*On fail goto*//*Label 6009*/ GIMT_Encode4(302955), // Rule ID 1420 //
     /* 302927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 302933 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 302936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302944 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302948 */   // (saddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 302948 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i8),
     /* 302953 */   GIR_RootConstrainSelectedInstOperands,
     /* 302954 */   // GIR_Coverage, 1420,
     /* 302954 */   GIR_Done,
     /* 302955 */ // Label 6009: @302955
     /* 302955 */ GIM_Reject,
     /* 302956 */ // Label 5975: @302956
     /* 302956 */ GIM_Try, /*On fail goto*//*Label 6010*/ GIMT_Encode4(302989), // Rule ID 1423 //
     /* 302961 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302964 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302967 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 302970 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302974 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302978 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302982 */   // (saddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 302982 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i16),
     /* 302987 */   GIR_RootConstrainSelectedInstOperands,
     /* 302988 */   // GIR_Coverage, 1423,
     /* 302988 */   GIR_Done,
     /* 302989 */ // Label 6010: @302989
     /* 302989 */ GIM_Reject,
     /* 302990 */ // Label 5976: @302990
     /* 302990 */ GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(303023), // Rule ID 1421 //
     /* 302995 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302998 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 303001 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 303004 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303008 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303012 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303016 */   // (saddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 303016 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv16i8),
     /* 303021 */   GIR_RootConstrainSelectedInstOperands,
     /* 303022 */   // GIR_Coverage, 1421,
     /* 303022 */   GIR_Done,
     /* 303023 */ // Label 6011: @303023
     /* 303023 */ GIM_Reject,
     /* 303024 */ // Label 5977: @303024
     /* 303024 */ GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(303049), // Rule ID 7541 //
     /* 303029 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303032 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 303035 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 303038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303042 */   // (saddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 303042 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_D),
     /* 303047 */   GIR_RootConstrainSelectedInstOperands,
     /* 303048 */   // GIR_Coverage, 7541,
     /* 303048 */   GIR_Done,
     /* 303049 */ // Label 6012: @303049
     /* 303049 */ GIM_Reject,
     /* 303050 */ // Label 5978: @303050
     /* 303050 */ GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(303075), // Rule ID 7540 //
     /* 303055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303058 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 303061 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 303064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303068 */   // (saddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 303068 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_S),
     /* 303073 */   GIR_RootConstrainSelectedInstOperands,
     /* 303074 */   // GIR_Coverage, 7540,
     /* 303074 */   GIR_Done,
     /* 303075 */ // Label 6013: @303075
     /* 303075 */ GIM_Reject,
     /* 303076 */ // Label 5979: @303076
     /* 303076 */ GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(303101), // Rule ID 7539 //
     /* 303081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303084 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 303087 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 303090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303094 */   // (saddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 303094 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_H),
     /* 303099 */   GIR_RootConstrainSelectedInstOperands,
     /* 303100 */   // GIR_Coverage, 7539,
     /* 303100 */   GIR_Done,
     /* 303101 */ // Label 6014: @303101
     /* 303101 */ GIM_Reject,
     /* 303102 */ // Label 5980: @303102
     /* 303102 */ GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(303127), // Rule ID 7538 //
     /* 303107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303110 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 303113 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 303116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303120 */   // (saddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 303120 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_B),
     /* 303125 */   GIR_RootConstrainSelectedInstOperands,
     /* 303126 */   // GIR_Coverage, 7538,
     /* 303126 */   GIR_Done,
     /* 303127 */ // Label 6015: @303127
     /* 303127 */ GIM_Reject,
     /* 303128 */ // Label 5981: @303128
     /* 303128 */ GIM_Reject,
     /* 303129 */ // Label 57: @303129
     /* 303129 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6028*/ GIMT_Encode4(303600),
     /* 303140 */ /*GILLT_s64*//*Label 6016*/ GIMT_Encode4(303224), GIMT_Encode4(0),
     /* 303148 */ /*GILLT_v2s32*//*Label 6017*/ GIMT_Encode4(303258),
     /* 303152 */ /*GILLT_v2s64*//*Label 6018*/ GIMT_Encode4(303292),
     /* 303156 */ /*GILLT_v4s16*//*Label 6019*/ GIMT_Encode4(303326),
     /* 303160 */ /*GILLT_v4s32*//*Label 6020*/ GIMT_Encode4(303360),
     /* 303164 */ /*GILLT_v8s8*//*Label 6021*/ GIMT_Encode4(303394),
     /* 303168 */ /*GILLT_v8s16*//*Label 6022*/ GIMT_Encode4(303428),
     /* 303172 */ /*GILLT_v16s8*//*Label 6023*/ GIMT_Encode4(303462), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 303192 */ /*GILLT_nxv2s64*//*Label 6024*/ GIMT_Encode4(303496), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 303204 */ /*GILLT_nxv4s32*//*Label 6025*/ GIMT_Encode4(303522), GIMT_Encode4(0),
     /* 303212 */ /*GILLT_nxv8s16*//*Label 6026*/ GIMT_Encode4(303548), GIMT_Encode4(0),
     /* 303220 */ /*GILLT_nxv16s8*//*Label 6027*/ GIMT_Encode4(303574),
     /* 303224 */ // Label 6016: @303224
     /* 303224 */ GIM_Try, /*On fail goto*//*Label 6029*/ GIMT_Encode4(303257), // Rule ID 1652 //
     /* 303229 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303232 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 303235 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 303238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303242 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303246 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303250 */   // (usubsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 303250 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
     /* 303255 */   GIR_RootConstrainSelectedInstOperands,
     /* 303256 */   // GIR_Coverage, 1652,
     /* 303256 */   GIR_Done,
     /* 303257 */ // Label 6029: @303257
     /* 303257 */ GIM_Reject,
     /* 303258 */ // Label 6017: @303258
     /* 303258 */ GIM_Try, /*On fail goto*//*Label 6030*/ GIMT_Encode4(303291), // Rule ID 1568 //
     /* 303263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303266 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 303269 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 303272 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303276 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303280 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303284 */   // (usubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 303284 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i32),
     /* 303289 */   GIR_RootConstrainSelectedInstOperands,
     /* 303290 */   // GIR_Coverage, 1568,
     /* 303290 */   GIR_Done,
     /* 303291 */ // Label 6030: @303291
     /* 303291 */ GIM_Reject,
     /* 303292 */ // Label 6018: @303292
     /* 303292 */ GIM_Try, /*On fail goto*//*Label 6031*/ GIMT_Encode4(303325), // Rule ID 1570 //
     /* 303297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303300 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 303303 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 303306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303310 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303314 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303318 */   // (usubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 303318 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i64),
     /* 303323 */   GIR_RootConstrainSelectedInstOperands,
     /* 303324 */   // GIR_Coverage, 1570,
     /* 303324 */   GIR_Done,
     /* 303325 */ // Label 6031: @303325
     /* 303325 */ GIM_Reject,
     /* 303326 */ // Label 6019: @303326
     /* 303326 */ GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(303359), // Rule ID 1566 //
     /* 303331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 303337 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 303340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303344 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303348 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303352 */   // (usubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 303352 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i16),
     /* 303357 */   GIR_RootConstrainSelectedInstOperands,
     /* 303358 */   // GIR_Coverage, 1566,
     /* 303358 */   GIR_Done,
     /* 303359 */ // Label 6032: @303359
     /* 303359 */ GIM_Reject,
     /* 303360 */ // Label 6020: @303360
     /* 303360 */ GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(303393), // Rule ID 1569 //
     /* 303365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303371 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 303374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303382 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303386 */   // (usubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 303386 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i32),
     /* 303391 */   GIR_RootConstrainSelectedInstOperands,
     /* 303392 */   // GIR_Coverage, 1569,
     /* 303392 */   GIR_Done,
     /* 303393 */ // Label 6033: @303393
     /* 303393 */ GIM_Reject,
     /* 303394 */ // Label 6021: @303394
     /* 303394 */ GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(303427), // Rule ID 1564 //
     /* 303399 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 303405 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 303408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303412 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303416 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303420 */   // (usubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 303420 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i8),
     /* 303425 */   GIR_RootConstrainSelectedInstOperands,
     /* 303426 */   // GIR_Coverage, 1564,
     /* 303426 */   GIR_Done,
     /* 303427 */ // Label 6034: @303427
     /* 303427 */ GIM_Reject,
     /* 303428 */ // Label 6022: @303428
     /* 303428 */ GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(303461), // Rule ID 1567 //
     /* 303433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 303439 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 303442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303446 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303450 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303454 */   // (usubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 303454 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i16),
     /* 303459 */   GIR_RootConstrainSelectedInstOperands,
     /* 303460 */   // GIR_Coverage, 1567,
     /* 303460 */   GIR_Done,
     /* 303461 */ // Label 6035: @303461
     /* 303461 */ GIM_Reject,
     /* 303462 */ // Label 6023: @303462
     /* 303462 */ GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(303495), // Rule ID 1565 //
     /* 303467 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303470 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 303473 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 303476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303480 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303484 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303488 */   // (usubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 303488 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv16i8),
     /* 303493 */   GIR_RootConstrainSelectedInstOperands,
     /* 303494 */   // GIR_Coverage, 1565,
     /* 303494 */   GIR_Done,
     /* 303495 */ // Label 6036: @303495
     /* 303495 */ GIM_Reject,
     /* 303496 */ // Label 6024: @303496
     /* 303496 */ GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(303521), // Rule ID 7553 //
     /* 303501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303504 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 303507 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 303510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303514 */   // (usubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 303514 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_D),
     /* 303519 */   GIR_RootConstrainSelectedInstOperands,
     /* 303520 */   // GIR_Coverage, 7553,
     /* 303520 */   GIR_Done,
     /* 303521 */ // Label 6037: @303521
     /* 303521 */ GIM_Reject,
     /* 303522 */ // Label 6025: @303522
     /* 303522 */ GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(303547), // Rule ID 7552 //
     /* 303527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303530 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 303533 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 303536 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303540 */   // (usubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 303540 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_S),
     /* 303545 */   GIR_RootConstrainSelectedInstOperands,
     /* 303546 */   // GIR_Coverage, 7552,
     /* 303546 */   GIR_Done,
     /* 303547 */ // Label 6038: @303547
     /* 303547 */ GIM_Reject,
     /* 303548 */ // Label 6026: @303548
     /* 303548 */ GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(303573), // Rule ID 7551 //
     /* 303553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303556 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 303559 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 303562 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303566 */   // (usubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 303566 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_H),
     /* 303571 */   GIR_RootConstrainSelectedInstOperands,
     /* 303572 */   // GIR_Coverage, 7551,
     /* 303572 */   GIR_Done,
     /* 303573 */ // Label 6039: @303573
     /* 303573 */ GIM_Reject,
     /* 303574 */ // Label 6027: @303574
     /* 303574 */ GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(303599), // Rule ID 7550 //
     /* 303579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 303582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 303585 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 303588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 303592 */   // (usubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 303592 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_B),
     /* 303597 */   GIR_RootConstrainSelectedInstOperands,
     /* 303598 */   // GIR_Coverage, 7550,
     /* 303598 */   GIR_Done,
     /* 303599 */ // Label 6040: @303599
     /* 303599 */ GIM_Reject,
     /* 303600 */ // Label 6028: @303600
     /* 303600 */ GIM_Reject,
     /* 303601 */ // Label 58: @303601
     /* 303601 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6053*/ GIMT_Encode4(304990),
     /* 303612 */ /*GILLT_s64*//*Label 6041*/ GIMT_Encode4(303696), GIMT_Encode4(0),
     /* 303620 */ /*GILLT_v2s32*//*Label 6042*/ GIMT_Encode4(303730),
     /* 303624 */ /*GILLT_v2s64*//*Label 6043*/ GIMT_Encode4(303764),
     /* 303628 */ /*GILLT_v4s16*//*Label 6044*/ GIMT_Encode4(304257),
     /* 303632 */ /*GILLT_v4s32*//*Label 6045*/ GIMT_Encode4(304291),
     /* 303636 */ /*GILLT_v8s8*//*Label 6046*/ GIMT_Encode4(304784),
     /* 303640 */ /*GILLT_v8s16*//*Label 6047*/ GIMT_Encode4(304818),
     /* 303644 */ /*GILLT_v16s8*//*Label 6048*/ GIMT_Encode4(304852), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 303664 */ /*GILLT_nxv2s64*//*Label 6049*/ GIMT_Encode4(304886), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 303676 */ /*GILLT_nxv4s32*//*Label 6050*/ GIMT_Encode4(304912), GIMT_Encode4(0),
     /* 303684 */ /*GILLT_nxv8s16*//*Label 6051*/ GIMT_Encode4(304938), GIMT_Encode4(0),
     /* 303692 */ /*GILLT_nxv16s8*//*Label 6052*/ GIMT_Encode4(304964),
     /* 303696 */ // Label 6041: @303696
     /* 303696 */ GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(303729), // Rule ID 1645 //
     /* 303701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303704 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 303707 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 303710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303714 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303718 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303722 */   // (ssubsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 303722 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
     /* 303727 */   GIR_RootConstrainSelectedInstOperands,
     /* 303728 */   // GIR_Coverage, 1645,
     /* 303728 */   GIR_Done,
     /* 303729 */ // Label 6054: @303729
     /* 303729 */ GIM_Reject,
     /* 303730 */ // Label 6042: @303730
     /* 303730 */ GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(303763), // Rule ID 1453 //
     /* 303735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303738 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 303741 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 303744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303748 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303752 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303756 */   // (ssubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 303756 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i32),
     /* 303761 */   GIR_RootConstrainSelectedInstOperands,
     /* 303762 */   // GIR_Coverage, 1453,
     /* 303762 */   GIR_Done,
     /* 303763 */ // Label 6055: @303763
     /* 303763 */ GIM_Reject,
     /* 303764 */ // Label 6043: @303764
     /* 303764 */ GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(304256),
     /* 303769 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 303772 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 303775 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303779 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303783 */   GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(303901), // Rule ID 2071 //
     /* 303788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303791 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 303795 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 303799 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 303802 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 303807 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 303811 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 303815 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 303819 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 303823 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303827 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 303831 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 303835 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303839 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 303843 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303848 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 303852 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 303856 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 303860 */     // MIs[4] Operand 1
     /* 303860 */     // No operand predicates
     /* 303860 */     // MIs[2] Operand 2
     /* 303860 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 303871 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 303873 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 303880 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SQDMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 303880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i32_indexed),
     /* 303883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 303885 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 303887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 303892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 303896 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 303899 */     GIR_RootConstrainSelectedInstOperands,
     /* 303900 */     // GIR_Coverage, 2071,
     /* 303900 */     GIR_EraseRootFromParent_Done,
     /* 303901 */   // Label 6057: @303901
     /* 303901 */   GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(304016), // Rule ID 2069 //
     /* 303906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 303913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 303917 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 303920 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 303925 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 303929 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 303933 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303938 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 303942 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 303946 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303950 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 303954 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 303958 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303962 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 303966 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303971 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 303975 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 303979 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 303983 */     // MIs[4] Operand 1
     /* 303983 */     // No operand predicates
     /* 303983 */     // MIs[2] Operand 2
     /* 303983 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 303994 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 303996 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 303996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_indexed),
     /* 303999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304001 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304003 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 304011 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 304014 */     GIR_RootConstrainSelectedInstOperands,
     /* 304015 */     // GIR_Coverage, 2069,
     /* 304015 */     GIR_EraseRootFromParent_Done,
     /* 304016 */   // Label 6058: @304016
     /* 304016 */   GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(304083), // Rule ID 1753 //
     /* 304021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304032 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304035 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304040 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 304044 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 304048 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304050 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 304057 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 304064 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SQDMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 304064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i32_v2i64),
     /* 304067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304069 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 304076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 304081 */     GIR_RootConstrainSelectedInstOperands,
     /* 304082 */     // GIR_Coverage, 1753,
     /* 304082 */     GIR_EraseRootFromParent_Done,
     /* 304083 */   // Label 6059: @304083
     /* 304083 */   GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(304175), // Rule ID 2070 //
     /* 304088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304091 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304095 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304099 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304102 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304107 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 304111 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 304115 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304120 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 304124 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 304128 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 304132 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 304136 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304141 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 304145 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 304149 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 304153 */     // MIs[3] Operand 1
     /* 304153 */     // No operand predicates
     /* 304153 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 304155 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 304155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_indexed),
     /* 304158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304160 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 304170 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 304173 */     GIR_RootConstrainSelectedInstOperands,
     /* 304174 */     // GIR_Coverage, 2070,
     /* 304174 */     GIR_EraseRootFromParent_Done,
     /* 304175 */   // Label 6060: @304175
     /* 304175 */   GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(304236), // Rule ID 1752 //
     /* 304180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304191 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304194 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304199 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 304203 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 304207 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304212 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304217 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304219 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 693:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 304219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_v2i64),
     /* 304222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304224 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304226 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304230 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 304234 */     GIR_RootConstrainSelectedInstOperands,
     /* 304235 */     // GIR_Coverage, 1752,
     /* 304235 */     GIR_EraseRootFromParent_Done,
     /* 304236 */   // Label 6061: @304236
     /* 304236 */   GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(304255), // Rule ID 1455 //
     /* 304241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304244 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304248 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 304248 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i64),
     /* 304253 */     GIR_RootConstrainSelectedInstOperands,
     /* 304254 */     // GIR_Coverage, 1455,
     /* 304254 */     GIR_Done,
     /* 304255 */   // Label 6062: @304255
     /* 304255 */   GIM_Reject,
     /* 304256 */ // Label 6056: @304256
     /* 304256 */ GIM_Reject,
     /* 304257 */ // Label 6044: @304257
     /* 304257 */ GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(304290), // Rule ID 1451 //
     /* 304262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 304268 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304275 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304279 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304283 */   // (ssubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 304283 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i16),
     /* 304288 */   GIR_RootConstrainSelectedInstOperands,
     /* 304289 */   // GIR_Coverage, 1451,
     /* 304289 */   GIR_Done,
     /* 304290 */ // Label 6063: @304290
     /* 304290 */ GIM_Reject,
     /* 304291 */ // Label 6045: @304291
     /* 304291 */ GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(304783),
     /* 304296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 304299 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 304302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304306 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304310 */   GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(304428), // Rule ID 2068 //
     /* 304315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304326 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304329 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304338 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 304342 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 304346 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 304350 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304354 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 304358 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 304362 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304366 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 304370 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 304375 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 304379 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 304383 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 304387 */     // MIs[4] Operand 1
     /* 304387 */     // No operand predicates
     /* 304387 */     // MIs[2] Operand 2
     /* 304387 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 304398 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 304400 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 304407 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SQDMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 304407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv8i16_indexed),
     /* 304410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304412 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 304419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 304423 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 304426 */     GIR_RootConstrainSelectedInstOperands,
     /* 304427 */     // GIR_Coverage, 2068,
     /* 304427 */     GIR_EraseRootFromParent_Done,
     /* 304428 */   // Label 6065: @304428
     /* 304428 */   GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(304543), // Rule ID 2066 //
     /* 304433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304444 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304447 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304452 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304456 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 304460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304465 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 304469 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 304473 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304477 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 304481 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 304485 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304489 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 304493 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 304498 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 304502 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 304506 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 304510 */     // MIs[4] Operand 1
     /* 304510 */     // No operand predicates
     /* 304510 */     // MIs[2] Operand 2
     /* 304510 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 304521 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 304523 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 304523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_indexed),
     /* 304526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304528 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304530 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304534 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 304538 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 304541 */     GIR_RootConstrainSelectedInstOperands,
     /* 304542 */     // GIR_Coverage, 2066,
     /* 304542 */     GIR_EraseRootFromParent_Done,
     /* 304543 */   // Label 6066: @304543
     /* 304543 */   GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(304610), // Rule ID 1751 //
     /* 304548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304559 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304562 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304567 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304571 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 304575 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304577 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 304584 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 304591 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SQDMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 304591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv8i16_v4i32),
     /* 304594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304596 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 304603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 304608 */     GIR_RootConstrainSelectedInstOperands,
     /* 304609 */     // GIR_Coverage, 1751,
     /* 304609 */     GIR_EraseRootFromParent_Done,
     /* 304610 */   // Label 6067: @304610
     /* 304610 */   GIM_Try, /*On fail goto*//*Label 6068*/ GIMT_Encode4(304702), // Rule ID 2067 //
     /* 304615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304626 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304629 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304634 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304638 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 304642 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304647 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 304651 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 304655 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304659 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 304663 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 304668 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 304672 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 304676 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 304680 */     // MIs[3] Operand 1
     /* 304680 */     // No operand predicates
     /* 304680 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 304682 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 304682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_indexed),
     /* 304685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304687 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304693 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 304697 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 304700 */     GIR_RootConstrainSelectedInstOperands,
     /* 304701 */     // GIR_Coverage, 2067,
     /* 304701 */     GIR_EraseRootFromParent_Done,
     /* 304702 */   // Label 6068: @304702
     /* 304702 */   GIM_Try, /*On fail goto*//*Label 6069*/ GIMT_Encode4(304763), // Rule ID 1750 //
     /* 304707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 304714 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304718 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 304721 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 304726 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304730 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 304734 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304739 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304744 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304746 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 693:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 304746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_v4i32),
     /* 304749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 304751 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 304753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 304761 */     GIR_RootConstrainSelectedInstOperands,
     /* 304762 */     // GIR_Coverage, 1750,
     /* 304762 */     GIR_EraseRootFromParent_Done,
     /* 304763 */   // Label 6069: @304763
     /* 304763 */   GIM_Try, /*On fail goto*//*Label 6070*/ GIMT_Encode4(304782), // Rule ID 1454 //
     /* 304768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304771 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304775 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 304775 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i32),
     /* 304780 */     GIR_RootConstrainSelectedInstOperands,
     /* 304781 */     // GIR_Coverage, 1454,
     /* 304781 */     GIR_Done,
     /* 304782 */   // Label 6070: @304782
     /* 304782 */   GIM_Reject,
     /* 304783 */ // Label 6064: @304783
     /* 304783 */ GIM_Reject,
     /* 304784 */ // Label 6046: @304784
     /* 304784 */ GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(304817), // Rule ID 1449 //
     /* 304789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304792 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 304795 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 304798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304802 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304806 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304810 */   // (ssubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 304810 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i8),
     /* 304815 */   GIR_RootConstrainSelectedInstOperands,
     /* 304816 */   // GIR_Coverage, 1449,
     /* 304816 */   GIR_Done,
     /* 304817 */ // Label 6071: @304817
     /* 304817 */ GIM_Reject,
     /* 304818 */ // Label 6047: @304818
     /* 304818 */ GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(304851), // Rule ID 1452 //
     /* 304823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304826 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 304829 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 304832 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304836 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304840 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304844 */   // (ssubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 304844 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i16),
     /* 304849 */   GIR_RootConstrainSelectedInstOperands,
     /* 304850 */   // GIR_Coverage, 1452,
     /* 304850 */   GIR_Done,
     /* 304851 */ // Label 6072: @304851
     /* 304851 */ GIM_Reject,
     /* 304852 */ // Label 6048: @304852
     /* 304852 */ GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(304885), // Rule ID 1450 //
     /* 304857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 304860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 304863 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 304866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304870 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304874 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304878 */   // (ssubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 304878 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv16i8),
     /* 304883 */   GIR_RootConstrainSelectedInstOperands,
     /* 304884 */   // GIR_Coverage, 1450,
     /* 304884 */   GIR_Done,
     /* 304885 */ // Label 6073: @304885
     /* 304885 */ GIM_Reject,
     /* 304886 */ // Label 6049: @304886
     /* 304886 */ GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(304911), // Rule ID 7549 //
     /* 304891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 304894 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 304897 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 304900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 304904 */   // (ssubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 304904 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_D),
     /* 304909 */   GIR_RootConstrainSelectedInstOperands,
     /* 304910 */   // GIR_Coverage, 7549,
     /* 304910 */   GIR_Done,
     /* 304911 */ // Label 6074: @304911
     /* 304911 */ GIM_Reject,
     /* 304912 */ // Label 6050: @304912
     /* 304912 */ GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(304937), // Rule ID 7548 //
     /* 304917 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 304920 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 304923 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 304926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 304930 */   // (ssubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 304930 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_S),
     /* 304935 */   GIR_RootConstrainSelectedInstOperands,
     /* 304936 */   // GIR_Coverage, 7548,
     /* 304936 */   GIR_Done,
     /* 304937 */ // Label 6075: @304937
     /* 304937 */ GIM_Reject,
     /* 304938 */ // Label 6051: @304938
     /* 304938 */ GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(304963), // Rule ID 7547 //
     /* 304943 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 304946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 304949 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 304952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 304956 */   // (ssubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 304956 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_H),
     /* 304961 */   GIR_RootConstrainSelectedInstOperands,
     /* 304962 */   // GIR_Coverage, 7547,
     /* 304962 */   GIR_Done,
     /* 304963 */ // Label 6076: @304963
     /* 304963 */ GIM_Reject,
     /* 304964 */ // Label 6052: @304964
     /* 304964 */ GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(304989), // Rule ID 7546 //
     /* 304969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 304972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 304975 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 304978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 304982 */   // (ssubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 304982 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_B),
     /* 304987 */   GIR_RootConstrainSelectedInstOperands,
     /* 304988 */   // GIR_Coverage, 7546,
     /* 304988 */   GIR_Done,
     /* 304989 */ // Label 6077: @304989
     /* 304989 */ GIM_Reject,
     /* 304990 */ // Label 6053: @304990
     /* 304990 */ GIM_Reject,
     /* 304991 */ // Label 59: @304991
     /* 304991 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6089*/ GIMT_Encode4(306788),
     /* 305002 */ /*GILLT_s16*//*Label 6078*/ GIMT_Encode4(305086),
     /* 305006 */ /*GILLT_s32*//*Label 6079*/ GIMT_Encode4(305312),
     /* 305010 */ /*GILLT_s64*//*Label 6080*/ GIMT_Encode4(305666), GIMT_Encode4(0),
     /* 305018 */ /*GILLT_v2s32*//*Label 6081*/ GIMT_Encode4(305838),
     /* 305022 */ /*GILLT_v2s64*//*Label 6082*/ GIMT_Encode4(305876),
     /* 305026 */ /*GILLT_v4s16*//*Label 6083*/ GIMT_Encode4(306052),
     /* 305030 */ /*GILLT_v4s32*//*Label 6084*/ GIMT_Encode4(306090), GIMT_Encode4(0),
     /* 305038 */ /*GILLT_v8s16*//*Label 6085*/ GIMT_Encode4(306266), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 305062 */ /*GILLT_nxv2s64*//*Label 6086*/ GIMT_Encode4(306710), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 305074 */ /*GILLT_nxv4s32*//*Label 6087*/ GIMT_Encode4(306736), GIMT_Encode4(0),
     /* 305082 */ /*GILLT_nxv8s16*//*Label 6088*/ GIMT_Encode4(306762),
     /* 305086 */ // Label 6078: @305086
     /* 305086 */ GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(305311),
     /* 305091 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 305094 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 305097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 305101 */   GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(305192), // Rule ID 6995 //
     /* 305106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 305118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305122 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305127 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 305131 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305135 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305139 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305143 */     // MIs[2] Rn
     /* 305143 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305148 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 305152 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305154 */     // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 305154 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 305157 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 305161 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305166 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 305172 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305177 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 305185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305187 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305190 */     GIR_RootConstrainSelectedInstOperands,
     /* 305191 */     // GIR_Coverage, 6995,
     /* 305191 */     GIR_EraseRootFromParent_Done,
     /* 305192 */   // Label 6091: @305192
     /* 305192 */   GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(305283), // Rule ID 14251 //
     /* 305197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305201 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305205 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 305209 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305213 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305218 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 305222 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305226 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305230 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305234 */     // MIs[2] Rn
     /* 305234 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305239 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 305243 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305245 */     // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 305245 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 305248 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 305252 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305257 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 305263 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305268 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 305276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305278 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305281 */     GIR_RootConstrainSelectedInstOperands,
     /* 305282 */     // GIR_Coverage, 14251,
     /* 305282 */     GIR_EraseRootFromParent_Done,
     /* 305283 */   // Label 6092: @305283
     /* 305283 */   GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(305310), // Rule ID 588 //
     /* 305288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 305291 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 305295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 305299 */     // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 305299 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
     /* 305304 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 305308 */     GIR_RootConstrainSelectedInstOperands,
     /* 305309 */     // GIR_Coverage, 588,
     /* 305309 */     GIR_Done,
     /* 305310 */   // Label 6093: @305310
     /* 305310 */   GIM_Reject,
     /* 305311 */ // Label 6090: @305311
     /* 305311 */ GIM_Reject,
     /* 305312 */ // Label 6079: @305312
     /* 305312 */ GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(305665),
     /* 305317 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 305320 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 305323 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 305327 */   GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(305418), // Rule ID 6993 //
     /* 305332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 305344 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305348 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305353 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 305357 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305361 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305365 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305369 */     // MIs[2] Rn
     /* 305369 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305374 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 305378 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305380 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 305380 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 305383 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 305387 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305392 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 305398 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305403 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 305411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305413 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305416 */     GIR_RootConstrainSelectedInstOperands,
     /* 305417 */     // GIR_Coverage, 6993,
     /* 305417 */     GIR_EraseRootFromParent_Done,
     /* 305418 */   // Label 6095: @305418
     /* 305418 */   GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(305482), // Rule ID 13416 //
     /* 305423 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305427 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305431 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 305435 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305439 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305444 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 305448 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305452 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305456 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305460 */     // MIs[2] Rn
     /* 305460 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305465 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 305469 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305471 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
     /* 305471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 305474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305476 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305480 */     GIR_RootConstrainSelectedInstOperands,
     /* 305481 */     // GIR_Coverage, 13416,
     /* 305481 */     GIR_EraseRootFromParent_Done,
     /* 305482 */   // Label 6096: @305482
     /* 305482 */   GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(305573), // Rule ID 14249 //
     /* 305487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 305499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305503 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305508 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 305512 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305516 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305520 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305524 */     // MIs[2] Rn
     /* 305524 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305529 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 305533 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305535 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 305535 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 305538 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 305542 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305547 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 305553 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305558 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 305566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305568 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305571 */     GIR_RootConstrainSelectedInstOperands,
     /* 305572 */     // GIR_Coverage, 14249,
     /* 305572 */     GIR_EraseRootFromParent_Done,
     /* 305573 */   // Label 6097: @305573
     /* 305573 */   GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(305637), // Rule ID 16425 //
     /* 305578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 305590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305594 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305599 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 305603 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305607 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305611 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305615 */     // MIs[2] Rn
     /* 305615 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305620 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 305624 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305626 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
     /* 305626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 305629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305635 */     GIR_RootConstrainSelectedInstOperands,
     /* 305636 */     // GIR_Coverage, 16425,
     /* 305636 */     GIR_EraseRootFromParent_Done,
     /* 305637 */   // Label 6098: @305637
     /* 305637 */   GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(305664), // Rule ID 590 //
     /* 305642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 305645 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 305649 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 305653 */     // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 305653 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
     /* 305658 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 305662 */     GIR_RootConstrainSelectedInstOperands,
     /* 305663 */     // GIR_Coverage, 590,
     /* 305663 */     GIR_Done,
     /* 305664 */   // Label 6099: @305664
     /* 305664 */   GIM_Reject,
     /* 305665 */ // Label 6094: @305665
     /* 305665 */ GIM_Reject,
     /* 305666 */ // Label 6080: @305666
     /* 305666 */ GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(305837),
     /* 305671 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 305674 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 305677 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305681 */   GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(305745), // Rule ID 6991 //
     /* 305686 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305690 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305694 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 305698 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305707 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 305711 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305715 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305719 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305723 */     // MIs[2] Rn
     /* 305723 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305728 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 305732 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305734 */     // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 305734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 305737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305743 */     GIR_RootConstrainSelectedInstOperands,
     /* 305744 */     // GIR_Coverage, 6991,
     /* 305744 */     GIR_EraseRootFromParent_Done,
     /* 305745 */   // Label 6101: @305745
     /* 305745 */   GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(305809), // Rule ID 14247 //
     /* 305750 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305754 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305758 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 305762 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305766 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305771 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 305775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305779 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305783 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 305787 */     // MIs[2] Rn
     /* 305787 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305792 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 305796 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305798 */     // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 305798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 305801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305807 */     GIR_RootConstrainSelectedInstOperands,
     /* 305808 */     // GIR_Coverage, 14247,
     /* 305808 */     GIR_EraseRootFromParent_Done,
     /* 305809 */   // Label 6102: @305809
     /* 305809 */   GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(305836), // Rule ID 592 //
     /* 305814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 305817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305821 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305825 */     // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 305825 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
     /* 305830 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 305834 */     GIR_RootConstrainSelectedInstOperands,
     /* 305835 */     // GIR_Coverage, 592,
     /* 305835 */     GIR_Done,
     /* 305836 */   // Label 6103: @305836
     /* 305836 */   GIM_Reject,
     /* 305837 */ // Label 6100: @305837
     /* 305837 */ GIM_Reject,
     /* 305838 */ // Label 6081: @305838
     /* 305838 */ GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(305875), // Rule ID 1207 //
     /* 305843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 305846 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 305849 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 305852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305856 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305860 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305864 */   // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 305864 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
     /* 305869 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 305873 */   GIR_RootConstrainSelectedInstOperands,
     /* 305874 */   // GIR_Coverage, 1207,
     /* 305874 */   GIR_Done,
     /* 305875 */ // Label 6104: @305875
     /* 305875 */ GIM_Reject,
     /* 305876 */ // Label 6082: @305876
     /* 305876 */ GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(306051),
     /* 305881 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 305884 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 305887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305891 */   GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(305957), // Rule ID 7013 //
     /* 305896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /* 305904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 305908 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 305912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305917 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305922 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305926 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP2),
     /* 305930 */     // MIs[2] Rn
     /* 305930 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 305935 */     // MIs[2] Rm
     /* 305935 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 305940 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305942 */     // (fadd:{ *:[v2f64] } (AArch64zip1:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm), (AArch64zip2:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm))  =>  (FADDPv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm)
     /* 305942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 305945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305951 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 305955 */     GIR_RootConstrainSelectedInstOperands,
     /* 305956 */     // GIR_Coverage, 7013,
     /* 305956 */     GIR_EraseRootFromParent_Done,
     /* 305957 */   // Label 6106: @305957
     /* 305957 */   GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(306023), // Rule ID 14259 //
     /* 305962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /* 305970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 305974 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 305978 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305983 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 305992 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP1),
     /* 305996 */     // MIs[2] Rn
     /* 305996 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 306001 */     // MIs[2] Rm
     /* 306001 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 306006 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306008 */     // (fadd:{ *:[v2f64] } (AArch64zip2:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm), (AArch64zip1:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm))  =>  (FADDPv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm)
     /* 306008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 306011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306017 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 306021 */     GIR_RootConstrainSelectedInstOperands,
     /* 306022 */     // GIR_Coverage, 14259,
     /* 306022 */     GIR_EraseRootFromParent_Done,
     /* 306023 */   // Label 6107: @306023
     /* 306023 */   GIM_Try, /*On fail goto*//*Label 6108*/ GIMT_Encode4(306050), // Rule ID 1211 //
     /* 306028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306031 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306039 */     // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 306039 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
     /* 306044 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306048 */     GIR_RootConstrainSelectedInstOperands,
     /* 306049 */     // GIR_Coverage, 1211,
     /* 306049 */     GIR_Done,
     /* 306050 */   // Label 6108: @306050
     /* 306050 */   GIM_Reject,
     /* 306051 */ // Label 6105: @306051
     /* 306051 */ GIM_Reject,
     /* 306052 */ // Label 6083: @306052
     /* 306052 */ GIM_Try, /*On fail goto*//*Label 6109*/ GIMT_Encode4(306089), // Rule ID 1203 //
     /* 306057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 306060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 306063 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 306066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306070 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306074 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306078 */   // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 306078 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
     /* 306083 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306087 */   GIR_RootConstrainSelectedInstOperands,
     /* 306088 */   // GIR_Coverage, 1203,
     /* 306088 */   GIR_Done,
     /* 306089 */ // Label 6109: @306089
     /* 306089 */ GIM_Reject,
     /* 306090 */ // Label 6084: @306090
     /* 306090 */ GIM_Try, /*On fail goto*//*Label 6110*/ GIMT_Encode4(306265),
     /* 306095 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 306098 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 306101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306105 */   GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(306171), // Rule ID 7014 //
     /* 306110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /* 306118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 306122 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 306126 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306131 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306136 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 306140 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /* 306144 */     // MIs[2] Rn
     /* 306144 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 306149 */     // MIs[2] Rm
     /* 306149 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 306154 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306156 */     // (fadd:{ *:[v4f32] } (AArch64uzp1:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm), (AArch64uzp2:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm))  =>  (FADDPv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm)
     /* 306156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 306159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306161 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306165 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 306169 */     GIR_RootConstrainSelectedInstOperands,
     /* 306170 */     // GIR_Coverage, 7014,
     /* 306170 */     GIR_EraseRootFromParent_Done,
     /* 306171 */   // Label 6111: @306171
     /* 306171 */   GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(306237), // Rule ID 14260 //
     /* 306176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /* 306184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 306188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 306192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306197 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306202 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 306206 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /* 306210 */     // MIs[2] Rn
     /* 306210 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 306215 */     // MIs[2] Rm
     /* 306215 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 306220 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306222 */     // (fadd:{ *:[v4f32] } (AArch64uzp2:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm), (AArch64uzp1:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm))  =>  (FADDPv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm)
     /* 306222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 306225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 306235 */     GIR_RootConstrainSelectedInstOperands,
     /* 306236 */     // GIR_Coverage, 14260,
     /* 306236 */     GIR_EraseRootFromParent_Done,
     /* 306237 */   // Label 6112: @306237
     /* 306237 */   GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(306264), // Rule ID 1209 //
     /* 306242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306245 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306249 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306253 */     // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 306253 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 306258 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306262 */     GIR_RootConstrainSelectedInstOperands,
     /* 306263 */     // GIR_Coverage, 1209,
     /* 306263 */     GIR_Done,
     /* 306264 */   // Label 6113: @306264
     /* 306264 */   GIM_Reject,
     /* 306265 */ // Label 6110: @306265
     /* 306265 */ GIM_Reject,
     /* 306266 */ // Label 6085: @306266
     /* 306266 */ GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(306709),
     /* 306271 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 306274 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 306277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306281 */   GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(306350), // Rule ID 7015 //
     /* 306286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 306289 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306293 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /* 306297 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 306301 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 306305 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306315 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 306319 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /* 306323 */     // MIs[2] Rn
     /* 306323 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 306328 */     // MIs[2] Rm
     /* 306328 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 306333 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306335 */     // (fadd:{ *:[v8f16] } (AArch64uzp1:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm), (AArch64uzp2:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm))  =>  (FADDPv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm)
     /* 306335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 306338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306344 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 306348 */     GIR_RootConstrainSelectedInstOperands,
     /* 306349 */     // GIR_Coverage, 7015,
     /* 306349 */     GIR_EraseRootFromParent_Done,
     /* 306350 */   // Label 6115: @306350
     /* 306350 */   GIM_Try, /*On fail goto*//*Label 6116*/ GIMT_Encode4(306419), // Rule ID 14261 //
     /* 306355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 306358 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306362 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /* 306366 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 306370 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 306374 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306379 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306384 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 306388 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /* 306392 */     // MIs[2] Rn
     /* 306392 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 306397 */     // MIs[2] Rm
     /* 306397 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 306402 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306404 */     // (fadd:{ *:[v8f16] } (AArch64uzp2:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm), (AArch64uzp1:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm))  =>  (FADDPv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm)
     /* 306404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 306407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306409 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306413 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 306417 */     GIR_RootConstrainSelectedInstOperands,
     /* 306418 */     // GIR_Coverage, 14261,
     /* 306418 */     GIR_EraseRootFromParent_Done,
     /* 306419 */   // Label 6116: @306419
     /* 306419 */   GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(306446), // Rule ID 1205 //
     /* 306424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 306427 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306431 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306435 */     // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 306435 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
     /* 306440 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306444 */     GIR_RootConstrainSelectedInstOperands,
     /* 306445 */     // GIR_Coverage, 1205,
     /* 306445 */     GIR_Done,
     /* 306446 */   // Label 6117: @306446
     /* 306446 */   GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(306708), // Rule ID 7090 //
     /* 306451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 306454 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306462 */     // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 306462 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 306465 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 306469 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306474 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 306478 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 306480 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 306483 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 306487 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306492 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 306496 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 306498 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 306501 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 306505 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306510 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 306513 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 306516 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 306518 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 306521 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306525 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306530 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 306536 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306541 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306546 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 306549 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 306553 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306558 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 306561 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 306563 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 306566 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306570 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306575 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 306581 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306586 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306591 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 306594 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 306598 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306603 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 306606 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 306608 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 306611 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 306615 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306620 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 306623 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 306626 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 306628 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 306631 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 306635 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306640 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 306643 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 306645 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 306648 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 306652 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306657 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 306659 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 306662 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 306666 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306671 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 306674 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 306677 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 306680 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306685 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306690 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 306698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 306700 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 306703 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 306706 */     GIR_RootConstrainSelectedInstOperands,
     /* 306707 */     // GIR_Coverage, 7090,
     /* 306707 */     GIR_EraseRootFromParent_Done,
     /* 306708 */   // Label 6118: @306708
     /* 306708 */   GIM_Reject,
     /* 306709 */ // Label 6114: @306709
     /* 306709 */ GIM_Reject,
     /* 306710 */ // Label 6086: @306710
     /* 306710 */ GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(306735), // Rule ID 2824 //
     /* 306715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 306718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 306721 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 306724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306728 */   // (fadd:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FADD_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 306728 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_D),
     /* 306733 */   GIR_RootConstrainSelectedInstOperands,
     /* 306734 */   // GIR_Coverage, 2824,
     /* 306734 */   GIR_Done,
     /* 306735 */ // Label 6119: @306735
     /* 306735 */ GIM_Reject,
     /* 306736 */ // Label 6087: @306736
     /* 306736 */ GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(306761), // Rule ID 2822 //
     /* 306741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 306744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 306747 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 306750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306754 */   // (fadd:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FADD_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 306754 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_S),
     /* 306759 */   GIR_RootConstrainSelectedInstOperands,
     /* 306760 */   // GIR_Coverage, 2822,
     /* 306760 */   GIR_Done,
     /* 306761 */ // Label 6120: @306761
     /* 306761 */ GIM_Reject,
     /* 306762 */ // Label 6088: @306762
     /* 306762 */ GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(306787), // Rule ID 2820 //
     /* 306767 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 306770 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 306773 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 306776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306780 */   // (fadd:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FADD_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 306780 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_H),
     /* 306785 */   GIR_RootConstrainSelectedInstOperands,
     /* 306786 */   // GIR_Coverage, 2820,
     /* 306786 */   GIR_Done,
     /* 306787 */ // Label 6121: @306787
     /* 306787 */ GIM_Reject,
     /* 306788 */ // Label 6089: @306788
     /* 306788 */ GIM_Reject,
     /* 306789 */ // Label 60: @306789
     /* 306789 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6133*/ GIMT_Encode4(307526),
     /* 306800 */ /*GILLT_s16*//*Label 6122*/ GIMT_Encode4(306884),
     /* 306804 */ /*GILLT_s32*//*Label 6123*/ GIMT_Encode4(306922),
     /* 306808 */ /*GILLT_s64*//*Label 6124*/ GIMT_Encode4(306960), GIMT_Encode4(0),
     /* 306816 */ /*GILLT_v2s32*//*Label 6125*/ GIMT_Encode4(306998),
     /* 306820 */ /*GILLT_v2s64*//*Label 6126*/ GIMT_Encode4(307036),
     /* 306824 */ /*GILLT_v4s16*//*Label 6127*/ GIMT_Encode4(307074),
     /* 306828 */ /*GILLT_v4s32*//*Label 6128*/ GIMT_Encode4(307112), GIMT_Encode4(0),
     /* 306836 */ /*GILLT_v8s16*//*Label 6129*/ GIMT_Encode4(307150), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 306860 */ /*GILLT_nxv2s64*//*Label 6130*/ GIMT_Encode4(307448), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 306872 */ /*GILLT_nxv4s32*//*Label 6131*/ GIMT_Encode4(307474), GIMT_Encode4(0),
     /* 306880 */ /*GILLT_nxv8s16*//*Label 6132*/ GIMT_Encode4(307500),
     /* 306884 */ // Label 6122: @306884
     /* 306884 */ GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(306921), // Rule ID 636 //
     /* 306889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 306892 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 306895 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 306898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 306902 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 306906 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 306910 */   // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 306910 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
     /* 306915 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306919 */   GIR_RootConstrainSelectedInstOperands,
     /* 306920 */   // GIR_Coverage, 636,
     /* 306920 */   GIR_Done,
     /* 306921 */ // Label 6134: @306921
     /* 306921 */ GIM_Reject,
     /* 306922 */ // Label 6123: @306922
     /* 306922 */ GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(306959), // Rule ID 638 //
     /* 306927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 306930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 306933 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 306936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 306940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 306944 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 306948 */   // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 306948 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
     /* 306953 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306957 */   GIR_RootConstrainSelectedInstOperands,
     /* 306958 */   // GIR_Coverage, 638,
     /* 306958 */   GIR_Done,
     /* 306959 */ // Label 6135: @306959
     /* 306959 */ GIM_Reject,
     /* 306960 */ // Label 6124: @306960
     /* 306960 */ GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(306997), // Rule ID 640 //
     /* 306965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 306968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 306971 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 306974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306982 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 306986 */   // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 306986 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
     /* 306991 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 306995 */   GIR_RootConstrainSelectedInstOperands,
     /* 306996 */   // GIR_Coverage, 640,
     /* 306996 */   GIR_Done,
     /* 306997 */ // Label 6136: @306997
     /* 306997 */ GIM_Reject,
     /* 306998 */ // Label 6125: @306998
     /* 306998 */ GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(307035), // Rule ID 1347 //
     /* 307003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 307006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 307009 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 307012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307016 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307020 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307024 */   // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 307024 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
     /* 307029 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 307033 */   GIR_RootConstrainSelectedInstOperands,
     /* 307034 */   // GIR_Coverage, 1347,
     /* 307034 */   GIR_Done,
     /* 307035 */ // Label 6137: @307035
     /* 307035 */ GIM_Reject,
     /* 307036 */ // Label 6126: @307036
     /* 307036 */ GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(307073), // Rule ID 1351 //
     /* 307041 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 307044 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 307047 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 307050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307054 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307058 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307062 */   // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 307062 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
     /* 307067 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 307071 */   GIR_RootConstrainSelectedInstOperands,
     /* 307072 */   // GIR_Coverage, 1351,
     /* 307072 */   GIR_Done,
     /* 307073 */ // Label 6138: @307073
     /* 307073 */ GIM_Reject,
     /* 307074 */ // Label 6127: @307074
     /* 307074 */ GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(307111), // Rule ID 1343 //
     /* 307079 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 307082 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 307085 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 307088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307092 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307096 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307100 */   // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 307100 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
     /* 307105 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 307109 */   GIR_RootConstrainSelectedInstOperands,
     /* 307110 */   // GIR_Coverage, 1343,
     /* 307110 */   GIR_Done,
     /* 307111 */ // Label 6139: @307111
     /* 307111 */ GIM_Reject,
     /* 307112 */ // Label 6128: @307112
     /* 307112 */ GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(307149), // Rule ID 1349 //
     /* 307117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 307120 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 307123 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 307126 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307130 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307134 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307138 */   // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 307138 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 307143 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 307147 */   GIR_RootConstrainSelectedInstOperands,
     /* 307148 */   // GIR_Coverage, 1349,
     /* 307148 */   GIR_Done,
     /* 307149 */ // Label 6140: @307149
     /* 307149 */ GIM_Reject,
     /* 307150 */ // Label 6129: @307150
     /* 307150 */ GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(307447),
     /* 307155 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307158 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 307161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307165 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307169 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307173 */   GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(307192), // Rule ID 1345 //
     /* 307178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 307181 */     // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 307181 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
     /* 307186 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 307190 */     GIR_RootConstrainSelectedInstOperands,
     /* 307191 */     // GIR_Coverage, 1345,
     /* 307191 */     GIR_Done,
     /* 307192 */   // Label 6142: @307192
     /* 307192 */   GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(307446), // Rule ID 7096 //
     /* 307197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 307200 */     // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 307200 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 307203 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 307207 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307212 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 307216 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 307218 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 307221 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 307225 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307230 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 307234 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 307236 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 307239 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 307243 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307248 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 307251 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 307254 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 307256 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 307259 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307263 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307268 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 307274 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307279 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307284 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 307287 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 307291 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307296 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 307299 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 307301 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 307304 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307308 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307313 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 307319 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307324 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307329 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 307332 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 307336 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307341 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 307344 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 307346 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 307349 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 307353 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307358 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 307361 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 307364 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 307366 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 307369 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 307373 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307378 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 307381 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 307383 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 307386 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307390 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307397 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 307400 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 307404 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307409 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 307412 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 307415 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 307418 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307423 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 307436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 307438 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307441 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 307444 */     GIR_RootConstrainSelectedInstOperands,
     /* 307445 */     // GIR_Coverage, 7096,
     /* 307445 */     GIR_EraseRootFromParent_Done,
     /* 307446 */   // Label 6143: @307446
     /* 307446 */   GIM_Reject,
     /* 307447 */ // Label 6141: @307447
     /* 307447 */ GIM_Reject,
     /* 307448 */ // Label 6130: @307448
     /* 307448 */ GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(307473), // Rule ID 8296 //
     /* 307453 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307456 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 307459 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 307462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 307466 */   // (fsub:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FSUB_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 307466 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_D),
     /* 307471 */   GIR_RootConstrainSelectedInstOperands,
     /* 307472 */   // GIR_Coverage, 8296,
     /* 307472 */   GIR_Done,
     /* 307473 */ // Label 6144: @307473
     /* 307473 */ GIM_Reject,
     /* 307474 */ // Label 6131: @307474
     /* 307474 */ GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(307499), // Rule ID 8294 //
     /* 307479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 307485 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 307488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 307492 */   // (fsub:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FSUB_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 307492 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_S),
     /* 307497 */   GIR_RootConstrainSelectedInstOperands,
     /* 307498 */   // GIR_Coverage, 8294,
     /* 307498 */   GIR_Done,
     /* 307499 */ // Label 6145: @307499
     /* 307499 */ GIM_Reject,
     /* 307500 */ // Label 6132: @307500
     /* 307500 */ GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(307525), // Rule ID 8292 //
     /* 307505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307508 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 307511 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 307514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 307518 */   // (fsub:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FSUB_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 307518 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_H),
     /* 307523 */   GIR_RootConstrainSelectedInstOperands,
     /* 307524 */   // GIR_Coverage, 8292,
     /* 307524 */   GIR_Done,
     /* 307525 */ // Label 6146: @307525
     /* 307525 */ GIM_Reject,
     /* 307526 */ // Label 6133: @307526
     /* 307526 */ GIM_Reject,
     /* 307527 */ // Label 61: @307527
     /* 307527 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6158*/ GIMT_Encode4(312142),
     /* 307538 */ /*GILLT_s16*//*Label 6147*/ GIMT_Encode4(307622),
     /* 307542 */ /*GILLT_s32*//*Label 6148*/ GIMT_Encode4(308264),
     /* 307546 */ /*GILLT_s64*//*Label 6149*/ GIMT_Encode4(308894), GIMT_Encode4(0),
     /* 307554 */ /*GILLT_v2s32*//*Label 6150*/ GIMT_Encode4(309524),
     /* 307558 */ /*GILLT_v2s64*//*Label 6151*/ GIMT_Encode4(310054),
     /* 307562 */ /*GILLT_v4s16*//*Label 6152*/ GIMT_Encode4(310412),
     /* 307566 */ /*GILLT_v4s32*//*Label 6153*/ GIMT_Encode4(310754), GIMT_Encode4(0),
     /* 307574 */ /*GILLT_v8s16*//*Label 6154*/ GIMT_Encode4(311112), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 307598 */ /*GILLT_nxv2s64*//*Label 6155*/ GIMT_Encode4(311544), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 307610 */ /*GILLT_nxv4s32*//*Label 6156*/ GIMT_Encode4(311858), GIMT_Encode4(0),
     /* 307618 */ /*GILLT_nxv8s16*//*Label 6157*/ GIMT_Encode4(312000),
     /* 307622 */ // Label 6147: @307622
     /* 307622 */ GIM_Try, /*On fail goto*//*Label 6159*/ GIMT_Encode4(308263),
     /* 307627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 307630 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 307633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307637 */   GIM_Try, /*On fail goto*//*Label 6160*/ GIMT_Encode4(307750), // Rule ID 6315 //
     /* 307642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 307645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307649 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307653 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307657 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 307661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307666 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 307670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 307674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307678 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307682 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 307686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307691 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 307695 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 307699 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 307703 */     // MIs[3] Operand 1
     /* 307703 */     // No operand predicates
     /* 307703 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 307705 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 307705 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 307708 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307712 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307717 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 307723 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307728 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 307736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 307738 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 307745 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 307748 */     GIR_RootConstrainSelectedInstOperands,
     /* 307749 */     // GIR_Coverage, 6315,
     /* 307749 */     GIR_EraseRootFromParent_Done,
     /* 307750 */   // Label 6160: @307750
     /* 307750 */   GIM_Try, /*On fail goto*//*Label 6161*/ GIMT_Encode4(307863), // Rule ID 14228 //
     /* 307755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 307758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307770 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 307774 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307779 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 307783 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 307787 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 307791 */     // MIs[2] Operand 1
     /* 307791 */     // No operand predicates
     /* 307791 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 307795 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307799 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307803 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 307807 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307812 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 307816 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 307818 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 307818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 307821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307830 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 307836 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307841 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 307849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 307851 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307854 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 307858 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 307861 */     GIR_RootConstrainSelectedInstOperands,
     /* 307862 */     // GIR_Coverage, 14228,
     /* 307862 */     GIR_EraseRootFromParent_Done,
     /* 307863 */   // Label 6161: @307863
     /* 307863 */   GIM_Try, /*On fail goto*//*Label 6162*/ GIMT_Encode4(307942), // Rule ID 14162 //
     /* 307868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 307871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307883 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 307887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307892 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 307896 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307900 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307902 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 307902 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 307905 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307909 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307914 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 307920 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307925 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 307933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 307935 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 307937 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307940 */     GIR_RootConstrainSelectedInstOperands,
     /* 307941 */     // GIR_Coverage, 14162,
     /* 307941 */     GIR_EraseRootFromParent_Done,
     /* 307942 */   // Label 6162: @307942
     /* 307942 */   GIM_Try, /*On fail goto*//*Label 6163*/ GIMT_Encode4(308021), // Rule ID 4872 //
     /* 307947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 307950 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307954 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 307958 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 307962 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 307966 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 307970 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307975 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 307979 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307981 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 307981 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 307984 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307988 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307993 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 307999 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308004 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 308012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308014 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 308016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308019 */     GIR_RootConstrainSelectedInstOperands,
     /* 308020 */     // GIR_Coverage, 4872,
     /* 308020 */     GIR_EraseRootFromParent_Done,
     /* 308021 */   // Label 6163: @308021
     /* 308021 */   GIM_Try, /*On fail goto*//*Label 6164*/ GIMT_Encode4(308084), // Rule ID 13766 //
     /* 308026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 308029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 308041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308045 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 308050 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 308054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308058 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 308062 */     // MIs[2] Operand 1
     /* 308062 */     // No operand predicates
     /* 308062 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308066 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 308068 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 308068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 308071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308073 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 308075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 308079 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 308082 */     GIR_RootConstrainSelectedInstOperands,
     /* 308083 */     // GIR_Coverage, 13766,
     /* 308083 */     GIR_EraseRootFromParent_Done,
     /* 308084 */   // Label 6164: @308084
     /* 308084 */   GIM_Try, /*On fail goto*//*Label 6165*/ GIMT_Encode4(308147), // Rule ID 2016 //
     /* 308089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 308092 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308096 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 308100 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308104 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 308108 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 308117 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 308121 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308125 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 308129 */     // MIs[2] Operand 1
     /* 308129 */     // No operand predicates
     /* 308129 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 308131 */     // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 308131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 308134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308136 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 308138 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 308142 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 308145 */     GIR_RootConstrainSelectedInstOperands,
     /* 308146 */     // GIR_Coverage, 2016,
     /* 308146 */     GIR_EraseRootFromParent_Done,
     /* 308147 */   // Label 6165: @308147
     /* 308147 */   GIM_Try, /*On fail goto*//*Label 6166*/ GIMT_Encode4(308191), // Rule ID 4877 //
     /* 308152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 308155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 308163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 308167 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308172 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308176 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308178 */     // (fmul:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a), FPR16:{ *:[f16] }:$b)  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 308178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 308181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 308187 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 308189 */     GIR_RootConstrainSelectedInstOperands,
     /* 308190 */     // GIR_Coverage, 4877,
     /* 308190 */     GIR_EraseRootFromParent_Done,
     /* 308191 */   // Label 6166: @308191
     /* 308191 */   GIM_Try, /*On fail goto*//*Label 6167*/ GIMT_Encode4(308235), // Rule ID 14167 //
     /* 308196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 308199 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 308207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 308211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 308215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308220 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308222 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$b, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 308222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 308225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 308231 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 308233 */     GIR_RootConstrainSelectedInstOperands,
     /* 308234 */     // GIR_Coverage, 14167,
     /* 308234 */     GIR_EraseRootFromParent_Done,
     /* 308235 */   // Label 6167: @308235
     /* 308235 */   GIM_Try, /*On fail goto*//*Label 6168*/ GIMT_Encode4(308262), // Rule ID 624 //
     /* 308240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 308243 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308247 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308251 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 308251 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 308256 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 308260 */     GIR_RootConstrainSelectedInstOperands,
     /* 308261 */     // GIR_Coverage, 624,
     /* 308261 */     GIR_Done,
     /* 308262 */   // Label 6168: @308262
     /* 308262 */   GIM_Reject,
     /* 308263 */ // Label 6159: @308263
     /* 308263 */ GIM_Reject,
     /* 308264 */ // Label 6148: @308264
     /* 308264 */ GIM_Try, /*On fail goto*//*Label 6169*/ GIMT_Encode4(308893),
     /* 308269 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 308272 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 308275 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308279 */   GIM_Try, /*On fail goto*//*Label 6170*/ GIMT_Encode4(308392), // Rule ID 6317 //
     /* 308284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 308287 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308291 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308295 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308299 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308303 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308308 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 308312 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 308316 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308320 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308324 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 308328 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308333 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 308337 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308341 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 308345 */     // MIs[3] Operand 1
     /* 308345 */     // No operand predicates
     /* 308345 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 308347 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 308347 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308350 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308354 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308359 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 308365 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308370 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 308378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308380 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 308387 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 308390 */     GIR_RootConstrainSelectedInstOperands,
     /* 308391 */     // GIR_Coverage, 6317,
     /* 308391 */     GIR_EraseRootFromParent_Done,
     /* 308392 */   // Label 6170: @308392
     /* 308392 */   GIM_Try, /*On fail goto*//*Label 6171*/ GIMT_Encode4(308505), // Rule ID 14230 //
     /* 308397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 308400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308412 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308416 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 308425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308429 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 308433 */     // MIs[2] Operand 1
     /* 308433 */     // No operand predicates
     /* 308433 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 308437 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308441 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308445 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 308449 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308454 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 308458 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 308460 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 308460 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308463 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308467 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308472 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 308478 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308483 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 308491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308493 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 308500 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 308503 */     GIR_RootConstrainSelectedInstOperands,
     /* 308504 */     // GIR_Coverage, 14230,
     /* 308504 */     GIR_EraseRootFromParent_Done,
     /* 308505 */   // Label 6171: @308505
     /* 308505 */   GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(308581), // Rule ID 14164 //
     /* 308510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308522 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308526 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308531 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 308535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308539 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308541 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 308541 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308544 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308548 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308553 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 308559 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308564 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 308572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 308576 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308579 */     GIR_RootConstrainSelectedInstOperands,
     /* 308580 */     // GIR_Coverage, 14164,
     /* 308580 */     GIR_EraseRootFromParent_Done,
     /* 308581 */   // Label 6172: @308581
     /* 308581 */   GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(308657), // Rule ID 4874 //
     /* 308586 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308590 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 308594 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308598 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308602 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308606 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308611 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 308615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308617 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 308617 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308624 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308629 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 308635 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308640 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 308648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308650 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 308652 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308655 */     GIR_RootConstrainSelectedInstOperands,
     /* 308656 */     // GIR_Coverage, 4874,
     /* 308656 */     GIR_EraseRootFromParent_Done,
     /* 308657 */   // Label 6173: @308657
     /* 308657 */   GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(308720), // Rule ID 13768 //
     /* 308662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 308665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308677 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308681 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308686 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 308690 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308694 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 308698 */     // MIs[2] Operand 1
     /* 308698 */     // No operand predicates
     /* 308698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308702 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 308704 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 308704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 308707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 308711 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 308715 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 308718 */     GIR_RootConstrainSelectedInstOperands,
     /* 308719 */     // GIR_Coverage, 13768,
     /* 308719 */     GIR_EraseRootFromParent_Done,
     /* 308720 */   // Label 6174: @308720
     /* 308720 */   GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(308783), // Rule ID 2018 //
     /* 308725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 308728 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 308736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308740 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 308744 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308748 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308753 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 308757 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308761 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 308765 */     // MIs[2] Operand 1
     /* 308765 */     // No operand predicates
     /* 308765 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 308767 */     // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 308767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 308770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308772 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 308774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 308778 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 308781 */     GIR_RootConstrainSelectedInstOperands,
     /* 308782 */     // GIR_Coverage, 2018,
     /* 308782 */     GIR_EraseRootFromParent_Done,
     /* 308783 */   // Label 6175: @308783
     /* 308783 */   GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(308824), // Rule ID 4878 //
     /* 308788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 308796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 308800 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308809 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308811 */     // (fmul:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a), FPR32:{ *:[f32] }:$b)  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 308811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 308814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308816 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 308820 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 308822 */     GIR_RootConstrainSelectedInstOperands,
     /* 308823 */     // GIR_Coverage, 4878,
     /* 308823 */     GIR_EraseRootFromParent_Done,
     /* 308824 */   // Label 6176: @308824
     /* 308824 */   GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(308865), // Rule ID 14168 //
     /* 308829 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 308837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 308841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 308845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308850 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308852 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$b, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 308852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 308855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 308857 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 308861 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 308863 */     GIR_RootConstrainSelectedInstOperands,
     /* 308864 */     // GIR_Coverage, 14168,
     /* 308864 */     GIR_EraseRootFromParent_Done,
     /* 308865 */   // Label 6177: @308865
     /* 308865 */   GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(308892), // Rule ID 626 //
     /* 308870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 308873 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308881 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 308881 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 308886 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 308890 */     GIR_RootConstrainSelectedInstOperands,
     /* 308891 */     // GIR_Coverage, 626,
     /* 308891 */     GIR_Done,
     /* 308892 */   // Label 6178: @308892
     /* 308892 */   GIM_Reject,
     /* 308893 */ // Label 6169: @308893
     /* 308893 */ GIM_Reject,
     /* 308894 */ // Label 6149: @308894
     /* 308894 */ GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(309523),
     /* 308899 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 308902 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 308905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 308909 */   GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(309022), // Rule ID 6319 //
     /* 308914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 308917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308925 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 308929 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 308933 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308938 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 308942 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 308946 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 308950 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 308954 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 308958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308963 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 308967 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 308971 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 308975 */     // MIs[3] Operand 1
     /* 308975 */     // No operand predicates
     /* 308975 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 308977 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 308977 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 308980 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308984 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308989 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 308995 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309000 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 309008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309010 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 309017 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 309020 */     GIR_RootConstrainSelectedInstOperands,
     /* 309021 */     // GIR_Coverage, 6319,
     /* 309021 */     GIR_EraseRootFromParent_Done,
     /* 309022 */   // Label 6180: @309022
     /* 309022 */   GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(309135), // Rule ID 14232 //
     /* 309027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309030 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309034 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309038 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309042 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309046 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309051 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 309055 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309059 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 309063 */     // MIs[2] Operand 1
     /* 309063 */     // No operand predicates
     /* 309063 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 309067 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309071 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309075 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 309079 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309084 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 309088 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 309090 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 309090 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 309093 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309097 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309102 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 309108 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309113 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 309121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309123 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309130 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 309133 */     GIR_RootConstrainSelectedInstOperands,
     /* 309134 */     // GIR_Coverage, 14232,
     /* 309134 */     GIR_EraseRootFromParent_Done,
     /* 309135 */   // Label 6181: @309135
     /* 309135 */   GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(309211), // Rule ID 14166 //
     /* 309140 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309144 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309148 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309152 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309156 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309161 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 309165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309169 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309171 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 309171 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 309174 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309178 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309183 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 309189 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309194 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 309202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 309206 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309209 */     GIR_RootConstrainSelectedInstOperands,
     /* 309210 */     // GIR_Coverage, 14166,
     /* 309210 */     GIR_EraseRootFromParent_Done,
     /* 309211 */   // Label 6182: @309211
     /* 309211 */   GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(309287), // Rule ID 4876 //
     /* 309216 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309232 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309236 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309241 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 309245 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309247 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 309247 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 309250 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309254 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309259 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 309265 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309270 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 309278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309280 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309282 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309285 */     GIR_RootConstrainSelectedInstOperands,
     /* 309286 */     // GIR_Coverage, 4876,
     /* 309286 */     GIR_EraseRootFromParent_Done,
     /* 309287 */   // Label 6183: @309287
     /* 309287 */   GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(309350), // Rule ID 13770 //
     /* 309292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309307 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309311 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 309320 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309324 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 309328 */     // MIs[2] Operand 1
     /* 309328 */     // No operand predicates
     /* 309328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 309334 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 309337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 309341 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309345 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 309348 */     GIR_RootConstrainSelectedInstOperands,
     /* 309349 */     // GIR_Coverage, 13770,
     /* 309349 */     GIR_EraseRootFromParent_Done,
     /* 309350 */   // Label 6184: @309350
     /* 309350 */   GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(309413), // Rule ID 2020 //
     /* 309355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309358 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 309370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 309374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 309387 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309391 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 309395 */     // MIs[2] Operand 1
     /* 309395 */     // No operand predicates
     /* 309395 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 309397 */     // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 309400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309402 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309408 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 309411 */     GIR_RootConstrainSelectedInstOperands,
     /* 309412 */     // GIR_Coverage, 2020,
     /* 309412 */     GIR_EraseRootFromParent_Done,
     /* 309413 */   // Label 6185: @309413
     /* 309413 */   GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(309454), // Rule ID 4879 //
     /* 309418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 309426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 309430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309435 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309439 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309441 */     // (fmul:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a), FPR64:{ *:[f64] }:$b)  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 309441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 309444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 309450 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 309452 */     GIR_RootConstrainSelectedInstOperands,
     /* 309453 */     // GIR_Coverage, 4879,
     /* 309453 */     GIR_EraseRootFromParent_Done,
     /* 309454 */   // Label 6186: @309454
     /* 309454 */   GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(309495), // Rule ID 14169 //
     /* 309459 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309463 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309467 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 309471 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 309475 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309480 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309482 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$b, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 309482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 309485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 309491 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 309493 */     GIR_RootConstrainSelectedInstOperands,
     /* 309494 */     // GIR_Coverage, 14169,
     /* 309494 */     GIR_EraseRootFromParent_Done,
     /* 309495 */   // Label 6187: @309495
     /* 309495 */   GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(309522), // Rule ID 628 //
     /* 309500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 309503 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309507 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309511 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 309511 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 309516 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 309520 */     GIR_RootConstrainSelectedInstOperands,
     /* 309521 */     // GIR_Coverage, 628,
     /* 309521 */     GIR_Done,
     /* 309522 */   // Label 6188: @309522
     /* 309522 */   GIM_Reject,
     /* 309523 */ // Label 6179: @309523
     /* 309523 */ GIM_Reject,
     /* 309524 */ // Label 6150: @309524
     /* 309524 */ GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(310053),
     /* 309529 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309532 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 309535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309539 */   GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(309625), // Rule ID 13759 //
     /* 309544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309547 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309551 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 309555 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309559 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 309563 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 309567 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309571 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 309575 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309580 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 309584 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309588 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 309592 */     // MIs[3] Operand 1
     /* 309592 */     // No operand predicates
     /* 309592 */     // MIs[1] Operand 2
     /* 309592 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 309603 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309607 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 309609 */     // (fmul:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 309612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 309616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 309620 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 309623 */     GIR_RootConstrainSelectedInstOperands,
     /* 309624 */     // GIR_Coverage, 13759,
     /* 309624 */     GIR_EraseRootFromParent_Done,
     /* 309625 */   // Label 6190: @309625
     /* 309625 */   GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(309711), // Rule ID 2009 //
     /* 309630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309633 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 309645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309649 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 309653 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 309657 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309661 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 309665 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309670 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 309674 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309678 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 309682 */     // MIs[3] Operand 1
     /* 309682 */     // No operand predicates
     /* 309682 */     // MIs[1] Operand 2
     /* 309682 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 309693 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 309695 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 309698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309700 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 309706 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 309709 */     GIR_RootConstrainSelectedInstOperands,
     /* 309710 */     // GIR_Coverage, 2009,
     /* 309710 */     GIR_EraseRootFromParent_Done,
     /* 309711 */   // Label 6191: @309711
     /* 309711 */   GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(309774), // Rule ID 13760 //
     /* 309716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309719 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309723 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 309727 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309731 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309735 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309740 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 309744 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309748 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 309752 */     // MIs[2] Operand 1
     /* 309752 */     // No operand predicates
     /* 309752 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309756 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 309758 */     // (fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 309761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 309765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309769 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 309772 */     GIR_RootConstrainSelectedInstOperands,
     /* 309773 */     // GIR_Coverage, 13760,
     /* 309773 */     GIR_EraseRootFromParent_Done,
     /* 309774 */   // Label 6192: @309774
     /* 309774 */   GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(309837), // Rule ID 2010 //
     /* 309779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309782 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309786 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309790 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 309794 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 309798 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 309802 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309807 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 309811 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 309815 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 309819 */     // MIs[2] Operand 1
     /* 309819 */     // No operand predicates
     /* 309819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 309821 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 309821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 309824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309826 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309828 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309832 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 309835 */     GIR_RootConstrainSelectedInstOperands,
     /* 309836 */     // GIR_Coverage, 2010,
     /* 309836 */     GIR_EraseRootFromParent_Done,
     /* 309837 */   // Label 6193: @309837
     /* 309837 */   GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(309931), // Rule ID 14234 //
     /* 309842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 309850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 309854 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 309859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309863 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309865 */     // (fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 309865 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 309868 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 309872 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309877 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 309879 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 309882 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 309886 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309891 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 309894 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309898 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 309901 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309906 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309911 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 309916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 309919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309921 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 309923 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309929 */     GIR_RootConstrainSelectedInstOperands,
     /* 309930 */     // GIR_Coverage, 14234,
     /* 309930 */     GIR_EraseRootFromParent_Done,
     /* 309931 */   // Label 6194: @309931
     /* 309931 */   GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(310025), // Rule ID 6321 //
     /* 309936 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 309944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 309948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 309952 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 309957 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309959 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 309959 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 309962 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 309966 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309971 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 309973 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 309976 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 309980 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309985 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 309988 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 309992 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 309995 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310000 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310005 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 310010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 310013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310015 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310017 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 310023 */     GIR_RootConstrainSelectedInstOperands,
     /* 310024 */     // GIR_Coverage, 6321,
     /* 310024 */     GIR_EraseRootFromParent_Done,
     /* 310025 */   // Label 6195: @310025
     /* 310025 */   GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(310052), // Rule ID 1327 //
     /* 310030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310033 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310037 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310041 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 310041 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
     /* 310046 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 310050 */     GIR_RootConstrainSelectedInstOperands,
     /* 310051 */     // GIR_Coverage, 1327,
     /* 310051 */     GIR_Done,
     /* 310052 */   // Label 6196: @310052
     /* 310052 */   GIM_Reject,
     /* 310053 */ // Label 6189: @310053
     /* 310053 */ GIM_Reject,
     /* 310054 */ // Label 6151: @310054
     /* 310054 */ GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(310411),
     /* 310059 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 310062 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 310065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310069 */   GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(310132), // Rule ID 13764 //
     /* 310074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 310085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 310089 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310093 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310098 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310102 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310106 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 310110 */     // MIs[2] Operand 1
     /* 310110 */     // No operand predicates
     /* 310110 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310114 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310116 */     // (fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 310119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310127 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310130 */     GIR_RootConstrainSelectedInstOperands,
     /* 310131 */     // GIR_Coverage, 13764,
     /* 310131 */     GIR_EraseRootFromParent_Done,
     /* 310132 */   // Label 6198: @310132
     /* 310132 */   GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(310195), // Rule ID 2014 //
     /* 310137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310140 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 310152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 310156 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310160 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310173 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 310177 */     // MIs[2] Operand 1
     /* 310177 */     // No operand predicates
     /* 310177 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310179 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 310182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310184 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310190 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310193 */     GIR_RootConstrainSelectedInstOperands,
     /* 310194 */     // GIR_Coverage, 2014,
     /* 310194 */     GIR_EraseRootFromParent_Done,
     /* 310195 */   // Label 6199: @310195
     /* 310195 */   GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(310289), // Rule ID 14238 //
     /* 310200 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310204 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 310208 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 310212 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310217 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310221 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310223 */     // (fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 310223 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 310226 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 310230 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310235 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 310237 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 310240 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 310244 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310249 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 310252 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310256 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 310259 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310264 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310269 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 310277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310279 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310281 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 310287 */     GIR_RootConstrainSelectedInstOperands,
     /* 310288 */     // GIR_Coverage, 14238,
     /* 310288 */     GIR_EraseRootFromParent_Done,
     /* 310289 */   // Label 6200: @310289
     /* 310289 */   GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(310383), // Rule ID 6325 //
     /* 310294 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 310306 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 310310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310315 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310317 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 310317 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 310320 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 310324 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310329 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 310331 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 310334 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 310338 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310343 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 310346 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310350 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 310353 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310358 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310363 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 310371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310373 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310375 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 310381 */     GIR_RootConstrainSelectedInstOperands,
     /* 310382 */     // GIR_Coverage, 6325,
     /* 310382 */     GIR_EraseRootFromParent_Done,
     /* 310383 */   // Label 6201: @310383
     /* 310383 */   GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(310410), // Rule ID 1331 //
     /* 310388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310391 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310399 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 310399 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
     /* 310404 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 310408 */     GIR_RootConstrainSelectedInstOperands,
     /* 310409 */     // GIR_Coverage, 1331,
     /* 310409 */     GIR_Done,
     /* 310410 */   // Label 6202: @310410
     /* 310410 */   GIM_Reject,
     /* 310411 */ // Label 6197: @310411
     /* 310411 */ GIM_Reject,
     /* 310412 */ // Label 6152: @310412
     /* 310412 */ GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(310753),
     /* 310417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 310420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 310423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310427 */   GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(310513), // Rule ID 13753 //
     /* 310432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 310435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310439 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 310443 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 310451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 310455 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310459 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 310463 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 310468 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 310472 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310476 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 310480 */     // MIs[3] Operand 1
     /* 310480 */     // No operand predicates
     /* 310480 */     // MIs[1] Operand 2
     /* 310480 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 310491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310495 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310497 */     // (fmul:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 310500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310504 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 310508 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 310511 */     GIR_RootConstrainSelectedInstOperands,
     /* 310512 */     // GIR_Coverage, 13753,
     /* 310512 */     GIR_EraseRootFromParent_Done,
     /* 310513 */   // Label 6204: @310513
     /* 310513 */   GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(310599), // Rule ID 2003 //
     /* 310518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 310521 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310525 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310529 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 310533 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 310541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 310545 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310549 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 310553 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 310558 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 310562 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310566 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 310570 */     // MIs[3] Operand 1
     /* 310570 */     // No operand predicates
     /* 310570 */     // MIs[1] Operand 2
     /* 310570 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 310581 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310583 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 310586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310588 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 310594 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 310597 */     GIR_RootConstrainSelectedInstOperands,
     /* 310598 */     // GIR_Coverage, 2003,
     /* 310598 */     GIR_EraseRootFromParent_Done,
     /* 310599 */   // Label 6205: @310599
     /* 310599 */   GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(310662), // Rule ID 13754 //
     /* 310604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 310607 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310611 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 310615 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310619 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310623 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 310628 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310632 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310636 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 310640 */     // MIs[2] Operand 1
     /* 310640 */     // No operand predicates
     /* 310640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310644 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310646 */     // (fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 310649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310651 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310653 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310657 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310660 */     GIR_RootConstrainSelectedInstOperands,
     /* 310661 */     // GIR_Coverage, 13754,
     /* 310661 */     GIR_EraseRootFromParent_Done,
     /* 310662 */   // Label 6206: @310662
     /* 310662 */   GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(310725), // Rule ID 2004 //
     /* 310667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 310670 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310674 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310678 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 310682 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310686 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310690 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 310695 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310699 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310703 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 310707 */     // MIs[2] Operand 1
     /* 310707 */     // No operand predicates
     /* 310707 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310709 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 310712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310714 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310716 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310720 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310723 */     GIR_RootConstrainSelectedInstOperands,
     /* 310724 */     // GIR_Coverage, 2004,
     /* 310724 */     GIR_EraseRootFromParent_Done,
     /* 310725 */   // Label 6207: @310725
     /* 310725 */   GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(310752), // Rule ID 1323 //
     /* 310730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 310733 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310741 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 310741 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
     /* 310746 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 310750 */     GIR_RootConstrainSelectedInstOperands,
     /* 310751 */     // GIR_Coverage, 1323,
     /* 310751 */     GIR_Done,
     /* 310752 */   // Label 6208: @310752
     /* 310752 */   GIM_Reject,
     /* 310753 */ // Label 6203: @310753
     /* 310753 */ GIM_Reject,
     /* 310754 */ // Label 6153: @310754
     /* 310754 */ GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(311111),
     /* 310759 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 310762 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 310765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310769 */   GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(310832), // Rule ID 13762 //
     /* 310774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310777 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310781 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 310785 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 310789 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310793 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310798 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310802 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310806 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 310810 */     // MIs[2] Operand 1
     /* 310810 */     // No operand predicates
     /* 310810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310814 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310816 */     // (fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 310819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310827 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310830 */     GIR_RootConstrainSelectedInstOperands,
     /* 310831 */     // GIR_Coverage, 13762,
     /* 310831 */     GIR_EraseRootFromParent_Done,
     /* 310832 */   // Label 6210: @310832
     /* 310832 */   GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(310895), // Rule ID 2012 //
     /* 310837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310840 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 310852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 310856 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 310860 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310865 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 310869 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310873 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 310877 */     // MIs[2] Operand 1
     /* 310877 */     // No operand predicates
     /* 310877 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 310879 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 310879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 310882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310884 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310890 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 310893 */     GIR_RootConstrainSelectedInstOperands,
     /* 310894 */     // GIR_Coverage, 2012,
     /* 310894 */     GIR_EraseRootFromParent_Done,
     /* 310895 */   // Label 6211: @310895
     /* 310895 */   GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(310989), // Rule ID 14236 //
     /* 310900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 310908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 310917 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310921 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310923 */     // (fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 310923 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 310926 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 310930 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310935 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 310937 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 310940 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 310944 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310949 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 310952 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310956 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 310959 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310964 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310969 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 310974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 310977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 310981 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 310987 */     GIR_RootConstrainSelectedInstOperands,
     /* 310988 */     // GIR_Coverage, 14236,
     /* 310988 */     GIR_EraseRootFromParent_Done,
     /* 310989 */   // Label 6212: @310989
     /* 310989 */   GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(311083), // Rule ID 6323 //
     /* 310994 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 311006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311010 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 311015 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311017 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 311017 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 311020 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 311024 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311029 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 311031 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 311034 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 311038 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311043 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 311046 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311050 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 311053 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311058 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311063 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 311068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 311071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311073 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 311081 */     GIR_RootConstrainSelectedInstOperands,
     /* 311082 */     // GIR_Coverage, 6323,
     /* 311082 */     GIR_EraseRootFromParent_Done,
     /* 311083 */   // Label 6213: @311083
     /* 311083 */   GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(311110), // Rule ID 1329 //
     /* 311088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 311091 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311099 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 311099 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 311104 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 311108 */     GIR_RootConstrainSelectedInstOperands,
     /* 311109 */     // GIR_Coverage, 1329,
     /* 311109 */     GIR_Done,
     /* 311110 */   // Label 6214: @311110
     /* 311110 */   GIM_Reject,
     /* 311111 */ // Label 6209: @311111
     /* 311111 */ GIM_Reject,
     /* 311112 */ // Label 6154: @311112
     /* 311112 */ GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(311543),
     /* 311117 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 311120 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 311123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311127 */   GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(311190), // Rule ID 13756 //
     /* 311132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 311135 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311139 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 311143 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 311147 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 311151 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 311156 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 311160 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311164 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 311168 */     // MIs[2] Operand 1
     /* 311168 */     // No operand predicates
     /* 311168 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311172 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311174 */     // (fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 311174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 311177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311179 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 311181 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311185 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 311188 */     GIR_RootConstrainSelectedInstOperands,
     /* 311189 */     // GIR_Coverage, 13756,
     /* 311189 */     GIR_EraseRootFromParent_Done,
     /* 311190 */   // Label 6216: @311190
     /* 311190 */   GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(311253), // Rule ID 2006 //
     /* 311195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 311198 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311202 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311206 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 311210 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 311214 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 311218 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 311223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 311227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311231 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 311235 */     // MIs[2] Operand 1
     /* 311235 */     // No operand predicates
     /* 311235 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311237 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 311237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 311240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311248 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 311251 */     GIR_RootConstrainSelectedInstOperands,
     /* 311252 */     // GIR_Coverage, 2006,
     /* 311252 */     GIR_EraseRootFromParent_Done,
     /* 311253 */   // Label 6217: @311253
     /* 311253 */   GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(311280), // Rule ID 1325 //
     /* 311258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 311261 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311269 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 311269 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
     /* 311274 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 311278 */     GIR_RootConstrainSelectedInstOperands,
     /* 311279 */     // GIR_Coverage, 1325,
     /* 311279 */     GIR_Done,
     /* 311280 */   // Label 6218: @311280
     /* 311280 */   GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(311542), // Rule ID 7094 //
     /* 311285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 311288 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311292 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311296 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 311296 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 311299 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 311303 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311308 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 311312 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 311314 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 311317 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 311321 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311326 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 311330 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 311332 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 311335 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 311339 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311344 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 311347 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 311350 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 311352 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 311355 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 311359 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311364 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 311370 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 311375 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311380 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 311383 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 311387 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311392 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 311395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 311397 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 311400 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 311404 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311409 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 311415 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 311420 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311425 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 311428 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 311432 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311437 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 311440 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 311442 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 311445 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 311449 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311454 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 311457 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 311460 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 311462 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 311465 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 311469 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311474 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 311477 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 311479 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 311482 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 311486 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311491 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 311493 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 311496 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 311500 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311505 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 311508 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 311511 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 311514 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311519 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 311524 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 311529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 311532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 311534 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311537 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 311540 */     GIR_RootConstrainSelectedInstOperands,
     /* 311541 */     // GIR_Coverage, 7094,
     /* 311541 */     GIR_EraseRootFromParent_Done,
     /* 311542 */   // Label 6219: @311542
     /* 311542 */   GIM_Reject,
     /* 311543 */ // Label 6215: @311543
     /* 311543 */ GIM_Reject,
     /* 311544 */ // Label 6155: @311544
     /* 311544 */ GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(311857),
     /* 311549 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 311552 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 311555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 311559 */   GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(311614), // Rule ID 13989 //
     /* 311564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 311575 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 311578 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 311583 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 311587 */     // MIs[1] idx
     /* 311587 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 311590 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 311595 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311597 */     // (fmul:{ *:[nxv2f64] } (intrinsic_wo_chain:{ *:[nxv2f64] } 1355:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx), nxv2f64:{ *:[nxv2f64] }:$Op1)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 311597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 311604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 311608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 311612 */     GIR_RootConstrainSelectedInstOperands,
     /* 311613 */     // GIR_Coverage, 13989,
     /* 311613 */     GIR_EraseRootFromParent_Done,
     /* 311614 */   // Label 6221: @311614
     /* 311614 */   GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(311669), // Rule ID 2867 //
     /* 311619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311622 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311626 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 311630 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 311633 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 311638 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 311642 */     // MIs[1] idx
     /* 311642 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 311645 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 311650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311652 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, (intrinsic_wo_chain:{ *:[nxv2f64] } 1355:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 311652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311657 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 311659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 311663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 311667 */     GIR_RootConstrainSelectedInstOperands,
     /* 311668 */     // GIR_Coverage, 2867,
     /* 311668 */     GIR_EraseRootFromParent_Done,
     /* 311669 */   // Label 6222: @311669
     /* 311669 */   GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(311712), // Rule ID 15357 //
     /* 311674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311677 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311681 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN1),
     /* 311685 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 311689 */     // MIs[1] R
     /* 311689 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 311694 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311696 */     // (fmul:{ *:[nxv2f64] } (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R), nxv2f64:{ *:[nxv2f64] }:$L)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 0:{ *:[i32] })
     /* 311696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311701 */     GIR_RootToRootCopy, /*OpIdx*/2, // L
     /* 311703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 311707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 311710 */     GIR_RootConstrainSelectedInstOperands,
     /* 311711 */     // GIR_Coverage, 15357,
     /* 311711 */     GIR_EraseRootFromParent_Done,
     /* 311712 */   // Label 6223: @311712
     /* 311712 */   GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(311755), // Rule ID 15358 //
     /* 311717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN2),
     /* 311728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 311732 */     // MIs[1] R
     /* 311732 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 311737 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311739 */     // (fmul:{ *:[nxv2f64] } (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R), nxv2f64:{ *:[nxv2f64] }:$L)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 1:{ *:[i32] })
     /* 311739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311744 */     GIR_RootToRootCopy, /*OpIdx*/2, // L
     /* 311746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 311750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 311753 */     GIR_RootConstrainSelectedInstOperands,
     /* 311754 */     // GIR_Coverage, 15358,
     /* 311754 */     GIR_EraseRootFromParent_Done,
     /* 311755 */   // Label 6224: @311755
     /* 311755 */   GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(311798), // Rule ID 8409 //
     /* 311760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN1),
     /* 311771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 311775 */     // MIs[1] R
     /* 311775 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 311780 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311782 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$L, (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 0:{ *:[i32] })
     /* 311782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311787 */     GIR_RootToRootCopy, /*OpIdx*/1, // L
     /* 311789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 311793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 311796 */     GIR_RootConstrainSelectedInstOperands,
     /* 311797 */     // GIR_Coverage, 8409,
     /* 311797 */     GIR_EraseRootFromParent_Done,
     /* 311798 */   // Label 6225: @311798
     /* 311798 */   GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(311841), // Rule ID 8412 //
     /* 311803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN2),
     /* 311814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 311818 */     // MIs[1] R
     /* 311818 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 311823 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311825 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$L, (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 1:{ *:[i32] })
     /* 311825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 311828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311830 */     GIR_RootToRootCopy, /*OpIdx*/1, // L
     /* 311832 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 311836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 311839 */     GIR_RootConstrainSelectedInstOperands,
     /* 311840 */     // GIR_Coverage, 8412,
     /* 311840 */     GIR_EraseRootFromParent_Done,
     /* 311841 */   // Label 6226: @311841
     /* 311841 */   GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(311856), // Rule ID 8304 //
     /* 311846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311849 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 311849 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_D),
     /* 311854 */     GIR_RootConstrainSelectedInstOperands,
     /* 311855 */     // GIR_Coverage, 8304,
     /* 311855 */     GIR_Done,
     /* 311856 */   // Label 6227: @311856
     /* 311856 */   GIM_Reject,
     /* 311857 */ // Label 6220: @311857
     /* 311857 */ GIM_Reject,
     /* 311858 */ // Label 6156: @311858
     /* 311858 */ GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(311999),
     /* 311863 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 311866 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 311869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 311873 */   GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(311928), // Rule ID 13988 //
     /* 311878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311881 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311885 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 311889 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 311892 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 311897 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 311901 */     // MIs[1] idx
     /* 311901 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 311904 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 311909 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311911 */     // (fmul:{ *:[nxv4f32] } (intrinsic_wo_chain:{ *:[nxv4f32] } 1355:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx), nxv4f32:{ *:[nxv4f32] }:$Op1)  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 311911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 311914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311916 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 311918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 311922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 311926 */     GIR_RootConstrainSelectedInstOperands,
     /* 311927 */     // GIR_Coverage, 13988,
     /* 311927 */     GIR_EraseRootFromParent_Done,
     /* 311928 */   // Label 6229: @311928
     /* 311928 */   GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(311983), // Rule ID 2863 //
     /* 311933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311936 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311940 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 311944 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 311947 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 311952 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 311956 */     // MIs[1] idx
     /* 311956 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 311959 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 311964 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311966 */     // (fmul:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, (intrinsic_wo_chain:{ *:[nxv4f32] } 1355:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx))  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 311966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 311969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 311971 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 311973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 311977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 311981 */     GIR_RootConstrainSelectedInstOperands,
     /* 311982 */     // GIR_Coverage, 2863,
     /* 311982 */     GIR_EraseRootFromParent_Done,
     /* 311983 */   // Label 6230: @311983
     /* 311983 */   GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(311998), // Rule ID 8301 //
     /* 311988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 311991 */     // (fmul:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 311991 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_S),
     /* 311996 */     GIR_RootConstrainSelectedInstOperands,
     /* 311997 */     // GIR_Coverage, 8301,
     /* 311997 */     GIR_Done,
     /* 311998 */   // Label 6231: @311998
     /* 311998 */   GIM_Reject,
     /* 311999 */ // Label 6228: @311999
     /* 311999 */ GIM_Reject,
     /* 312000 */ // Label 6157: @312000
     /* 312000 */ GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(312141),
     /* 312005 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 312008 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 312011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 312015 */   GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(312070), // Rule ID 13987 //
     /* 312020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 312023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 312031 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 312034 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 312039 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 312043 */     // MIs[1] idx
     /* 312043 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 312046 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 312051 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312053 */     // (fmul:{ *:[nxv8f16] } (intrinsic_wo_chain:{ *:[nxv8f16] } 1355:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx), nxv8f16:{ *:[nxv8f16] }:$Op1)  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 312053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 312056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 312058 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 312060 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 312064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 312068 */     GIR_RootConstrainSelectedInstOperands,
     /* 312069 */     // GIR_Coverage, 13987,
     /* 312069 */     GIR_EraseRootFromParent_Done,
     /* 312070 */   // Label 6233: @312070
     /* 312070 */   GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(312125), // Rule ID 2859 //
     /* 312075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 312078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 312086 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 312089 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 312094 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 312098 */     // MIs[1] idx
     /* 312098 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 312101 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 312106 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312108 */     // (fmul:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, (intrinsic_wo_chain:{ *:[nxv8f16] } 1355:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx))  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 312108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 312111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 312113 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 312115 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 312119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 312123 */     GIR_RootConstrainSelectedInstOperands,
     /* 312124 */     // GIR_Coverage, 2859,
     /* 312124 */     GIR_EraseRootFromParent_Done,
     /* 312125 */   // Label 6234: @312125
     /* 312125 */   GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(312140), // Rule ID 8298 //
     /* 312130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 312133 */     // (fmul:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 312133 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_H),
     /* 312138 */     GIR_RootConstrainSelectedInstOperands,
     /* 312139 */     // GIR_Coverage, 8298,
     /* 312139 */     GIR_Done,
     /* 312140 */   // Label 6235: @312140
     /* 312140 */   GIM_Reject,
     /* 312141 */ // Label 6232: @312141
     /* 312141 */ GIM_Reject,
     /* 312142 */ // Label 6158: @312142
     /* 312142 */ GIM_Reject,
     /* 312143 */ // Label 62: @312143
     /* 312143 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6244*/ GIMT_Encode4(328415),
     /* 312154 */ /*GILLT_s16*//*Label 6236*/ GIMT_Encode4(312194),
     /* 312158 */ /*GILLT_s32*//*Label 6237*/ GIMT_Encode4(315198),
     /* 312162 */ /*GILLT_s64*//*Label 6238*/ GIMT_Encode4(318346), GIMT_Encode4(0),
     /* 312170 */ /*GILLT_v2s32*//*Label 6239*/ GIMT_Encode4(321494),
     /* 312174 */ /*GILLT_v2s64*//*Label 6240*/ GIMT_Encode4(323015),
     /* 312178 */ /*GILLT_v4s16*//*Label 6241*/ GIMT_Encode4(324536),
     /* 312182 */ /*GILLT_v4s32*//*Label 6242*/ GIMT_Encode4(325715), GIMT_Encode4(0),
     /* 312190 */ /*GILLT_v8s16*//*Label 6243*/ GIMT_Encode4(327236),
     /* 312194 */ // Label 6236: @312194
     /* 312194 */ GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(315197),
     /* 312199 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 312202 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 312205 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 312208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312212 */   GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(312362), // Rule ID 4934 //
     /* 312217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 312220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312232 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 312236 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312241 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 312245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 312249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312257 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 312261 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312266 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 312270 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 312274 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312278 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 312282 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312287 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 312289 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 312289 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 312292 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312296 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312301 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 312307 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312312 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312317 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 312320 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312324 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312329 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 312335 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312340 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 312348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312350 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312353 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 312356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 312360 */     GIR_RootConstrainSelectedInstOperands,
     /* 312361 */     // GIR_Coverage, 4934,
     /* 312361 */     GIR_EraseRootFromParent_Done,
     /* 312362 */   // Label 6246: @312362
     /* 312362 */   GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(312509), // Rule ID 4898 //
     /* 312367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 312370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 312386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312391 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 312395 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 312399 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312403 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 312407 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 312411 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312415 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312419 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 312423 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312428 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 312432 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312436 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 312438 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 312438 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 312441 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312445 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312450 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 312456 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312461 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312466 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 312469 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312473 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312478 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 312484 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312489 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 312497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312499 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312502 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 312505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 312507 */     GIR_RootConstrainSelectedInstOperands,
     /* 312508 */     // GIR_Coverage, 4898,
     /* 312508 */     GIR_EraseRootFromParent_Done,
     /* 312509 */   // Label 6247: @312509
     /* 312509 */   GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(312656), // Rule ID 14175 //
     /* 312514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 312517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 312529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 312533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312537 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312541 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 312545 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312550 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 312554 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 312558 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312562 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312566 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 312570 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312575 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 312579 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312583 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 312585 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 312585 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 312588 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312592 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312597 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 312603 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312613 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 312616 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312620 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312625 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 312631 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312636 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 312644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312646 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312649 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 312652 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 312654 */     GIR_RootConstrainSelectedInstOperands,
     /* 312655 */     // GIR_Coverage, 14175,
     /* 312655 */     GIR_EraseRootFromParent_Done,
     /* 312656 */   // Label 6248: @312656
     /* 312656 */   GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(312787), // Rule ID 6153 //
     /* 312661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 312664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312676 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 312680 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312685 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 312689 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 312693 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312697 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 312701 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 312705 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312709 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312713 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 312717 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 312722 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 312726 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312730 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 312734 */     // MIs[4] Operand 1
     /* 312734 */     // No operand predicates
     /* 312734 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312738 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 312740 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 312740 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 312743 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312747 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312752 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 312758 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312763 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 312771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 312773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 312775 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 312782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 312785 */     GIR_RootConstrainSelectedInstOperands,
     /* 312786 */     // GIR_Coverage, 6153,
     /* 312786 */     GIR_EraseRootFromParent_Done,
     /* 312787 */   // Label 6249: @312787
     /* 312787 */   GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(312918), // Rule ID 6185 //
     /* 312792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 312795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312807 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 312811 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 312816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 312820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312824 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 312828 */     // MIs[2] Operand 1
     /* 312828 */     // No operand predicates
     /* 312828 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 312832 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312836 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 312840 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 312844 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312848 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312852 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 312856 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312861 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 312865 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312869 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 312871 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 312871 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 312874 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312878 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312883 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 312889 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 312894 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 312902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 312904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 312906 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312913 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 312916 */     GIR_RootConstrainSelectedInstOperands,
     /* 312917 */     // GIR_Coverage, 6185,
     /* 312917 */     GIR_EraseRootFromParent_Done,
     /* 312918 */   // Label 6250: @312918
     /* 312918 */   GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(313049), // Rule ID 6249 //
     /* 312923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 312926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 312934 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 312938 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 312942 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312946 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312950 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 312954 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 312959 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 312963 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 312967 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 312971 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 312975 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 312979 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 312984 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 312988 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312992 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 312996 */     // MIs[4] Operand 1
     /* 312996 */     // No operand predicates
     /* 312996 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313000 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 313002 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 313002 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313005 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313009 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313014 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313020 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313025 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 313033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 313035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 313037 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 313044 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 313047 */     GIR_RootConstrainSelectedInstOperands,
     /* 313048 */     // GIR_Coverage, 6249,
     /* 313048 */     GIR_EraseRootFromParent_Done,
     /* 313049 */   // Label 6251: @313049
     /* 313049 */   GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(313180), // Rule ID 6217 //
     /* 313054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 313057 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313061 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313065 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 313069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 313073 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313077 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313081 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 313085 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 313090 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 313094 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 313098 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 313102 */     // MIs[3] Operand 1
     /* 313102 */     // No operand predicates
     /* 313102 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 313106 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313110 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313114 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 313118 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313123 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 313127 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313131 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 313133 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 313133 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313136 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313140 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313145 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313151 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313156 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 313164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 313166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 313168 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 313175 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 313178 */     GIR_RootConstrainSelectedInstOperands,
     /* 313179 */     // GIR_Coverage, 6217,
     /* 313179 */     GIR_EraseRootFromParent_Done,
     /* 313180 */   // Label 6252: @313180
     /* 313180 */   GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(313315), // Rule ID 2463 //
     /* 313185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313196 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313200 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313204 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313209 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 313213 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 313217 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313221 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313225 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 313229 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313234 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 313238 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313242 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 313244 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 313244 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 313247 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313251 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313256 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 313262 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313267 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313272 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313275 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313279 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313284 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313290 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313295 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 313303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313305 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313308 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 313311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 313313 */     GIR_RootConstrainSelectedInstOperands,
     /* 313314 */     // GIR_Coverage, 2463,
     /* 313314 */     GIR_EraseRootFromParent_Done,
     /* 313315 */   // Label 6253: @313315
     /* 313315 */   GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(313434), // Rule ID 6121 //
     /* 313320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 313323 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313327 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313331 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313335 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313339 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313344 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 313348 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 313352 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313356 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313360 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 313364 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 313369 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 313373 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 313377 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 313381 */     // MIs[3] Operand 1
     /* 313381 */     // No operand predicates
     /* 313381 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313385 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 313387 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 313387 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313390 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313394 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313399 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313405 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313410 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 313418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 313420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 313422 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 313429 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 313432 */     GIR_RootConstrainSelectedInstOperands,
     /* 313433 */     // GIR_Coverage, 6121,
     /* 313433 */     GIR_EraseRootFromParent_Done,
     /* 313434 */   // Label 6254: @313434
     /* 313434 */   GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(313553), // Rule ID 2538 //
     /* 313439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 313442 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313446 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313450 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313454 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313458 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 313463 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 313467 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 313471 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 313475 */     // MIs[2] Operand 1
     /* 313475 */     // No operand predicates
     /* 313475 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 313479 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313483 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313487 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 313491 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313496 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 313500 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313504 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 313506 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 313506 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313509 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313518 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313524 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313529 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 313537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 313539 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 313541 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 313548 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 313551 */     GIR_RootConstrainSelectedInstOperands,
     /* 313552 */     // GIR_Coverage, 2538,
     /* 313552 */     GIR_EraseRootFromParent_Done,
     /* 313553 */   // Label 6255: @313553
     /* 313553 */   GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(313653), // Rule ID 4896 //
     /* 313558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313569 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313573 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313577 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313582 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 313586 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 313590 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313594 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 313598 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313603 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313607 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 313609 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 313609 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313612 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313616 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313621 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313627 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313632 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 313640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313642 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313645 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 313649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 313651 */     GIR_RootConstrainSelectedInstOperands,
     /* 313652 */     // GIR_Coverage, 4896,
     /* 313652 */     GIR_EraseRootFromParent_Done,
     /* 313653 */   // Label 6256: @313653
     /* 313653 */   GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(313753), // Rule ID 4932 //
     /* 313658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313673 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313677 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313682 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 313686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 313694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 313702 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313707 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 313709 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 313709 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313712 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313716 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313721 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313727 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313732 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 313740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313742 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 313747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 313751 */     GIR_RootConstrainSelectedInstOperands,
     /* 313752 */     // GIR_Coverage, 4932,
     /* 313752 */     GIR_EraseRootFromParent_Done,
     /* 313753 */   // Label 6257: @313753
     /* 313753 */   GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(313850), // Rule ID 14171 //
     /* 313758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313765 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313769 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 313773 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 313777 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313781 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313785 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 313789 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313794 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 313798 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313802 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313806 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 313808 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 313808 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313811 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313815 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313820 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 313826 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313831 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 313839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313843 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 313848 */     GIR_RootConstrainSelectedInstOperands,
     /* 313849 */     // GIR_Coverage, 14171,
     /* 313849 */     GIR_EraseRootFromParent_Done,
     /* 313850 */   // Label 6258: @313850
     /* 313850 */   GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(313950), // Rule ID 14173 //
     /* 313855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 313862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313866 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 313870 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 313879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313883 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313887 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 313891 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313896 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 313900 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313904 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 313906 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 313906 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 313909 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 313913 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 313918 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 313924 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313929 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 313937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313939 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 313942 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 313946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 313948 */     GIR_RootConstrainSelectedInstOperands,
     /* 313949 */     // GIR_Coverage, 14173,
     /* 313949 */     GIR_EraseRootFromParent_Done,
     /* 313950 */   // Label 6259: @313950
     /* 313950 */   GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(314050), // Rule ID 4930 //
     /* 313955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 313958 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 313962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 313970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 313974 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 313978 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 313983 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 313987 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 313991 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 313995 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 313999 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314004 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314006 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 314006 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 314009 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 314013 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 314018 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 314024 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314029 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 314037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314039 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 314041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 314044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 314048 */     GIR_RootConstrainSelectedInstOperands,
     /* 314049 */     // GIR_Coverage, 4930,
     /* 314049 */     GIR_EraseRootFromParent_Done,
     /* 314050 */   // Label 6260: @314050
     /* 314050 */   GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(314147), // Rule ID 4894 //
     /* 314055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 314058 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314070 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314074 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 314078 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314082 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314086 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 314090 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314095 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 314099 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314105 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 314105 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 314108 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 314112 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 314117 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 314123 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314128 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 314136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314138 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 314140 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 314143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 314145 */     GIR_RootConstrainSelectedInstOperands,
     /* 314146 */     // GIR_Coverage, 4894,
     /* 314146 */     GIR_EraseRootFromParent_Done,
     /* 314147 */   // Label 6261: @314147
     /* 314147 */   GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(314231), // Rule ID 6183 //
     /* 314152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314167 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 314171 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 314180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314184 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314188 */     // MIs[2] Operand 1
     /* 314188 */     // No operand predicates
     /* 314188 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 314192 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314196 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 314200 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314205 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314209 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 314211 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 314214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314218 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 314222 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 314226 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 314229 */     GIR_RootConstrainSelectedInstOperands,
     /* 314230 */     // GIR_Coverage, 6183,
     /* 314230 */     GIR_EraseRootFromParent_Done,
     /* 314231 */   // Label 6262: @314231
     /* 314231 */   GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(314312), // Rule ID 6215 //
     /* 314236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314247 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314251 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 314255 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314259 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314263 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 314267 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314272 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 314276 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314280 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314284 */     // MIs[3] Operand 1
     /* 314284 */     // No operand predicates
     /* 314284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314292 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 314294 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 314297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 314307 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 314310 */     GIR_RootConstrainSelectedInstOperands,
     /* 314311 */     // GIR_Coverage, 6215,
     /* 314311 */     GIR_EraseRootFromParent_Done,
     /* 314312 */   // Label 6263: @314312
     /* 314312 */   GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(314396), // Rule ID 6247 //
     /* 314317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314328 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314332 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 314341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314345 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314349 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 314353 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314358 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 314362 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314366 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314370 */     // MIs[3] Operand 1
     /* 314370 */     // No operand predicates
     /* 314370 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 314376 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 314379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 314387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 314391 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 314394 */     GIR_RootConstrainSelectedInstOperands,
     /* 314395 */     // GIR_Coverage, 6247,
     /* 314395 */     GIR_EraseRootFromParent_Done,
     /* 314396 */   // Label 6264: @314396
     /* 314396 */   GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(314477), // Rule ID 6151 //
     /* 314401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314404 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314408 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314412 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314416 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314420 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 314424 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314428 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314432 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 314436 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314441 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 314445 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314449 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314453 */     // MIs[3] Operand 1
     /* 314453 */     // No operand predicates
     /* 314453 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314457 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 314459 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 314462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314464 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314466 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 314468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 314472 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 314475 */     GIR_RootConstrainSelectedInstOperands,
     /* 314476 */     // GIR_Coverage, 6151,
     /* 314476 */     GIR_EraseRootFromParent_Done,
     /* 314477 */   // Label 6265: @314477
     /* 314477 */   GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(314562), // Rule ID 2461 //
     /* 314482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 314485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314497 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 314501 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314506 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 314510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314514 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314518 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314520 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 314520 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 314523 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 314527 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 314532 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 314538 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 314551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314553 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 314556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 314558 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 314560 */     GIR_RootConstrainSelectedInstOperands,
     /* 314561 */     // GIR_Coverage, 2461,
     /* 314561 */     GIR_EraseRootFromParent_Done,
     /* 314562 */   // Label 6266: @314562
     /* 314562 */   GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(314647), // Rule ID 2459 //
     /* 314567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 314570 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314574 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314578 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314582 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314586 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 314590 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314595 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 314599 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314603 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314605 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 314605 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 314608 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 314612 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 314617 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 314623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314628 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 314636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314638 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 314640 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 314643 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 314645 */     GIR_RootConstrainSelectedInstOperands,
     /* 314646 */     // GIR_Coverage, 2459,
     /* 314646 */     GIR_EraseRootFromParent_Done,
     /* 314647 */   // Label 6267: @314647
     /* 314647 */   GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(314716), // Rule ID 2536 //
     /* 314652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314663 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314667 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 314671 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 314680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314684 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314688 */     // MIs[2] Operand 1
     /* 314688 */     // No operand predicates
     /* 314688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314692 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314696 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314698 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 314701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314703 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 314711 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 314714 */     GIR_RootConstrainSelectedInstOperands,
     /* 314715 */     // GIR_Coverage, 2536,
     /* 314715 */     GIR_EraseRootFromParent_Done,
     /* 314716 */   // Label 6268: @314716
     /* 314716 */   GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(314785), // Rule ID 6119 //
     /* 314721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314724 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314732 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 314736 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 314740 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 314744 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 314749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 314753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 314757 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 314761 */     // MIs[2] Operand 1
     /* 314761 */     // No operand predicates
     /* 314761 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314765 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314767 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 314767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 314770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 314772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 314774 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 314776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 314780 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 314783 */     GIR_RootConstrainSelectedInstOperands,
     /* 314784 */     // GIR_Coverage, 6119,
     /* 314784 */     GIR_EraseRootFromParent_Done,
     /* 314785 */   // Label 6269: @314785
     /* 314785 */   GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(314850), // Rule ID 4950 //
     /* 314790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314805 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314814 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 314818 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314822 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 314826 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314831 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314833 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 314833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 314836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314838 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 314842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 314844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 314848 */     GIR_RootConstrainSelectedInstOperands,
     /* 314849 */     // GIR_Coverage, 4950,
     /* 314849 */     GIR_EraseRootFromParent_Done,
     /* 314850 */   // Label 6270: @314850
     /* 314850 */   GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(314915), // Rule ID 14191 //
     /* 314855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314858 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314874 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 314883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 314891 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314896 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 314898 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 314898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 314901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 314907 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 314909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 314913 */     GIR_RootConstrainSelectedInstOperands,
     /* 314914 */     // GIR_Coverage, 14191,
     /* 314914 */     GIR_EraseRootFromParent_Done,
     /* 314915 */   // Label 6271: @314915
     /* 314915 */   GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(314965), // Rule ID 4947 //
     /* 314920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 314923 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314927 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314931 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314935 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314944 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314948 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314950 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 314950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 314953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314955 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 314959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 314961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 314963 */     GIR_RootConstrainSelectedInstOperands,
     /* 314964 */     // GIR_Coverage, 4947,
     /* 314964 */     GIR_EraseRootFromParent_Done,
     /* 314965 */   // Label 6272: @314965
     /* 314965 */   GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(315015), // Rule ID 13602 //
     /* 314970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 314973 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 314977 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 314981 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 314985 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314994 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 314998 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315000 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 315000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 315003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315005 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 315011 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 315013 */     GIR_RootConstrainSelectedInstOperands,
     /* 315014 */     // GIR_Coverage, 13602,
     /* 315014 */     GIR_EraseRootFromParent_Done,
     /* 315015 */   // Label 6273: @315015
     /* 315015 */   GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(315065), // Rule ID 648 //
     /* 315020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 315023 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315027 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315035 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 315039 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315044 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315048 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315050 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 315050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 315053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315055 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 315057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 315061 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 315063 */     GIR_RootConstrainSelectedInstOperands,
     /* 315064 */     // GIR_Coverage, 648,
     /* 315064 */     GIR_EraseRootFromParent_Done,
     /* 315065 */   // Label 6274: @315065
     /* 315065 */   GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(315115), // Rule ID 14188 //
     /* 315070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 315073 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 315089 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315094 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315098 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315100 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 315100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 315103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315105 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 315109 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 315111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 315113 */     GIR_RootConstrainSelectedInstOperands,
     /* 315114 */     // GIR_Coverage, 14188,
     /* 315114 */     GIR_EraseRootFromParent_Done,
     /* 315115 */   // Label 6275: @315115
     /* 315115 */   GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(315165), // Rule ID 660 //
     /* 315120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 315123 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315127 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 315143 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315148 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315150 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 315150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 315153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315155 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 315157 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 315159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 315163 */     GIR_RootConstrainSelectedInstOperands,
     /* 315164 */     // GIR_Coverage, 660,
     /* 315164 */     GIR_EraseRootFromParent_Done,
     /* 315165 */   // Label 6276: @315165
     /* 315165 */   GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(315196), // Rule ID 642 //
     /* 315170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 315173 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315181 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 315185 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 315185 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 315190 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 315194 */     GIR_RootConstrainSelectedInstOperands,
     /* 315195 */     // GIR_Coverage, 642,
     /* 315195 */     GIR_Done,
     /* 315196 */   // Label 6277: @315196
     /* 315196 */   GIM_Reject,
     /* 315197 */ // Label 6245: @315197
     /* 315197 */ GIM_Reject,
     /* 315198 */ // Label 6237: @315198
     /* 315198 */ GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(318345),
     /* 315203 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 315206 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 315209 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 315212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315216 */   GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(315366), // Rule ID 4940 //
     /* 315221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 315224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 315240 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315245 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 315249 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 315253 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315257 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315261 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 315265 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315270 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 315274 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 315278 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315282 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 315286 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315291 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 315293 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 315293 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 315296 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315300 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315305 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 315311 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315316 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315321 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 315324 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315328 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315333 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 315339 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315344 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 315352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315354 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 315357 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 315360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 315364 */     GIR_RootConstrainSelectedInstOperands,
     /* 315365 */     // GIR_Coverage, 4940,
     /* 315365 */     GIR_EraseRootFromParent_Done,
     /* 315366 */   // Label 6279: @315366
     /* 315366 */   GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(315513), // Rule ID 4904 //
     /* 315371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 315374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315386 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 315390 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315395 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 315399 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 315403 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315407 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 315411 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 315415 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315419 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315423 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 315427 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315432 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 315436 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315440 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 315442 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 315442 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 315445 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315449 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315454 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 315460 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315465 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315470 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 315473 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315477 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315482 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 315488 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315493 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 315501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315503 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 315506 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 315509 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 315511 */     GIR_RootConstrainSelectedInstOperands,
     /* 315512 */     // GIR_Coverage, 4904,
     /* 315512 */     GIR_EraseRootFromParent_Done,
     /* 315513 */   // Label 6280: @315513
     /* 315513 */   GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(315660), // Rule ID 14181 //
     /* 315518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 315521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315529 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 315533 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 315537 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315541 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315545 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 315549 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315554 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 315558 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 315562 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315566 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315570 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 315574 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315579 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 315583 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315587 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 315589 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 315589 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 315592 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315596 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315601 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 315607 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315612 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315617 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 315620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315624 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315629 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 315635 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315640 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 315648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315650 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 315653 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 315656 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 315658 */     GIR_RootConstrainSelectedInstOperands,
     /* 315659 */     // GIR_Coverage, 14181,
     /* 315659 */     GIR_EraseRootFromParent_Done,
     /* 315660 */   // Label 6281: @315660
     /* 315660 */   GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(315791), // Rule ID 6169 //
     /* 315665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315676 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315680 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 315684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315689 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 315693 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 315697 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315701 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 315705 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 315709 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315713 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315717 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 315721 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315726 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 315730 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 315734 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 315738 */     // MIs[4] Operand 1
     /* 315738 */     // No operand predicates
     /* 315738 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315742 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 315744 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 315744 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 315747 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315751 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315756 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 315762 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315767 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 315775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 315777 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 315779 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 315782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 315786 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 315789 */     GIR_RootConstrainSelectedInstOperands,
     /* 315790 */     // GIR_Coverage, 6169,
     /* 315790 */     GIR_EraseRootFromParent_Done,
     /* 315791 */   // Label 6282: @315791
     /* 315791 */   GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(315922), // Rule ID 6201 //
     /* 315796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315811 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 315815 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 315824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 315828 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 315832 */     // MIs[2] Operand 1
     /* 315832 */     // No operand predicates
     /* 315832 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 315836 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315840 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 315844 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 315848 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315852 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315856 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 315860 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315865 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 315869 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315873 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 315875 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 315875 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 315878 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 315882 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 315887 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 315893 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 315898 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 315906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 315908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 315910 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 315913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 315917 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 315920 */     GIR_RootConstrainSelectedInstOperands,
     /* 315921 */     // GIR_Coverage, 6201,
     /* 315921 */     GIR_EraseRootFromParent_Done,
     /* 315922 */   // Label 6283: @315922
     /* 315922 */   GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(316053), // Rule ID 6265 //
     /* 315927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315930 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 315934 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 315938 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 315942 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 315946 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315950 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315954 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 315958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315963 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 315967 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 315971 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 315975 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 315979 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 315983 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315988 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 315992 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 315996 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 316000 */     // MIs[4] Operand 1
     /* 316000 */     // No operand predicates
     /* 316000 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316004 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 316006 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 316006 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316009 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316013 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316018 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316024 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316029 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 316037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 316039 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 316041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 316048 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 316051 */     GIR_RootConstrainSelectedInstOperands,
     /* 316052 */     // GIR_Coverage, 6265,
     /* 316052 */     GIR_EraseRootFromParent_Done,
     /* 316053 */   // Label 6284: @316053
     /* 316053 */   GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(316184), // Rule ID 6233 //
     /* 316058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316061 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316065 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316069 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 316073 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 316077 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316081 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316085 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 316089 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316094 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 316098 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 316102 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 316106 */     // MIs[3] Operand 1
     /* 316106 */     // No operand predicates
     /* 316106 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 316110 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316114 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316118 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 316122 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316127 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 316131 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316135 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 316137 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 316137 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316140 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316144 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316149 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316155 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316160 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 316168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 316170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 316172 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 316179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 316182 */     GIR_RootConstrainSelectedInstOperands,
     /* 316183 */     // GIR_Coverage, 6233,
     /* 316183 */     GIR_EraseRootFromParent_Done,
     /* 316184 */   // Label 6285: @316184
     /* 316184 */   GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(316319), // Rule ID 2469 //
     /* 316189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316192 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316196 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316200 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316204 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316208 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316213 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 316217 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 316221 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316225 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316229 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 316233 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316238 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 316242 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316246 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 316248 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 316248 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 316251 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316255 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316260 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 316266 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316271 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316276 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316279 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316283 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316288 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316294 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316299 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 316307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316309 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316312 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 316315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 316317 */     GIR_RootConstrainSelectedInstOperands,
     /* 316318 */     // GIR_Coverage, 2469,
     /* 316318 */     GIR_EraseRootFromParent_Done,
     /* 316319 */   // Label 6286: @316319
     /* 316319 */   GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(316438), // Rule ID 6137 //
     /* 316324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316327 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316331 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316335 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316339 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316343 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316348 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 316352 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 316356 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316360 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316364 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 316368 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316373 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 316377 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 316381 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 316385 */     // MIs[3] Operand 1
     /* 316385 */     // No operand predicates
     /* 316385 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316389 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 316391 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 316391 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316394 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316398 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316403 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316409 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316414 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 316422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 316424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 316426 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 316433 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 316436 */     GIR_RootConstrainSelectedInstOperands,
     /* 316437 */     // GIR_Coverage, 6137,
     /* 316437 */     GIR_EraseRootFromParent_Done,
     /* 316438 */   // Label 6287: @316438
     /* 316438 */   GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(316557), // Rule ID 2554 //
     /* 316443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316454 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316458 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316462 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316467 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 316471 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 316475 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 316479 */     // MIs[2] Operand 1
     /* 316479 */     // No operand predicates
     /* 316479 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 316483 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316487 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316491 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 316495 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316500 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 316504 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316508 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 316510 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 316510 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316513 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316517 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316522 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316528 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316533 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 316541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 316543 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 316545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 316552 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 316555 */     GIR_RootConstrainSelectedInstOperands,
     /* 316556 */     // GIR_Coverage, 2554,
     /* 316556 */     GIR_EraseRootFromParent_Done,
     /* 316557 */   // Label 6288: @316557
     /* 316557 */   GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(316657), // Rule ID 4902 //
     /* 316562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316586 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 316590 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 316594 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316598 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 316602 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316607 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 316613 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 316613 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316616 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316620 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316625 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316631 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316636 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 316644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316646 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316649 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 316653 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 316655 */     GIR_RootConstrainSelectedInstOperands,
     /* 316656 */     // GIR_Coverage, 4902,
     /* 316656 */     GIR_EraseRootFromParent_Done,
     /* 316657 */   // Label 6289: @316657
     /* 316657 */   GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(316757), // Rule ID 4938 //
     /* 316662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316677 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316681 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316686 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 316690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 316698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316702 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 316706 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316711 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 316713 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 316713 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316716 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316720 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316725 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316731 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316736 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 316744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316746 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 316751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 316755 */     GIR_RootConstrainSelectedInstOperands,
     /* 316756 */     // GIR_Coverage, 4938,
     /* 316756 */     GIR_EraseRootFromParent_Done,
     /* 316757 */   // Label 6290: @316757
     /* 316757 */   GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(316854), // Rule ID 14177 //
     /* 316762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316765 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 316777 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 316781 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316785 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316789 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 316793 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316798 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 316802 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316806 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316810 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 316812 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 316812 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316815 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316819 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316824 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 316830 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316835 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 316843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316847 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316850 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 316852 */     GIR_RootConstrainSelectedInstOperands,
     /* 316853 */     // GIR_Coverage, 14177,
     /* 316853 */     GIR_EraseRootFromParent_Done,
     /* 316854 */   // Label 6291: @316854
     /* 316854 */   GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(316954), // Rule ID 14179 //
     /* 316859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 316866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 316874 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 316883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316891 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 316895 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316900 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 316904 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316908 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 316910 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 316910 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 316913 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 316917 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 316922 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 316928 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316933 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 316941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316943 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 316946 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 316950 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 316952 */     GIR_RootConstrainSelectedInstOperands,
     /* 316953 */     // GIR_Coverage, 14179,
     /* 316953 */     GIR_EraseRootFromParent_Done,
     /* 316954 */   // Label 6292: @316954
     /* 316954 */   GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(317054), // Rule ID 4936 //
     /* 316959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 316962 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 316966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316970 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 316974 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 316978 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 316982 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316987 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 316991 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 316995 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 316999 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 317003 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317008 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 317010 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 317010 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 317013 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 317017 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 317022 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 317028 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317033 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 317041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317045 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 317048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 317052 */     GIR_RootConstrainSelectedInstOperands,
     /* 317053 */     // GIR_Coverage, 4936,
     /* 317053 */     GIR_EraseRootFromParent_Done,
     /* 317054 */   // Label 6293: @317054
     /* 317054 */   GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(317151), // Rule ID 4900 //
     /* 317059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 317062 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317074 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 317078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 317082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317086 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317090 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 317094 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317099 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 317103 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317107 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 317109 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 317109 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 317112 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 317116 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 317121 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 317127 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317132 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 317140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317142 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317144 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 317147 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 317149 */     GIR_RootConstrainSelectedInstOperands,
     /* 317150 */     // GIR_Coverage, 4900,
     /* 317150 */     GIR_EraseRootFromParent_Done,
     /* 317151 */   // Label 6294: @317151
     /* 317151 */   GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(317229), // Rule ID 6287 //
     /* 317156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317172 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 317176 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317180 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317184 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317189 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 317193 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317197 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317201 */     // MIs[3] Operand 1
     /* 317201 */     // No operand predicates
     /* 317201 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317205 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317209 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317211 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 317224 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 317227 */     GIR_RootConstrainSelectedInstOperands,
     /* 317228 */     // GIR_Coverage, 6287,
     /* 317228 */     GIR_EraseRootFromParent_Done,
     /* 317229 */   // Label 6295: @317229
     /* 317229 */   GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(317313), // Rule ID 6199 //
     /* 317234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317249 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 317262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317266 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317270 */     // MIs[2] Operand 1
     /* 317270 */     // No operand predicates
     /* 317270 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 317274 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317278 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 317282 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317287 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317291 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317293 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 317304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 317308 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 317311 */     GIR_RootConstrainSelectedInstOperands,
     /* 317312 */     // GIR_Coverage, 6199,
     /* 317312 */     GIR_EraseRootFromParent_Done,
     /* 317313 */   // Label 6296: @317313
     /* 317313 */   GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(317394), // Rule ID 6231 //
     /* 317318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 317333 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 317337 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317341 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317345 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 317349 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317354 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 317358 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317362 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317366 */     // MIs[3] Operand 1
     /* 317366 */     // No operand predicates
     /* 317366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317370 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317376 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 317389 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 317392 */     GIR_RootConstrainSelectedInstOperands,
     /* 317393 */     // GIR_Coverage, 6231,
     /* 317393 */     GIR_EraseRootFromParent_Done,
     /* 317394 */   // Label 6297: @317394
     /* 317394 */   GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(317478), // Rule ID 6263 //
     /* 317399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 317414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 317423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317427 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317431 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 317435 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317440 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 317444 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317448 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317452 */     // MIs[3] Operand 1
     /* 317452 */     // No operand predicates
     /* 317452 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317456 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317458 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317463 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 317469 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 317473 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 317476 */     GIR_RootConstrainSelectedInstOperands,
     /* 317477 */     // GIR_Coverage, 6263,
     /* 317477 */     GIR_EraseRootFromParent_Done,
     /* 317478 */   // Label 6298: @317478
     /* 317478 */   GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(317556), // Rule ID 6309 //
     /* 317483 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317503 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 317507 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317511 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317515 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317520 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 317524 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317528 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317532 */     // MIs[3] Operand 1
     /* 317532 */     // No operand predicates
     /* 317532 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317536 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317538 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317543 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317545 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317547 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 317551 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 317554 */     GIR_RootConstrainSelectedInstOperands,
     /* 317555 */     // GIR_Coverage, 6309,
     /* 317555 */     GIR_EraseRootFromParent_Done,
     /* 317556 */   // Label 6299: @317556
     /* 317556 */   GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(317637), // Rule ID 6167 //
     /* 317561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317564 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317568 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317572 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317576 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 317580 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 317584 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317588 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317592 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 317596 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317601 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 317605 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317609 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317613 */     // MIs[3] Operand 1
     /* 317613 */     // No operand predicates
     /* 317613 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317617 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 317619 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 317622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317624 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317626 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 317632 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 317635 */     GIR_RootConstrainSelectedInstOperands,
     /* 317636 */     // GIR_Coverage, 6167,
     /* 317636 */     GIR_EraseRootFromParent_Done,
     /* 317637 */   // Label 6300: @317637
     /* 317637 */   GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(317722), // Rule ID 2467 //
     /* 317642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 317645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317649 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317653 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317657 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317666 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 317670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317674 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317678 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317680 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 317680 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 317683 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 317687 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 317692 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 317698 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317703 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 317711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317713 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 317716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 317718 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 317720 */     GIR_RootConstrainSelectedInstOperands,
     /* 317721 */     // GIR_Coverage, 2467,
     /* 317721 */     GIR_EraseRootFromParent_Done,
     /* 317722 */   // Label 6301: @317722
     /* 317722 */   GIM_Try, /*On fail goto*//*Label 6302*/ GIMT_Encode4(317807), // Rule ID 2465 //
     /* 317727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 317730 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317734 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317738 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317742 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317746 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317750 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317755 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 317759 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317763 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317765 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 317765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 317768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 317772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 317777 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 317783 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 317796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317800 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 317803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 317805 */     GIR_RootConstrainSelectedInstOperands,
     /* 317806 */     // GIR_Coverage, 2465,
     /* 317806 */     GIR_EraseRootFromParent_Done,
     /* 317807 */   // Label 6302: @317807
     /* 317807 */   GIM_Try, /*On fail goto*//*Label 6303*/ GIMT_Encode4(317876), // Rule ID 2552 //
     /* 317812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317827 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317831 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 317840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317844 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317848 */     // MIs[2] Operand 1
     /* 317848 */     // No operand predicates
     /* 317848 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317852 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317856 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 317858 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 317861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317863 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 317871 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 317874 */     GIR_RootConstrainSelectedInstOperands,
     /* 317875 */     // GIR_Coverage, 2552,
     /* 317875 */     GIR_EraseRootFromParent_Done,
     /* 317876 */   // Label 6303: @317876
     /* 317876 */   GIM_Try, /*On fail goto*//*Label 6304*/ GIMT_Encode4(317945), // Rule ID 6135 //
     /* 317881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317884 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 317896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 317900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 317904 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317909 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 317913 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 317917 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 317921 */     // MIs[2] Operand 1
     /* 317921 */     // No operand predicates
     /* 317921 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317925 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 317927 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 317927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 317930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 317932 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 317934 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 317936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 317940 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 317943 */     GIR_RootConstrainSelectedInstOperands,
     /* 317944 */     // GIR_Coverage, 6135,
     /* 317944 */     GIR_EraseRootFromParent_Done,
     /* 317945 */   // Label 6304: @317945
     /* 317945 */   GIM_Try, /*On fail goto*//*Label 6305*/ GIMT_Encode4(318007), // Rule ID 4951 //
     /* 317950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 317954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 317962 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317971 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 317975 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 317979 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 317983 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 317988 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 317990 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 317990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 317993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 317999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 318001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 318005 */     GIR_RootConstrainSelectedInstOperands,
     /* 318006 */     // GIR_Coverage, 4951,
     /* 318006 */     GIR_EraseRootFromParent_Done,
     /* 318007 */   // Label 6305: @318007
     /* 318007 */   GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(318069), // Rule ID 14192 //
     /* 318012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318028 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318033 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 318037 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318041 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 318045 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318050 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 318052 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 318055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 318061 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 318063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 318067 */     GIR_RootConstrainSelectedInstOperands,
     /* 318068 */     // GIR_Coverage, 14192,
     /* 318068 */     GIR_EraseRootFromParent_Done,
     /* 318069 */   // Label 6306: @318069
     /* 318069 */   GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(318116), // Rule ID 4948 //
     /* 318074 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318078 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318082 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318086 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318091 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318095 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318099 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318101 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 318104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318106 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 318110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 318112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318114 */     GIR_RootConstrainSelectedInstOperands,
     /* 318115 */     // GIR_Coverage, 4948,
     /* 318115 */     GIR_EraseRootFromParent_Done,
     /* 318116 */   // Label 6307: @318116
     /* 318116 */   GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(318166), // Rule ID 13604 //
     /* 318121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318124 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318128 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318132 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318136 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318141 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318145 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318149 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318151 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 318154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 318162 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318164 */     GIR_RootConstrainSelectedInstOperands,
     /* 318165 */     // GIR_Coverage, 13604,
     /* 318165 */     GIR_EraseRootFromParent_Done,
     /* 318166 */   // Label 6308: @318166
     /* 318166 */   GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(318216), // Rule ID 650 //
     /* 318171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318174 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318178 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318182 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318186 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318190 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318195 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318199 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318201 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 318204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318206 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 318208 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 318212 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318214 */     GIR_RootConstrainSelectedInstOperands,
     /* 318215 */     // GIR_Coverage, 650,
     /* 318215 */     GIR_EraseRootFromParent_Done,
     /* 318216 */   // Label 6309: @318216
     /* 318216 */   GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(318263), // Rule ID 14189 //
     /* 318221 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318225 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318229 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318233 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318242 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318246 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318248 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 318251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 318257 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 318259 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318261 */     GIR_RootConstrainSelectedInstOperands,
     /* 318262 */     // GIR_Coverage, 14189,
     /* 318262 */     GIR_EraseRootFromParent_Done,
     /* 318263 */   // Label 6310: @318263
     /* 318263 */   GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(318313), // Rule ID 662 //
     /* 318268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318271 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 318291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318298 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 318301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318303 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 318305 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 318307 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 318311 */     GIR_RootConstrainSelectedInstOperands,
     /* 318312 */     // GIR_Coverage, 662,
     /* 318312 */     GIR_EraseRootFromParent_Done,
     /* 318313 */   // Label 6311: @318313
     /* 318313 */   GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(318344), // Rule ID 644 //
     /* 318318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318329 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 318333 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 318333 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 318338 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 318342 */     GIR_RootConstrainSelectedInstOperands,
     /* 318343 */     // GIR_Coverage, 644,
     /* 318343 */     GIR_Done,
     /* 318344 */   // Label 6312: @318344
     /* 318344 */   GIM_Reject,
     /* 318345 */ // Label 6278: @318345
     /* 318345 */ GIM_Reject,
     /* 318346 */ // Label 6238: @318346
     /* 318346 */ GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(321493),
     /* 318351 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 318354 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 318357 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 318360 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318364 */   GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(318514), // Rule ID 4946 //
     /* 318369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318384 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 318388 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318393 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 318397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 318401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318405 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318409 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 318413 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318418 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 318422 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 318426 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318430 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 318434 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318439 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 318441 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 318441 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 318444 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318448 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318453 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 318459 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318464 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318469 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 318472 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318476 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318481 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 318487 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318492 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 318500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318502 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 318505 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 318508 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 318512 */     GIR_RootConstrainSelectedInstOperands,
     /* 318513 */     // GIR_Coverage, 4946,
     /* 318513 */     GIR_EraseRootFromParent_Done,
     /* 318514 */   // Label 6314: @318514
     /* 318514 */   GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(318661), // Rule ID 4910 //
     /* 318519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318522 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318526 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318530 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318534 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 318538 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318543 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 318547 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 318551 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318555 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 318559 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 318563 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318567 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318571 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 318575 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318580 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 318584 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318588 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 318590 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 318590 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 318593 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318597 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318602 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 318608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318613 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318618 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 318621 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318625 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318630 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 318636 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318641 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 318649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318651 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 318654 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 318657 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318659 */     GIR_RootConstrainSelectedInstOperands,
     /* 318660 */     // GIR_Coverage, 4910,
     /* 318660 */     GIR_EraseRootFromParent_Done,
     /* 318661 */   // Label 6315: @318661
     /* 318661 */   GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(318808), // Rule ID 14187 //
     /* 318666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 318669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318673 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318677 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 318681 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 318685 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318689 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318693 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 318697 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318702 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 318706 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 318710 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318714 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318718 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 318722 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318727 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 318731 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318735 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 318737 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 318737 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 318740 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318744 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318749 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 318755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 318768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318777 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 318783 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 318796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318798 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 318801 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 318804 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 318806 */     GIR_RootConstrainSelectedInstOperands,
     /* 318807 */     // GIR_Coverage, 14187,
     /* 318807 */     GIR_EraseRootFromParent_Done,
     /* 318808 */   // Label 6316: @318808
     /* 318808 */   GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(318939), // Rule ID 6173 //
     /* 318813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318824 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318828 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 318832 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318837 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 318841 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 318845 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318849 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 318853 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 318857 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318861 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318865 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 318869 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318874 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 318878 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 318882 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 318886 */     // MIs[4] Operand 1
     /* 318886 */     // No operand predicates
     /* 318886 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318890 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 318892 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 318892 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 318895 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 318899 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 318904 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 318910 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318915 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 318923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 318925 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 318927 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 318930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 318934 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 318937 */     GIR_RootConstrainSelectedInstOperands,
     /* 318938 */     // GIR_Coverage, 6173,
     /* 318938 */     GIR_EraseRootFromParent_Done,
     /* 318939 */   // Label 6317: @318939
     /* 318939 */   GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(319070), // Rule ID 6205 //
     /* 318944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318947 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 318951 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 318955 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 318959 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 318963 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318968 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 318972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 318976 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 318980 */     // MIs[2] Operand 1
     /* 318980 */     // No operand predicates
     /* 318980 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 318984 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 318988 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 318992 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 318996 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319000 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319004 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 319008 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319013 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 319017 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319021 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 319023 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 319023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319035 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 319054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 319056 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 319058 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 319065 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 319068 */     GIR_RootConstrainSelectedInstOperands,
     /* 319069 */     // GIR_Coverage, 6205,
     /* 319069 */     GIR_EraseRootFromParent_Done,
     /* 319070 */   // Label 6318: @319070
     /* 319070 */   GIM_Try, /*On fail goto*//*Label 6319*/ GIMT_Encode4(319201), // Rule ID 6269 //
     /* 319075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 319086 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 319090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 319094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319098 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319102 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 319106 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319111 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 319115 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 319119 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319123 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319127 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 319131 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319136 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 319140 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 319144 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 319148 */     // MIs[4] Operand 1
     /* 319148 */     // No operand predicates
     /* 319148 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319152 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 319154 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 319154 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319157 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319161 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319166 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319172 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319177 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 319185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 319187 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 319189 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319192 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 319196 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 319199 */     GIR_RootConstrainSelectedInstOperands,
     /* 319200 */     // GIR_Coverage, 6269,
     /* 319200 */     GIR_EraseRootFromParent_Done,
     /* 319201 */   // Label 6319: @319201
     /* 319201 */   GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(319332), // Rule ID 6237 //
     /* 319206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319209 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319213 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 319217 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 319221 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 319225 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319229 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319233 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 319237 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319242 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 319246 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 319250 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 319254 */     // MIs[3] Operand 1
     /* 319254 */     // No operand predicates
     /* 319254 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 319258 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319262 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319266 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 319270 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319275 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 319279 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319283 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 319285 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 319285 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319288 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319292 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319297 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319303 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319308 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 319316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 319318 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 319320 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319323 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 319327 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 319330 */     GIR_RootConstrainSelectedInstOperands,
     /* 319331 */     // GIR_Coverage, 6237,
     /* 319331 */     GIR_EraseRootFromParent_Done,
     /* 319332 */   // Label 6320: @319332
     /* 319332 */   GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(319467), // Rule ID 2475 //
     /* 319337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 319340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319348 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319352 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 319356 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319361 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 319365 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 319369 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319373 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319377 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 319381 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319386 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 319390 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319394 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 319396 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 319396 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 319399 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319403 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319408 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 319414 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319419 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319424 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319427 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319431 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319436 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319442 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319447 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 319455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319457 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319460 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 319463 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 319465 */     GIR_RootConstrainSelectedInstOperands,
     /* 319466 */     // GIR_Coverage, 2475,
     /* 319466 */     GIR_EraseRootFromParent_Done,
     /* 319467 */   // Label 6321: @319467
     /* 319467 */   GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(319586), // Rule ID 6141 //
     /* 319472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319475 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319479 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319483 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319487 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 319491 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319496 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 319500 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 319504 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319508 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319512 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 319516 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319521 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 319525 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 319529 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 319533 */     // MIs[3] Operand 1
     /* 319533 */     // No operand predicates
     /* 319533 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319537 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 319539 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 319539 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319542 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319546 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319551 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319557 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319562 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 319570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 319572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 319574 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319577 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 319581 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 319584 */     GIR_RootConstrainSelectedInstOperands,
     /* 319585 */     // GIR_Coverage, 6141,
     /* 319585 */     GIR_EraseRootFromParent_Done,
     /* 319586 */   // Label 6322: @319586
     /* 319586 */   GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(319705), // Rule ID 2558 //
     /* 319591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319594 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319598 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319602 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319606 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 319610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319615 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 319619 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 319623 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 319627 */     // MIs[2] Operand 1
     /* 319627 */     // No operand predicates
     /* 319627 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 319631 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319635 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319639 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 319643 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319648 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 319652 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319656 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 319658 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 319658 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319661 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319665 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319670 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319676 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319681 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 319689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 319691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 319693 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 319700 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 319703 */     GIR_RootConstrainSelectedInstOperands,
     /* 319704 */     // GIR_Coverage, 2558,
     /* 319704 */     GIR_EraseRootFromParent_Done,
     /* 319705 */   // Label 6323: @319705
     /* 319705 */   GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(319805), // Rule ID 4908 //
     /* 319710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 319713 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319717 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319721 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319725 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 319729 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319734 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 319738 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 319742 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 319746 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 319750 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319755 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319759 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 319761 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 319761 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319764 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319768 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319773 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319779 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319784 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 319792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319794 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 319801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 319803 */     GIR_RootConstrainSelectedInstOperands,
     /* 319804 */     // GIR_Coverage, 4908,
     /* 319804 */     GIR_EraseRootFromParent_Done,
     /* 319805 */   // Label 6324: @319805
     /* 319805 */   GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(319905), // Rule ID 4944 //
     /* 319810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 319813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 319829 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319834 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 319838 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 319846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 319850 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 319854 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319859 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 319861 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 319861 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319864 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319868 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319873 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 319879 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319884 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 319892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 319899 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 319903 */     GIR_RootConstrainSelectedInstOperands,
     /* 319904 */     // GIR_Coverage, 4944,
     /* 319904 */     GIR_EraseRootFromParent_Done,
     /* 319905 */   // Label 6325: @319905
     /* 319905 */   GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(320002), // Rule ID 14183 //
     /* 319910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 319913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 319917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 319921 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 319925 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 319929 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 319933 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 319937 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 319941 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319946 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 319950 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319954 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319958 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 319960 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 319960 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 319963 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 319967 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 319972 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 319978 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 319983 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 319991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319995 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 319998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 320000 */     GIR_RootConstrainSelectedInstOperands,
     /* 320001 */     // GIR_Coverage, 14183,
     /* 320001 */     GIR_EraseRootFromParent_Done,
     /* 320002 */   // Label 6326: @320002
     /* 320002 */   GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(320102), // Rule ID 14185 //
     /* 320007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 320010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 320022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 320031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320035 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320039 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 320043 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320048 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 320052 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320056 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 320058 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 320058 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 320061 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 320065 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 320070 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 320076 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320081 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 320089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320091 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 320094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 320098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 320100 */     GIR_RootConstrainSelectedInstOperands,
     /* 320101 */     // GIR_Coverage, 14185,
     /* 320101 */     GIR_EraseRootFromParent_Done,
     /* 320102 */   // Label 6327: @320102
     /* 320102 */   GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(320202), // Rule ID 4942 //
     /* 320107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 320110 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320114 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320118 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320122 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320126 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320130 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320135 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 320139 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 320143 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320147 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 320151 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320156 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 320158 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 320158 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 320161 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 320165 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 320170 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 320176 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320181 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 320189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320191 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 320193 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 320196 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 320200 */     GIR_RootConstrainSelectedInstOperands,
     /* 320201 */     // GIR_Coverage, 4942,
     /* 320201 */     GIR_EraseRootFromParent_Done,
     /* 320202 */   // Label 6328: @320202
     /* 320202 */   GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(320299), // Rule ID 4906 //
     /* 320207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 320210 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320214 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320218 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320222 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 320226 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320230 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320234 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320238 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 320242 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320247 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 320251 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320255 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 320257 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 320257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 320260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 320264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 320269 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 320275 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320280 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 320288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320290 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 320292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 320295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 320297 */     GIR_RootConstrainSelectedInstOperands,
     /* 320298 */     // GIR_Coverage, 4906,
     /* 320298 */     GIR_EraseRootFromParent_Done,
     /* 320299 */   // Label 6329: @320299
     /* 320299 */   GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(320377), // Rule ID 6291 //
     /* 320304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320316 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320320 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320324 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320328 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320332 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320337 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 320341 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320345 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 320349 */     // MIs[3] Operand 1
     /* 320349 */     // No operand predicates
     /* 320349 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320353 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320357 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320359 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 320359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320368 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 320372 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 320375 */     GIR_RootConstrainSelectedInstOperands,
     /* 320376 */     // GIR_Coverage, 6291,
     /* 320376 */     GIR_EraseRootFromParent_Done,
     /* 320377 */   // Label 6330: @320377
     /* 320377 */   GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(320461), // Rule ID 6203 //
     /* 320382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320397 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320406 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 320410 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320414 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 320418 */     // MIs[2] Operand 1
     /* 320418 */     // No operand predicates
     /* 320418 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 320422 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320426 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 320430 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320435 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320439 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320441 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 320441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320446 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320448 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 320452 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 320456 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 320459 */     GIR_RootConstrainSelectedInstOperands,
     /* 320460 */     // GIR_Coverage, 6203,
     /* 320460 */     GIR_EraseRootFromParent_Done,
     /* 320461 */   // Label 6331: @320461
     /* 320461 */   GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(320542), // Rule ID 6235 //
     /* 320466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320469 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320473 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320477 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 320481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320489 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320493 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 320497 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320502 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 320506 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320510 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 320514 */     // MIs[3] Operand 1
     /* 320514 */     // No operand predicates
     /* 320514 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320518 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320522 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320524 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 320524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320529 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 320537 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 320540 */     GIR_RootConstrainSelectedInstOperands,
     /* 320541 */     // GIR_Coverage, 6235,
     /* 320541 */     GIR_EraseRootFromParent_Done,
     /* 320542 */   // Label 6332: @320542
     /* 320542 */   GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(320626), // Rule ID 6267 //
     /* 320547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320554 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320558 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 320562 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 320571 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320575 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320579 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 320583 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320588 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 320592 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320596 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 320600 */     // MIs[3] Operand 1
     /* 320600 */     // No operand predicates
     /* 320600 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320604 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320606 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 320606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320611 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 320617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 320621 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 320624 */     GIR_RootConstrainSelectedInstOperands,
     /* 320625 */     // GIR_Coverage, 6267,
     /* 320625 */     GIR_EraseRootFromParent_Done,
     /* 320626 */   // Label 6333: @320626
     /* 320626 */   GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(320704), // Rule ID 6313 //
     /* 320631 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320659 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320663 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320668 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 320672 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320676 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 320680 */     // MIs[3] Operand 1
     /* 320680 */     // No operand predicates
     /* 320680 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320684 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320686 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 320686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320693 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 320695 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 320699 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 320702 */     GIR_RootConstrainSelectedInstOperands,
     /* 320703 */     // GIR_Coverage, 6313,
     /* 320703 */     GIR_EraseRootFromParent_Done,
     /* 320704 */   // Label 6334: @320704
     /* 320704 */   GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(320785), // Rule ID 6171 //
     /* 320709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320712 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 320724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 320728 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320732 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320736 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320740 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 320744 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320749 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 320753 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320757 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 320761 */     // MIs[3] Operand 1
     /* 320761 */     // No operand predicates
     /* 320761 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320765 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 320767 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 320767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 320770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 320772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 320774 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 320776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 320780 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 320783 */     GIR_RootConstrainSelectedInstOperands,
     /* 320784 */     // GIR_Coverage, 6171,
     /* 320784 */     GIR_EraseRootFromParent_Done,
     /* 320785 */   // Label 6335: @320785
     /* 320785 */   GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(320870), // Rule ID 2473 //
     /* 320790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 320793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320805 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320809 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320814 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 320818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320822 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320826 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320828 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 320828 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 320831 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 320835 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 320840 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 320846 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320851 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 320859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320861 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 320864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 320866 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 320868 */     GIR_RootConstrainSelectedInstOperands,
     /* 320869 */     // GIR_Coverage, 2473,
     /* 320869 */     GIR_EraseRootFromParent_Done,
     /* 320870 */   // Label 6336: @320870
     /* 320870 */   GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(320955), // Rule ID 2471 //
     /* 320875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 320878 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320882 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320886 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320890 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320894 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320898 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320903 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 320907 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320911 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320913 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 320913 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 320916 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 320920 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 320925 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 320931 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 320936 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 320944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 320948 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 320951 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 320953 */     GIR_RootConstrainSelectedInstOperands,
     /* 320954 */     // GIR_Coverage, 2471,
     /* 320954 */     GIR_EraseRootFromParent_Done,
     /* 320955 */   // Label 6337: @320955
     /* 320955 */   GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(321024), // Rule ID 2556 //
     /* 320960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320963 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 320967 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 320971 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 320975 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 320979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320984 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 320988 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 320992 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 320996 */     // MIs[2] Operand 1
     /* 320996 */     // No operand predicates
     /* 320996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321000 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321004 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321006 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 321006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 321009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321011 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 321015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 321019 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 321022 */     GIR_RootConstrainSelectedInstOperands,
     /* 321023 */     // GIR_Coverage, 2556,
     /* 321023 */     GIR_EraseRootFromParent_Done,
     /* 321024 */   // Label 6338: @321024
     /* 321024 */   GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(321093), // Rule ID 6139 //
     /* 321029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 321032 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 321044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 321048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 321052 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321057 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 321061 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321065 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 321069 */     // MIs[2] Operand 1
     /* 321069 */     // No operand predicates
     /* 321069 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321073 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321075 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 321075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 321078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321082 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 321084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 321088 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 321091 */     GIR_RootConstrainSelectedInstOperands,
     /* 321092 */     // GIR_Coverage, 6139,
     /* 321092 */     GIR_EraseRootFromParent_Done,
     /* 321093 */   // Label 6339: @321093
     /* 321093 */   GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(321155), // Rule ID 4952 //
     /* 321098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321102 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321106 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321110 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321115 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321119 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 321123 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321127 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 321131 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321136 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321138 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 321141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 321147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 321149 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 321153 */     GIR_RootConstrainSelectedInstOperands,
     /* 321154 */     // GIR_Coverage, 4952,
     /* 321154 */     GIR_EraseRootFromParent_Done,
     /* 321155 */   // Label 6340: @321155
     /* 321155 */   GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(321217), // Rule ID 14193 //
     /* 321160 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321176 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321181 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 321185 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321189 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 321193 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321198 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321200 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 321203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 321209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 321211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 321215 */     GIR_RootConstrainSelectedInstOperands,
     /* 321216 */     // GIR_Coverage, 14193,
     /* 321216 */     GIR_EraseRootFromParent_Done,
     /* 321217 */   // Label 6341: @321217
     /* 321217 */   GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(321264), // Rule ID 4949 //
     /* 321222 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321226 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321230 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321234 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321239 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321243 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321247 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321249 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 321252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 321258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 321260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 321262 */     GIR_RootConstrainSelectedInstOperands,
     /* 321263 */     // GIR_Coverage, 4949,
     /* 321263 */     GIR_EraseRootFromParent_Done,
     /* 321264 */   // Label 6342: @321264
     /* 321264 */   GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(321314), // Rule ID 13606 //
     /* 321269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 321272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321280 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321284 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321297 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321299 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 321302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 321306 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 321310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 321312 */     GIR_RootConstrainSelectedInstOperands,
     /* 321313 */     // GIR_Coverage, 13606,
     /* 321313 */     GIR_EraseRootFromParent_Done,
     /* 321314 */   // Label 6343: @321314
     /* 321314 */   GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(321364), // Rule ID 652 //
     /* 321319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 321322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321338 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321343 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321347 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321349 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 321352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321354 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 321356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 321360 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 321362 */     GIR_RootConstrainSelectedInstOperands,
     /* 321363 */     // GIR_Coverage, 652,
     /* 321363 */     GIR_EraseRootFromParent_Done,
     /* 321364 */   // Label 6344: @321364
     /* 321364 */   GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(321411), // Rule ID 14190 //
     /* 321369 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321381 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321385 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321390 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321394 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321396 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 321399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321401 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 321405 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 321407 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 321409 */     GIR_RootConstrainSelectedInstOperands,
     /* 321410 */     // GIR_Coverage, 14190,
     /* 321410 */     GIR_EraseRootFromParent_Done,
     /* 321411 */   // Label 6345: @321411
     /* 321411 */   GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(321461), // Rule ID 664 //
     /* 321416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 321419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 321431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321435 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321439 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321444 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321446 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 321449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321451 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 321453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 321455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 321459 */     GIR_RootConstrainSelectedInstOperands,
     /* 321460 */     // GIR_Coverage, 664,
     /* 321460 */     GIR_EraseRootFromParent_Done,
     /* 321461 */   // Label 6346: @321461
     /* 321461 */   GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(321492), // Rule ID 646 //
     /* 321466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 321469 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321481 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 321481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 321486 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 321490 */     GIR_RootConstrainSelectedInstOperands,
     /* 321491 */     // GIR_Coverage, 646,
     /* 321491 */     GIR_Done,
     /* 321492 */   // Label 6347: @321492
     /* 321492 */   GIM_Reject,
     /* 321493 */ // Label 6313: @321493
     /* 321493 */ GIM_Reject,
     /* 321494 */ // Label 6239: @321494
     /* 321494 */ GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(323014),
     /* 321499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 321502 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 321505 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 321508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321512 */   GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(321590), // Rule ID 6271 //
     /* 321517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 321533 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321537 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321541 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321545 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321550 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 321554 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321558 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321562 */     // MIs[3] Operand 1
     /* 321562 */     // No operand predicates
     /* 321562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321566 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321570 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321572 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321577 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321579 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 321581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 321585 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 321588 */     GIR_RootConstrainSelectedInstOperands,
     /* 321589 */     // GIR_Coverage, 6271,
     /* 321589 */     GIR_EraseRootFromParent_Done,
     /* 321590 */   // Label 6349: @321590
     /* 321590 */   GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(321674), // Rule ID 6187 //
     /* 321595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 321598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321610 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 321614 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321619 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 321623 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321627 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321631 */     // MIs[2] Operand 1
     /* 321631 */     // No operand predicates
     /* 321631 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 321635 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321639 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 321643 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321652 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321654 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 321665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 321669 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 321672 */     GIR_RootConstrainSelectedInstOperands,
     /* 321673 */     // GIR_Coverage, 6187,
     /* 321673 */     GIR_EraseRootFromParent_Done,
     /* 321674 */   // Label 6350: @321674
     /* 321674 */   GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(321755), // Rule ID 6219 //
     /* 321679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 321682 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321686 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321690 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 321694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321702 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321706 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 321710 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 321719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321723 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321727 */     // MIs[3] Operand 1
     /* 321727 */     // No operand predicates
     /* 321727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321731 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321735 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321737 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321742 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 321746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 321750 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 321753 */     GIR_RootConstrainSelectedInstOperands,
     /* 321754 */     // GIR_Coverage, 6219,
     /* 321754 */     GIR_EraseRootFromParent_Done,
     /* 321755 */   // Label 6351: @321755
     /* 321755 */   GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(321839), // Rule ID 6251 //
     /* 321760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 321763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 321767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 321775 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321780 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 321784 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321788 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321792 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 321796 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321801 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 321805 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321809 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321813 */     // MIs[3] Operand 1
     /* 321813 */     // No operand predicates
     /* 321813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321817 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321819 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 321830 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 321834 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 321837 */     GIR_RootConstrainSelectedInstOperands,
     /* 321838 */     // GIR_Coverage, 6251,
     /* 321838 */     GIR_EraseRootFromParent_Done,
     /* 321839 */   // Label 6352: @321839
     /* 321839 */   GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(321917), // Rule ID 6293 //
     /* 321844 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321848 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321852 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321856 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321860 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 321864 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321868 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321872 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321876 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321881 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 321885 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321889 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321893 */     // MIs[3] Operand 1
     /* 321893 */     // No operand predicates
     /* 321893 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321897 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321899 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321906 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 321908 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 321912 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 321915 */     GIR_RootConstrainSelectedInstOperands,
     /* 321916 */     // GIR_Coverage, 6293,
     /* 321916 */     GIR_EraseRootFromParent_Done,
     /* 321917 */   // Label 6353: @321917
     /* 321917 */   GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(321998), // Rule ID 6155 //
     /* 321922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 321925 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321929 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321933 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 321937 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 321941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 321949 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321953 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 321957 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321962 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 321966 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 321970 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 321974 */     // MIs[3] Operand 1
     /* 321974 */     // No operand predicates
     /* 321974 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321978 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 321980 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 321980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 321983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 321985 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 321987 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 321989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 321993 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 321996 */     GIR_RootConstrainSelectedInstOperands,
     /* 321997 */     // GIR_Coverage, 6155,
     /* 321997 */     GIR_EraseRootFromParent_Done,
     /* 321998 */   // Label 6354: @321998
     /* 321998 */   GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(322067), // Rule ID 2540 //
     /* 322003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 322014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 322018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 322022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 322031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 322035 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 322039 */     // MIs[2] Operand 1
     /* 322039 */     // No operand predicates
     /* 322039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322047 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322049 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 322049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 322052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 322058 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322062 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 322065 */     GIR_RootConstrainSelectedInstOperands,
     /* 322066 */     // GIR_Coverage, 2540,
     /* 322066 */     GIR_EraseRootFromParent_Done,
     /* 322067 */   // Label 6355: @322067
     /* 322067 */   GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(322136), // Rule ID 6123 //
     /* 322072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 322083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 322087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 322091 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 322095 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322100 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 322104 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 322108 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 322112 */     // MIs[2] Operand 1
     /* 322112 */     // No operand predicates
     /* 322112 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322116 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322118 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 322118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 322121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322125 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 322127 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322131 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 322134 */     GIR_RootConstrainSelectedInstOperands,
     /* 322135 */     // GIR_Coverage, 6123,
     /* 322135 */     GIR_EraseRootFromParent_Done,
     /* 322136 */   // Label 6356: @322136
     /* 322136 */   GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(322229), // Rule ID 6275 //
     /* 322141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 322149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 322153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 322157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322161 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 322165 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322170 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322174 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322178 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322180 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322180 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322183 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322187 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322192 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322195 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 322199 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322202 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322207 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322217 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 322221 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322227 */     GIR_RootConstrainSelectedInstOperands,
     /* 322228 */     // GIR_Coverage, 6275,
     /* 322228 */     GIR_EraseRootFromParent_Done,
     /* 322229 */   // Label 6357: @322229
     /* 322229 */   GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(322328), // Rule ID 6189 //
     /* 322234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 322245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 322249 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322254 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 322258 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322262 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322266 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322271 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322275 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322277 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322277 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322280 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322284 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322289 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322292 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322296 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322299 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322304 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 322320 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322326 */     GIR_RootConstrainSelectedInstOperands,
     /* 322327 */     // GIR_Coverage, 6189,
     /* 322327 */     GIR_EraseRootFromParent_Done,
     /* 322328 */   // Label 6358: @322328
     /* 322328 */   GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(322424), // Rule ID 6221 //
     /* 322333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322336 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322340 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322344 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322348 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 322352 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 322356 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 322360 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322369 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322373 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322375 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322375 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322378 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322382 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322387 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322390 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 322394 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322397 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322402 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322412 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 322416 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322422 */     GIR_RootConstrainSelectedInstOperands,
     /* 322423 */     // GIR_Coverage, 6221,
     /* 322423 */     GIR_EraseRootFromParent_Done,
     /* 322424 */   // Label 6359: @322424
     /* 322424 */   GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(322523), // Rule ID 6253 //
     /* 322429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322440 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322444 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 322453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 322457 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 322461 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322466 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322470 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322472 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322472 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322475 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322479 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322484 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322487 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 322491 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322494 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322499 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322509 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322511 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 322515 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322521 */     GIR_RootConstrainSelectedInstOperands,
     /* 322522 */     // GIR_Coverage, 6253,
     /* 322522 */     GIR_EraseRootFromParent_Done,
     /* 322523 */   // Label 6360: @322523
     /* 322523 */   GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(322616), // Rule ID 6297 //
     /* 322528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 322536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 322540 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 322544 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 322548 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322552 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 322556 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322561 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322565 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322567 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322567 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322570 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322574 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322579 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322582 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 322586 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322589 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322594 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322604 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322606 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 322608 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322614 */     GIR_RootConstrainSelectedInstOperands,
     /* 322615 */     // GIR_Coverage, 6297,
     /* 322615 */     GIR_EraseRootFromParent_Done,
     /* 322616 */   // Label 6361: @322616
     /* 322616 */   GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(322712), // Rule ID 6157 //
     /* 322621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322624 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322628 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 322632 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322636 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322640 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 322644 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 322648 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 322652 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322657 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322661 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 322663 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322663 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322666 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322670 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322675 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322678 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 322682 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322685 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322690 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 322698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322702 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 322704 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322710 */     GIR_RootConstrainSelectedInstOperands,
     /* 322711 */     // GIR_Coverage, 6157,
     /* 322711 */     GIR_EraseRootFromParent_Done,
     /* 322712 */   // Label 6362: @322712
     /* 322712 */   GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(322796), // Rule ID 2542 //
     /* 322717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 322728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 322732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322741 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322745 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 322747 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322747 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322750 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322754 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322759 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322762 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322766 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322769 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322774 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 322782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322784 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 322788 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322794 */     GIR_RootConstrainSelectedInstOperands,
     /* 322795 */     // GIR_Coverage, 2542,
     /* 322795 */     GIR_EraseRootFromParent_Done,
     /* 322796 */   // Label 6363: @322796
     /* 322796 */   GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(322846), // Rule ID 13636 //
     /* 322801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 322808 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322812 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322816 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322821 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322825 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322829 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 322831 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 322831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 322834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322836 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 322840 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322844 */     GIR_RootConstrainSelectedInstOperands,
     /* 322845 */     // GIR_Coverage, 13636,
     /* 322845 */     GIR_EraseRootFromParent_Done,
     /* 322846 */   // Label 6364: @322846
     /* 322846 */   GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(322930), // Rule ID 6125 //
     /* 322851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322854 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 322862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 322866 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 322870 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322875 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322879 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 322881 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 322881 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322884 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 322888 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322893 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 322896 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322900 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 322903 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322908 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 322913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 322916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322918 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322920 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 322922 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 322928 */     GIR_RootConstrainSelectedInstOperands,
     /* 322929 */     // GIR_Coverage, 6125,
     /* 322929 */     GIR_EraseRootFromParent_Done,
     /* 322930 */   // Label 6365: @322930
     /* 322930 */   GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(322980), // Rule ID 1312 //
     /* 322935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322938 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322942 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 322946 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 322950 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322954 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322959 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322963 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 322965 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 322965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 322968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 322970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 322972 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 322974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 322978 */     GIR_RootConstrainSelectedInstOperands,
     /* 322979 */     // GIR_Coverage, 1312,
     /* 322979 */     GIR_EraseRootFromParent_Done,
     /* 322980 */   // Label 6366: @322980
     /* 322980 */   GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(323013), // Rule ID 1302 //
     /* 322985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322988 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322996 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323000 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 323000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
     /* 323003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323009 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 323011 */     GIR_RootConstrainSelectedInstOperands,
     /* 323012 */     // GIR_Coverage, 1302,
     /* 323012 */     GIR_EraseRootFromParent_Done,
     /* 323013 */   // Label 6367: @323013
     /* 323013 */   GIM_Reject,
     /* 323014 */ // Label 6348: @323014
     /* 323014 */ GIM_Reject,
     /* 323015 */ // Label 6240: @323015
     /* 323015 */ GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(324535),
     /* 323020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323023 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 323026 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 323029 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323033 */   GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(323111), // Rule ID 6283 //
     /* 323038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323042 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323046 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323050 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 323054 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323058 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323062 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323066 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323071 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 323075 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323079 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323083 */     // MIs[3] Operand 1
     /* 323083 */     // No operand predicates
     /* 323083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323087 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323091 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323093 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323102 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323106 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 323109 */     GIR_RootConstrainSelectedInstOperands,
     /* 323110 */     // GIR_Coverage, 6283,
     /* 323110 */     GIR_EraseRootFromParent_Done,
     /* 323111 */   // Label 6369: @323111
     /* 323111 */   GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(323195), // Rule ID 6195 //
     /* 323116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323131 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 323135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323140 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 323144 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323148 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323152 */     // MIs[2] Operand 1
     /* 323152 */     // No operand predicates
     /* 323152 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 323156 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323160 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323164 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323169 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323173 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323175 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 323186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 323190 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 323193 */     GIR_RootConstrainSelectedInstOperands,
     /* 323194 */     // GIR_Coverage, 6195,
     /* 323194 */     GIR_EraseRootFromParent_Done,
     /* 323195 */   // Label 6370: @323195
     /* 323195 */   GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(323276), // Rule ID 6227 //
     /* 323200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323215 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323219 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323223 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323227 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 323231 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323236 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 323240 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323244 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323248 */     // MIs[3] Operand 1
     /* 323248 */     // No operand predicates
     /* 323248 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323252 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323256 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323258 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323265 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323267 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323271 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 323274 */     GIR_RootConstrainSelectedInstOperands,
     /* 323275 */     // GIR_Coverage, 6227,
     /* 323275 */     GIR_EraseRootFromParent_Done,
     /* 323276 */   // Label 6371: @323276
     /* 323276 */   GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(323360), // Rule ID 6259 //
     /* 323281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323301 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 323305 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323309 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323313 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 323317 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323322 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 323326 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323330 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323334 */     // MIs[3] Operand 1
     /* 323334 */     // No operand predicates
     /* 323334 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323338 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323340 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 323351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323355 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 323358 */     GIR_RootConstrainSelectedInstOperands,
     /* 323359 */     // GIR_Coverage, 6259,
     /* 323359 */     GIR_EraseRootFromParent_Done,
     /* 323360 */   // Label 6372: @323360
     /* 323360 */   GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(323438), // Rule ID 6305 //
     /* 323365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323381 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 323385 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323389 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323393 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323397 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323402 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 323406 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323410 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323414 */     // MIs[3] Operand 1
     /* 323414 */     // No operand predicates
     /* 323414 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323418 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323420 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323427 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 323429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323433 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 323436 */     GIR_RootConstrainSelectedInstOperands,
     /* 323437 */     // GIR_Coverage, 6305,
     /* 323437 */     GIR_EraseRootFromParent_Done,
     /* 323438 */   // Label 6373: @323438
     /* 323438 */   GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(323519), // Rule ID 6163 //
     /* 323443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323470 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323474 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 323478 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323483 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 323487 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323491 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323495 */     // MIs[3] Operand 1
     /* 323495 */     // No operand predicates
     /* 323495 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323499 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 323501 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323508 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 323510 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323514 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 323517 */     GIR_RootConstrainSelectedInstOperands,
     /* 323518 */     // GIR_Coverage, 6163,
     /* 323518 */     GIR_EraseRootFromParent_Done,
     /* 323519 */   // Label 6374: @323519
     /* 323519 */   GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(323588), // Rule ID 2548 //
     /* 323524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 323543 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323548 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 323552 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323556 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323560 */     // MIs[2] Operand 1
     /* 323560 */     // No operand predicates
     /* 323560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323564 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323568 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323570 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 323573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 323583 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 323586 */     GIR_RootConstrainSelectedInstOperands,
     /* 323587 */     // GIR_Coverage, 2548,
     /* 323587 */     GIR_EraseRootFromParent_Done,
     /* 323588 */   // Label 6375: @323588
     /* 323588 */   GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(323657), // Rule ID 6131 //
     /* 323593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323596 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 323608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323612 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 323616 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323621 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 323625 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323629 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 323633 */     // MIs[2] Operand 1
     /* 323633 */     // No operand predicates
     /* 323633 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323637 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323639 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 323639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 323642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323644 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323646 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 323648 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 323652 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 323655 */     GIR_RootConstrainSelectedInstOperands,
     /* 323656 */     // GIR_Coverage, 6131,
     /* 323656 */     GIR_EraseRootFromParent_Done,
     /* 323657 */   // Label 6376: @323657
     /* 323657 */   GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(323750), // Rule ID 6285 //
     /* 323662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 323670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 323674 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323678 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323682 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 323686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323695 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323699 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323701 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 323701 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 323704 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 323708 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 323713 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 323716 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323720 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 323723 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323728 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323742 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 323745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 323748 */     GIR_RootConstrainSelectedInstOperands,
     /* 323749 */     // GIR_Coverage, 6285,
     /* 323749 */     GIR_EraseRootFromParent_Done,
     /* 323750 */   // Label 6377: @323750
     /* 323750 */   GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(323849), // Rule ID 6197 //
     /* 323755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 323766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 323770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 323779 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323783 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323787 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323792 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323796 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323798 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 323798 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 323801 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 323805 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 323810 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 323813 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 323817 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 323820 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323825 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323835 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323837 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 323841 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 323844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 323847 */     GIR_RootConstrainSelectedInstOperands,
     /* 323848 */     // GIR_Coverage, 6197,
     /* 323848 */     GIR_EraseRootFromParent_Done,
     /* 323849 */   // Label 6378: @323849
     /* 323849 */   GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(323945), // Rule ID 6229 //
     /* 323854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323865 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323869 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 323873 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 323877 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 323881 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323886 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323890 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323894 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323896 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 323896 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 323899 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 323903 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 323908 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 323911 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 323915 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 323918 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323923 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 323931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323933 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 323935 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 323937 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 323940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 323943 */     GIR_RootConstrainSelectedInstOperands,
     /* 323944 */     // GIR_Coverage, 6229,
     /* 323944 */     GIR_EraseRootFromParent_Done,
     /* 323945 */   // Label 6379: @323945
     /* 323945 */   GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(324044), // Rule ID 6261 //
     /* 323950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 323961 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323965 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323970 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 323974 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 323978 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 323982 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323987 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 323993 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 323993 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 323996 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 324000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 324005 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 324008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324012 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 324015 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324020 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 324028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324032 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 324036 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 324039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 324042 */     GIR_RootConstrainSelectedInstOperands,
     /* 324043 */     // GIR_Coverage, 6261,
     /* 324043 */     GIR_EraseRootFromParent_Done,
     /* 324044 */   // Label 6380: @324044
     /* 324044 */   GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(324137), // Rule ID 6307 //
     /* 324049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 324061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 324065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 324069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324073 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 324077 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324082 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324086 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 324088 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 324088 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 324091 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 324095 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 324100 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 324103 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324107 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 324110 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324115 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 324123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324127 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 324129 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 324132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 324135 */     GIR_RootConstrainSelectedInstOperands,
     /* 324136 */     // GIR_Coverage, 6307,
     /* 324136 */     GIR_EraseRootFromParent_Done,
     /* 324137 */   // Label 6381: @324137
     /* 324137 */   GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(324233), // Rule ID 6165 //
     /* 324142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324145 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 324161 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 324165 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 324169 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 324173 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324178 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324182 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 324184 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 324184 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 324187 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 324191 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 324196 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 324199 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324203 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 324206 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324211 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 324219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324223 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 324225 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 324228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 324231 */     GIR_RootConstrainSelectedInstOperands,
     /* 324232 */     // GIR_Coverage, 6165,
     /* 324232 */     GIR_EraseRootFromParent_Done,
     /* 324233 */   // Label 6382: @324233
     /* 324233 */   GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(324317), // Rule ID 2550 //
     /* 324238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324241 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324245 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 324249 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 324253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324262 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324266 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324268 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 324268 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 324271 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 324275 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 324280 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 324283 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324287 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 324290 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324295 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 324303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 324309 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 324312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 324315 */     GIR_RootConstrainSelectedInstOperands,
     /* 324316 */     // GIR_Coverage, 2550,
     /* 324316 */     GIR_EraseRootFromParent_Done,
     /* 324317 */   // Label 6383: @324317
     /* 324317 */   GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(324367), // Rule ID 13640 //
     /* 324322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 324337 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324342 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324346 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324350 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324352 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 324352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 324355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324357 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 324361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324365 */     GIR_RootConstrainSelectedInstOperands,
     /* 324366 */     // GIR_Coverage, 13640,
     /* 324366 */     GIR_EraseRootFromParent_Done,
     /* 324367 */   // Label 6384: @324367
     /* 324367 */   GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(324451), // Rule ID 6133 //
     /* 324372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324375 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324379 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324383 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 324387 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 324391 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324396 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324400 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324402 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 324402 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 324405 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 324409 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 324414 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 324417 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324421 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 324424 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324429 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 324437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324441 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 324443 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 324446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 324449 */     GIR_RootConstrainSelectedInstOperands,
     /* 324450 */     // GIR_Coverage, 6133,
     /* 324450 */     GIR_EraseRootFromParent_Done,
     /* 324451 */   // Label 6385: @324451
     /* 324451 */   GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(324501), // Rule ID 1316 //
     /* 324456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324459 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324463 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324467 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324471 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 324475 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324480 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324484 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324486 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 324486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 324489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324491 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 324495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324499 */     GIR_RootConstrainSelectedInstOperands,
     /* 324500 */     // GIR_Coverage, 1316,
     /* 324500 */     GIR_EraseRootFromParent_Done,
     /* 324501 */   // Label 6386: @324501
     /* 324501 */   GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(324534), // Rule ID 1306 //
     /* 324506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324509 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324513 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324517 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324521 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 324521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
     /* 324524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 324530 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 324532 */     GIR_RootConstrainSelectedInstOperands,
     /* 324533 */     // GIR_Coverage, 1306,
     /* 324533 */     GIR_EraseRootFromParent_Done,
     /* 324534 */   // Label 6387: @324534
     /* 324534 */   GIM_Reject,
     /* 324535 */ // Label 6368: @324535
     /* 324535 */ GIM_Reject,
     /* 324536 */ // Label 6241: @324536
     /* 324536 */ GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(325714),
     /* 324541 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324544 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324547 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324554 */   GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(324638), // Rule ID 6179 //
     /* 324559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324574 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 324578 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324583 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 324587 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324591 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324595 */     // MIs[2] Operand 1
     /* 324595 */     // No operand predicates
     /* 324595 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 324599 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324603 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324607 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324612 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324616 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324618 */     // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 324618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 324621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324623 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324625 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 324629 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324633 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 324636 */     GIR_RootConstrainSelectedInstOperands,
     /* 324637 */     // GIR_Coverage, 6179,
     /* 324637 */     GIR_EraseRootFromParent_Done,
     /* 324638 */   // Label 6389: @324638
     /* 324638 */   GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(324719), // Rule ID 6211 //
     /* 324643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324654 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324658 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 324662 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324666 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324670 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 324674 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324679 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 324683 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324687 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324691 */     // MIs[3] Operand 1
     /* 324691 */     // No operand predicates
     /* 324691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324695 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324699 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324701 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 324701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 324704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324706 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 324710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324714 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 324717 */     GIR_RootConstrainSelectedInstOperands,
     /* 324718 */     // GIR_Coverage, 6211,
     /* 324718 */     GIR_EraseRootFromParent_Done,
     /* 324719 */   // Label 6390: @324719
     /* 324719 */   GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(324803), // Rule ID 6243 //
     /* 324724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324739 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324744 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 324748 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324752 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324756 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 324760 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324765 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 324769 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324773 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324777 */     // MIs[3] Operand 1
     /* 324777 */     // No operand predicates
     /* 324777 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324781 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324783 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 324783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 324786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324788 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 324794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324798 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 324801 */     GIR_RootConstrainSelectedInstOperands,
     /* 324802 */     // GIR_Coverage, 6243,
     /* 324802 */     GIR_EraseRootFromParent_Done,
     /* 324803 */   // Label 6391: @324803
     /* 324803 */   GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(324884), // Rule ID 6147 //
     /* 324808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324811 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 324823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 324831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324835 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324839 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 324843 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324848 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 324852 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324856 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324860 */     // MIs[3] Operand 1
     /* 324860 */     // No operand predicates
     /* 324860 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324864 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324866 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 324866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 324869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324871 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324873 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 324875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324879 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 324882 */     GIR_RootConstrainSelectedInstOperands,
     /* 324883 */     // GIR_Coverage, 6147,
     /* 324883 */     GIR_EraseRootFromParent_Done,
     /* 324884 */   // Label 6392: @324884
     /* 324884 */   GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(324953), // Rule ID 2532 //
     /* 324889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324896 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324900 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324904 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 324908 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 324917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324921 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324925 */     // MIs[2] Operand 1
     /* 324925 */     // No operand predicates
     /* 324925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324929 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324933 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 324935 */     // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 324935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 324938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 324942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 324944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 324948 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 324951 */     GIR_RootConstrainSelectedInstOperands,
     /* 324952 */     // GIR_Coverage, 2532,
     /* 324952 */     GIR_EraseRootFromParent_Done,
     /* 324953 */   // Label 6393: @324953
     /* 324953 */   GIM_Try, /*On fail goto*//*Label 6394*/ GIMT_Encode4(325022), // Rule ID 6115 //
     /* 324958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 324961 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324969 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324973 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324977 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 324981 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324986 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 324990 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324994 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324998 */     // MIs[2] Operand 1
     /* 324998 */     // No operand predicates
     /* 324998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325002 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 325004 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 325004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 325007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325011 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 325013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325017 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 325020 */     GIR_RootConstrainSelectedInstOperands,
     /* 325021 */     // GIR_Coverage, 6115,
     /* 325021 */     GIR_EraseRootFromParent_Done,
     /* 325022 */   // Label 6394: @325022
     /* 325022 */   GIM_Try, /*On fail goto*//*Label 6395*/ GIMT_Encode4(325121), // Rule ID 6181 //
     /* 325027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325030 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325034 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 325038 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 325042 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325047 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 325051 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325055 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325059 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325064 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325068 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 325070 */     // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325070 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325073 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325077 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325082 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325085 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325089 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325092 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325097 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 325105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 325113 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325119 */     GIR_RootConstrainSelectedInstOperands,
     /* 325120 */     // GIR_Coverage, 6181,
     /* 325120 */     GIR_EraseRootFromParent_Done,
     /* 325121 */   // Label 6395: @325121
     /* 325121 */   GIM_Try, /*On fail goto*//*Label 6396*/ GIMT_Encode4(325217), // Rule ID 6213 //
     /* 325126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325137 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325141 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 325145 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 325149 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 325153 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325158 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325162 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325166 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 325168 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325168 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325171 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325175 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325180 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325183 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325187 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325190 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325195 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 325203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325209 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325212 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325215 */     GIR_RootConstrainSelectedInstOperands,
     /* 325216 */     // GIR_Coverage, 6213,
     /* 325216 */     GIR_EraseRootFromParent_Done,
     /* 325217 */   // Label 6396: @325217
     /* 325217 */   GIM_Try, /*On fail goto*//*Label 6397*/ GIMT_Encode4(325316), // Rule ID 6245 //
     /* 325222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325225 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325229 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325233 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 325246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 325250 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 325254 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325259 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325263 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 325265 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325265 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325268 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325272 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325277 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325280 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325284 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325287 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325292 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 325300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325302 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 325308 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325314 */     GIR_RootConstrainSelectedInstOperands,
     /* 325315 */     // GIR_Coverage, 6245,
     /* 325315 */     GIR_EraseRootFromParent_Done,
     /* 325316 */   // Label 6397: @325316
     /* 325316 */   GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(325412), // Rule ID 6149 //
     /* 325321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325324 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325328 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 325332 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325336 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325340 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 325344 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 325348 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 325352 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325357 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325361 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 325363 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325363 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325366 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325370 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325375 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325378 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325382 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325385 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325390 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 325398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325400 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325402 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 325404 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325410 */     GIR_RootConstrainSelectedInstOperands,
     /* 325411 */     // GIR_Coverage, 6149,
     /* 325411 */     GIR_EraseRootFromParent_Done,
     /* 325412 */   // Label 6398: @325412
     /* 325412 */   GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(325496), // Rule ID 2534 //
     /* 325417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325424 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 325428 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 325432 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325437 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325441 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325445 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325447 */     // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325447 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325450 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325454 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325459 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325462 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325466 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325469 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325474 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 325482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325488 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325494 */     GIR_RootConstrainSelectedInstOperands,
     /* 325495 */     // GIR_Coverage, 2534,
     /* 325495 */     GIR_EraseRootFromParent_Done,
     /* 325496 */   // Label 6399: @325496
     /* 325496 */   GIM_Try, /*On fail goto*//*Label 6400*/ GIMT_Encode4(325546), // Rule ID 13632 //
     /* 325501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325516 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325521 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325525 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325529 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325531 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 325531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 325534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325538 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325540 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325544 */     GIR_RootConstrainSelectedInstOperands,
     /* 325545 */     // GIR_Coverage, 13632,
     /* 325545 */     GIR_EraseRootFromParent_Done,
     /* 325546 */   // Label 6400: @325546
     /* 325546 */   GIM_Try, /*On fail goto*//*Label 6401*/ GIMT_Encode4(325630), // Rule ID 6117 //
     /* 325551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325554 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 325562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 325566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 325570 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325575 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325579 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325581 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 325581 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 325584 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 325588 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 325593 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 325596 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325600 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 325603 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325608 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 325613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 325616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325620 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 325622 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 325625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 325628 */     GIR_RootConstrainSelectedInstOperands,
     /* 325629 */     // GIR_Coverage, 6117,
     /* 325629 */     GIR_EraseRootFromParent_Done,
     /* 325630 */   // Label 6401: @325630
     /* 325630 */   GIM_Try, /*On fail goto*//*Label 6402*/ GIMT_Encode4(325680), // Rule ID 1308 //
     /* 325635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325638 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325642 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 325646 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325650 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325654 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325659 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325663 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325665 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 325665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 325668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325670 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325672 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 325674 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325678 */     GIR_RootConstrainSelectedInstOperands,
     /* 325679 */     // GIR_Coverage, 1308,
     /* 325679 */     GIR_EraseRootFromParent_Done,
     /* 325680 */   // Label 6402: @325680
     /* 325680 */   GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(325713), // Rule ID 1298 //
     /* 325685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 325688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325696 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325700 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 325700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
     /* 325703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325709 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 325711 */     GIR_RootConstrainSelectedInstOperands,
     /* 325712 */     // GIR_Coverage, 1298,
     /* 325712 */     GIR_EraseRootFromParent_Done,
     /* 325713 */   // Label 6403: @325713
     /* 325713 */   GIM_Reject,
     /* 325714 */ // Label 6388: @325714
     /* 325714 */ GIM_Reject,
     /* 325715 */ // Label 6242: @325715
     /* 325715 */ GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(327235),
     /* 325720 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325723 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 325726 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 325729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325733 */   GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(325811), // Rule ID 6277 //
     /* 325738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 325746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325750 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 325754 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 325758 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325762 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325766 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325771 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 325775 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 325779 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 325783 */     // MIs[3] Operand 1
     /* 325783 */     // No operand predicates
     /* 325783 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325787 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325791 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 325793 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 325793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 325796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325798 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325806 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 325809 */     GIR_RootConstrainSelectedInstOperands,
     /* 325810 */     // GIR_Coverage, 6277,
     /* 325810 */     GIR_EraseRootFromParent_Done,
     /* 325811 */   // Label 6405: @325811
     /* 325811 */   GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(325895), // Rule ID 6191 //
     /* 325816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 325827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 325835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 325844 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 325848 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 325852 */     // MIs[2] Operand 1
     /* 325852 */     // No operand predicates
     /* 325852 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 325856 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325860 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325864 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325869 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325873 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 325875 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 325875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 325878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325880 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 325886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 325890 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 325893 */     GIR_RootConstrainSelectedInstOperands,
     /* 325894 */     // GIR_Coverage, 6191,
     /* 325894 */     GIR_EraseRootFromParent_Done,
     /* 325895 */   // Label 6406: @325895
     /* 325895 */   GIM_Try, /*On fail goto*//*Label 6407*/ GIMT_Encode4(325976), // Rule ID 6223 //
     /* 325900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325911 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325915 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 325919 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 325923 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325927 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 325931 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325936 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 325940 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 325944 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 325948 */     // MIs[3] Operand 1
     /* 325948 */     // No operand predicates
     /* 325948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325952 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325956 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 325958 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 325958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 325961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 325965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 325967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325971 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 325974 */     GIR_RootConstrainSelectedInstOperands,
     /* 325975 */     // GIR_Coverage, 6223,
     /* 325975 */     GIR_EraseRootFromParent_Done,
     /* 325976 */   // Label 6407: @325976
     /* 325976 */   GIM_Try, /*On fail goto*//*Label 6408*/ GIMT_Encode4(326060), // Rule ID 6255 //
     /* 325981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 325992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325996 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 326005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326009 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326013 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 326017 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326022 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 326026 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326030 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326034 */     // MIs[3] Operand 1
     /* 326034 */     // No operand predicates
     /* 326034 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326038 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 326040 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 326040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326047 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 326051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326055 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 326058 */     GIR_RootConstrainSelectedInstOperands,
     /* 326059 */     // GIR_Coverage, 6255,
     /* 326059 */     GIR_EraseRootFromParent_Done,
     /* 326060 */   // Label 6408: @326060
     /* 326060 */   GIM_Try, /*On fail goto*//*Label 6409*/ GIMT_Encode4(326138), // Rule ID 6299 //
     /* 326065 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326069 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326073 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326077 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326081 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 326085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326093 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326097 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326102 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 326106 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326110 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326114 */     // MIs[3] Operand 1
     /* 326114 */     // No operand predicates
     /* 326114 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326118 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 326120 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 326120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326127 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 326129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326133 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 326136 */     GIR_RootConstrainSelectedInstOperands,
     /* 326137 */     // GIR_Coverage, 6299,
     /* 326137 */     GIR_EraseRootFromParent_Done,
     /* 326138 */   // Label 6409: @326138
     /* 326138 */   GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(326219), // Rule ID 6159 //
     /* 326143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326146 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326158 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326162 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326166 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326170 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326174 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 326178 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326183 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 326187 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326191 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326195 */     // MIs[3] Operand 1
     /* 326195 */     // No operand predicates
     /* 326195 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326199 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 326201 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 326201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326206 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326208 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 326210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326214 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 326217 */     GIR_RootConstrainSelectedInstOperands,
     /* 326218 */     // GIR_Coverage, 6159,
     /* 326218 */     GIR_EraseRootFromParent_Done,
     /* 326219 */   // Label 6410: @326219
     /* 326219 */   GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(326288), // Rule ID 2544 //
     /* 326224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326235 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326239 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 326243 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326248 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 326252 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326256 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326260 */     // MIs[2] Operand 1
     /* 326260 */     // No operand predicates
     /* 326260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326264 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326268 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326270 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 326270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 326273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326275 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 326279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 326283 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 326286 */     GIR_RootConstrainSelectedInstOperands,
     /* 326287 */     // GIR_Coverage, 2544,
     /* 326287 */     GIR_EraseRootFromParent_Done,
     /* 326288 */   // Label 6411: @326288
     /* 326288 */   GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(326357), // Rule ID 6127 //
     /* 326293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326296 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326308 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326312 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 326316 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326321 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 326325 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326329 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326333 */     // MIs[2] Operand 1
     /* 326333 */     // No operand predicates
     /* 326333 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326337 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326339 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 326339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 326342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326346 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 326348 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 326352 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 326355 */     GIR_RootConstrainSelectedInstOperands,
     /* 326356 */     // GIR_Coverage, 6127,
     /* 326356 */     GIR_EraseRootFromParent_Done,
     /* 326357 */   // Label 6412: @326357
     /* 326357 */   GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(326450), // Rule ID 6281 //
     /* 326362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 326370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 326374 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326378 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326382 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 326386 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326391 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326395 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326401 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326401 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326404 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326408 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326413 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326416 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326420 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326423 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326438 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 326442 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326448 */     GIR_RootConstrainSelectedInstOperands,
     /* 326449 */     // GIR_Coverage, 6281,
     /* 326449 */     GIR_EraseRootFromParent_Done,
     /* 326450 */   // Label 6413: @326450
     /* 326450 */   GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(326549), // Rule ID 6193 //
     /* 326455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326458 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326462 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 326466 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 326470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 326479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326483 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326487 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326492 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326496 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326498 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326498 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326501 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326505 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326510 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326513 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 326517 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326520 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326525 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 326541 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326547 */     GIR_RootConstrainSelectedInstOperands,
     /* 326548 */     // GIR_Coverage, 6193,
     /* 326548 */     GIR_EraseRootFromParent_Done,
     /* 326549 */   // Label 6414: @326549
     /* 326549 */   GIM_Try, /*On fail goto*//*Label 6415*/ GIMT_Encode4(326645), // Rule ID 6225 //
     /* 326554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326557 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326561 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326565 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326569 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326573 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 326577 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 326581 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326586 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326590 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326594 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326596 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326596 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326599 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326603 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326608 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326611 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326615 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326618 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326633 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 326637 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326643 */     GIR_RootConstrainSelectedInstOperands,
     /* 326644 */     // GIR_Coverage, 6225,
     /* 326644 */     GIR_EraseRootFromParent_Done,
     /* 326645 */   // Label 6415: @326645
     /* 326645 */   GIM_Try, /*On fail goto*//*Label 6416*/ GIMT_Encode4(326744), // Rule ID 6257 //
     /* 326650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326653 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326657 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326661 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326665 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 326674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 326678 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 326682 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326687 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326691 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326693 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326693 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326696 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326700 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326705 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326708 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326712 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326715 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326720 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 326736 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326742 */     GIR_RootConstrainSelectedInstOperands,
     /* 326743 */     // GIR_Coverage, 6257,
     /* 326743 */     GIR_EraseRootFromParent_Done,
     /* 326744 */   // Label 6416: @326744
     /* 326744 */   GIM_Try, /*On fail goto*//*Label 6417*/ GIMT_Encode4(326837), // Rule ID 6303 //
     /* 326749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326753 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326757 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 326761 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 326765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326773 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 326777 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326782 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326786 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326788 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326788 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326791 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326795 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326800 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326803 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326807 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326810 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326815 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326825 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326827 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 326829 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326835 */     GIR_RootConstrainSelectedInstOperands,
     /* 326836 */     // GIR_Coverage, 6303,
     /* 326836 */     GIR_EraseRootFromParent_Done,
     /* 326837 */   // Label 6417: @326837
     /* 326837 */   GIM_Try, /*On fail goto*//*Label 6418*/ GIMT_Encode4(326933), // Rule ID 6161 //
     /* 326842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 326857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 326865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 326869 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 326873 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326878 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326882 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 326884 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326884 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326887 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326891 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326896 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326899 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326903 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326906 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326911 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 326919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326921 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 326923 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 326925 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 326928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 326931 */     GIR_RootConstrainSelectedInstOperands,
     /* 326932 */     // GIR_Coverage, 6161,
     /* 326932 */     GIR_EraseRootFromParent_Done,
     /* 326933 */   // Label 6418: @326933
     /* 326933 */   GIM_Try, /*On fail goto*//*Label 6419*/ GIMT_Encode4(327017), // Rule ID 2546 //
     /* 326938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326941 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 326945 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 326949 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 326953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 326958 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326962 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326966 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 326968 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 326968 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 326971 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 326975 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 326980 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 326983 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 326987 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 326990 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326995 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 327000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 327003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327009 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 327015 */     GIR_RootConstrainSelectedInstOperands,
     /* 327016 */     // GIR_Coverage, 2546,
     /* 327016 */     GIR_EraseRootFromParent_Done,
     /* 327017 */   // Label 6419: @327017
     /* 327017 */   GIM_Try, /*On fail goto*//*Label 6420*/ GIMT_Encode4(327067), // Rule ID 13638 //
     /* 327022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327025 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327029 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327033 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 327037 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327046 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327050 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 327052 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 327052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 327055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327057 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327065 */     GIR_RootConstrainSelectedInstOperands,
     /* 327066 */     // GIR_Coverage, 13638,
     /* 327066 */     GIR_EraseRootFromParent_Done,
     /* 327067 */   // Label 6420: @327067
     /* 327067 */   GIM_Try, /*On fail goto*//*Label 6421*/ GIMT_Encode4(327151), // Rule ID 6129 //
     /* 327072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 327087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 327091 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 327096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327100 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 327102 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 327102 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 327105 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 327109 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327114 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 327117 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327121 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 327124 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327129 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 327134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 327137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327141 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 327143 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 327149 */     GIR_RootConstrainSelectedInstOperands,
     /* 327150 */     // GIR_Coverage, 6129,
     /* 327150 */     GIR_EraseRootFromParent_Done,
     /* 327151 */   // Label 6421: @327151
     /* 327151 */   GIM_Try, /*On fail goto*//*Label 6422*/ GIMT_Encode4(327201), // Rule ID 1314 //
     /* 327156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 327175 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327180 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327184 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 327186 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 327186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 327189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327191 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327193 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 327195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327199 */     GIR_RootConstrainSelectedInstOperands,
     /* 327200 */     // GIR_Coverage, 1314,
     /* 327200 */     GIR_EraseRootFromParent_Done,
     /* 327201 */   // Label 6422: @327201
     /* 327201 */   GIM_Try, /*On fail goto*//*Label 6423*/ GIMT_Encode4(327234), // Rule ID 1304 //
     /* 327206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327213 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327217 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327221 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 327221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
     /* 327224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327226 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327230 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 327232 */     GIR_RootConstrainSelectedInstOperands,
     /* 327233 */     // GIR_Coverage, 1304,
     /* 327233 */     GIR_EraseRootFromParent_Done,
     /* 327234 */   // Label 6423: @327234
     /* 327234 */   GIM_Reject,
     /* 327235 */ // Label 6404: @327235
     /* 327235 */ GIM_Reject,
     /* 327236 */ // Label 6243: @327236
     /* 327236 */ GIM_Try, /*On fail goto*//*Label 6424*/ GIMT_Encode4(328414),
     /* 327241 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327244 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 327247 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 327250 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327254 */   GIM_Try, /*On fail goto*//*Label 6425*/ GIMT_Encode4(327338), // Rule ID 6175 //
     /* 327259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327274 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327283 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 327287 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327291 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327295 */     // MIs[2] Operand 1
     /* 327295 */     // No operand predicates
     /* 327295 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 327299 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327303 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327307 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327312 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327316 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 327318 */     // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327323 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 327329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327333 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 327336 */     GIR_RootConstrainSelectedInstOperands,
     /* 327337 */     // GIR_Coverage, 6175,
     /* 327337 */     GIR_EraseRootFromParent_Done,
     /* 327338 */   // Label 6425: @327338
     /* 327338 */   GIM_Try, /*On fail goto*//*Label 6426*/ GIMT_Encode4(327419), // Rule ID 6207 //
     /* 327343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327346 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327350 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327354 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327358 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 327362 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327366 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327370 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327374 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327379 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 327383 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327387 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327391 */     // MIs[3] Operand 1
     /* 327391 */     // No operand predicates
     /* 327391 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327395 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327399 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 327401 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327414 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 327417 */     GIR_RootConstrainSelectedInstOperands,
     /* 327418 */     // GIR_Coverage, 6207,
     /* 327418 */     GIR_EraseRootFromParent_Done,
     /* 327419 */   // Label 6426: @327419
     /* 327419 */   GIM_Try, /*On fail goto*//*Label 6427*/ GIMT_Encode4(327503), // Rule ID 6239 //
     /* 327424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327435 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327439 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327444 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327448 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327452 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327456 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327460 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327465 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 327469 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327473 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327477 */     // MIs[3] Operand 1
     /* 327477 */     // No operand predicates
     /* 327477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327481 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 327483 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 327494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327498 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 327501 */     GIR_RootConstrainSelectedInstOperands,
     /* 327502 */     // GIR_Coverage, 6239,
     /* 327502 */     GIR_EraseRootFromParent_Done,
     /* 327503 */   // Label 6427: @327503
     /* 327503 */   GIM_Try, /*On fail goto*//*Label 6428*/ GIMT_Encode4(327584), // Rule ID 6143 //
     /* 327508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327511 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327519 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327523 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327527 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 327531 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327535 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327539 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327543 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327548 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 327552 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327556 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327560 */     // MIs[3] Operand 1
     /* 327560 */     // No operand predicates
     /* 327560 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327564 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 327566 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327573 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 327575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 327582 */     GIR_RootConstrainSelectedInstOperands,
     /* 327583 */     // GIR_Coverage, 6143,
     /* 327583 */     GIR_EraseRootFromParent_Done,
     /* 327584 */   // Label 6428: @327584
     /* 327584 */   GIM_Try, /*On fail goto*//*Label 6429*/ GIMT_Encode4(327653), // Rule ID 2528 //
     /* 327589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327604 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327613 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 327617 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327621 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327625 */     // MIs[2] Operand 1
     /* 327625 */     // No operand predicates
     /* 327625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327629 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327633 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327635 */     // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 327638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327642 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327648 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 327651 */     GIR_RootConstrainSelectedInstOperands,
     /* 327652 */     // GIR_Coverage, 2528,
     /* 327652 */     GIR_EraseRootFromParent_Done,
     /* 327653 */   // Label 6429: @327653
     /* 327653 */   GIM_Try, /*On fail goto*//*Label 6430*/ GIMT_Encode4(327722), // Rule ID 6111 //
     /* 327658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327661 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327677 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327681 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327686 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 327690 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327694 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327698 */     // MIs[2] Operand 1
     /* 327698 */     // No operand predicates
     /* 327698 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327702 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327704 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 327704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 327707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327709 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327711 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 327713 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327717 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 327720 */     GIR_RootConstrainSelectedInstOperands,
     /* 327721 */     // GIR_Coverage, 6111,
     /* 327721 */     GIR_EraseRootFromParent_Done,
     /* 327722 */   // Label 6430: @327722
     /* 327722 */   GIM_Try, /*On fail goto*//*Label 6431*/ GIMT_Encode4(327821), // Rule ID 6177 //
     /* 327727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 327738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 327742 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327755 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327759 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327764 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327768 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327770 */     // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 327770 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 327773 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 327777 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327782 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 327785 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 327789 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 327792 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327797 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327809 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 327813 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 327819 */     GIR_RootConstrainSelectedInstOperands,
     /* 327820 */     // GIR_Coverage, 6177,
     /* 327820 */     GIR_EraseRootFromParent_Done,
     /* 327821 */   // Label 6431: @327821
     /* 327821 */   GIM_Try, /*On fail goto*//*Label 6432*/ GIMT_Encode4(327917), // Rule ID 6209 //
     /* 327826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327841 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 327845 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 327849 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 327853 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327862 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327866 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327868 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 327868 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 327871 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 327875 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327880 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 327883 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327887 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 327890 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327895 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 327903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 327907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 327909 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327912 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 327915 */     GIR_RootConstrainSelectedInstOperands,
     /* 327916 */     // GIR_Coverage, 6209,
     /* 327916 */     GIR_EraseRootFromParent_Done,
     /* 327917 */   // Label 6432: @327917
     /* 327917 */   GIM_Try, /*On fail goto*//*Label 6433*/ GIMT_Encode4(328016), // Rule ID 6241 //
     /* 327922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 327925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327929 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 327933 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327937 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327942 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327946 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 327950 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 327954 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327959 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327963 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327965 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 327965 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 327968 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 327972 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327977 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 327980 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327984 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 327987 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327992 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 327997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 328000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328002 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328004 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328008 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 328011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 328014 */     GIR_RootConstrainSelectedInstOperands,
     /* 328015 */     // GIR_Coverage, 6241,
     /* 328015 */     GIR_EraseRootFromParent_Done,
     /* 328016 */   // Label 6433: @328016
     /* 328016 */   GIM_Try, /*On fail goto*//*Label 6434*/ GIMT_Encode4(328112), // Rule ID 6145 //
     /* 328021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328024 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 328032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 328036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 328044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 328048 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 328052 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328057 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328061 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328063 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 328063 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 328066 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 328070 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328075 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 328078 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 328082 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 328085 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328090 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 328098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328102 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 328104 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 328107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 328110 */     GIR_RootConstrainSelectedInstOperands,
     /* 328111 */     // GIR_Coverage, 6145,
     /* 328111 */     GIR_EraseRootFromParent_Done,
     /* 328112 */   // Label 6434: @328112
     /* 328112 */   GIM_Try, /*On fail goto*//*Label 6435*/ GIMT_Encode4(328196), // Rule ID 2530 //
     /* 328117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328120 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328124 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 328128 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 328132 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328141 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328145 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 328147 */     // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 328147 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 328150 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 328154 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328159 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 328162 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 328166 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 328169 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328174 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 328182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 328188 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 328191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 328194 */     GIR_RootConstrainSelectedInstOperands,
     /* 328195 */     // GIR_Coverage, 2530,
     /* 328195 */     GIR_EraseRootFromParent_Done,
     /* 328196 */   // Label 6435: @328196
     /* 328196 */   GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(328246), // Rule ID 13634 //
     /* 328201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 328212 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328216 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328221 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328225 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328229 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 328231 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 328231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 328234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 328240 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 328244 */     GIR_RootConstrainSelectedInstOperands,
     /* 328245 */     // GIR_Coverage, 13634,
     /* 328245 */     GIR_EraseRootFromParent_Done,
     /* 328246 */   // Label 6436: @328246
     /* 328246 */   GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(328330), // Rule ID 6113 //
     /* 328251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328254 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 328262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 328266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 328270 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328275 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328279 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 328281 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 328281 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 328284 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 328288 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328293 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 328296 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 328300 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 328303 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328308 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 328313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 328316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328318 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 328322 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 328325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 328328 */     GIR_RootConstrainSelectedInstOperands,
     /* 328329 */     // GIR_Coverage, 6113,
     /* 328329 */     GIR_EraseRootFromParent_Done,
     /* 328330 */   // Label 6437: @328330
     /* 328330 */   GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(328380), // Rule ID 1310 //
     /* 328335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328338 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 328346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 328350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328354 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328359 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328363 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 328365 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 328365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 328368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328370 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328372 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 328374 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 328378 */     GIR_RootConstrainSelectedInstOperands,
     /* 328379 */     // GIR_Coverage, 1310,
     /* 328379 */     GIR_EraseRootFromParent_Done,
     /* 328380 */   // Label 6438: @328380
     /* 328380 */   GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(328413), // Rule ID 1300 //
     /* 328385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328388 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328396 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328400 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 328400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
     /* 328403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 328405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 328407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 328409 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 328411 */     GIR_RootConstrainSelectedInstOperands,
     /* 328412 */     // GIR_Coverage, 1300,
     /* 328412 */     GIR_EraseRootFromParent_Done,
     /* 328413 */   // Label 6439: @328413
     /* 328413 */   GIM_Reject,
     /* 328414 */ // Label 6424: @328414
     /* 328414 */ GIM_Reject,
     /* 328415 */ // Label 6244: @328415
     /* 328415 */ GIM_Reject,
     /* 328416 */ // Label 63: @328416
     /* 328416 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6448*/ GIMT_Encode4(329031),
     /* 328427 */ /*GILLT_s16*//*Label 6440*/ GIMT_Encode4(328467),
     /* 328431 */ /*GILLT_s32*//*Label 6441*/ GIMT_Encode4(328505),
     /* 328435 */ /*GILLT_s64*//*Label 6442*/ GIMT_Encode4(328543), GIMT_Encode4(0),
     /* 328443 */ /*GILLT_v2s32*//*Label 6443*/ GIMT_Encode4(328581),
     /* 328447 */ /*GILLT_v2s64*//*Label 6444*/ GIMT_Encode4(328619),
     /* 328451 */ /*GILLT_v4s16*//*Label 6445*/ GIMT_Encode4(328657),
     /* 328455 */ /*GILLT_v4s32*//*Label 6446*/ GIMT_Encode4(328695), GIMT_Encode4(0),
     /* 328463 */ /*GILLT_v8s16*//*Label 6447*/ GIMT_Encode4(328733),
     /* 328467 */ // Label 6440: @328467
     /* 328467 */ GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(328504), // Rule ID 594 //
     /* 328472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 328475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 328478 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 328481 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 328485 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 328489 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 328493 */   // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 328493 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
     /* 328498 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328502 */   GIR_RootConstrainSelectedInstOperands,
     /* 328503 */   // GIR_Coverage, 594,
     /* 328503 */   GIR_Done,
     /* 328504 */ // Label 6449: @328504
     /* 328504 */ GIM_Reject,
     /* 328505 */ // Label 6441: @328505
     /* 328505 */ GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(328542), // Rule ID 596 //
     /* 328510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 328513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 328516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 328519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 328523 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 328527 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 328531 */   // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 328531 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
     /* 328536 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328540 */   GIR_RootConstrainSelectedInstOperands,
     /* 328541 */   // GIR_Coverage, 596,
     /* 328541 */   GIR_Done,
     /* 328542 */ // Label 6450: @328542
     /* 328542 */ GIM_Reject,
     /* 328543 */ // Label 6442: @328543
     /* 328543 */ GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(328580), // Rule ID 598 //
     /* 328548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 328551 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 328554 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 328557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328565 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328569 */   // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 328569 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
     /* 328574 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328578 */   GIR_RootConstrainSelectedInstOperands,
     /* 328579 */   // GIR_Coverage, 598,
     /* 328579 */   GIR_Done,
     /* 328580 */ // Label 6451: @328580
     /* 328580 */ GIM_Reject,
     /* 328581 */ // Label 6443: @328581
     /* 328581 */ GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(328618), // Rule ID 1232 //
     /* 328586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328589 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 328592 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 328595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328599 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328603 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328607 */   // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 328607 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
     /* 328612 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328616 */   GIR_RootConstrainSelectedInstOperands,
     /* 328617 */   // GIR_Coverage, 1232,
     /* 328617 */   GIR_Done,
     /* 328618 */ // Label 6452: @328618
     /* 328618 */ GIM_Reject,
     /* 328619 */ // Label 6444: @328619
     /* 328619 */ GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(328656), // Rule ID 1236 //
     /* 328624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328630 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 328633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328637 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328641 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328645 */   // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 328645 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
     /* 328650 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328654 */   GIR_RootConstrainSelectedInstOperands,
     /* 328655 */   // GIR_Coverage, 1236,
     /* 328655 */   GIR_Done,
     /* 328656 */ // Label 6453: @328656
     /* 328656 */ GIM_Reject,
     /* 328657 */ // Label 6445: @328657
     /* 328657 */ GIM_Try, /*On fail goto*//*Label 6454*/ GIMT_Encode4(328694), // Rule ID 1228 //
     /* 328662 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328665 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 328668 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 328671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328675 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328679 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328683 */   // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 328683 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
     /* 328688 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328692 */   GIR_RootConstrainSelectedInstOperands,
     /* 328693 */   // GIR_Coverage, 1228,
     /* 328693 */   GIR_Done,
     /* 328694 */ // Label 6454: @328694
     /* 328694 */ GIM_Reject,
     /* 328695 */ // Label 6446: @328695
     /* 328695 */ GIM_Try, /*On fail goto*//*Label 6455*/ GIMT_Encode4(328732), // Rule ID 1234 //
     /* 328700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328703 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 328706 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 328709 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328713 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328717 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328721 */   // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 328721 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 328726 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328730 */   GIR_RootConstrainSelectedInstOperands,
     /* 328731 */   // GIR_Coverage, 1234,
     /* 328731 */   GIR_Done,
     /* 328732 */ // Label 6455: @328732
     /* 328732 */ GIM_Reject,
     /* 328733 */ // Label 6447: @328733
     /* 328733 */ GIM_Try, /*On fail goto*//*Label 6456*/ GIMT_Encode4(329030),
     /* 328738 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328741 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 328744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328748 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328752 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328756 */   GIM_Try, /*On fail goto*//*Label 6457*/ GIMT_Encode4(328775), // Rule ID 1230 //
     /* 328761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328764 */     // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 328764 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
     /* 328769 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328773 */     GIR_RootConstrainSelectedInstOperands,
     /* 328774 */     // GIR_Coverage, 1230,
     /* 328774 */     GIR_Done,
     /* 328775 */   // Label 6457: @328775
     /* 328775 */   GIM_Try, /*On fail goto*//*Label 6458*/ GIMT_Encode4(329029), // Rule ID 7092 //
     /* 328780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 328783 */     // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 328783 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 328786 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 328790 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328795 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 328799 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 328801 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 328804 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 328808 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328813 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 328817 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 328819 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 328822 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 328826 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328831 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 328834 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 328837 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 328839 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 328842 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 328846 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328851 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 328857 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328862 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328867 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 328870 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 328874 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328879 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 328882 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 328884 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 328887 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 328891 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328896 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 328902 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328907 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328912 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 328915 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 328919 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328924 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 328927 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 328929 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 328932 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 328936 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328941 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 328944 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 328947 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 328949 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 328952 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 328956 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328961 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 328964 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 328966 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 328969 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 328973 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328978 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 328980 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 328983 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 328987 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328992 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 328995 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 328998 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 329001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329006 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329011 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 329019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 329021 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329024 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 329027 */     GIR_RootConstrainSelectedInstOperands,
     /* 329028 */     // GIR_Coverage, 7092,
     /* 329028 */     GIR_EraseRootFromParent_Done,
     /* 329029 */   // Label 6458: @329029
     /* 329029 */   GIM_Reject,
     /* 329030 */ // Label 6456: @329030
     /* 329030 */ GIM_Reject,
     /* 329031 */ // Label 6448: @329031
     /* 329031 */ GIM_Reject,
     /* 329032 */ // Label 64: @329032
     /* 329032 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6467*/ GIMT_Encode4(332538),
     /* 329043 */ /*GILLT_s16*//*Label 6459*/ GIMT_Encode4(329083),
     /* 329047 */ /*GILLT_s32*//*Label 6460*/ GIMT_Encode4(330251),
     /* 329051 */ /*GILLT_s64*//*Label 6461*/ GIMT_Encode4(331274), GIMT_Encode4(0),
     /* 329059 */ /*GILLT_v2s32*//*Label 6462*/ GIMT_Encode4(332297),
     /* 329063 */ /*GILLT_v2s64*//*Label 6463*/ GIMT_Encode4(332324),
     /* 329067 */ /*GILLT_v4s16*//*Label 6464*/ GIMT_Encode4(332351),
     /* 329071 */ /*GILLT_v4s32*//*Label 6465*/ GIMT_Encode4(332431), GIMT_Encode4(0),
     /* 329079 */ /*GILLT_v8s16*//*Label 6466*/ GIMT_Encode4(332458),
     /* 329083 */ // Label 6459: @329083
     /* 329083 */ GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(330250),
     /* 329088 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 329091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329095 */   GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(329253), // Rule ID 4916 //
     /* 329100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329103 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329107 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 329111 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329115 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329119 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 329127 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329131 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329135 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329139 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329144 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329148 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 329152 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329156 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329160 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 329164 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329169 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 329173 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329178 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 329180 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 329180 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 329183 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329187 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329192 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 329198 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329203 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329208 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329211 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329215 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329220 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 329226 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329241 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329244 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 329247 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329251 */     GIR_RootConstrainSelectedInstOperands,
     /* 329252 */     // GIR_Coverage, 4916,
     /* 329252 */     GIR_EraseRootFromParent_Done,
     /* 329253 */   // Label 6469: @329253
     /* 329253 */   GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(329411), // Rule ID 4915 //
     /* 329258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329261 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329265 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 329269 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329273 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329277 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329281 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 329285 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329289 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329293 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329297 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329302 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329306 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 329310 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329314 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329318 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 329322 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329327 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 329331 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329336 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 329338 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 329338 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 329341 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329345 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329350 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 329356 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329361 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329366 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329369 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329373 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329378 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 329384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329389 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329399 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329402 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 329405 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329409 */     GIR_RootConstrainSelectedInstOperands,
     /* 329410 */     // GIR_Coverage, 4915,
     /* 329410 */     GIR_EraseRootFromParent_Done,
     /* 329411 */   // Label 6470: @329411
     /* 329411 */   GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(329522), // Rule ID 4914 //
     /* 329416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329419 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329423 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 329427 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329431 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329435 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329439 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 329443 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329447 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329451 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329455 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329460 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329464 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329469 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329474 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 329476 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 329476 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329479 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329483 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329488 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 329494 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329499 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329509 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 329516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329520 */     GIR_RootConstrainSelectedInstOperands,
     /* 329521 */     // GIR_Coverage, 4914,
     /* 329521 */     GIR_EraseRootFromParent_Done,
     /* 329522 */   // Label 6471: @329522
     /* 329522 */   GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(329633), // Rule ID 4912 //
     /* 329527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 329538 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329546 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329550 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329555 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 329559 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329563 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329567 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329571 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329576 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329580 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 329587 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 329587 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329590 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329594 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329599 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 329605 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329610 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 329624 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329631 */     GIR_RootConstrainSelectedInstOperands,
     /* 329632 */     // GIR_Coverage, 4912,
     /* 329632 */     GIR_EraseRootFromParent_Done,
     /* 329633 */   // Label 6472: @329633
     /* 329633 */   GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(329744), // Rule ID 4913 //
     /* 329638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 329649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329653 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329657 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329661 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 329665 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329669 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329673 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329677 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329682 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329686 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329691 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329696 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 329698 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 329698 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329701 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329705 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329710 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 329716 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329721 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329731 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 329738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329742 */     GIR_RootConstrainSelectedInstOperands,
     /* 329743 */     // GIR_Coverage, 4913,
     /* 329743 */     GIR_EraseRootFromParent_Done,
     /* 329744 */   // Label 6473: @329744
     /* 329744 */   GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(329855), // Rule ID 4911 //
     /* 329749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 329760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329764 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329768 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329772 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329777 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 329781 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 329785 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329789 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 329793 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329798 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 329802 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329807 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 329809 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 329809 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 329812 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329816 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329821 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 329827 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329832 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329842 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 329846 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329853 */     GIR_RootConstrainSelectedInstOperands,
     /* 329854 */     // GIR_Coverage, 4911,
     /* 329854 */     GIR_EraseRootFromParent_Done,
     /* 329855 */   // Label 6474: @329855
     /* 329855 */   GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(329919), // Rule ID 654 //
     /* 329860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 329871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329879 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329883 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329888 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329898 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 329900 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 329900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329905 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 329909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 329913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329917 */     GIR_RootConstrainSelectedInstOperands,
     /* 329918 */     // GIR_Coverage, 654,
     /* 329918 */     GIR_EraseRootFromParent_Done,
     /* 329919 */   // Label 6475: @329919
     /* 329919 */   GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(329983), // Rule ID 653 //
     /* 329924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 329935 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 329939 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 329943 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 329947 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329952 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329957 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329962 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 329964 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 329964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 329967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 329969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 329973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 329977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 329981 */     GIR_RootConstrainSelectedInstOperands,
     /* 329982 */     // GIR_Coverage, 653,
     /* 329982 */     GIR_EraseRootFromParent_Done,
     /* 329983 */   // Label 6476: @329983
     /* 329983 */   GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(330034), // Rule ID 630 //
     /* 329988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 329995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 329999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 330003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 330007 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330017 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330019 */     // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 330019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 330022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 330028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 330032 */     GIR_RootConstrainSelectedInstOperands,
     /* 330033 */     // GIR_Coverage, 630,
     /* 330033 */     GIR_EraseRootFromParent_Done,
     /* 330034 */   // Label 6477: @330034
     /* 330034 */   GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(330085), // Rule ID 629 //
     /* 330039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 330050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 330054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 330058 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330063 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330068 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330070 */     // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 330070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 330073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 330079 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 330083 */     GIR_RootConstrainSelectedInstOperands,
     /* 330084 */     // GIR_Coverage, 629,
     /* 330084 */     GIR_EraseRootFromParent_Done,
     /* 330085 */   // Label 6478: @330085
     /* 330085 */   GIM_Try, /*On fail goto*//*Label 6479*/ GIMT_Encode4(330104), // Rule ID 528 //
     /* 330090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330093 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330097 */     // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 330097 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGHr),
     /* 330102 */     GIR_RootConstrainSelectedInstOperands,
     /* 330103 */     // GIR_Coverage, 528,
     /* 330103 */     GIR_Done,
     /* 330104 */   // Label 6479: @330104
     /* 330104 */   GIM_Try, /*On fail goto*//*Label 6480*/ GIMT_Encode4(330249), // Rule ID 6443 //
     /* 330109 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330113 */     // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (EORWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32768:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
     /* 330113 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 330116 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 330120 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330125 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 330127 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /* 330130 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 330134 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330139 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 330142 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 330146 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 330149 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330154 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330159 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330164 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 330167 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330171 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330176 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 330179 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 330184 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 330187 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
     /* 330191 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330196 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 330199 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // 
     /* 330204 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 330206 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330209 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330213 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330218 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 330221 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 330231 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 330238 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330243 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330248 */     // GIR_Coverage, 6443,
     /* 330248 */     GIR_EraseRootFromParent_Done,
     /* 330249 */   // Label 6480: @330249
     /* 330249 */   GIM_Reject,
     /* 330250 */ // Label 6468: @330250
     /* 330250 */ GIM_Reject,
     /* 330251 */ // Label 6460: @330251
     /* 330251 */ GIM_Try, /*On fail goto*//*Label 6481*/ GIMT_Encode4(331273),
     /* 330256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 330259 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330263 */   GIM_Try, /*On fail goto*//*Label 6482*/ GIMT_Encode4(330421), // Rule ID 4922 //
     /* 330268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 330279 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330287 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330291 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 330295 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330299 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330303 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330307 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330312 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330316 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 330320 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330324 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330328 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 330332 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330337 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 330341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330346 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330348 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 330348 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 330351 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330355 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330360 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 330366 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330371 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330376 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330379 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330383 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330388 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330394 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330399 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 330407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330409 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330412 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 330415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 330419 */     GIR_RootConstrainSelectedInstOperands,
     /* 330420 */     // GIR_Coverage, 4922,
     /* 330420 */     GIR_EraseRootFromParent_Done,
     /* 330421 */   // Label 6482: @330421
     /* 330421 */   GIM_Try, /*On fail goto*//*Label 6483*/ GIMT_Encode4(330579), // Rule ID 4921 //
     /* 330426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330429 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330433 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 330437 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330441 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330445 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 330453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330457 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330461 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330465 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330470 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330474 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 330478 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330482 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330486 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 330490 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330495 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 330499 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330504 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330506 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 330506 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 330509 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330513 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330518 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 330524 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330529 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330534 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330537 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330541 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330546 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330552 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330557 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 330565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330567 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330570 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 330573 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 330577 */     GIR_RootConstrainSelectedInstOperands,
     /* 330578 */     // GIR_Coverage, 4921,
     /* 330578 */     GIR_EraseRootFromParent_Done,
     /* 330579 */   // Label 6483: @330579
     /* 330579 */   GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(330690), // Rule ID 4920 //
     /* 330584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330587 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330591 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 330595 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330599 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330603 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 330611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330615 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330619 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330623 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330628 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330632 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330637 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330642 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330644 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 330644 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330647 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330651 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330656 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330662 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330667 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 330675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330677 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 330684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 330688 */     GIR_RootConstrainSelectedInstOperands,
     /* 330689 */     // GIR_Coverage, 4920,
     /* 330689 */     GIR_EraseRootFromParent_Done,
     /* 330690 */   // Label 6484: @330690
     /* 330690 */   GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(330801), // Rule ID 4918 //
     /* 330695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330698 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330702 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 330706 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330710 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330714 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330718 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330723 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330727 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330731 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330735 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330739 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330744 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330748 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330753 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330755 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 330755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330767 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 330773 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330778 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 330786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 330792 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 330799 */     GIR_RootConstrainSelectedInstOperands,
     /* 330800 */     // GIR_Coverage, 4918,
     /* 330800 */     GIR_EraseRootFromParent_Done,
     /* 330801 */   // Label 6485: @330801
     /* 330801 */   GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(330912), // Rule ID 4919 //
     /* 330806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330809 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330813 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 330817 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330821 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330825 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330829 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 330833 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330837 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330841 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330845 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330850 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330854 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330859 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330864 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330866 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 330866 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330869 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330873 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330878 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330884 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330889 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 330897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330899 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330902 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 330906 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 330910 */     GIR_RootConstrainSelectedInstOperands,
     /* 330911 */     // GIR_Coverage, 4919,
     /* 330911 */     GIR_EraseRootFromParent_Done,
     /* 330912 */   // Label 6486: @330912
     /* 330912 */   GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(331023), // Rule ID 4917 //
     /* 330917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 330920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 330928 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 330932 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 330936 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 330940 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330945 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330949 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330953 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330957 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330961 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330966 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 330970 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330975 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330977 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 330977 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330980 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330984 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330989 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 330995 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331000 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 331008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331014 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331017 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331021 */     GIR_RootConstrainSelectedInstOperands,
     /* 331022 */     // GIR_Coverage, 4917,
     /* 331022 */     GIR_EraseRootFromParent_Done,
     /* 331023 */   // Label 6487: @331023
     /* 331023 */   GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(331087), // Rule ID 656 //
     /* 331028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 331039 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331043 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 331047 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 331051 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331061 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331066 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331068 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 331068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 331071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331081 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331085 */     GIR_RootConstrainSelectedInstOperands,
     /* 331086 */     // GIR_Coverage, 656,
     /* 331086 */     GIR_EraseRootFromParent_Done,
     /* 331087 */   // Label 6488: @331087
     /* 331087 */   GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(331151), // Rule ID 655 //
     /* 331092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331095 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331099 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 331103 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331107 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 331111 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 331115 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331120 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331125 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331130 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331132 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 331132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 331135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331149 */     GIR_RootConstrainSelectedInstOperands,
     /* 331150 */     // GIR_Coverage, 655,
     /* 331150 */     GIR_EraseRootFromParent_Done,
     /* 331151 */   // Label 6489: @331151
     /* 331151 */   GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(331202), // Rule ID 632 //
     /* 331156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331159 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331163 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 331167 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331171 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 331175 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331180 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331185 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331187 */     // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 331187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 331190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331192 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331196 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331200 */     GIR_RootConstrainSelectedInstOperands,
     /* 331201 */     // GIR_Coverage, 632,
     /* 331201 */     GIR_EraseRootFromParent_Done,
     /* 331202 */   // Label 6490: @331202
     /* 331202 */   GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(331253), // Rule ID 631 //
     /* 331207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331210 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331214 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 331218 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331222 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 331226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331231 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331236 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331238 */     // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 331238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 331241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331243 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331247 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331251 */     GIR_RootConstrainSelectedInstOperands,
     /* 331252 */     // GIR_Coverage, 631,
     /* 331252 */     GIR_EraseRootFromParent_Done,
     /* 331253 */   // Label 6491: @331253
     /* 331253 */   GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(331272), // Rule ID 529 //
     /* 331258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331261 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331265 */     // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 331265 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGSr),
     /* 331270 */     GIR_RootConstrainSelectedInstOperands,
     /* 331271 */     // GIR_Coverage, 529,
     /* 331271 */     GIR_Done,
     /* 331272 */   // Label 6492: @331272
     /* 331272 */   GIM_Reject,
     /* 331273 */ // Label 6481: @331273
     /* 331273 */ GIM_Reject,
     /* 331274 */ // Label 6461: @331274
     /* 331274 */ GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(332296),
     /* 331279 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 331282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331286 */   GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(331444), // Rule ID 4928 //
     /* 331291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331294 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 331302 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331310 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331314 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 331318 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331322 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331326 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331330 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331335 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331339 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 331343 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331347 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331351 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 331355 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331360 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 331364 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331369 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 331371 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 331371 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 331374 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331378 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331383 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 331389 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331394 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331399 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331402 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331406 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331411 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331417 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331422 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 331430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331432 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331435 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 331438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331442 */     GIR_RootConstrainSelectedInstOperands,
     /* 331443 */     // GIR_Coverage, 4928,
     /* 331443 */     GIR_EraseRootFromParent_Done,
     /* 331444 */   // Label 6494: @331444
     /* 331444 */   GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(331602), // Rule ID 4927 //
     /* 331449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 331460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331464 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331468 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331472 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 331476 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331480 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331484 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331488 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331493 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331497 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 331501 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331505 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331509 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 331513 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331518 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 331522 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331527 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 331529 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 331529 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 331532 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331536 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331541 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 331547 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331552 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331557 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331560 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331564 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331569 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331575 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331580 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 331588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331590 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331593 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 331596 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331600 */     GIR_RootConstrainSelectedInstOperands,
     /* 331601 */     // GIR_Coverage, 4927,
     /* 331601 */     GIR_EraseRootFromParent_Done,
     /* 331602 */   // Label 6495: @331602
     /* 331602 */   GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(331713), // Rule ID 4926 //
     /* 331607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331610 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331614 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 331618 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331622 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331626 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331630 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 331634 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331638 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331642 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331646 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331651 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331655 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331660 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331665 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331667 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 331667 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331670 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331674 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331679 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331685 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331690 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 331698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331700 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331711 */     GIR_RootConstrainSelectedInstOperands,
     /* 331712 */     // GIR_Coverage, 4926,
     /* 331712 */     GIR_EraseRootFromParent_Done,
     /* 331713 */   // Label 6496: @331713
     /* 331713 */   GIM_Try, /*On fail goto*//*Label 6497*/ GIMT_Encode4(331824), // Rule ID 4924 //
     /* 331718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 331729 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331733 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331737 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331741 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331746 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331750 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331754 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331758 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331762 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331767 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331771 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331776 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331778 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 331778 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331781 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331785 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331790 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 331796 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331801 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 331809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 331815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331822 */     GIR_RootConstrainSelectedInstOperands,
     /* 331823 */     // GIR_Coverage, 4924,
     /* 331823 */     GIR_EraseRootFromParent_Done,
     /* 331824 */   // Label 6497: @331824
     /* 331824 */   GIM_Try, /*On fail goto*//*Label 6498*/ GIMT_Encode4(331935), // Rule ID 4925 //
     /* 331829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331832 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331836 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 331840 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331844 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331848 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331852 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 331856 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331860 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331864 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331868 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331873 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331877 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331887 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331889 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 331889 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331892 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331896 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331901 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331907 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331912 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 331920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331922 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331925 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 331929 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 331933 */     GIR_RootConstrainSelectedInstOperands,
     /* 331934 */     // GIR_Coverage, 4925,
     /* 331934 */     GIR_EraseRootFromParent_Done,
     /* 331935 */   // Label 6498: @331935
     /* 331935 */   GIM_Try, /*On fail goto*//*Label 6499*/ GIMT_Encode4(332046), // Rule ID 4923 //
     /* 331940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 331951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331959 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 331963 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331968 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331976 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331980 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331984 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331989 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 331993 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331998 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 332000 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 332000 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 332003 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 332007 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332012 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 332018 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332023 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 332031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332033 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 332037 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 332044 */     GIR_RootConstrainSelectedInstOperands,
     /* 332045 */     // GIR_Coverage, 4923,
     /* 332045 */     GIR_EraseRootFromParent_Done,
     /* 332046 */   // Label 6499: @332046
     /* 332046 */   GIM_Try, /*On fail goto*//*Label 6500*/ GIMT_Encode4(332110), // Rule ID 658 //
     /* 332051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 332062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332070 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 332074 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332079 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332084 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332089 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332091 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 332091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 332094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332096 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 332100 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 332104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 332108 */     GIR_RootConstrainSelectedInstOperands,
     /* 332109 */     // GIR_Coverage, 658,
     /* 332109 */     GIR_EraseRootFromParent_Done,
     /* 332110 */   // Label 6500: @332110
     /* 332110 */   GIM_Try, /*On fail goto*//*Label 6501*/ GIMT_Encode4(332174), // Rule ID 657 //
     /* 332115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332118 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332122 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 332126 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332130 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332134 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 332138 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332143 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332148 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332153 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332155 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 332155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 332158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 332164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 332168 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 332172 */     GIR_RootConstrainSelectedInstOperands,
     /* 332173 */     // GIR_Coverage, 657,
     /* 332173 */     GIR_EraseRootFromParent_Done,
     /* 332174 */   // Label 6501: @332174
     /* 332174 */   GIM_Try, /*On fail goto*//*Label 6502*/ GIMT_Encode4(332225), // Rule ID 634 //
     /* 332179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 332190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332194 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332203 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332208 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332210 */     // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 332210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 332213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 332219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 332223 */     GIR_RootConstrainSelectedInstOperands,
     /* 332224 */     // GIR_Coverage, 634,
     /* 332224 */     GIR_EraseRootFromParent_Done,
     /* 332225 */   // Label 6502: @332225
     /* 332225 */   GIM_Try, /*On fail goto*//*Label 6503*/ GIMT_Encode4(332276), // Rule ID 633 //
     /* 332230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 332241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332245 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332249 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332254 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332259 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332261 */     // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 332261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 332264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 332270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 332274 */     GIR_RootConstrainSelectedInstOperands,
     /* 332275 */     // GIR_Coverage, 633,
     /* 332275 */     GIR_EraseRootFromParent_Done,
     /* 332276 */   // Label 6503: @332276
     /* 332276 */   GIM_Try, /*On fail goto*//*Label 6504*/ GIMT_Encode4(332295), // Rule ID 530 //
     /* 332281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332284 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332288 */     // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 332288 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGDr),
     /* 332293 */     GIR_RootConstrainSelectedInstOperands,
     /* 332294 */     // GIR_Coverage, 530,
     /* 332294 */     GIR_Done,
     /* 332295 */   // Label 6504: @332295
     /* 332295 */   GIM_Reject,
     /* 332296 */ // Label 6493: @332296
     /* 332296 */ GIM_Reject,
     /* 332297 */ // Label 6462: @332297
     /* 332297 */ GIM_Try, /*On fail goto*//*Label 6505*/ GIMT_Encode4(332323), // Rule ID 864 //
     /* 332302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332305 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 332308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332312 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332316 */   // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 332316 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f32),
     /* 332321 */   GIR_RootConstrainSelectedInstOperands,
     /* 332322 */   // GIR_Coverage, 864,
     /* 332322 */   GIR_Done,
     /* 332323 */ // Label 6505: @332323
     /* 332323 */ GIM_Reject,
     /* 332324 */ // Label 6463: @332324
     /* 332324 */ GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(332350), // Rule ID 866 //
     /* 332329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332332 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 332335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332339 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332343 */   // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 332343 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f64),
     /* 332348 */   GIR_RootConstrainSelectedInstOperands,
     /* 332349 */   // GIR_Coverage, 866,
     /* 332349 */   GIR_Done,
     /* 332350 */ // Label 6506: @332350
     /* 332350 */ GIM_Reject,
     /* 332351 */ // Label 6464: @332351
     /* 332351 */ GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(332430),
     /* 332356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 332359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332363 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332367 */   GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(332382), // Rule ID 862 //
     /* 332372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 332375 */     // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 332375 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f16),
     /* 332380 */     GIR_RootConstrainSelectedInstOperands,
     /* 332381 */     // GIR_Coverage, 862,
     /* 332381 */     GIR_Done,
     /* 332382 */   // Label 6508: @332382
     /* 332382 */   GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(332429), // Rule ID 6446 //
     /* 332387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332390 */     // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (EORv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (MOVIv4i16:{ *:[i64] } 128:{ *:[i32] }, 8:{ *:[i32] }))
     /* 332390 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 332393 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i16),
     /* 332397 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332402 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
     /* 332412 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 332415 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 332417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /* 332420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332422 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332424 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332427 */     GIR_RootConstrainSelectedInstOperands,
     /* 332428 */     // GIR_Coverage, 6446,
     /* 332428 */     GIR_EraseRootFromParent_Done,
     /* 332429 */   // Label 6509: @332429
     /* 332429 */   GIM_Reject,
     /* 332430 */ // Label 6507: @332430
     /* 332430 */ GIM_Reject,
     /* 332431 */ // Label 6465: @332431
     /* 332431 */ GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(332457), // Rule ID 865 //
     /* 332436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332439 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332446 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332450 */   // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 332450 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f32),
     /* 332455 */   GIR_RootConstrainSelectedInstOperands,
     /* 332456 */   // GIR_Coverage, 865,
     /* 332456 */   GIR_Done,
     /* 332457 */ // Label 6510: @332457
     /* 332457 */ GIM_Reject,
     /* 332458 */ // Label 6466: @332458
     /* 332458 */ GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(332537),
     /* 332463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 332466 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332470 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332474 */   GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(332489), // Rule ID 863 //
     /* 332479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 332482 */     // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 332482 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv8f16),
     /* 332487 */     GIR_RootConstrainSelectedInstOperands,
     /* 332488 */     // GIR_Coverage, 863,
     /* 332488 */     GIR_Done,
     /* 332489 */   // Label 6512: @332489
     /* 332489 */   GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(332536), // Rule ID 6447 //
     /* 332494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332497 */     // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (EORv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (MOVIv8i16:{ *:[f128] } 128:{ *:[i32] }, 8:{ *:[i32] }))
     /* 332497 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 332500 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv8i16),
     /* 332504 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332509 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
     /* 332519 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 332522 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 332524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /* 332527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332529 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332531 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332534 */     GIR_RootConstrainSelectedInstOperands,
     /* 332535 */     // GIR_Coverage, 6447,
     /* 332535 */     GIR_EraseRootFromParent_Done,
     /* 332536 */   // Label 6513: @332536
     /* 332536 */   GIM_Reject,
     /* 332537 */ // Label 6511: @332537
     /* 332537 */ GIM_Reject,
     /* 332538 */ // Label 6467: @332538
     /* 332538 */ GIM_Reject,
     /* 332539 */ // Label 65: @332539
     /* 332539 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(9), /*)*//*default:*//*Label 6518*/ GIMT_Encode4(332786),
     /* 332550 */ /*GILLT_s32*//*Label 6514*/ GIMT_Encode4(332578),
     /* 332554 */ /*GILLT_s64*//*Label 6515*/ GIMT_Encode4(332609), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 332566 */ /*GILLT_v2s64*//*Label 6516*/ GIMT_Encode4(332670), GIMT_Encode4(0),
     /* 332574 */ /*GILLT_v4s32*//*Label 6517*/ GIMT_Encode4(332728),
     /* 332578 */ // Label 6514: @332578
     /* 332578 */ GIM_Try, /*On fail goto*//*Label 6519*/ GIMT_Encode4(332608), // Rule ID 520 //
     /* 332583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332586 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 332589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332593 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 332597 */   // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 332597 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSHr),
     /* 332602 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332606 */   GIR_RootConstrainSelectedInstOperands,
     /* 332607 */   // GIR_Coverage, 520,
     /* 332607 */   GIR_Done,
     /* 332608 */ // Label 6519: @332608
     /* 332608 */ GIM_Reject,
     /* 332609 */ // Label 6515: @332609
     /* 332609 */ GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(332639), // Rule ID 518 //
     /* 332614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332617 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 332620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332624 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 332628 */   // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 332628 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDHr),
     /* 332633 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332637 */   GIR_RootConstrainSelectedInstOperands,
     /* 332638 */   // GIR_Coverage, 518,
     /* 332638 */   GIR_Done,
     /* 332639 */ // Label 6520: @332639
     /* 332639 */ GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(332669), // Rule ID 522 //
     /* 332644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332647 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 332650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332654 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332658 */   // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 332658 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDSr),
     /* 332663 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332667 */   GIR_RootConstrainSelectedInstOperands,
     /* 332668 */   // GIR_Coverage, 522,
     /* 332668 */   GIR_Done,
     /* 332669 */ // Label 6521: @332669
     /* 332669 */ GIM_Reject,
     /* 332670 */ // Label 6516: @332670
     /* 332670 */ GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(332727),
     /* 332675 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 332678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332682 */   GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(332706), // Rule ID 4971 //
     /* 332687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 332694 */     // (fpextend:{ *:[v2f64] } (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn))  =>  (FCVTLv4i32:{ *:[v2f64] } V128:{ *:[v4f32] }:$Rn)
     /* 332694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i32),
     /* 332697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 332704 */     GIR_RootConstrainSelectedInstOperands,
     /* 332705 */     // GIR_Coverage, 4971,
     /* 332705 */     GIR_EraseRootFromParent_Done,
     /* 332706 */   // Label 6523: @332706
     /* 332706 */   GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(332726), // Rule ID 4969 //
     /* 332711 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332715 */     // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn)
     /* 332715 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv2i32),
     /* 332720 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332724 */     GIR_RootConstrainSelectedInstOperands,
     /* 332725 */     // GIR_Coverage, 4969,
     /* 332725 */     GIR_Done,
     /* 332726 */   // Label 6524: @332726
     /* 332726 */   GIM_Reject,
     /* 332727 */ // Label 6522: @332727
     /* 332727 */ GIM_Reject,
     /* 332728 */ // Label 6517: @332728
     /* 332728 */ GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(332785),
     /* 332733 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 332736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332740 */   GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(332764), // Rule ID 4975 //
     /* 332745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 332752 */     // (fpextend:{ *:[v4f32] } (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn))  =>  (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)
     /* 332752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 332755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 332762 */     GIR_RootConstrainSelectedInstOperands,
     /* 332763 */     // GIR_Coverage, 4975,
     /* 332763 */     GIR_EraseRootFromParent_Done,
     /* 332764 */   // Label 6526: @332764
     /* 332764 */   GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(332784), // Rule ID 4973 //
     /* 332769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332773 */     // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn)
     /* 332773 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 332778 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332782 */     GIR_RootConstrainSelectedInstOperands,
     /* 332783 */     // GIR_Coverage, 4973,
     /* 332783 */     GIR_Done,
     /* 332784 */   // Label 6527: @332784
     /* 332784 */   GIM_Reject,
     /* 332785 */ // Label 6525: @332785
     /* 332785 */ GIM_Reject,
     /* 332786 */ // Label 6518: @332786
     /* 332786 */ GIM_Reject,
     /* 332787 */ // Label 66: @332787
     /* 332787 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 6532*/ GIMT_Encode4(332974),
     /* 332798 */ /*GILLT_s16*//*Label 6528*/ GIMT_Encode4(332826),
     /* 332802 */ /*GILLT_s32*//*Label 6529*/ GIMT_Encode4(332887), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 332814 */ /*GILLT_v2s32*//*Label 6530*/ GIMT_Encode4(332918), GIMT_Encode4(0),
     /* 332822 */ /*GILLT_v4s16*//*Label 6531*/ GIMT_Encode4(332946),
     /* 332826 */ // Label 6528: @332826
     /* 332826 */ GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(332856), // Rule ID 514 //
     /* 332831 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332834 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 332837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 332841 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332845 */   // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)
     /* 332845 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHDr),
     /* 332850 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332854 */   GIR_RootConstrainSelectedInstOperands,
     /* 332855 */   // GIR_Coverage, 514,
     /* 332855 */   GIR_Done,
     /* 332856 */ // Label 6533: @332856
     /* 332856 */ GIM_Try, /*On fail goto*//*Label 6534*/ GIMT_Encode4(332886), // Rule ID 524 //
     /* 332861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 332867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 332871 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332875 */   // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)
     /* 332875 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHSr),
     /* 332880 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332884 */   GIR_RootConstrainSelectedInstOperands,
     /* 332885 */   // GIR_Coverage, 524,
     /* 332885 */   GIR_Done,
     /* 332886 */ // Label 6534: @332886
     /* 332886 */ GIM_Reject,
     /* 332887 */ // Label 6529: @332887
     /* 332887 */ GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(332917), // Rule ID 516 //
     /* 332892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 332895 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 332898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332902 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332906 */   // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 332906 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSDr),
     /* 332911 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332915 */   GIR_RootConstrainSelectedInstOperands,
     /* 332916 */   // GIR_Coverage, 516,
     /* 332916 */   GIR_Done,
     /* 332917 */ // Label 6535: @332917
     /* 332917 */ GIM_Reject,
     /* 332918 */ // Label 6530: @332918
     /* 332918 */ GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(332945), // Rule ID 4979 //
     /* 332923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 332926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332930 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332934 */   // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
     /* 332934 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv2i32),
     /* 332939 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332943 */   GIR_RootConstrainSelectedInstOperands,
     /* 332944 */   // GIR_Coverage, 4979,
     /* 332944 */   GIR_Done,
     /* 332945 */ // Label 6536: @332945
     /* 332945 */ GIM_Reject,
     /* 332946 */ // Label 6531: @332946
     /* 332946 */ GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(332973), // Rule ID 4981 //
     /* 332951 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332958 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332962 */   // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)
     /* 332962 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 332967 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332971 */   GIR_RootConstrainSelectedInstOperands,
     /* 332972 */   // GIR_Coverage, 4981,
     /* 332972 */   GIR_Done,
     /* 332973 */ // Label 6537: @332973
     /* 332973 */ GIM_Reject,
     /* 332974 */ // Label 6532: @332974
     /* 332974 */ GIM_Reject,
     /* 332975 */ // Label 67: @332975
     /* 332975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6545*/ GIMT_Encode4(333951),
     /* 332986 */ /*GILLT_s32*//*Label 6538*/ GIMT_Encode4(333022),
     /* 332990 */ /*GILLT_s64*//*Label 6539*/ GIMT_Encode4(333409), GIMT_Encode4(0),
     /* 332998 */ /*GILLT_v2s32*//*Label 6540*/ GIMT_Encode4(333796),
     /* 333002 */ /*GILLT_v2s64*//*Label 6541*/ GIMT_Encode4(333827),
     /* 333006 */ /*GILLT_v4s16*//*Label 6542*/ GIMT_Encode4(333858),
     /* 333010 */ /*GILLT_v4s32*//*Label 6543*/ GIMT_Encode4(333889), GIMT_Encode4(0),
     /* 333018 */ /*GILLT_v8s16*//*Label 6544*/ GIMT_Encode4(333920),
     /* 333022 */ // Label 6538: @333022
     /* 333022 */ GIM_Try, /*On fail goto*//*Label 6546*/ GIMT_Encode4(333059), // Rule ID 4718 //
     /* 333027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333034 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333038 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 333042 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333046 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333048 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 333048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
     /* 333051 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333053 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333057 */   GIR_RootConstrainSelectedInstOperands,
     /* 333058 */   // GIR_Coverage, 4718,
     /* 333058 */   GIR_EraseRootFromParent_Done,
     /* 333059 */ // Label 6546: @333059
     /* 333059 */ GIM_Try, /*On fail goto*//*Label 6547*/ GIMT_Encode4(333096), // Rule ID 4720 //
     /* 333064 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333071 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333075 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 333079 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333083 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333085 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 333085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
     /* 333088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333090 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333094 */   GIR_RootConstrainSelectedInstOperands,
     /* 333095 */   // GIR_Coverage, 4720,
     /* 333095 */   GIR_EraseRootFromParent_Done,
     /* 333096 */ // Label 6547: @333096
     /* 333096 */ GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(333133), // Rule ID 4738 //
     /* 333101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333108 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333112 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 333116 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333120 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333122 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 333122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
     /* 333125 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333127 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333131 */   GIR_RootConstrainSelectedInstOperands,
     /* 333132 */   // GIR_Coverage, 4738,
     /* 333132 */   GIR_EraseRootFromParent_Done,
     /* 333133 */ // Label 6548: @333133
     /* 333133 */ GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(333170), // Rule ID 4740 //
     /* 333138 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333141 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333145 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333149 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 333153 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333157 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333159 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 333159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
     /* 333162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333164 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333168 */   GIR_RootConstrainSelectedInstOperands,
     /* 333169 */   // GIR_Coverage, 4740,
     /* 333169 */   GIR_EraseRootFromParent_Done,
     /* 333170 */ // Label 6549: @333170
     /* 333170 */ GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(333207), // Rule ID 4778 //
     /* 333175 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333178 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333182 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333186 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 333190 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333194 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333196 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 333196 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 333199 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333201 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333205 */   GIR_RootConstrainSelectedInstOperands,
     /* 333206 */   // GIR_Coverage, 4778,
     /* 333206 */   GIR_EraseRootFromParent_Done,
     /* 333207 */ // Label 6550: @333207
     /* 333207 */ GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(333244), // Rule ID 4780 //
     /* 333212 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333219 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333223 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 333227 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333231 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333233 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 333233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 333236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333238 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333242 */   GIR_RootConstrainSelectedInstOperands,
     /* 333243 */   // GIR_Coverage, 4780,
     /* 333243 */   GIR_EraseRootFromParent_Done,
     /* 333244 */ // Label 6551: @333244
     /* 333244 */ GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(333281), // Rule ID 4758 //
     /* 333249 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333252 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333256 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333260 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 333264 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333268 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333270 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 333270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 333273 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333275 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333279 */   GIR_RootConstrainSelectedInstOperands,
     /* 333280 */   // GIR_Coverage, 4758,
     /* 333280 */   GIR_EraseRootFromParent_Done,
     /* 333281 */ // Label 6552: @333281
     /* 333281 */ GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(333318), // Rule ID 4760 //
     /* 333286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333293 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333297 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 333301 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333305 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333307 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 333307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 333310 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333312 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333316 */   GIR_RootConstrainSelectedInstOperands,
     /* 333317 */   // GIR_Coverage, 4760,
     /* 333317 */   GIR_EraseRootFromParent_Done,
     /* 333318 */ // Label 6553: @333318
     /* 333318 */ GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(333348), // Rule ID 399 //
     /* 333323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 333326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 333329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333333 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 333337 */   // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 333337 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 333342 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333346 */   GIR_RootConstrainSelectedInstOperands,
     /* 333347 */   // GIR_Coverage, 399,
     /* 333347 */   GIR_Done,
     /* 333348 */ // Label 6554: @333348
     /* 333348 */ GIM_Try, /*On fail goto*//*Label 6555*/ GIMT_Encode4(333378), // Rule ID 403 //
     /* 333353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 333356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333363 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333367 */   // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 333367 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 333372 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333376 */   GIR_RootConstrainSelectedInstOperands,
     /* 333377 */   // GIR_Coverage, 403,
     /* 333377 */   GIR_Done,
     /* 333378 */ // Label 6555: @333378
     /* 333378 */ GIM_Try, /*On fail goto*//*Label 6556*/ GIMT_Encode4(333408), // Rule ID 407 //
     /* 333383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 333386 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 333393 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333397 */   // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 333397 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 333402 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333406 */   GIR_RootConstrainSelectedInstOperands,
     /* 333407 */   // GIR_Coverage, 407,
     /* 333407 */   GIR_Done,
     /* 333408 */ // Label 6556: @333408
     /* 333408 */ GIM_Reject,
     /* 333409 */ // Label 6539: @333409
     /* 333409 */ GIM_Try, /*On fail goto*//*Label 6557*/ GIMT_Encode4(333446), // Rule ID 4719 //
     /* 333414 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333421 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333425 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 333429 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333433 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333435 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 333435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
     /* 333438 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333440 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333444 */   GIR_RootConstrainSelectedInstOperands,
     /* 333445 */   // GIR_Coverage, 4719,
     /* 333445 */   GIR_EraseRootFromParent_Done,
     /* 333446 */ // Label 6557: @333446
     /* 333446 */ GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(333483), // Rule ID 4721 //
     /* 333451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333458 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333462 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 333466 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333470 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333472 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 333472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
     /* 333475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333477 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333481 */   GIR_RootConstrainSelectedInstOperands,
     /* 333482 */   // GIR_Coverage, 4721,
     /* 333482 */   GIR_EraseRootFromParent_Done,
     /* 333483 */ // Label 6558: @333483
     /* 333483 */ GIM_Try, /*On fail goto*//*Label 6559*/ GIMT_Encode4(333520), // Rule ID 4739 //
     /* 333488 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333491 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333495 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333499 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 333503 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333507 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333509 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 333509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
     /* 333512 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333514 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333518 */   GIR_RootConstrainSelectedInstOperands,
     /* 333519 */   // GIR_Coverage, 4739,
     /* 333519 */   GIR_EraseRootFromParent_Done,
     /* 333520 */ // Label 6559: @333520
     /* 333520 */ GIM_Try, /*On fail goto*//*Label 6560*/ GIMT_Encode4(333557), // Rule ID 4741 //
     /* 333525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333532 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333536 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 333540 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333544 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333546 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 333546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
     /* 333549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333551 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333555 */   GIR_RootConstrainSelectedInstOperands,
     /* 333556 */   // GIR_Coverage, 4741,
     /* 333556 */   GIR_EraseRootFromParent_Done,
     /* 333557 */ // Label 6560: @333557
     /* 333557 */ GIM_Try, /*On fail goto*//*Label 6561*/ GIMT_Encode4(333594), // Rule ID 4779 //
     /* 333562 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333569 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333573 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 333577 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333581 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333583 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 333583 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 333586 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333588 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333592 */   GIR_RootConstrainSelectedInstOperands,
     /* 333593 */   // GIR_Coverage, 4779,
     /* 333593 */   GIR_EraseRootFromParent_Done,
     /* 333594 */ // Label 6561: @333594
     /* 333594 */ GIM_Try, /*On fail goto*//*Label 6562*/ GIMT_Encode4(333631), // Rule ID 4781 //
     /* 333599 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333606 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333610 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 333614 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333618 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333620 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 333620 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 333623 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333625 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333629 */   GIR_RootConstrainSelectedInstOperands,
     /* 333630 */   // GIR_Coverage, 4781,
     /* 333630 */   GIR_EraseRootFromParent_Done,
     /* 333631 */ // Label 6562: @333631
     /* 333631 */ GIM_Try, /*On fail goto*//*Label 6563*/ GIMT_Encode4(333668), // Rule ID 4759 //
     /* 333636 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333643 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333647 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 333651 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333655 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333657 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 333657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 333660 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333662 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333666 */   GIR_RootConstrainSelectedInstOperands,
     /* 333667 */   // GIR_Coverage, 4759,
     /* 333667 */   GIR_EraseRootFromParent_Done,
     /* 333668 */ // Label 6563: @333668
     /* 333668 */ GIM_Try, /*On fail goto*//*Label 6564*/ GIMT_Encode4(333705), // Rule ID 4761 //
     /* 333673 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333676 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333680 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333684 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 333688 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 333692 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333694 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 333694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 333697 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333699 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 333703 */   GIR_RootConstrainSelectedInstOperands,
     /* 333704 */   // GIR_Coverage, 4761,
     /* 333704 */   GIR_EraseRootFromParent_Done,
     /* 333705 */ // Label 6564: @333705
     /* 333705 */ GIM_Try, /*On fail goto*//*Label 6565*/ GIMT_Encode4(333735), // Rule ID 401 //
     /* 333710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 333713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 333716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333720 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 333724 */   // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 333724 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 333729 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333733 */   GIR_RootConstrainSelectedInstOperands,
     /* 333734 */   // GIR_Coverage, 401,
     /* 333734 */   GIR_Done,
     /* 333735 */ // Label 6565: @333735
     /* 333735 */ GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(333765), // Rule ID 405 //
     /* 333740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 333743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 333746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333754 */   // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 333754 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 333759 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333763 */   GIR_RootConstrainSelectedInstOperands,
     /* 333764 */   // GIR_Coverage, 405,
     /* 333764 */   GIR_Done,
     /* 333765 */ // Label 6566: @333765
     /* 333765 */ GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(333795), // Rule ID 409 //
     /* 333770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 333773 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 333776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 333780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333784 */   // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 333784 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 333789 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333793 */   GIR_RootConstrainSelectedInstOperands,
     /* 333794 */   // GIR_Coverage, 409,
     /* 333794 */   GIR_Done,
     /* 333795 */ // Label 6567: @333795
     /* 333795 */ GIM_Reject,
     /* 333796 */ // Label 6540: @333796
     /* 333796 */ GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(333826), // Rule ID 847 //
     /* 333801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333804 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 333807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333811 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333815 */   // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 333815 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 333820 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333824 */   GIR_RootConstrainSelectedInstOperands,
     /* 333825 */   // GIR_Coverage, 847,
     /* 333825 */   GIR_Done,
     /* 333826 */ // Label 6568: @333826
     /* 333826 */ GIM_Reject,
     /* 333827 */ // Label 6541: @333827
     /* 333827 */ GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(333857), // Rule ID 851 //
     /* 333832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 333838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333842 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333846 */   // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 333846 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 333851 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333855 */   GIR_RootConstrainSelectedInstOperands,
     /* 333856 */   // GIR_Coverage, 851,
     /* 333856 */   GIR_Done,
     /* 333857 */ // Label 6569: @333857
     /* 333857 */ GIM_Reject,
     /* 333858 */ // Label 6542: @333858
     /* 333858 */ GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(333888), // Rule ID 843 //
     /* 333863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333866 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 333869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333873 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333877 */   // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 333877 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 333882 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333886 */   GIR_RootConstrainSelectedInstOperands,
     /* 333887 */   // GIR_Coverage, 843,
     /* 333887 */   GIR_Done,
     /* 333888 */ // Label 6570: @333888
     /* 333888 */ GIM_Reject,
     /* 333889 */ // Label 6543: @333889
     /* 333889 */ GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(333919), // Rule ID 849 //
     /* 333894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 333900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333904 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333908 */   // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 333908 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 333913 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333917 */   GIR_RootConstrainSelectedInstOperands,
     /* 333918 */   // GIR_Coverage, 849,
     /* 333918 */   GIR_Done,
     /* 333919 */ // Label 6571: @333919
     /* 333919 */ GIM_Reject,
     /* 333920 */ // Label 6544: @333920
     /* 333920 */ GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(333950), // Rule ID 845 //
     /* 333925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333935 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333939 */   // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 333939 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 333944 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333948 */   GIR_RootConstrainSelectedInstOperands,
     /* 333949 */   // GIR_Coverage, 845,
     /* 333949 */   GIR_Done,
     /* 333950 */ // Label 6572: @333950
     /* 333950 */ GIM_Reject,
     /* 333951 */ // Label 6545: @333951
     /* 333951 */ GIM_Reject,
     /* 333952 */ // Label 68: @333952
     /* 333952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6580*/ GIMT_Encode4(334928),
     /* 333963 */ /*GILLT_s32*//*Label 6573*/ GIMT_Encode4(333999),
     /* 333967 */ /*GILLT_s64*//*Label 6574*/ GIMT_Encode4(334386), GIMT_Encode4(0),
     /* 333975 */ /*GILLT_v2s32*//*Label 6575*/ GIMT_Encode4(334773),
     /* 333979 */ /*GILLT_v2s64*//*Label 6576*/ GIMT_Encode4(334804),
     /* 333983 */ /*GILLT_v4s16*//*Label 6577*/ GIMT_Encode4(334835),
     /* 333987 */ /*GILLT_v4s32*//*Label 6578*/ GIMT_Encode4(334866), GIMT_Encode4(0),
     /* 333995 */ /*GILLT_v8s16*//*Label 6579*/ GIMT_Encode4(334897),
     /* 333999 */ // Label 6573: @333999
     /* 333999 */ GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(334036), // Rule ID 4728 //
     /* 334004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334011 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334015 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 334019 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334023 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334025 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 334025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
     /* 334028 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334030 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334034 */   GIR_RootConstrainSelectedInstOperands,
     /* 334035 */   // GIR_Coverage, 4728,
     /* 334035 */   GIR_EraseRootFromParent_Done,
     /* 334036 */ // Label 6581: @334036
     /* 334036 */ GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(334073), // Rule ID 4730 //
     /* 334041 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334048 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334052 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 334056 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334060 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334062 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 334062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
     /* 334065 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334067 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334071 */   GIR_RootConstrainSelectedInstOperands,
     /* 334072 */   // GIR_Coverage, 4730,
     /* 334072 */   GIR_EraseRootFromParent_Done,
     /* 334073 */ // Label 6582: @334073
     /* 334073 */ GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(334110), // Rule ID 4748 //
     /* 334078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334085 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334089 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 334093 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334097 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334099 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 334099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
     /* 334102 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334104 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334108 */   GIR_RootConstrainSelectedInstOperands,
     /* 334109 */   // GIR_Coverage, 4748,
     /* 334109 */   GIR_EraseRootFromParent_Done,
     /* 334110 */ // Label 6583: @334110
     /* 334110 */ GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(334147), // Rule ID 4750 //
     /* 334115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334122 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334126 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 334130 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334134 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334136 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 334136 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
     /* 334139 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334141 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334145 */   GIR_RootConstrainSelectedInstOperands,
     /* 334146 */   // GIR_Coverage, 4750,
     /* 334146 */   GIR_EraseRootFromParent_Done,
     /* 334147 */ // Label 6584: @334147
     /* 334147 */ GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(334184), // Rule ID 4788 //
     /* 334152 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334159 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334163 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 334167 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334171 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334173 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 334173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
     /* 334176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334178 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334182 */   GIR_RootConstrainSelectedInstOperands,
     /* 334183 */   // GIR_Coverage, 4788,
     /* 334183 */   GIR_EraseRootFromParent_Done,
     /* 334184 */ // Label 6585: @334184
     /* 334184 */ GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(334221), // Rule ID 4790 //
     /* 334189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334196 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334200 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 334204 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334208 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334210 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 334210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
     /* 334213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334215 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334219 */   GIR_RootConstrainSelectedInstOperands,
     /* 334220 */   // GIR_Coverage, 4790,
     /* 334220 */   GIR_EraseRootFromParent_Done,
     /* 334221 */ // Label 6586: @334221
     /* 334221 */ GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(334258), // Rule ID 4768 //
     /* 334226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334233 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334237 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 334241 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334245 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334247 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 334247 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 334250 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334252 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334256 */   GIR_RootConstrainSelectedInstOperands,
     /* 334257 */   // GIR_Coverage, 4768,
     /* 334257 */   GIR_EraseRootFromParent_Done,
     /* 334258 */ // Label 6587: @334258
     /* 334258 */ GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(334295), // Rule ID 4770 //
     /* 334263 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334270 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334274 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 334278 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334282 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334284 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 334284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 334287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334289 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334293 */   GIR_RootConstrainSelectedInstOperands,
     /* 334294 */   // GIR_Coverage, 4770,
     /* 334294 */   GIR_EraseRootFromParent_Done,
     /* 334295 */ // Label 6588: @334295
     /* 334295 */ GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(334325), // Rule ID 411 //
     /* 334300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 334303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 334306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334310 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334314 */   // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 334314 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 334319 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334323 */   GIR_RootConstrainSelectedInstOperands,
     /* 334324 */   // GIR_Coverage, 411,
     /* 334324 */   GIR_Done,
     /* 334325 */ // Label 6589: @334325
     /* 334325 */ GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(334355), // Rule ID 415 //
     /* 334330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 334333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334340 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 334344 */   // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 334344 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 334349 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334353 */   GIR_RootConstrainSelectedInstOperands,
     /* 334354 */   // GIR_Coverage, 415,
     /* 334354 */   GIR_Done,
     /* 334355 */ // Label 6590: @334355
     /* 334355 */ GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(334385), // Rule ID 419 //
     /* 334360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 334363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 334370 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334374 */   // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 334374 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 334379 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334383 */   GIR_RootConstrainSelectedInstOperands,
     /* 334384 */   // GIR_Coverage, 419,
     /* 334384 */   GIR_Done,
     /* 334385 */ // Label 6591: @334385
     /* 334385 */ GIM_Reject,
     /* 334386 */ // Label 6574: @334386
     /* 334386 */ GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(334423), // Rule ID 4729 //
     /* 334391 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334394 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334398 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334402 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 334406 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334410 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334412 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 334412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
     /* 334415 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334417 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334421 */   GIR_RootConstrainSelectedInstOperands,
     /* 334422 */   // GIR_Coverage, 4729,
     /* 334422 */   GIR_EraseRootFromParent_Done,
     /* 334423 */ // Label 6592: @334423
     /* 334423 */ GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(334460), // Rule ID 4731 //
     /* 334428 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334435 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334439 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 334443 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334447 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334449 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 334449 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
     /* 334452 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334454 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334458 */   GIR_RootConstrainSelectedInstOperands,
     /* 334459 */   // GIR_Coverage, 4731,
     /* 334459 */   GIR_EraseRootFromParent_Done,
     /* 334460 */ // Label 6593: @334460
     /* 334460 */ GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(334497), // Rule ID 4749 //
     /* 334465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334472 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334476 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 334480 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334484 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334486 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 334486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
     /* 334489 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334491 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334495 */   GIR_RootConstrainSelectedInstOperands,
     /* 334496 */   // GIR_Coverage, 4749,
     /* 334496 */   GIR_EraseRootFromParent_Done,
     /* 334497 */ // Label 6594: @334497
     /* 334497 */ GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(334534), // Rule ID 4751 //
     /* 334502 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334505 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334509 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334513 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 334517 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334521 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334523 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 334523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
     /* 334526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334528 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334532 */   GIR_RootConstrainSelectedInstOperands,
     /* 334533 */   // GIR_Coverage, 4751,
     /* 334533 */   GIR_EraseRootFromParent_Done,
     /* 334534 */ // Label 6595: @334534
     /* 334534 */ GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(334571), // Rule ID 4789 //
     /* 334539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334546 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334550 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 334554 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334558 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334560 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 334560 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
     /* 334563 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334565 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334569 */   GIR_RootConstrainSelectedInstOperands,
     /* 334570 */   // GIR_Coverage, 4789,
     /* 334570 */   GIR_EraseRootFromParent_Done,
     /* 334571 */ // Label 6596: @334571
     /* 334571 */ GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(334608), // Rule ID 4791 //
     /* 334576 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334583 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334587 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 334591 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334595 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334597 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 334597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
     /* 334600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334602 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334606 */   GIR_RootConstrainSelectedInstOperands,
     /* 334607 */   // GIR_Coverage, 4791,
     /* 334607 */   GIR_EraseRootFromParent_Done,
     /* 334608 */ // Label 6597: @334608
     /* 334608 */ GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(334645), // Rule ID 4769 //
     /* 334613 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334620 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334624 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 334628 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 334632 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334634 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 334634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 334637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334639 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334643 */   GIR_RootConstrainSelectedInstOperands,
     /* 334644 */   // GIR_Coverage, 4769,
     /* 334644 */   GIR_EraseRootFromParent_Done,
     /* 334645 */ // Label 6598: @334645
     /* 334645 */ GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(334682), // Rule ID 4771 //
     /* 334650 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334653 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334657 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334661 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 334665 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 334669 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334671 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 334671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 334674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334676 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 334680 */   GIR_RootConstrainSelectedInstOperands,
     /* 334681 */   // GIR_Coverage, 4771,
     /* 334681 */   GIR_EraseRootFromParent_Done,
     /* 334682 */ // Label 6599: @334682
     /* 334682 */ GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(334712), // Rule ID 413 //
     /* 334687 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 334690 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 334693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334697 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334701 */   // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 334701 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 334706 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334710 */   GIR_RootConstrainSelectedInstOperands,
     /* 334711 */   // GIR_Coverage, 413,
     /* 334711 */   GIR_Done,
     /* 334712 */ // Label 6600: @334712
     /* 334712 */ GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(334742), // Rule ID 417 //
     /* 334717 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 334720 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334727 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 334731 */   // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 334731 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 334736 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334740 */   GIR_RootConstrainSelectedInstOperands,
     /* 334741 */   // GIR_Coverage, 417,
     /* 334741 */   GIR_Done,
     /* 334742 */ // Label 6601: @334742
     /* 334742 */ GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(334772), // Rule ID 421 //
     /* 334747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 334750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 334753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 334757 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334761 */   // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 334761 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 334766 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334770 */   GIR_RootConstrainSelectedInstOperands,
     /* 334771 */   // GIR_Coverage, 421,
     /* 334771 */   GIR_Done,
     /* 334772 */ // Label 6602: @334772
     /* 334772 */ GIM_Reject,
     /* 334773 */ // Label 6575: @334773
     /* 334773 */ GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(334803), // Rule ID 857 //
     /* 334778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 334781 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 334784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334788 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334792 */   // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 334792 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 334797 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334801 */   GIR_RootConstrainSelectedInstOperands,
     /* 334802 */   // GIR_Coverage, 857,
     /* 334802 */   GIR_Done,
     /* 334803 */ // Label 6603: @334803
     /* 334803 */ GIM_Reject,
     /* 334804 */ // Label 6576: @334804
     /* 334804 */ GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(334834), // Rule ID 861 //
     /* 334809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 334812 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 334815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334819 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334823 */   // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 334823 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 334828 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334832 */   GIR_RootConstrainSelectedInstOperands,
     /* 334833 */   // GIR_Coverage, 861,
     /* 334833 */   GIR_Done,
     /* 334834 */ // Label 6604: @334834
     /* 334834 */ GIM_Reject,
     /* 334835 */ // Label 6577: @334835
     /* 334835 */ GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(334865), // Rule ID 853 //
     /* 334840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 334843 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 334846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334850 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 334854 */   // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 334854 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 334859 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334863 */   GIR_RootConstrainSelectedInstOperands,
     /* 334864 */   // GIR_Coverage, 853,
     /* 334864 */   GIR_Done,
     /* 334865 */ // Label 6605: @334865
     /* 334865 */ GIM_Reject,
     /* 334866 */ // Label 6578: @334866
     /* 334866 */ GIM_Try, /*On fail goto*//*Label 6606*/ GIMT_Encode4(334896), // Rule ID 859 //
     /* 334871 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 334874 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 334877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334881 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334885 */   // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 334885 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 334890 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334894 */   GIR_RootConstrainSelectedInstOperands,
     /* 334895 */   // GIR_Coverage, 859,
     /* 334895 */   GIR_Done,
     /* 334896 */ // Label 6606: @334896
     /* 334896 */ GIM_Reject,
     /* 334897 */ // Label 6579: @334897
     /* 334897 */ GIM_Try, /*On fail goto*//*Label 6607*/ GIMT_Encode4(334927), // Rule ID 855 //
     /* 334902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 334905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334912 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334916 */   // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 334916 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 334921 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 334925 */   GIR_RootConstrainSelectedInstOperands,
     /* 334926 */   // GIR_Coverage, 855,
     /* 334926 */   GIR_Done,
     /* 334927 */ // Label 6607: @334927
     /* 334927 */ GIM_Reject,
     /* 334928 */ // Label 6580: @334928
     /* 334928 */ GIM_Reject,
     /* 334929 */ // Label 69: @334929
     /* 334929 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6616*/ GIMT_Encode4(339556),
     /* 334940 */ /*GILLT_s16*//*Label 6608*/ GIMT_Encode4(334980),
     /* 334944 */ /*GILLT_s32*//*Label 6609*/ GIMT_Encode4(335421),
     /* 334948 */ /*GILLT_s64*//*Label 6610*/ GIMT_Encode4(337417), GIMT_Encode4(0),
     /* 334956 */ /*GILLT_v2s32*//*Label 6611*/ GIMT_Encode4(339401),
     /* 334960 */ /*GILLT_v2s64*//*Label 6612*/ GIMT_Encode4(339432),
     /* 334964 */ /*GILLT_v4s16*//*Label 6613*/ GIMT_Encode4(339463),
     /* 334968 */ /*GILLT_v4s32*//*Label 6614*/ GIMT_Encode4(339494), GIMT_Encode4(0),
     /* 334976 */ /*GILLT_v8s16*//*Label 6615*/ GIMT_Encode4(339525),
     /* 334980 */ // Label 6608: @334980
     /* 334980 */ GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(335083), // Rule ID 5371 //
     /* 334985 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 334988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 334991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334995 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334999 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 335003 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 335007 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 335011 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335015 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335019 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 335023 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335028 */   GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 335032 */   // MIs[1] Operand 2
     /* 335032 */   GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 335043 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 335045 */   // (sint_to_fp:{ *:[f16] } (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), i16:{ *:[Other] }))  =>  (SCVTFv1i16:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR128:{ *:[v8i16] }:$Rn, hsub:{ *:[i32] }))
     /* 335045 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335048 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335052 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335057 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335063 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335068 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 335076 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335078 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335081 */   GIR_RootConstrainSelectedInstOperands,
     /* 335082 */   // GIR_Coverage, 5371,
     /* 335082 */   GIR_EraseRootFromParent_Done,
     /* 335083 */ // Label 6617: @335083
     /* 335083 */ GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(335163), // Rule ID 2451 //
     /* 335088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 335091 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335098 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335102 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335106 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 335110 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335114 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335119 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 335123 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335125 */   // (sint_to_fp:{ *:[f16] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFHSr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 335125 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 335128 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335132 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335137 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 335143 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335148 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHSr),
     /* 335156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335158 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335161 */   GIR_RootConstrainSelectedInstOperands,
     /* 335162 */   // GIR_Coverage, 2451,
     /* 335162 */   GIR_EraseRootFromParent_Done,
     /* 335163 */ // Label 6618: @335163
     /* 335163 */ GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(335243), // Rule ID 2455 //
     /* 335168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 335171 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 335174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335178 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335182 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335186 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 335190 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335194 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335199 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 335203 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335205 */   // (sint_to_fp:{ *:[f16] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFHDr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 335205 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 335208 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335212 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335217 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 335223 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335228 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHDr),
     /* 335236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335238 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335241 */   GIR_RootConstrainSelectedInstOperands,
     /* 335242 */   // GIR_Coverage, 2455,
     /* 335242 */   GIR_EraseRootFromParent_Done,
     /* 335243 */ // Label 6619: @335243
     /* 335243 */ GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(335300), // Rule ID 5362 //
     /* 335248 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 335251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335258 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335262 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 335266 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 335270 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335272 */   // (sint_to_fp:{ *:[f16] } (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$Rn))  =>  (SCVTFv1i16:{ *:[f16] } (FCVTZSv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
     /* 335272 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335275 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1f16),
     /* 335279 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335284 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 335288 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 335290 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 335293 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335295 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335298 */   GIR_RootConstrainSelectedInstOperands,
     /* 335299 */   // GIR_Coverage, 5362,
     /* 335299 */   GIR_EraseRootFromParent_Done,
     /* 335300 */ // Label 6620: @335300
     /* 335300 */ GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(335330), // Rule ID 447 //
     /* 335305 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 335308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335315 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 335319 */   // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
     /* 335319 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWHri),
     /* 335324 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 335328 */   GIR_RootConstrainSelectedInstOperands,
     /* 335329 */   // GIR_Coverage, 447,
     /* 335329 */   GIR_Done,
     /* 335330 */ // Label 6621: @335330
     /* 335330 */ GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(335360), // Rule ID 453 //
     /* 335335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 335338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 335341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335345 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 335349 */   // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
     /* 335349 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXHri),
     /* 335354 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 335358 */   GIR_RootConstrainSelectedInstOperands,
     /* 335359 */   // GIR_Coverage, 453,
     /* 335359 */   GIR_Done,
     /* 335360 */ // Label 6622: @335360
     /* 335360 */ GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(335390), // Rule ID 495 //
     /* 335365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 335368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335375 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335379 */   // (sint_to_fp:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)  =>  (SCVTFHSr:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)
     /* 335379 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHSr),
     /* 335384 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 335388 */   GIR_RootConstrainSelectedInstOperands,
     /* 335389 */   // GIR_Coverage, 495,
     /* 335389 */   GIR_Done,
     /* 335390 */ // Label 6623: @335390
     /* 335390 */ GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(335420), // Rule ID 499 //
     /* 335395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 335398 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 335401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335409 */   // (sint_to_fp:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)  =>  (SCVTFHDr:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)
     /* 335409 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHDr),
     /* 335414 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 335418 */   GIR_RootConstrainSelectedInstOperands,
     /* 335419 */   // GIR_Coverage, 499,
     /* 335419 */   GIR_Done,
     /* 335420 */ // Label 6624: @335420
     /* 335420 */ GIM_Reject,
     /* 335421 */ // Label 6609: @335421
     /* 335421 */ GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(335659), // Rule ID 6448 //
     /* 335426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 335429 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335436 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335440 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 335444 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 335447 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 335454 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 335458 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335460 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 335467 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 335467 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 335470 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 335474 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 335484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 335489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 335494 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 335499 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 335501 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 335504 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 335508 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335513 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 335515 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 335518 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 335522 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335527 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 335530 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 335533 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 335536 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335541 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335546 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 335551 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 335554 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 335558 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335563 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 335566 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 335569 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 335571 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 335574 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335578 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335583 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 335590 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335595 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335600 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 335603 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 335607 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335612 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 335615 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 335618 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 335620 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 335623 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335627 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335632 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 335639 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335644 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 335652 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335654 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335657 */   GIR_RootConstrainSelectedInstOperands,
     /* 335658 */   // GIR_Coverage, 6448,
     /* 335658 */   GIR_EraseRootFromParent_Done,
     /* 335659 */ // Label 6625: @335659
     /* 335659 */ GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(335897), // Rule ID 6449 //
     /* 335664 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 335667 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335674 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335678 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 335682 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 335685 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 335692 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 335696 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335698 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 335705 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 335705 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 335708 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 335712 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 335722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 335727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 335732 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 335737 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 335739 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 335742 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 335746 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335751 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 335753 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 335756 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 335760 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335765 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 335768 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 335771 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 335774 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335779 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335784 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 335789 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 335792 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 335796 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335801 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 335804 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 335807 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 335809 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 335812 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335816 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335821 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 335828 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 335833 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335838 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 335841 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 335845 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335850 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 335853 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 335856 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 335858 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 335861 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335865 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335870 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 335877 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335882 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 335890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335892 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335895 */   GIR_RootConstrainSelectedInstOperands,
     /* 335896 */   // GIR_Coverage, 6449,
     /* 335896 */   GIR_EraseRootFromParent_Done,
     /* 335897 */ // Label 6626: @335897
     /* 335897 */ GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(336086), // Rule ID 6452 //
     /* 335902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 335905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 335908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 335912 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335916 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 335920 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 335923 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 335930 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 335934 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 335936 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 335943 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 335943 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 335946 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 335950 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 335960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 335965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 335970 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 335975 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 335977 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 335980 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 335984 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335989 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 335991 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 335994 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 335998 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336003 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 336006 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 336009 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 336012 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336017 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336022 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336027 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 336030 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 336034 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336039 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 336042 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 336045 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 336047 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 336050 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336054 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336059 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 336066 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336071 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 336079 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336081 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336084 */   GIR_RootConstrainSelectedInstOperands,
     /* 336085 */   // GIR_Coverage, 6452,
     /* 336085 */   GIR_EraseRootFromParent_Done,
     /* 336086 */ // Label 6627: @336086
     /* 336086 */ GIM_Try, /*On fail goto*//*Label 6628*/ GIMT_Encode4(336275), // Rule ID 6453 //
     /* 336091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 336094 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 336097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336101 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336105 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 336109 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 336112 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 336119 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 336123 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336125 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 336132 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 336132 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 336135 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 336139 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 336149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 336154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 336159 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 336164 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 336166 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 336169 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 336173 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336178 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 336180 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 336183 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 336187 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336192 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 336195 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 336198 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 336201 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336206 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336211 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336216 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 336219 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 336223 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336228 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 336231 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 336234 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 336236 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 336239 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336243 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336248 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 336255 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336260 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336265 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 336268 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336270 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336273 */   GIR_RootConstrainSelectedInstOperands,
     /* 336274 */   // GIR_Coverage, 6453,
     /* 336274 */   GIR_EraseRootFromParent_Done,
     /* 336275 */ // Label 6628: @336275
     /* 336275 */ GIM_Try, /*On fail goto*//*Label 6629*/ GIMT_Encode4(336508), // Rule ID 6450 //
     /* 336280 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 336283 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 336286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336290 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336294 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 336298 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 336301 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 336308 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 336312 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336314 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 336321 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 336321 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 336324 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 336328 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 336338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 336343 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 336348 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 336350 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 336353 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 336357 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336362 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 336364 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 336367 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 336371 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336376 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 336379 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 336382 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 336385 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336390 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336395 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 336400 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 336403 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 336407 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336412 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 336415 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 336418 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 336420 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 336423 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336427 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336432 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 336439 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336444 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336449 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 336452 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 336456 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336461 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 336464 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 336467 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 336469 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 336472 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336476 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336481 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 336488 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336493 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336498 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 336501 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336503 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336506 */   GIR_RootConstrainSelectedInstOperands,
     /* 336507 */   // GIR_Coverage, 6450,
     /* 336507 */   GIR_EraseRootFromParent_Done,
     /* 336508 */ // Label 6629: @336508
     /* 336508 */ GIM_Try, /*On fail goto*//*Label 6630*/ GIMT_Encode4(336741), // Rule ID 6451 //
     /* 336513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 336516 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 336519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336523 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336527 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 336531 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 336534 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 336541 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 336545 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336547 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 336554 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 336554 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 336557 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 336561 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 336571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 336576 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 336581 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 336583 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 336586 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 336590 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336595 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 336597 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 336600 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 336604 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336609 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 336612 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 336615 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 336618 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336623 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336628 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 336633 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 336636 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 336640 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336645 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 336648 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 336651 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 336653 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 336656 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336660 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336665 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 336672 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336677 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336682 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 336685 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 336689 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336694 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 336697 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 336700 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 336702 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 336705 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336709 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336714 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 336721 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336726 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 336734 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336736 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336739 */   GIR_RootConstrainSelectedInstOperands,
     /* 336740 */   // GIR_Coverage, 6451,
     /* 336740 */   GIR_EraseRootFromParent_Done,
     /* 336741 */ // Label 6630: @336741
     /* 336741 */ GIM_Try, /*On fail goto*//*Label 6631*/ GIMT_Encode4(336925), // Rule ID 6454 //
     /* 336746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 336749 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 336752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336756 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336760 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 336764 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 336767 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 336774 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 336778 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336780 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 336787 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 336787 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 336790 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 336794 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 336804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 336809 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 336814 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 336816 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 336819 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 336823 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336828 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 336830 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 336833 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 336837 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336842 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 336845 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 336848 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 336851 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336856 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 336861 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336866 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 336869 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 336873 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336878 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 336881 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 336884 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 336886 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 336889 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336893 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336898 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 336905 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336910 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336915 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 336918 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336920 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336923 */   GIR_RootConstrainSelectedInstOperands,
     /* 336924 */   // GIR_Coverage, 6454,
     /* 336924 */   GIR_EraseRootFromParent_Done,
     /* 336925 */ // Label 6631: @336925
     /* 336925 */ GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(337109), // Rule ID 6455 //
     /* 336930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 336933 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 336936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 336940 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336944 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 336948 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 336951 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 336958 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 336962 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336964 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 336971 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 336971 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 336974 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 336978 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 336988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 336993 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 336998 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 337000 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 337003 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 337007 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337012 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 337014 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 337017 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 337021 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337026 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 337029 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 337032 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 337035 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337040 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337045 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337050 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 337053 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 337057 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337062 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 337065 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 337068 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 337070 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 337073 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337077 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337082 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 337089 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337094 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 337102 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337104 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337107 */   GIR_RootConstrainSelectedInstOperands,
     /* 337108 */   // GIR_Coverage, 6455,
     /* 337108 */   GIR_EraseRootFromParent_Done,
     /* 337109 */ // Label 6632: @337109
     /* 337109 */ GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(337189), // Rule ID 2457 //
     /* 337114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 337117 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 337120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337124 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337128 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337132 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 337136 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337140 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337145 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 337149 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337151 */   // (sint_to_fp:{ *:[f32] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFSDr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 337151 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 337154 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337158 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337163 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 337169 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337174 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337179 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFSDr),
     /* 337182 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337184 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337187 */   GIR_RootConstrainSelectedInstOperands,
     /* 337188 */   // GIR_Coverage, 2457,
     /* 337188 */   GIR_EraseRootFromParent_Done,
     /* 337189 */ // Label 6633: @337189
     /* 337189 */ GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(337269), // Rule ID 5367 //
     /* 337194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 337197 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337204 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337208 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337212 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337216 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337220 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337225 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 337229 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337231 */   // (sint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 337231 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 337234 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337238 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337243 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 337249 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337254 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 337262 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337264 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337267 */   GIR_RootConstrainSelectedInstOperands,
     /* 337268 */   // GIR_Coverage, 5367,
     /* 337268 */   GIR_EraseRootFromParent_Done,
     /* 337269 */ // Label 6634: @337269
     /* 337269 */ GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(337326), // Rule ID 5350 //
     /* 337274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 337277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337284 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337288 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 337292 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 337296 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337298 */   // (sint_to_fp:{ *:[f32] } (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$Rn))  =>  (SCVTFv1i32:{ *:[f32] } (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 337298 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 337301 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 337305 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337310 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 337314 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 337316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 337319 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337321 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337324 */   GIR_RootConstrainSelectedInstOperands,
     /* 337325 */   // GIR_Coverage, 5350,
     /* 337325 */   GIR_EraseRootFromParent_Done,
     /* 337326 */ // Label 6635: @337326
     /* 337326 */ GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(337356), // Rule ID 449 //
     /* 337331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 337334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337341 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 337345 */   // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
     /* 337345 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWSri),
     /* 337350 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 337354 */   GIR_RootConstrainSelectedInstOperands,
     /* 337355 */   // GIR_Coverage, 449,
     /* 337355 */   GIR_Done,
     /* 337356 */ // Label 6636: @337356
     /* 337356 */ GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(337386), // Rule ID 455 //
     /* 337361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 337364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 337367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337371 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 337375 */   // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
     /* 337375 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXSri),
     /* 337380 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 337384 */   GIR_RootConstrainSelectedInstOperands,
     /* 337385 */   // GIR_Coverage, 455,
     /* 337385 */   GIR_Done,
     /* 337386 */ // Label 6637: @337386
     /* 337386 */ GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(337416), // Rule ID 501 //
     /* 337391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 337394 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 337397 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337401 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337405 */   // (sint_to_fp:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)  =>  (SCVTFSDr:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)
     /* 337405 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFSDr),
     /* 337410 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 337414 */   GIR_RootConstrainSelectedInstOperands,
     /* 337415 */   // GIR_Coverage, 501,
     /* 337415 */   GIR_Done,
     /* 337416 */ // Label 6638: @337416
     /* 337416 */ GIM_Reject,
     /* 337417 */ // Label 6610: @337417
     /* 337417 */ GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(337603), // Rule ID 6460 //
     /* 337422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 337425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337432 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337436 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 337440 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 337443 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 337447 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 337451 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337453 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 337460 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 337460 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 337463 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 337467 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 337477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 337482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 337487 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 337492 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 337494 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 337497 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 337501 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337506 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 337508 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 337511 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 337515 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337520 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 337523 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 337526 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 337529 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337534 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337539 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337544 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 337547 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 337551 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337556 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 337559 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 337562 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 337564 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 337567 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337571 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337576 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 337583 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337588 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 337596 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337598 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337601 */   GIR_RootConstrainSelectedInstOperands,
     /* 337602 */   // GIR_Coverage, 6460,
     /* 337602 */   GIR_EraseRootFromParent_Done,
     /* 337603 */ // Label 6639: @337603
     /* 337603 */ GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(337789), // Rule ID 6461 //
     /* 337608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 337611 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337614 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337618 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337622 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 337626 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 337629 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 337633 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 337637 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337639 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 337646 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 337646 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 337649 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 337653 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 337663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 337668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 337673 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 337678 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 337680 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 337683 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 337687 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337692 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 337694 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 337697 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 337701 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337706 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 337709 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 337712 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 337715 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337720 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337725 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337730 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 337733 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 337737 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337742 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 337745 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 337748 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 337750 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 337753 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337757 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337762 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 337769 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337774 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 337782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337784 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337787 */   GIR_RootConstrainSelectedInstOperands,
     /* 337788 */   // GIR_Coverage, 6461,
     /* 337788 */   GIR_EraseRootFromParent_Done,
     /* 337789 */ // Label 6640: @337789
     /* 337789 */ GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(338027), // Rule ID 6456 //
     /* 337794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 337797 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337804 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337808 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 337812 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 337815 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 337822 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 337826 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337828 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 337835 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 337835 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 337838 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 337842 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 337852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 337857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 337862 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 337867 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 337869 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 337872 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 337876 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337881 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 337883 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 337886 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 337890 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337895 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 337898 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 337901 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 337904 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337909 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337914 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337919 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 337922 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 337926 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337931 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 337934 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 337937 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 337939 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 337942 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337946 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337951 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 337958 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 337963 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337968 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 337971 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 337975 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337980 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 337983 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 337986 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 337988 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 337991 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337995 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338000 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338007 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338012 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 338020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338022 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338025 */   GIR_RootConstrainSelectedInstOperands,
     /* 338026 */   // GIR_Coverage, 6456,
     /* 338026 */   GIR_EraseRootFromParent_Done,
     /* 338027 */ // Label 6641: @338027
     /* 338027 */ GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(338265), // Rule ID 6457 //
     /* 338032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 338035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 338038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338042 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338046 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 338050 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 338053 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 338060 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 338064 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 338066 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 338073 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 338073 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 338076 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 338080 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 338090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 338095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 338100 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 338105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 338107 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 338110 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 338114 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338119 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 338121 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 338124 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 338128 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338133 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 338136 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 338139 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 338142 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338147 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338152 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 338157 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 338160 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 338164 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338169 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 338172 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 338175 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 338177 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 338180 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338184 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338189 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338196 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338201 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338206 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 338209 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 338213 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338218 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 338221 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 338224 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 338226 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 338229 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338233 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338238 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338245 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338250 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338255 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 338258 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338260 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338263 */   GIR_RootConstrainSelectedInstOperands,
     /* 338264 */   // GIR_Coverage, 6457,
     /* 338264 */   GIR_EraseRootFromParent_Done,
     /* 338265 */ // Label 6642: @338265
     /* 338265 */ GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(338446), // Rule ID 6462 //
     /* 338270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 338273 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 338276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338280 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338284 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 338288 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 338291 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 338295 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 338299 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 338301 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 338308 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 338308 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 338311 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 338315 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 338325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 338330 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 338335 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 338337 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 338340 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 338344 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338349 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 338351 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 338354 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 338358 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338363 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 338366 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 338369 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 338372 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338377 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338382 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338387 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 338390 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 338394 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338399 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 338402 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 338405 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 338407 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 338410 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338414 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338419 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338426 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338431 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 338439 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338441 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338444 */   GIR_RootConstrainSelectedInstOperands,
     /* 338445 */   // GIR_Coverage, 6462,
     /* 338445 */   GIR_EraseRootFromParent_Done,
     /* 338446 */ // Label 6643: @338446
     /* 338446 */ GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(338627), // Rule ID 6463 //
     /* 338451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 338454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 338457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338461 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338465 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 338469 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 338472 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 338476 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 338480 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 338482 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 338489 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 338489 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 338492 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 338496 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 338506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 338511 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 338516 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 338518 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 338521 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 338525 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338530 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 338532 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 338535 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 338539 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338544 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 338547 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 338550 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 338553 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338558 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338563 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338568 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 338571 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 338575 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338580 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 338583 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 338586 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 338588 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 338591 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338595 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338600 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338607 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338612 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 338620 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338622 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338625 */   GIR_RootConstrainSelectedInstOperands,
     /* 338626 */   // GIR_Coverage, 6463,
     /* 338626 */   GIR_EraseRootFromParent_Done,
     /* 338627 */ // Label 6644: @338627
     /* 338627 */ GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(338860), // Rule ID 6458 //
     /* 338632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 338635 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 338638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338642 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338646 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 338650 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 338653 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 338660 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 338664 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 338666 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 338673 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 338673 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 338676 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 338680 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 338690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 338695 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 338700 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 338702 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 338705 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 338709 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338714 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 338716 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 338719 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 338723 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338728 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 338731 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 338734 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 338737 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338742 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338747 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 338752 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 338755 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 338759 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338764 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 338767 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 338770 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 338772 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 338775 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338779 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338784 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338791 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338796 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338801 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 338804 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 338808 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338813 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 338816 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 338819 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 338821 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 338824 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338828 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338833 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 338840 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338845 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 338853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338855 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338858 */   GIR_RootConstrainSelectedInstOperands,
     /* 338859 */   // GIR_Coverage, 6458,
     /* 338859 */   GIR_EraseRootFromParent_Done,
     /* 338860 */ // Label 6645: @338860
     /* 338860 */ GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(339093), // Rule ID 6459 //
     /* 338865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 338868 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 338871 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338875 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338879 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 338883 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 338886 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 338893 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 338897 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 338899 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 338906 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 338906 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 338909 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 338913 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 338923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 338928 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 338933 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 338935 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 338938 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 338942 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338947 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 338949 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 338952 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 338956 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338961 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 338964 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 338967 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 338970 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338975 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 338980 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 338985 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 338988 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 338992 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338997 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 339000 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 339003 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 339005 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 339008 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339012 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339017 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 339024 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339029 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339034 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 339037 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 339041 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339046 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 339049 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 339052 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 339054 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 339057 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339061 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339066 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 339073 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339078 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339083 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 339086 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339088 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339091 */   GIR_RootConstrainSelectedInstOperands,
     /* 339092 */   // GIR_Coverage, 6459,
     /* 339092 */   GIR_EraseRootFromParent_Done,
     /* 339093 */ // Label 6646: @339093
     /* 339093 */ GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(339173), // Rule ID 2453 //
     /* 339098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 339101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339108 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339112 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339116 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339120 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339124 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339129 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339133 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339135 */   // (sint_to_fp:{ *:[f64] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFDSr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 339135 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339138 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339142 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339147 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 339153 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339158 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 339166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339168 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339171 */   GIR_RootConstrainSelectedInstOperands,
     /* 339172 */   // GIR_Coverage, 2453,
     /* 339172 */   GIR_EraseRootFromParent_Done,
     /* 339173 */ // Label 6647: @339173
     /* 339173 */ GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(339253), // Rule ID 5369 //
     /* 339178 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 339181 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 339184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339188 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339192 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339196 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 339200 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339204 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339209 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339213 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339215 */   // (sint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 339215 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 339218 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339222 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339227 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 339233 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339238 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 339246 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339248 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339251 */   GIR_RootConstrainSelectedInstOperands,
     /* 339252 */   // GIR_Coverage, 5369,
     /* 339252 */   GIR_EraseRootFromParent_Done,
     /* 339253 */ // Label 6648: @339253
     /* 339253 */ GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(339310), // Rule ID 5346 //
     /* 339258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 339261 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 339264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339268 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339272 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 339276 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 339280 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339282 */   // (sint_to_fp:{ *:[f64] } (fp_to_sint:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (SCVTFv1i64:{ *:[f64] } (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 339282 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 339285 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 339289 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339294 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 339298 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 339300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 339303 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339305 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339308 */   GIR_RootConstrainSelectedInstOperands,
     /* 339309 */   // GIR_Coverage, 5346,
     /* 339309 */   GIR_EraseRootFromParent_Done,
     /* 339310 */ // Label 6649: @339310
     /* 339310 */ GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(339340), // Rule ID 451 //
     /* 339315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339318 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339325 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 339329 */   // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
     /* 339329 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWDri),
     /* 339334 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339338 */   GIR_RootConstrainSelectedInstOperands,
     /* 339339 */   // GIR_Coverage, 451,
     /* 339339 */   GIR_Done,
     /* 339340 */ // Label 6650: @339340
     /* 339340 */ GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(339370), // Rule ID 457 //
     /* 339345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339348 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 339351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339355 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 339359 */   // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
     /* 339359 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXDri),
     /* 339364 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339368 */   GIR_RootConstrainSelectedInstOperands,
     /* 339369 */   // GIR_Coverage, 457,
     /* 339369 */   GIR_Done,
     /* 339370 */ // Label 6651: @339370
     /* 339370 */ GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(339400), // Rule ID 497 //
     /* 339375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 339378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339385 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339389 */   // (sint_to_fp:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)  =>  (SCVTFDSr:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)
     /* 339389 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 339394 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339398 */   GIR_RootConstrainSelectedInstOperands,
     /* 339399 */   // GIR_Coverage, 497,
     /* 339399 */   GIR_Done,
     /* 339400 */ // Label 6652: @339400
     /* 339400 */ GIM_Reject,
     /* 339401 */ // Label 6611: @339401
     /* 339401 */ GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(339431), // Rule ID 1021 //
     /* 339406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339409 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 339412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339416 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339420 */   // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)  =>  (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
     /* 339420 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f32),
     /* 339425 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339429 */   GIR_RootConstrainSelectedInstOperands,
     /* 339430 */   // GIR_Coverage, 1021,
     /* 339430 */   GIR_Done,
     /* 339431 */ // Label 6653: @339431
     /* 339431 */ GIM_Reject,
     /* 339432 */ // Label 6612: @339432
     /* 339432 */ GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(339462), // Rule ID 1025 //
     /* 339437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339440 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 339443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339447 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339451 */   // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)  =>  (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
     /* 339451 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f64),
     /* 339456 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339460 */   GIR_RootConstrainSelectedInstOperands,
     /* 339461 */   // GIR_Coverage, 1025,
     /* 339461 */   GIR_Done,
     /* 339462 */ // Label 6654: @339462
     /* 339462 */ GIM_Reject,
     /* 339463 */ // Label 6613: @339463
     /* 339463 */ GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(339493), // Rule ID 1017 //
     /* 339468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 339471 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 339474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339478 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339482 */   // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)  =>  (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
     /* 339482 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f16),
     /* 339487 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339491 */   GIR_RootConstrainSelectedInstOperands,
     /* 339492 */   // GIR_Coverage, 1017,
     /* 339492 */   GIR_Done,
     /* 339493 */ // Label 6655: @339493
     /* 339493 */ GIM_Reject,
     /* 339494 */ // Label 6614: @339494
     /* 339494 */ GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(339524), // Rule ID 1023 //
     /* 339499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339502 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339505 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339509 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339513 */   // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)  =>  (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
     /* 339513 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f32),
     /* 339518 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339522 */   GIR_RootConstrainSelectedInstOperands,
     /* 339523 */   // GIR_Coverage, 1023,
     /* 339523 */   GIR_Done,
     /* 339524 */ // Label 6656: @339524
     /* 339524 */ GIM_Reject,
     /* 339525 */ // Label 6615: @339525
     /* 339525 */ GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(339555), // Rule ID 1019 //
     /* 339530 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 339533 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 339536 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339540 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339544 */   // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)  =>  (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
     /* 339544 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8f16),
     /* 339549 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339553 */   GIR_RootConstrainSelectedInstOperands,
     /* 339554 */   // GIR_Coverage, 1019,
     /* 339554 */   GIR_Done,
     /* 339555 */ // Label 6657: @339555
     /* 339555 */ GIM_Reject,
     /* 339556 */ // Label 6616: @339556
     /* 339556 */ GIM_Reject,
     /* 339557 */ // Label 70: @339557
     /* 339557 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6666*/ GIMT_Encode4(343562),
     /* 339568 */ /*GILLT_s16*//*Label 6658*/ GIMT_Encode4(339608),
     /* 339572 */ /*GILLT_s32*//*Label 6659*/ GIMT_Encode4(340053),
     /* 339576 */ /*GILLT_s64*//*Label 6660*/ GIMT_Encode4(341461), GIMT_Encode4(0),
     /* 339584 */ /*GILLT_v2s32*//*Label 6661*/ GIMT_Encode4(343407),
     /* 339588 */ /*GILLT_v2s64*//*Label 6662*/ GIMT_Encode4(343438),
     /* 339592 */ /*GILLT_v4s16*//*Label 6663*/ GIMT_Encode4(343469),
     /* 339596 */ /*GILLT_v4s32*//*Label 6664*/ GIMT_Encode4(343500), GIMT_Encode4(0),
     /* 339604 */ /*GILLT_v8s16*//*Label 6665*/ GIMT_Encode4(343531),
     /* 339608 */ // Label 6658: @339608
     /* 339608 */ GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(339715), // Rule ID 5372 //
     /* 339613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 339616 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339623 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339627 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 339631 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339635 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 339639 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339643 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339647 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 339651 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339655 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339660 */   GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 339664 */   GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 339675 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339677 */   // (uint_to_fp:{ *:[f16] } (and:{ *:[i32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), 65535:{ *:[i32] }))  =>  (UCVTFv1i16:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR128:{ *:[v8i16] }:$Rn, hsub:{ *:[i32] }))
     /* 339677 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 339680 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339684 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339689 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 339695 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339700 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 339708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339710 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339713 */   GIR_RootConstrainSelectedInstOperands,
     /* 339714 */   // GIR_Coverage, 5372,
     /* 339714 */   GIR_EraseRootFromParent_Done,
     /* 339715 */ // Label 6667: @339715
     /* 339715 */ GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(339795), // Rule ID 4817 //
     /* 339720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 339723 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339730 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339734 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339738 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339742 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339746 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339751 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339755 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339757 */   // (uint_to_fp:{ *:[f16] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFHSr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 339757 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339760 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339764 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339769 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 339775 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339780 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHSr),
     /* 339788 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339790 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339793 */   GIR_RootConstrainSelectedInstOperands,
     /* 339794 */   // GIR_Coverage, 4817,
     /* 339794 */   GIR_EraseRootFromParent_Done,
     /* 339795 */ // Label 6668: @339795
     /* 339795 */ GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(339875), // Rule ID 4821 //
     /* 339800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 339803 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 339806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339810 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339814 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339818 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 339822 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339826 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339831 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339835 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339837 */   // (uint_to_fp:{ *:[f16] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFHDr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 339837 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 339840 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339844 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339849 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 339855 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 339860 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339865 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHDr),
     /* 339868 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339870 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339873 */   GIR_RootConstrainSelectedInstOperands,
     /* 339874 */   // GIR_Coverage, 4821,
     /* 339874 */   GIR_EraseRootFromParent_Done,
     /* 339875 */ // Label 6669: @339875
     /* 339875 */ GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(339932), // Rule ID 5366 //
     /* 339880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 339883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339890 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339894 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 339898 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 339902 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 339904 */   // (uint_to_fp:{ *:[f16] } (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$Rn))  =>  (UCVTFv1i16:{ *:[f16] } (FCVTZUv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
     /* 339904 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 339907 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1f16),
     /* 339911 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339916 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 339920 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 339922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 339925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339927 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339930 */   GIR_RootConstrainSelectedInstOperands,
     /* 339931 */   // GIR_Coverage, 5366,
     /* 339931 */   GIR_EraseRootFromParent_Done,
     /* 339932 */ // Label 6670: @339932
     /* 339932 */ GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(339962), // Rule ID 471 //
     /* 339937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 339940 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 339943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339947 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 339951 */   // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
     /* 339951 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWHri),
     /* 339956 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339960 */   GIR_RootConstrainSelectedInstOperands,
     /* 339961 */   // GIR_Coverage, 471,
     /* 339961 */   GIR_Done,
     /* 339962 */ // Label 6671: @339962
     /* 339962 */ GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(339992), // Rule ID 477 //
     /* 339967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 339970 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 339973 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 339977 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 339981 */   // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
     /* 339981 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXHri),
     /* 339986 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 339990 */   GIR_RootConstrainSelectedInstOperands,
     /* 339991 */   // GIR_Coverage, 477,
     /* 339991 */   GIR_Done,
     /* 339992 */ // Label 6672: @339992
     /* 339992 */ GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(340022), // Rule ID 503 //
     /* 339997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 340000 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 340007 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340011 */   // (uint_to_fp:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)  =>  (UCVTFHSr:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)
     /* 340011 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHSr),
     /* 340016 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 340020 */   GIR_RootConstrainSelectedInstOperands,
     /* 340021 */   // GIR_Coverage, 503,
     /* 340021 */   GIR_Done,
     /* 340022 */ // Label 6673: @340022
     /* 340022 */ GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(340052), // Rule ID 507 //
     /* 340027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 340030 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 340033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 340037 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 340041 */   // (uint_to_fp:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)  =>  (UCVTFHDr:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)
     /* 340041 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHDr),
     /* 340046 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 340050 */   GIR_RootConstrainSelectedInstOperands,
     /* 340051 */   // GIR_Coverage, 507,
     /* 340051 */   GIR_Done,
     /* 340052 */ // Label 6674: @340052
     /* 340052 */ GIM_Reject,
     /* 340053 */ // Label 6659: @340053
     /* 340053 */ GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(340193), // Rule ID 5373 //
     /* 340058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340061 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340068 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340072 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340076 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340079 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 340086 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340090 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340092 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 340099 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 340099 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 340102 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 340106 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 340121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 340126 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340131 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340133 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340136 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340140 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340145 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340147 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340150 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340154 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340159 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340162 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340165 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 340168 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340173 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340178 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 340183 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340186 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340188 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340191 */   GIR_RootConstrainSelectedInstOperands,
     /* 340192 */   // GIR_Coverage, 5373,
     /* 340192 */   GIR_EraseRootFromParent_Done,
     /* 340193 */ // Label 6675: @340193
     /* 340193 */ GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(340333), // Rule ID 5374 //
     /* 340198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340208 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340212 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340216 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340219 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 340226 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340230 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340232 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 340239 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 340239 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 340242 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 340246 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 340261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 340266 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340271 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340273 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340276 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340280 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340285 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340287 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340290 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340294 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340299 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340302 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340305 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 340308 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340313 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340318 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 340323 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340326 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340328 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340331 */   GIR_RootConstrainSelectedInstOperands,
     /* 340332 */   // GIR_Coverage, 5374,
     /* 340332 */   GIR_EraseRootFromParent_Done,
     /* 340333 */ // Label 6676: @340333
     /* 340333 */ GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(340473), // Rule ID 5377 //
     /* 340338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340341 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340348 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340352 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340356 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340359 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 340366 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340370 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340372 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 340379 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 340379 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 340382 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 340386 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 340401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 340406 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340411 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340413 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340416 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340420 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340425 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340427 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340430 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340434 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340439 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340442 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340445 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 340448 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340453 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340458 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 340463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340468 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340471 */   GIR_RootConstrainSelectedInstOperands,
     /* 340472 */   // GIR_Coverage, 5377,
     /* 340472 */   GIR_EraseRootFromParent_Done,
     /* 340473 */ // Label 6677: @340473
     /* 340473 */ GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(340613), // Rule ID 5378 //
     /* 340478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340481 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340488 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340492 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340496 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340499 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 340506 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340510 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340512 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 340519 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 340519 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 340522 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 340526 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 340541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 340546 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340551 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340553 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340556 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340560 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340565 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340567 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340570 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340574 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340579 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340582 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340585 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 340588 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340593 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340598 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 340603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340608 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340611 */   GIR_RootConstrainSelectedInstOperands,
     /* 340612 */   // GIR_Coverage, 5378,
     /* 340612 */   GIR_EraseRootFromParent_Done,
     /* 340613 */ // Label 6678: @340613
     /* 340613 */ GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(340748), // Rule ID 5375 //
     /* 340618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340621 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340628 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340632 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340636 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340639 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 340646 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340650 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340652 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 340659 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
     /* 340659 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 340662 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 340666 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 340681 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340686 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340688 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340691 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340695 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340700 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340702 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340705 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340709 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340714 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340717 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340720 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 340723 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340728 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340733 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 340738 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340741 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340743 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340746 */   GIR_RootConstrainSelectedInstOperands,
     /* 340747 */   // GIR_Coverage, 5375,
     /* 340747 */   GIR_EraseRootFromParent_Done,
     /* 340748 */ // Label 6679: @340748
     /* 340748 */ GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(340883), // Rule ID 5376 //
     /* 340753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340756 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340763 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340767 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340771 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340774 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 340781 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340785 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340787 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 340794 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
     /* 340794 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 340797 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 340801 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 340816 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340821 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340823 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340826 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340830 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340835 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340837 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340840 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340844 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340849 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340852 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340855 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 340858 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340863 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340868 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 340873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 340876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340878 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340881 */   GIR_RootConstrainSelectedInstOperands,
     /* 340882 */   // GIR_Coverage, 5376,
     /* 340882 */   GIR_EraseRootFromParent_Done,
     /* 340883 */ // Label 6680: @340883
     /* 340883 */ GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(341018), // Rule ID 5379 //
     /* 340888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 340891 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 340894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340898 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340902 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 340906 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 340909 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 340916 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 340920 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340922 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 340929 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
     /* 340929 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 340932 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 340936 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 340946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 340951 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 340956 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 340958 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 340961 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 340965 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340970 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 340972 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340975 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 340979 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340984 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 340987 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 340990 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 340993 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340998 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341003 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 341008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 341011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341013 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341016 */   GIR_RootConstrainSelectedInstOperands,
     /* 341017 */   // GIR_Coverage, 5379,
     /* 341017 */   GIR_EraseRootFromParent_Done,
     /* 341018 */ // Label 6681: @341018
     /* 341018 */ GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(341153), // Rule ID 5380 //
     /* 341023 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341026 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341029 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341033 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341037 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 341041 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 341044 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 341051 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 341055 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341057 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 341064 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
     /* 341064 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 341067 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 341071 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 341081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 341086 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 341091 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 341093 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 341096 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 341100 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 341107 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 341110 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 341114 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341119 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 341122 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 341125 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 341128 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341133 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341138 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 341143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 341146 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341148 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341151 */   GIR_RootConstrainSelectedInstOperands,
     /* 341152 */   // GIR_Coverage, 5380,
     /* 341152 */   GIR_EraseRootFromParent_Done,
     /* 341153 */ // Label 6682: @341153
     /* 341153 */ GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(341233), // Rule ID 4823 //
     /* 341158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 341161 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 341164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341168 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341172 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341176 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341180 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341184 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341189 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 341193 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341195 */   // (uint_to_fp:{ *:[f32] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFSDr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 341195 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341198 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341202 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341207 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341213 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341218 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFSDr),
     /* 341226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341228 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341231 */   GIR_RootConstrainSelectedInstOperands,
     /* 341232 */   // GIR_Coverage, 4823,
     /* 341232 */   GIR_EraseRootFromParent_Done,
     /* 341233 */ // Label 6683: @341233
     /* 341233 */ GIM_Try, /*On fail goto*//*Label 6684*/ GIMT_Encode4(341313), // Rule ID 5368 //
     /* 341238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341241 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341248 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341252 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341256 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 341260 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341264 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341269 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 341273 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341275 */   // (uint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 341275 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 341278 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341282 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341287 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 341293 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341298 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 341306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341308 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341311 */   GIR_RootConstrainSelectedInstOperands,
     /* 341312 */   // GIR_Coverage, 5368,
     /* 341312 */   GIR_EraseRootFromParent_Done,
     /* 341313 */ // Label 6684: @341313
     /* 341313 */ GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(341370), // Rule ID 5358 //
     /* 341318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341321 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341328 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341332 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 341336 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 341340 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341342 */   // (uint_to_fp:{ *:[f32] } (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$Rn))  =>  (UCVTFv1i32:{ *:[f32] } (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 341342 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 341345 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 341349 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341354 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 341358 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 341360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 341363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341365 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341368 */   GIR_RootConstrainSelectedInstOperands,
     /* 341369 */   // GIR_Coverage, 5358,
     /* 341369 */   GIR_EraseRootFromParent_Done,
     /* 341370 */ // Label 6685: @341370
     /* 341370 */ GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(341400), // Rule ID 473 //
     /* 341375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 341378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341385 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 341389 */   // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
     /* 341389 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWSri),
     /* 341394 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 341398 */   GIR_RootConstrainSelectedInstOperands,
     /* 341399 */   // GIR_Coverage, 473,
     /* 341399 */   GIR_Done,
     /* 341400 */ // Label 6686: @341400
     /* 341400 */ GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(341430), // Rule ID 479 //
     /* 341405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 341408 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 341411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341415 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 341419 */   // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
     /* 341419 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXSri),
     /* 341424 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 341428 */   GIR_RootConstrainSelectedInstOperands,
     /* 341429 */   // GIR_Coverage, 479,
     /* 341429 */   GIR_Done,
     /* 341430 */ // Label 6687: @341430
     /* 341430 */ GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(341460), // Rule ID 509 //
     /* 341435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 341438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 341441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341445 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341449 */   // (uint_to_fp:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)  =>  (UCVTFSDr:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)
     /* 341449 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFSDr),
     /* 341454 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 341458 */   GIR_RootConstrainSelectedInstOperands,
     /* 341459 */   // GIR_Coverage, 509,
     /* 341459 */   GIR_Done,
     /* 341460 */ // Label 6688: @341460
     /* 341460 */ GIM_Reject,
     /* 341461 */ // Label 6660: @341461
     /* 341461 */ GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(341598), // Rule ID 5389 //
     /* 341466 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341476 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341480 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 341484 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 341487 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 341491 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 341495 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341497 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 341504 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
     /* 341504 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 341507 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 341511 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 341521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 341526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 341531 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 341536 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 341538 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341541 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 341545 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341550 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 341552 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341555 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 341559 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341564 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 341567 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 341570 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 341573 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341578 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341583 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 341591 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341593 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341596 */   GIR_RootConstrainSelectedInstOperands,
     /* 341597 */   // GIR_Coverage, 5389,
     /* 341597 */   GIR_EraseRootFromParent_Done,
     /* 341598 */ // Label 6689: @341598
     /* 341598 */ GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(341735), // Rule ID 5390 //
     /* 341603 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341606 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341613 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341617 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 341621 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 341624 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 341628 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 341632 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341634 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 341641 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
     /* 341641 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 341644 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 341648 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 341658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 341663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 341668 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 341673 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 341675 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341678 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 341682 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341687 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 341689 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341692 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 341696 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341701 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 341704 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 341707 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 341710 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341715 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341720 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 341725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 341728 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341730 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341733 */   GIR_RootConstrainSelectedInstOperands,
     /* 341734 */   // GIR_Coverage, 5390,
     /* 341734 */   GIR_EraseRootFromParent_Done,
     /* 341735 */ // Label 6690: @341735
     /* 341735 */ GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(341875), // Rule ID 5381 //
     /* 341740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341750 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341754 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 341758 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 341761 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 341768 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 341772 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341774 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 341781 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 341781 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 341784 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 341788 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 341798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 341803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 341808 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 341813 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 341815 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341818 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 341822 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341827 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 341829 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341832 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 341836 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341841 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 341844 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 341847 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 341850 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341855 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341860 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 341865 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 341868 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341870 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341873 */   GIR_RootConstrainSelectedInstOperands,
     /* 341874 */   // GIR_Coverage, 5381,
     /* 341874 */   GIR_EraseRootFromParent_Done,
     /* 341875 */ // Label 6691: @341875
     /* 341875 */ GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(342015), // Rule ID 5382 //
     /* 341880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 341883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 341886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341890 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341894 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 341898 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 341901 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 341908 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 341912 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 341914 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 341921 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 341921 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 341924 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 341928 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 341938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 341943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 341948 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 341953 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 341955 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341958 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 341962 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341967 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 341969 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341972 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 341976 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341981 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 341984 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 341987 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 341990 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341995 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342000 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 342005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342010 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342013 */   GIR_RootConstrainSelectedInstOperands,
     /* 342014 */   // GIR_Coverage, 5382,
     /* 342014 */   GIR_EraseRootFromParent_Done,
     /* 342015 */ // Label 6692: @342015
     /* 342015 */ GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(342155), // Rule ID 5385 //
     /* 342020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342023 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342030 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342034 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342038 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342041 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 342048 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342052 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342054 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 342061 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 342061 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 342064 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 342068 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 342083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 342088 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342093 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342095 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342098 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342102 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342107 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342109 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342112 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342116 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342121 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342124 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342127 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 342130 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342135 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342140 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 342145 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342148 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342150 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342153 */   GIR_RootConstrainSelectedInstOperands,
     /* 342154 */   // GIR_Coverage, 5385,
     /* 342154 */   GIR_EraseRootFromParent_Done,
     /* 342155 */ // Label 6693: @342155
     /* 342155 */ GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(342295), // Rule ID 5386 //
     /* 342160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342170 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342174 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342178 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342181 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 342188 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342192 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342194 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 342201 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 342201 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 342204 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 342208 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 342223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 342228 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342233 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342235 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342238 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342242 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342247 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342249 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342252 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342256 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342261 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342264 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342267 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 342270 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342275 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342280 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 342285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342288 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342290 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342293 */   GIR_RootConstrainSelectedInstOperands,
     /* 342294 */   // GIR_Coverage, 5386,
     /* 342294 */   GIR_EraseRootFromParent_Done,
     /* 342295 */ // Label 6694: @342295
     /* 342295 */ GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(342427), // Rule ID 5391 //
     /* 342300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342310 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342314 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 342318 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342321 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 342325 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342329 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342331 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 342338 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }))
     /* 342338 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 342341 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 342345 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 342360 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342365 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342367 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342370 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342374 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342379 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342381 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342384 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342388 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342393 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342396 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342399 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 342402 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342407 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342412 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 342417 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342420 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342422 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342425 */   GIR_RootConstrainSelectedInstOperands,
     /* 342426 */   // GIR_Coverage, 5391,
     /* 342426 */   GIR_EraseRootFromParent_Done,
     /* 342427 */ // Label 6695: @342427
     /* 342427 */ GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(342559), // Rule ID 5392 //
     /* 342432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342435 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342442 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342446 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 342450 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342453 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 342457 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342461 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342463 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 342470 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }))
     /* 342470 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 342473 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 342477 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 342492 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342497 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342499 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342502 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342506 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342511 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342513 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342516 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342520 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342525 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342528 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342531 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 342534 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342539 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342544 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 342549 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342552 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342554 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342557 */   GIR_RootConstrainSelectedInstOperands,
     /* 342558 */   // GIR_Coverage, 5392,
     /* 342558 */   GIR_EraseRootFromParent_Done,
     /* 342559 */ // Label 6696: @342559
     /* 342559 */ GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(342694), // Rule ID 5383 //
     /* 342564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342574 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342578 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342582 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342585 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 342592 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342596 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342598 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 342605 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
     /* 342605 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 342608 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 342612 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 342627 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342632 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342634 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342637 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342641 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342646 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342648 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342651 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342655 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342660 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342663 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342666 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 342669 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342674 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342679 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 342684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342687 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342689 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342692 */   GIR_RootConstrainSelectedInstOperands,
     /* 342693 */   // GIR_Coverage, 5383,
     /* 342693 */   GIR_EraseRootFromParent_Done,
     /* 342694 */ // Label 6697: @342694
     /* 342694 */ GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(342829), // Rule ID 5384 //
     /* 342699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342709 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342713 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342717 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342720 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 342727 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342731 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342733 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 342740 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
     /* 342740 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 342743 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 342747 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 342762 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342767 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342769 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342772 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342776 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342781 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342783 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342786 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342790 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342795 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342798 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342801 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 342804 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342809 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342814 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 342819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342824 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342827 */   GIR_RootConstrainSelectedInstOperands,
     /* 342828 */   // GIR_Coverage, 5384,
     /* 342828 */   GIR_EraseRootFromParent_Done,
     /* 342829 */ // Label 6698: @342829
     /* 342829 */ GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(342964), // Rule ID 5387 //
     /* 342834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342837 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342844 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342848 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342852 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342855 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 342862 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 342866 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 342868 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 342875 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
     /* 342875 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 342878 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 342882 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 342892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 342897 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 342902 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 342904 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 342907 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 342911 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342916 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 342918 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342921 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 342925 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342930 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 342933 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 342936 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 342939 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342944 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342949 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 342954 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 342957 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342959 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342962 */   GIR_RootConstrainSelectedInstOperands,
     /* 342963 */   // GIR_Coverage, 5387,
     /* 342963 */   GIR_EraseRootFromParent_Done,
     /* 342964 */ // Label 6699: @342964
     /* 342964 */ GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(343099), // Rule ID 5388 //
     /* 342969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 342972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 342975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342979 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342983 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 342987 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 342990 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 342997 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 343001 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343003 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 343010 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
     /* 343010 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 343013 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 343017 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 343027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 343032 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 343037 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 343039 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 343042 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 343046 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343051 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 343053 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 343056 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 343060 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343065 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 343068 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 343071 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 343074 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343079 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343084 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 343089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 343092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343094 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343097 */   GIR_RootConstrainSelectedInstOperands,
     /* 343098 */   // GIR_Coverage, 5388,
     /* 343098 */   GIR_EraseRootFromParent_Done,
     /* 343099 */ // Label 6700: @343099
     /* 343099 */ GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(343179), // Rule ID 4819 //
     /* 343104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 343107 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343114 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343118 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343122 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 343126 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343130 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343135 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 343139 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343141 */   // (uint_to_fp:{ *:[f64] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFDSr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 343141 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 343144 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 343148 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343153 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 343159 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 343164 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 343172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343174 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343177 */   GIR_RootConstrainSelectedInstOperands,
     /* 343178 */   // GIR_Coverage, 4819,
     /* 343178 */   GIR_EraseRootFromParent_Done,
     /* 343179 */ // Label 6701: @343179
     /* 343179 */ GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(343259), // Rule ID 5370 //
     /* 343184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 343187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343194 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343198 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343202 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343206 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343210 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343215 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 343219 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343221 */   // (uint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 343221 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 343224 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 343228 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343233 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 343239 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343244 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 343252 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343254 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343257 */   GIR_RootConstrainSelectedInstOperands,
     /* 343258 */   // GIR_Coverage, 5370,
     /* 343258 */   GIR_EraseRootFromParent_Done,
     /* 343259 */ // Label 6702: @343259
     /* 343259 */ GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(343316), // Rule ID 5354 //
     /* 343264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 343267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343274 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343278 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 343282 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343286 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343288 */   // (uint_to_fp:{ *:[f64] } (fp_to_uint:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (UCVTFv1i64:{ *:[f64] } (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 343288 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 343291 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 343295 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343300 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343304 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 343306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 343309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343311 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343314 */   GIR_RootConstrainSelectedInstOperands,
     /* 343315 */   // GIR_Coverage, 5354,
     /* 343315 */   GIR_EraseRootFromParent_Done,
     /* 343316 */ // Label 6703: @343316
     /* 343316 */ GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(343346), // Rule ID 475 //
     /* 343321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343331 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343335 */   // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
     /* 343335 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWDri),
     /* 343340 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343344 */   GIR_RootConstrainSelectedInstOperands,
     /* 343345 */   // GIR_Coverage, 475,
     /* 343345 */   GIR_Done,
     /* 343346 */ // Label 6704: @343346
     /* 343346 */ GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(343376), // Rule ID 481 //
     /* 343351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343361 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 343365 */   // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
     /* 343365 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXDri),
     /* 343370 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343374 */   GIR_RootConstrainSelectedInstOperands,
     /* 343375 */   // GIR_Coverage, 481,
     /* 343375 */   GIR_Done,
     /* 343376 */ // Label 6705: @343376
     /* 343376 */ GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(343406), // Rule ID 505 //
     /* 343381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 343384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343391 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 343395 */   // (uint_to_fp:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)  =>  (UCVTFDSr:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)
     /* 343395 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 343400 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343404 */   GIR_RootConstrainSelectedInstOperands,
     /* 343405 */   // GIR_Coverage, 505,
     /* 343405 */   GIR_Done,
     /* 343406 */ // Label 6706: @343406
     /* 343406 */ GIM_Reject,
     /* 343407 */ // Label 6661: @343407
     /* 343407 */ GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(343437), // Rule ID 1082 //
     /* 343412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343415 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 343418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343422 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343426 */   // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)  =>  (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
     /* 343426 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f32),
     /* 343431 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343435 */   GIR_RootConstrainSelectedInstOperands,
     /* 343436 */   // GIR_Coverage, 1082,
     /* 343436 */   GIR_Done,
     /* 343437 */ // Label 6707: @343437
     /* 343437 */ GIM_Reject,
     /* 343438 */ // Label 6662: @343438
     /* 343438 */ GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(343468), // Rule ID 1086 //
     /* 343443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343446 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343449 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343453 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343457 */   // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)  =>  (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
     /* 343457 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f64),
     /* 343462 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343466 */   GIR_RootConstrainSelectedInstOperands,
     /* 343467 */   // GIR_Coverage, 1086,
     /* 343467 */   GIR_Done,
     /* 343468 */ // Label 6708: @343468
     /* 343468 */ GIM_Reject,
     /* 343469 */ // Label 6663: @343469
     /* 343469 */ GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(343499), // Rule ID 1078 //
     /* 343474 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 343477 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 343480 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343484 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343488 */   // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)  =>  (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
     /* 343488 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f16),
     /* 343493 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343497 */   GIR_RootConstrainSelectedInstOperands,
     /* 343498 */   // GIR_Coverage, 1078,
     /* 343498 */   GIR_Done,
     /* 343499 */ // Label 6709: @343499
     /* 343499 */ GIM_Reject,
     /* 343500 */ // Label 6664: @343500
     /* 343500 */ GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(343530), // Rule ID 1084 //
     /* 343505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343508 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 343511 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343515 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343519 */   // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)  =>  (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
     /* 343519 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f32),
     /* 343524 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343528 */   GIR_RootConstrainSelectedInstOperands,
     /* 343529 */   // GIR_Coverage, 1084,
     /* 343529 */   GIR_Done,
     /* 343530 */ // Label 6710: @343530
     /* 343530 */ GIM_Reject,
     /* 343531 */ // Label 6665: @343531
     /* 343531 */ GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(343561), // Rule ID 1080 //
     /* 343536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 343539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 343542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343546 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343550 */   // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)  =>  (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
     /* 343550 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8f16),
     /* 343555 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343559 */   GIR_RootConstrainSelectedInstOperands,
     /* 343560 */   // GIR_Coverage, 1080,
     /* 343560 */   GIR_Done,
     /* 343561 */ // Label 6711: @343561
     /* 343561 */ GIM_Reject,
     /* 343562 */ // Label 6666: @343562
     /* 343562 */ GIM_Reject,
     /* 343563 */ // Label 71: @343563
     /* 343563 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6719*/ GIMT_Encode4(343882),
     /* 343574 */ /*GILLT_s32*//*Label 6712*/ GIMT_Encode4(343610),
     /* 343578 */ /*GILLT_s64*//*Label 6713*/ GIMT_Encode4(343683), GIMT_Encode4(0),
     /* 343586 */ /*GILLT_v2s32*//*Label 6714*/ GIMT_Encode4(343756),
     /* 343590 */ /*GILLT_v2s64*//*Label 6715*/ GIMT_Encode4(343780),
     /* 343594 */ /*GILLT_v4s16*//*Label 6716*/ GIMT_Encode4(343804),
     /* 343598 */ /*GILLT_v4s32*//*Label 6717*/ GIMT_Encode4(343831), GIMT_Encode4(0),
     /* 343606 */ /*GILLT_v8s16*//*Label 6718*/ GIMT_Encode4(343855),
     /* 343610 */ // Label 6712: @343610
     /* 343610 */ GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(343636), // Rule ID 4652 //
     /* 343615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 343618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 343621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343625 */   // (fp_to_sint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 343625 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 343630 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343634 */   GIR_RootConstrainSelectedInstOperands,
     /* 343635 */   // GIR_Coverage, 4652,
     /* 343635 */   GIR_Done,
     /* 343636 */ // Label 6720: @343636
     /* 343636 */ GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(343659), // Rule ID 4654 //
     /* 343641 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343648 */   // (fp_to_sint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 343648 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 343653 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343657 */   GIR_RootConstrainSelectedInstOperands,
     /* 343658 */   // GIR_Coverage, 4654,
     /* 343658 */   GIR_Done,
     /* 343659 */ // Label 6721: @343659
     /* 343659 */ GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(343682), // Rule ID 4656 //
     /* 343664 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343671 */   // (fp_to_sint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 343671 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 343676 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343680 */   GIR_RootConstrainSelectedInstOperands,
     /* 343681 */   // GIR_Coverage, 4656,
     /* 343681 */   GIR_Done,
     /* 343682 */ // Label 6722: @343682
     /* 343682 */ GIM_Reject,
     /* 343683 */ // Label 6713: @343683
     /* 343683 */ GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(343709), // Rule ID 4653 //
     /* 343688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 343691 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 343694 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 343698 */   // (fp_to_sint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 343698 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 343703 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343707 */   GIR_RootConstrainSelectedInstOperands,
     /* 343708 */   // GIR_Coverage, 4653,
     /* 343708 */   GIR_Done,
     /* 343709 */ // Label 6723: @343709
     /* 343709 */ GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(343732), // Rule ID 4655 //
     /* 343714 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 343721 */   // (fp_to_sint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 343721 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 343726 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343730 */   GIR_RootConstrainSelectedInstOperands,
     /* 343731 */   // GIR_Coverage, 4655,
     /* 343731 */   GIR_Done,
     /* 343732 */ // Label 6724: @343732
     /* 343732 */ GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(343755), // Rule ID 4657 //
     /* 343737 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 343744 */   // (fp_to_sint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 343744 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 343749 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343753 */   GIR_RootConstrainSelectedInstOperands,
     /* 343754 */   // GIR_Coverage, 4657,
     /* 343754 */   GIR_Done,
     /* 343755 */ // Label 6725: @343755
     /* 343755 */ GIM_Reject,
     /* 343756 */ // Label 6714: @343756
     /* 343756 */ GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(343779), // Rule ID 4993 //
     /* 343761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 343764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343768 */   // (fp_to_sint_sat_gi:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)
     /* 343768 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 343773 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343777 */   GIR_RootConstrainSelectedInstOperands,
     /* 343778 */   // GIR_Coverage, 4993,
     /* 343778 */   GIR_Done,
     /* 343779 */ // Label 6726: @343779
     /* 343779 */ GIM_Reject,
     /* 343780 */ // Label 6715: @343780
     /* 343780 */ GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(343803), // Rule ID 4995 //
     /* 343785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343792 */   // (fp_to_sint_sat_gi:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)
     /* 343792 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 343797 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343801 */   GIR_RootConstrainSelectedInstOperands,
     /* 343802 */   // GIR_Coverage, 4995,
     /* 343802 */   GIR_Done,
     /* 343803 */ // Label 6727: @343803
     /* 343803 */ GIM_Reject,
     /* 343804 */ // Label 6716: @343804
     /* 343804 */ GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(343830), // Rule ID 4988 //
     /* 343809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 343812 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 343815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343819 */   // (fp_to_sint_sat_gi:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)
     /* 343819 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 343824 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343828 */   GIR_RootConstrainSelectedInstOperands,
     /* 343829 */   // GIR_Coverage, 4988,
     /* 343829 */   GIR_Done,
     /* 343830 */ // Label 6728: @343830
     /* 343830 */ GIM_Reject,
     /* 343831 */ // Label 6717: @343831
     /* 343831 */ GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(343854), // Rule ID 4994 //
     /* 343836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 343839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343843 */   // (fp_to_sint_sat_gi:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)
     /* 343843 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 343848 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343852 */   GIR_RootConstrainSelectedInstOperands,
     /* 343853 */   // GIR_Coverage, 4994,
     /* 343853 */   GIR_Done,
     /* 343854 */ // Label 6729: @343854
     /* 343854 */ GIM_Reject,
     /* 343855 */ // Label 6718: @343855
     /* 343855 */ GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(343881), // Rule ID 4989 //
     /* 343860 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 343863 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 343866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343870 */   // (fp_to_sint_sat_gi:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)
     /* 343870 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 343875 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343879 */   GIR_RootConstrainSelectedInstOperands,
     /* 343880 */   // GIR_Coverage, 4989,
     /* 343880 */   GIR_Done,
     /* 343881 */ // Label 6730: @343881
     /* 343881 */ GIM_Reject,
     /* 343882 */ // Label 6719: @343882
     /* 343882 */ GIM_Reject,
     /* 343883 */ // Label 72: @343883
     /* 343883 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6738*/ GIMT_Encode4(344202),
     /* 343894 */ /*GILLT_s32*//*Label 6731*/ GIMT_Encode4(343930),
     /* 343898 */ /*GILLT_s64*//*Label 6732*/ GIMT_Encode4(344003), GIMT_Encode4(0),
     /* 343906 */ /*GILLT_v2s32*//*Label 6733*/ GIMT_Encode4(344076),
     /* 343910 */ /*GILLT_v2s64*//*Label 6734*/ GIMT_Encode4(344100),
     /* 343914 */ /*GILLT_v4s16*//*Label 6735*/ GIMT_Encode4(344124),
     /* 343918 */ /*GILLT_v4s32*//*Label 6736*/ GIMT_Encode4(344151), GIMT_Encode4(0),
     /* 343926 */ /*GILLT_v8s16*//*Label 6737*/ GIMT_Encode4(344175),
     /* 343930 */ // Label 6731: @343930
     /* 343930 */ GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(343956), // Rule ID 4676 //
     /* 343935 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 343938 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 343941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343945 */   // (fp_to_uint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 343945 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 343950 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343954 */   GIR_RootConstrainSelectedInstOperands,
     /* 343955 */   // GIR_Coverage, 4676,
     /* 343955 */   GIR_Done,
     /* 343956 */ // Label 6739: @343956
     /* 343956 */ GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(343979), // Rule ID 4678 //
     /* 343961 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 343964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343968 */   // (fp_to_uint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 343968 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 343973 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343977 */   GIR_RootConstrainSelectedInstOperands,
     /* 343978 */   // GIR_Coverage, 4678,
     /* 343978 */   GIR_Done,
     /* 343979 */ // Label 6740: @343979
     /* 343979 */ GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(344002), // Rule ID 4680 //
     /* 343984 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 343987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 343991 */   // (fp_to_uint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 343991 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 343996 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344000 */   GIR_RootConstrainSelectedInstOperands,
     /* 344001 */   // GIR_Coverage, 4680,
     /* 344001 */   GIR_Done,
     /* 344002 */ // Label 6741: @344002
     /* 344002 */ GIM_Reject,
     /* 344003 */ // Label 6732: @344003
     /* 344003 */ GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(344029), // Rule ID 4677 //
     /* 344008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 344011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 344014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 344018 */   // (fp_to_uint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 344018 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 344023 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344027 */   GIR_RootConstrainSelectedInstOperands,
     /* 344028 */   // GIR_Coverage, 4677,
     /* 344028 */   GIR_Done,
     /* 344029 */ // Label 6742: @344029
     /* 344029 */ GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(344052), // Rule ID 4679 //
     /* 344034 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 344037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 344041 */   // (fp_to_uint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 344041 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 344046 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344050 */   GIR_RootConstrainSelectedInstOperands,
     /* 344051 */   // GIR_Coverage, 4679,
     /* 344051 */   GIR_Done,
     /* 344052 */ // Label 6743: @344052
     /* 344052 */ GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(344075), // Rule ID 4681 //
     /* 344057 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 344060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 344064 */   // (fp_to_uint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 344064 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 344069 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344073 */   GIR_RootConstrainSelectedInstOperands,
     /* 344074 */   // GIR_Coverage, 4681,
     /* 344074 */   GIR_Done,
     /* 344075 */ // Label 6744: @344075
     /* 344075 */ GIM_Reject,
     /* 344076 */ // Label 6733: @344076
     /* 344076 */ GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(344099), // Rule ID 5003 //
     /* 344081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344088 */   // (fp_to_uint_sat_gi:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)
     /* 344088 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 344093 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344097 */   GIR_RootConstrainSelectedInstOperands,
     /* 344098 */   // GIR_Coverage, 5003,
     /* 344098 */   GIR_Done,
     /* 344099 */ // Label 6745: @344099
     /* 344099 */ GIM_Reject,
     /* 344100 */ // Label 6734: @344100
     /* 344100 */ GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(344123), // Rule ID 5005 //
     /* 344105 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 344108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344112 */   // (fp_to_uint_sat_gi:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)
     /* 344112 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 344117 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344121 */   GIR_RootConstrainSelectedInstOperands,
     /* 344122 */   // GIR_Coverage, 5005,
     /* 344122 */   GIR_Done,
     /* 344123 */ // Label 6746: @344123
     /* 344123 */ GIM_Reject,
     /* 344124 */ // Label 6735: @344124
     /* 344124 */ GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(344150), // Rule ID 4998 //
     /* 344129 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 344132 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 344135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344139 */   // (fp_to_uint_sat_gi:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)
     /* 344139 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 344144 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344148 */   GIR_RootConstrainSelectedInstOperands,
     /* 344149 */   // GIR_Coverage, 4998,
     /* 344149 */   GIR_Done,
     /* 344150 */ // Label 6747: @344150
     /* 344150 */ GIM_Reject,
     /* 344151 */ // Label 6736: @344151
     /* 344151 */ GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(344174), // Rule ID 5004 //
     /* 344156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344163 */   // (fp_to_uint_sat_gi:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)
     /* 344163 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 344168 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344172 */   GIR_RootConstrainSelectedInstOperands,
     /* 344173 */   // GIR_Coverage, 5004,
     /* 344173 */   GIR_Done,
     /* 344174 */ // Label 6748: @344174
     /* 344174 */ GIM_Reject,
     /* 344175 */ // Label 6737: @344175
     /* 344175 */ GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(344201), // Rule ID 4999 //
     /* 344180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 344183 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 344186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344190 */   // (fp_to_uint_sat_gi:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)
     /* 344190 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 344195 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 344199 */   GIR_RootConstrainSelectedInstOperands,
     /* 344200 */   // GIR_Coverage, 4999,
     /* 344200 */   GIR_Done,
     /* 344201 */ // Label 6749: @344201
     /* 344201 */ GIM_Reject,
     /* 344202 */ // Label 6738: @344202
     /* 344202 */ GIM_Reject,
     /* 344203 */ // Label 73: @344203
     /* 344203 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6758*/ GIMT_Encode4(345059),
     /* 344214 */ /*GILLT_s16*//*Label 6750*/ GIMT_Encode4(344254),
     /* 344218 */ /*GILLT_s32*//*Label 6751*/ GIMT_Encode4(344473),
     /* 344222 */ /*GILLT_s64*//*Label 6752*/ GIMT_Encode4(344547), GIMT_Encode4(0),
     /* 344230 */ /*GILLT_v2s32*//*Label 6753*/ GIMT_Encode4(344621),
     /* 344234 */ /*GILLT_v2s64*//*Label 6754*/ GIMT_Encode4(344695),
     /* 344238 */ /*GILLT_v4s16*//*Label 6755*/ GIMT_Encode4(344769),
     /* 344242 */ /*GILLT_v4s32*//*Label 6756*/ GIMT_Encode4(344877), GIMT_Encode4(0),
     /* 344250 */ /*GILLT_v8s16*//*Label 6757*/ GIMT_Encode4(344951),
     /* 344254 */ // Label 6750: @344254
     /* 344254 */ GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(344472),
     /* 344259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 344262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 344266 */   GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(344307), // Rule ID 5256 //
     /* 344271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 344274 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344278 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344282 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 344286 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 344290 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344292 */     // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm))  =>  (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)
     /* 344292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
     /* 344295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344305 */     GIR_RootConstrainSelectedInstOperands,
     /* 344306 */     // GIR_Coverage, 5256,
     /* 344306 */     GIR_EraseRootFromParent_Done,
     /* 344307 */   // Label 6760: @344307
     /* 344307 */   GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(344326), // Rule ID 525 //
     /* 344312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 344315 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 344319 */     // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 344319 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSHr),
     /* 344324 */     GIR_RootConstrainSelectedInstOperands,
     /* 344325 */     // GIR_Coverage, 525,
     /* 344325 */     GIR_Done,
     /* 344326 */   // Label 6761: @344326
     /* 344326 */   GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(344471), // Rule ID 6442 //
     /* 344331 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 344335 */     // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (ANDWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32767:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
     /* 344335 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 344338 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 344342 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344347 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 344349 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /* 344352 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 344356 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344361 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 344364 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 344368 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 344371 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344376 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344381 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 344386 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 344389 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 344393 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344398 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 344401 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 344406 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 344409 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
     /* 344413 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344418 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 344421 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // 
     /* 344426 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 344428 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 344431 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 344435 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344440 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 344443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 344451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344453 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 344460 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 344465 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344470 */     // GIR_Coverage, 6442,
     /* 344470 */     GIR_EraseRootFromParent_Done,
     /* 344471 */   // Label 6762: @344471
     /* 344471 */   GIM_Reject,
     /* 344472 */ // Label 6759: @344472
     /* 344472 */ GIM_Reject,
     /* 344473 */ // Label 6751: @344473
     /* 344473 */ GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(344546),
     /* 344478 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 344481 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344485 */   GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(344526), // Rule ID 5257 //
     /* 344490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344493 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344497 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344501 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 344505 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 344509 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344511 */     // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm))  =>  (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)
     /* 344511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
     /* 344514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344520 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344524 */     GIR_RootConstrainSelectedInstOperands,
     /* 344525 */     // GIR_Coverage, 5257,
     /* 344525 */     GIR_EraseRootFromParent_Done,
     /* 344526 */   // Label 6764: @344526
     /* 344526 */   GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(344545), // Rule ID 526 //
     /* 344531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 344534 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344538 */     // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 344538 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSSr),
     /* 344543 */     GIR_RootConstrainSelectedInstOperands,
     /* 344544 */     // GIR_Coverage, 526,
     /* 344544 */     GIR_Done,
     /* 344545 */   // Label 6765: @344545
     /* 344545 */   GIM_Reject,
     /* 344546 */ // Label 6763: @344546
     /* 344546 */ GIM_Reject,
     /* 344547 */ // Label 6752: @344547
     /* 344547 */ GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(344620),
     /* 344552 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 344555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344559 */   GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(344600), // Rule ID 5258 //
     /* 344564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 344579 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 344583 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344585 */     // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm))  =>  (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)
     /* 344585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 344588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344598 */     GIR_RootConstrainSelectedInstOperands,
     /* 344599 */     // GIR_Coverage, 5258,
     /* 344599 */     GIR_EraseRootFromParent_Done,
     /* 344600 */   // Label 6767: @344600
     /* 344600 */   GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(344619), // Rule ID 527 //
     /* 344605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 344608 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344612 */     // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 344612 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSDr),
     /* 344617 */     GIR_RootConstrainSelectedInstOperands,
     /* 344618 */     // GIR_Coverage, 527,
     /* 344618 */     GIR_Done,
     /* 344619 */   // Label 6768: @344619
     /* 344619 */   GIM_Reject,
     /* 344620 */ // Label 6766: @344620
     /* 344620 */ GIM_Reject,
     /* 344621 */ // Label 6753: @344621
     /* 344621 */ GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(344694),
     /* 344626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344629 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344633 */   GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(344674), // Rule ID 5070 //
     /* 344638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344653 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 344657 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344659 */     // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm))  =>  (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)
     /* 344659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
     /* 344662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344664 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344672 */     GIR_RootConstrainSelectedInstOperands,
     /* 344673 */     // GIR_Coverage, 5070,
     /* 344673 */     GIR_EraseRootFromParent_Done,
     /* 344674 */   // Label 6770: @344674
     /* 344674 */   GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(344693), // Rule ID 772 //
     /* 344679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344682 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344686 */     // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 344686 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f32),
     /* 344691 */     GIR_RootConstrainSelectedInstOperands,
     /* 344692 */     // GIR_Coverage, 772,
     /* 344692 */     GIR_Done,
     /* 344693 */   // Label 6771: @344693
     /* 344693 */   GIM_Reject,
     /* 344694 */ // Label 6769: @344694
     /* 344694 */ GIM_Reject,
     /* 344695 */ // Label 6754: @344695
     /* 344695 */ GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(344768),
     /* 344700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 344703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344707 */   GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(344748), // Rule ID 5072 //
     /* 344712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344723 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 344727 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 344731 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344733 */     // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm))  =>  (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)
     /* 344733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
     /* 344736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344742 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344746 */     GIR_RootConstrainSelectedInstOperands,
     /* 344747 */     // GIR_Coverage, 5072,
     /* 344747 */     GIR_EraseRootFromParent_Done,
     /* 344748 */   // Label 6773: @344748
     /* 344748 */   GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(344767), // Rule ID 774 //
     /* 344753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344756 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344760 */     // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 344760 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f64),
     /* 344765 */     GIR_RootConstrainSelectedInstOperands,
     /* 344766 */     // GIR_Coverage, 774,
     /* 344766 */     GIR_Done,
     /* 344767 */   // Label 6774: @344767
     /* 344767 */   GIM_Reject,
     /* 344768 */ // Label 6772: @344768
     /* 344768 */ GIM_Reject,
     /* 344769 */ // Label 6755: @344769
     /* 344769 */ GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(344876),
     /* 344774 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 344777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344781 */   GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(344822), // Rule ID 5073 //
     /* 344786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 344789 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344793 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344797 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 344801 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 344805 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344807 */     // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm))  =>  (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)
     /* 344807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
     /* 344810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344812 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344816 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344820 */     GIR_RootConstrainSelectedInstOperands,
     /* 344821 */     // GIR_Coverage, 5073,
     /* 344821 */     GIR_EraseRootFromParent_Done,
     /* 344822 */   // Label 6776: @344822
     /* 344822 */   GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(344841), // Rule ID 770 //
     /* 344827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 344830 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344834 */     // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 344834 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f16),
     /* 344839 */     GIR_RootConstrainSelectedInstOperands,
     /* 344840 */     // GIR_Coverage, 770,
     /* 344840 */     GIR_Done,
     /* 344841 */   // Label 6777: @344841
     /* 344841 */   GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(344875), // Rule ID 6444 //
     /* 344846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344849 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344853 */     // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (BICv4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
     /* 344853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv4i16),
     /* 344856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344858 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 344860 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
     /* 344870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 344873 */     GIR_RootConstrainSelectedInstOperands,
     /* 344874 */     // GIR_Coverage, 6444,
     /* 344874 */     GIR_EraseRootFromParent_Done,
     /* 344875 */   // Label 6778: @344875
     /* 344875 */   GIM_Reject,
     /* 344876 */ // Label 6775: @344876
     /* 344876 */ GIM_Reject,
     /* 344877 */ // Label 6756: @344877
     /* 344877 */ GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(344950),
     /* 344882 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344889 */   GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(344930), // Rule ID 5071 //
     /* 344894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344909 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 344913 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344915 */     // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm))  =>  (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)
     /* 344915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
     /* 344918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344920 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 344928 */     GIR_RootConstrainSelectedInstOperands,
     /* 344929 */     // GIR_Coverage, 5071,
     /* 344929 */     GIR_EraseRootFromParent_Done,
     /* 344930 */   // Label 6780: @344930
     /* 344930 */   GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(344949), // Rule ID 773 //
     /* 344935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344938 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344942 */     // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 344942 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f32),
     /* 344947 */     GIR_RootConstrainSelectedInstOperands,
     /* 344948 */     // GIR_Coverage, 773,
     /* 344948 */     GIR_Done,
     /* 344949 */   // Label 6781: @344949
     /* 344949 */   GIM_Reject,
     /* 344950 */ // Label 6779: @344950
     /* 344950 */ GIM_Reject,
     /* 344951 */ // Label 6757: @344951
     /* 344951 */ GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(345058),
     /* 344956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 344959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344963 */   GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(345004), // Rule ID 5074 //
     /* 344968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 344971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 344979 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 344983 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 344987 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 344989 */     // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm))  =>  (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)
     /* 344989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
     /* 344992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 344994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 345002 */     GIR_RootConstrainSelectedInstOperands,
     /* 345003 */     // GIR_Coverage, 5074,
     /* 345003 */     GIR_EraseRootFromParent_Done,
     /* 345004 */   // Label 6783: @345004
     /* 345004 */   GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(345023), // Rule ID 771 //
     /* 345009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345016 */     // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 345016 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv8f16),
     /* 345021 */     GIR_RootConstrainSelectedInstOperands,
     /* 345022 */     // GIR_Coverage, 771,
     /* 345022 */     GIR_Done,
     /* 345023 */   // Label 6784: @345023
     /* 345023 */   GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(345057), // Rule ID 6445 //
     /* 345028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345031 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345035 */     // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (BICv8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
     /* 345035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i16),
     /* 345038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345040 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345042 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
     /* 345052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 345055 */     GIR_RootConstrainSelectedInstOperands,
     /* 345056 */     // GIR_Coverage, 6445,
     /* 345056 */     GIR_EraseRootFromParent_Done,
     /* 345057 */   // Label 6785: @345057
     /* 345057 */   GIM_Reject,
     /* 345058 */ // Label 6782: @345058
     /* 345058 */ GIM_Reject,
     /* 345059 */ // Label 6758: @345059
     /* 345059 */ GIM_Reject,
     /* 345060 */ // Label 74: @345060
     /* 345060 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6794*/ GIMT_Encode4(345341),
     /* 345071 */ /*GILLT_s16*//*Label 6786*/ GIMT_Encode4(345111),
     /* 345075 */ /*GILLT_s32*//*Label 6787*/ GIMT_Encode4(345138),
     /* 345079 */ /*GILLT_s64*//*Label 6788*/ GIMT_Encode4(345162), GIMT_Encode4(0),
     /* 345087 */ /*GILLT_v2s32*//*Label 6789*/ GIMT_Encode4(345186),
     /* 345091 */ /*GILLT_v2s64*//*Label 6790*/ GIMT_Encode4(345217),
     /* 345095 */ /*GILLT_v4s16*//*Label 6791*/ GIMT_Encode4(345248),
     /* 345099 */ /*GILLT_v4s32*//*Label 6792*/ GIMT_Encode4(345279), GIMT_Encode4(0),
     /* 345107 */ /*GILLT_v8s16*//*Label 6793*/ GIMT_Encode4(345310),
     /* 345111 */ // Label 6786: @345111
     /* 345111 */ GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(345137), // Rule ID 4892 //
     /* 345116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 345119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 345122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345126 */   // (fcanonicalize:{ *:[f16] } f16:{ *:[f16] }:$a)  =>  (FMINNMHrr:{ *:[f16] } f16:{ *:[f16] }:$a, f16:{ *:[f16] }:$a)
     /* 345126 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 345129 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345131 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345133 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345135 */   GIR_RootConstrainSelectedInstOperands,
     /* 345136 */   // GIR_Coverage, 4892,
     /* 345136 */   GIR_EraseRootFromParent_Done,
     /* 345137 */ // Label 6795: @345137
     /* 345137 */ GIM_Reject,
     /* 345138 */ // Label 6787: @345138
     /* 345138 */ GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(345161), // Rule ID 4889 //
     /* 345143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 345146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345150 */   // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$a)  =>  (FMINNMSrr:{ *:[f32] } f32:{ *:[f32] }:$a, f32:{ *:[f32] }:$a)
     /* 345150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 345153 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345155 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345157 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345159 */   GIR_RootConstrainSelectedInstOperands,
     /* 345160 */   // GIR_Coverage, 4889,
     /* 345160 */   GIR_EraseRootFromParent_Done,
     /* 345161 */ // Label 6796: @345161
     /* 345161 */ GIM_Reject,
     /* 345162 */ // Label 6788: @345162
     /* 345162 */ GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(345185), // Rule ID 4886 //
     /* 345167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 345170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345174 */   // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$a)  =>  (FMINNMDrr:{ *:[f64] } f64:{ *:[f64] }:$a, f64:{ *:[f64] }:$a)
     /* 345174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 345177 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345179 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345181 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 345183 */   GIR_RootConstrainSelectedInstOperands,
     /* 345184 */   // GIR_Coverage, 4886,
     /* 345184 */   GIR_EraseRootFromParent_Done,
     /* 345185 */ // Label 6797: @345185
     /* 345185 */ GIM_Reject,
     /* 345186 */ // Label 6789: @345186
     /* 345186 */ GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(345216), // Rule ID 5083 //
     /* 345191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345201 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345205 */   // (fcanonicalize:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rn)
     /* 345205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 345208 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345210 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345212 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345214 */   GIR_RootConstrainSelectedInstOperands,
     /* 345215 */   // GIR_Coverage, 5083,
     /* 345215 */   GIR_EraseRootFromParent_Done,
     /* 345216 */ // Label 6798: @345216
     /* 345216 */ GIM_Reject,
     /* 345217 */ // Label 6790: @345217
     /* 345217 */ GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(345247), // Rule ID 5077 //
     /* 345222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345225 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345232 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345236 */   // (fcanonicalize:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn)
     /* 345236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 345239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345241 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345243 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345245 */   GIR_RootConstrainSelectedInstOperands,
     /* 345246 */   // GIR_Coverage, 5077,
     /* 345246 */   GIR_EraseRootFromParent_Done,
     /* 345247 */ // Label 6799: @345247
     /* 345247 */ GIM_Reject,
     /* 345248 */ // Label 6791: @345248
     /* 345248 */ GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(345278), // Rule ID 5089 //
     /* 345253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 345259 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345263 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345267 */   // (fcanonicalize:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rn)
     /* 345267 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 345270 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345272 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345274 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345276 */   GIR_RootConstrainSelectedInstOperands,
     /* 345277 */   // GIR_Coverage, 5089,
     /* 345277 */   GIR_EraseRootFromParent_Done,
     /* 345278 */ // Label 6800: @345278
     /* 345278 */ GIM_Reject,
     /* 345279 */ // Label 6792: @345279
     /* 345279 */ GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(345309), // Rule ID 5080 //
     /* 345284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345287 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 345290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345294 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345298 */   // (fcanonicalize:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn)
     /* 345298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 345301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345303 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345305 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345307 */   GIR_RootConstrainSelectedInstOperands,
     /* 345308 */   // GIR_Coverage, 5080,
     /* 345308 */   GIR_EraseRootFromParent_Done,
     /* 345309 */ // Label 6801: @345309
     /* 345309 */ GIM_Reject,
     /* 345310 */ // Label 6793: @345310
     /* 345310 */ GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(345340), // Rule ID 5086 //
     /* 345315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345318 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 345321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345325 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345329 */   // (fcanonicalize:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn)
     /* 345329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 345332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 345334 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345336 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345338 */   GIR_RootConstrainSelectedInstOperands,
     /* 345339 */   // GIR_Coverage, 5086,
     /* 345339 */   GIR_EraseRootFromParent_Done,
     /* 345340 */ // Label 6802: @345340
     /* 345340 */ GIM_Reject,
     /* 345341 */ // Label 6794: @345341
     /* 345341 */ GIM_Reject,
     /* 345342 */ // Label 75: @345342
     /* 345342 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6811*/ GIMT_Encode4(345719),
     /* 345353 */ /*GILLT_s16*//*Label 6803*/ GIMT_Encode4(345393),
     /* 345357 */ /*GILLT_s32*//*Label 6804*/ GIMT_Encode4(345431),
     /* 345361 */ /*GILLT_s64*//*Label 6805*/ GIMT_Encode4(345469), GIMT_Encode4(0),
     /* 345369 */ /*GILLT_v2s32*//*Label 6806*/ GIMT_Encode4(345529),
     /* 345373 */ /*GILLT_v2s64*//*Label 6807*/ GIMT_Encode4(345567),
     /* 345377 */ /*GILLT_v4s16*//*Label 6808*/ GIMT_Encode4(345605),
     /* 345381 */ /*GILLT_v4s32*//*Label 6809*/ GIMT_Encode4(345643), GIMT_Encode4(0),
     /* 345389 */ /*GILLT_v8s16*//*Label 6810*/ GIMT_Encode4(345681),
     /* 345393 */ // Label 6803: @345393
     /* 345393 */ GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(345430), // Rule ID 612 //
     /* 345398 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 345401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 345404 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 345407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345411 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345415 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345419 */   // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 345419 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 345424 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345428 */   GIR_RootConstrainSelectedInstOperands,
     /* 345429 */   // GIR_Coverage, 612,
     /* 345429 */   GIR_Done,
     /* 345430 */ // Label 6812: @345430
     /* 345430 */ GIM_Reject,
     /* 345431 */ // Label 6804: @345431
     /* 345431 */ GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(345468), // Rule ID 614 //
     /* 345436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 345439 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 345442 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 345445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345449 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345453 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345457 */   // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 345457 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 345462 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345466 */   GIR_RootConstrainSelectedInstOperands,
     /* 345467 */   // GIR_Coverage, 614,
     /* 345467 */   GIR_Done,
     /* 345468 */ // Label 6813: @345468
     /* 345468 */ GIM_Reject,
     /* 345469 */ // Label 6805: @345469
     /* 345469 */ GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(345528),
     /* 345474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 345477 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 345480 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345484 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345488 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345492 */   GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(345511), // Rule ID 616 //
     /* 345497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 345500 */     // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 345500 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 345505 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345509 */     GIR_RootConstrainSelectedInstOperands,
     /* 345510 */     // GIR_Coverage, 616,
     /* 345510 */     GIR_Done,
     /* 345511 */   // Label 6815: @345511
     /* 345511 */   GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(345527), // Rule ID 4883 //
     /* 345516 */     // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 345516 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 345521 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345525 */     GIR_RootConstrainSelectedInstOperands,
     /* 345526 */     // GIR_Coverage, 4883,
     /* 345526 */     GIR_Done,
     /* 345527 */   // Label 6816: @345527
     /* 345527 */   GIM_Reject,
     /* 345528 */ // Label 6814: @345528
     /* 345528 */ GIM_Reject,
     /* 345529 */ // Label 6806: @345529
     /* 345529 */ GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(345566), // Rule ID 1277 //
     /* 345534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345537 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345540 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 345543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345547 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345551 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345555 */   // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 345555 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 345560 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345564 */   GIR_RootConstrainSelectedInstOperands,
     /* 345565 */   // GIR_Coverage, 1277,
     /* 345565 */   GIR_Done,
     /* 345566 */ // Label 6817: @345566
     /* 345566 */ GIM_Reject,
     /* 345567 */ // Label 6807: @345567
     /* 345567 */ GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(345604), // Rule ID 1281 //
     /* 345572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345575 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345578 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 345581 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345585 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345589 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345593 */   // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 345593 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 345598 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345602 */   GIR_RootConstrainSelectedInstOperands,
     /* 345603 */   // GIR_Coverage, 1281,
     /* 345603 */   GIR_Done,
     /* 345604 */ // Label 6818: @345604
     /* 345604 */ GIM_Reject,
     /* 345605 */ // Label 6808: @345605
     /* 345605 */ GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(345642), // Rule ID 1273 //
     /* 345610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345613 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 345616 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 345619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345623 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345627 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345631 */   // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 345631 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 345636 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345640 */   GIR_RootConstrainSelectedInstOperands,
     /* 345641 */   // GIR_Coverage, 1273,
     /* 345641 */   GIR_Done,
     /* 345642 */ // Label 6819: @345642
     /* 345642 */ GIM_Reject,
     /* 345643 */ // Label 6809: @345643
     /* 345643 */ GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(345680), // Rule ID 1279 //
     /* 345648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 345654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 345657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345661 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345665 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345669 */   // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 345669 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 345674 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345678 */   GIR_RootConstrainSelectedInstOperands,
     /* 345679 */   // GIR_Coverage, 1279,
     /* 345679 */   GIR_Done,
     /* 345680 */ // Label 6820: @345680
     /* 345680 */ GIM_Reject,
     /* 345681 */ // Label 6810: @345681
     /* 345681 */ GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(345718), // Rule ID 1275 //
     /* 345686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345689 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 345692 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 345695 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345699 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345703 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345707 */   // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 345707 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 345712 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345716 */   GIR_RootConstrainSelectedInstOperands,
     /* 345717 */   // GIR_Coverage, 1275,
     /* 345717 */   GIR_Done,
     /* 345718 */ // Label 6821: @345718
     /* 345718 */ GIM_Reject,
     /* 345719 */ // Label 6811: @345719
     /* 345719 */ GIM_Reject,
     /* 345720 */ // Label 76: @345720
     /* 345720 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6830*/ GIMT_Encode4(346097),
     /* 345731 */ /*GILLT_s16*//*Label 6822*/ GIMT_Encode4(345771),
     /* 345735 */ /*GILLT_s32*//*Label 6823*/ GIMT_Encode4(345809),
     /* 345739 */ /*GILLT_s64*//*Label 6824*/ GIMT_Encode4(345847), GIMT_Encode4(0),
     /* 345747 */ /*GILLT_v2s32*//*Label 6825*/ GIMT_Encode4(345907),
     /* 345751 */ /*GILLT_v2s64*//*Label 6826*/ GIMT_Encode4(345945),
     /* 345755 */ /*GILLT_v4s16*//*Label 6827*/ GIMT_Encode4(345983),
     /* 345759 */ /*GILLT_v4s32*//*Label 6828*/ GIMT_Encode4(346021), GIMT_Encode4(0),
     /* 345767 */ /*GILLT_v8s16*//*Label 6829*/ GIMT_Encode4(346059),
     /* 345771 */ // Label 6822: @345771
     /* 345771 */ GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(345808), // Rule ID 600 //
     /* 345776 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 345779 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 345782 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 345785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345789 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345793 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 345797 */   // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 345797 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMHrr),
     /* 345802 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345806 */   GIR_RootConstrainSelectedInstOperands,
     /* 345807 */   // GIR_Coverage, 600,
     /* 345807 */   GIR_Done,
     /* 345808 */ // Label 6831: @345808
     /* 345808 */ GIM_Reject,
     /* 345809 */ // Label 6823: @345809
     /* 345809 */ GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(345846), // Rule ID 602 //
     /* 345814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 345817 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 345820 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 345823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345827 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345831 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345835 */   // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 345835 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMSrr),
     /* 345840 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345844 */   GIR_RootConstrainSelectedInstOperands,
     /* 345845 */   // GIR_Coverage, 602,
     /* 345845 */   GIR_Done,
     /* 345846 */ // Label 6832: @345846
     /* 345846 */ GIM_Reject,
     /* 345847 */ // Label 6824: @345847
     /* 345847 */ GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(345906),
     /* 345852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 345855 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 345858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345862 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345866 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345870 */   GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(345889), // Rule ID 604 //
     /* 345875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 345878 */     // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 345878 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 345883 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345887 */     GIR_RootConstrainSelectedInstOperands,
     /* 345888 */     // GIR_Coverage, 604,
     /* 345888 */     GIR_Done,
     /* 345889 */   // Label 6834: @345889
     /* 345889 */   GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(345905), // Rule ID 4882 //
     /* 345894 */     // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 345894 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 345899 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345903 */     GIR_RootConstrainSelectedInstOperands,
     /* 345904 */     // GIR_Coverage, 4882,
     /* 345904 */     GIR_Done,
     /* 345905 */   // Label 6835: @345905
     /* 345905 */   GIM_Reject,
     /* 345906 */ // Label 6833: @345906
     /* 345906 */ GIM_Reject,
     /* 345907 */ // Label 6825: @345907
     /* 345907 */ GIM_Try, /*On fail goto*//*Label 6836*/ GIMT_Encode4(345944), // Rule ID 1247 //
     /* 345912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345915 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345918 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 345921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345925 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345929 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345933 */   // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 345933 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f32),
     /* 345938 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345942 */   GIR_RootConstrainSelectedInstOperands,
     /* 345943 */   // GIR_Coverage, 1247,
     /* 345943 */   GIR_Done,
     /* 345944 */ // Label 6836: @345944
     /* 345944 */ GIM_Reject,
     /* 345945 */ // Label 6826: @345945
     /* 345945 */ GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(345982), // Rule ID 1251 //
     /* 345950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345953 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345956 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 345959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345963 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345967 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345971 */   // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 345971 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f64),
     /* 345976 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 345980 */   GIR_RootConstrainSelectedInstOperands,
     /* 345981 */   // GIR_Coverage, 1251,
     /* 345981 */   GIR_Done,
     /* 345982 */ // Label 6837: @345982
     /* 345982 */ GIM_Reject,
     /* 345983 */ // Label 6827: @345983
     /* 345983 */ GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(346020), // Rule ID 1243 //
     /* 345988 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 345991 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 345994 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 345997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346001 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346005 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346009 */   // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 346009 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f16),
     /* 346014 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346018 */   GIR_RootConstrainSelectedInstOperands,
     /* 346019 */   // GIR_Coverage, 1243,
     /* 346019 */   GIR_Done,
     /* 346020 */ // Label 6838: @346020
     /* 346020 */ GIM_Reject,
     /* 346021 */ // Label 6828: @346021
     /* 346021 */ GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(346058), // Rule ID 1249 //
     /* 346026 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346029 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 346032 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 346035 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346039 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346043 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346047 */   // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 346047 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f32),
     /* 346052 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346056 */   GIR_RootConstrainSelectedInstOperands,
     /* 346057 */   // GIR_Coverage, 1249,
     /* 346057 */   GIR_Done,
     /* 346058 */ // Label 6839: @346058
     /* 346058 */ GIM_Reject,
     /* 346059 */ // Label 6829: @346059
     /* 346059 */ GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(346096), // Rule ID 1245 //
     /* 346064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 346067 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 346070 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 346073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346077 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346081 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346085 */   // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 346085 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv8f16),
     /* 346090 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346094 */   GIR_RootConstrainSelectedInstOperands,
     /* 346095 */   // GIR_Coverage, 1245,
     /* 346095 */   GIR_Done,
     /* 346096 */ // Label 6840: @346096
     /* 346096 */ GIM_Reject,
     /* 346097 */ // Label 6830: @346097
     /* 346097 */ GIM_Reject,
     /* 346098 */ // Label 77: @346098
     /* 346098 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6849*/ GIMT_Encode4(346447),
     /* 346109 */ /*GILLT_s16*//*Label 6841*/ GIMT_Encode4(346149),
     /* 346113 */ /*GILLT_s32*//*Label 6842*/ GIMT_Encode4(346187),
     /* 346117 */ /*GILLT_s64*//*Label 6843*/ GIMT_Encode4(346222), GIMT_Encode4(0),
     /* 346125 */ /*GILLT_v2s32*//*Label 6844*/ GIMT_Encode4(346257),
     /* 346129 */ /*GILLT_v2s64*//*Label 6845*/ GIMT_Encode4(346295),
     /* 346133 */ /*GILLT_v4s16*//*Label 6846*/ GIMT_Encode4(346333),
     /* 346137 */ /*GILLT_v4s32*//*Label 6847*/ GIMT_Encode4(346371), GIMT_Encode4(0),
     /* 346145 */ /*GILLT_v8s16*//*Label 6848*/ GIMT_Encode4(346409),
     /* 346149 */ // Label 6841: @346149
     /* 346149 */ GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(346186), // Rule ID 4890 //
     /* 346154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 346157 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 346160 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 346163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346167 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346171 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346175 */   // (fminnum_ieee:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)  =>  (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 346175 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 346180 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346184 */   GIR_RootConstrainSelectedInstOperands,
     /* 346185 */   // GIR_Coverage, 4890,
     /* 346185 */   GIR_Done,
     /* 346186 */ // Label 6850: @346186
     /* 346186 */ GIM_Reject,
     /* 346187 */ // Label 6842: @346187
     /* 346187 */ GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(346221), // Rule ID 4887 //
     /* 346192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 346195 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 346198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346202 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346206 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346210 */   // (fminnum_ieee:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)  =>  (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 346210 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 346215 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346219 */   GIR_RootConstrainSelectedInstOperands,
     /* 346220 */   // GIR_Coverage, 4887,
     /* 346220 */   GIR_Done,
     /* 346221 */ // Label 6851: @346221
     /* 346221 */ GIM_Reject,
     /* 346222 */ // Label 6843: @346222
     /* 346222 */ GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(346256), // Rule ID 4884 //
     /* 346227 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 346230 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 346233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346237 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346241 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346245 */   // (fminnum_ieee:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)  =>  (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 346245 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 346250 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346254 */   GIR_RootConstrainSelectedInstOperands,
     /* 346255 */   // GIR_Coverage, 4884,
     /* 346255 */   GIR_Done,
     /* 346256 */ // Label 6852: @346256
     /* 346256 */ GIM_Reject,
     /* 346257 */ // Label 6844: @346257
     /* 346257 */ GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(346294), // Rule ID 5081 //
     /* 346262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 346268 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 346271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346275 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346279 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346283 */   // (fminnum_ieee:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 346283 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 346288 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346292 */   GIR_RootConstrainSelectedInstOperands,
     /* 346293 */   // GIR_Coverage, 5081,
     /* 346293 */   GIR_Done,
     /* 346294 */ // Label 6853: @346294
     /* 346294 */ GIM_Reject,
     /* 346295 */ // Label 6845: @346295
     /* 346295 */ GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(346332), // Rule ID 5075 //
     /* 346300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346306 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 346309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346313 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346317 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346321 */   // (fminnum_ieee:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 346321 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 346326 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346330 */   GIR_RootConstrainSelectedInstOperands,
     /* 346331 */   // GIR_Coverage, 5075,
     /* 346331 */   GIR_Done,
     /* 346332 */ // Label 6854: @346332
     /* 346332 */ GIM_Reject,
     /* 346333 */ // Label 6846: @346333
     /* 346333 */ GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(346370), // Rule ID 5087 //
     /* 346338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 346341 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 346344 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 346347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346351 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346355 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346359 */   // (fminnum_ieee:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 346359 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 346364 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346368 */   GIR_RootConstrainSelectedInstOperands,
     /* 346369 */   // GIR_Coverage, 5087,
     /* 346369 */   GIR_Done,
     /* 346370 */ // Label 6855: @346370
     /* 346370 */ GIM_Reject,
     /* 346371 */ // Label 6847: @346371
     /* 346371 */ GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(346408), // Rule ID 5078 //
     /* 346376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 346382 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 346385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346393 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346397 */   // (fminnum_ieee:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 346397 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 346402 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346406 */   GIR_RootConstrainSelectedInstOperands,
     /* 346407 */   // GIR_Coverage, 5078,
     /* 346407 */   GIR_Done,
     /* 346408 */ // Label 6856: @346408
     /* 346408 */ GIM_Reject,
     /* 346409 */ // Label 6848: @346409
     /* 346409 */ GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(346446), // Rule ID 5084 //
     /* 346414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 346417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 346420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 346423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346431 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346435 */   // (fminnum_ieee:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 346435 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 346440 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346444 */   GIR_RootConstrainSelectedInstOperands,
     /* 346445 */   // GIR_Coverage, 5084,
     /* 346445 */   GIR_Done,
     /* 346446 */ // Label 6857: @346446
     /* 346446 */ GIM_Reject,
     /* 346447 */ // Label 6849: @346447
     /* 346447 */ GIM_Reject,
     /* 346448 */ // Label 78: @346448
     /* 346448 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6866*/ GIMT_Encode4(346797),
     /* 346459 */ /*GILLT_s16*//*Label 6858*/ GIMT_Encode4(346499),
     /* 346463 */ /*GILLT_s32*//*Label 6859*/ GIMT_Encode4(346537),
     /* 346467 */ /*GILLT_s64*//*Label 6860*/ GIMT_Encode4(346572), GIMT_Encode4(0),
     /* 346475 */ /*GILLT_v2s32*//*Label 6861*/ GIMT_Encode4(346607),
     /* 346479 */ /*GILLT_v2s64*//*Label 6862*/ GIMT_Encode4(346645),
     /* 346483 */ /*GILLT_v4s16*//*Label 6863*/ GIMT_Encode4(346683),
     /* 346487 */ /*GILLT_v4s32*//*Label 6864*/ GIMT_Encode4(346721), GIMT_Encode4(0),
     /* 346495 */ /*GILLT_v8s16*//*Label 6865*/ GIMT_Encode4(346759),
     /* 346499 */ // Label 6858: @346499
     /* 346499 */ GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(346536), // Rule ID 4891 //
     /* 346504 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 346507 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 346510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 346513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346521 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346525 */   // (fmaxnum_ieee:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)  =>  (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 346525 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMHrr),
     /* 346530 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346534 */   GIR_RootConstrainSelectedInstOperands,
     /* 346535 */   // GIR_Coverage, 4891,
     /* 346535 */   GIR_Done,
     /* 346536 */ // Label 6867: @346536
     /* 346536 */ GIM_Reject,
     /* 346537 */ // Label 6859: @346537
     /* 346537 */ GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(346571), // Rule ID 4888 //
     /* 346542 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 346545 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 346548 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346552 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346556 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346560 */   // (fmaxnum_ieee:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)  =>  (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 346560 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMSrr),
     /* 346565 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346569 */   GIR_RootConstrainSelectedInstOperands,
     /* 346570 */   // GIR_Coverage, 4888,
     /* 346570 */   GIR_Done,
     /* 346571 */ // Label 6868: @346571
     /* 346571 */ GIM_Reject,
     /* 346572 */ // Label 6860: @346572
     /* 346572 */ GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(346606), // Rule ID 4885 //
     /* 346577 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 346580 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 346583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346587 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346591 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346595 */   // (fmaxnum_ieee:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)  =>  (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 346595 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 346600 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346604 */   GIR_RootConstrainSelectedInstOperands,
     /* 346605 */   // GIR_Coverage, 4885,
     /* 346605 */   GIR_Done,
     /* 346606 */ // Label 6869: @346606
     /* 346606 */ GIM_Reject,
     /* 346607 */ // Label 6861: @346607
     /* 346607 */ GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(346644), // Rule ID 5082 //
     /* 346612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346615 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 346618 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 346621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346625 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346629 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346633 */   // (fmaxnum_ieee:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 346633 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f32),
     /* 346638 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346642 */   GIR_RootConstrainSelectedInstOperands,
     /* 346643 */   // GIR_Coverage, 5082,
     /* 346643 */   GIR_Done,
     /* 346644 */ // Label 6870: @346644
     /* 346644 */ GIM_Reject,
     /* 346645 */ // Label 6862: @346645
     /* 346645 */ GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(346682), // Rule ID 5076 //
     /* 346650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346656 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 346659 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346663 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346667 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346671 */   // (fmaxnum_ieee:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 346671 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f64),
     /* 346676 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346680 */   GIR_RootConstrainSelectedInstOperands,
     /* 346681 */   // GIR_Coverage, 5076,
     /* 346681 */   GIR_Done,
     /* 346682 */ // Label 6871: @346682
     /* 346682 */ GIM_Reject,
     /* 346683 */ // Label 6863: @346683
     /* 346683 */ GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(346720), // Rule ID 5088 //
     /* 346688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 346691 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 346694 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 346697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346701 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346705 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346709 */   // (fmaxnum_ieee:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 346709 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f16),
     /* 346714 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346718 */   GIR_RootConstrainSelectedInstOperands,
     /* 346719 */   // GIR_Coverage, 5088,
     /* 346719 */   GIR_Done,
     /* 346720 */ // Label 6872: @346720
     /* 346720 */ GIM_Reject,
     /* 346721 */ // Label 6864: @346721
     /* 346721 */ GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(346758), // Rule ID 5079 //
     /* 346726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346729 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 346732 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 346735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346739 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346743 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346747 */   // (fmaxnum_ieee:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 346747 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f32),
     /* 346752 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346756 */   GIR_RootConstrainSelectedInstOperands,
     /* 346757 */   // GIR_Coverage, 5079,
     /* 346757 */   GIR_Done,
     /* 346758 */ // Label 6873: @346758
     /* 346758 */ GIM_Reject,
     /* 346759 */ // Label 6865: @346759
     /* 346759 */ GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(346796), // Rule ID 5085 //
     /* 346764 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 346767 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 346770 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 346773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346777 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346781 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346785 */   // (fmaxnum_ieee:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 346785 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv8f16),
     /* 346790 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346794 */   GIR_RootConstrainSelectedInstOperands,
     /* 346795 */   // GIR_Coverage, 5085,
     /* 346795 */   GIR_Done,
     /* 346796 */ // Label 6874: @346796
     /* 346796 */ GIM_Reject,
     /* 346797 */ // Label 6866: @346797
     /* 346797 */ GIM_Reject,
     /* 346798 */ // Label 79: @346798
     /* 346798 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6883*/ GIMT_Encode4(347500),
     /* 346809 */ /*GILLT_s16*//*Label 6875*/ GIMT_Encode4(346849),
     /* 346813 */ /*GILLT_s32*//*Label 6876*/ GIMT_Encode4(346887),
     /* 346817 */ /*GILLT_s64*//*Label 6877*/ GIMT_Encode4(346925), GIMT_Encode4(0),
     /* 346825 */ /*GILLT_v2s32*//*Label 6878*/ GIMT_Encode4(346985),
     /* 346829 */ /*GILLT_v2s64*//*Label 6879*/ GIMT_Encode4(347088),
     /* 346833 */ /*GILLT_v4s16*//*Label 6880*/ GIMT_Encode4(347191),
     /* 346837 */ /*GILLT_v4s32*//*Label 6881*/ GIMT_Encode4(347294), GIMT_Encode4(0),
     /* 346845 */ /*GILLT_v8s16*//*Label 6882*/ GIMT_Encode4(347397),
     /* 346849 */ // Label 6875: @346849
     /* 346849 */ GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(346886), // Rule ID 618 //
     /* 346854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 346857 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 346860 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 346863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346871 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 346875 */   // (fminimum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMINHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 346875 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINHrr),
     /* 346880 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346884 */   GIR_RootConstrainSelectedInstOperands,
     /* 346885 */   // GIR_Coverage, 618,
     /* 346885 */   GIR_Done,
     /* 346886 */ // Label 6884: @346886
     /* 346886 */ GIM_Reject,
     /* 346887 */ // Label 6876: @346887
     /* 346887 */ GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(346924), // Rule ID 620 //
     /* 346892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 346895 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 346898 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 346901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346905 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346909 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 346913 */   // (fminimum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMINSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 346913 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINSrr),
     /* 346918 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346922 */   GIR_RootConstrainSelectedInstOperands,
     /* 346923 */   // GIR_Coverage, 620,
     /* 346923 */   GIR_Done,
     /* 346924 */ // Label 6885: @346924
     /* 346924 */ GIM_Reject,
     /* 346925 */ // Label 6877: @346925
     /* 346925 */ GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(346984),
     /* 346930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 346933 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 346936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346944 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346948 */   GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(346967), // Rule ID 622 //
     /* 346953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 346956 */     // (fminimum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMINDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 346956 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
     /* 346961 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346965 */     GIR_RootConstrainSelectedInstOperands,
     /* 346966 */     // GIR_Coverage, 622,
     /* 346966 */     GIR_Done,
     /* 346967 */   // Label 6887: @346967
     /* 346967 */   GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(346983), // Rule ID 4881 //
     /* 346972 */     // (fminimum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMINDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 346972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
     /* 346977 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 346981 */     GIR_RootConstrainSelectedInstOperands,
     /* 346982 */     // GIR_Coverage, 4881,
     /* 346982 */     GIR_Done,
     /* 346983 */   // Label 6888: @346983
     /* 346983 */   GIM_Reject,
     /* 346984 */ // Label 6886: @346984
     /* 346984 */ GIM_Reject,
     /* 346985 */ // Label 6878: @346985
     /* 346985 */ GIM_Try, /*On fail goto*//*Label 6889*/ GIMT_Encode4(347087),
     /* 346990 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 346993 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 346996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347000 */   GIM_Try, /*On fail goto*//*Label 6890*/ GIMT_Encode4(347059), // Rule ID 2370 //
     /* 347005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347008 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347012 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347016 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 347020 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347025 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347029 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347033 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 347037 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347042 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347044 */     // (fminimum:{ *:[v2f32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FAMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 347044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f32),
     /* 347047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347049 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347053 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347057 */     GIR_RootConstrainSelectedInstOperands,
     /* 347058 */     // GIR_Coverage, 2370,
     /* 347058 */     GIR_EraseRootFromParent_Done,
     /* 347059 */   // Label 6890: @347059
     /* 347059 */   GIM_Try, /*On fail goto*//*Label 6891*/ GIMT_Encode4(347086), // Rule ID 1292 //
     /* 347064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 347067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347075 */     // (fminimum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 347075 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f32),
     /* 347080 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347084 */     GIR_RootConstrainSelectedInstOperands,
     /* 347085 */     // GIR_Coverage, 1292,
     /* 347085 */     GIR_Done,
     /* 347086 */   // Label 6891: @347086
     /* 347086 */   GIM_Reject,
     /* 347087 */ // Label 6889: @347087
     /* 347087 */ GIM_Reject,
     /* 347088 */ // Label 6879: @347088
     /* 347088 */ GIM_Try, /*On fail goto*//*Label 6892*/ GIMT_Encode4(347190),
     /* 347093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347096 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 347099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347103 */   GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(347162), // Rule ID 2376 //
     /* 347108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347119 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347123 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347128 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347132 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347136 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347140 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347145 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347147 */     // (fminimum:{ *:[v2f64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FAMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 347147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f64),
     /* 347150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347152 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347160 */     GIR_RootConstrainSelectedInstOperands,
     /* 347161 */     // GIR_Coverage, 2376,
     /* 347161 */     GIR_EraseRootFromParent_Done,
     /* 347162 */   // Label 6893: @347162
     /* 347162 */   GIM_Try, /*On fail goto*//*Label 6894*/ GIMT_Encode4(347189), // Rule ID 1296 //
     /* 347167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 347170 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347178 */     // (fminimum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 347178 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f64),
     /* 347183 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347187 */     GIR_RootConstrainSelectedInstOperands,
     /* 347188 */     // GIR_Coverage, 1296,
     /* 347188 */     GIR_Done,
     /* 347189 */   // Label 6894: @347189
     /* 347189 */   GIM_Reject,
     /* 347190 */ // Label 6892: @347190
     /* 347190 */ GIM_Reject,
     /* 347191 */ // Label 6880: @347191
     /* 347191 */ GIM_Try, /*On fail goto*//*Label 6895*/ GIMT_Encode4(347293),
     /* 347196 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347199 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 347202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347206 */   GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(347265), // Rule ID 2364 //
     /* 347211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347214 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347218 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347222 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347231 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347235 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347239 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347243 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347248 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347250 */     // (fminimum:{ *:[v4f16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FAMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 347250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f16),
     /* 347253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347263 */     GIR_RootConstrainSelectedInstOperands,
     /* 347264 */     // GIR_Coverage, 2364,
     /* 347264 */     GIR_EraseRootFromParent_Done,
     /* 347265 */   // Label 6896: @347265
     /* 347265 */   GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(347292), // Rule ID 1288 //
     /* 347270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347273 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347277 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347281 */     // (fminimum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 347281 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f16),
     /* 347286 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347290 */     GIR_RootConstrainSelectedInstOperands,
     /* 347291 */     // GIR_Coverage, 1288,
     /* 347291 */     GIR_Done,
     /* 347292 */   // Label 6897: @347292
     /* 347292 */   GIM_Reject,
     /* 347293 */ // Label 6895: @347293
     /* 347293 */ GIM_Reject,
     /* 347294 */ // Label 6881: @347294
     /* 347294 */ GIM_Try, /*On fail goto*//*Label 6898*/ GIMT_Encode4(347396),
     /* 347299 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 347302 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 347305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347309 */   GIM_Try, /*On fail goto*//*Label 6899*/ GIMT_Encode4(347368), // Rule ID 2373 //
     /* 347314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347317 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347325 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 347329 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347342 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 347346 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347353 */     // (fminimum:{ *:[v4f32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FAMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 347353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f32),
     /* 347356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347366 */     GIR_RootConstrainSelectedInstOperands,
     /* 347367 */     // GIR_Coverage, 2373,
     /* 347367 */     GIR_EraseRootFromParent_Done,
     /* 347368 */   // Label 6899: @347368
     /* 347368 */   GIM_Try, /*On fail goto*//*Label 6900*/ GIMT_Encode4(347395), // Rule ID 1294 //
     /* 347373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 347376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347384 */     // (fminimum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 347384 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f32),
     /* 347389 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347393 */     GIR_RootConstrainSelectedInstOperands,
     /* 347394 */     // GIR_Coverage, 1294,
     /* 347394 */     GIR_Done,
     /* 347395 */   // Label 6900: @347395
     /* 347395 */   GIM_Reject,
     /* 347396 */ // Label 6898: @347396
     /* 347396 */ GIM_Reject,
     /* 347397 */ // Label 6882: @347397
     /* 347397 */ GIM_Try, /*On fail goto*//*Label 6901*/ GIMT_Encode4(347499),
     /* 347402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347405 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 347408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347412 */   GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(347471), // Rule ID 2367 //
     /* 347417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347424 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347428 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347432 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347437 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347441 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347445 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347449 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347454 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347456 */     // (fminimum:{ *:[v8f16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FAMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 347456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv8f16),
     /* 347459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347469 */     GIR_RootConstrainSelectedInstOperands,
     /* 347470 */     // GIR_Coverage, 2367,
     /* 347470 */     GIR_EraseRootFromParent_Done,
     /* 347471 */   // Label 6902: @347471
     /* 347471 */   GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(347498), // Rule ID 1290 //
     /* 347476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347479 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347483 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347487 */     // (fminimum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 347487 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv8f16),
     /* 347492 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347496 */     GIR_RootConstrainSelectedInstOperands,
     /* 347497 */     // GIR_Coverage, 1290,
     /* 347497 */     GIR_Done,
     /* 347498 */   // Label 6903: @347498
     /* 347498 */   GIM_Reject,
     /* 347499 */ // Label 6901: @347499
     /* 347499 */ GIM_Reject,
     /* 347500 */ // Label 6883: @347500
     /* 347500 */ GIM_Reject,
     /* 347501 */ // Label 80: @347501
     /* 347501 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6912*/ GIMT_Encode4(348203),
     /* 347512 */ /*GILLT_s16*//*Label 6904*/ GIMT_Encode4(347552),
     /* 347516 */ /*GILLT_s32*//*Label 6905*/ GIMT_Encode4(347590),
     /* 347520 */ /*GILLT_s64*//*Label 6906*/ GIMT_Encode4(347628), GIMT_Encode4(0),
     /* 347528 */ /*GILLT_v2s32*//*Label 6907*/ GIMT_Encode4(347688),
     /* 347532 */ /*GILLT_v2s64*//*Label 6908*/ GIMT_Encode4(347791),
     /* 347536 */ /*GILLT_v4s16*//*Label 6909*/ GIMT_Encode4(347894),
     /* 347540 */ /*GILLT_v4s32*//*Label 6910*/ GIMT_Encode4(347997), GIMT_Encode4(0),
     /* 347548 */ /*GILLT_v8s16*//*Label 6911*/ GIMT_Encode4(348100),
     /* 347552 */ // Label 6904: @347552
     /* 347552 */ GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(347589), // Rule ID 606 //
     /* 347557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 347560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 347563 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 347566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 347570 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 347574 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 347578 */   // (fmaximum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMAXHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 347578 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXHrr),
     /* 347583 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347587 */   GIR_RootConstrainSelectedInstOperands,
     /* 347588 */   // GIR_Coverage, 606,
     /* 347588 */   GIR_Done,
     /* 347589 */ // Label 6913: @347589
     /* 347589 */ GIM_Reject,
     /* 347590 */ // Label 6905: @347590
     /* 347590 */ GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(347627), // Rule ID 608 //
     /* 347595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 347598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 347601 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 347604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 347608 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 347612 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 347616 */   // (fmaximum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMAXSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 347616 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXSrr),
     /* 347621 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347625 */   GIR_RootConstrainSelectedInstOperands,
     /* 347626 */   // GIR_Coverage, 608,
     /* 347626 */   GIR_Done,
     /* 347627 */ // Label 6914: @347627
     /* 347627 */ GIM_Reject,
     /* 347628 */ // Label 6906: @347628
     /* 347628 */ GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(347687),
     /* 347633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 347636 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 347639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347643 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347647 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347651 */   GIM_Try, /*On fail goto*//*Label 6916*/ GIMT_Encode4(347670), // Rule ID 610 //
     /* 347656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 347659 */     // (fmaximum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMAXDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 347659 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
     /* 347664 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347668 */     GIR_RootConstrainSelectedInstOperands,
     /* 347669 */     // GIR_Coverage, 610,
     /* 347669 */     GIR_Done,
     /* 347670 */   // Label 6916: @347670
     /* 347670 */   GIM_Try, /*On fail goto*//*Label 6917*/ GIMT_Encode4(347686), // Rule ID 4880 //
     /* 347675 */     // (fmaximum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMAXDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 347675 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
     /* 347680 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347684 */     GIR_RootConstrainSelectedInstOperands,
     /* 347685 */     // GIR_Coverage, 4880,
     /* 347685 */     GIR_Done,
     /* 347686 */   // Label 6917: @347686
     /* 347686 */   GIM_Reject,
     /* 347687 */ // Label 6915: @347687
     /* 347687 */ GIM_Reject,
     /* 347688 */ // Label 6907: @347688
     /* 347688 */ GIM_Try, /*On fail goto*//*Label 6918*/ GIMT_Encode4(347790),
     /* 347693 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 347696 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 347699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347703 */   GIM_Try, /*On fail goto*//*Label 6919*/ GIMT_Encode4(347762), // Rule ID 2355 //
     /* 347708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347711 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347715 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347719 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 347723 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347728 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347732 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347736 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 347740 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347745 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347747 */     // (fmaximum:{ *:[v2f32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FAMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 347747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f32),
     /* 347750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347760 */     GIR_RootConstrainSelectedInstOperands,
     /* 347761 */     // GIR_Coverage, 2355,
     /* 347761 */     GIR_EraseRootFromParent_Done,
     /* 347762 */   // Label 6919: @347762
     /* 347762 */   GIM_Try, /*On fail goto*//*Label 6920*/ GIMT_Encode4(347789), // Rule ID 1262 //
     /* 347767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 347770 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347774 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347778 */     // (fmaximum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 347778 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f32),
     /* 347783 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347787 */     GIR_RootConstrainSelectedInstOperands,
     /* 347788 */     // GIR_Coverage, 1262,
     /* 347788 */     GIR_Done,
     /* 347789 */   // Label 6920: @347789
     /* 347789 */   GIM_Reject,
     /* 347790 */ // Label 6918: @347790
     /* 347790 */ GIM_Reject,
     /* 347791 */ // Label 6908: @347791
     /* 347791 */ GIM_Try, /*On fail goto*//*Label 6921*/ GIMT_Encode4(347893),
     /* 347796 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347799 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 347802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347806 */   GIM_Try, /*On fail goto*//*Label 6922*/ GIMT_Encode4(347865), // Rule ID 2361 //
     /* 347811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347831 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347839 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 347843 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347848 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347850 */     // (fmaximum:{ *:[v2f64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FAMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 347850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f64),
     /* 347853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347859 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347863 */     GIR_RootConstrainSelectedInstOperands,
     /* 347864 */     // GIR_Coverage, 2361,
     /* 347864 */     GIR_EraseRootFromParent_Done,
     /* 347865 */   // Label 6922: @347865
     /* 347865 */   GIM_Try, /*On fail goto*//*Label 6923*/ GIMT_Encode4(347892), // Rule ID 1266 //
     /* 347870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 347873 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347881 */     // (fmaximum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 347881 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f64),
     /* 347886 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347890 */     GIR_RootConstrainSelectedInstOperands,
     /* 347891 */     // GIR_Coverage, 1266,
     /* 347891 */     GIR_Done,
     /* 347892 */   // Label 6923: @347892
     /* 347892 */   GIM_Reject,
     /* 347893 */ // Label 6921: @347893
     /* 347893 */ GIM_Reject,
     /* 347894 */ // Label 6909: @347894
     /* 347894 */ GIM_Try, /*On fail goto*//*Label 6924*/ GIMT_Encode4(347996),
     /* 347899 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347902 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 347905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347909 */   GIM_Try, /*On fail goto*//*Label 6925*/ GIMT_Encode4(347968), // Rule ID 2349 //
     /* 347914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 347917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347925 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347929 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347934 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347938 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 347942 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347946 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347951 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347953 */     // (fmaximum:{ *:[v4f16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FAMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 347953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f16),
     /* 347956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 347958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347962 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347966 */     GIR_RootConstrainSelectedInstOperands,
     /* 347967 */     // GIR_Coverage, 2349,
     /* 347967 */     GIR_EraseRootFromParent_Done,
     /* 347968 */   // Label 6925: @347968
     /* 347968 */   GIM_Try, /*On fail goto*//*Label 6926*/ GIMT_Encode4(347995), // Rule ID 1258 //
     /* 347973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347984 */     // (fmaximum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 347984 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f16),
     /* 347989 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 347993 */     GIR_RootConstrainSelectedInstOperands,
     /* 347994 */     // GIR_Coverage, 1258,
     /* 347994 */     GIR_Done,
     /* 347995 */   // Label 6926: @347995
     /* 347995 */   GIM_Reject,
     /* 347996 */ // Label 6924: @347996
     /* 347996 */ GIM_Reject,
     /* 347997 */ // Label 6910: @347997
     /* 347997 */ GIM_Try, /*On fail goto*//*Label 6927*/ GIMT_Encode4(348099),
     /* 348002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348005 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 348008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348012 */   GIM_Try, /*On fail goto*//*Label 6928*/ GIMT_Encode4(348071), // Rule ID 2358 //
     /* 348017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 348020 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348024 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 348028 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348032 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348037 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 348041 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 348045 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348049 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348054 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348056 */     // (fmaximum:{ *:[v4f32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FAMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 348056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f32),
     /* 348059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 348065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348069 */     GIR_RootConstrainSelectedInstOperands,
     /* 348070 */     // GIR_Coverage, 2358,
     /* 348070 */     GIR_EraseRootFromParent_Done,
     /* 348071 */   // Label 6928: @348071
     /* 348071 */   GIM_Try, /*On fail goto*//*Label 6929*/ GIMT_Encode4(348098), // Rule ID 1264 //
     /* 348076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348079 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348087 */     // (fmaximum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 348087 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f32),
     /* 348092 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 348096 */     GIR_RootConstrainSelectedInstOperands,
     /* 348097 */     // GIR_Coverage, 1264,
     /* 348097 */     GIR_Done,
     /* 348098 */   // Label 6929: @348098
     /* 348098 */   GIM_Reject,
     /* 348099 */ // Label 6927: @348099
     /* 348099 */ GIM_Reject,
     /* 348100 */ // Label 6911: @348100
     /* 348100 */ GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(348202),
     /* 348105 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 348108 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 348111 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348115 */   GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(348174), // Rule ID 2352 //
     /* 348120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 348123 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348127 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 348131 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 348135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348140 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 348144 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 348148 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 348152 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348157 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348159 */     // (fmaximum:{ *:[v8f16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FAMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 348159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv8f16),
     /* 348162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 348168 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348172 */     GIR_RootConstrainSelectedInstOperands,
     /* 348173 */     // GIR_Coverage, 2352,
     /* 348173 */     GIR_EraseRootFromParent_Done,
     /* 348174 */   // Label 6931: @348174
     /* 348174 */   GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(348201), // Rule ID 1260 //
     /* 348179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 348182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348186 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348190 */     // (fmaximum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 348190 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv8f16),
     /* 348195 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 348199 */     GIR_RootConstrainSelectedInstOperands,
     /* 348200 */     // GIR_Coverage, 1260,
     /* 348200 */     GIR_Done,
     /* 348201 */   // Label 6932: @348201
     /* 348201 */   GIM_Reject,
     /* 348202 */ // Label 6930: @348202
     /* 348202 */ GIM_Reject,
     /* 348203 */ // Label 6912: @348203
     /* 348203 */ GIM_Reject,
     /* 348204 */ // Label 81: @348204
     /* 348204 */ GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(348703),
     /* 348209 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 348212 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
     /* 348216 */   GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(348307), // Rule ID 7072 //
     /* 348221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348228 */     // MIs[0] Rn
     /* 348228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 348232 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348236 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348240 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 348244 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348248 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348252 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /* 348256 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348260 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 348264 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 348268 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348272 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348277 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 348281 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348285 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 348289 */     // MIs[3] Operand 1
     /* 348289 */     // No operand predicates
     /* 348289 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348291 */     // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, (shl:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)))  =>  (SUBPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)
     /* 348291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBPT_shift),
     /* 348294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348296 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348298 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348302 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 348305 */     GIR_RootConstrainSelectedInstOperands,
     /* 348306 */     // GIR_Coverage, 7072,
     /* 348306 */     GIR_EraseRootFromParent_Done,
     /* 348307 */   // Label 6934: @348307
     /* 348307 */   GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(348471),
     /* 348312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 348320 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348324 */     GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(348397), // Rule ID 15296 //
     /* 348329 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348332 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348336 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 348340 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348344 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348348 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348352 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 348356 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 348360 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348364 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 0,
     /* 348368 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348373 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348378 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348380 */       // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64:{ *:[i64] }:$Rn))  =>  (MSUBPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 348380 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBPT),
     /* 348383 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348385 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 348389 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 348393 */       GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 348395 */       GIR_RootConstrainSelectedInstOperands,
     /* 348396 */       // GIR_Coverage, 15296,
     /* 348396 */       GIR_EraseRootFromParent_Done,
     /* 348397 */     // Label 6936: @348397
     /* 348397 */     GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(348470), // Rule ID 7074 //
     /* 348402 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348405 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348409 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 348413 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348417 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348421 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348426 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348430 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 348434 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 348438 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348442 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 0,
     /* 348446 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348451 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348453 */       // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm)))  =>  (MSUBPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 348453 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBPT),
     /* 348456 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348458 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 348462 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 348466 */       GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 348468 */       GIR_RootConstrainSelectedInstOperands,
     /* 348469 */       // GIR_Coverage, 7074,
     /* 348469 */       GIR_EraseRootFromParent_Done,
     /* 348470 */     // Label 6937: @348470
     /* 348470 */     GIM_Reject,
     /* 348471 */   // Label 6935: @348471
     /* 348471 */   GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(348599),
     /* 348476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348480 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 348484 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348488 */     GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(348539), // Rule ID 7071 //
     /* 348493 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348496 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348500 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 348504 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348508 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348512 */       GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /* 348516 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348521 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348523 */       // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rm))  =>  (SUBPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, 0:{ *:[i64] })
     /* 348523 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBPT_shift),
     /* 348526 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348528 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348530 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 348534 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 348537 */       GIR_RootConstrainSelectedInstOperands,
     /* 348538 */       // GIR_Coverage, 7071,
     /* 348538 */       GIR_EraseRootFromParent_Done,
     /* 348539 */     // Label 6939: @348539
     /* 348539 */     GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(348598), // Rule ID 7070 //
     /* 348544 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348547 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348551 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 348555 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348559 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348563 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348568 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348572 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348576 */       GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 348580 */       // MIs[2] Operand 1
     /* 348580 */       // No operand predicates
     /* 348580 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348582 */       // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (shl:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm))  =>  (ADDPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)
     /* 348582 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPT_shift),
     /* 348585 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348587 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348589 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348593 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 348596 */       GIR_RootConstrainSelectedInstOperands,
     /* 348597 */       // GIR_Coverage, 7070,
     /* 348597 */       GIR_EraseRootFromParent_Done,
     /* 348598 */     // Label 6940: @348598
     /* 348598 */     GIM_Reject,
     /* 348599 */   // Label 6938: @348599
     /* 348599 */   GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(348664), // Rule ID 7073 //
     /* 348604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348611 */     // MIs[0] Ra
     /* 348611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 348615 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348619 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348623 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 348627 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 348631 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348635 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348640 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348645 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348647 */     // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MADDPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 348647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDPT),
     /* 348650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 348656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 348660 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 348662 */     GIR_RootConstrainSelectedInstOperands,
     /* 348663 */     // GIR_Coverage, 7073,
     /* 348663 */     GIR_EraseRootFromParent_Done,
     /* 348664 */   // Label 6941: @348664
     /* 348664 */   GIM_Try, /*On fail goto*//*Label 6942*/ GIMT_Encode4(348702), // Rule ID 7069 //
     /* 348669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 348672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348676 */     // MIs[0] Rn
     /* 348676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 348680 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 348688 */     // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (ADDPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, 0:{ *:[i64] })
     /* 348688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPT_shift),
     /* 348691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348693 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 348697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 348700 */     GIR_RootConstrainSelectedInstOperands,
     /* 348701 */     // GIR_Coverage, 7069,
     /* 348701 */     GIR_EraseRootFromParent_Done,
     /* 348702 */   // Label 6942: @348702
     /* 348702 */   GIM_Reject,
     /* 348703 */ // Label 6933: @348703
     /* 348703 */ GIM_Reject,
     /* 348704 */ // Label 82: @348704
     /* 348704 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6951*/ GIMT_Encode4(349107),
     /* 348715 */ /*GILLT_s32*//*Label 6943*/ GIMT_Encode4(348755),
     /* 348719 */ /*GILLT_s64*//*Label 6944*/ GIMT_Encode4(348829), GIMT_Encode4(0),
     /* 348727 */ /*GILLT_v2s32*//*Label 6945*/ GIMT_Encode4(348903), GIMT_Encode4(0),
     /* 348735 */ /*GILLT_v4s16*//*Label 6946*/ GIMT_Encode4(348937),
     /* 348739 */ /*GILLT_v4s32*//*Label 6947*/ GIMT_Encode4(348971),
     /* 348743 */ /*GILLT_v8s8*//*Label 6948*/ GIMT_Encode4(349005),
     /* 348747 */ /*GILLT_v8s16*//*Label 6949*/ GIMT_Encode4(349039),
     /* 348751 */ /*GILLT_v16s8*//*Label 6950*/ GIMT_Encode4(349073),
     /* 348755 */ // Label 6943: @348755
     /* 348755 */ GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(348828),
     /* 348760 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 348763 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 348766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 348770 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 348774 */   GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(348808), // Rule ID 2332 //
     /* 348779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 348782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348790 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
     /* 348794 */     // MIs[1] Operand 1
     /* 348794 */     // No operand predicates
     /* 348794 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348796 */     // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm)  =>  (SMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 348796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINWri),
     /* 348799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348801 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348803 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 348806 */     GIR_RootConstrainSelectedInstOperands,
     /* 348807 */     // GIR_Coverage, 2332,
     /* 348807 */     GIR_EraseRootFromParent_Done,
     /* 348808 */   // Label 6953: @348808
     /* 348808 */   GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(348827), // Rule ID 2331 //
     /* 348813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 348816 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 348820 */     // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 348820 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINWrr),
     /* 348825 */     GIR_RootConstrainSelectedInstOperands,
     /* 348826 */     // GIR_Coverage, 2331,
     /* 348826 */     GIR_Done,
     /* 348827 */   // Label 6954: @348827
     /* 348827 */   GIM_Reject,
     /* 348828 */ // Label 6952: @348828
     /* 348828 */ GIM_Reject,
     /* 348829 */ // Label 6944: @348829
     /* 348829 */ GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(348902),
     /* 348834 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 348837 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 348840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348844 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348848 */   GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(348882), // Rule ID 2334 //
     /* 348853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 348856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348864 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
     /* 348868 */     // MIs[1] Operand 1
     /* 348868 */     // No operand predicates
     /* 348868 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348870 */     // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm)  =>  (SMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 348870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINXri),
     /* 348873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 348875 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348877 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 348880 */     GIR_RootConstrainSelectedInstOperands,
     /* 348881 */     // GIR_Coverage, 2334,
     /* 348881 */     GIR_EraseRootFromParent_Done,
     /* 348882 */   // Label 6956: @348882
     /* 348882 */   GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(348901), // Rule ID 2333 //
     /* 348887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 348890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 348894 */     // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 348894 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINXrr),
     /* 348899 */     GIR_RootConstrainSelectedInstOperands,
     /* 348900 */     // GIR_Coverage, 2333,
     /* 348900 */     GIR_Done,
     /* 348901 */   // Label 6957: @348901
     /* 348901 */   GIM_Reject,
     /* 348902 */ // Label 6955: @348902
     /* 348902 */ GIM_Reject,
     /* 348903 */ // Label 6945: @348903
     /* 348903 */ GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(348936), // Rule ID 1418 //
     /* 348908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 348914 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 348917 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348921 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348925 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348929 */   // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 348929 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv2i32),
     /* 348934 */   GIR_RootConstrainSelectedInstOperands,
     /* 348935 */   // GIR_Coverage, 1418,
     /* 348935 */   GIR_Done,
     /* 348936 */ // Label 6958: @348936
     /* 348936 */ GIM_Reject,
     /* 348937 */ // Label 6946: @348937
     /* 348937 */ GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(348970), // Rule ID 1416 //
     /* 348942 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348945 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 348948 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 348951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348955 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348959 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348963 */   // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 348963 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i16),
     /* 348968 */   GIR_RootConstrainSelectedInstOperands,
     /* 348969 */   // GIR_Coverage, 1416,
     /* 348969 */   GIR_Done,
     /* 348970 */ // Label 6959: @348970
     /* 348970 */ GIM_Reject,
     /* 348971 */ // Label 6947: @348971
     /* 348971 */ GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(349004), // Rule ID 1419 //
     /* 348976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348982 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 348985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348989 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348993 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348997 */   // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 348997 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i32),
     /* 349002 */   GIR_RootConstrainSelectedInstOperands,
     /* 349003 */   // GIR_Coverage, 1419,
     /* 349003 */   GIR_Done,
     /* 349004 */ // Label 6960: @349004
     /* 349004 */ GIM_Reject,
     /* 349005 */ // Label 6948: @349005
     /* 349005 */ GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(349038), // Rule ID 1414 //
     /* 349010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349013 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 349016 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 349019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349023 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349027 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349031 */   // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 349031 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i8),
     /* 349036 */   GIR_RootConstrainSelectedInstOperands,
     /* 349037 */   // GIR_Coverage, 1414,
     /* 349037 */   GIR_Done,
     /* 349038 */ // Label 6961: @349038
     /* 349038 */ GIM_Reject,
     /* 349039 */ // Label 6949: @349039
     /* 349039 */ GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(349072), // Rule ID 1417 //
     /* 349044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349047 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349050 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 349053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349057 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349061 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349065 */   // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 349065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i16),
     /* 349070 */   GIR_RootConstrainSelectedInstOperands,
     /* 349071 */   // GIR_Coverage, 1417,
     /* 349071 */   GIR_Done,
     /* 349072 */ // Label 6962: @349072
     /* 349072 */ GIM_Reject,
     /* 349073 */ // Label 6950: @349073
     /* 349073 */ GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(349106), // Rule ID 1415 //
     /* 349078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 349084 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 349087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349091 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349095 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349099 */   // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 349099 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv16i8),
     /* 349104 */   GIR_RootConstrainSelectedInstOperands,
     /* 349105 */   // GIR_Coverage, 1415,
     /* 349105 */   GIR_Done,
     /* 349106 */ // Label 6963: @349106
     /* 349106 */ GIM_Reject,
     /* 349107 */ // Label 6951: @349107
     /* 349107 */ GIM_Reject,
     /* 349108 */ // Label 83: @349108
     /* 349108 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6972*/ GIMT_Encode4(349511),
     /* 349119 */ /*GILLT_s32*//*Label 6964*/ GIMT_Encode4(349159),
     /* 349123 */ /*GILLT_s64*//*Label 6965*/ GIMT_Encode4(349233), GIMT_Encode4(0),
     /* 349131 */ /*GILLT_v2s32*//*Label 6966*/ GIMT_Encode4(349307), GIMT_Encode4(0),
     /* 349139 */ /*GILLT_v4s16*//*Label 6967*/ GIMT_Encode4(349341),
     /* 349143 */ /*GILLT_v4s32*//*Label 6968*/ GIMT_Encode4(349375),
     /* 349147 */ /*GILLT_v8s8*//*Label 6969*/ GIMT_Encode4(349409),
     /* 349151 */ /*GILLT_v8s16*//*Label 6970*/ GIMT_Encode4(349443),
     /* 349155 */ /*GILLT_v16s8*//*Label 6971*/ GIMT_Encode4(349477),
     /* 349159 */ // Label 6964: @349159
     /* 349159 */ GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(349232),
     /* 349164 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 349167 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 349170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349174 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349178 */   GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(349212), // Rule ID 2328 //
     /* 349183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349194 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
     /* 349198 */     // MIs[1] Operand 1
     /* 349198 */     // No operand predicates
     /* 349198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349200 */     // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm)  =>  (SMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 349200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXWri),
     /* 349203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 349205 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349207 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 349210 */     GIR_RootConstrainSelectedInstOperands,
     /* 349211 */     // GIR_Coverage, 2328,
     /* 349211 */     GIR_EraseRootFromParent_Done,
     /* 349212 */   // Label 6974: @349212
     /* 349212 */   GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(349231), // Rule ID 2327 //
     /* 349217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349224 */     // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 349224 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXWrr),
     /* 349229 */     GIR_RootConstrainSelectedInstOperands,
     /* 349230 */     // GIR_Coverage, 2327,
     /* 349230 */     GIR_Done,
     /* 349231 */   // Label 6975: @349231
     /* 349231 */   GIM_Reject,
     /* 349232 */ // Label 6973: @349232
     /* 349232 */ GIM_Reject,
     /* 349233 */ // Label 6965: @349233
     /* 349233 */ GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(349306),
     /* 349238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 349241 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 349244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349248 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349252 */   GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(349286), // Rule ID 2330 //
     /* 349257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349260 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349264 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349268 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
     /* 349272 */     // MIs[1] Operand 1
     /* 349272 */     // No operand predicates
     /* 349272 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349274 */     // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm)  =>  (SMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 349274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXXri),
     /* 349277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 349279 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349281 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 349284 */     GIR_RootConstrainSelectedInstOperands,
     /* 349285 */     // GIR_Coverage, 2330,
     /* 349285 */     GIR_EraseRootFromParent_Done,
     /* 349286 */   // Label 6977: @349286
     /* 349286 */   GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(349305), // Rule ID 2329 //
     /* 349291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349298 */     // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 349298 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXXrr),
     /* 349303 */     GIR_RootConstrainSelectedInstOperands,
     /* 349304 */     // GIR_Coverage, 2329,
     /* 349304 */     GIR_Done,
     /* 349305 */   // Label 6978: @349305
     /* 349305 */   GIM_Reject,
     /* 349306 */ // Label 6976: @349306
     /* 349306 */ GIM_Reject,
     /* 349307 */ // Label 6966: @349307
     /* 349307 */ GIM_Try, /*On fail goto*//*Label 6979*/ GIMT_Encode4(349340), // Rule ID 1406 //
     /* 349312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 349318 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 349321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349325 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349329 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349333 */   // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 349333 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv2i32),
     /* 349338 */   GIR_RootConstrainSelectedInstOperands,
     /* 349339 */   // GIR_Coverage, 1406,
     /* 349339 */   GIR_Done,
     /* 349340 */ // Label 6979: @349340
     /* 349340 */ GIM_Reject,
     /* 349341 */ // Label 6967: @349341
     /* 349341 */ GIM_Try, /*On fail goto*//*Label 6980*/ GIMT_Encode4(349374), // Rule ID 1404 //
     /* 349346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349349 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 349352 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 349355 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349359 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349363 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349367 */   // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 349367 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i16),
     /* 349372 */   GIR_RootConstrainSelectedInstOperands,
     /* 349373 */   // GIR_Coverage, 1404,
     /* 349373 */   GIR_Done,
     /* 349374 */ // Label 6980: @349374
     /* 349374 */ GIM_Reject,
     /* 349375 */ // Label 6968: @349375
     /* 349375 */ GIM_Try, /*On fail goto*//*Label 6981*/ GIMT_Encode4(349408), // Rule ID 1407 //
     /* 349380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349383 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349386 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 349389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349393 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349397 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349401 */   // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 349401 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i32),
     /* 349406 */   GIR_RootConstrainSelectedInstOperands,
     /* 349407 */   // GIR_Coverage, 1407,
     /* 349407 */   GIR_Done,
     /* 349408 */ // Label 6981: @349408
     /* 349408 */ GIM_Reject,
     /* 349409 */ // Label 6969: @349409
     /* 349409 */ GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(349442), // Rule ID 1402 //
     /* 349414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 349420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 349423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349431 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349435 */   // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 349435 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i8),
     /* 349440 */   GIR_RootConstrainSelectedInstOperands,
     /* 349441 */   // GIR_Coverage, 1402,
     /* 349441 */   GIR_Done,
     /* 349442 */ // Label 6982: @349442
     /* 349442 */ GIM_Reject,
     /* 349443 */ // Label 6970: @349443
     /* 349443 */ GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(349476), // Rule ID 1405 //
     /* 349448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349454 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 349457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349461 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349465 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349469 */   // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 349469 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i16),
     /* 349474 */   GIR_RootConstrainSelectedInstOperands,
     /* 349475 */   // GIR_Coverage, 1405,
     /* 349475 */   GIR_Done,
     /* 349476 */ // Label 6983: @349476
     /* 349476 */ GIM_Reject,
     /* 349477 */ // Label 6971: @349477
     /* 349477 */ GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(349510), // Rule ID 1403 //
     /* 349482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 349488 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 349491 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349495 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349499 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349503 */   // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 349503 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv16i8),
     /* 349508 */   GIR_RootConstrainSelectedInstOperands,
     /* 349509 */   // GIR_Coverage, 1403,
     /* 349509 */   GIR_Done,
     /* 349510 */ // Label 6984: @349510
     /* 349510 */ GIM_Reject,
     /* 349511 */ // Label 6972: @349511
     /* 349511 */ GIM_Reject,
     /* 349512 */ // Label 84: @349512
     /* 349512 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6993*/ GIMT_Encode4(349915),
     /* 349523 */ /*GILLT_s32*//*Label 6985*/ GIMT_Encode4(349563),
     /* 349527 */ /*GILLT_s64*//*Label 6986*/ GIMT_Encode4(349637), GIMT_Encode4(0),
     /* 349535 */ /*GILLT_v2s32*//*Label 6987*/ GIMT_Encode4(349711), GIMT_Encode4(0),
     /* 349543 */ /*GILLT_v4s16*//*Label 6988*/ GIMT_Encode4(349745),
     /* 349547 */ /*GILLT_v4s32*//*Label 6989*/ GIMT_Encode4(349779),
     /* 349551 */ /*GILLT_v8s8*//*Label 6990*/ GIMT_Encode4(349813),
     /* 349555 */ /*GILLT_v8s16*//*Label 6991*/ GIMT_Encode4(349847),
     /* 349559 */ /*GILLT_v16s8*//*Label 6992*/ GIMT_Encode4(349881),
     /* 349563 */ // Label 6985: @349563
     /* 349563 */ GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(349636),
     /* 349568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 349571 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 349574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349578 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349582 */   GIM_Try, /*On fail goto*//*Label 6995*/ GIMT_Encode4(349616), // Rule ID 2340 //
     /* 349587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349590 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349594 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349598 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
     /* 349602 */     // MIs[1] Operand 1
     /* 349602 */     // No operand predicates
     /* 349602 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349604 */     // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm)  =>  (UMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 349604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINWri),
     /* 349607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 349609 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349611 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 349614 */     GIR_RootConstrainSelectedInstOperands,
     /* 349615 */     // GIR_Coverage, 2340,
     /* 349615 */     GIR_EraseRootFromParent_Done,
     /* 349616 */   // Label 6995: @349616
     /* 349616 */   GIM_Try, /*On fail goto*//*Label 6996*/ GIMT_Encode4(349635), // Rule ID 2339 //
     /* 349621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349628 */     // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 349628 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINWrr),
     /* 349633 */     GIR_RootConstrainSelectedInstOperands,
     /* 349634 */     // GIR_Coverage, 2339,
     /* 349634 */     GIR_Done,
     /* 349635 */   // Label 6996: @349635
     /* 349635 */   GIM_Reject,
     /* 349636 */ // Label 6994: @349636
     /* 349636 */ GIM_Reject,
     /* 349637 */ // Label 6986: @349637
     /* 349637 */ GIM_Try, /*On fail goto*//*Label 6997*/ GIMT_Encode4(349710),
     /* 349642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 349645 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 349648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349652 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349656 */   GIM_Try, /*On fail goto*//*Label 6998*/ GIMT_Encode4(349690), // Rule ID 2342 //
     /* 349661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349672 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
     /* 349676 */     // MIs[1] Operand 1
     /* 349676 */     // No operand predicates
     /* 349676 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349678 */     // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm)  =>  (UMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 349678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINXri),
     /* 349681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 349683 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349685 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 349688 */     GIR_RootConstrainSelectedInstOperands,
     /* 349689 */     // GIR_Coverage, 2342,
     /* 349689 */     GIR_EraseRootFromParent_Done,
     /* 349690 */   // Label 6998: @349690
     /* 349690 */   GIM_Try, /*On fail goto*//*Label 6999*/ GIMT_Encode4(349709), // Rule ID 2341 //
     /* 349695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 349702 */     // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 349702 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINXrr),
     /* 349707 */     GIR_RootConstrainSelectedInstOperands,
     /* 349708 */     // GIR_Coverage, 2341,
     /* 349708 */     GIR_Done,
     /* 349709 */   // Label 6999: @349709
     /* 349709 */   GIM_Reject,
     /* 349710 */ // Label 6997: @349710
     /* 349710 */ GIM_Reject,
     /* 349711 */ // Label 6987: @349711
     /* 349711 */ GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(349744), // Rule ID 1541 //
     /* 349716 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349719 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 349722 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 349725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349729 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349733 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349737 */   // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 349737 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv2i32),
     /* 349742 */   GIR_RootConstrainSelectedInstOperands,
     /* 349743 */   // GIR_Coverage, 1541,
     /* 349743 */   GIR_Done,
     /* 349744 */ // Label 7000: @349744
     /* 349744 */ GIM_Reject,
     /* 349745 */ // Label 6988: @349745
     /* 349745 */ GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(349778), // Rule ID 1539 //
     /* 349750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349753 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 349756 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 349759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349763 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349767 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349771 */   // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 349771 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i16),
     /* 349776 */   GIR_RootConstrainSelectedInstOperands,
     /* 349777 */   // GIR_Coverage, 1539,
     /* 349777 */   GIR_Done,
     /* 349778 */ // Label 7001: @349778
     /* 349778 */ GIM_Reject,
     /* 349779 */ // Label 6989: @349779
     /* 349779 */ GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(349812), // Rule ID 1542 //
     /* 349784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349787 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349790 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 349793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349797 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349801 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349805 */   // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 349805 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i32),
     /* 349810 */   GIR_RootConstrainSelectedInstOperands,
     /* 349811 */   // GIR_Coverage, 1542,
     /* 349811 */   GIR_Done,
     /* 349812 */ // Label 7002: @349812
     /* 349812 */ GIM_Reject,
     /* 349813 */ // Label 6990: @349813
     /* 349813 */ GIM_Try, /*On fail goto*//*Label 7003*/ GIMT_Encode4(349846), // Rule ID 1537 //
     /* 349818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349821 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 349824 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 349827 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349831 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349835 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 349839 */   // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 349839 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i8),
     /* 349844 */   GIR_RootConstrainSelectedInstOperands,
     /* 349845 */   // GIR_Coverage, 1537,
     /* 349845 */   GIR_Done,
     /* 349846 */ // Label 7003: @349846
     /* 349846 */ GIM_Reject,
     /* 349847 */ // Label 6991: @349847
     /* 349847 */ GIM_Try, /*On fail goto*//*Label 7004*/ GIMT_Encode4(349880), // Rule ID 1540 //
     /* 349852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 349861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349865 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349869 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349873 */   // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 349873 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i16),
     /* 349878 */   GIR_RootConstrainSelectedInstOperands,
     /* 349879 */   // GIR_Coverage, 1540,
     /* 349879 */   GIR_Done,
     /* 349880 */ // Label 7004: @349880
     /* 349880 */ GIM_Reject,
     /* 349881 */ // Label 6992: @349881
     /* 349881 */ GIM_Try, /*On fail goto*//*Label 7005*/ GIMT_Encode4(349914), // Rule ID 1538 //
     /* 349886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 349892 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 349895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349899 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349903 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349907 */   // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 349907 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv16i8),
     /* 349912 */   GIR_RootConstrainSelectedInstOperands,
     /* 349913 */   // GIR_Coverage, 1538,
     /* 349913 */   GIR_Done,
     /* 349914 */ // Label 7005: @349914
     /* 349914 */ GIM_Reject,
     /* 349915 */ // Label 6993: @349915
     /* 349915 */ GIM_Reject,
     /* 349916 */ // Label 85: @349916
     /* 349916 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7014*/ GIMT_Encode4(350319),
     /* 349927 */ /*GILLT_s32*//*Label 7006*/ GIMT_Encode4(349967),
     /* 349931 */ /*GILLT_s64*//*Label 7007*/ GIMT_Encode4(350041), GIMT_Encode4(0),
     /* 349939 */ /*GILLT_v2s32*//*Label 7008*/ GIMT_Encode4(350115), GIMT_Encode4(0),
     /* 349947 */ /*GILLT_v4s16*//*Label 7009*/ GIMT_Encode4(350149),
     /* 349951 */ /*GILLT_v4s32*//*Label 7010*/ GIMT_Encode4(350183),
     /* 349955 */ /*GILLT_v8s8*//*Label 7011*/ GIMT_Encode4(350217),
     /* 349959 */ /*GILLT_v8s16*//*Label 7012*/ GIMT_Encode4(350251),
     /* 349963 */ /*GILLT_v16s8*//*Label 7013*/ GIMT_Encode4(350285),
     /* 349967 */ // Label 7006: @349967
     /* 349967 */ GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(350040),
     /* 349972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 349975 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 349978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349982 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 349986 */   GIM_Try, /*On fail goto*//*Label 7016*/ GIMT_Encode4(350020), // Rule ID 2336 //
     /* 349991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 349994 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349998 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 350002 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
     /* 350006 */     // MIs[1] Operand 1
     /* 350006 */     // No operand predicates
     /* 350006 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350008 */     // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm)  =>  (UMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 350008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXWri),
     /* 350011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350013 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350015 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 350018 */     GIR_RootConstrainSelectedInstOperands,
     /* 350019 */     // GIR_Coverage, 2336,
     /* 350019 */     GIR_EraseRootFromParent_Done,
     /* 350020 */   // Label 7016: @350020
     /* 350020 */   GIM_Try, /*On fail goto*//*Label 7017*/ GIMT_Encode4(350039), // Rule ID 2335 //
     /* 350025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 350028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 350032 */     // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 350032 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXWrr),
     /* 350037 */     GIR_RootConstrainSelectedInstOperands,
     /* 350038 */     // GIR_Coverage, 2335,
     /* 350038 */     GIR_Done,
     /* 350039 */   // Label 7017: @350039
     /* 350039 */   GIM_Reject,
     /* 350040 */ // Label 7015: @350040
     /* 350040 */ GIM_Reject,
     /* 350041 */ // Label 7007: @350041
     /* 350041 */ GIM_Try, /*On fail goto*//*Label 7018*/ GIMT_Encode4(350114),
     /* 350046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 350049 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 350052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 350056 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 350060 */   GIM_Try, /*On fail goto*//*Label 7019*/ GIMT_Encode4(350094), // Rule ID 2338 //
     /* 350065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 350068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 350072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 350076 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
     /* 350080 */     // MIs[1] Operand 1
     /* 350080 */     // No operand predicates
     /* 350080 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350082 */     // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm)  =>  (UMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 350082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXXri),
     /* 350085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350087 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350089 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 350092 */     GIR_RootConstrainSelectedInstOperands,
     /* 350093 */     // GIR_Coverage, 2338,
     /* 350093 */     GIR_EraseRootFromParent_Done,
     /* 350094 */   // Label 7019: @350094
     /* 350094 */   GIM_Try, /*On fail goto*//*Label 7020*/ GIMT_Encode4(350113), // Rule ID 2337 //
     /* 350099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 350102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 350106 */     // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 350106 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXXrr),
     /* 350111 */     GIR_RootConstrainSelectedInstOperands,
     /* 350112 */     // GIR_Coverage, 2337,
     /* 350112 */     GIR_Done,
     /* 350113 */   // Label 7020: @350113
     /* 350113 */   GIM_Reject,
     /* 350114 */ // Label 7018: @350114
     /* 350114 */ GIM_Reject,
     /* 350115 */ // Label 7008: @350115
     /* 350115 */ GIM_Try, /*On fail goto*//*Label 7021*/ GIMT_Encode4(350148), // Rule ID 1529 //
     /* 350120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350126 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 350129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350133 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350137 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350141 */   // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 350141 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv2i32),
     /* 350146 */   GIR_RootConstrainSelectedInstOperands,
     /* 350147 */   // GIR_Coverage, 1529,
     /* 350147 */   GIR_Done,
     /* 350148 */ // Label 7021: @350148
     /* 350148 */ GIM_Reject,
     /* 350149 */ // Label 7009: @350149
     /* 350149 */ GIM_Try, /*On fail goto*//*Label 7022*/ GIMT_Encode4(350182), // Rule ID 1527 //
     /* 350154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350157 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350160 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 350163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350167 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350171 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350175 */   // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 350175 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i16),
     /* 350180 */   GIR_RootConstrainSelectedInstOperands,
     /* 350181 */   // GIR_Coverage, 1527,
     /* 350181 */   GIR_Done,
     /* 350182 */ // Label 7022: @350182
     /* 350182 */ GIM_Reject,
     /* 350183 */ // Label 7010: @350183
     /* 350183 */ GIM_Try, /*On fail goto*//*Label 7023*/ GIMT_Encode4(350216), // Rule ID 1530 //
     /* 350188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350191 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 350194 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 350197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350201 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350205 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350209 */   // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 350209 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i32),
     /* 350214 */   GIR_RootConstrainSelectedInstOperands,
     /* 350215 */   // GIR_Coverage, 1530,
     /* 350215 */   GIR_Done,
     /* 350216 */ // Label 7023: @350216
     /* 350216 */ GIM_Reject,
     /* 350217 */ // Label 7011: @350217
     /* 350217 */ GIM_Try, /*On fail goto*//*Label 7024*/ GIMT_Encode4(350250), // Rule ID 1525 //
     /* 350222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350225 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 350228 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 350231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350235 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350239 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350243 */   // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 350243 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i8),
     /* 350248 */   GIR_RootConstrainSelectedInstOperands,
     /* 350249 */   // GIR_Coverage, 1525,
     /* 350249 */   GIR_Done,
     /* 350250 */ // Label 7024: @350250
     /* 350250 */ GIM_Reject,
     /* 350251 */ // Label 7012: @350251
     /* 350251 */ GIM_Try, /*On fail goto*//*Label 7025*/ GIMT_Encode4(350284), // Rule ID 1528 //
     /* 350256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350262 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 350265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350269 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350273 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350277 */   // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 350277 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i16),
     /* 350282 */   GIR_RootConstrainSelectedInstOperands,
     /* 350283 */   // GIR_Coverage, 1528,
     /* 350283 */   GIR_Done,
     /* 350284 */ // Label 7025: @350284
     /* 350284 */ GIM_Reject,
     /* 350285 */ // Label 7013: @350285
     /* 350285 */ GIM_Try, /*On fail goto*//*Label 7026*/ GIMT_Encode4(350318), // Rule ID 1526 //
     /* 350290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 350296 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 350299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350303 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350307 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350311 */   // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 350311 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv16i8),
     /* 350316 */   GIR_RootConstrainSelectedInstOperands,
     /* 350317 */   // GIR_Coverage, 1526,
     /* 350317 */   GIR_Done,
     /* 350318 */ // Label 7026: @350318
     /* 350318 */ GIM_Reject,
     /* 350319 */ // Label 7014: @350319
     /* 350319 */ GIM_Reject,
     /* 350320 */ // Label 86: @350320
     /* 350320 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7036*/ GIMT_Encode4(351134),
     /* 350331 */ /*GILLT_s32*//*Label 7027*/ GIMT_Encode4(350371),
     /* 350335 */ /*GILLT_s64*//*Label 7028*/ GIMT_Encode4(350398), GIMT_Encode4(0),
     /* 350343 */ /*GILLT_v2s32*//*Label 7029*/ GIMT_Encode4(350477),
     /* 350347 */ /*GILLT_v2s64*//*Label 7030*/ GIMT_Encode4(350504),
     /* 350351 */ /*GILLT_v4s16*//*Label 7031*/ GIMT_Encode4(350687),
     /* 350355 */ /*GILLT_v4s32*//*Label 7032*/ GIMT_Encode4(350714),
     /* 350359 */ /*GILLT_v8s8*//*Label 7033*/ GIMT_Encode4(350897),
     /* 350363 */ /*GILLT_v8s16*//*Label 7034*/ GIMT_Encode4(350924),
     /* 350367 */ /*GILLT_v16s8*//*Label 7035*/ GIMT_Encode4(351107),
     /* 350371 */ // Label 7027: @350371
     /* 350371 */ GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(350397), // Rule ID 2321 //
     /* 350376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 350379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 350382 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 350386 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 350390 */   // (abs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (ABSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 350390 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSWr),
     /* 350395 */   GIR_RootConstrainSelectedInstOperands,
     /* 350396 */   // GIR_Coverage, 2321,
     /* 350396 */   GIR_Done,
     /* 350397 */ // Label 7037: @350397
     /* 350397 */ GIM_Reject,
     /* 350398 */ // Label 7028: @350398
     /* 350398 */ GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(350476),
     /* 350403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 350406 */   GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(350429), // Rule ID 1656 //
     /* 350411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350422 */     // (abs:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)  =>  (ABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 350422 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
     /* 350427 */     GIR_RootConstrainSelectedInstOperands,
     /* 350428 */     // GIR_Coverage, 1656,
     /* 350428 */     GIR_Done,
     /* 350429 */   // Label 7039: @350429
     /* 350429 */   GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(350452), // Rule ID 2322 //
     /* 350434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 350437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 350441 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 350445 */     // (abs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (ABSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 350445 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSXr),
     /* 350450 */     GIR_RootConstrainSelectedInstOperands,
     /* 350451 */     // GIR_Coverage, 2322,
     /* 350451 */     GIR_Done,
     /* 350452 */   // Label 7040: @350452
     /* 350452 */   GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(350475), // Rule ID 2514 //
     /* 350457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCSSC),
     /* 350460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350464 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350468 */     // (abs:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)  =>  (ABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 350468 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
     /* 350473 */     GIR_RootConstrainSelectedInstOperands,
     /* 350474 */     // GIR_Coverage, 2514,
     /* 350474 */     GIR_Done,
     /* 350475 */   // Label 7041: @350475
     /* 350475 */   GIM_Reject,
     /* 350476 */ // Label 7038: @350476
     /* 350476 */ GIM_Reject,
     /* 350477 */ // Label 7029: @350477
     /* 350477 */ GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(350503), // Rule ID 711 //
     /* 350482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350492 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350496 */   // (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (ABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 350496 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i32),
     /* 350501 */   GIR_RootConstrainSelectedInstOperands,
     /* 350502 */   // GIR_Coverage, 711,
     /* 350502 */   GIR_Done,
     /* 350503 */ // Label 7042: @350503
     /* 350503 */ GIM_Reject,
     /* 350504 */ // Label 7030: @350504
     /* 350504 */ GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(350686),
     /* 350509 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 350512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350516 */   GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(350594), // Rule ID 4958 //
     /* 350521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 350529 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 350533 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 350537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350545 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350549 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 350553 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350557 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350561 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350563 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 350570 */     GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 350577 */     // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$opA)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$opB))))  =>  (UABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$opA, V128:{ *:[v4i32] }:$opB)
     /* 350577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i32_v2i64),
     /* 350580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
     /* 350587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
     /* 350592 */     GIR_RootConstrainSelectedInstOperands,
     /* 350593 */     // GIR_Coverage, 4958,
     /* 350593 */     GIR_EraseRootFromParent_Done,
     /* 350594 */   // Label 7044: @350594
     /* 350594 */   GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(350666), // Rule ID 4957 //
     /* 350599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 350607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 350611 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 350615 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350619 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350623 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350627 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350632 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 350636 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350640 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 350644 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350649 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350651 */     // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opB)))  =>  (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA, V64:{ *:[v2i32] }:$opB)
     /* 350651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv2i32_v2i64),
     /* 350654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
     /* 350660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
     /* 350664 */     GIR_RootConstrainSelectedInstOperands,
     /* 350665 */     // GIR_Coverage, 4957,
     /* 350665 */     GIR_EraseRootFromParent_Done,
     /* 350666 */   // Label 7045: @350666
     /* 350666 */   GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(350685), // Rule ID 713 //
     /* 350671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350678 */     // (abs:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)  =>  (ABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 350678 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i64),
     /* 350683 */     GIR_RootConstrainSelectedInstOperands,
     /* 350684 */     // GIR_Coverage, 713,
     /* 350684 */     GIR_Done,
     /* 350685 */   // Label 7046: @350685
     /* 350685 */   GIM_Reject,
     /* 350686 */ // Label 7043: @350686
     /* 350686 */ GIM_Reject,
     /* 350687 */ // Label 7031: @350687
     /* 350687 */ GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(350713), // Rule ID 709 //
     /* 350692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350702 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350706 */   // (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (ABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 350706 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i16),
     /* 350711 */   GIR_RootConstrainSelectedInstOperands,
     /* 350712 */   // GIR_Coverage, 709,
     /* 350712 */   GIR_Done,
     /* 350713 */ // Label 7047: @350713
     /* 350713 */ GIM_Reject,
     /* 350714 */ // Label 7032: @350714
     /* 350714 */ GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(350896),
     /* 350719 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 350722 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350726 */   GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(350804), // Rule ID 4956 //
     /* 350731 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350735 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 350739 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 350743 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 350747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350755 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350759 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 350763 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350767 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350771 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350773 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 350780 */     GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 350787 */     // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$opA)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$opB))))  =>  (UABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$opA, V128:{ *:[v8i16] }:$opB)
     /* 350787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i16_v4i32),
     /* 350790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
     /* 350797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
     /* 350802 */     GIR_RootConstrainSelectedInstOperands,
     /* 350803 */     // GIR_Coverage, 4956,
     /* 350803 */     GIR_EraseRootFromParent_Done,
     /* 350804 */   // Label 7049: @350804
     /* 350804 */   GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(350876), // Rule ID 4955 //
     /* 350809 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350813 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 350817 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 350821 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 350825 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350829 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350833 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350837 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350842 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 350846 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350850 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 350854 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350859 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350861 */     // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opB)))  =>  (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA, V64:{ *:[v4i16] }:$opB)
     /* 350861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i16_v4i32),
     /* 350864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 350866 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
     /* 350870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
     /* 350874 */     GIR_RootConstrainSelectedInstOperands,
     /* 350875 */     // GIR_Coverage, 4955,
     /* 350875 */     GIR_EraseRootFromParent_Done,
     /* 350876 */   // Label 7050: @350876
     /* 350876 */   GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(350895), // Rule ID 712 //
     /* 350881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350884 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350888 */     // (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (ABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 350888 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i32),
     /* 350893 */     GIR_RootConstrainSelectedInstOperands,
     /* 350894 */     // GIR_Coverage, 712,
     /* 350894 */     GIR_Done,
     /* 350895 */   // Label 7051: @350895
     /* 350895 */   GIM_Reject,
     /* 350896 */ // Label 7048: @350896
     /* 350896 */ GIM_Reject,
     /* 350897 */ // Label 7033: @350897
     /* 350897 */ GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(350923), // Rule ID 707 //
     /* 350902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 350905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 350908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350912 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 350916 */   // (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (ABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 350916 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i8),
     /* 350921 */   GIR_RootConstrainSelectedInstOperands,
     /* 350922 */   // GIR_Coverage, 707,
     /* 350922 */   GIR_Done,
     /* 350923 */ // Label 7052: @350923
     /* 350923 */ GIM_Reject,
     /* 350924 */ // Label 7034: @350924
     /* 350924 */ GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(351106),
     /* 350929 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350936 */   GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(351014), // Rule ID 4954 //
     /* 350941 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350945 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 350949 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350953 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 350957 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350961 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350965 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 350969 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 350973 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 350977 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 350981 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350983 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 350990 */     GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 350997 */     // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$opA)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$opB))))  =>  (UABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$opA, V128:{ *:[v16i8] }:$opB)
     /* 350997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv16i8_v8i16),
     /* 351000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
     /* 351007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
     /* 351012 */     GIR_RootConstrainSelectedInstOperands,
     /* 351013 */     // GIR_Coverage, 4954,
     /* 351013 */     GIR_EraseRootFromParent_Done,
     /* 351014 */   // Label 7054: @351014
     /* 351014 */   GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(351086), // Rule ID 4953 //
     /* 351019 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351023 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 351027 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351031 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 351035 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 351039 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 351043 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 351047 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351052 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 351056 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 351060 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 351064 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351069 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 351071 */     // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)))  =>  (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB)
     /* 351071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i8_v8i16),
     /* 351074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351076 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
     /* 351080 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
     /* 351084 */     GIR_RootConstrainSelectedInstOperands,
     /* 351085 */     // GIR_Coverage, 4953,
     /* 351085 */     GIR_EraseRootFromParent_Done,
     /* 351086 */   // Label 7055: @351086
     /* 351086 */   GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(351105), // Rule ID 710 //
     /* 351091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 351094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351098 */     // (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (ABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 351098 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i16),
     /* 351103 */     GIR_RootConstrainSelectedInstOperands,
     /* 351104 */     // GIR_Coverage, 710,
     /* 351104 */     GIR_Done,
     /* 351105 */   // Label 7056: @351105
     /* 351105 */   GIM_Reject,
     /* 351106 */ // Label 7053: @351106
     /* 351106 */ GIM_Reject,
     /* 351107 */ // Label 7035: @351107
     /* 351107 */ GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(351133), // Rule ID 708 //
     /* 351112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 351115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 351118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351122 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351126 */   // (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (ABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 351126 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv16i8),
     /* 351131 */   GIR_RootConstrainSelectedInstOperands,
     /* 351132 */   // GIR_Coverage, 708,
     /* 351132 */   GIR_Done,
     /* 351133 */ // Label 7057: @351133
     /* 351133 */ GIM_Reject,
     /* 351134 */ // Label 7036: @351134
     /* 351134 */ GIM_Reject,
     /* 351135 */ // Label 87: @351135
     /* 351135 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 7060*/ GIMT_Encode4(351300),
     /* 351146 */ /*GILLT_s32*//*Label 7058*/ GIMT_Encode4(351154),
     /* 351150 */ /*GILLT_s64*//*Label 7059*/ GIMT_Encode4(351227),
     /* 351154 */ // Label 7058: @351154
     /* 351154 */ GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(351180), // Rule ID 4799 //
     /* 351159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351162 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 351165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 351169 */   // (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 351169 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
     /* 351174 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351178 */   GIR_RootConstrainSelectedInstOperands,
     /* 351179 */   // GIR_Coverage, 4799,
     /* 351179 */   GIR_Done,
     /* 351180 */ // Label 7061: @351180
     /* 351180 */ GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(351203), // Rule ID 4805 //
     /* 351185 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 351188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 351192 */   // (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 351192 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 351197 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351201 */   GIR_RootConstrainSelectedInstOperands,
     /* 351202 */   // GIR_Coverage, 4805,
     /* 351202 */   GIR_Done,
     /* 351203 */ // Label 7062: @351203
     /* 351203 */ GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(351226), // Rule ID 4807 //
     /* 351208 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 351211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 351215 */   // (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 351215 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 351220 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351224 */   GIR_RootConstrainSelectedInstOperands,
     /* 351225 */   // GIR_Coverage, 4807,
     /* 351225 */   GIR_Done,
     /* 351226 */ // Label 7063: @351226
     /* 351226 */ GIM_Reject,
     /* 351227 */ // Label 7059: @351227
     /* 351227 */ GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(351253), // Rule ID 4801 //
     /* 351232 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351235 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 351238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351242 */   // (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 351242 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 351247 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351251 */   GIR_RootConstrainSelectedInstOperands,
     /* 351252 */   // GIR_Coverage, 4801,
     /* 351252 */   GIR_Done,
     /* 351253 */ // Label 7064: @351253
     /* 351253 */ GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(351276), // Rule ID 4809 //
     /* 351258 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 351261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351265 */   // (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 351265 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 351270 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351274 */   GIR_RootConstrainSelectedInstOperands,
     /* 351275 */   // GIR_Coverage, 4809,
     /* 351275 */   GIR_Done,
     /* 351276 */ // Label 7065: @351276
     /* 351276 */ GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(351299), // Rule ID 4811 //
     /* 351281 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 351284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351288 */   // (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 351288 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 351293 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351297 */   GIR_RootConstrainSelectedInstOperands,
     /* 351298 */   // GIR_Coverage, 4811,
     /* 351298 */   GIR_Done,
     /* 351299 */ // Label 7066: @351299
     /* 351299 */ GIM_Reject,
     /* 351300 */ // Label 7060: @351300
     /* 351300 */ GIM_Reject,
     /* 351301 */ // Label 88: @351301
     /* 351301 */ GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(351399),
     /* 351306 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 351309 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7071*/ GIMT_Encode4(351398),
     /* 351320 */   /*GILLT_s16*//*Label 7068*/ GIMT_Encode4(351332),
     /* 351324 */   /*GILLT_s32*//*Label 7069*/ GIMT_Encode4(351356),
     /* 351328 */   /*GILLT_s64*//*Label 7070*/ GIMT_Encode4(351377),
     /* 351332 */   // Label 7068: @351332
     /* 351332 */   GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(351355), // Rule ID 4803 //
     /* 351337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351344 */     // (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 351344 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 351349 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351353 */     GIR_RootConstrainSelectedInstOperands,
     /* 351354 */     // GIR_Coverage, 4803,
     /* 351354 */     GIR_Done,
     /* 351355 */   // Label 7072: @351355
     /* 351355 */   GIM_Reject,
     /* 351356 */   // Label 7069: @351356
     /* 351356 */   GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(351376), // Rule ID 4813 //
     /* 351361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351365 */     // (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 351365 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 351370 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351374 */     GIR_RootConstrainSelectedInstOperands,
     /* 351375 */     // GIR_Coverage, 4813,
     /* 351375 */     GIR_Done,
     /* 351376 */   // Label 7073: @351376
     /* 351376 */   GIM_Reject,
     /* 351377 */   // Label 7070: @351377
     /* 351377 */   GIM_Try, /*On fail goto*//*Label 7074*/ GIMT_Encode4(351397), // Rule ID 4815 //
     /* 351382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 351386 */     // (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 351386 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 351391 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351395 */     GIR_RootConstrainSelectedInstOperands,
     /* 351396 */     // GIR_Coverage, 4815,
     /* 351396 */     GIR_Done,
     /* 351397 */   // Label 7074: @351397
     /* 351397 */   GIM_Reject,
     /* 351398 */   // Label 7071: @351398
     /* 351398 */   GIM_Reject,
     /* 351399 */ // Label 7067: @351399
     /* 351399 */ GIM_Reject,
     /* 351400 */ // Label 89: @351400
     /* 351400 */ GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(351415), // Rule ID 229 //
     /* 351405 */   // MIs[0] addr
     /* 351405 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
     /* 351408 */   // (br (bb:{ *:[Other] }):$addr)  =>  (B (bb:{ *:[Other] }):$addr)
     /* 351408 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::B),
     /* 351413 */   GIR_RootConstrainSelectedInstOperands,
     /* 351414 */   // GIR_Coverage, 229,
     /* 351414 */   GIR_Done,
     /* 351415 */ // Label 7075: @351415
     /* 351415 */ GIM_Reject,
     /* 351416 */ // Label 90: @351416
     /* 351416 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(21), /*)*//*default:*//*Label 7087*/ GIMT_Encode4(356787),
     /* 351427 */ /*GILLT_s64*//*Label 7076*/ GIMT_Encode4(351499), GIMT_Encode4(0),
     /* 351435 */ /*GILLT_v2s32*//*Label 7077*/ GIMT_Encode4(351901), GIMT_Encode4(0),
     /* 351443 */ /*GILLT_v4s16*//*Label 7078*/ GIMT_Encode4(352303), GIMT_Encode4(0),
     /* 351451 */ /*GILLT_v8s8*//*Label 7079*/ GIMT_Encode4(352705), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 351463 */ /*GILLT_nxv1s1*//*Label 7080*/ GIMT_Encode4(352885),
     /* 351467 */ /*GILLT_nxv2s1*//*Label 7081*/ GIMT_Encode4(355148),
     /* 351471 */ /*GILLT_nxv2s16*//*Label 7082*/ GIMT_Encode4(356003),
     /* 351475 */ /*GILLT_nxv2s32*//*Label 7083*/ GIMT_Encode4(356290), GIMT_Encode4(0),
     /* 351483 */ /*GILLT_nxv4s1*//*Label 7084*/ GIMT_Encode4(356360),
     /* 351487 */ /*GILLT_nxv4s16*//*Label 7085*/ GIMT_Encode4(356647), GIMT_Encode4(0),
     /* 351495 */ /*GILLT_nxv8s1*//*Label 7086*/ GIMT_Encode4(356717),
     /* 351499 */ // Label 7076: @351499
     /* 351499 */ GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(351900),
     /* 351504 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 351507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351511 */   GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(351563), // Rule ID 5628 //
     /* 351516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 351524 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 351528 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 351530 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351535 */     // MIs[0] Operand 2
     /* 351535 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 351546 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 351548 */     // (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v2i32:{ *:[v1i64] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vn)
     /* 351548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 351551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351553 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351557 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351561 */     GIR_RootConstrainSelectedInstOperands,
     /* 351562 */     // GIR_Coverage, 5628,
     /* 351562 */     GIR_EraseRootFromParent_Done,
     /* 351563 */   // Label 7089: @351563
     /* 351563 */   GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(351615), // Rule ID 5631 //
     /* 351568 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351572 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 351576 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 351580 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 351582 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351587 */     // MIs[0] Operand 2
     /* 351587 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 351598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 351600 */     // (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Vn)<<P:Predicate_anyext_oneuse>>, 1:{ *:[i64] })  =>  (ZIP2v2i32:{ *:[v1i64] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vn)
     /* 351600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 351603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351613 */     GIR_RootConstrainSelectedInstOperands,
     /* 351614 */     // GIR_Coverage, 5631,
     /* 351614 */     GIR_EraseRootFromParent_Done,
     /* 351615 */   // Label 7090: @351615
     /* 351615 */   GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(351683), // Rule ID 5507 //
     /* 351620 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351624 */     // MIs[0] Operand 2
     /* 351624 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 351635 */     // (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 351635 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 351638 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 351642 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351647 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351651 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351655 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 351658 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 351660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351665 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 351672 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351677 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351682 */     // GIR_Coverage, 5507,
     /* 351682 */     GIR_EraseRootFromParent_Done,
     /* 351683 */   // Label 7091: @351683
     /* 351683 */   GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(351751), // Rule ID 5512 //
     /* 351688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351692 */     // MIs[0] Operand 2
     /* 351692 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 351703 */     // (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 351703 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 351706 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 351710 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351715 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351719 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351723 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 351726 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 351728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351733 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 351740 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351745 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351750 */     // GIR_Coverage, 5512,
     /* 351750 */     GIR_EraseRootFromParent_Done,
     /* 351751 */   // Label 7092: @351751
     /* 351751 */   GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(351793), // Rule ID 6969 //
     /* 351756 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351760 */     // MIs[0] Operand 2
     /* 351760 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 351771 */     // (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] })
     /* 351771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351776 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 351782 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351787 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351792 */     // GIR_Coverage, 6969,
     /* 351792 */     GIR_EraseRootFromParent_Done,
     /* 351793 */   // Label 7093: @351793
     /* 351793 */   GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(351835), // Rule ID 6970 //
     /* 351798 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351802 */     // MIs[0] Operand 2
     /* 351802 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 351813 */     // (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] })
     /* 351813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351818 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 351824 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351829 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351834 */     // GIR_Coverage, 6970,
     /* 351834 */     GIR_EraseRootFromParent_Done,
     /* 351835 */   // Label 7094: @351835
     /* 351835 */   GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(351899), // Rule ID 6974 //
     /* 351840 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351844 */     // MIs[0] Operand 2
     /* 351844 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 351855 */     // (extract_subvector:{ *:[v1i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 351855 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 351858 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 351862 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351867 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351871 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 351874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 351876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351881 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 351888 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351893 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351898 */     // GIR_Coverage, 6974,
     /* 351898 */     GIR_EraseRootFromParent_Done,
     /* 351899 */   // Label 7095: @351899
     /* 351899 */   GIM_Reject,
     /* 351900 */ // Label 7088: @351900
     /* 351900 */ GIM_Reject,
     /* 351901 */ // Label 7077: @351901
     /* 351901 */ GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(352302),
     /* 351906 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 351909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351913 */   GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(351965), // Rule ID 5627 //
     /* 351918 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351922 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 351926 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 351930 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 351932 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351937 */     // MIs[0] Operand 2
     /* 351937 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 351948 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 351950 */     // (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v4i16:{ *:[v2i32] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vn)
     /* 351950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 351953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351955 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351959 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 351963 */     GIR_RootConstrainSelectedInstOperands,
     /* 351964 */     // GIR_Coverage, 5627,
     /* 351964 */     GIR_EraseRootFromParent_Done,
     /* 351965 */   // Label 7097: @351965
     /* 351965 */   GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(352017), // Rule ID 5630 //
     /* 351970 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351974 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 351978 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 351982 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 351984 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351989 */     // MIs[0] Operand 2
     /* 351989 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 352000 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352002 */     // (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Vn)<<P:Predicate_anyext_oneuse>>, 2:{ *:[i64] })  =>  (ZIP2v4i16:{ *:[v2i32] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vn)
     /* 352002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 352005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352011 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352015 */     GIR_RootConstrainSelectedInstOperands,
     /* 352016 */     // GIR_Coverage, 5630,
     /* 352016 */     GIR_EraseRootFromParent_Done,
     /* 352017 */   // Label 7098: @352017
     /* 352017 */   GIM_Try, /*On fail goto*//*Label 7099*/ GIMT_Encode4(352085), // Rule ID 5497 //
     /* 352022 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352026 */     // MIs[0] Operand 2
     /* 352026 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 352037 */     // (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 352037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352040 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 352044 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352049 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352053 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352057 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 352060 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352067 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352074 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352079 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352084 */     // GIR_Coverage, 5497,
     /* 352084 */     GIR_EraseRootFromParent_Done,
     /* 352085 */   // Label 7099: @352085
     /* 352085 */   GIM_Try, /*On fail goto*//*Label 7100*/ GIMT_Encode4(352153), // Rule ID 5502 //
     /* 352090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352094 */     // MIs[0] Operand 2
     /* 352094 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 352105 */     // (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 352105 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352108 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 352112 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352117 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352121 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352125 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 352128 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352135 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352142 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352147 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352152 */     // GIR_Coverage, 5502,
     /* 352152 */     GIR_EraseRootFromParent_Done,
     /* 352153 */   // Label 7100: @352153
     /* 352153 */   GIM_Try, /*On fail goto*//*Label 7101*/ GIMT_Encode4(352195), // Rule ID 6966 //
     /* 352158 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352162 */     // MIs[0] Operand 2
     /* 352162 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352173 */     // (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })
     /* 352173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352178 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 352184 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352189 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352194 */     // GIR_Coverage, 6966,
     /* 352194 */     GIR_EraseRootFromParent_Done,
     /* 352195 */   // Label 7101: @352195
     /* 352195 */   GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(352237), // Rule ID 6968 //
     /* 352200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352204 */     // MIs[0] Operand 2
     /* 352204 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352215 */     // (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] })
     /* 352215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352220 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 352226 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352231 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352236 */     // GIR_Coverage, 6968,
     /* 352236 */     GIR_EraseRootFromParent_Done,
     /* 352237 */   // Label 7102: @352237
     /* 352237 */   GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(352301), // Rule ID 6973 //
     /* 352242 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352246 */     // MIs[0] Operand 2
     /* 352246 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 352257 */     // (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 352257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 352264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352269 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352273 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 352276 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352283 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352290 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352295 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352300 */     // GIR_Coverage, 6973,
     /* 352300 */     GIR_EraseRootFromParent_Done,
     /* 352301 */   // Label 7103: @352301
     /* 352301 */   GIM_Reject,
     /* 352302 */ // Label 7096: @352302
     /* 352302 */ GIM_Reject,
     /* 352303 */ // Label 7078: @352303
     /* 352303 */ GIM_Try, /*On fail goto*//*Label 7104*/ GIMT_Encode4(352704),
     /* 352308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 352311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352315 */   GIM_Try, /*On fail goto*//*Label 7105*/ GIMT_Encode4(352367), // Rule ID 5626 //
     /* 352320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 352328 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 352332 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 352334 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352339 */     // MIs[0] Operand 2
     /* 352339 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352350 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352352 */     // (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v8i8:{ *:[v4i16] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vn)
     /* 352352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i8),
     /* 352355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352365 */     GIR_RootConstrainSelectedInstOperands,
     /* 352366 */     // GIR_Coverage, 5626,
     /* 352366 */     GIR_EraseRootFromParent_Done,
     /* 352367 */   // Label 7105: @352367
     /* 352367 */   GIM_Try, /*On fail goto*//*Label 7106*/ GIMT_Encode4(352419), // Rule ID 5629 //
     /* 352372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 352380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 352384 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 352386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352391 */     // MIs[0] Operand 2
     /* 352391 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 352402 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352404 */     // (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Vn)<<P:Predicate_anyext_oneuse>>, 4:{ *:[i64] })  =>  (ZIP2v8i8:{ *:[v4i16] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vn)
     /* 352404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i8),
     /* 352407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352409 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352413 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 352417 */     GIR_RootConstrainSelectedInstOperands,
     /* 352418 */     // GIR_Coverage, 5629,
     /* 352418 */     GIR_EraseRootFromParent_Done,
     /* 352419 */   // Label 7106: @352419
     /* 352419 */   GIM_Try, /*On fail goto*//*Label 7107*/ GIMT_Encode4(352487), // Rule ID 5487 //
     /* 352424 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352428 */     // MIs[0] Operand 2
     /* 352428 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 352439 */     // (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 352439 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352442 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 352446 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352451 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352455 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352459 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 352462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352469 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352486 */     // GIR_Coverage, 5487,
     /* 352486 */     GIR_EraseRootFromParent_Done,
     /* 352487 */   // Label 7107: @352487
     /* 352487 */   GIM_Try, /*On fail goto*//*Label 7108*/ GIMT_Encode4(352555), // Rule ID 5492 //
     /* 352492 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352496 */     // MIs[0] Operand 2
     /* 352496 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 352507 */     // (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 352507 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352510 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 352514 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352523 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352527 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 352530 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352537 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352544 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352554 */     // GIR_Coverage, 5492,
     /* 352554 */     GIR_EraseRootFromParent_Done,
     /* 352555 */   // Label 7108: @352555
     /* 352555 */   GIM_Try, /*On fail goto*//*Label 7109*/ GIMT_Encode4(352597), // Rule ID 6964 //
     /* 352560 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352564 */     // MIs[0] Operand 2
     /* 352564 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352575 */     // (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] })
     /* 352575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352580 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 352586 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352591 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352596 */     // GIR_Coverage, 6964,
     /* 352596 */     GIR_EraseRootFromParent_Done,
     /* 352597 */   // Label 7109: @352597
     /* 352597 */   GIM_Try, /*On fail goto*//*Label 7110*/ GIMT_Encode4(352639), // Rule ID 6967 //
     /* 352602 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352606 */     // MIs[0] Operand 2
     /* 352606 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352617 */     // (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })
     /* 352617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352622 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 352628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352633 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352638 */     // GIR_Coverage, 6967,
     /* 352638 */     GIR_EraseRootFromParent_Done,
     /* 352639 */   // Label 7110: @352639
     /* 352639 */   GIM_Try, /*On fail goto*//*Label 7111*/ GIMT_Encode4(352703), // Rule ID 6972 //
     /* 352644 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352648 */     // MIs[0] Operand 2
     /* 352648 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 352659 */     // (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 352659 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352662 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 352666 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352671 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352675 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 352678 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352685 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352692 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352697 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352702 */     // GIR_Coverage, 6972,
     /* 352702 */     GIR_EraseRootFromParent_Done,
     /* 352703 */   // Label 7111: @352703
     /* 352703 */   GIM_Reject,
     /* 352704 */ // Label 7104: @352704
     /* 352704 */ GIM_Reject,
     /* 352705 */ // Label 7079: @352705
     /* 352705 */ GIM_Try, /*On fail goto*//*Label 7112*/ GIMT_Encode4(352884),
     /* 352710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 352713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352717 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352721 */   GIM_Try, /*On fail goto*//*Label 7113*/ GIMT_Encode4(352785), // Rule ID 5482 //
     /* 352726 */     // MIs[0] Operand 2
     /* 352726 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 352737 */     // (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EXTv16i8:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 352737 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352740 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 352744 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352749 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352753 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352757 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 352760 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352767 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352774 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352779 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352784 */     // GIR_Coverage, 5482,
     /* 352784 */     GIR_EraseRootFromParent_Done,
     /* 352785 */   // Label 7113: @352785
     /* 352785 */   GIM_Try, /*On fail goto*//*Label 7114*/ GIMT_Encode4(352823), // Rule ID 6965 //
     /* 352790 */     // MIs[0] Operand 2
     /* 352790 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352801 */     // (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] })
     /* 352801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352806 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 352812 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352817 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352822 */     // GIR_Coverage, 6965,
     /* 352822 */     GIR_EraseRootFromParent_Done,
     /* 352823 */   // Label 7114: @352823
     /* 352823 */   GIM_Try, /*On fail goto*//*Label 7115*/ GIMT_Encode4(352883), // Rule ID 6971 //
     /* 352828 */     // MIs[0] Operand 2
     /* 352828 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 352839 */     // (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 352839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 352842 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 352846 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352851 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352855 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 352858 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352865 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 352872 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 352877 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352882 */     // GIR_Coverage, 6971,
     /* 352882 */     GIR_EraseRootFromParent_Done,
     /* 352883 */   // Label 7115: @352883
     /* 352883 */   GIM_Reject,
     /* 352884 */ // Label 7112: @352884
     /* 352884 */ GIM_Reject,
     /* 352885 */ // Label 7080: @352885
     /* 352885 */ GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(352920), // Rule ID 9094 //
     /* 352890 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 352893 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 352896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 352900 */   // MIs[0] Operand 2
     /* 352900 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352911 */   // (extract_subvector:{ *:[nxv1i1] } nxv2i1:{ *:[nxv2i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv2i1] }:$Ps)
     /* 352911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 352914 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 352916 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 352918 */   GIR_RootConstrainSelectedInstOperands,
     /* 352919 */   // GIR_Coverage, 9094,
     /* 352919 */   GIR_EraseRootFromParent_Done,
     /* 352920 */ // Label 7116: @352920
     /* 352920 */ GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(352955), // Rule ID 9095 //
     /* 352925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 352928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 352931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 352935 */   // MIs[0] Operand 2
     /* 352935 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 352946 */   // (extract_subvector:{ *:[nxv1i1] } nxv2i1:{ *:[nxv2i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv2i1] }:$Ps)
     /* 352946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 352949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 352951 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 352953 */   GIR_RootConstrainSelectedInstOperands,
     /* 352954 */   // GIR_Coverage, 9095,
     /* 352954 */   GIR_EraseRootFromParent_Done,
     /* 352955 */ // Label 7117: @352955
     /* 352955 */ GIM_Try, /*On fail goto*//*Label 7118*/ GIMT_Encode4(353009), // Rule ID 9102 //
     /* 352960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 352963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 352966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 352970 */   // MIs[0] Operand 2
     /* 352970 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 352981 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 352981 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 352984 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 352988 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352993 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 352997 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 352999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353004 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353007 */   GIR_RootConstrainSelectedInstOperands,
     /* 353008 */   // GIR_Coverage, 9102,
     /* 353008 */   GIR_EraseRootFromParent_Done,
     /* 353009 */ // Label 7118: @353009
     /* 353009 */ GIM_Try, /*On fail goto*//*Label 7119*/ GIMT_Encode4(353063), // Rule ID 9103 //
     /* 353014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353017 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 353020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353024 */   // MIs[0] Operand 2
     /* 353024 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 353035 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 353035 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353038 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353042 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353047 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353051 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353058 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353061 */   GIR_RootConstrainSelectedInstOperands,
     /* 353062 */   // GIR_Coverage, 9103,
     /* 353062 */   GIR_EraseRootFromParent_Done,
     /* 353063 */ // Label 7119: @353063
     /* 353063 */ GIM_Try, /*On fail goto*//*Label 7120*/ GIMT_Encode4(353117), // Rule ID 9104 //
     /* 353068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353071 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 353074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353078 */   // MIs[0] Operand 2
     /* 353078 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 353089 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 353089 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353092 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353096 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353101 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353112 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353115 */   GIR_RootConstrainSelectedInstOperands,
     /* 353116 */   // GIR_Coverage, 9104,
     /* 353116 */   GIR_EraseRootFromParent_Done,
     /* 353117 */ // Label 7120: @353117
     /* 353117 */ GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(353171), // Rule ID 9105 //
     /* 353122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 353128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353132 */   // MIs[0] Operand 2
     /* 353132 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 353143 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 353143 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353146 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353150 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353155 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353159 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353166 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353169 */   GIR_RootConstrainSelectedInstOperands,
     /* 353170 */   // GIR_Coverage, 9105,
     /* 353170 */   GIR_EraseRootFromParent_Done,
     /* 353171 */ // Label 7121: @353171
     /* 353171 */ GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(353242), // Rule ID 9114 //
     /* 353176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353179 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353186 */   // MIs[0] Operand 2
     /* 353186 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 353197 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353197 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353200 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353204 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353209 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353213 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353215 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353218 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353222 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353227 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353230 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353235 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353237 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353240 */   GIR_RootConstrainSelectedInstOperands,
     /* 353241 */   // GIR_Coverage, 9114,
     /* 353241 */   GIR_EraseRootFromParent_Done,
     /* 353242 */ // Label 7122: @353242
     /* 353242 */ GIM_Try, /*On fail goto*//*Label 7123*/ GIMT_Encode4(353313), // Rule ID 9115 //
     /* 353247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353257 */   // MIs[0] Operand 2
     /* 353257 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 353268 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353268 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353271 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353275 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353280 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353284 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353286 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353289 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353293 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353298 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353301 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353308 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353311 */   GIR_RootConstrainSelectedInstOperands,
     /* 353312 */   // GIR_Coverage, 9115,
     /* 353312 */   GIR_EraseRootFromParent_Done,
     /* 353313 */ // Label 7123: @353313
     /* 353313 */ GIM_Try, /*On fail goto*//*Label 7124*/ GIMT_Encode4(353384), // Rule ID 9116 //
     /* 353318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353321 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353328 */   // MIs[0] Operand 2
     /* 353328 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 353339 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353339 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353342 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353346 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353351 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353355 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353357 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353360 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353364 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353369 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353372 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353377 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353379 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353382 */   GIR_RootConstrainSelectedInstOperands,
     /* 353383 */   // GIR_Coverage, 9116,
     /* 353383 */   GIR_EraseRootFromParent_Done,
     /* 353384 */ // Label 7124: @353384
     /* 353384 */ GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(353455), // Rule ID 9117 //
     /* 353389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353392 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353399 */   // MIs[0] Operand 2
     /* 353399 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 353410 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353410 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353413 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353417 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353422 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353426 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353428 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353431 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353435 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353440 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353443 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353448 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353450 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353453 */   GIR_RootConstrainSelectedInstOperands,
     /* 353454 */   // GIR_Coverage, 9117,
     /* 353454 */   GIR_EraseRootFromParent_Done,
     /* 353455 */ // Label 7125: @353455
     /* 353455 */ GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(353526), // Rule ID 9118 //
     /* 353460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353466 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353470 */   // MIs[0] Operand 2
     /* 353470 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 353481 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353481 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353484 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353488 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353493 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353497 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353499 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353502 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353506 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353511 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353514 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353516 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353519 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353521 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353524 */   GIR_RootConstrainSelectedInstOperands,
     /* 353525 */   // GIR_Coverage, 9118,
     /* 353525 */   GIR_EraseRootFromParent_Done,
     /* 353526 */ // Label 7126: @353526
     /* 353526 */ GIM_Try, /*On fail goto*//*Label 7127*/ GIMT_Encode4(353597), // Rule ID 9119 //
     /* 353531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353534 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353541 */   // MIs[0] Operand 2
     /* 353541 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(5),
     /* 353552 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 5:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353552 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353555 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353559 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353564 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353568 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353570 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353573 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353577 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353582 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353592 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353595 */   GIR_RootConstrainSelectedInstOperands,
     /* 353596 */   // GIR_Coverage, 9119,
     /* 353596 */   GIR_EraseRootFromParent_Done,
     /* 353597 */ // Label 7127: @353597
     /* 353597 */ GIM_Try, /*On fail goto*//*Label 7128*/ GIMT_Encode4(353668), // Rule ID 9120 //
     /* 353602 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353605 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353612 */   // MIs[0] Operand 2
     /* 353612 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 353623 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353623 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353626 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353630 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353635 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353639 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353641 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353644 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353648 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353653 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353656 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353661 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353663 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353666 */   GIR_RootConstrainSelectedInstOperands,
     /* 353667 */   // GIR_Coverage, 9120,
     /* 353667 */   GIR_EraseRootFromParent_Done,
     /* 353668 */ // Label 7128: @353668
     /* 353668 */ GIM_Try, /*On fail goto*//*Label 7129*/ GIMT_Encode4(353739), // Rule ID 9121 //
     /* 353673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353676 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 353679 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353683 */   // MIs[0] Operand 2
     /* 353683 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 353694 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 7:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 353694 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353697 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353701 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353706 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353710 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353712 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353715 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353719 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353724 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353727 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353732 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353734 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353737 */   GIR_RootConstrainSelectedInstOperands,
     /* 353738 */   // GIR_Coverage, 9121,
     /* 353738 */   GIR_EraseRootFromParent_Done,
     /* 353739 */ // Label 7129: @353739
     /* 353739 */ GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(353827), // Rule ID 9130 //
     /* 353744 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353747 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 353750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353754 */   // MIs[0] Operand 2
     /* 353754 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 353765 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 353765 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 353768 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353772 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353777 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353781 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 353783 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353786 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353790 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353795 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 353798 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353812 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353815 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353820 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353822 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353825 */   GIR_RootConstrainSelectedInstOperands,
     /* 353826 */   // GIR_Coverage, 9130,
     /* 353826 */   GIR_EraseRootFromParent_Done,
     /* 353827 */ // Label 7130: @353827
     /* 353827 */ GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(353915), // Rule ID 9131 //
     /* 353832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 353838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353842 */   // MIs[0] Operand 2
     /* 353842 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 353853 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 353853 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 353856 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353860 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353865 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353869 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 353871 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353874 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353878 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353883 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 353886 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353888 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353891 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353895 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353900 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353903 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353910 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353913 */   GIR_RootConstrainSelectedInstOperands,
     /* 353914 */   // GIR_Coverage, 9131,
     /* 353914 */   GIR_EraseRootFromParent_Done,
     /* 353915 */ // Label 7131: @353915
     /* 353915 */ GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(354003), // Rule ID 9132 //
     /* 353920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 353923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 353926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 353930 */   // MIs[0] Operand 2
     /* 353930 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 353941 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 353941 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 353944 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353948 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353953 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 353957 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 353959 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 353962 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353966 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353971 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 353974 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 353976 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 353979 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 353983 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353988 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 353991 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 353993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 353996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 353998 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354001 */   GIR_RootConstrainSelectedInstOperands,
     /* 354002 */   // GIR_Coverage, 9132,
     /* 354002 */   GIR_EraseRootFromParent_Done,
     /* 354003 */ // Label 7132: @354003
     /* 354003 */ GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(354091), // Rule ID 9133 //
     /* 354008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354018 */   // MIs[0] Operand 2
     /* 354018 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 354029 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354029 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354032 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354036 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354041 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354045 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354047 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354050 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354054 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354059 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354062 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354064 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354067 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354071 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354076 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354079 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354086 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354089 */   GIR_RootConstrainSelectedInstOperands,
     /* 354090 */   // GIR_Coverage, 9133,
     /* 354090 */   GIR_EraseRootFromParent_Done,
     /* 354091 */ // Label 7133: @354091
     /* 354091 */ GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(354179), // Rule ID 9134 //
     /* 354096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354099 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354106 */   // MIs[0] Operand 2
     /* 354106 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 354117 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354117 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354120 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354124 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354129 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354133 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354135 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354138 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354142 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354147 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354150 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354152 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354155 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354159 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354164 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354167 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354174 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354177 */   GIR_RootConstrainSelectedInstOperands,
     /* 354178 */   // GIR_Coverage, 9134,
     /* 354178 */   GIR_EraseRootFromParent_Done,
     /* 354179 */ // Label 7134: @354179
     /* 354179 */ GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(354267), // Rule ID 9135 //
     /* 354184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354194 */   // MIs[0] Operand 2
     /* 354194 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(5),
     /* 354205 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 5:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354205 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354208 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354212 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354217 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354221 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354223 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354226 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354230 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354235 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354238 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354240 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354243 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354247 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354252 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354255 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354262 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354265 */   GIR_RootConstrainSelectedInstOperands,
     /* 354266 */   // GIR_Coverage, 9135,
     /* 354266 */   GIR_EraseRootFromParent_Done,
     /* 354267 */ // Label 7135: @354267
     /* 354267 */ GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(354355), // Rule ID 9136 //
     /* 354272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354275 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354282 */   // MIs[0] Operand 2
     /* 354282 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 354293 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354293 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354296 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354300 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354305 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354309 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354311 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354314 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354318 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354323 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354326 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354328 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354331 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354335 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354340 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354343 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354348 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354350 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354353 */   GIR_RootConstrainSelectedInstOperands,
     /* 354354 */   // GIR_Coverage, 9136,
     /* 354354 */   GIR_EraseRootFromParent_Done,
     /* 354355 */ // Label 7136: @354355
     /* 354355 */ GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(354443), // Rule ID 9137 //
     /* 354360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354370 */   // MIs[0] Operand 2
     /* 354370 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 354381 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 7:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354381 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354384 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354388 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354393 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354397 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354399 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354402 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354406 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354411 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354414 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354416 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354419 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354423 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354428 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354431 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354436 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354438 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354441 */   GIR_RootConstrainSelectedInstOperands,
     /* 354442 */   // GIR_Coverage, 9137,
     /* 354442 */   GIR_EraseRootFromParent_Done,
     /* 354443 */ // Label 7137: @354443
     /* 354443 */ GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(354531), // Rule ID 9138 //
     /* 354448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354458 */   // MIs[0] Operand 2
     /* 354458 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 354469 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354469 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354472 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354476 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354481 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354485 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354487 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354490 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354494 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354499 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354502 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354504 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354507 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354511 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354516 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354519 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354526 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354529 */   GIR_RootConstrainSelectedInstOperands,
     /* 354530 */   // GIR_Coverage, 9138,
     /* 354530 */   GIR_EraseRootFromParent_Done,
     /* 354531 */ // Label 7138: @354531
     /* 354531 */ GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(354619), // Rule ID 9139 //
     /* 354536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354546 */   // MIs[0] Operand 2
     /* 354546 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9),
     /* 354557 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 9:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354557 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354560 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354564 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354569 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354573 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354575 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354578 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354582 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354587 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354590 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354592 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354595 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354599 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354604 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354607 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354612 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354614 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354617 */   GIR_RootConstrainSelectedInstOperands,
     /* 354618 */   // GIR_Coverage, 9139,
     /* 354618 */   GIR_EraseRootFromParent_Done,
     /* 354619 */ // Label 7139: @354619
     /* 354619 */ GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(354707), // Rule ID 9140 //
     /* 354624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354634 */   // MIs[0] Operand 2
     /* 354634 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(10),
     /* 354645 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 10:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354645 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354648 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354652 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354657 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354661 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354663 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354666 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354670 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354675 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354678 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354680 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354683 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354687 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354692 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354695 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354702 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354705 */   GIR_RootConstrainSelectedInstOperands,
     /* 354706 */   // GIR_Coverage, 9140,
     /* 354706 */   GIR_EraseRootFromParent_Done,
     /* 354707 */ // Label 7140: @354707
     /* 354707 */ GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(354795), // Rule ID 9141 //
     /* 354712 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354715 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354718 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354722 */   // MIs[0] Operand 2
     /* 354722 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(11),
     /* 354733 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 11:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354733 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354736 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354740 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354745 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354749 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354751 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354754 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354758 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354763 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354766 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354768 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354771 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354775 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354780 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354783 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354788 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354790 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354793 */   GIR_RootConstrainSelectedInstOperands,
     /* 354794 */   // GIR_Coverage, 9141,
     /* 354794 */   GIR_EraseRootFromParent_Done,
     /* 354795 */ // Label 7141: @354795
     /* 354795 */ GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(354883), // Rule ID 9142 //
     /* 354800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354803 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354810 */   // MIs[0] Operand 2
     /* 354810 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 354821 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354821 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354824 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354828 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354833 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354837 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354839 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354842 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354846 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354851 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354854 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354856 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354859 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354863 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354868 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354871 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354878 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354881 */   GIR_RootConstrainSelectedInstOperands,
     /* 354882 */   // GIR_Coverage, 9142,
     /* 354882 */   GIR_EraseRootFromParent_Done,
     /* 354883 */ // Label 7142: @354883
     /* 354883 */ GIM_Try, /*On fail goto*//*Label 7143*/ GIMT_Encode4(354971), // Rule ID 9143 //
     /* 354888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354891 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354898 */   // MIs[0] Operand 2
     /* 354898 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(13),
     /* 354909 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 13:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354909 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 354912 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354916 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354921 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 354925 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 354927 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 354930 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354934 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354939 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 354942 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 354944 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 354947 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 354951 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354956 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 354959 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 354964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 354966 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354969 */   GIR_RootConstrainSelectedInstOperands,
     /* 354970 */   // GIR_Coverage, 9143,
     /* 354970 */   GIR_EraseRootFromParent_Done,
     /* 354971 */ // Label 7143: @354971
     /* 354971 */ GIM_Try, /*On fail goto*//*Label 7144*/ GIMT_Encode4(355059), // Rule ID 9144 //
     /* 354976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 354979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 354982 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 354986 */   // MIs[0] Operand 2
     /* 354986 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(14),
     /* 354997 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 14:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 354997 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 355000 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355004 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355009 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355013 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 355015 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355018 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355022 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355027 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 355030 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355032 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355035 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355039 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355044 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355047 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355052 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355054 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355057 */   GIR_RootConstrainSelectedInstOperands,
     /* 355058 */   // GIR_Coverage, 9144,
     /* 355058 */   GIR_EraseRootFromParent_Done,
     /* 355059 */ // Label 7144: @355059
     /* 355059 */ GIM_Try, /*On fail goto*//*Label 7145*/ GIMT_Encode4(355147), // Rule ID 9145 //
     /* 355064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355067 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355074 */   // MIs[0] Operand 2
     /* 355074 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 355085 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 15:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 355085 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 355088 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355092 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355097 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355101 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 355103 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355106 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355110 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355115 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 355118 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355120 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355123 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355127 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355132 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355135 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355137 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355140 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355142 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355145 */   GIR_RootConstrainSelectedInstOperands,
     /* 355146 */   // GIR_Coverage, 9145,
     /* 355146 */   GIR_EraseRootFromParent_Done,
     /* 355147 */ // Label 7145: @355147
     /* 355147 */ GIM_Reject,
     /* 355148 */ // Label 7081: @355148
     /* 355148 */ GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(355183), // Rule ID 9096 //
     /* 355153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 355159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355163 */   // MIs[0] Operand 2
     /* 355163 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 355174 */   // (extract_subvector:{ *:[nxv2i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } PPR:{ *:[nxv4i1] }:$Ps)
     /* 355174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355177 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355179 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 355181 */   GIR_RootConstrainSelectedInstOperands,
     /* 355182 */   // GIR_Coverage, 9096,
     /* 355182 */   GIR_EraseRootFromParent_Done,
     /* 355183 */ // Label 7146: @355183
     /* 355183 */ GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(355218), // Rule ID 9097 //
     /* 355188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355191 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 355194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355198 */   // MIs[0] Operand 2
     /* 355198 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 355209 */   // (extract_subvector:{ *:[nxv2i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } PPR:{ *:[nxv4i1] }:$Ps)
     /* 355209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355214 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 355216 */   GIR_RootConstrainSelectedInstOperands,
     /* 355217 */   // GIR_Coverage, 9097,
     /* 355217 */   GIR_EraseRootFromParent_Done,
     /* 355218 */ // Label 7147: @355218
     /* 355218 */ GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(355272), // Rule ID 9106 //
     /* 355223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 355229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355233 */   // MIs[0] Operand 2
     /* 355233 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 355244 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 355244 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355247 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355251 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355256 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355260 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355267 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355270 */   GIR_RootConstrainSelectedInstOperands,
     /* 355271 */   // GIR_Coverage, 9106,
     /* 355271 */   GIR_EraseRootFromParent_Done,
     /* 355272 */ // Label 7148: @355272
     /* 355272 */ GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(355326), // Rule ID 9107 //
     /* 355277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 355283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355287 */   // MIs[0] Operand 2
     /* 355287 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 355298 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 355298 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355301 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355305 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355310 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355314 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355319 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355321 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355324 */   GIR_RootConstrainSelectedInstOperands,
     /* 355325 */   // GIR_Coverage, 9107,
     /* 355325 */   GIR_EraseRootFromParent_Done,
     /* 355326 */ // Label 7149: @355326
     /* 355326 */ GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(355380), // Rule ID 9108 //
     /* 355331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 355337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355341 */   // MIs[0] Operand 2
     /* 355341 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 355352 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 355352 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355355 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355359 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355364 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355368 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355370 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355373 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355375 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355378 */   GIR_RootConstrainSelectedInstOperands,
     /* 355379 */   // GIR_Coverage, 9108,
     /* 355379 */   GIR_EraseRootFromParent_Done,
     /* 355380 */ // Label 7150: @355380
     /* 355380 */ GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(355434), // Rule ID 9109 //
     /* 355385 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355388 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 355391 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355395 */   // MIs[0] Operand 2
     /* 355395 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 355406 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 355406 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355409 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355413 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355418 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355422 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355427 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355429 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355432 */   GIR_RootConstrainSelectedInstOperands,
     /* 355433 */   // GIR_Coverage, 9109,
     /* 355433 */   GIR_EraseRootFromParent_Done,
     /* 355434 */ // Label 7151: @355434
     /* 355434 */ GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(355505), // Rule ID 9122 //
     /* 355439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355449 */   // MIs[0] Operand 2
     /* 355449 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 355460 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355460 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355463 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355467 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355472 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355476 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355478 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355481 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355485 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355490 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355493 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355495 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355498 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355500 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355503 */   GIR_RootConstrainSelectedInstOperands,
     /* 355504 */   // GIR_Coverage, 9122,
     /* 355504 */   GIR_EraseRootFromParent_Done,
     /* 355505 */ // Label 7152: @355505
     /* 355505 */ GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(355576), // Rule ID 9123 //
     /* 355510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355520 */   // MIs[0] Operand 2
     /* 355520 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 355531 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355531 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355534 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355538 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355543 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355547 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355549 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355552 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355556 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355561 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355564 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355569 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355571 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355574 */   GIR_RootConstrainSelectedInstOperands,
     /* 355575 */   // GIR_Coverage, 9123,
     /* 355575 */   GIR_EraseRootFromParent_Done,
     /* 355576 */ // Label 7153: @355576
     /* 355576 */ GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(355647), // Rule ID 9124 //
     /* 355581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355584 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355591 */   // MIs[0] Operand 2
     /* 355591 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 355602 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355602 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355605 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355609 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355614 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355618 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355620 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355623 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355627 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355632 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355635 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355640 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355642 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355645 */   GIR_RootConstrainSelectedInstOperands,
     /* 355646 */   // GIR_Coverage, 9124,
     /* 355646 */   GIR_EraseRootFromParent_Done,
     /* 355647 */ // Label 7154: @355647
     /* 355647 */ GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(355718), // Rule ID 9125 //
     /* 355652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355662 */   // MIs[0] Operand 2
     /* 355662 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 355673 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355673 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355676 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355680 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355685 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355689 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355691 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355694 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355698 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355703 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355706 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355713 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355716 */   GIR_RootConstrainSelectedInstOperands,
     /* 355717 */   // GIR_Coverage, 9125,
     /* 355717 */   GIR_EraseRootFromParent_Done,
     /* 355718 */ // Label 7155: @355718
     /* 355718 */ GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(355789), // Rule ID 9126 //
     /* 355723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355733 */   // MIs[0] Operand 2
     /* 355733 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 355744 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355744 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355747 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355751 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355756 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355760 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355762 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355765 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355769 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355774 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355777 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355784 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355787 */   GIR_RootConstrainSelectedInstOperands,
     /* 355788 */   // GIR_Coverage, 9126,
     /* 355788 */   GIR_EraseRootFromParent_Done,
     /* 355789 */ // Label 7156: @355789
     /* 355789 */ GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(355860), // Rule ID 9127 //
     /* 355794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355797 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355804 */   // MIs[0] Operand 2
     /* 355804 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(10),
     /* 355815 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 10:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355815 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355818 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355822 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355827 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355831 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355833 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355836 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355840 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355845 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355848 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355855 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355858 */   GIR_RootConstrainSelectedInstOperands,
     /* 355859 */   // GIR_Coverage, 9127,
     /* 355859 */   GIR_EraseRootFromParent_Done,
     /* 355860 */ // Label 7157: @355860
     /* 355860 */ GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(355931), // Rule ID 9128 //
     /* 355865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355868 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355871 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355875 */   // MIs[0] Operand 2
     /* 355875 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 355886 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355886 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355889 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355893 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355898 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355902 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355904 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355907 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355911 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355916 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355919 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 355924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355926 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 355929 */   GIR_RootConstrainSelectedInstOperands,
     /* 355930 */   // GIR_Coverage, 9128,
     /* 355930 */   GIR_EraseRootFromParent_Done,
     /* 355931 */ // Label 7158: @355931
     /* 355931 */ GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(356002), // Rule ID 9129 //
     /* 355936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 355939 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 355942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 355946 */   // MIs[0] Operand 2
     /* 355946 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(14),
     /* 355957 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 14:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 355957 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 355960 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355964 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355969 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 355973 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 355975 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 355978 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355982 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 355987 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 355990 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 355992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 355995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 355997 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356000 */   GIR_RootConstrainSelectedInstOperands,
     /* 356001 */   // GIR_Coverage, 9129,
     /* 356001 */   GIR_EraseRootFromParent_Done,
     /* 356002 */ // Label 7159: @356002
     /* 356002 */ GIM_Reject,
     /* 356003 */ // Label 7082: @356003
     /* 356003 */ GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(356038), // Rule ID 9146 //
     /* 356008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 356014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356018 */   // MIs[0] Operand 2
     /* 356018 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356029 */   // (extract_subvector:{ *:[nxv2f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$Zs)
     /* 356029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 356032 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356034 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356036 */   GIR_RootConstrainSelectedInstOperands,
     /* 356037 */   // GIR_Coverage, 9146,
     /* 356037 */   GIR_EraseRootFromParent_Done,
     /* 356038 */ // Label 7160: @356038
     /* 356038 */ GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(356073), // Rule ID 9147 //
     /* 356043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 356049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356053 */   // MIs[0] Operand 2
     /* 356053 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 356064 */   // (extract_subvector:{ *:[nxv2f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$Zs)
     /* 356064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 356067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356069 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356071 */   GIR_RootConstrainSelectedInstOperands,
     /* 356072 */   // GIR_Coverage, 9147,
     /* 356072 */   GIR_EraseRootFromParent_Done,
     /* 356073 */ // Label 7161: @356073
     /* 356073 */ GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(356127), // Rule ID 9152 //
     /* 356078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 356084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356088 */   // MIs[0] Operand 2
     /* 356088 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356099 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } (UUNPKLO_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 356099 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 356102 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 356106 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356111 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 356115 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 356120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356122 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356125 */   GIR_RootConstrainSelectedInstOperands,
     /* 356126 */   // GIR_Coverage, 9152,
     /* 356126 */   GIR_EraseRootFromParent_Done,
     /* 356127 */ // Label 7162: @356127
     /* 356127 */ GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(356181), // Rule ID 9153 //
     /* 356132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356135 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 356138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356142 */   // MIs[0] Operand 2
     /* 356142 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 356153 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } (UUNPKLO_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 356153 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 356156 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 356160 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356165 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 356169 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 356174 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356176 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356179 */   GIR_RootConstrainSelectedInstOperands,
     /* 356180 */   // GIR_Coverage, 9153,
     /* 356180 */   GIR_EraseRootFromParent_Done,
     /* 356181 */ // Label 7163: @356181
     /* 356181 */ GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(356235), // Rule ID 9154 //
     /* 356186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 356192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356196 */   // MIs[0] Operand 2
     /* 356196 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 356207 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 4:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } (UUNPKHI_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 356207 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 356210 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 356214 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356219 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 356223 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356225 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 356228 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356230 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356233 */   GIR_RootConstrainSelectedInstOperands,
     /* 356234 */   // GIR_Coverage, 9154,
     /* 356234 */   GIR_EraseRootFromParent_Done,
     /* 356235 */ // Label 7164: @356235
     /* 356235 */ GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(356289), // Rule ID 9155 //
     /* 356240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356243 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 356246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356250 */   // MIs[0] Operand 2
     /* 356250 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 356261 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 6:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } (UUNPKHI_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 356261 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 356264 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 356268 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356273 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 356277 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 356282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356284 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356287 */   GIR_RootConstrainSelectedInstOperands,
     /* 356288 */   // GIR_Coverage, 9155,
     /* 356288 */   GIR_EraseRootFromParent_Done,
     /* 356289 */ // Label 7165: @356289
     /* 356289 */ GIM_Reject,
     /* 356290 */ // Label 7083: @356290
     /* 356290 */ GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(356359),
     /* 356295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 356298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356302 */   GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(356330), // Rule ID 9150 //
     /* 356307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356310 */     // MIs[0] Operand 2
     /* 356310 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356321 */     // (extract_subvector:{ *:[nxv2f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$Zs)
     /* 356321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 356324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356326 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356328 */     GIR_RootConstrainSelectedInstOperands,
     /* 356329 */     // GIR_Coverage, 9150,
     /* 356329 */     GIR_EraseRootFromParent_Done,
     /* 356330 */   // Label 7167: @356330
     /* 356330 */   GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(356358), // Rule ID 9151 //
     /* 356335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356338 */     // MIs[0] Operand 2
     /* 356338 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 356349 */     // (extract_subvector:{ *:[nxv2f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$Zs)
     /* 356349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 356352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356354 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356356 */     GIR_RootConstrainSelectedInstOperands,
     /* 356357 */     // GIR_Coverage, 9151,
     /* 356357 */     GIR_EraseRootFromParent_Done,
     /* 356358 */   // Label 7168: @356358
     /* 356358 */   GIM_Reject,
     /* 356359 */ // Label 7166: @356359
     /* 356359 */ GIM_Reject,
     /* 356360 */ // Label 7084: @356360
     /* 356360 */ GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(356395), // Rule ID 9098 //
     /* 356365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 356371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356375 */   // MIs[0] Operand 2
     /* 356375 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356386 */   // (extract_subvector:{ *:[nxv4i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } PPR:{ *:[nxv8i1] }:$Ps)
     /* 356386 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356389 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356391 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 356393 */   GIR_RootConstrainSelectedInstOperands,
     /* 356394 */   // GIR_Coverage, 9098,
     /* 356394 */   GIR_EraseRootFromParent_Done,
     /* 356395 */ // Label 7169: @356395
     /* 356395 */ GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(356430), // Rule ID 9099 //
     /* 356400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 356406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356410 */   // MIs[0] Operand 2
     /* 356410 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 356421 */   // (extract_subvector:{ *:[nxv4i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } PPR:{ *:[nxv8i1] }:$Ps)
     /* 356421 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356424 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356426 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 356428 */   GIR_RootConstrainSelectedInstOperands,
     /* 356429 */   // GIR_Coverage, 9099,
     /* 356429 */   GIR_EraseRootFromParent_Done,
     /* 356430 */ // Label 7170: @356430
     /* 356430 */ GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(356484), // Rule ID 9110 //
     /* 356435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 356441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356445 */   // MIs[0] Operand 2
     /* 356445 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356456 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 356456 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 356459 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356463 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356468 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 356472 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356474 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356477 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356479 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356482 */   GIR_RootConstrainSelectedInstOperands,
     /* 356483 */   // GIR_Coverage, 9110,
     /* 356483 */   GIR_EraseRootFromParent_Done,
     /* 356484 */ // Label 7171: @356484
     /* 356484 */ GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(356538), // Rule ID 9111 //
     /* 356489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 356495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356499 */   // MIs[0] Operand 2
     /* 356499 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 356510 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 356510 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 356513 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356517 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356522 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 356526 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356533 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356536 */   GIR_RootConstrainSelectedInstOperands,
     /* 356537 */   // GIR_Coverage, 9111,
     /* 356537 */   GIR_EraseRootFromParent_Done,
     /* 356538 */ // Label 7172: @356538
     /* 356538 */ GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(356592), // Rule ID 9112 //
     /* 356543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 356549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356553 */   // MIs[0] Operand 2
     /* 356553 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 356564 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 356564 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 356567 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356571 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356576 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 356580 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356582 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356585 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356587 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356590 */   GIR_RootConstrainSelectedInstOperands,
     /* 356591 */   // GIR_Coverage, 9112,
     /* 356591 */   GIR_EraseRootFromParent_Done,
     /* 356592 */ // Label 7173: @356592
     /* 356592 */ GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(356646), // Rule ID 9113 //
     /* 356597 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356600 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 356603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356607 */   // MIs[0] Operand 2
     /* 356607 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 356618 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 356618 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 356621 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356625 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356630 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 356634 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 356636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356641 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 356644 */   GIR_RootConstrainSelectedInstOperands,
     /* 356645 */   // GIR_Coverage, 9113,
     /* 356645 */   GIR_EraseRootFromParent_Done,
     /* 356646 */ // Label 7174: @356646
     /* 356646 */ GIM_Reject,
     /* 356647 */ // Label 7085: @356647
     /* 356647 */ GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(356716),
     /* 356652 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 356655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 356659 */   GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(356687), // Rule ID 9148 //
     /* 356664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356667 */     // MIs[0] Operand 2
     /* 356667 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356678 */     // (extract_subvector:{ *:[nxv4f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_S:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$Zs)
     /* 356678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 356681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356683 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356685 */     GIR_RootConstrainSelectedInstOperands,
     /* 356686 */     // GIR_Coverage, 9148,
     /* 356686 */     GIR_EraseRootFromParent_Done,
     /* 356687 */   // Label 7176: @356687
     /* 356687 */   GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(356715), // Rule ID 9149 //
     /* 356692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356695 */     // MIs[0] Operand 2
     /* 356695 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 356706 */     // (extract_subvector:{ *:[nxv4f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 4:{ *:[i64] })  =>  (UUNPKHI_ZZ_S:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$Zs)
     /* 356706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 356709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 356711 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 356713 */     GIR_RootConstrainSelectedInstOperands,
     /* 356714 */     // GIR_Coverage, 9149,
     /* 356714 */     GIR_EraseRootFromParent_Done,
     /* 356715 */   // Label 7177: @356715
     /* 356715 */   GIM_Reject,
     /* 356716 */ // Label 7175: @356716
     /* 356716 */ GIM_Reject,
     /* 356717 */ // Label 7086: @356717
     /* 356717 */ GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(356786),
     /* 356722 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 356725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 356729 */   GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(356757), // Rule ID 9100 //
     /* 356734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356737 */     // MIs[0] Operand 2
     /* 356737 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 356748 */     // (extract_subvector:{ *:[nxv8i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv8i1] } PPR:{ *:[nxv16i1] }:$Ps)
     /* 356748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 356751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356753 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 356755 */     GIR_RootConstrainSelectedInstOperands,
     /* 356756 */     // GIR_Coverage, 9100,
     /* 356756 */     GIR_EraseRootFromParent_Done,
     /* 356757 */   // Label 7179: @356757
     /* 356757 */   GIM_Try, /*On fail goto*//*Label 7180*/ GIMT_Encode4(356785), // Rule ID 9101 //
     /* 356762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 356765 */     // MIs[0] Operand 2
     /* 356765 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 356776 */     // (extract_subvector:{ *:[nxv8i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv8i1] } PPR:{ *:[nxv16i1] }:$Ps)
     /* 356776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 356779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 356781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 356783 */     GIR_RootConstrainSelectedInstOperands,
     /* 356784 */     // GIR_Coverage, 9101,
     /* 356784 */     GIR_EraseRootFromParent_Done,
     /* 356785 */   // Label 7180: @356785
     /* 356785 */   GIM_Reject,
     /* 356786 */ // Label 7178: @356786
     /* 356786 */ GIM_Reject,
     /* 356787 */ // Label 7087: @356787
     /* 356787 */ GIM_Reject,
     /* 356788 */ // Label 91: @356788
     /* 356788 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 7196*/ GIMT_Encode4(389709),
     /* 356799 */ /*GILLT_s64*//*Label 7181*/ GIMT_Encode4(356883), GIMT_Encode4(0),
     /* 356807 */ /*GILLT_v2s32*//*Label 7182*/ GIMT_Encode4(357593),
     /* 356811 */ /*GILLT_v2s64*//*Label 7183*/ GIMT_Encode4(361124),
     /* 356815 */ /*GILLT_v4s16*//*Label 7184*/ GIMT_Encode4(364365),
     /* 356819 */ /*GILLT_v4s32*//*Label 7185*/ GIMT_Encode4(368005),
     /* 356823 */ /*GILLT_v8s8*//*Label 7186*/ GIMT_Encode4(371073),
     /* 356827 */ /*GILLT_v8s16*//*Label 7187*/ GIMT_Encode4(374286),
     /* 356831 */ /*GILLT_v16s8*//*Label 7188*/ GIMT_Encode4(377705), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 356843 */ /*GILLT_nxv2s16*//*Label 7189*/ GIMT_Encode4(380909),
     /* 356847 */ /*GILLT_nxv2s32*//*Label 7190*/ GIMT_Encode4(381034),
     /* 356851 */ /*GILLT_nxv2s64*//*Label 7191*/ GIMT_Encode4(381159), GIMT_Encode4(0),
     /* 356859 */ /*GILLT_nxv4s16*//*Label 7192*/ GIMT_Encode4(383137),
     /* 356863 */ /*GILLT_nxv4s32*//*Label 7193*/ GIMT_Encode4(383289), GIMT_Encode4(0),
     /* 356871 */ /*GILLT_nxv8s16*//*Label 7194*/ GIMT_Encode4(385321), GIMT_Encode4(0),
     /* 356879 */ /*GILLT_nxv16s8*//*Label 7195*/ GIMT_Encode4(387589),
     /* 356883 */ // Label 7181: @356883
     /* 356883 */ GIM_Try, /*On fail goto*//*Label 7197*/ GIMT_Encode4(357592),
     /* 356888 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356891 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 356894 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 356897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356901 */   GIM_Try, /*On fail goto*//*Label 7198*/ GIMT_Encode4(357031), // Rule ID 5784 //
     /* 356906 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 356914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 356918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 356922 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 356926 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 356931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 356935 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 356939 */     // MIs[2] Operand 1
     /* 356939 */     // No operand predicates
     /* 356939 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 356943 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 356947 */     // MIs[3] Operand 1
     /* 356947 */     // No operand predicates
     /* 356947 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 356949 */     // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 356949 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 356952 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 356956 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356961 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 356964 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 356968 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 356971 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 356976 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356981 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 356984 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 356988 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 356993 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 356996 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 356999 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357003 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 357006 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357013 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 357020 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357025 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357030 */     // GIR_Coverage, 5784,
     /* 357030 */     GIR_EraseRootFromParent_Done,
     /* 357031 */   // Label 7198: @357031
     /* 357031 */   GIM_Try, /*On fail goto*//*Label 7199*/ GIMT_Encode4(357192), // Rule ID 5785 //
     /* 357036 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 357044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 357048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357052 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 357056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 357065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357069 */     // MIs[2] Operand 1
     /* 357069 */     // No operand predicates
     /* 357069 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 357073 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357077 */     // MIs[3] Operand 1
     /* 357077 */     // No operand predicates
     /* 357077 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 357079 */     // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 357079 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 357082 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357086 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357091 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 357094 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357098 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 357101 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357106 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357111 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 357114 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357118 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357123 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 357126 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 357130 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 357133 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357138 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357143 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 357146 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 357150 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357155 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 357158 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 357161 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 357164 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 357167 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357174 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 357181 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357186 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357191 */     // GIR_Coverage, 5785,
     /* 357191 */     GIR_EraseRootFromParent_Done,
     /* 357192 */   // Label 7199: @357192
     /* 357192 */   GIM_Try, /*On fail goto*//*Label 7200*/ GIMT_Encode4(357322), // Rule ID 5824 //
     /* 357197 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357201 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 357205 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 357209 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 357213 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 357217 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357222 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 357226 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357230 */     // MIs[2] Operand 1
     /* 357230 */     // No operand predicates
     /* 357230 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 357234 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357238 */     // MIs[3] Operand 1
     /* 357238 */     // No operand predicates
     /* 357238 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 357240 */     // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 357240 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 357243 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357247 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357252 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 357255 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 357259 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 357262 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357267 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357272 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 357275 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 357279 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357284 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 357287 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 357290 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357294 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 357297 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357304 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 357311 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357316 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357321 */     // GIR_Coverage, 5824,
     /* 357321 */     GIR_EraseRootFromParent_Done,
     /* 357322 */   // Label 7200: @357322
     /* 357322 */   GIM_Try, /*On fail goto*//*Label 7201*/ GIMT_Encode4(357483), // Rule ID 5825 //
     /* 357327 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 357335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 357339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357343 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 357347 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357352 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 357356 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357360 */     // MIs[2] Operand 1
     /* 357360 */     // No operand predicates
     /* 357360 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 357364 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 357368 */     // MIs[3] Operand 1
     /* 357368 */     // No operand predicates
     /* 357368 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 357370 */     // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 357370 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 357373 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357377 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357382 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 357385 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357389 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 357392 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357397 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357402 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 357405 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357409 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357414 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 357417 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 357421 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 357424 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357429 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357434 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 357437 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 357441 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357446 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 357449 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 357452 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 357455 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 357458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357465 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 357472 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357477 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357482 */     // GIR_Coverage, 5825,
     /* 357482 */     GIR_EraseRootFromParent_Done,
     /* 357483 */   // Label 7201: @357483
     /* 357483 */   GIM_Try, /*On fail goto*//*Label 7202*/ GIMT_Encode4(357519), // Rule ID 6745 //
     /* 357488 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357492 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 357496 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 357500 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357504 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357506 */     // (vector_insert:{ *:[v1i64] } (undef:{ *:[v1i64] }), GPR64:{ *:[i64] }:$Xn, 0:{ *:[i64] })  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 357506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 357513 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357518 */     // GIR_Coverage, 6745,
     /* 357518 */     GIR_EraseRootFromParent_Done,
     /* 357519 */   // Label 7202: @357519
     /* 357519 */   GIM_Try, /*On fail goto*//*Label 7203*/ GIMT_Encode4(357555), // Rule ID 6747 //
     /* 357524 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357528 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 357532 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 357536 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357540 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357542 */     // (vector_insert:{ *:[v1f64] } (undef:{ *:[v1f64] }), GPR64:{ *:[i64] }:$Xn, 0:{ *:[i64] })  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 357542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 357549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357554 */     // GIR_Coverage, 6747,
     /* 357554 */     GIR_EraseRootFromParent_Done,
     /* 357555 */   // Label 7203: @357555
     /* 357555 */   GIM_Try, /*On fail goto*//*Label 7204*/ GIMT_Encode4(357591), // Rule ID 6749 //
     /* 357560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 357568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357572 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357576 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357578 */     // (vector_insert:{ *:[v1f64] } (undef:{ *:[v1f64] }), FPR64:{ *:[f64] }:$Xn, 0:{ *:[i64] })  =>  FPR64:{ *:[v1f64] }:$Xn
     /* 357578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 357581 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 357583 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 357585 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357590 */     // GIR_Coverage, 6749,
     /* 357590 */     GIR_EraseRootFromParent_Done,
     /* 357591 */   // Label 7204: @357591
     /* 357591 */   GIM_Reject,
     /* 357592 */ // Label 7197: @357592
     /* 357592 */ GIM_Reject,
     /* 357593 */ // Label 7182: @357593
     /* 357593 */ GIM_Try, /*On fail goto*//*Label 7205*/ GIMT_Encode4(361123),
     /* 357598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 357601 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 357604 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 357607 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357611 */   GIM_Try, /*On fail goto*//*Label 7206*/ GIMT_Encode4(357720), // Rule ID 4341 //
     /* 357616 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357620 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 357626 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 357628 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 357632 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 357636 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 357639 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 357643 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 357647 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357651 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 357653 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 357660 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 357660 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 357663 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 357667 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 357677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 357682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 357687 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 357693 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 357703 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 357706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 357709 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357714 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357719 */     // GIR_Coverage, 4341,
     /* 357719 */     GIR_EraseRootFromParent_Done,
     /* 357720 */   // Label 7206: @357720
     /* 357720 */   GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(357829), // Rule ID 4342 //
     /* 357725 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357729 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 357735 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 357737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 357741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 357745 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 357748 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 357752 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 357756 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357760 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 357762 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 357769 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 357769 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 357772 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 357776 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 357786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 357791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 357796 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 357802 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 357812 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 357815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 357818 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357823 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357828 */     // GIR_Coverage, 4342,
     /* 357828 */     GIR_EraseRootFromParent_Done,
     /* 357829 */   // Label 7207: @357829
     /* 357829 */   GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(357938), // Rule ID 4449 //
     /* 357834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357838 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 357844 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 357846 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 357850 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 357854 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 357857 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 357861 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 357865 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357869 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 357871 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 357878 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 357878 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 357881 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 357885 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 357895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 357900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 357905 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 357911 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 357913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 357916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 357918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 357921 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 357924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 357927 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357932 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357937 */     // GIR_Coverage, 4449,
     /* 357937 */     GIR_EraseRootFromParent_Done,
     /* 357938 */   // Label 7208: @357938
     /* 357938 */   GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(358047), // Rule ID 4450 //
     /* 357943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357947 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 357953 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 357955 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 357959 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 357963 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 357966 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 357970 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 357974 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 357978 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 357980 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 357987 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 357987 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 357990 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 357994 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 357999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 358009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 358014 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358020 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358030 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358036 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358041 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358046 */     // GIR_Coverage, 4450,
     /* 358046 */     GIR_EraseRootFromParent_Done,
     /* 358047 */   // Label 7209: @358047
     /* 358047 */   GIM_Try, /*On fail goto*//*Label 7210*/ GIMT_Encode4(358152), // Rule ID 4347 //
     /* 358052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358060 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358064 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358068 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358071 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358075 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358079 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358083 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358085 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 358092 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 358092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 358099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 358114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 358119 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358125 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358135 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358141 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358146 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358151 */     // GIR_Coverage, 4347,
     /* 358151 */     GIR_EraseRootFromParent_Done,
     /* 358152 */   // Label 7210: @358152
     /* 358152 */   GIM_Try, /*On fail goto*//*Label 7211*/ GIMT_Encode4(358257), // Rule ID 4349 //
     /* 358157 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358161 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358173 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358176 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358180 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358184 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358188 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358190 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 358197 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 358197 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358200 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 358204 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 358219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 358224 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358230 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358246 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358251 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358256 */     // GIR_Coverage, 4349,
     /* 358256 */     GIR_EraseRootFromParent_Done,
     /* 358257 */   // Label 7211: @358257
     /* 358257 */   GIM_Try, /*On fail goto*//*Label 7212*/ GIMT_Encode4(358362), // Rule ID 4455 //
     /* 358262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358270 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358274 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358278 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358281 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358285 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358289 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358293 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358295 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 358302 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 358302 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358305 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 358309 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 358324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 358329 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358335 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358345 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358351 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358356 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358361 */     // GIR_Coverage, 4455,
     /* 358361 */     GIR_EraseRootFromParent_Done,
     /* 358362 */   // Label 7212: @358362
     /* 358362 */   GIM_Try, /*On fail goto*//*Label 7213*/ GIMT_Encode4(358467), // Rule ID 4457 //
     /* 358367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358375 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358379 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358383 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358386 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358390 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358394 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358398 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358400 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 358407 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 358407 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358410 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 358414 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 358429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 358434 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358440 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358450 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358456 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358461 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358466 */     // GIR_Coverage, 4457,
     /* 358466 */     GIR_EraseRootFromParent_Done,
     /* 358467 */   // Label 7213: @358467
     /* 358467 */   GIM_Try, /*On fail goto*//*Label 7214*/ GIMT_Encode4(358571), // Rule ID 4339 //
     /* 358472 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358476 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 358482 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 358484 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358488 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358492 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358495 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358499 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358503 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358507 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358509 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 358516 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 358516 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358519 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 358523 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 358538 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358544 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358554 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358560 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358565 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358570 */     // GIR_Coverage, 4339,
     /* 358570 */     GIR_EraseRootFromParent_Done,
     /* 358571 */   // Label 7214: @358571
     /* 358571 */   GIM_Try, /*On fail goto*//*Label 7215*/ GIMT_Encode4(358675), // Rule ID 4340 //
     /* 358576 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358580 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 358586 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 358588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358596 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358599 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358603 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358607 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358613 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 358620 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 358620 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358623 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 358627 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 358642 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358648 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358658 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358664 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358669 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358674 */     // GIR_Coverage, 4340,
     /* 358674 */     GIR_EraseRootFromParent_Done,
     /* 358675 */   // Label 7215: @358675
     /* 358675 */   GIM_Try, /*On fail goto*//*Label 7216*/ GIMT_Encode4(358779), // Rule ID 4447 //
     /* 358680 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358684 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 358690 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 358692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358700 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358703 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358707 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358711 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358715 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358717 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 358724 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 358724 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358727 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 358731 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 358746 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358752 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358762 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358768 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358773 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358778 */     // GIR_Coverage, 4447,
     /* 358778 */     GIR_EraseRootFromParent_Done,
     /* 358779 */   // Label 7216: @358779
     /* 358779 */   GIM_Try, /*On fail goto*//*Label 7217*/ GIMT_Encode4(358883), // Rule ID 4448 //
     /* 358784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358788 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 358794 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 358796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358804 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358807 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358811 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358815 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358821 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 358828 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 358828 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358831 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 358835 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 358850 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358856 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358866 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358872 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358877 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358882 */     // GIR_Coverage, 4448,
     /* 358882 */     GIR_EraseRootFromParent_Done,
     /* 358883 */   // Label 7217: @358883
     /* 358883 */   GIM_Try, /*On fail goto*//*Label 7218*/ GIMT_Encode4(358983), // Rule ID 4343 //
     /* 358888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358896 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 358900 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 358904 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 358907 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 358911 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 358915 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 358919 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 358921 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 358928 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 358928 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 358931 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 358935 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 358940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 358945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 358950 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 358956 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 358958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 358961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 358963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 358966 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 358969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 358972 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358977 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358982 */     // GIR_Coverage, 4343,
     /* 358982 */     GIR_EraseRootFromParent_Done,
     /* 358983 */   // Label 7218: @358983
     /* 358983 */   GIM_Try, /*On fail goto*//*Label 7219*/ GIMT_Encode4(359083), // Rule ID 4345 //
     /* 358988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 358996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 359000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 359004 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359007 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 359011 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 359015 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 359019 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359021 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 359028 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 359028 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 359031 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 359035 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 359045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 359050 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 359056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 359066 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 359072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359077 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359082 */     // GIR_Coverage, 4345,
     /* 359082 */     GIR_EraseRootFromParent_Done,
     /* 359083 */   // Label 7219: @359083
     /* 359083 */   GIM_Try, /*On fail goto*//*Label 7220*/ GIMT_Encode4(359183), // Rule ID 4451 //
     /* 359088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 359096 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 359100 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 359104 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359107 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 359111 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 359115 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 359119 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359121 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 359128 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 359128 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 359131 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 359135 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 359145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 359150 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 359156 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 359166 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 359172 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359177 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359182 */     // GIR_Coverage, 4451,
     /* 359182 */     GIR_EraseRootFromParent_Done,
     /* 359183 */   // Label 7220: @359183
     /* 359183 */   GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(359283), // Rule ID 4453 //
     /* 359188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 359196 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 359200 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 359204 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359207 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 359211 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 359215 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 359219 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359221 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 359228 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 359228 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 359231 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 359235 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 359245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 359250 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 359256 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 359266 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 359272 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359277 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359282 */     // GIR_Coverage, 4453,
     /* 359282 */     GIR_EraseRootFromParent_Done,
     /* 359283 */   // Label 7221: @359283
     /* 359283 */   GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(359403), // Rule ID 6523 //
     /* 359288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 359291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359295 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 359299 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 359303 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 359307 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359310 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 359314 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 359321 */     // MIs[2] Rn
     /* 359321 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 359325 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 359330 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 359334 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359336 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i16:{ *:[f128] } (IMPLICIT_DEF:{ *:[v8i16] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 359336 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 359339 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 359343 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359348 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 359350 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 359353 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 359357 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359362 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 359365 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 359368 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 359372 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 359378 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359385 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359392 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359397 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359402 */     // GIR_Coverage, 6523,
     /* 359402 */     GIR_EraseRootFromParent_Done,
     /* 359403 */   // Label 7222: @359403
     /* 359403 */   GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(359523), // Rule ID 6525 //
     /* 359408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 359411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359415 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 359419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 359423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 359427 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359430 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 359434 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 359441 */     // MIs[2] Rn
     /* 359441 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 359445 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 359450 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 359454 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359456 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i8:{ *:[f128] } (IMPLICIT_DEF:{ *:[v16i8] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 359456 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 359459 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 359463 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359468 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 359470 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 359473 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 359477 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359482 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 359485 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 359488 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 359492 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 359498 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359505 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359512 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359517 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359522 */     // GIR_Coverage, 6525,
     /* 359522 */     GIR_EraseRootFromParent_Done,
     /* 359523 */   // Label 7223: @359523
     /* 359523 */   GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(359653), // Rule ID 5776 //
     /* 359528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 359536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359540 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 359544 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359548 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 359557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359561 */     // MIs[2] Operand 1
     /* 359561 */     // No operand predicates
     /* 359561 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 359565 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359569 */     // MIs[3] Operand 1
     /* 359569 */     // No operand predicates
     /* 359569 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 359571 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 359571 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 359574 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359578 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359583 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 359586 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 359590 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 359593 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359598 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359603 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 359606 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 359610 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359615 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 359618 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 359621 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359625 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 359628 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359635 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359642 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359647 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359652 */     // GIR_Coverage, 5776,
     /* 359652 */     GIR_EraseRootFromParent_Done,
     /* 359653 */   // Label 7224: @359653
     /* 359653 */   GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(359814), // Rule ID 5777 //
     /* 359658 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 359666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 359674 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359678 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 359687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359691 */     // MIs[2] Operand 1
     /* 359691 */     // No operand predicates
     /* 359691 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 359695 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359699 */     // MIs[3] Operand 1
     /* 359699 */     // No operand predicates
     /* 359699 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 359701 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 359701 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 359704 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359708 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359713 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 359716 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359720 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 359723 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359728 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359733 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 359736 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359740 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359745 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 359748 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 359752 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 359755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 359768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 359772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359777 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 359780 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 359783 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 359786 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 359789 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359796 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359803 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359813 */     // GIR_Coverage, 5777,
     /* 359813 */     GIR_EraseRootFromParent_Done,
     /* 359814 */   // Label 7225: @359814
     /* 359814 */   GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(359944), // Rule ID 5816 //
     /* 359819 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 359827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 359835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359839 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359844 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 359848 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359852 */     // MIs[2] Operand 1
     /* 359852 */     // No operand predicates
     /* 359852 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 359856 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359860 */     // MIs[3] Operand 1
     /* 359860 */     // No operand predicates
     /* 359860 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 359862 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 359862 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 359865 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359869 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359874 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 359877 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 359881 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 359884 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359889 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359894 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 359897 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 359901 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359906 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 359909 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 359912 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359916 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 359919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 359926 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359933 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359938 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359943 */     // GIR_Coverage, 5816,
     /* 359943 */     GIR_EraseRootFromParent_Done,
     /* 359944 */   // Label 7226: @359944
     /* 359944 */   GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(360105), // Rule ID 5817 //
     /* 359949 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 359957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359961 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 359965 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359969 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359974 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 359978 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359982 */     // MIs[2] Operand 1
     /* 359982 */     // No operand predicates
     /* 359982 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 359986 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 359990 */     // MIs[3] Operand 1
     /* 359990 */     // No operand predicates
     /* 359990 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 359992 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 359992 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 359995 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 359999 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360004 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 360007 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 360011 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 360014 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360019 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360024 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360027 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 360031 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360036 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360039 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 360043 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360046 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360051 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360056 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360059 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 360063 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360068 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360071 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 360074 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 360077 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 360080 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360087 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360094 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360099 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360104 */     // GIR_Coverage, 5817,
     /* 360104 */     GIR_EraseRootFromParent_Done,
     /* 360105 */   // Label 7227: @360105
     /* 360105 */   GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(360171), // Rule ID 5723 //
     /* 360110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 360118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 360122 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 360126 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360128 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i32] } (IMPLICIT_DEF:{ *:[v2i32] }), GPR32:{ *:[i32] }:$Rn, ssub:{ *:[i32] })
     /* 360128 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
     /* 360131 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360135 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360140 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360147 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360150 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 360152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 360155 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360160 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360165 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 360170 */     // GIR_Coverage, 5723,
     /* 360170 */     GIR_EraseRootFromParent_Done,
     /* 360171 */   // Label 7228: @360171
     /* 360171 */   GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(360237), // Rule ID 5739 //
     /* 360176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 360184 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360188 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 360192 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360194 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), FPR32:{ *:[f32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] })
     /* 360194 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
     /* 360197 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360201 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360206 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360213 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 360218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 360221 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360226 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360231 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360236 */     // GIR_Coverage, 5739,
     /* 360236 */     GIR_EraseRootFromParent_Done,
     /* 360237 */   // Label 7229: @360237
     /* 360237 */   GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(360372), // Rule ID 5747 //
     /* 360242 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 360250 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 360254 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 360258 */     // MIs[1] Operand 1
     /* 360258 */     // No operand predicates
     /* 360258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 360262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 360266 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 360270 */     // MIs[2] Operand 1
     /* 360270 */     // No operand predicates
     /* 360270 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 360272 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
     /* 360272 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 360275 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360279 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360284 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 360286 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 360289 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360293 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360298 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360301 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 360305 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360308 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360313 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360318 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360323 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360326 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 360330 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360335 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360338 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
     /* 360341 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 360347 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360354 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360361 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360366 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360371 */     // GIR_Coverage, 5747,
     /* 360371 */     GIR_EraseRootFromParent_Done,
     /* 360372 */   // Label 7230: @360372
     /* 360372 */   GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(360504), // Rule ID 6532 //
     /* 360377 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 360385 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 360389 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360392 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 360396 */     // MIs[1] Rn
     /* 360396 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 360400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 360405 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 360409 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 360413 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 360417 */     // MIs[2] Operand 1
     /* 360417 */     // No operand predicates
     /* 360417 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 360419 */     // (vector_insert:{ *:[v2i32] } VecListOne64:{ *:[v2i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 360419 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360422 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 360426 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360431 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360434 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 360438 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360441 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360446 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360451 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360454 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 360458 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360463 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360466 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 360469 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 360473 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 360479 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360486 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360493 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360498 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360503 */     // GIR_Coverage, 6532,
     /* 360503 */     GIR_EraseRootFromParent_Done,
     /* 360504 */   // Label 7231: @360504
     /* 360504 */   GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(360636), // Rule ID 6533 //
     /* 360509 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 360517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 360521 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360524 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 360528 */     // MIs[1] Rn
     /* 360528 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 360532 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 360537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 360541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 360545 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 360549 */     // MIs[2] Operand 1
     /* 360549 */     // No operand predicates
     /* 360549 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 360551 */     // (vector_insert:{ *:[v2f32] } VecListOne64:{ *:[v2f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 360551 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360554 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 360558 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360563 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360566 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 360570 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360573 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360578 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360583 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360586 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 360590 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360595 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360598 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 360601 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 360605 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 360611 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360618 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360625 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360630 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360635 */     // GIR_Coverage, 6533,
     /* 360635 */     GIR_EraseRootFromParent_Done,
     /* 360636 */   // Label 7232: @360636
     /* 360636 */   GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(360819), // Rule ID 5827 //
     /* 360641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 360645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 360649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 360653 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360658 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 360662 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 360666 */     // MIs[2] Operand 1
     /* 360666 */     // No operand predicates
     /* 360666 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 360668 */     // (vector_insert:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 360668 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /* 360671 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360675 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360680 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 360682 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 360685 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360689 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360694 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 360697 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 360701 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/18,
     /* 360704 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360709 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360714 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360719 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 360722 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360726 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360731 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 360733 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 360736 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360740 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360745 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360748 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 360752 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360765 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360770 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360773 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 360777 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360782 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360785 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immd
     /* 360788 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 360791 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 360794 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360801 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360813 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360818 */     // GIR_Coverage, 5827,
     /* 360818 */     GIR_EraseRootFromParent_Done,
     /* 360819 */   // Label 7233: @360819
     /* 360819 */   GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(360997), // Rule ID 5750 //
     /* 360824 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360832 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 360836 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 360840 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 360844 */     // MIs[1] Operand 1
     /* 360844 */     // No operand predicates
     /* 360844 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360846 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 360846 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 360849 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360853 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360858 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 360860 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 360863 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360867 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360872 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 360875 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 360879 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/18,
     /* 360882 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360887 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360892 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360897 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 360900 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360904 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360909 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 360911 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 360914 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360918 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360923 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360926 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 360930 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 360933 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360938 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360943 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 360951 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 360955 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360960 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 360963 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 360966 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 360969 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 360972 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 360974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 360979 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360986 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360991 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360996 */     // GIR_Coverage, 5750,
     /* 360996 */     GIR_EraseRootFromParent_Done,
     /* 360997 */   // Label 7234: @360997
     /* 360997 */   GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(361122), // Rule ID 5753 //
     /* 361002 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 361010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 361014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 361018 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 361022 */     // MIs[1] Operand 1
     /* 361022 */     // No operand predicates
     /* 361022 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361024 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 361024 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 361027 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 361031 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361036 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 361038 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 361041 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 361045 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361050 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 361053 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 361057 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 361060 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361065 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361070 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361075 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 361078 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 361082 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361087 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 361090 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 361093 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 361097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361104 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 361111 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361116 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361121 */     // GIR_Coverage, 5753,
     /* 361121 */     GIR_EraseRootFromParent_Done,
     /* 361122 */   // Label 7235: @361122
     /* 361122 */   GIM_Reject,
     /* 361123 */ // Label 7205: @361123
     /* 361123 */ GIM_Reject,
     /* 361124 */ // Label 7183: @361124
     /* 361124 */ GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(364364),
     /* 361129 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 361132 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 361135 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 361138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361142 */   GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(361251), // Rule ID 4365 //
     /* 361147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361151 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 361157 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 361159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361167 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361170 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361174 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361178 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361182 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361184 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 361191 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361191 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361194 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 361198 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361218 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361224 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361234 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361240 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361245 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361250 */     // GIR_Coverage, 4365,
     /* 361250 */     GIR_EraseRootFromParent_Done,
     /* 361251 */   // Label 7237: @361251
     /* 361251 */   GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(361360), // Rule ID 4366 //
     /* 361256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361260 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 361266 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 361268 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361272 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361276 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361279 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361283 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361287 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361291 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361293 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 361300 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361300 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361303 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 361307 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361327 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361333 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361343 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361349 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361354 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361359 */     // GIR_Coverage, 4366,
     /* 361359 */     GIR_EraseRootFromParent_Done,
     /* 361360 */   // Label 7238: @361360
     /* 361360 */   GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(361469), // Rule ID 4473 //
     /* 361365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361369 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 361375 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 361377 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361381 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361385 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361388 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361392 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361396 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361400 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361402 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 361409 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361409 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361412 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 361416 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361436 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361442 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361452 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361458 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361463 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361468 */     // GIR_Coverage, 4473,
     /* 361468 */     GIR_EraseRootFromParent_Done,
     /* 361469 */   // Label 7239: @361469
     /* 361469 */   GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(361578), // Rule ID 4474 //
     /* 361474 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361478 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 361484 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 361486 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361490 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361494 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361497 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361501 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361505 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361509 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361511 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 361518 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361518 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361521 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 361525 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361545 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361561 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361567 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361572 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361577 */     // GIR_Coverage, 4474,
     /* 361577 */     GIR_EraseRootFromParent_Done,
     /* 361578 */   // Label 7240: @361578
     /* 361578 */   GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(361683), // Rule ID 4371 //
     /* 361583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 361591 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361595 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361599 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361602 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361606 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361610 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361614 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361616 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 361623 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361623 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361626 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 361630 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361650 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361656 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361666 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361672 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361677 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361682 */     // GIR_Coverage, 4371,
     /* 361682 */     GIR_EraseRootFromParent_Done,
     /* 361683 */   // Label 7241: @361683
     /* 361683 */   GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(361788), // Rule ID 4373 //
     /* 361688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 361696 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361700 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361704 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361707 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361711 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361715 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361719 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361721 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 361728 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361728 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361731 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 361735 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361755 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361761 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361771 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361777 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361782 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361787 */     // GIR_Coverage, 4373,
     /* 361787 */     GIR_EraseRootFromParent_Done,
     /* 361788 */   // Label 7242: @361788
     /* 361788 */   GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(361893), // Rule ID 4479 //
     /* 361793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 361801 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361805 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361809 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361812 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361816 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361820 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361824 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361826 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 361833 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361833 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361836 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 361840 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361860 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361866 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361876 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361882 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361887 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361892 */     // GIR_Coverage, 4479,
     /* 361892 */     GIR_EraseRootFromParent_Done,
     /* 361893 */   // Label 7243: @361893
     /* 361893 */   GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(361998), // Rule ID 4481 //
     /* 361898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 361906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 361910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361914 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361917 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 361921 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 361925 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 361929 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 361931 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 361938 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 361938 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361941 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 361945 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 361965 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 361971 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 361976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 361978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 361981 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 361987 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361992 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361997 */     // GIR_Coverage, 4481,
     /* 361997 */     GIR_EraseRootFromParent_Done,
     /* 361998 */   // Label 7244: @361998
     /* 361998 */   GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(362102), // Rule ID 4363 //
     /* 362003 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362007 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 362013 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 362015 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362019 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362023 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362026 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362030 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362034 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362038 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362040 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 362047 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 362047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 362054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362069 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362075 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362085 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362091 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362096 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362101 */     // GIR_Coverage, 4363,
     /* 362101 */     GIR_EraseRootFromParent_Done,
     /* 362102 */   // Label 7245: @362102
     /* 362102 */   GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(362206), // Rule ID 4364 //
     /* 362107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362111 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 362117 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 362119 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362123 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362127 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362130 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362134 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362138 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362142 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362144 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 362151 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 362151 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362154 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 362158 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362173 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362179 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362189 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362195 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362200 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362205 */     // GIR_Coverage, 4364,
     /* 362205 */     GIR_EraseRootFromParent_Done,
     /* 362206 */   // Label 7246: @362206
     /* 362206 */   GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(362310), // Rule ID 4471 //
     /* 362211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362215 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 362221 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 362223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362231 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362234 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362238 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362242 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362246 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362248 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 362255 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 362255 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362258 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 362262 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362277 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362283 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362293 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362299 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362309 */     // GIR_Coverage, 4471,
     /* 362309 */     GIR_EraseRootFromParent_Done,
     /* 362310 */   // Label 7247: @362310
     /* 362310 */   GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(362414), // Rule ID 4472 //
     /* 362315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362319 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 362325 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 362327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362335 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362338 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362342 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362346 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362352 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 362359 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 362359 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362362 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 362366 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362381 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362387 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362397 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362403 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362408 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362413 */     // GIR_Coverage, 4472,
     /* 362413 */     GIR_EraseRootFromParent_Done,
     /* 362414 */   // Label 7248: @362414
     /* 362414 */   GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(362514), // Rule ID 4367 //
     /* 362419 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362423 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362427 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362431 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362435 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362438 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362442 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362446 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362452 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 362459 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 362459 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362462 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 362466 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362481 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362487 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362497 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362503 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362508 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362513 */     // GIR_Coverage, 4367,
     /* 362513 */     GIR_EraseRootFromParent_Done,
     /* 362514 */   // Label 7249: @362514
     /* 362514 */   GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(362614), // Rule ID 4369 //
     /* 362519 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362523 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362527 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362531 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362535 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362538 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362542 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362546 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362550 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362552 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 362559 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 362559 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362562 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 362566 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362581 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362587 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362603 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362608 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362613 */     // GIR_Coverage, 4369,
     /* 362613 */     GIR_EraseRootFromParent_Done,
     /* 362614 */   // Label 7250: @362614
     /* 362614 */   GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(362714), // Rule ID 4475 //
     /* 362619 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362623 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362627 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362631 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362635 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362638 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362642 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362646 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362650 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362652 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 362659 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 362659 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362662 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 362666 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362681 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362687 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362697 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362703 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362708 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362713 */     // GIR_Coverage, 4475,
     /* 362713 */     GIR_EraseRootFromParent_Done,
     /* 362714 */   // Label 7251: @362714
     /* 362714 */   GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(362814), // Rule ID 4477 //
     /* 362719 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362723 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362727 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362731 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362735 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362738 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 362742 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 362746 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362750 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 362752 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 362759 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 362759 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362762 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 362766 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362781 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 362787 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 362792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 362797 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362803 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362813 */     // GIR_Coverage, 4477,
     /* 362813 */     GIR_EraseRootFromParent_Done,
     /* 362814 */   // Label 7252: @362814
     /* 362814 */   GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(362927), // Rule ID 5782 //
     /* 362819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 362835 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 362839 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 362843 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362848 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 362852 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 362856 */     // MIs[3] Operand 1
     /* 362856 */     // No operand predicates
     /* 362856 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362860 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 362862 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), (DUPi64:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 362862 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 362865 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 362869 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362874 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 362878 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 362881 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362883 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 362886 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 362890 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362895 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 362897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 362900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 362902 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362905 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 362908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 362911 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362916 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362921 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362926 */     // GIR_Coverage, 5782,
     /* 362926 */     GIR_EraseRootFromParent_Done,
     /* 362927 */   // Label 7253: @362927
     /* 362927 */   GIM_Try, /*On fail goto*//*Label 7254*/ GIMT_Encode4(363040), // Rule ID 5822 //
     /* 362932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 362940 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 362944 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 362948 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 362952 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 362956 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362961 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 362965 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 362969 */     // MIs[3] Operand 1
     /* 362969 */     // No operand predicates
     /* 362969 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 362973 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 362975 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (DUPi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 362975 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 362978 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 362982 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362987 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 362991 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 362994 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362996 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 362999 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 363003 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363008 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 363010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 363013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363015 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363018 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 363021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 363024 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363029 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363034 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363039 */     // GIR_Coverage, 5822,
     /* 363039 */     GIR_EraseRootFromParent_Done,
     /* 363040 */   // Label 7254: @363040
     /* 363040 */   GIM_Try, /*On fail goto*//*Label 7255*/ GIMT_Encode4(363118), // Rule ID 1945 //
     /* 363045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 363048 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 363064 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363068 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363073 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363077 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363081 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363085 */     // MIs[2] Operand 1
     /* 363085 */     // No operand predicates
     /* 363085 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363089 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363093 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363097 */     // MIs[3] Operand 1
     /* 363097 */     // No operand predicates
     /* 363097 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363099 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 363099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363104 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 363106 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 363109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363113 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 363116 */     GIR_RootConstrainSelectedInstOperands,
     /* 363117 */     // GIR_Coverage, 1945,
     /* 363117 */     GIR_EraseRootFromParent_Done,
     /* 363118 */   // Label 7255: @363118
     /* 363118 */   GIM_Try, /*On fail goto*//*Label 7256*/ GIMT_Encode4(363213), // Rule ID 7518 //
     /* 363123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 363126 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363134 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 363138 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 363142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 363146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 363150 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 363153 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 363157 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 363164 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 363167 */     // MIs[2] Rn
     /* 363167 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 363171 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 363176 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363180 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363184 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363188 */     // MIs[3] Operand 1
     /* 363188 */     // No operand predicates
     /* 363188 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363190 */     // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15874>>), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LDAP1:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 363190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
     /* 363193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363195 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 363197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 363200 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 363204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
     /* 363211 */     GIR_RootConstrainSelectedInstOperands,
     /* 363212 */     // GIR_Coverage, 7518,
     /* 363212 */     GIR_EraseRootFromParent_Done,
     /* 363213 */   // Label 7256: @363213
     /* 363213 */   GIM_Try, /*On fail goto*//*Label 7257*/ GIMT_Encode4(363302), // Rule ID 5779 //
     /* 363218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 363230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363242 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363246 */     // MIs[2] Operand 1
     /* 363246 */     // No operand predicates
     /* 363246 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363250 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363254 */     // MIs[3] Operand 1
     /* 363254 */     // No operand predicates
     /* 363254 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363256 */     // (vector_insert:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v2f64] } ZPR:{ *:[nxv2f64] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn)
     /* 363256 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363259 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363263 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363268 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 363274 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363279 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 363284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363289 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 363291 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363294 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363297 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363300 */     GIR_RootConstrainSelectedInstOperands,
     /* 363301 */     // GIR_Coverage, 5779,
     /* 363301 */     GIR_EraseRootFromParent_Done,
     /* 363302 */   // Label 7257: @363302
     /* 363302 */   GIM_Try, /*On fail goto*//*Label 7258*/ GIMT_Encode4(363391), // Rule ID 5819 //
     /* 363307 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 363319 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363323 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363327 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363331 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363335 */     // MIs[2] Operand 1
     /* 363335 */     // No operand predicates
     /* 363335 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363339 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363343 */     // MIs[3] Operand 1
     /* 363343 */     // No operand predicates
     /* 363343 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363345 */     // (vector_insert:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn)
     /* 363345 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363348 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363352 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363357 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 363363 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363368 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 363373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 363380 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363383 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363386 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363389 */     GIR_RootConstrainSelectedInstOperands,
     /* 363390 */     // GIR_Coverage, 5819,
     /* 363390 */     GIR_EraseRootFromParent_Done,
     /* 363391 */   // Label 7258: @363391
     /* 363391 */   GIM_Try, /*On fail goto*//*Label 7259*/ GIMT_Encode4(363458), // Rule ID 5781 //
     /* 363396 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 363412 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363416 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363429 */     // MIs[2] Operand 1
     /* 363429 */     // No operand predicates
     /* 363429 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363433 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363437 */     // MIs[3] Operand 1
     /* 363437 */     // No operand predicates
     /* 363437 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363439 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 363439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363444 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 363446 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363453 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363456 */     GIR_RootConstrainSelectedInstOperands,
     /* 363457 */     // GIR_Coverage, 5781,
     /* 363457 */     GIR_EraseRootFromParent_Done,
     /* 363458 */   // Label 7259: @363458
     /* 363458 */   GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(363556), // Rule ID 5783 //
     /* 363463 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363475 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 363479 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363483 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363488 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363492 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363496 */     // MIs[2] Operand 1
     /* 363496 */     // No operand predicates
     /* 363496 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363500 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363504 */     // MIs[3] Operand 1
     /* 363504 */     // No operand predicates
     /* 363504 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363506 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 363506 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363509 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 363513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363518 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 363521 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363525 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 363528 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363533 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363543 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 363545 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363548 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363551 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363554 */     GIR_RootConstrainSelectedInstOperands,
     /* 363555 */     // GIR_Coverage, 5783,
     /* 363555 */     GIR_EraseRootFromParent_Done,
     /* 363556 */   // Label 7260: @363556
     /* 363556 */   GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(363623), // Rule ID 5821 //
     /* 363561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 363577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363586 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363590 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363594 */     // MIs[2] Operand 1
     /* 363594 */     // No operand predicates
     /* 363594 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363598 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363602 */     // MIs[3] Operand 1
     /* 363602 */     // No operand predicates
     /* 363602 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363604 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 363604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363609 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 363611 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363618 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363621 */     GIR_RootConstrainSelectedInstOperands,
     /* 363622 */     // GIR_Coverage, 5821,
     /* 363622 */     GIR_EraseRootFromParent_Done,
     /* 363623 */   // Label 7261: @363623
     /* 363623 */   GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(363721), // Rule ID 5823 //
     /* 363628 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363640 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 363644 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363648 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 363657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363661 */     // MIs[2] Operand 1
     /* 363661 */     // No operand predicates
     /* 363661 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 363665 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363669 */     // MIs[3] Operand 1
     /* 363669 */     // No operand predicates
     /* 363669 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 363671 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 363671 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363674 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 363678 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363683 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 363686 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363690 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 363693 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363698 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 363706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363708 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 363710 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 363713 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363716 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 363719 */     GIR_RootConstrainSelectedInstOperands,
     /* 363720 */     // GIR_Coverage, 5823,
     /* 363720 */     GIR_EraseRootFromParent_Done,
     /* 363721 */   // Label 7262: @363721
     /* 363721 */   GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(363787), // Rule ID 5727 //
     /* 363726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 363734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 363738 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 363742 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363744 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), GPR64:{ *:[i64] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), GPR64:{ *:[i64] }:$Rn, dsub:{ *:[i32] })
     /* 363744 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363747 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 363751 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363756 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 363758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 363761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363763 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 363768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 363771 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363776 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363781 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 363786 */     // GIR_Coverage, 5727,
     /* 363786 */     GIR_EraseRootFromParent_Done,
     /* 363787 */   // Label 7263: @363787
     /* 363787 */   GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(363853), // Rule ID 5741 //
     /* 363792 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363796 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 363800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363804 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 363808 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363810 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] })
     /* 363810 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 363813 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 363817 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363822 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 363824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 363827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363829 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363832 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 363834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 363837 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363842 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363847 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363852 */     // GIR_Coverage, 5741,
     /* 363852 */     GIR_EraseRootFromParent_Done,
     /* 363853 */   // Label 7264: @363853
     /* 363853 */   GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(363922), // Rule ID 6514 //
     /* 363858 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 363870 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 363873 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 363877 */     // MIs[1] Rn
     /* 363877 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 363881 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 363886 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 363890 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363894 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363898 */     // MIs[2] Operand 1
     /* 363898 */     // No operand predicates
     /* 363898 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 363900 */     // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LD1i64:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 363900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
     /* 363903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363905 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 363907 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 363910 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 363920 */     GIR_RootConstrainSelectedInstOperands,
     /* 363921 */     // GIR_Coverage, 6514,
     /* 363921 */     GIR_EraseRootFromParent_Done,
     /* 363922 */   // Label 7265: @363922
     /* 363922 */   GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(363991), // Rule ID 6515 //
     /* 363927 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363931 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 363935 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 363939 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 363942 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 363946 */     // MIs[1] Rn
     /* 363946 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 363950 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 363955 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 363959 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 363963 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 363967 */     // MIs[2] Operand 1
     /* 363967 */     // No operand predicates
     /* 363967 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 363969 */     // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LD1i64:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 363969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
     /* 363972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 363974 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 363976 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 363979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 363989 */     GIR_RootConstrainSelectedInstOperands,
     /* 363990 */     // GIR_Coverage, 6515,
     /* 363990 */     GIR_EraseRootFromParent_Done,
     /* 363991 */   // Label 7266: @363991
     /* 363991 */   GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(364073), // Rule ID 7517 //
     /* 363996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 363999 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364003 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 364007 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364011 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 364014 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 364018 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 364025 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 364028 */     // MIs[1] Rn
     /* 364028 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 364032 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 364037 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 364041 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 364045 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 364049 */     // MIs[2] Operand 1
     /* 364049 */     // No operand predicates
     /* 364049 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364051 */     // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_15874>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LDAP1:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 364051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
     /* 364054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364056 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 364058 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 364061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 364065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364071 */     GIR_RootConstrainSelectedInstOperands,
     /* 364072 */     // GIR_Coverage, 7517,
     /* 364072 */     GIR_EraseRootFromParent_Done,
     /* 364073 */   // Label 7267: @364073
     /* 364073 */   GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(364122), // Rule ID 5748 //
     /* 364078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 364082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 364086 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 364090 */     // MIs[1] Operand 1
     /* 364090 */     // No operand predicates
     /* 364090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 364094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 364098 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 364102 */     // MIs[2] Operand 1
     /* 364102 */     // No operand predicates
     /* 364102 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364104 */     // (vector_insert:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (INSvi64gpr:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, XZR:{ *:[i64] })
     /* 364104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
     /* 364107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364109 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 364111 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 364114 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 364120 */     GIR_RootConstrainSelectedInstOperands,
     /* 364121 */     // GIR_Coverage, 5748,
     /* 364121 */     GIR_EraseRootFromParent_Done,
     /* 364122 */   // Label 7268: @364122
     /* 364122 */   GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(364223), // Rule ID 5828 //
     /* 364127 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 364131 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 364135 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 364139 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364144 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 364148 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 364152 */     // MIs[2] Operand 1
     /* 364152 */     // No operand predicates
     /* 364152 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364154 */     // (vector_insert:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src, (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR64:{ *:[f64] }:$Sn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 364154 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 364157 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364161 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364166 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364168 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 364171 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364175 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364180 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364183 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 364187 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 364190 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364195 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364200 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 364208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364210 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 364212 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
     /* 364215 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364221 */     GIR_RootConstrainSelectedInstOperands,
     /* 364222 */     // GIR_Coverage, 5828,
     /* 364222 */     GIR_EraseRootFromParent_Done,
     /* 364223 */   // Label 7269: @364223
     /* 364223 */   GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(364267), // Rule ID 1941 //
     /* 364228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 364231 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 364239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 364243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 364247 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 364251 */     // MIs[1] Operand 1
     /* 364251 */     // No operand predicates
     /* 364251 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364253 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (INSvi64gpr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, GPR64:{ *:[i64] }:$Rn)
     /* 364253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
     /* 364256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364258 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 364260 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 364263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 364265 */     GIR_RootConstrainSelectedInstOperands,
     /* 364266 */     // GIR_Coverage, 1941,
     /* 364266 */     GIR_EraseRootFromParent_Done,
     /* 364267 */   // Label 7270: @364267
     /* 364267 */   GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(364363), // Rule ID 5752 //
     /* 364272 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364276 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 364284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 364288 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 364292 */     // MIs[1] Operand 1
     /* 364292 */     // No operand predicates
     /* 364292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364294 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm, (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 364294 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 364297 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364301 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364306 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364308 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 364311 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364315 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364320 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364323 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 364327 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 364330 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364335 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364340 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 364348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364350 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 364352 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 364355 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364361 */     GIR_RootConstrainSelectedInstOperands,
     /* 364362 */     // GIR_Coverage, 5752,
     /* 364362 */     GIR_EraseRootFromParent_Done,
     /* 364363 */   // Label 7271: @364363
     /* 364363 */   GIM_Reject,
     /* 364364 */ // Label 7236: @364364
     /* 364364 */ GIM_Reject,
     /* 364365 */ // Label 7184: @364365
     /* 364365 */ GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(368004),
     /* 364370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 364373 */   GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(364499), // Rule ID 4305 //
     /* 364378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 364381 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364392 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 364398 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 364400 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 364404 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364408 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364411 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 364415 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 364422 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 364426 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 364430 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364432 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 364439 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 364439 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364442 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 364446 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364466 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364472 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 364477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364482 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 364488 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364493 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364498 */     // GIR_Coverage, 4305,
     /* 364498 */     GIR_EraseRootFromParent_Done,
     /* 364499 */   // Label 7273: @364499
     /* 364499 */   GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(364625), // Rule ID 4306 //
     /* 364504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 364507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364518 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 364524 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 364526 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 364530 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364534 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364537 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 364541 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 364548 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 364552 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 364556 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364558 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 364565 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 364565 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364568 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 364572 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364592 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364598 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 364603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364608 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 364614 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364619 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364624 */     // GIR_Coverage, 4306,
     /* 364624 */     GIR_EraseRootFromParent_Done,
     /* 364625 */   // Label 7274: @364625
     /* 364625 */   GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(364744), // Rule ID 4413 //
     /* 364630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 364633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364644 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 364650 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 364652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 364656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364660 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364663 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 364667 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 364671 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 364675 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364677 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 364684 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 364684 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364687 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 364691 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364711 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364717 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 364722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364727 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 364733 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364738 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364743 */     // GIR_Coverage, 4413,
     /* 364743 */     GIR_EraseRootFromParent_Done,
     /* 364744 */   // Label 7275: @364744
     /* 364744 */   GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(364863), // Rule ID 4414 //
     /* 364749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 364752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364763 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 364769 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 364771 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 364775 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364779 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364782 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 364786 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 364790 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 364794 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364796 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 364803 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 364803 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364806 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 364810 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364830 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364836 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 364841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364846 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 364852 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364857 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364862 */     // GIR_Coverage, 4414,
     /* 364862 */     GIR_EraseRootFromParent_Done,
     /* 364863 */   // Label 7276: @364863
     /* 364863 */   GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(364985), // Rule ID 4311 //
     /* 364868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 364871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364878 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364882 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 364886 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 364890 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 364894 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364897 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 364901 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 364908 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 364912 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 364916 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364918 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 364925 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 364925 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364928 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 364932 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364952 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 364958 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 364963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 364965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 364968 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 364974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364979 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364984 */     // GIR_Coverage, 4311,
     /* 364984 */     GIR_EraseRootFromParent_Done,
     /* 364985 */   // Label 7277: @364985
     /* 364985 */   GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(365107), // Rule ID 4313 //
     /* 364990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 364993 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 364996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 365008 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365012 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365016 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365019 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365023 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365030 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365034 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365038 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365040 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 365047 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 365047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 365054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365074 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365080 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365090 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365096 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365101 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365106 */     // GIR_Coverage, 4313,
     /* 365106 */     GIR_EraseRootFromParent_Done,
     /* 365107 */   // Label 7278: @365107
     /* 365107 */   GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(365222), // Rule ID 4419 //
     /* 365112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 365115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 365130 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365134 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365138 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365141 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365145 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365149 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365153 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365155 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 365162 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 365162 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365165 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 365169 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365189 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365195 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365205 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365211 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365216 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365221 */     // GIR_Coverage, 4419,
     /* 365221 */     GIR_EraseRootFromParent_Done,
     /* 365222 */   // Label 7279: @365222
     /* 365222 */   GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(365337), // Rule ID 4421 //
     /* 365227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 365230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 365245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365253 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365256 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365260 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365264 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365268 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365270 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 365277 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 365277 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365280 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 365284 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365304 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365310 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365320 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365326 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365331 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365336 */     // GIR_Coverage, 4421,
     /* 365336 */     GIR_EraseRootFromParent_Done,
     /* 365337 */   // Label 7280: @365337
     /* 365337 */   GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(365458), // Rule ID 4303 //
     /* 365342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 365345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365352 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365356 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 365362 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 365364 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365368 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365372 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365375 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365379 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365386 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365390 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365394 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365396 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 365403 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 365403 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365406 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 365410 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365425 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365431 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365441 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365447 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365452 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365457 */     // GIR_Coverage, 4303,
     /* 365457 */     GIR_EraseRootFromParent_Done,
     /* 365458 */   // Label 7281: @365458
     /* 365458 */   GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(365579), // Rule ID 4304 //
     /* 365463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 365466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365477 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 365483 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 365485 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365489 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365493 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365496 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365500 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365507 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365511 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365515 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365517 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 365524 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 365524 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365527 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 365531 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365546 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365552 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365562 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365568 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365573 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365578 */     // GIR_Coverage, 4304,
     /* 365578 */     GIR_EraseRootFromParent_Done,
     /* 365579 */   // Label 7282: @365579
     /* 365579 */   GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(365693), // Rule ID 4411 //
     /* 365584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 365587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365594 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365598 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 365604 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 365606 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365610 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365614 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365617 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365621 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365625 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365629 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365631 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 365638 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 365638 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365641 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 365645 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365660 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365666 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365676 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365682 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365687 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365692 */     // GIR_Coverage, 4411,
     /* 365692 */     GIR_EraseRootFromParent_Done,
     /* 365693 */   // Label 7283: @365693
     /* 365693 */   GIM_Try, /*On fail goto*//*Label 7284*/ GIMT_Encode4(365807), // Rule ID 4412 //
     /* 365698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 365701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365712 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 365718 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 365720 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365724 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365728 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365731 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365735 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365739 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365743 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365745 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 365752 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 365752 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365755 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 365759 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365774 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365780 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365790 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365796 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365801 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365806 */     // GIR_Coverage, 4412,
     /* 365806 */     GIR_EraseRootFromParent_Done,
     /* 365807 */   // Label 7284: @365807
     /* 365807 */   GIM_Try, /*On fail goto*//*Label 7285*/ GIMT_Encode4(365924), // Rule ID 4307 //
     /* 365812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 365815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 365830 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365834 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365838 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365841 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365845 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365852 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365856 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365860 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365862 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 365869 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 365869 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365872 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 365876 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365891 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 365897 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 365899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 365902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 365904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 365907 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 365913 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365918 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365923 */     // GIR_Coverage, 4307,
     /* 365923 */     GIR_EraseRootFromParent_Done,
     /* 365924 */   // Label 7285: @365924
     /* 365924 */   GIM_Try, /*On fail goto*//*Label 7286*/ GIMT_Encode4(366041), // Rule ID 4309 //
     /* 365929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 365932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 365935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365939 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365943 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 365947 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 365951 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 365955 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365958 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 365962 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365969 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 365973 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 365977 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 365979 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 365986 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 365986 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 365989 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 365993 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 366008 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 366014 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 366024 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 366030 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366035 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 366040 */     // GIR_Coverage, 4309,
     /* 366040 */     GIR_EraseRootFromParent_Done,
     /* 366041 */   // Label 7286: @366041
     /* 366041 */   GIM_Try, /*On fail goto*//*Label 7287*/ GIMT_Encode4(366151), // Rule ID 4415 //
     /* 366046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 366049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 366064 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 366068 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 366072 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366075 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 366079 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 366083 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 366087 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 366089 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 366096 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 366096 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 366099 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 366103 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 366118 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 366124 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 366134 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 366140 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366145 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 366150 */     // GIR_Coverage, 4415,
     /* 366150 */     GIR_EraseRootFromParent_Done,
     /* 366151 */   // Label 7287: @366151
     /* 366151 */   GIM_Try, /*On fail goto*//*Label 7288*/ GIMT_Encode4(366261), // Rule ID 4417 //
     /* 366156 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 366159 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366166 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366170 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 366174 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 366178 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 366182 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366185 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 366189 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 366193 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 366197 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 366199 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 366206 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 366206 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 366209 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 366213 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 366228 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 366234 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 366244 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 366250 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366255 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 366260 */     // GIR_Coverage, 4417,
     /* 366260 */     GIR_EraseRootFromParent_Done,
     /* 366261 */   // Label 7288: @366261
     /* 366261 */   GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(366391), // Rule ID 6527 //
     /* 366266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 366269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 366272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 366287 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 366291 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 366295 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366298 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 366302 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 366309 */     // MIs[2] Rn
     /* 366309 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 366313 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 366318 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 366322 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 366324 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (LD1i8:{ *:[f128] } (IMPLICIT_DEF:{ *:[v16i8] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 366324 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 366327 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 366331 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366336 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 366338 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 366341 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 366345 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366350 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366353 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 366356 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 366360 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 366366 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366373 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 366380 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366385 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366390 */     // GIR_Coverage, 6527,
     /* 366390 */     GIR_EraseRootFromParent_Done,
     /* 366391 */   // Label 7289: @366391
     /* 366391 */   GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(366531), // Rule ID 5768 //
     /* 366396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 366399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366406 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 366414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 366422 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366426 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366431 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 366435 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366439 */     // MIs[2] Operand 1
     /* 366439 */     // No operand predicates
     /* 366439 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 366443 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366447 */     // MIs[3] Operand 1
     /* 366447 */     // No operand predicates
     /* 366447 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 366449 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 366449 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 366452 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366456 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366461 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 366464 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 366468 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 366471 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366476 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366481 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 366484 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 366488 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366493 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366496 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 366499 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 366506 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366513 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 366520 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366525 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366530 */     // GIR_Coverage, 5768,
     /* 366530 */     GIR_EraseRootFromParent_Done,
     /* 366531 */   // Label 7290: @366531
     /* 366531 */   GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(366702), // Rule ID 5769 //
     /* 366536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 366539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366546 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 366554 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366558 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 366562 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366566 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 366575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366579 */     // MIs[2] Operand 1
     /* 366579 */     // No operand predicates
     /* 366579 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 366583 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366587 */     // MIs[3] Operand 1
     /* 366587 */     // No operand predicates
     /* 366587 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 366589 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 366589 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 366592 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366596 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366601 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 366604 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366608 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 366611 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366616 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366621 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 366624 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366628 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366633 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 366636 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 366640 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 366643 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366648 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366653 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 366656 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 366660 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366665 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366668 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 366671 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366674 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 366677 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366684 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 366691 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366696 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366701 */     // GIR_Coverage, 5769,
     /* 366701 */     GIR_EraseRootFromParent_Done,
     /* 366702 */   // Label 7291: @366702
     /* 366702 */   GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(366842), // Rule ID 5808 //
     /* 366707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 366710 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366717 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 366725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366729 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 366733 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366737 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366742 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 366746 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366750 */     // MIs[2] Operand 1
     /* 366750 */     // No operand predicates
     /* 366750 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 366754 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366758 */     // MIs[3] Operand 1
     /* 366758 */     // No operand predicates
     /* 366758 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 366760 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 366760 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 366763 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366767 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366772 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 366775 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 366779 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 366782 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366787 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366792 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 366795 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 366799 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366804 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366807 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 366810 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366814 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 366817 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366824 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 366831 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366836 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366841 */     // GIR_Coverage, 5808,
     /* 366841 */     GIR_EraseRootFromParent_Done,
     /* 366842 */   // Label 7292: @366842
     /* 366842 */   GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(367013), // Rule ID 5809 //
     /* 366847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 366850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 366853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366861 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 366865 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366869 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 366873 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366877 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366882 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 366886 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366890 */     // MIs[2] Operand 1
     /* 366890 */     // No operand predicates
     /* 366890 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 366894 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 366898 */     // MIs[3] Operand 1
     /* 366898 */     // No operand predicates
     /* 366898 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 366900 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 366900 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 366903 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366907 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366912 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 366915 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366919 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 366922 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366927 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366932 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 366935 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 366939 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366944 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 366947 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 366951 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 366954 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366959 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366964 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 366967 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 366971 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366976 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366979 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 366982 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366985 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 366988 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 366995 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367002 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367007 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367012 */     // GIR_Coverage, 5809,
     /* 367012 */     GIR_EraseRootFromParent_Done,
     /* 367013 */   // Label 7293: @367013
     /* 367013 */   GIM_Try, /*On fail goto*//*Label 7294*/ GIMT_Encode4(367092), // Rule ID 5721 //
     /* 367018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 367021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 367036 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 367040 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 367044 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367046 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 367046 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 367049 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367053 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367058 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 367062 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 367067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 367070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 367075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 367081 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367086 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 367091 */     // GIR_Coverage, 5721,
     /* 367091 */     GIR_EraseRootFromParent_Done,
     /* 367092 */   // Label 7294: @367092
     /* 367092 */   GIM_Try, /*On fail goto*//*Label 7295*/ GIMT_Encode4(367168), // Rule ID 5729 //
     /* 367097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 367100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 367115 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367119 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 367123 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367125 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 367125 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
     /* 367128 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367132 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367137 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367144 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 367149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 367152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367162 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367167 */     // GIR_Coverage, 5729,
     /* 367167 */     GIR_EraseRootFromParent_Done,
     /* 367168 */   // Label 7295: @367168
     /* 367168 */   GIM_Try, /*On fail goto*//*Label 7296*/ GIMT_Encode4(367244), // Rule ID 5733 //
     /* 367173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 367176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 367191 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367195 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 367199 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367201 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 367201 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
     /* 367204 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367208 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367213 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367220 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367223 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 367225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 367228 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367233 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367238 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367243 */     // GIR_Coverage, 5733,
     /* 367243 */     GIR_EraseRootFromParent_Done,
     /* 367244 */   // Label 7296: @367244
     /* 367244 */   GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(367389), // Rule ID 5745 //
     /* 367249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 367252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367259 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 367267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 367271 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 367275 */     // MIs[1] Operand 1
     /* 367275 */     // No operand predicates
     /* 367275 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 367279 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 367283 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 367287 */     // MIs[2] Operand 1
     /* 367287 */     // No operand predicates
     /* 367287 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 367289 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
     /* 367289 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 367292 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367296 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367301 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367303 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 367306 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367310 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367315 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 367318 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 367322 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 367325 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367330 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367335 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 367343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 367347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367352 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367355 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
     /* 367358 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 367364 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367371 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367378 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367383 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367388 */     // GIR_Coverage, 5745,
     /* 367388 */     GIR_EraseRootFromParent_Done,
     /* 367389 */   // Label 7297: @367389
     /* 367389 */   GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(367538), // Rule ID 6531 //
     /* 367394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 367397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367404 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367408 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 367412 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 367416 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367419 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 367423 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 367430 */     // MIs[1] Rn
     /* 367430 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 367434 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 367439 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 367443 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 367447 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 367451 */     // MIs[2] Operand 1
     /* 367451 */     // No operand predicates
     /* 367451 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 367453 */     // (vector_insert:{ *:[v4i16] } VecListOne64:{ *:[v4i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 367453 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 367456 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 367460 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367465 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 367468 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 367472 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 367475 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367480 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367485 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 367488 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 367492 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367497 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367500 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 367503 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 367507 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 367513 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367520 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367527 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367532 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367537 */     // GIR_Coverage, 6531,
     /* 367537 */     GIR_EraseRootFromParent_Done,
     /* 367538 */   // Label 7298: @367538
     /* 367538 */   GIM_Try, /*On fail goto*//*Label 7299*/ GIMT_Encode4(367680), // Rule ID 6534 //
     /* 367543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 367546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367553 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367557 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 367561 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 367565 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367568 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 367572 */     // MIs[1] Rn
     /* 367572 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 367576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 367581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 367585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 367589 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 367593 */     // MIs[2] Operand 1
     /* 367593 */     // No operand predicates
     /* 367593 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 367595 */     // (vector_insert:{ *:[v4f16] } VecListOne64:{ *:[v4f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 367595 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 367598 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 367602 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367607 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 367610 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 367614 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 367617 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367622 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367627 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 367630 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 367634 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367639 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367642 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 367645 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 367649 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 367655 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367662 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367669 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367674 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367679 */     // GIR_Coverage, 6534,
     /* 367679 */     GIR_EraseRootFromParent_Done,
     /* 367680 */   // Label 7299: @367680
     /* 367680 */   GIM_Try, /*On fail goto*//*Label 7300*/ GIMT_Encode4(367868), // Rule ID 5743 //
     /* 367685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 367688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367695 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367699 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367703 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 367707 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 367711 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 367715 */     // MIs[1] Operand 1
     /* 367715 */     // No operand predicates
     /* 367715 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367717 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 367717 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s16,
     /* 367720 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367724 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367729 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 367731 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s16,
     /* 367734 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367738 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367743 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 367746 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 367750 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 367753 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367758 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367763 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367768 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 367771 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367775 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367780 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367782 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 367785 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367789 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367794 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 367797 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 367801 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 367804 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367809 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367814 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367819 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 367822 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 367826 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367831 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367834 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 367837 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 367840 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 367843 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367850 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367857 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367862 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367867 */     // GIR_Coverage, 5743,
     /* 367867 */     GIR_EraseRootFromParent_Done,
     /* 367868 */   // Label 7300: @367868
     /* 367868 */   GIM_Try, /*On fail goto*//*Label 7301*/ GIMT_Encode4(368003), // Rule ID 5754 //
     /* 367873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 367876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 367879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367883 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 367891 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 367895 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 367899 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 367903 */     // MIs[1] Operand 1
     /* 367903 */     // No operand predicates
     /* 367903 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367905 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 367905 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 367908 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367912 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367917 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367919 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 367922 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367926 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367931 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 367934 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 367938 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 367941 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367946 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 367951 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367956 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 367959 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 367963 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367968 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367971 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 367974 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 367978 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 367980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 367983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 367985 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 367992 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367997 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368002 */     // GIR_Coverage, 5754,
     /* 368002 */     GIR_EraseRootFromParent_Done,
     /* 368003 */   // Label 7301: @368003
     /* 368003 */   GIM_Reject,
     /* 368004 */ // Label 7272: @368004
     /* 368004 */ GIM_Reject,
     /* 368005 */ // Label 7185: @368005
     /* 368005 */ GIM_Try, /*On fail goto*//*Label 7302*/ GIMT_Encode4(371072),
     /* 368010 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 368013 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 368016 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 368019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368023 */   GIM_Try, /*On fail goto*//*Label 7303*/ GIMT_Encode4(368132), // Rule ID 4329 //
     /* 368028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368032 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368038 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 368040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368048 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368051 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368055 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368059 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368063 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368065 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 368072 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368072 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368075 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 368079 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368099 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368105 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368115 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368121 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368126 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368131 */     // GIR_Coverage, 4329,
     /* 368131 */     GIR_EraseRootFromParent_Done,
     /* 368132 */   // Label 7303: @368132
     /* 368132 */   GIM_Try, /*On fail goto*//*Label 7304*/ GIMT_Encode4(368241), // Rule ID 4330 //
     /* 368137 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368141 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368147 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 368149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368157 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368160 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368164 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368168 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368172 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368174 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 368181 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368181 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368184 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 368188 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368208 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368214 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368224 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368240 */     // GIR_Coverage, 4330,
     /* 368240 */     GIR_EraseRootFromParent_Done,
     /* 368241 */   // Label 7304: @368241
     /* 368241 */   GIM_Try, /*On fail goto*//*Label 7305*/ GIMT_Encode4(368350), // Rule ID 4437 //
     /* 368246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368250 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368256 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 368258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368266 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368269 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368273 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368277 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368281 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368283 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 368290 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 368297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368317 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368323 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368333 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368339 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368344 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368349 */     // GIR_Coverage, 4437,
     /* 368349 */     GIR_EraseRootFromParent_Done,
     /* 368350 */   // Label 7305: @368350
     /* 368350 */   GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(368459), // Rule ID 4438 //
     /* 368355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368359 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368365 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 368367 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368371 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368375 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368378 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368382 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368386 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368390 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368392 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 368399 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368399 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368402 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 368406 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368426 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368432 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368442 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368448 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368453 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368458 */     // GIR_Coverage, 4438,
     /* 368458 */     GIR_EraseRootFromParent_Done,
     /* 368459 */   // Label 7306: @368459
     /* 368459 */   GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(368564), // Rule ID 4335 //
     /* 368464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 368472 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368476 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368480 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368483 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368487 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368491 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368495 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368497 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 368504 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368504 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368507 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 368511 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368531 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368537 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368547 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368553 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368558 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368563 */     // GIR_Coverage, 4335,
     /* 368563 */     GIR_EraseRootFromParent_Done,
     /* 368564 */   // Label 7307: @368564
     /* 368564 */   GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(368669), // Rule ID 4337 //
     /* 368569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 368577 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368581 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368585 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368588 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368592 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368596 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368600 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368602 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 368609 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368609 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368612 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 368616 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368636 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368642 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368652 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368658 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368663 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368668 */     // GIR_Coverage, 4337,
     /* 368668 */     GIR_EraseRootFromParent_Done,
     /* 368669 */   // Label 7308: @368669
     /* 368669 */   GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(368774), // Rule ID 4443 //
     /* 368674 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368678 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 368682 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368686 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368690 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368693 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368697 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368701 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368705 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368707 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 368714 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368714 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368717 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 368721 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368741 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368747 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368757 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368763 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368768 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368773 */     // GIR_Coverage, 4443,
     /* 368773 */     GIR_EraseRootFromParent_Done,
     /* 368774 */   // Label 7309: @368774
     /* 368774 */   GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(368879), // Rule ID 4445 //
     /* 368779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 368787 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368791 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368795 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368798 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368802 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368806 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368810 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368812 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 368819 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 368819 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368822 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 368826 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 368841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 368846 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368852 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368862 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368868 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368873 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368878 */     // GIR_Coverage, 4445,
     /* 368878 */     GIR_EraseRootFromParent_Done,
     /* 368879 */   // Label 7310: @368879
     /* 368879 */   GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(368983), // Rule ID 4327 //
     /* 368884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368888 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368894 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 368896 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 368900 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 368904 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368907 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 368911 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 368915 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 368919 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 368921 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 368928 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 368928 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368931 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 368935 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 368950 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 368956 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 368961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 368963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 368966 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 368972 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368977 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368982 */     // GIR_Coverage, 4327,
     /* 368982 */     GIR_EraseRootFromParent_Done,
     /* 368983 */   // Label 7311: @368983
     /* 368983 */   GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(369087), // Rule ID 4328 //
     /* 368988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368992 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 368998 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 369000 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369004 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369008 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369011 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369015 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369019 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369023 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369025 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 369032 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 369032 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369035 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 369039 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369054 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369060 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369070 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369076 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369081 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369086 */     // GIR_Coverage, 4328,
     /* 369086 */     GIR_EraseRootFromParent_Done,
     /* 369087 */   // Label 7312: @369087
     /* 369087 */   GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(369191), // Rule ID 4435 //
     /* 369092 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369096 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 369102 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 369104 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369108 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369112 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369115 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369119 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369123 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369127 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369129 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 369136 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 369136 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369139 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 369143 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369158 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369164 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369174 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369180 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369185 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369190 */     // GIR_Coverage, 4435,
     /* 369190 */     GIR_EraseRootFromParent_Done,
     /* 369191 */   // Label 7313: @369191
     /* 369191 */   GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(369295), // Rule ID 4436 //
     /* 369196 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369200 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 369206 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 369208 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369212 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369216 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369219 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369223 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369227 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369231 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369233 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 369240 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 369240 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369243 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 369247 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369262 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369278 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369284 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369289 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369294 */     // GIR_Coverage, 4436,
     /* 369294 */     GIR_EraseRootFromParent_Done,
     /* 369295 */   // Label 7314: @369295
     /* 369295 */   GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(369395), // Rule ID 4331 //
     /* 369300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369308 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369312 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369316 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369319 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369323 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369327 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369331 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369333 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 369340 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 369340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 369347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369362 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369368 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369378 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369384 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369389 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369394 */     // GIR_Coverage, 4331,
     /* 369394 */     GIR_EraseRootFromParent_Done,
     /* 369395 */   // Label 7315: @369395
     /* 369395 */   GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(369495), // Rule ID 4333 //
     /* 369400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369408 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369412 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369416 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369419 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369423 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369427 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369431 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369433 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 369440 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 369440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 369447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369462 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369468 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369478 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369484 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369489 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369494 */     // GIR_Coverage, 4333,
     /* 369494 */     GIR_EraseRootFromParent_Done,
     /* 369495 */   // Label 7316: @369495
     /* 369495 */   GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(369595), // Rule ID 4439 //
     /* 369500 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369504 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369508 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369512 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369516 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369519 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369523 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369527 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369531 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369533 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 369540 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 369540 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369543 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 369547 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369562 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369568 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369578 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369584 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369589 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369594 */     // GIR_Coverage, 4439,
     /* 369594 */     GIR_EraseRootFromParent_Done,
     /* 369595 */   // Label 7317: @369595
     /* 369595 */   GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(369695), // Rule ID 4441 //
     /* 369600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369608 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369612 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 369616 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 369619 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 369623 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 369627 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369631 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 369633 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 369640 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 369640 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 369643 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 369647 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 369657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 369662 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 369668 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 369673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 369678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369684 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369689 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369694 */     // GIR_Coverage, 4441,
     /* 369694 */     GIR_EraseRootFromParent_Done,
     /* 369695 */   // Label 7318: @369695
     /* 369695 */   GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(369808), // Rule ID 5774 //
     /* 369700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369708 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369712 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 369716 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 369720 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 369724 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369729 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 369733 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 369737 */     // MIs[3] Operand 1
     /* 369737 */     // No operand predicates
     /* 369737 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369741 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 369743 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), (DUPi32:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), ssub:{ *:[i32] })
     /* 369743 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 369746 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 369750 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369755 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 369759 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 369762 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 369764 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 369767 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 369771 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369776 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 369781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369783 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369786 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 369789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369792 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369797 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369802 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369807 */     // GIR_Coverage, 5774,
     /* 369807 */     GIR_EraseRootFromParent_Done,
     /* 369808 */   // Label 7319: @369808
     /* 369808 */   GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(369921), // Rule ID 5814 //
     /* 369813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 369821 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 369825 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 369829 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 369833 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 369837 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369842 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 369846 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 369850 */     // MIs[3] Operand 1
     /* 369850 */     // No operand predicates
     /* 369850 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 369854 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 369856 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), (DUPi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), ssub:{ *:[i32] })
     /* 369856 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 369859 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 369863 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369868 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 369872 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 369875 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 369877 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 369880 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 369884 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 369889 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 369891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 369894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369896 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 369899 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 369902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 369905 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369915 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369920 */     // GIR_Coverage, 5814,
     /* 369920 */     GIR_EraseRootFromParent_Done,
     /* 369921 */   // Label 7320: @369921
     /* 369921 */   GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(369999), // Rule ID 1944 //
     /* 369926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 369929 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 369937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 369941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 369945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 369949 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 369954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 369958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 369962 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 369966 */     // MIs[2] Operand 1
     /* 369966 */     // No operand predicates
     /* 369966 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 369970 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 369974 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 369978 */     // MIs[3] Operand 1
     /* 369978 */     // No operand predicates
     /* 369978 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 369980 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 369980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 369983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 369985 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 369987 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 369990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369994 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 369997 */     GIR_RootConstrainSelectedInstOperands,
     /* 369998 */     // GIR_Coverage, 1944,
     /* 369998 */     GIR_EraseRootFromParent_Done,
     /* 369999 */   // Label 7321: @369999
     /* 369999 */   GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(370088), // Rule ID 5771 //
     /* 370004 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370008 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370012 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 370016 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370020 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370024 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370028 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370032 */     // MIs[2] Operand 1
     /* 370032 */     // No operand predicates
     /* 370032 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370036 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370040 */     // MIs[3] Operand 1
     /* 370040 */     // No operand predicates
     /* 370040 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370042 */     // (vector_insert:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v4f32] } ZPR:{ *:[nxv4f32] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn)
     /* 370042 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370045 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 370049 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370054 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 370060 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370065 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 370070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370075 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 370077 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370080 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370083 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370086 */     GIR_RootConstrainSelectedInstOperands,
     /* 370087 */     // GIR_Coverage, 5771,
     /* 370087 */     GIR_EraseRootFromParent_Done,
     /* 370088 */   // Label 7322: @370088
     /* 370088 */   GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(370177), // Rule ID 5811 //
     /* 370093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 370105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370117 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370121 */     // MIs[2] Operand 1
     /* 370121 */     // No operand predicates
     /* 370121 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370125 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370129 */     // MIs[3] Operand 1
     /* 370129 */     // No operand predicates
     /* 370129 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370131 */     // (vector_insert:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn)
     /* 370131 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370134 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 370138 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370143 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 370149 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370154 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 370159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370164 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 370166 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370169 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370172 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370175 */     GIR_RootConstrainSelectedInstOperands,
     /* 370176 */     // GIR_Coverage, 5811,
     /* 370176 */     GIR_EraseRootFromParent_Done,
     /* 370177 */   // Label 7323: @370177
     /* 370177 */   GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(370244), // Rule ID 5773 //
     /* 370182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 370198 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370202 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370207 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370211 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370215 */     // MIs[2] Operand 1
     /* 370215 */     // No operand predicates
     /* 370215 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370219 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370223 */     // MIs[3] Operand 1
     /* 370223 */     // No operand predicates
     /* 370223 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370225 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 370225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370230 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 370232 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370239 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370242 */     GIR_RootConstrainSelectedInstOperands,
     /* 370243 */     // GIR_Coverage, 5773,
     /* 370243 */     GIR_EraseRootFromParent_Done,
     /* 370244 */   // Label 7324: @370244
     /* 370244 */   GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(370342), // Rule ID 5775 //
     /* 370249 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 370265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370269 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370274 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370278 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370282 */     // MIs[2] Operand 1
     /* 370282 */     // No operand predicates
     /* 370282 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370286 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370290 */     // MIs[3] Operand 1
     /* 370290 */     // No operand predicates
     /* 370290 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370292 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 370292 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370295 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 370299 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370304 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 370307 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370311 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 370314 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370319 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370329 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 370331 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370334 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370337 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370340 */     GIR_RootConstrainSelectedInstOperands,
     /* 370341 */     // GIR_Coverage, 5775,
     /* 370341 */     GIR_EraseRootFromParent_Done,
     /* 370342 */   // Label 7325: @370342
     /* 370342 */   GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(370409), // Rule ID 5813 //
     /* 370347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 370363 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370367 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370372 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370376 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370380 */     // MIs[2] Operand 1
     /* 370380 */     // No operand predicates
     /* 370380 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370384 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370388 */     // MIs[3] Operand 1
     /* 370388 */     // No operand predicates
     /* 370388 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370390 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 370390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370395 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 370397 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370404 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370407 */     GIR_RootConstrainSelectedInstOperands,
     /* 370408 */     // GIR_Coverage, 5813,
     /* 370408 */     GIR_EraseRootFromParent_Done,
     /* 370409 */   // Label 7326: @370409
     /* 370409 */   GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(370507), // Rule ID 5815 //
     /* 370414 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 370426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 370430 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 370434 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370439 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 370443 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370447 */     // MIs[2] Operand 1
     /* 370447 */     // No operand predicates
     /* 370447 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 370451 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370455 */     // MIs[3] Operand 1
     /* 370455 */     // No operand predicates
     /* 370455 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 370457 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 370457 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370460 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 370464 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370469 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 370472 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370476 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 370479 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370484 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370494 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 370496 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 370499 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370502 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 370505 */     GIR_RootConstrainSelectedInstOperands,
     /* 370506 */     // GIR_Coverage, 5815,
     /* 370506 */     GIR_EraseRootFromParent_Done,
     /* 370507 */   // Label 7327: @370507
     /* 370507 */   GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(370573), // Rule ID 5725 //
     /* 370512 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370516 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 370520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370524 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 370528 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370530 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), GPR32:{ *:[i32] }:$Rn, ssub:{ *:[i32] })
     /* 370530 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370533 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 370537 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370542 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 370544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 370547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370549 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 370554 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 370557 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370562 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370567 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370572 */     // GIR_Coverage, 5725,
     /* 370572 */     GIR_EraseRootFromParent_Done,
     /* 370573 */   // Label 7328: @370573
     /* 370573 */   GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(370639), // Rule ID 5737 //
     /* 370578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 370586 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370590 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 370594 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370596 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] })
     /* 370596 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 370599 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 370603 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370608 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 370610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 370613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370615 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 370620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 370623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370633 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370638 */     // GIR_Coverage, 5737,
     /* 370638 */     GIR_EraseRootFromParent_Done,
     /* 370639 */   // Label 7329: @370639
     /* 370639 */   GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(370692), // Rule ID 5746 //
     /* 370644 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 370656 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 370660 */     // MIs[1] Operand 1
     /* 370660 */     // No operand predicates
     /* 370660 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 370664 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370668 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370672 */     // MIs[2] Operand 1
     /* 370672 */     // No operand predicates
     /* 370672 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 370674 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (INSvi32gpr:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] })
     /* 370674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 370677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370679 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 370681 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 370684 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 370690 */     GIR_RootConstrainSelectedInstOperands,
     /* 370691 */     // GIR_Coverage, 5746,
     /* 370691 */     GIR_EraseRootFromParent_Done,
     /* 370692 */   // Label 7330: @370692
     /* 370692 */   GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(370761), // Rule ID 6512 //
     /* 370697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 370709 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 370712 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 370716 */     // MIs[1] Rn
     /* 370716 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 370720 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 370725 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 370729 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370733 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370737 */     // MIs[2] Operand 1
     /* 370737 */     // No operand predicates
     /* 370737 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 370739 */     // (vector_insert:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (LD1i32:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 370739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 370742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370744 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 370746 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 370749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 370759 */     GIR_RootConstrainSelectedInstOperands,
     /* 370760 */     // GIR_Coverage, 6512,
     /* 370760 */     GIR_EraseRootFromParent_Done,
     /* 370761 */   // Label 7331: @370761
     /* 370761 */   GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(370830), // Rule ID 6513 //
     /* 370766 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 370778 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 370781 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 370785 */     // MIs[1] Rn
     /* 370785 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 370789 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 370794 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 370798 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370802 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370806 */     // MIs[2] Operand 1
     /* 370806 */     // No operand predicates
     /* 370806 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 370808 */     // (vector_insert:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (LD1i32:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 370808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 370811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370813 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 370815 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 370818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 370828 */     GIR_RootConstrainSelectedInstOperands,
     /* 370829 */     // GIR_Coverage, 6513,
     /* 370829 */     GIR_EraseRootFromParent_Done,
     /* 370830 */   // Label 7332: @370830
     /* 370830 */   GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(370931), // Rule ID 5826 //
     /* 370835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 370839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 370843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370847 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370852 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 370856 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370860 */     // MIs[2] Operand 1
     /* 370860 */     // No operand predicates
     /* 370860 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 370862 */     // (vector_insert:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 370862 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 370865 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 370869 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 370876 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 370879 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 370883 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 370888 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 370891 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 370895 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 370898 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370903 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370908 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 370916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370918 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 370920 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
     /* 370923 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 370926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 370929 */     GIR_RootConstrainSelectedInstOperands,
     /* 370930 */     // GIR_Coverage, 5826,
     /* 370930 */     GIR_EraseRootFromParent_Done,
     /* 370931 */   // Label 7333: @370931
     /* 370931 */   GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(370975), // Rule ID 1940 //
     /* 370936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 370939 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370943 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370947 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 370951 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370955 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 370959 */     // MIs[1] Operand 1
     /* 370959 */     // No operand predicates
     /* 370959 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370961 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (INSvi32gpr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 370961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 370964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 370966 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 370968 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 370971 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 370973 */     GIR_RootConstrainSelectedInstOperands,
     /* 370974 */     // GIR_Coverage, 1940,
     /* 370974 */     GIR_EraseRootFromParent_Done,
     /* 370975 */   // Label 7334: @370975
     /* 370975 */   GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(371071), // Rule ID 5751 //
     /* 370980 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 370992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 370996 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 371000 */     // MIs[1] Operand 1
     /* 371000 */     // No operand predicates
     /* 371000 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371002 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 371002 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 371005 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 371009 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371014 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 371016 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 371019 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 371023 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371028 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 371031 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 371035 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 371038 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 371043 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 371048 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 371056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371058 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 371060 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 371063 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371069 */     GIR_RootConstrainSelectedInstOperands,
     /* 371070 */     // GIR_Coverage, 5751,
     /* 371070 */     GIR_EraseRootFromParent_Done,
     /* 371071 */   // Label 7335: @371071
     /* 371071 */   GIM_Reject,
     /* 371072 */ // Label 7302: @371072
     /* 371072 */ GIM_Reject,
     /* 371073 */ // Label 7186: @371073
     /* 371073 */ GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(374285),
     /* 371078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 371081 */   GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(371200), // Rule ID 4233 //
     /* 371086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 371089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371096 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371100 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 371106 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 371108 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371112 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371116 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371119 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371123 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371127 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371131 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371133 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 371140 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371140 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371143 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 371147 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371167 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371173 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371183 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371189 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371194 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371199 */     // GIR_Coverage, 4233,
     /* 371199 */     GIR_EraseRootFromParent_Done,
     /* 371200 */   // Label 7337: @371200
     /* 371200 */   GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(371319), // Rule ID 4234 //
     /* 371205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 371208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371215 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371219 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 371225 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 371227 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371231 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371235 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371238 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371242 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371246 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371250 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371252 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 371259 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371259 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371262 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 371266 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371286 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371292 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371302 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371313 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371318 */     // GIR_Coverage, 4234,
     /* 371318 */     GIR_EraseRootFromParent_Done,
     /* 371319 */   // Label 7338: @371319
     /* 371319 */   GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(371445), // Rule ID 4269 //
     /* 371324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 371327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371334 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371338 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 371344 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 371346 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371350 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371354 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371357 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371361 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 371368 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371372 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371376 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371378 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 371385 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 371392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371412 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371418 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371428 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371434 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371439 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371444 */     // GIR_Coverage, 4269,
     /* 371444 */     GIR_EraseRootFromParent_Done,
     /* 371445 */   // Label 7339: @371445
     /* 371445 */   GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(371571), // Rule ID 4270 //
     /* 371450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 371453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371464 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 371470 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 371472 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371476 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371480 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371483 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371487 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 371494 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371498 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371502 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371504 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 371511 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371511 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371514 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 371518 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371538 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371544 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371554 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371560 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371565 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371570 */     // GIR_Coverage, 4270,
     /* 371570 */     GIR_EraseRootFromParent_Done,
     /* 371571 */   // Label 7340: @371571
     /* 371571 */   GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(371686), // Rule ID 4239 //
     /* 371576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 371579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371586 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371590 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 371594 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371598 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371602 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371605 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371609 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371613 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371617 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371619 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 371626 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371626 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371629 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 371633 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371653 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371659 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371669 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371675 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371680 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371685 */     // GIR_Coverage, 4239,
     /* 371685 */     GIR_EraseRootFromParent_Done,
     /* 371686 */   // Label 7341: @371686
     /* 371686 */   GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(371801), // Rule ID 4241 //
     /* 371691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 371694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 371709 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371713 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371717 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371720 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371724 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371728 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371732 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371734 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 371741 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371741 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371744 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 371748 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371768 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371774 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371784 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371790 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371795 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371800 */     // GIR_Coverage, 4241,
     /* 371800 */     GIR_EraseRootFromParent_Done,
     /* 371801 */   // Label 7342: @371801
     /* 371801 */   GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(371923), // Rule ID 4275 //
     /* 371806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 371809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 371824 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371828 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371832 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371835 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371839 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 371846 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371850 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371856 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 371863 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371863 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371866 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 371870 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 371880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 371885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 371890 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 371896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 371898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 371901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 371906 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 371909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 371912 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371917 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 371922 */     // GIR_Coverage, 4275,
     /* 371922 */     GIR_EraseRootFromParent_Done,
     /* 371923 */   // Label 7343: @371923
     /* 371923 */   GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(372045), // Rule ID 4277 //
     /* 371928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 371931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 371934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 371946 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 371950 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 371954 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 371957 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 371961 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 371968 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 371972 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 371976 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 371978 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 371985 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 371985 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 371988 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 371992 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 372007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 372012 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372018 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372028 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372034 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372039 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372044 */     // GIR_Coverage, 4277,
     /* 372044 */     GIR_EraseRootFromParent_Done,
     /* 372045 */   // Label 7344: @372045
     /* 372045 */   GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(372159), // Rule ID 4231 //
     /* 372050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 372053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372064 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 372070 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 372072 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372076 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372080 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372083 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372087 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372091 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372095 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372097 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 372104 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 372104 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372107 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 372111 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372126 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372132 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372142 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372148 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372153 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372158 */     // GIR_Coverage, 4231,
     /* 372158 */     GIR_EraseRootFromParent_Done,
     /* 372159 */   // Label 7345: @372159
     /* 372159 */   GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(372273), // Rule ID 4232 //
     /* 372164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 372167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372178 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 372184 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 372186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372194 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372197 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372201 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372205 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372209 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372211 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 372218 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 372218 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 372225 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372240 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372246 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372256 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372262 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372267 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372272 */     // GIR_Coverage, 4232,
     /* 372272 */     GIR_EraseRootFromParent_Done,
     /* 372273 */   // Label 7346: @372273
     /* 372273 */   GIM_Try, /*On fail goto*//*Label 7347*/ GIMT_Encode4(372394), // Rule ID 4267 //
     /* 372278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 372281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372288 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372292 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 372298 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 372300 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372304 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372308 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372311 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372315 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 372322 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372326 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372330 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372332 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 372339 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 372339 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372342 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 372346 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372361 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372367 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372377 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372383 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372388 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372393 */     // GIR_Coverage, 4267,
     /* 372393 */     GIR_EraseRootFromParent_Done,
     /* 372394 */   // Label 7347: @372394
     /* 372394 */   GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(372515), // Rule ID 4268 //
     /* 372399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 372402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372409 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372413 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 372419 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 372421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372429 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372432 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372436 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 372443 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372447 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372451 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372453 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 372460 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 372460 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372463 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 372467 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372482 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372488 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372498 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372504 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372509 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372514 */     // GIR_Coverage, 4268,
     /* 372514 */     GIR_EraseRootFromParent_Done,
     /* 372515 */   // Label 7348: @372515
     /* 372515 */   GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(372625), // Rule ID 4235 //
     /* 372520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 372523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 372538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372546 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372549 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372553 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372557 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372561 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372563 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 372570 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 372570 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372573 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 372577 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372592 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372598 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372608 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372614 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372619 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372624 */     // GIR_Coverage, 4235,
     /* 372624 */     GIR_EraseRootFromParent_Done,
     /* 372625 */   // Label 7349: @372625
     /* 372625 */   GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(372735), // Rule ID 4237 //
     /* 372630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 372633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 372648 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372652 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372656 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372659 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372663 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372667 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372671 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372673 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 372680 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 372680 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372683 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 372687 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372702 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372708 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372718 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372724 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372729 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372734 */     // GIR_Coverage, 4237,
     /* 372734 */     GIR_EraseRootFromParent_Done,
     /* 372735 */   // Label 7350: @372735
     /* 372735 */   GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(372852), // Rule ID 4271 //
     /* 372740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 372743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372750 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372754 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 372758 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372762 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372766 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372769 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372773 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 372780 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372784 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372788 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372790 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 372797 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 372797 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372800 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 372804 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372819 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372835 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372841 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372846 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372851 */     // GIR_Coverage, 4271,
     /* 372851 */     GIR_EraseRootFromParent_Done,
     /* 372852 */   // Label 7351: @372852
     /* 372852 */   GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(372969), // Rule ID 4273 //
     /* 372857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 372860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 372875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 372879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 372883 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 372886 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 372890 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 372897 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 372901 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 372905 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 372907 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 372914 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 372914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 372917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 372921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 372926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 372931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 372936 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 372942 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 372944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 372947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 372952 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 372955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 372958 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372963 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 372968 */     // GIR_Coverage, 4273,
     /* 372968 */     GIR_EraseRootFromParent_Done,
     /* 372969 */   // Label 7352: @372969
     /* 372969 */   GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(373109), // Rule ID 5792 //
     /* 372974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 372977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 372980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372984 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 372992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 372996 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 373000 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 373004 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373009 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 373013 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373017 */     // MIs[2] Operand 1
     /* 373017 */     // No operand predicates
     /* 373017 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 373021 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373025 */     // MIs[3] Operand 1
     /* 373025 */     // No operand predicates
     /* 373025 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 373027 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 373027 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 373030 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373034 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373039 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373042 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 373046 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373049 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373054 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373059 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373062 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 373066 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373071 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 373077 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373081 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 373084 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373091 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373098 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373103 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373108 */     // GIR_Coverage, 5792,
     /* 373108 */     GIR_EraseRootFromParent_Done,
     /* 373109 */   // Label 7353: @373109
     /* 373109 */   GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(373280), // Rule ID 5793 //
     /* 373114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 373117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373124 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373128 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 373132 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 373136 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 373140 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 373144 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 373153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373157 */     // MIs[2] Operand 1
     /* 373157 */     // No operand predicates
     /* 373157 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 373161 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373165 */     // MIs[3] Operand 1
     /* 373165 */     // No operand predicates
     /* 373165 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 373167 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 373167 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 373170 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373174 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373179 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 373182 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373186 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 373189 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373194 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373199 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 373202 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373206 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373211 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373214 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 373218 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373221 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373226 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373231 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373234 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 373238 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373243 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373246 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 373249 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 373252 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 373255 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373262 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373269 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373274 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373279 */     // GIR_Coverage, 5793,
     /* 373279 */     GIR_EraseRootFromParent_Done,
     /* 373280 */   // Label 7354: @373280
     /* 373280 */   GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(373420), // Rule ID 5800 //
     /* 373285 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373288 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373295 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373299 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 373303 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 373307 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 373311 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 373315 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373320 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 373324 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373328 */     // MIs[2] Operand 1
     /* 373328 */     // No operand predicates
     /* 373328 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 373332 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373336 */     // MIs[3] Operand 1
     /* 373336 */     // No operand predicates
     /* 373336 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 373338 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 373338 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 373341 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373345 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373350 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373353 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 373357 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373360 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373365 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373370 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373373 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 373377 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373382 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373385 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 373388 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373392 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 373395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373402 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373409 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373414 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373419 */     // GIR_Coverage, 5800,
     /* 373419 */     GIR_EraseRootFromParent_Done,
     /* 373420 */   // Label 7355: @373420
     /* 373420 */   GIM_Try, /*On fail goto*//*Label 7356*/ GIMT_Encode4(373591), // Rule ID 5801 //
     /* 373425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 373443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 373447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 373451 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 373455 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 373464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373468 */     // MIs[2] Operand 1
     /* 373468 */     // No operand predicates
     /* 373468 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 373472 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373476 */     // MIs[3] Operand 1
     /* 373476 */     // No operand predicates
     /* 373476 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 373478 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 373478 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 373481 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373485 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373490 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 373493 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373497 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 373500 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373505 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373510 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 373513 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373517 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373522 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373525 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 373529 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373532 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373537 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373542 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373545 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 373549 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373554 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373557 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 373560 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 373563 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 373566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373573 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373580 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373585 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373590 */     // GIR_Coverage, 5801,
     /* 373590 */     GIR_EraseRootFromParent_Done,
     /* 373591 */   // Label 7356: @373591
     /* 373591 */   GIM_Try, /*On fail goto*//*Label 7357*/ GIMT_Encode4(373670), // Rule ID 5716 //
     /* 373596 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373599 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373606 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 373610 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 373614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 373618 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 373622 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 373624 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 373624 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 373627 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373631 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373636 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 373640 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 373653 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 373656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 373659 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373664 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373669 */     // GIR_Coverage, 5716,
     /* 373669 */     GIR_EraseRootFromParent_Done,
     /* 373670 */   // Label 7357: @373670
     /* 373670 */   GIM_Try, /*On fail goto*//*Label 7358*/ GIMT_Encode4(373812), // Rule ID 6529 //
     /* 373675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 373678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373685 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373689 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 373693 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 373697 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 373700 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 373704 */     // MIs[1] Rn
     /* 373704 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 373708 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 373713 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 373717 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373721 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 373725 */     // MIs[2] Operand 1
     /* 373725 */     // No operand predicates
     /* 373725 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 373727 */     // (vector_insert:{ *:[v8i8] } VecListOne64:{ *:[v8i8] }:$Rd, (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (LD1i8:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 373727 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 373730 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373734 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373739 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373742 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 373746 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373749 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373754 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373759 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373762 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 373766 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373771 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373774 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 373777 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373781 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 373787 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373794 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373801 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373806 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373811 */     // GIR_Coverage, 6529,
     /* 373811 */     GIR_EraseRootFromParent_Done,
     /* 373812 */   // Label 7358: @373812
     /* 373812 */   GIM_Try, /*On fail goto*//*Label 7359*/ GIMT_Encode4(373961), // Rule ID 6530 //
     /* 373817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373827 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373831 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 373835 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 373839 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 373842 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 373846 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 373853 */     // MIs[1] Rn
     /* 373853 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 373857 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 373862 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 373866 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373870 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 373874 */     // MIs[2] Operand 1
     /* 373874 */     // No operand predicates
     /* 373874 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 373876 */     // (vector_insert:{ *:[v8i8] } VecListOne64:{ *:[v8i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (LD1i8:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 373876 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 373879 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 373883 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373888 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 373891 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 373895 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 373898 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373903 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373908 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 373911 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 373915 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 373920 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 373923 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 373926 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 373930 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 373936 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 373938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 373941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 373943 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 373950 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373955 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373960 */     // GIR_Coverage, 6530,
     /* 373960 */     GIR_EraseRootFromParent_Done,
     /* 373961 */   // Label 7359: @373961
     /* 373961 */   GIM_Try, /*On fail goto*//*Label 7360*/ GIMT_Encode4(374096), // Rule ID 5755 //
     /* 373966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 373972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 373984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 373988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 373992 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 373996 */     // MIs[1] Operand 1
     /* 373996 */     // No operand predicates
     /* 373996 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 373998 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 373998 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 374001 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 374005 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374010 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 374012 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 374015 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 374019 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374024 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 374027 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 374031 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 374034 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374039 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374044 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374049 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 374052 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
     /* 374056 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374061 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 374064 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 374067 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 374071 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 374076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374078 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 374085 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374090 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374095 */     // GIR_Coverage, 5755,
     /* 374095 */     GIR_EraseRootFromParent_Done,
     /* 374096 */   // Label 7360: @374096
     /* 374096 */   GIM_Try, /*On fail goto*//*Label 7361*/ GIMT_Encode4(374284), // Rule ID 5756 //
     /* 374101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 374104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374115 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 374119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 374123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 374127 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 374131 */     // MIs[1] Operand 1
     /* 374131 */     // No operand predicates
     /* 374131 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 374133 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 374133 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s8,
     /* 374136 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 374140 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374145 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 374147 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /* 374150 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 374154 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374159 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 374162 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 374166 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
     /* 374169 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374174 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374179 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 374184 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 374187 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 374191 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374196 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 374198 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 374201 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 374205 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374210 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 374213 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 374217 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 374220 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374225 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374230 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374235 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 374238 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 374242 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374247 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 374250 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 374253 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 374256 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 374259 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 374264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374266 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 374273 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374278 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374283 */     // GIR_Coverage, 5756,
     /* 374283 */     GIR_EraseRootFromParent_Done,
     /* 374284 */   // Label 7361: @374284
     /* 374284 */   GIM_Reject,
     /* 374285 */ // Label 7336: @374285
     /* 374285 */ GIM_Reject,
     /* 374286 */ // Label 7187: @374286
     /* 374286 */ GIM_Try, /*On fail goto*//*Label 7362*/ GIMT_Encode4(377704),
     /* 374291 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 374294 */   GIM_Try, /*On fail goto*//*Label 7363*/ GIMT_Encode4(374420), // Rule ID 4293 //
     /* 374299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 374302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374309 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374313 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 374319 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 374321 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374325 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374329 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374332 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374336 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 374343 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374347 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374353 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 374360 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374360 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374363 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 374367 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374387 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 374393 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 374398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 374403 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 374406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 374409 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374414 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374419 */     // GIR_Coverage, 4293,
     /* 374419 */     GIR_EraseRootFromParent_Done,
     /* 374420 */   // Label 7363: @374420
     /* 374420 */   GIM_Try, /*On fail goto*//*Label 7364*/ GIMT_Encode4(374546), // Rule ID 4294 //
     /* 374425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 374428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374439 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 374445 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 374447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374455 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374458 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374462 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 374469 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374473 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374477 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374479 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 374486 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374486 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374489 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 374493 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374513 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 374519 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 374524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 374529 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 374532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 374535 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374540 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374545 */     // GIR_Coverage, 4294,
     /* 374545 */     GIR_EraseRootFromParent_Done,
     /* 374546 */   // Label 7364: @374546
     /* 374546 */   GIM_Try, /*On fail goto*//*Label 7365*/ GIMT_Encode4(374665), // Rule ID 4401 //
     /* 374551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 374554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374565 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 374571 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 374573 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374577 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374581 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374584 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374588 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374592 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374596 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374598 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 374605 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374605 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374608 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 374612 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374632 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 374638 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 374643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 374648 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 374651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 374654 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374659 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374664 */     // GIR_Coverage, 4401,
     /* 374664 */     GIR_EraseRootFromParent_Done,
     /* 374665 */   // Label 7365: @374665
     /* 374665 */   GIM_Try, /*On fail goto*//*Label 7366*/ GIMT_Encode4(374784), // Rule ID 4402 //
     /* 374670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 374673 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374680 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374684 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 374690 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 374692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374700 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374703 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374707 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374711 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374715 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374717 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 374724 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374724 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374727 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 374731 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374751 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 374757 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 374762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 374767 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 374770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 374773 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374778 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374783 */     // GIR_Coverage, 4402,
     /* 374783 */     GIR_EraseRootFromParent_Done,
     /* 374784 */   // Label 7366: @374784
     /* 374784 */   GIM_Try, /*On fail goto*//*Label 7367*/ GIMT_Encode4(374906), // Rule ID 4299 //
     /* 374789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 374792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 374807 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374811 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374815 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374818 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374822 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 374829 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374833 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374837 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374839 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 374846 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374846 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374849 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 374853 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374873 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 374879 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 374881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 374884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 374886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 374889 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 374892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 374895 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374905 */     // GIR_Coverage, 4299,
     /* 374905 */     GIR_EraseRootFromParent_Done,
     /* 374906 */   // Label 7367: @374906
     /* 374906 */   GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(375028), // Rule ID 4301 //
     /* 374911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 374914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 374917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 374929 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374933 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 374937 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 374940 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 374944 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 374951 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 374955 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 374959 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374961 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 374968 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 374968 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 374971 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 374975 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 374980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 374985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 374990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 374995 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375001 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375011 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375017 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375022 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375027 */     // GIR_Coverage, 4301,
     /* 375027 */     GIR_EraseRootFromParent_Done,
     /* 375028 */   // Label 7368: @375028
     /* 375028 */   GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(375143), // Rule ID 4407 //
     /* 375033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375043 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375047 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 375051 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375055 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375059 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375062 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375066 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375070 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375074 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375076 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 375083 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 375083 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375086 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 375090 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 375105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 375110 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375116 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375126 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375132 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375137 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375142 */     // GIR_Coverage, 4407,
     /* 375142 */     GIR_EraseRootFromParent_Done,
     /* 375143 */   // Label 7369: @375143
     /* 375143 */   GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(375258), // Rule ID 4409 //
     /* 375148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 375166 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375170 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375174 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375177 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375181 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375185 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375189 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375191 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 375198 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 375198 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375201 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 375205 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 375220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 375225 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375231 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375241 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375247 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375252 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375257 */     // GIR_Coverage, 4409,
     /* 375257 */     GIR_EraseRootFromParent_Done,
     /* 375258 */   // Label 7370: @375258
     /* 375258 */   GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(375379), // Rule ID 4291 //
     /* 375263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 375266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375277 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 375283 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 375285 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375289 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375293 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375296 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375300 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 375307 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375311 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375315 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375317 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 375324 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 375324 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375327 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 375331 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375346 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375352 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375362 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375368 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375373 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375378 */     // GIR_Coverage, 4291,
     /* 375378 */     GIR_EraseRootFromParent_Done,
     /* 375379 */   // Label 7371: @375379
     /* 375379 */   GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(375500), // Rule ID 4292 //
     /* 375384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 375387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375398 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 375404 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 375406 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375410 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375414 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375417 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375421 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 375428 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375432 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375436 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375438 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 375445 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 375445 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375448 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 375452 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375467 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375473 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375483 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375489 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375494 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375499 */     // GIR_Coverage, 4292,
     /* 375499 */     GIR_EraseRootFromParent_Done,
     /* 375500 */   // Label 7372: @375500
     /* 375500 */   GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(375614), // Rule ID 4399 //
     /* 375505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375519 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 375525 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 375527 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375531 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375535 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375538 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375542 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375546 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375550 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375552 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 375559 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 375559 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375562 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 375566 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375581 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375587 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375603 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375608 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375613 */     // GIR_Coverage, 4399,
     /* 375613 */     GIR_EraseRootFromParent_Done,
     /* 375614 */   // Label 7373: @375614
     /* 375614 */   GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(375728), // Rule ID 4400 //
     /* 375619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375633 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 375639 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 375641 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375645 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375649 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375652 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375656 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375660 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375666 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 375673 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 375673 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375676 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 375680 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375695 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375701 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375711 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375717 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375722 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375727 */     // GIR_Coverage, 4400,
     /* 375727 */     GIR_EraseRootFromParent_Done,
     /* 375728 */   // Label 7374: @375728
     /* 375728 */   GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(375845), // Rule ID 4295 //
     /* 375733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 375736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 375751 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375755 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375759 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375762 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375766 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 375773 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375777 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375781 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375783 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 375790 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 375790 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375793 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 375797 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375812 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375818 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375828 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375834 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375839 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375844 */     // GIR_Coverage, 4295,
     /* 375844 */     GIR_EraseRootFromParent_Done,
     /* 375845 */   // Label 7375: @375845
     /* 375845 */   GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(375962), // Rule ID 4297 //
     /* 375850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 375853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375860 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375864 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 375868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375876 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375879 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 375883 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 375890 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 375894 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 375898 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375900 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 375907 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 375907 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 375910 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 375914 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 375919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 375924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 375929 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 375935 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 375937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 375940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 375942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375945 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 375948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 375951 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375956 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375961 */     // GIR_Coverage, 4297,
     /* 375961 */     GIR_EraseRootFromParent_Done,
     /* 375962 */   // Label 7376: @375962
     /* 375962 */   GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(376072), // Rule ID 4403 //
     /* 375967 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375970 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 375973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375977 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375981 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 375985 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375989 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 375993 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 375996 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 376000 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 376004 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 376008 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 376010 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 376017 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 376017 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 376020 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 376024 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 376034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 376039 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 376045 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 376047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 376050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 376055 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 376061 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376066 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 376071 */     // GIR_Coverage, 4403,
     /* 376071 */     GIR_EraseRootFromParent_Done,
     /* 376072 */   // Label 7377: @376072
     /* 376072 */   GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(376182), // Rule ID 4405 //
     /* 376077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 376080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376087 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 376091 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 376095 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 376099 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 376103 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 376106 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 376110 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 376114 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 376118 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 376120 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 376127 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 376127 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 376130 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 376134 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 376144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 376149 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 376155 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 376157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 376160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 376165 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 376171 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376176 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 376181 */     // GIR_Coverage, 4405,
     /* 376181 */     GIR_EraseRootFromParent_Done,
     /* 376182 */   // Label 7378: @376182
     /* 376182 */   GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(376305), // Rule ID 5766 //
     /* 376187 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 376190 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 376201 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 376205 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 376209 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376213 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376217 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 376221 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376226 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 376230 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376234 */     // MIs[3] Operand 1
     /* 376234 */     // No operand predicates
     /* 376234 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 376238 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376240 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), (DUPi16:{ *:[i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), hsub:{ *:[i32] })
     /* 376240 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 376243 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 376247 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376252 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 376256 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 376259 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 376261 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 376264 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 376268 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376273 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 376275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 376278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376280 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376283 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 376286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 376289 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376294 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376299 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 376304 */     // GIR_Coverage, 5766,
     /* 376304 */     GIR_EraseRootFromParent_Done,
     /* 376305 */   // Label 7379: @376305
     /* 376305 */   GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(376428), // Rule ID 5806 //
     /* 376310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 376324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 376328 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 376332 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376336 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376340 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 376344 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376349 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 376353 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376357 */     // MIs[3] Operand 1
     /* 376357 */     // No operand predicates
     /* 376357 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 376361 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376363 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), (DUPi16:{ *:[i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), hsub:{ *:[i32] })
     /* 376363 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 376366 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 376370 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376375 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 376379 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 376382 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 376384 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 376387 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 376391 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376396 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 376398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 376401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376403 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376406 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 376409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 376412 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376417 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376422 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 376427 */     // GIR_Coverage, 5806,
     /* 376427 */     GIR_EraseRootFromParent_Done,
     /* 376428 */   // Label 7380: @376428
     /* 376428 */   GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(376516), // Rule ID 1943 //
     /* 376433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376462 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376471 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376475 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376479 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 376483 */     // MIs[2] Operand 1
     /* 376483 */     // No operand predicates
     /* 376483 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376487 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376491 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 376495 */     // MIs[3] Operand 1
     /* 376495 */     // No operand predicates
     /* 376495 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376497 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 376497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376502 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 376504 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 376507 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 376511 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 376514 */     GIR_RootConstrainSelectedInstOperands,
     /* 376515 */     // GIR_Coverage, 1943,
     /* 376515 */     GIR_EraseRootFromParent_Done,
     /* 376516 */   // Label 7381: @376516
     /* 376516 */   GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(376615), // Rule ID 5763 //
     /* 376521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 376524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376531 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376535 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376539 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 376543 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376547 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376551 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376555 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 376559 */     // MIs[2] Operand 1
     /* 376559 */     // No operand predicates
     /* 376559 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376563 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376567 */     // MIs[3] Operand 1
     /* 376567 */     // No operand predicates
     /* 376567 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376569 */     // (vector_insert:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v8f16] } ZPR:{ *:[nxv8f16] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn)
     /* 376569 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 376572 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 376576 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376581 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 376587 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376592 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 376597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376602 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376604 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 376607 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376610 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 376613 */     GIR_RootConstrainSelectedInstOperands,
     /* 376614 */     // GIR_Coverage, 5763,
     /* 376614 */     GIR_EraseRootFromParent_Done,
     /* 376615 */   // Label 7382: @376615
     /* 376615 */   GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(376714), // Rule ID 5803 //
     /* 376620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 376642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376646 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376650 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376654 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 376658 */     // MIs[2] Operand 1
     /* 376658 */     // No operand predicates
     /* 376658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376662 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376666 */     // MIs[3] Operand 1
     /* 376666 */     // No operand predicates
     /* 376666 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376668 */     // (vector_insert:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn)
     /* 376668 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 376671 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 376675 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376680 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 376686 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376691 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 376696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376701 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376703 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 376706 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376709 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 376712 */     GIR_RootConstrainSelectedInstOperands,
     /* 376713 */     // GIR_Coverage, 5803,
     /* 376713 */     GIR_EraseRootFromParent_Done,
     /* 376714 */   // Label 7383: @376714
     /* 376714 */   GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(376791), // Rule ID 5765 //
     /* 376719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 376722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376745 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376749 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376754 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376758 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376762 */     // MIs[2] Operand 1
     /* 376762 */     // No operand predicates
     /* 376762 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376766 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376770 */     // MIs[3] Operand 1
     /* 376770 */     // No operand predicates
     /* 376770 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376772 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 376772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376777 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 376779 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 376782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 376786 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 376789 */     GIR_RootConstrainSelectedInstOperands,
     /* 376790 */     // GIR_Coverage, 5765,
     /* 376790 */     GIR_EraseRootFromParent_Done,
     /* 376791 */   // Label 7384: @376791
     /* 376791 */   GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(376899), // Rule ID 5767 //
     /* 376796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 376799 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376806 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 376822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376831 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376839 */     // MIs[2] Operand 1
     /* 376839 */     // No operand predicates
     /* 376839 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376843 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376847 */     // MIs[3] Operand 1
     /* 376847 */     // No operand predicates
     /* 376847 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376849 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 376849 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 376852 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 376856 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 376861 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 376864 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 376868 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 376871 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376876 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376886 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 376888 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 376891 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 376894 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 376897 */     GIR_RootConstrainSelectedInstOperands,
     /* 376898 */     // GIR_Coverage, 5767,
     /* 376898 */     GIR_EraseRootFromParent_Done,
     /* 376899 */   // Label 7385: @376899
     /* 376899 */   GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(376976), // Rule ID 5805 //
     /* 376904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376914 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376918 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376922 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 376926 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376930 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376934 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376939 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376943 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376947 */     // MIs[2] Operand 1
     /* 376947 */     // No operand predicates
     /* 376947 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 376951 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376955 */     // MIs[3] Operand 1
     /* 376955 */     // No operand predicates
     /* 376955 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 376957 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 376957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 376960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 376962 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 376964 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 376967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 376971 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 376974 */     GIR_RootConstrainSelectedInstOperands,
     /* 376975 */     // GIR_Coverage, 5805,
     /* 376975 */     GIR_EraseRootFromParent_Done,
     /* 376976 */   // Label 7386: @376976
     /* 376976 */   GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(377084), // Rule ID 5807 //
     /* 376981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 376987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376991 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 377003 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 377007 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 377011 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377016 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 377020 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377024 */     // MIs[2] Operand 1
     /* 377024 */     // No operand predicates
     /* 377024 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 377028 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377032 */     // MIs[3] Operand 1
     /* 377032 */     // No operand predicates
     /* 377032 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 377034 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 377034 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 377037 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 377041 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377046 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 377049 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 377053 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 377056 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377061 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 377069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377071 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 377073 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 377076 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377079 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 377082 */     GIR_RootConstrainSelectedInstOperands,
     /* 377083 */     // GIR_Coverage, 5807,
     /* 377083 */     GIR_EraseRootFromParent_Done,
     /* 377084 */   // Label 7387: @377084
     /* 377084 */   GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(377163), // Rule ID 5719 //
     /* 377089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 377107 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377111 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 377115 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377117 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 377117 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 377120 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 377124 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377129 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 377133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 377138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 377141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 377146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 377152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 377162 */     // GIR_Coverage, 5719,
     /* 377162 */     GIR_EraseRootFromParent_Done,
     /* 377163 */   // Label 7388: @377163
     /* 377163 */   GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(377239), // Rule ID 5731 //
     /* 377168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 377171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377178 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377182 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 377186 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377190 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 377194 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377196 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 377196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 377199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 377203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377208 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 377210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 377213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377215 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 377220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 377223 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377228 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377233 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377238 */     // GIR_Coverage, 5731,
     /* 377238 */     GIR_EraseRootFromParent_Done,
     /* 377239 */   // Label 7389: @377239
     /* 377239 */   GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(377315), // Rule ID 5735 //
     /* 377244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 377247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 377262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377266 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 377270 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377272 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 377272 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 377275 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 377279 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377284 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 377286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 377289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377291 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 377296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 377299 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377309 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377314 */     // GIR_Coverage, 5735,
     /* 377314 */     GIR_EraseRootFromParent_Done,
     /* 377315 */   // Label 7390: @377315
     /* 377315 */   GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(377378), // Rule ID 5744 //
     /* 377320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 377323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377330 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377334 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377338 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 377342 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 377346 */     // MIs[1] Operand 1
     /* 377346 */     // No operand predicates
     /* 377346 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 377350 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377354 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 377358 */     // MIs[2] Operand 1
     /* 377358 */     // No operand predicates
     /* 377358 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 377360 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (INSvi16gpr:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] })
     /* 377360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 377363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377365 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377367 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 377370 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 377376 */     GIR_RootConstrainSelectedInstOperands,
     /* 377377 */     // GIR_Coverage, 5744,
     /* 377377 */     GIR_EraseRootFromParent_Done,
     /* 377378 */   // Label 7391: @377378
     /* 377378 */   GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(377464), // Rule ID 6511 //
     /* 377383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377393 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 377405 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 377408 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 377412 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 377419 */     // MIs[1] Rn
     /* 377419 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 377423 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 377428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 377432 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377436 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 377440 */     // MIs[2] Operand 1
     /* 377440 */     // No operand predicates
     /* 377440 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 377442 */     // (vector_insert:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (LD1i16:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 377442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 377445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377447 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 377449 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 377452 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 377456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 377462 */     GIR_RootConstrainSelectedInstOperands,
     /* 377463 */     // GIR_Coverage, 6511,
     /* 377463 */     GIR_EraseRootFromParent_Done,
     /* 377464 */   // Label 7392: @377464
     /* 377464 */   GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(377543), // Rule ID 6516 //
     /* 377469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 377472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377479 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377483 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377487 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 377491 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 377494 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 377498 */     // MIs[1] Rn
     /* 377498 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 377502 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 377507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 377511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377515 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 377519 */     // MIs[2] Operand 1
     /* 377519 */     // No operand predicates
     /* 377519 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 377521 */     // (vector_insert:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (LD1i16:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 377521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 377524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377526 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 377528 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 377531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 377535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 377541 */     GIR_RootConstrainSelectedInstOperands,
     /* 377542 */     // GIR_Coverage, 6516,
     /* 377542 */     GIR_EraseRootFromParent_Done,
     /* 377543 */   // Label 7393: @377543
     /* 377543 */   GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(377597), // Rule ID 1939 //
     /* 377548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377565 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 377573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377577 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 377581 */     // MIs[1] Operand 1
     /* 377581 */     // No operand predicates
     /* 377581 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377583 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (INSvi16gpr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 377583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 377586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377588 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 377590 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 377593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 377595 */     GIR_RootConstrainSelectedInstOperands,
     /* 377596 */     // GIR_Coverage, 1939,
     /* 377596 */     GIR_EraseRootFromParent_Done,
     /* 377597 */   // Label 7394: @377597
     /* 377597 */   GIM_Try, /*On fail goto*//*Label 7395*/ GIMT_Encode4(377703), // Rule ID 5749 //
     /* 377602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 377605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377612 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377616 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377620 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 377624 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377628 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 377632 */     // MIs[1] Operand 1
     /* 377632 */     // No operand predicates
     /* 377632 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377634 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 377634 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 377637 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 377641 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377646 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 377648 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 377651 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 377655 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377660 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 377663 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 377667 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 377670 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377675 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377680 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 377685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 377688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377690 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377692 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 377695 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 377701 */     GIR_RootConstrainSelectedInstOperands,
     /* 377702 */     // GIR_Coverage, 5749,
     /* 377702 */     GIR_EraseRootFromParent_Done,
     /* 377703 */   // Label 7395: @377703
     /* 377703 */   GIM_Reject,
     /* 377704 */ // Label 7362: @377704
     /* 377704 */ GIM_Reject,
     /* 377705 */ // Label 7188: @377705
     /* 377705 */ GIM_Try, /*On fail goto*//*Label 7396*/ GIMT_Encode4(380908),
     /* 377710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 377713 */   GIM_Try, /*On fail goto*//*Label 7397*/ GIMT_Encode4(377832), // Rule ID 4221 //
     /* 377718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 377721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377732 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 377738 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 377740 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 377744 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 377748 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 377751 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 377755 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 377759 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 377763 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 377765 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 377772 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 377772 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 377775 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 377779 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 377789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 377794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 377799 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 377805 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 377807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 377810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 377815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 377821 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377826 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 377831 */     // GIR_Coverage, 4221,
     /* 377831 */     GIR_EraseRootFromParent_Done,
     /* 377832 */   // Label 7397: @377832
     /* 377832 */   GIM_Try, /*On fail goto*//*Label 7398*/ GIMT_Encode4(377951), // Rule ID 4222 //
     /* 377837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 377840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377847 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377851 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 377857 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 377859 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 377863 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 377867 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 377870 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 377874 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 377878 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 377882 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 377884 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 377891 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 377891 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 377894 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 377898 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 377903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 377908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 377913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 377918 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 377924 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 377926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 377929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 377931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 377934 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 377937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 377940 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377945 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 377950 */     // GIR_Coverage, 4222,
     /* 377950 */     GIR_EraseRootFromParent_Done,
     /* 377951 */   // Label 7398: @377951
     /* 377951 */   GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(378077), // Rule ID 4257 //
     /* 377956 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377959 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 377962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 377970 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 377976 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 377978 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 377982 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 377986 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 377989 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 377993 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 378000 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378004 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378008 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378010 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 378017 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378017 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378020 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 378024 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378044 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378050 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378060 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378066 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378071 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378076 */     // GIR_Coverage, 4257,
     /* 378076 */     GIR_EraseRootFromParent_Done,
     /* 378077 */   // Label 7399: @378077
     /* 378077 */   GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(378203), // Rule ID 4258 //
     /* 378082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 378085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378092 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378096 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 378102 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 378104 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378108 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378112 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378115 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378119 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 378126 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378130 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378134 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378136 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 378143 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378143 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378146 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 378150 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378170 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378176 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378186 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378192 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378197 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378202 */     // GIR_Coverage, 4258,
     /* 378202 */     GIR_EraseRootFromParent_Done,
     /* 378203 */   // Label 7400: @378203
     /* 378203 */   GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(378318), // Rule ID 4227 //
     /* 378208 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 378211 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 378226 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378230 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378234 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378237 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378241 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378245 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378249 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378251 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 378258 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378258 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378261 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 378265 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378285 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378291 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378301 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378307 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378312 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378317 */     // GIR_Coverage, 4227,
     /* 378317 */     GIR_EraseRootFromParent_Done,
     /* 378318 */   // Label 7401: @378318
     /* 378318 */   GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(378433), // Rule ID 4229 //
     /* 378323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 378326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378333 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378337 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 378341 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378345 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378349 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378352 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378356 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378360 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378364 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378366 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 378373 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378373 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378376 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 378380 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378400 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378406 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378416 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378422 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378427 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378432 */     // GIR_Coverage, 4229,
     /* 378432 */     GIR_EraseRootFromParent_Done,
     /* 378433 */   // Label 7402: @378433
     /* 378433 */   GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(378555), // Rule ID 4263 //
     /* 378438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 378441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 378456 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378460 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378464 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378467 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378471 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 378478 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378482 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378486 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378488 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 378495 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378495 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378498 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 378502 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378522 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378528 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378538 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378544 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378554 */     // GIR_Coverage, 4263,
     /* 378554 */     GIR_EraseRootFromParent_Done,
     /* 378555 */   // Label 7403: @378555
     /* 378555 */   GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(378677), // Rule ID 4265 //
     /* 378560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 378563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378574 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 378578 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378582 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378586 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378589 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378593 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 378600 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378604 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378608 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378610 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 378617 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 378617 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 378624 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 378639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 378644 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378650 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378660 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378666 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378671 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378676 */     // GIR_Coverage, 4265,
     /* 378676 */     GIR_EraseRootFromParent_Done,
     /* 378677 */   // Label 7404: @378677
     /* 378677 */   GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(378791), // Rule ID 4219 //
     /* 378682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 378685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378696 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 378702 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 378704 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378708 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378712 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378715 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378719 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378723 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378727 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378729 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 378736 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 378736 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378739 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 378743 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 378758 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378764 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378774 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378780 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378785 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378790 */     // GIR_Coverage, 4219,
     /* 378790 */     GIR_EraseRootFromParent_Done,
     /* 378791 */   // Label 7405: @378791
     /* 378791 */   GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(378905), // Rule ID 4220 //
     /* 378796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 378799 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378810 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 378816 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 378818 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378822 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378826 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378829 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378833 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378837 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378841 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378843 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 378850 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 378850 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378853 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 378857 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 378872 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378878 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 378880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 378883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 378885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 378888 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 378894 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 378904 */     // GIR_Coverage, 4220,
     /* 378904 */     GIR_EraseRootFromParent_Done,
     /* 378905 */   // Label 7406: @378905
     /* 378905 */   GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(379026), // Rule ID 4255 //
     /* 378910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 378913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 378916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378924 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 378930 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 378932 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 378936 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 378940 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 378943 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 378947 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 378954 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 378958 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 378962 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378964 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 378971 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 378971 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 378974 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 378978 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 378988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 378993 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 378999 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379009 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379015 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379020 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379025 */     // GIR_Coverage, 4255,
     /* 379025 */     GIR_EraseRootFromParent_Done,
     /* 379026 */   // Label 7407: @379026
     /* 379026 */   GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(379147), // Rule ID 4256 //
     /* 379031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 379034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379045 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 379051 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 379053 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379057 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 379061 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 379064 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 379068 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 379075 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 379079 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379083 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 379085 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 379092 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 379092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 379095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 379099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 379109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 379114 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 379120 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379130 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379136 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379141 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379146 */     // GIR_Coverage, 4256,
     /* 379146 */     GIR_EraseRootFromParent_Done,
     /* 379147 */   // Label 7408: @379147
     /* 379147 */   GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(379257), // Rule ID 4223 //
     /* 379152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 379155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379162 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379166 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379170 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379174 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 379178 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 379181 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 379185 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 379189 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379193 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 379195 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 379202 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 379202 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 379205 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 379209 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 379219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 379224 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 379230 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379246 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379251 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379256 */     // GIR_Coverage, 4223,
     /* 379256 */     GIR_EraseRootFromParent_Done,
     /* 379257 */   // Label 7409: @379257
     /* 379257 */   GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(379367), // Rule ID 4225 //
     /* 379262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 379265 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 379288 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 379291 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 379295 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 379299 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379303 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 379305 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 379312 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 379312 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 379315 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 379319 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 379329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 379334 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 379340 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379350 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379356 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379361 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379366 */     // GIR_Coverage, 4225,
     /* 379366 */     GIR_EraseRootFromParent_Done,
     /* 379367 */   // Label 7410: @379367
     /* 379367 */   GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(379484), // Rule ID 4259 //
     /* 379372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 379375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379382 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379386 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379390 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379394 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 379398 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 379401 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 379405 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 379412 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 379416 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379420 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 379422 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 379429 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 379429 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 379432 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 379436 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 379446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 379451 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 379457 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379467 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379473 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379478 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379483 */     // GIR_Coverage, 4259,
     /* 379483 */     GIR_EraseRootFromParent_Done,
     /* 379484 */   // Label 7411: @379484
     /* 379484 */   GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(379601), // Rule ID 4261 //
     /* 379489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 379492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 379515 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 379518 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 379522 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 379529 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 379533 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379537 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 379539 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 379546 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 379546 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 379549 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 379553 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 379563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 379568 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 379574 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 379579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 379584 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379590 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379595 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379600 */     // GIR_Coverage, 4261,
     /* 379600 */     GIR_EraseRootFromParent_Done,
     /* 379601 */   // Label 7412: @379601
     /* 379601 */   GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(379724), // Rule ID 5790 //
     /* 379606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 379609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379616 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379620 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379624 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379628 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 379632 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 379636 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 379640 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379645 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 379649 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379653 */     // MIs[3] Operand 1
     /* 379653 */     // No operand predicates
     /* 379653 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379657 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 379659 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (DUPi8:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), bsub:{ *:[i32] })
     /* 379659 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s8,
     /* 379662 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi8),
     /* 379666 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379671 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 379675 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 379678 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 379680 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 379683 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 379687 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379692 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 379697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379699 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379702 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 379705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379708 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379713 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379718 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379723 */     // GIR_Coverage, 5790,
     /* 379723 */     GIR_EraseRootFromParent_Done,
     /* 379724 */   // Label 7413: @379724
     /* 379724 */   GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(379847), // Rule ID 5798 //
     /* 379729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 379732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379739 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379743 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 379747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 379751 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 379755 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 379759 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 379763 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379768 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 379772 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379776 */     // MIs[3] Operand 1
     /* 379776 */     // No operand predicates
     /* 379776 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 379780 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 379782 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (DUPi8:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), bsub:{ *:[i32] })
     /* 379782 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s8,
     /* 379785 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi8),
     /* 379789 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379794 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 379798 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 379801 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 379803 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 379806 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 379810 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379815 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 379820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379822 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 379825 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 379828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 379831 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379836 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379841 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 379846 */     // GIR_Coverage, 5798,
     /* 379846 */     GIR_EraseRootFromParent_Done,
     /* 379847 */   // Label 7414: @379847
     /* 379847 */   GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(379935), // Rule ID 1942 //
     /* 379852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 379855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 379858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379865 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 379873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 379877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 379881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 379885 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379890 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 379894 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379898 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 379902 */     // MIs[2] Operand 1
     /* 379902 */     // No operand predicates
     /* 379902 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 379906 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379910 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 379914 */     // MIs[3] Operand 1
     /* 379914 */     // No operand predicates
     /* 379914 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 379916 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 379916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 379919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379921 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 379923 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 379926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 379930 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 379933 */     GIR_RootConstrainSelectedInstOperands,
     /* 379934 */     // GIR_Coverage, 1942,
     /* 379934 */     GIR_EraseRootFromParent_Done,
     /* 379935 */   // Label 7415: @379935
     /* 379935 */   GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(380034), // Rule ID 5787 //
     /* 379940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 379943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 379946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 379954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 379958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 379962 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 379966 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 379970 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379974 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 379978 */     // MIs[2] Operand 1
     /* 379978 */     // No operand predicates
     /* 379978 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 379982 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 379986 */     // MIs[3] Operand 1
     /* 379986 */     // No operand predicates
     /* 379986 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 379988 */     // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (vector_extract:{ *:[i8] } nxv16i8:{ *:[nxv16i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn)
     /* 379988 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 379991 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379995 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380000 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 380006 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380011 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 380016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380021 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 380023 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380026 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380029 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380032 */     GIR_RootConstrainSelectedInstOperands,
     /* 380033 */     // GIR_Coverage, 5787,
     /* 380033 */     GIR_EraseRootFromParent_Done,
     /* 380034 */   // Label 7416: @380034
     /* 380034 */   GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(380133), // Rule ID 5795 //
     /* 380039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380049 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380053 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 380057 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 380061 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 380065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 380069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380073 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 380077 */     // MIs[2] Operand 1
     /* 380077 */     // No operand predicates
     /* 380077 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 380081 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380085 */     // MIs[3] Operand 1
     /* 380085 */     // No operand predicates
     /* 380085 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 380087 */     // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn)
     /* 380087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 380090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380099 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 380105 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380110 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 380115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380120 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 380122 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380125 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380128 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380131 */     GIR_RootConstrainSelectedInstOperands,
     /* 380132 */     // GIR_Coverage, 5795,
     /* 380132 */     GIR_EraseRootFromParent_Done,
     /* 380133 */   // Label 7417: @380133
     /* 380133 */   GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(380210), // Rule ID 5789 //
     /* 380138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 380141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380148 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380152 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380156 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 380160 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 380164 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 380168 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380173 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 380177 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380181 */     // MIs[2] Operand 1
     /* 380181 */     // No operand predicates
     /* 380181 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 380185 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380189 */     // MIs[3] Operand 1
     /* 380189 */     // No operand predicates
     /* 380189 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 380191 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 380191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380196 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 380198 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380205 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380208 */     GIR_RootConstrainSelectedInstOperands,
     /* 380209 */     // GIR_Coverage, 5789,
     /* 380209 */     GIR_EraseRootFromParent_Done,
     /* 380210 */   // Label 7418: @380210
     /* 380210 */   GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(380318), // Rule ID 5791 //
     /* 380215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 380218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 380237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 380241 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 380245 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 380254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380258 */     // MIs[2] Operand 1
     /* 380258 */     // No operand predicates
     /* 380258 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 380262 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380266 */     // MIs[3] Operand 1
     /* 380266 */     // No operand predicates
     /* 380266 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 380268 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 380268 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 380271 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 380275 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380280 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 380283 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380287 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 380290 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380295 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380305 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 380307 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380310 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380313 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380316 */     GIR_RootConstrainSelectedInstOperands,
     /* 380317 */     // GIR_Coverage, 5791,
     /* 380317 */     GIR_EraseRootFromParent_Done,
     /* 380318 */   // Label 7419: @380318
     /* 380318 */   GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(380395), // Rule ID 5797 //
     /* 380323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380333 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380337 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380341 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 380345 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 380349 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 380353 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380358 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 380362 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380366 */     // MIs[2] Operand 1
     /* 380366 */     // No operand predicates
     /* 380366 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 380370 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380374 */     // MIs[3] Operand 1
     /* 380374 */     // No operand predicates
     /* 380374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 380376 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 380376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380381 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 380383 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380386 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380390 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380393 */     GIR_RootConstrainSelectedInstOperands,
     /* 380394 */     // GIR_Coverage, 5797,
     /* 380394 */     GIR_EraseRootFromParent_Done,
     /* 380395 */   // Label 7420: @380395
     /* 380395 */   GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(380503), // Rule ID 5799 //
     /* 380400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380403 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 380422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 380426 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 380430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380435 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 380439 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380443 */     // MIs[2] Operand 1
     /* 380443 */     // No operand predicates
     /* 380443 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 380447 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380451 */     // MIs[3] Operand 1
     /* 380451 */     // No operand predicates
     /* 380451 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 380453 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 380453 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 380456 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 380460 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380465 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 380468 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380472 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 380475 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380480 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380490 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 380492 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 380495 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380498 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 380501 */     GIR_RootConstrainSelectedInstOperands,
     /* 380502 */     // GIR_Coverage, 5799,
     /* 380502 */     GIR_EraseRootFromParent_Done,
     /* 380503 */   // Label 7421: @380503
     /* 380503 */   GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(380582), // Rule ID 5714 //
     /* 380508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380518 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 380522 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 380526 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 380530 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 380534 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 380536 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 380536 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 380539 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380543 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380548 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 380552 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 380557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 380560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 380565 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 380571 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380576 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 380581 */     // GIR_Coverage, 5714,
     /* 380581 */     GIR_EraseRootFromParent_Done,
     /* 380582 */   // Label 7422: @380582
     /* 380582 */   GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(380661), // Rule ID 6509 //
     /* 380587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 380590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380597 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380601 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 380609 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 380612 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 380616 */     // MIs[1] Rn
     /* 380616 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 380620 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 380625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 380629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380633 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 380637 */     // MIs[2] Operand 1
     /* 380637 */     // No operand predicates
     /* 380637 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 380639 */     // (vector_insert:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (LD1i8:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 380639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 380642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380644 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 380646 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 380649 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380653 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 380659 */     GIR_RootConstrainSelectedInstOperands,
     /* 380660 */     // GIR_Coverage, 6509,
     /* 380660 */     GIR_EraseRootFromParent_Done,
     /* 380661 */   // Label 7423: @380661
     /* 380661 */   GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(380747), // Rule ID 6510 //
     /* 380666 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380676 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380680 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 380684 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 380688 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 380691 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 380695 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 380702 */     // MIs[1] Rn
     /* 380702 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 380706 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 380711 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 380715 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380719 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 380723 */     // MIs[2] Operand 1
     /* 380723 */     // No operand predicates
     /* 380723 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 380725 */     // (vector_insert:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (LD1i8:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 380725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 380728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380730 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 380732 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 380735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 380739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 380745 */     GIR_RootConstrainSelectedInstOperands,
     /* 380746 */     // GIR_Coverage, 6510,
     /* 380746 */     GIR_EraseRootFromParent_Done,
     /* 380747 */   // Label 7424: @380747
     /* 380747 */   GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(380801), // Rule ID 1938 //
     /* 380752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 380755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 380758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 380773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 380777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380781 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 380785 */     // MIs[1] Operand 1
     /* 380785 */     // No operand predicates
     /* 380785 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 380787 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (INSvi8gpr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 380787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
     /* 380790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380792 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 380794 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 380797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 380799 */     GIR_RootConstrainSelectedInstOperands,
     /* 380800 */     // GIR_Coverage, 1938,
     /* 380800 */     GIR_EraseRootFromParent_Done,
     /* 380801 */   // Label 7425: @380801
     /* 380801 */   GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(380907), // Rule ID 5757 //
     /* 380806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 380809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380816 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 380824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 380828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 380832 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 380836 */     // MIs[1] Operand 1
     /* 380836 */     // No operand predicates
     /* 380836 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 380838 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 380838 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 380841 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 380845 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380850 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380852 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 380855 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 380859 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380864 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380867 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 380871 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 380874 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380879 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380884 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 380889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 380892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380894 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 380896 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 380899 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 380905 */     GIR_RootConstrainSelectedInstOperands,
     /* 380906 */     // GIR_Coverage, 5757,
     /* 380906 */     GIR_EraseRootFromParent_Done,
     /* 380907 */   // Label 7426: @380907
     /* 380907 */   GIM_Reject,
     /* 380908 */ // Label 7396: @380908
     /* 380908 */ GIM_Reject,
     /* 380909 */ // Label 7189: @380909
     /* 380909 */ GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(381033), // Rule ID 11317 //
     /* 380914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380917 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 380920 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 380923 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 380926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 380930 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 380934 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 380938 */   // (vector_insert:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv2f16] } ZPR:{ *:[nxv2f16] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f16] }:$src)
     /* 380938 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 380941 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 380945 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380950 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 380954 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 380956 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 380959 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 380963 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380968 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 380971 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 380974 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 380976 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380979 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 380983 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380988 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 380991 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380993 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380996 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 381000 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381005 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381008 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 381011 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 381014 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 381017 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381019 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 381022 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 381024 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 381026 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381029 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 381031 */   GIR_RootConstrainSelectedInstOperands,
     /* 381032 */   // GIR_Coverage, 11317,
     /* 381032 */   GIR_EraseRootFromParent_Done,
     /* 381033 */ // Label 7427: @381033
     /* 381033 */ GIM_Reject,
     /* 381034 */ // Label 7190: @381034
     /* 381034 */ GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(381158), // Rule ID 11320 //
     /* 381039 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381042 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 381045 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 381048 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 381051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381055 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 381059 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 381063 */   // (vector_insert:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_S:{ *:[nxv2f32] } ZPR:{ *:[nxv2f32] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f32] }:$src)
     /* 381063 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 381066 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 381070 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381075 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 381079 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 381081 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 381084 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 381088 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381093 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 381096 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 381099 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381101 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381104 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 381108 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381113 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 381116 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381118 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381121 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 381125 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381130 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381133 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 381136 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 381139 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 381142 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
     /* 381147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 381149 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 381151 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381154 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 381156 */   GIR_RootConstrainSelectedInstOperands,
     /* 381157 */   // GIR_Coverage, 11320,
     /* 381157 */   GIR_EraseRootFromParent_Done,
     /* 381158 */ // Label 7428: @381158
     /* 381158 */ GIM_Reject,
     /* 381159 */ // Label 7191: @381159
     /* 381159 */ GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(383136),
     /* 381164 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 381167 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 381170 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 381173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381177 */   GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(381286), // Rule ID 4389 //
     /* 381182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381186 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 381192 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 381194 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381198 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381202 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381205 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381209 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381213 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381217 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381219 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 381226 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381226 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381229 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 381233 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381253 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381259 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381269 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381275 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381280 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381285 */     // GIR_Coverage, 4389,
     /* 381285 */     GIR_EraseRootFromParent_Done,
     /* 381286 */   // Label 7430: @381286
     /* 381286 */   GIM_Try, /*On fail goto*//*Label 7431*/ GIMT_Encode4(381395), // Rule ID 4390 //
     /* 381291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381295 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 381301 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 381303 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381307 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381311 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381314 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381318 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381322 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381326 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381328 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 381335 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381335 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381338 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 381342 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381362 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381368 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381378 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381384 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381389 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381394 */     // GIR_Coverage, 4390,
     /* 381394 */     GIR_EraseRootFromParent_Done,
     /* 381395 */   // Label 7431: @381395
     /* 381395 */   GIM_Try, /*On fail goto*//*Label 7432*/ GIMT_Encode4(381504), // Rule ID 4497 //
     /* 381400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381404 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 381410 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 381412 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381416 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381420 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381423 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381427 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381431 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381435 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381437 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 381444 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381444 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381447 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 381451 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381471 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381477 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381487 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381493 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381498 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381503 */     // GIR_Coverage, 4497,
     /* 381503 */     GIR_EraseRootFromParent_Done,
     /* 381504 */   // Label 7432: @381504
     /* 381504 */   GIM_Try, /*On fail goto*//*Label 7433*/ GIMT_Encode4(381613), // Rule ID 4498 //
     /* 381509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381513 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 381519 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 381521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381525 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381529 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381532 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381536 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381540 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381544 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381546 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 381553 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381553 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381556 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 381560 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381580 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381586 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381596 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381602 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381607 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381612 */     // GIR_Coverage, 4498,
     /* 381612 */     GIR_EraseRootFromParent_Done,
     /* 381613 */   // Label 7433: @381613
     /* 381613 */   GIM_Try, /*On fail goto*//*Label 7434*/ GIMT_Encode4(381718), // Rule ID 4395 //
     /* 381618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 381626 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381630 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381634 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381637 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381641 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381645 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381649 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381651 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 381658 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381658 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381661 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 381665 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381685 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381691 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381701 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381707 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381712 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381717 */     // GIR_Coverage, 4395,
     /* 381717 */     GIR_EraseRootFromParent_Done,
     /* 381718 */   // Label 7434: @381718
     /* 381718 */   GIM_Try, /*On fail goto*//*Label 7435*/ GIMT_Encode4(381823), // Rule ID 4397 //
     /* 381723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 381731 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381735 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381739 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381742 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381746 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381750 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381754 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381756 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 381763 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381763 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381766 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 381770 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381790 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381796 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381806 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381812 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381817 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381822 */     // GIR_Coverage, 4397,
     /* 381822 */     GIR_EraseRootFromParent_Done,
     /* 381823 */   // Label 7435: @381823
     /* 381823 */   GIM_Try, /*On fail goto*//*Label 7436*/ GIMT_Encode4(381928), // Rule ID 4503 //
     /* 381828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381832 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 381836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381844 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381847 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381851 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381855 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381859 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381861 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 381868 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381868 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381871 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 381875 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 381895 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 381901 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 381906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 381908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 381911 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 381917 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 381922 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 381927 */     // GIR_Coverage, 4503,
     /* 381927 */     GIR_EraseRootFromParent_Done,
     /* 381928 */   // Label 7436: @381928
     /* 381928 */   GIM_Try, /*On fail goto*//*Label 7437*/ GIMT_Encode4(382033), // Rule ID 4505 //
     /* 381933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 381937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 381941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 381945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 381949 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 381952 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 381956 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 381960 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 381964 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 381966 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 381973 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 381973 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 381976 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 381980 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 381990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 381995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 382000 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382006 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382022 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382027 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382032 */     // GIR_Coverage, 4505,
     /* 382032 */     GIR_EraseRootFromParent_Done,
     /* 382033 */   // Label 7437: @382033
     /* 382033 */   GIM_Try, /*On fail goto*//*Label 7438*/ GIMT_Encode4(382137), // Rule ID 4387 //
     /* 382038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382042 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 382048 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 382050 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382058 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382061 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382065 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382069 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382073 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382075 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 382082 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 382082 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382085 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 382089 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382104 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382110 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382120 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382126 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382131 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382136 */     // GIR_Coverage, 4387,
     /* 382136 */     GIR_EraseRootFromParent_Done,
     /* 382137 */   // Label 7438: @382137
     /* 382137 */   GIM_Try, /*On fail goto*//*Label 7439*/ GIMT_Encode4(382241), // Rule ID 4388 //
     /* 382142 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382146 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 382152 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 382154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382162 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382165 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382169 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382173 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382177 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382179 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 382186 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 382186 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382189 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 382193 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382208 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382214 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382224 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382240 */     // GIR_Coverage, 4388,
     /* 382240 */     GIR_EraseRootFromParent_Done,
     /* 382241 */   // Label 7439: @382241
     /* 382241 */   GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(382345), // Rule ID 4495 //
     /* 382246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382250 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 382256 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 382258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382266 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382269 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382273 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382277 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382281 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382283 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 382290 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 382290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 382297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382312 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382318 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382328 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382334 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382339 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382344 */     // GIR_Coverage, 4495,
     /* 382344 */     GIR_EraseRootFromParent_Done,
     /* 382345 */   // Label 7440: @382345
     /* 382345 */   GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(382449), // Rule ID 4496 //
     /* 382350 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382354 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 382360 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 382362 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382366 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382370 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382373 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382377 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382381 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382385 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382387 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 382394 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 382394 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382397 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 382401 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382416 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382422 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382432 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382438 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382443 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382448 */     // GIR_Coverage, 4496,
     /* 382448 */     GIR_EraseRootFromParent_Done,
     /* 382449 */   // Label 7441: @382449
     /* 382449 */   GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(382549), // Rule ID 4391 //
     /* 382454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 382462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382470 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382473 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382477 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382481 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382485 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382487 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 382494 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 382494 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382497 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 382501 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382516 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382522 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382532 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382538 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382543 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382548 */     // GIR_Coverage, 4391,
     /* 382548 */     GIR_EraseRootFromParent_Done,
     /* 382549 */   // Label 7442: @382549
     /* 382549 */   GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(382649), // Rule ID 4393 //
     /* 382554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 382562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382570 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382573 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382577 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382581 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382587 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 382594 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 382594 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382597 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 382601 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382616 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382622 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382632 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382638 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382648 */     // GIR_Coverage, 4393,
     /* 382648 */     GIR_EraseRootFromParent_Done,
     /* 382649 */   // Label 7443: @382649
     /* 382649 */   GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(382749), // Rule ID 4499 //
     /* 382654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 382662 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382666 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382670 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382673 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382677 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382681 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382685 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382687 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 382694 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 382694 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382697 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 382701 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382716 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382722 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382732 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382738 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382743 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382748 */     // GIR_Coverage, 4499,
     /* 382748 */     GIR_EraseRootFromParent_Done,
     /* 382749 */   // Label 7444: @382749
     /* 382749 */   GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(382849), // Rule ID 4501 //
     /* 382754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 382762 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382766 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 382770 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 382773 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 382777 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 382781 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382785 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 382787 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 382794 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 382794 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 382797 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 382801 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 382811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 382816 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 382822 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 382827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 382829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 382832 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 382838 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 382843 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 382848 */     // GIR_Coverage, 4501,
     /* 382848 */     GIR_EraseRootFromParent_Done,
     /* 382849 */   // Label 7445: @382849
     /* 382849 */   GIM_Try, /*On fail goto*//*Label 7446*/ GIMT_Encode4(382913), // Rule ID 11375 //
     /* 382854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 382861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 382865 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 382869 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 382873 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 382877 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 382881 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 382885 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 382889 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 382893 */     // MIs[3] Operand 1
     /* 382893 */     // No operand predicates
     /* 382893 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 382897 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 382899 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$Idx)
     /* 382899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 382902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 382904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 382908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 382911 */     GIR_RootConstrainSelectedInstOperands,
     /* 382912 */     // GIR_Coverage, 11375,
     /* 382912 */     GIR_EraseRootFromParent_Done,
     /* 382913 */   // Label 7446: @382913
     /* 382913 */   GIM_Try, /*On fail goto*//*Label 7447*/ GIMT_Encode4(383024), // Rule ID 11316 //
     /* 382918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 382925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 382929 */     // (vector_insert:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), GPR64:{ *:[i64] }:$src)
     /* 382929 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 382932 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 382936 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382941 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 382945 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 382947 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 382950 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 382954 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382959 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 382962 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 382965 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382967 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382970 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 382974 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382979 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 382982 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382984 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382987 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 382991 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382996 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382999 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 383002 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 383005 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 383008 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_D),
     /* 383013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383015 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 383017 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383020 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 383022 */     GIR_RootConstrainSelectedInstOperands,
     /* 383023 */     // GIR_Coverage, 11316,
     /* 383023 */     GIR_EraseRootFromParent_Done,
     /* 383024 */   // Label 7447: @383024
     /* 383024 */   GIM_Try, /*On fail goto*//*Label 7448*/ GIMT_Encode4(383135), // Rule ID 11322 //
     /* 383029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 383036 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 383040 */     // (vector_insert:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$vec, FPR64:{ *:[f64] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_D:{ *:[nxv2f64] } ZPR:{ *:[nxv2f64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } ?:{ *:[i64] }:$index)), ?:{ *:[f64] }:$src)
     /* 383040 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 383043 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 383047 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383052 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 383056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 383058 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 383061 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 383065 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383070 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 383073 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 383076 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 383078 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383081 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 383085 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383090 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 383093 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383095 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383098 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 383102 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383107 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383110 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 383113 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 383116 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 383119 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_D),
     /* 383124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383126 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 383128 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383131 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 383133 */     GIR_RootConstrainSelectedInstOperands,
     /* 383134 */     // GIR_Coverage, 11322,
     /* 383134 */     GIR_EraseRootFromParent_Done,
     /* 383135 */   // Label 7448: @383135
     /* 383135 */   GIM_Reject,
     /* 383136 */ // Label 7429: @383136
     /* 383136 */ GIM_Reject,
     /* 383137 */ // Label 7192: @383137
     /* 383137 */ GIM_Try, /*On fail goto*//*Label 7449*/ GIMT_Encode4(383288), // Rule ID 11318 //
     /* 383142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383145 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 383148 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 383151 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 383154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383158 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 383162 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 383166 */   // (vector_insert:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv4f16] } ZPR:{ *:[nxv4f16] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
     /* 383166 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 383169 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 383173 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383178 */   GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 383184 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 383189 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 383194 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 383197 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 383201 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383206 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 383209 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 383211 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 383214 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 383218 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383223 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 383226 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 383229 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 383231 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383234 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 383238 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383243 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 383246 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383248 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383251 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 383255 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383260 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383263 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 383266 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 383269 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 383272 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 383277 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383279 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 383281 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383284 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 383286 */   GIR_RootConstrainSelectedInstOperands,
     /* 383287 */   // GIR_Coverage, 11318,
     /* 383287 */   GIR_EraseRootFromParent_Done,
     /* 383288 */ // Label 7449: @383288
     /* 383288 */ GIM_Reject,
     /* 383289 */ // Label 7193: @383289
     /* 383289 */ GIM_Try, /*On fail goto*//*Label 7450*/ GIMT_Encode4(385320),
     /* 383294 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 383297 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 383300 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 383303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383307 */   GIM_Try, /*On fail goto*//*Label 7451*/ GIMT_Encode4(383416), // Rule ID 4353 //
     /* 383312 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383316 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 383322 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 383324 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383328 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383332 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383335 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383339 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383343 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383347 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383349 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 383356 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383356 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383359 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 383363 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383383 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383389 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383399 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383405 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383410 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383415 */     // GIR_Coverage, 4353,
     /* 383415 */     GIR_EraseRootFromParent_Done,
     /* 383416 */   // Label 7451: @383416
     /* 383416 */   GIM_Try, /*On fail goto*//*Label 7452*/ GIMT_Encode4(383525), // Rule ID 4354 //
     /* 383421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383425 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 383431 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 383433 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383437 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383441 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383444 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383448 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383452 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383456 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383458 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 383465 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383465 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383468 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 383472 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383492 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383498 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383514 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383519 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383524 */     // GIR_Coverage, 4354,
     /* 383524 */     GIR_EraseRootFromParent_Done,
     /* 383525 */   // Label 7452: @383525
     /* 383525 */   GIM_Try, /*On fail goto*//*Label 7453*/ GIMT_Encode4(383634), // Rule ID 4461 //
     /* 383530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383534 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 383540 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 383542 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383546 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383550 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383553 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383557 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383561 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383565 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383567 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 383574 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383574 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383577 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 383581 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383601 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383607 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383617 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383633 */     // GIR_Coverage, 4461,
     /* 383633 */     GIR_EraseRootFromParent_Done,
     /* 383634 */   // Label 7453: @383634
     /* 383634 */   GIM_Try, /*On fail goto*//*Label 7454*/ GIMT_Encode4(383743), // Rule ID 4462 //
     /* 383639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383643 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 383649 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 383651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383659 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383662 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383666 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383670 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383674 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383676 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 383683 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383683 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383686 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 383690 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383710 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383716 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383726 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383732 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383737 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383742 */     // GIR_Coverage, 4462,
     /* 383742 */     GIR_EraseRootFromParent_Done,
     /* 383743 */   // Label 7454: @383743
     /* 383743 */   GIM_Try, /*On fail goto*//*Label 7455*/ GIMT_Encode4(383848), // Rule ID 4359 //
     /* 383748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 383756 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383760 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383764 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383767 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383771 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383775 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383779 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383781 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 383788 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383788 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383791 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 383795 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383815 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383821 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383837 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383842 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383847 */     // GIR_Coverage, 4359,
     /* 383847 */     GIR_EraseRootFromParent_Done,
     /* 383848 */   // Label 7455: @383848
     /* 383848 */   GIM_Try, /*On fail goto*//*Label 7456*/ GIMT_Encode4(383953), // Rule ID 4361 //
     /* 383853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 383861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383869 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383872 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383876 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383880 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383884 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383886 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 383893 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383893 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 383896 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 383900 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 383910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 383915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 383920 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 383926 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 383931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 383933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 383936 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 383942 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383947 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 383952 */     // GIR_Coverage, 4361,
     /* 383952 */     GIR_EraseRootFromParent_Done,
     /* 383953 */   // Label 7456: @383953
     /* 383953 */   GIM_Try, /*On fail goto*//*Label 7457*/ GIMT_Encode4(384058), // Rule ID 4467 //
     /* 383958 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 383962 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 383966 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 383970 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 383974 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 383977 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 383981 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 383985 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 383989 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 383991 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 383998 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 383998 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384001 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 384005 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 384020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 384025 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384031 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384047 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384052 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384057 */     // GIR_Coverage, 4467,
     /* 384057 */     GIR_EraseRootFromParent_Done,
     /* 384058 */   // Label 7457: @384058
     /* 384058 */   GIM_Try, /*On fail goto*//*Label 7458*/ GIMT_Encode4(384163), // Rule ID 4469 //
     /* 384063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384067 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384071 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384075 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384079 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384082 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384086 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384090 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384094 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384096 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 384103 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 384103 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384106 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 384110 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 384125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 384130 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384136 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384162 */     // GIR_Coverage, 4469,
     /* 384162 */     GIR_EraseRootFromParent_Done,
     /* 384163 */   // Label 7458: @384163
     /* 384163 */   GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(384267), // Rule ID 4351 //
     /* 384168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384172 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 384178 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 384180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384188 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384191 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384195 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384199 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384203 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384205 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 384212 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 384212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 384219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384234 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384240 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384250 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384256 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384266 */     // GIR_Coverage, 4351,
     /* 384266 */     GIR_EraseRootFromParent_Done,
     /* 384267 */   // Label 7459: @384267
     /* 384267 */   GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(384371), // Rule ID 4352 //
     /* 384272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384276 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 384282 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 384284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384292 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384295 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384299 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384303 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384307 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384309 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 384316 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 384316 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384319 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 384323 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384338 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384344 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384354 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384360 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384365 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384370 */     // GIR_Coverage, 4352,
     /* 384370 */     GIR_EraseRootFromParent_Done,
     /* 384371 */   // Label 7460: @384371
     /* 384371 */   GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(384475), // Rule ID 4459 //
     /* 384376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384380 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 384386 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 384388 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384392 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384396 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384399 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384403 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384407 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384411 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384413 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 384420 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 384420 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384423 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 384427 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384442 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384448 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384458 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384464 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384469 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384474 */     // GIR_Coverage, 4459,
     /* 384474 */     GIR_EraseRootFromParent_Done,
     /* 384475 */   // Label 7461: @384475
     /* 384475 */   GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(384579), // Rule ID 4460 //
     /* 384480 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384484 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 384490 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 384492 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384496 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384500 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384503 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384507 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384511 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384515 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384517 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 384524 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 384524 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384527 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 384531 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384546 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384552 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384562 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384568 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384573 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384578 */     // GIR_Coverage, 4460,
     /* 384578 */     GIR_EraseRootFromParent_Done,
     /* 384579 */   // Label 7462: @384579
     /* 384579 */   GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(384679), // Rule ID 4355 //
     /* 384584 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384588 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384592 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384596 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384600 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384603 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384607 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384611 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384615 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384617 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 384624 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 384624 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384627 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 384631 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384646 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384652 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384662 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384668 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384673 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384678 */     // GIR_Coverage, 4355,
     /* 384678 */     GIR_EraseRootFromParent_Done,
     /* 384679 */   // Label 7463: @384679
     /* 384679 */   GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(384779), // Rule ID 4357 //
     /* 384684 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384688 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384700 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384703 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384707 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384711 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384715 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384717 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 384724 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 384724 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384727 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 384731 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384746 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384752 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384762 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384768 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384773 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384778 */     // GIR_Coverage, 4357,
     /* 384778 */     GIR_EraseRootFromParent_Done,
     /* 384779 */   // Label 7464: @384779
     /* 384779 */   GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(384879), // Rule ID 4463 //
     /* 384784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384800 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384803 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384807 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384811 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384815 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384817 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 384824 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 384824 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384827 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 384831 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384846 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384852 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384862 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384868 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384873 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384878 */     // GIR_Coverage, 4463,
     /* 384878 */     GIR_EraseRootFromParent_Done,
     /* 384879 */   // Label 7465: @384879
     /* 384879 */   GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(384979), // Rule ID 4465 //
     /* 384884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384892 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384896 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 384900 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 384903 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 384907 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 384911 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384915 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 384917 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 384924 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 384924 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 384927 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 384931 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 384941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 384946 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 384952 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 384962 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 384968 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384973 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 384978 */     // GIR_Coverage, 4465,
     /* 384978 */     GIR_EraseRootFromParent_Done,
     /* 384979 */   // Label 7466: @384979
     /* 384979 */   GIM_Try, /*On fail goto*//*Label 7467*/ GIMT_Encode4(385043), // Rule ID 11373 //
     /* 384984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 384987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384995 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 384999 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 385003 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 385007 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 385011 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 385015 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 385019 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 385023 */     // MIs[3] Operand 1
     /* 385023 */     // No operand predicates
     /* 385023 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385027 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 385029 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$Idx)
     /* 385029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 385032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 385034 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 385038 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 385041 */     GIR_RootConstrainSelectedInstOperands,
     /* 385042 */     // GIR_Coverage, 11373,
     /* 385042 */     GIR_EraseRootFromParent_Done,
     /* 385043 */   // Label 7467: @385043
     /* 385043 */   GIM_Try, /*On fail goto*//*Label 7468*/ GIMT_Encode4(385181), // Rule ID 11315 //
     /* 385048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 385051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 385055 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 385059 */     // (vector_insert:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 385059 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 385062 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 385066 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385071 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 385077 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 385082 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 385087 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 385090 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 385094 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385099 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 385102 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 385104 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 385107 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 385111 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385116 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 385119 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 385122 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 385124 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 385127 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 385131 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385136 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 385139 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 385141 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 385144 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 385148 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385153 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 385156 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 385159 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 385162 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 385165 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_S),
     /* 385170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 385172 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 385174 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385177 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 385179 */     GIR_RootConstrainSelectedInstOperands,
     /* 385180 */     // GIR_Coverage, 11315,
     /* 385180 */     GIR_EraseRootFromParent_Done,
     /* 385181 */   // Label 7468: @385181
     /* 385181 */   GIM_Try, /*On fail goto*//*Label 7469*/ GIMT_Encode4(385319), // Rule ID 11321 //
     /* 385186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 385189 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385193 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 385197 */     // (vector_insert:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_S:{ *:[nxv4f32] } ZPR:{ *:[nxv4f32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f32] }:$src)
     /* 385197 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 385200 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 385204 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385209 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 385215 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 385220 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 385225 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 385228 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 385232 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385237 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 385240 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 385242 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 385245 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 385249 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385254 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 385257 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 385260 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 385262 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 385265 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 385269 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385274 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 385277 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 385279 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 385282 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 385286 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385291 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 385294 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 385297 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 385300 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 385303 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
     /* 385308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 385310 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 385312 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385315 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 385317 */     GIR_RootConstrainSelectedInstOperands,
     /* 385318 */     // GIR_Coverage, 11321,
     /* 385318 */     GIR_EraseRootFromParent_Done,
     /* 385319 */   // Label 7469: @385319
     /* 385319 */   GIM_Reject,
     /* 385320 */ // Label 7450: @385320
     /* 385320 */ GIM_Reject,
     /* 385321 */ // Label 7194: @385321
     /* 385321 */ GIM_Try, /*On fail goto*//*Label 7470*/ GIMT_Encode4(387588),
     /* 385326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 385329 */   GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(385455), // Rule ID 4317 //
     /* 385334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 385337 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385348 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385354 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385356 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385360 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385364 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385367 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385371 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 385378 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385382 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385386 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385388 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 385395 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 385395 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 385398 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 385402 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385422 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385428 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385438 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 385444 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385449 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 385454 */     // GIR_Coverage, 4317,
     /* 385454 */     GIR_EraseRootFromParent_Done,
     /* 385455 */   // Label 7471: @385455
     /* 385455 */   GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(385581), // Rule ID 4318 //
     /* 385460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 385463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385474 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385480 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385482 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385486 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385490 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385493 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385497 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 385504 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385508 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385512 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385514 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 385521 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 385521 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 385524 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 385528 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385548 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385554 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385564 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 385570 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385575 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 385580 */     // GIR_Coverage, 4318,
     /* 385580 */     GIR_EraseRootFromParent_Done,
     /* 385581 */   // Label 7472: @385581
     /* 385581 */   GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(385700), // Rule ID 4425 //
     /* 385586 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 385589 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385600 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385606 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385608 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385612 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385616 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385619 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385623 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385627 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385631 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385633 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 385640 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 385640 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 385643 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 385647 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385667 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385673 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385683 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 385689 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385694 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 385699 */     // GIR_Coverage, 4425,
     /* 385699 */     GIR_EraseRootFromParent_Done,
     /* 385700 */   // Label 7473: @385700
     /* 385700 */   GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(385819), // Rule ID 4426 //
     /* 385705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 385708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385719 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385725 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385727 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385731 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385735 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385738 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385742 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385746 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385750 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385752 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 385759 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 385759 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 385762 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 385766 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385786 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385792 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385802 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 385808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385813 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 385818 */     // GIR_Coverage, 4426,
     /* 385818 */     GIR_EraseRootFromParent_Done,
     /* 385819 */   // Label 7474: @385819
     /* 385819 */   GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(385941), // Rule ID 4323 //
     /* 385824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 385827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385850 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385853 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385857 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 385864 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385868 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385872 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385874 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 385881 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 385881 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 385884 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 385888 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385908 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385914 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385924 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 385930 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385935 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 385940 */     // GIR_Coverage, 4323,
     /* 385940 */     GIR_EraseRootFromParent_Done,
     /* 385941 */   // Label 7475: @385941
     /* 385941 */   GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(386063), // Rule ID 4325 //
     /* 385946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 385949 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 385952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 385956 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385960 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385964 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385968 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385972 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385975 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385979 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 385986 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385990 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385994 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385996 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 386003 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 386003 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386006 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 386010 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 386025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 386030 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386036 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386046 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386052 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386057 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386062 */     // GIR_Coverage, 4325,
     /* 386062 */     GIR_EraseRootFromParent_Done,
     /* 386063 */   // Label 7476: @386063
     /* 386063 */   GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(386178), // Rule ID 4431 //
     /* 386068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 386071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386086 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386090 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386094 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386097 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386101 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386105 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386109 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386111 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 386118 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 386118 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386121 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 386125 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 386140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 386145 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386151 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386161 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386167 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386172 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386177 */     // GIR_Coverage, 4431,
     /* 386177 */     GIR_EraseRootFromParent_Done,
     /* 386178 */   // Label 7477: @386178
     /* 386178 */   GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(386293), // Rule ID 4433 //
     /* 386183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 386186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386201 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386205 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386209 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386212 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386216 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386220 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386224 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386226 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 386233 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 386233 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386236 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 386240 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 386255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 386260 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386266 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386276 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386282 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386287 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386292 */     // GIR_Coverage, 4433,
     /* 386292 */     GIR_EraseRootFromParent_Done,
     /* 386293 */   // Label 7478: @386293
     /* 386293 */   GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(386414), // Rule ID 4315 //
     /* 386298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 386301 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386304 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386312 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386318 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386320 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386324 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386328 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386331 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386335 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 386342 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386346 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386352 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 386359 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 386359 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386362 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 386366 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386381 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386387 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386397 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386403 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386408 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386413 */     // GIR_Coverage, 4315,
     /* 386413 */     GIR_EraseRootFromParent_Done,
     /* 386414 */   // Label 7479: @386414
     /* 386414 */   GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(386535), // Rule ID 4316 //
     /* 386419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 386422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386429 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386433 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386439 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386441 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386445 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386449 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386452 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386456 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 386463 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386467 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386471 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386473 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 386480 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 386480 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386483 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 386487 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386502 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386508 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386518 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386524 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386529 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386534 */     // GIR_Coverage, 4316,
     /* 386534 */     GIR_EraseRootFromParent_Done,
     /* 386535 */   // Label 7480: @386535
     /* 386535 */   GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(386649), // Rule ID 4423 //
     /* 386540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 386543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386554 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386560 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386570 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386573 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386577 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386581 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386587 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 386594 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 386594 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386597 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 386601 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386616 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386622 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386632 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386638 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386648 */     // GIR_Coverage, 4423,
     /* 386648 */     GIR_EraseRootFromParent_Done,
     /* 386649 */   // Label 7481: @386649
     /* 386649 */   GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(386763), // Rule ID 4424 //
     /* 386654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 386657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386668 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386674 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386684 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386687 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386691 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386695 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386699 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386701 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 386708 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 386708 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386711 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 386715 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386730 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386736 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386746 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386752 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386757 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386762 */     // GIR_Coverage, 4424,
     /* 386762 */     GIR_EraseRootFromParent_Done,
     /* 386763 */   // Label 7482: @386763
     /* 386763 */   GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(386880), // Rule ID 4319 //
     /* 386768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 386771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386778 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386782 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386794 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386797 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386801 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 386808 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386812 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386816 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386818 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 386825 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 386825 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386828 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 386832 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386847 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386853 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386863 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386869 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386874 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386879 */     // GIR_Coverage, 4319,
     /* 386879 */     GIR_EraseRootFromParent_Done,
     /* 386880 */   // Label 7483: @386880
     /* 386880 */   GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(386997), // Rule ID 4321 //
     /* 386885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 386888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 386891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386895 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386899 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386903 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386907 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386911 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386914 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386918 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 386925 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386929 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386933 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386935 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 386942 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 386942 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 386945 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 386949 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386964 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386970 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386980 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 386986 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 386991 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 386996 */     // GIR_Coverage, 4321,
     /* 386996 */     GIR_EraseRootFromParent_Done,
     /* 386997 */   // Label 7484: @386997
     /* 386997 */   GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(387107), // Rule ID 4427 //
     /* 387002 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 387005 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387012 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387016 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 387020 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387024 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387028 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387031 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 387035 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 387039 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387043 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387045 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 387052 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 387052 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 387055 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 387059 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 387069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 387074 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387080 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 387090 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 387096 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387101 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 387106 */     // GIR_Coverage, 4427,
     /* 387106 */     GIR_EraseRootFromParent_Done,
     /* 387107 */   // Label 7485: @387107
     /* 387107 */   GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(387217), // Rule ID 4429 //
     /* 387112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 387115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 387130 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387134 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387138 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387141 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 387145 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 387149 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387153 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387155 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 387162 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 387162 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 387165 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 387169 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 387179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 387184 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387190 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 387200 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 387206 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387211 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 387216 */     // GIR_Coverage, 4429,
     /* 387216 */     GIR_EraseRootFromParent_Done,
     /* 387217 */   // Label 7486: @387217
     /* 387217 */   GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(387291), // Rule ID 11371 //
     /* 387222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 387225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 387228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 387243 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387247 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 387251 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 387255 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 387259 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 387263 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387267 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 387271 */     // MIs[3] Operand 1
     /* 387271 */     // No operand predicates
     /* 387271 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387275 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 387277 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$Idx)
     /* 387277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 387280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 387282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 387286 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 387289 */     GIR_RootConstrainSelectedInstOperands,
     /* 387290 */     // GIR_Coverage, 11371,
     /* 387290 */     GIR_EraseRootFromParent_Done,
     /* 387291 */   // Label 7487: @387291
     /* 387291 */   GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(387439), // Rule ID 11314 //
     /* 387296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 387299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 387302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 387313 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 387317 */     // (vector_insert:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 387317 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 387320 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387324 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387329 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 387335 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 387340 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 387345 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 387348 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 387352 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387357 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 387360 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 387362 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 387365 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
     /* 387369 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387374 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 387377 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 387380 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 387382 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 387385 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 387389 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387394 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 387397 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 387399 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 387402 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
     /* 387406 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387411 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387414 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 387417 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 387420 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 387423 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_H),
     /* 387428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 387430 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 387432 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 387437 */     GIR_RootConstrainSelectedInstOperands,
     /* 387438 */     // GIR_Coverage, 11314,
     /* 387438 */     GIR_EraseRootFromParent_Done,
     /* 387439 */   // Label 7488: @387439
     /* 387439 */   GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(387587), // Rule ID 11319 //
     /* 387444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 387447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 387450 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387457 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 387461 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 387465 */     // (vector_insert:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv8f16] } ZPR:{ *:[nxv8f16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
     /* 387465 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 387468 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387472 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387477 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 387483 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 387488 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 387493 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 387496 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 387500 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387505 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 387508 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 387510 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 387513 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
     /* 387517 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387522 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 387525 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 387528 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 387530 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 387533 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 387537 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387542 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 387545 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 387547 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 387550 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
     /* 387554 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387559 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387562 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 387565 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 387568 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 387571 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 387576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 387578 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 387580 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387583 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 387585 */     GIR_RootConstrainSelectedInstOperands,
     /* 387586 */     // GIR_Coverage, 11319,
     /* 387586 */     GIR_EraseRootFromParent_Done,
     /* 387587 */   // Label 7489: @387587
     /* 387587 */   GIM_Reject,
     /* 387588 */ // Label 7470: @387588
     /* 387588 */ GIM_Reject,
     /* 387589 */ // Label 7195: @387589
     /* 387589 */ GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(389708),
     /* 387594 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 387597 */   GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(387716), // Rule ID 4245 //
     /* 387602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 387605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387612 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387616 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 387622 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 387624 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387628 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387632 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387635 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 387639 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 387643 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387647 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387649 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 387656 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 387656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 387659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 387663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 387673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 387678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 387683 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387689 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 387699 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 387705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387710 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 387715 */     // GIR_Coverage, 4245,
     /* 387715 */     GIR_EraseRootFromParent_Done,
     /* 387716 */   // Label 7491: @387716
     /* 387716 */   GIM_Try, /*On fail goto*//*Label 7492*/ GIMT_Encode4(387835), // Rule ID 4246 //
     /* 387721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 387724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387731 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387735 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 387741 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 387743 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387747 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387751 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387754 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 387758 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 387762 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387766 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387768 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 387775 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 387775 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 387778 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 387782 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 387792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 387797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 387802 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 387818 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 387824 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387829 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 387834 */     // GIR_Coverage, 4246,
     /* 387834 */     GIR_EraseRootFromParent_Done,
     /* 387835 */   // Label 7492: @387835
     /* 387835 */   GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(387961), // Rule ID 4281 //
     /* 387840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 387843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387854 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 387860 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 387862 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387866 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387870 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387873 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 387877 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 387884 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 387888 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387892 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387894 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 387901 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 387901 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 387904 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 387908 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 387918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 387923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 387928 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387934 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 387944 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 387950 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387955 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 387960 */     // GIR_Coverage, 4281,
     /* 387960 */     GIR_EraseRootFromParent_Done,
     /* 387961 */   // Label 7493: @387961
     /* 387961 */   GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(388087), // Rule ID 4282 //
     /* 387966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 387969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 387972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 387976 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387980 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 387986 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 387988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 387992 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387996 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387999 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388003 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 388010 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388014 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388018 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388020 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 388027 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 388027 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388030 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 388034 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388054 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388060 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388070 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388076 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388081 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388086 */     // GIR_Coverage, 4282,
     /* 388086 */     GIR_EraseRootFromParent_Done,
     /* 388087 */   // Label 7494: @388087
     /* 388087 */   GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(388202), // Rule ID 4251 //
     /* 388092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 388095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388102 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 388110 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388114 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388118 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388121 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388125 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388129 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388135 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 388142 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 388142 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388145 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 388149 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388169 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388175 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388185 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388191 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388196 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388201 */     // GIR_Coverage, 4251,
     /* 388201 */     GIR_EraseRootFromParent_Done,
     /* 388202 */   // Label 7495: @388202
     /* 388202 */   GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(388317), // Rule ID 4253 //
     /* 388207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 388210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388217 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388221 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 388225 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388229 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388233 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388236 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388240 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388244 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388248 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388250 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 388257 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 388257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 388264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388284 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388290 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388300 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388306 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388311 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388316 */     // GIR_Coverage, 4253,
     /* 388316 */     GIR_EraseRootFromParent_Done,
     /* 388317 */   // Label 7496: @388317
     /* 388317 */   GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(388439), // Rule ID 4287 //
     /* 388322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 388325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 388340 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388344 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388348 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388351 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388355 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 388362 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388366 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388370 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388372 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 388379 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 388379 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388382 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 388386 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388406 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388412 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388422 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388428 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388433 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388438 */     // GIR_Coverage, 4287,
     /* 388438 */     GIR_EraseRootFromParent_Done,
     /* 388439 */   // Label 7497: @388439
     /* 388439 */   GIM_Try, /*On fail goto*//*Label 7498*/ GIMT_Encode4(388561), // Rule ID 4289 //
     /* 388444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 388447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 388462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388470 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388473 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388477 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 388484 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388488 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388492 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388494 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 388501 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 388501 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388504 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 388508 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388528 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388534 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388544 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388550 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388555 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388560 */     // GIR_Coverage, 4289,
     /* 388560 */     GIR_EraseRootFromParent_Done,
     /* 388561 */   // Label 7498: @388561
     /* 388561 */   GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(388675), // Rule ID 4243 //
     /* 388566 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 388569 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388576 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388580 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388586 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388596 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388599 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388603 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388607 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388613 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 388620 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 388620 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388623 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 388627 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 388642 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388648 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388658 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388664 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388669 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388674 */     // GIR_Coverage, 4243,
     /* 388674 */     GIR_EraseRootFromParent_Done,
     /* 388675 */   // Label 7499: @388675
     /* 388675 */   GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(388789), // Rule ID 4244 //
     /* 388680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 388683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388694 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388700 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388710 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388713 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388717 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388721 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388725 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388727 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 388734 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 388734 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388737 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 388741 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 388756 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388762 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388772 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388778 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388783 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388788 */     // GIR_Coverage, 4244,
     /* 388788 */     GIR_EraseRootFromParent_Done,
     /* 388789 */   // Label 7500: @388789
     /* 388789 */   GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(388910), // Rule ID 4279 //
     /* 388794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 388797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388808 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388814 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388824 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388827 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388831 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 388838 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388842 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388846 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388848 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 388855 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 388855 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388858 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 388862 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 388877 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388883 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388893 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 388899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388904 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 388909 */     // GIR_Coverage, 4279,
     /* 388909 */     GIR_EraseRootFromParent_Done,
     /* 388910 */   // Label 7501: @388910
     /* 388910 */   GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(389031), // Rule ID 4280 //
     /* 388915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 388918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 388925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388929 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388935 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388945 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388948 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388952 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 388959 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388963 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388967 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388969 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 388976 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 388976 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 388979 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 388983 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 388998 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389004 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389014 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 389020 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389025 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 389030 */     // GIR_Coverage, 4280,
     /* 389030 */     GIR_EraseRootFromParent_Done,
     /* 389031 */   // Label 7502: @389031
     /* 389031 */   GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(389141), // Rule ID 4247 //
     /* 389036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 389039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389054 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389058 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389062 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389065 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389069 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389073 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389077 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389079 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 389086 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 389086 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 389089 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 389093 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389108 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389114 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389124 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 389130 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389135 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 389140 */     // GIR_Coverage, 4247,
     /* 389140 */     GIR_EraseRootFromParent_Done,
     /* 389141 */   // Label 7503: @389141
     /* 389141 */   GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(389251), // Rule ID 4249 //
     /* 389146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 389149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389164 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389168 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389172 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389175 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389179 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389183 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389187 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389189 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 389196 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 389196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 389199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 389203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389218 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389224 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389234 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 389240 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389245 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 389250 */     // GIR_Coverage, 4249,
     /* 389250 */     GIR_EraseRootFromParent_Done,
     /* 389251 */   // Label 7504: @389251
     /* 389251 */   GIM_Try, /*On fail goto*//*Label 7505*/ GIMT_Encode4(389368), // Rule ID 4283 //
     /* 389256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 389259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389274 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389278 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389282 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389285 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389289 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 389296 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389300 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389304 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389306 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 389313 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 389313 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 389316 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 389320 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389335 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389341 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389351 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 389357 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389362 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 389367 */     // GIR_Coverage, 4283,
     /* 389367 */     GIR_EraseRootFromParent_Done,
     /* 389368 */   // Label 7505: @389368
     /* 389368 */   GIM_Try, /*On fail goto*//*Label 7506*/ GIMT_Encode4(389485), // Rule ID 4285 //
     /* 389373 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 389376 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389391 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389395 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389399 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389402 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389406 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 389413 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389417 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389421 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389423 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 389430 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 389430 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 389433 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 389437 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389452 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389468 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 389474 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389479 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 389484 */     // GIR_Coverage, 4285,
     /* 389484 */     GIR_EraseRootFromParent_Done,
     /* 389485 */   // Label 7506: @389485
     /* 389485 */   GIM_Try, /*On fail goto*//*Label 7507*/ GIMT_Encode4(389559), // Rule ID 11369 //
     /* 389490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 389496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389507 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389511 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389515 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 389519 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 389523 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 389527 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 389531 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 389535 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 389539 */     // MIs[3] Operand 1
     /* 389539 */     // No operand predicates
     /* 389539 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389543 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 389545 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$Idx)
     /* 389545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 389548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 389550 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 389554 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 389557 */     GIR_RootConstrainSelectedInstOperands,
     /* 389558 */     // GIR_Coverage, 11369,
     /* 389558 */     GIR_EraseRootFromParent_Done,
     /* 389559 */   // Label 7507: @389559
     /* 389559 */   GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(389707), // Rule ID 11313 //
     /* 389564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389567 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 389570 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 389573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 389581 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 389585 */     // (vector_insert:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (CMPEQ_PPzZZ_B:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_B:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_B:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 389585 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 389588 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 389592 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389597 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 389603 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 389608 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 389613 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 389616 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_B),
     /* 389620 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389625 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 389628 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 389630 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 389633 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_B),
     /* 389637 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389642 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 389645 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 389648 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 389650 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 389653 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 389657 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389662 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 389665 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 389667 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 389670 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_B),
     /* 389674 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389679 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 389682 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 389685 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 389688 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 389691 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_B),
     /* 389696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 389698 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 389700 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389703 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 389705 */     GIR_RootConstrainSelectedInstOperands,
     /* 389706 */     // GIR_Coverage, 11313,
     /* 389706 */     GIR_EraseRootFromParent_Done,
     /* 389707 */   // Label 7508: @389707
     /* 389707 */   GIM_Reject,
     /* 389708 */ // Label 7490: @389708
     /* 389708 */ GIM_Reject,
     /* 389709 */ // Label 7196: @389709
     /* 389709 */ GIM_Reject,
     /* 389710 */ // Label 92: @389710
     /* 389710 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7512*/ GIMT_Encode4(392627),
     /* 389721 */ /*GILLT_s16*//*Label 7509*/ GIMT_Encode4(389733),
     /* 389725 */ /*GILLT_s32*//*Label 7510*/ GIMT_Encode4(390367),
     /* 389729 */ /*GILLT_s64*//*Label 7511*/ GIMT_Encode4(391960),
     /* 389733 */ // Label 7509: @389733
     /* 389733 */ GIM_Try, /*On fail goto*//*Label 7513*/ GIMT_Encode4(389777), // Rule ID 11362 //
     /* 389738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389741 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 389744 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389751 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 389755 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$Zs, hsub:{ *:[i32] })
     /* 389755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 389758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389760 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 389766 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389771 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389776 */   // GIR_Coverage, 11362,
     /* 389776 */   GIR_EraseRootFromParent_Done,
     /* 389777 */ // Label 7513: @389777
     /* 389777 */ GIM_Try, /*On fail goto*//*Label 7514*/ GIMT_Encode4(389821), // Rule ID 11363 //
     /* 389782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 389788 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389791 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389795 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 389799 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$Zs, hsub:{ *:[i32] })
     /* 389799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 389802 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389804 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 389810 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389815 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389820 */   // GIR_Coverage, 11363,
     /* 389820 */   GIR_EraseRootFromParent_Done,
     /* 389821 */ // Label 7514: @389821
     /* 389821 */ GIM_Try, /*On fail goto*//*Label 7515*/ GIMT_Encode4(389865), // Rule ID 11364 //
     /* 389826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389829 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 389832 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389839 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 389843 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$Zs, hsub:{ *:[i32] })
     /* 389843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 389846 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389848 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 389854 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389859 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 389864 */   // GIR_Coverage, 11364,
     /* 389864 */   GIR_EraseRootFromParent_Done,
     /* 389865 */ // Label 7515: @389865
     /* 389865 */ GIM_Try, /*On fail goto*//*Label 7516*/ GIMT_Encode4(389910), // Rule ID 5851 //
     /* 389870 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 389873 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389880 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389884 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 389888 */   // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] })
     /* 389888 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 389891 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389893 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 389899 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389904 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389909 */   // GIR_Coverage, 5851,
     /* 389909 */   GIR_EraseRootFromParent_Done,
     /* 389910 */ // Label 7516: @389910
     /* 389910 */ GIM_Try, /*On fail goto*//*Label 7517*/ GIMT_Encode4(389955), // Rule ID 5854 //
     /* 389915 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 389918 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389925 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389929 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 389933 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 389937 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 389941 */   // MIs[1] Operand 1
     /* 389941 */   // No operand predicates
     /* 389941 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 389943 */   // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 389943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 389946 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389948 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 389950 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 389953 */   GIR_RootConstrainSelectedInstOperands,
     /* 389954 */   // GIR_Coverage, 5854,
     /* 389954 */   GIR_EraseRootFromParent_Done,
     /* 389955 */ // Label 7517: @389955
     /* 389955 */ GIM_Try, /*On fail goto*//*Label 7518*/ GIMT_Encode4(390031), // Rule ID 11337 //
     /* 389960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 389963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 389966 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 389969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 389973 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 389977 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 389981 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 389985 */   // MIs[1] Operand 1
     /* 389985 */   // No operand predicates
     /* 389985 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 389987 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), hsub:{ *:[i32] })
     /* 389987 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 389990 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 389994 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389999 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 390003 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 390006 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390013 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 390020 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390025 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390030 */   // GIR_Coverage, 11337,
     /* 390030 */   GIR_EraseRootFromParent_Done,
     /* 390031 */ // Label 7518: @390031
     /* 390031 */ GIM_Try, /*On fail goto*//*Label 7519*/ GIMT_Encode4(390107), // Rule ID 11338 //
     /* 390036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390039 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 390042 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390045 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390049 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390053 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390057 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 390061 */   // MIs[1] Operand 1
     /* 390061 */   // No operand predicates
     /* 390061 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390063 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), hsub:{ *:[i32] })
     /* 390063 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 390066 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 390070 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390075 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 390079 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 390082 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390087 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390089 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 390096 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390101 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390106 */   // GIR_Coverage, 11338,
     /* 390106 */   GIR_EraseRootFromParent_Done,
     /* 390107 */ // Label 7519: @390107
     /* 390107 */ GIM_Try, /*On fail goto*//*Label 7520*/ GIMT_Encode4(390183), // Rule ID 11339 //
     /* 390112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 390118 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390125 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390129 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390133 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 390137 */   // MIs[1] Operand 1
     /* 390137 */   // No operand predicates
     /* 390137 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390139 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), hsub:{ *:[i32] })
     /* 390139 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 390142 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 390146 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390151 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 390155 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 390158 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390163 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390165 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 390172 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390177 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390182 */   // GIR_Coverage, 11339,
     /* 390182 */   GIR_EraseRootFromParent_Done,
     /* 390183 */ // Label 7520: @390183
     /* 390183 */ GIM_Try, /*On fail goto*//*Label 7521*/ GIMT_Encode4(390244), // Rule ID 11327 //
     /* 390188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390191 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 390194 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390201 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 390205 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8f16] }:$vec)
     /* 390205 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 390208 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 390212 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390217 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 390223 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 390227 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 390230 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 390235 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 390237 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390240 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 390242 */   GIR_RootConstrainSelectedInstOperands,
     /* 390243 */   // GIR_Coverage, 11327,
     /* 390243 */   GIR_EraseRootFromParent_Done,
     /* 390244 */ // Label 7521: @390244
     /* 390244 */ GIM_Try, /*On fail goto*//*Label 7522*/ GIMT_Encode4(390305), // Rule ID 11328 //
     /* 390249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390252 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 390255 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390262 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 390266 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f16] }:$vec)
     /* 390266 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 390269 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 390273 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390278 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 390284 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 390288 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 390291 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 390296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 390298 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390301 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 390303 */   GIR_RootConstrainSelectedInstOperands,
     /* 390304 */   // GIR_Coverage, 11328,
     /* 390304 */   GIR_EraseRootFromParent_Done,
     /* 390305 */ // Label 7522: @390305
     /* 390305 */ GIM_Try, /*On fail goto*//*Label 7523*/ GIMT_Encode4(390366), // Rule ID 11329 //
     /* 390310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 390316 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 390323 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 390327 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f16] }:$vec)
     /* 390327 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 390330 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 390334 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390339 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 390345 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 390349 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 390352 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 390357 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 390359 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390362 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 390364 */   GIR_RootConstrainSelectedInstOperands,
     /* 390365 */   // GIR_Coverage, 11329,
     /* 390365 */   GIR_EraseRootFromParent_Done,
     /* 390366 */ // Label 7523: @390366
     /* 390366 */ GIM_Reject,
     /* 390367 */ // Label 7510: @390367
     /* 390367 */ GIM_Try, /*On fail goto*//*Label 7524*/ GIMT_Encode4(390412), // Rule ID 7038 //
     /* 390372 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 390375 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390382 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390386 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390390 */   // (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$V, ssub:{ *:[i32] })
     /* 390390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390393 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390395 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // V
     /* 390401 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390406 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390411 */   // GIR_Coverage, 7038,
     /* 390411 */   GIR_EraseRootFromParent_Done,
     /* 390412 */ // Label 7524: @390412
     /* 390412 */ GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(390457), // Rule ID 7039 //
     /* 390417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 390420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390431 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390435 */   // (extractelt:{ *:[i32] } V64:{ *:[v2i32] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$V, ssub:{ *:[i32] })
     /* 390435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390438 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390440 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // V
     /* 390446 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390451 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390456 */   // GIR_Coverage, 7039,
     /* 390456 */   GIR_EraseRootFromParent_Done,
     /* 390457 */ // Label 7525: @390457
     /* 390457 */ GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(390501), // Rule ID 11358 //
     /* 390462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 390468 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390475 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390479 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$Zs, ssub:{ *:[i32] })
     /* 390479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390482 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390484 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 390490 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390495 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390500 */   // GIR_Coverage, 11358,
     /* 390500 */   GIR_EraseRootFromParent_Done,
     /* 390501 */ // Label 7526: @390501
     /* 390501 */ GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(390545), // Rule ID 11359 //
     /* 390506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390509 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 390512 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390519 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390523 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$Zs, ssub:{ *:[i32] })
     /* 390523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390528 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 390534 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390539 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390544 */   // GIR_Coverage, 11359,
     /* 390544 */   GIR_EraseRootFromParent_Done,
     /* 390545 */ // Label 7527: @390545
     /* 390545 */ GIM_Try, /*On fail goto*//*Label 7528*/ GIMT_Encode4(390589), // Rule ID 11360 //
     /* 390550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 390556 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390563 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390567 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$Zs, ssub:{ *:[i32] })
     /* 390567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390572 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 390578 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390583 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390588 */   // GIR_Coverage, 11360,
     /* 390588 */   GIR_EraseRootFromParent_Done,
     /* 390589 */ // Label 7528: @390589
     /* 390589 */ GIM_Try, /*On fail goto*//*Label 7529*/ GIMT_Encode4(390633), // Rule ID 11365 //
     /* 390594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 390600 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390607 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390611 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$Zs, ssub:{ *:[i32] })
     /* 390611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390616 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 390622 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390627 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390632 */   // GIR_Coverage, 11365,
     /* 390632 */   GIR_EraseRootFromParent_Done,
     /* 390633 */ // Label 7529: @390633
     /* 390633 */ GIM_Try, /*On fail goto*//*Label 7530*/ GIMT_Encode4(390677), // Rule ID 11366 //
     /* 390638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 390641 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 390644 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390651 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390655 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$Zs, ssub:{ *:[i32] })
     /* 390655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390658 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390660 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 390666 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390671 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390676 */   // GIR_Coverage, 11366,
     /* 390676 */   GIR_EraseRootFromParent_Done,
     /* 390677 */ // Label 7530: @390677
     /* 390677 */ GIM_Try, /*On fail goto*//*Label 7531*/ GIMT_Encode4(390722), // Rule ID 5850 //
     /* 390682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 390685 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390692 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390696 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 390700 */   // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] })
     /* 390700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390705 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 390711 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 390716 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390721 */   // GIR_Coverage, 5850,
     /* 390721 */   GIR_EraseRootFromParent_Done,
     /* 390722 */ // Label 7531: @390722
     /* 390722 */ GIM_Try, /*On fail goto*//*Label 7532*/ GIMT_Encode4(390795), // Rule ID 11343 //
     /* 390727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 390730 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 390733 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 390740 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390744 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390748 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 390752 */   // MIs[1] Operand 1
     /* 390752 */   // No operand predicates
     /* 390752 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390754 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)  =>  (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 390754 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 390757 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390761 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390766 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 390772 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390777 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /* 390785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 390787 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390790 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 390793 */   GIR_RootConstrainSelectedInstOperands,
     /* 390794 */   // GIR_Coverage, 11343,
     /* 390794 */   GIR_EraseRootFromParent_Done,
     /* 390795 */ // Label 7532: @390795
     /* 390795 */ GIM_Try, /*On fail goto*//*Label 7533*/ GIMT_Encode4(390868), // Rule ID 11344 //
     /* 390800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 390803 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 390806 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390809 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 390813 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390817 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390821 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 390825 */   // MIs[1] Operand 1
     /* 390825 */   // No operand predicates
     /* 390825 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390827 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)  =>  (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 390827 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 390830 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390834 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390839 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 390845 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390850 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /* 390858 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 390860 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390863 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 390866 */   GIR_RootConstrainSelectedInstOperands,
     /* 390867 */   // GIR_Coverage, 11344,
     /* 390867 */   GIR_EraseRootFromParent_Done,
     /* 390868 */ // Label 7533: @390868
     /* 390868 */ GIM_Try, /*On fail goto*//*Label 7534*/ GIMT_Encode4(390941), // Rule ID 11345 //
     /* 390873 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 390876 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 390879 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390882 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 390886 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390890 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390894 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 390898 */   // MIs[1] Operand 1
     /* 390898 */   // No operand predicates
     /* 390898 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390900 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)  =>  (UMOVvi32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
     /* 390900 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 390903 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390907 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390912 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 390918 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390923 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
     /* 390931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 390933 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390936 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 390939 */   GIR_RootConstrainSelectedInstOperands,
     /* 390940 */   // GIR_Coverage, 11345,
     /* 390940 */   GIR_EraseRootFromParent_Done,
     /* 390941 */ // Label 7534: @390941
     /* 390941 */ GIM_Try, /*On fail goto*//*Label 7535*/ GIMT_Encode4(390989), // Rule ID 1930 //
     /* 390946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 390949 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 390952 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 390955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 390959 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390963 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390967 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390971 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 390975 */   // MIs[1] Operand 1
     /* 390975 */   // No operand predicates
     /* 390975 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 390977 */   // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi8_idx0:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 390977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8_idx0),
     /* 390980 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 390982 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 390984 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 390987 */   GIR_RootConstrainSelectedInstOperands,
     /* 390988 */   // GIR_Coverage, 1930,
     /* 390988 */   GIR_EraseRootFromParent_Done,
     /* 390989 */ // Label 7535: @390989
     /* 390989 */ GIM_Try, /*On fail goto*//*Label 7536*/ GIMT_Encode4(391037), // Rule ID 1931 //
     /* 390994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 390997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 391000 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391007 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391011 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391015 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391019 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 391023 */   // MIs[1] Operand 1
     /* 391023 */   // No operand predicates
     /* 391023 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391025 */   // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi16_idx0:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 391025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16_idx0),
     /* 391028 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391030 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391032 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391035 */   GIR_RootConstrainSelectedInstOperands,
     /* 391036 */   // GIR_Coverage, 1931,
     /* 391036 */   GIR_EraseRootFromParent_Done,
     /* 391037 */ // Label 7536: @391037
     /* 391037 */ GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(391085), // Rule ID 1932 //
     /* 391042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 391045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 391048 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391055 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391059 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391063 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391067 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 391071 */   // MIs[1] Operand 1
     /* 391071 */   // No operand predicates
     /* 391071 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391073 */   // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi32_idx0:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 391073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32_idx0),
     /* 391076 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391078 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391080 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391083 */   GIR_RootConstrainSelectedInstOperands,
     /* 391084 */   // GIR_Coverage, 1932,
     /* 391084 */   GIR_EraseRootFromParent_Done,
     /* 391085 */ // Label 7537: @391085
     /* 391085 */ GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(391133), // Rule ID 1934 //
     /* 391090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 391093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 391096 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391103 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391107 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391111 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391115 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 391119 */   // MIs[1] Operand 1
     /* 391119 */   // No operand predicates
     /* 391119 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391121 */   // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 391121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /* 391124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391126 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391128 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391131 */   GIR_RootConstrainSelectedInstOperands,
     /* 391132 */   // GIR_Coverage, 1934,
     /* 391132 */   GIR_EraseRootFromParent_Done,
     /* 391133 */ // Label 7538: @391133
     /* 391133 */ GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(391181), // Rule ID 1935 //
     /* 391138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 391141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 391144 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391151 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391155 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391159 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391163 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 391167 */   // MIs[1] Operand 1
     /* 391167 */   // No operand predicates
     /* 391167 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391169 */   // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 391169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /* 391172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391174 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391176 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391179 */   GIR_RootConstrainSelectedInstOperands,
     /* 391180 */   // GIR_Coverage, 1935,
     /* 391180 */   GIR_EraseRootFromParent_Done,
     /* 391181 */ // Label 7539: @391181
     /* 391181 */ GIM_Try, /*On fail goto*//*Label 7540*/ GIMT_Encode4(391229), // Rule ID 1936 //
     /* 391186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 391189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 391192 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391199 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391203 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391207 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391211 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 391215 */   // MIs[1] Operand 1
     /* 391215 */   // No operand predicates
     /* 391215 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391217 */   // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 391217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
     /* 391220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391222 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391224 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391227 */   GIR_RootConstrainSelectedInstOperands,
     /* 391228 */   // GIR_Coverage, 1936,
     /* 391228 */   GIR_EraseRootFromParent_Done,
     /* 391229 */ // Label 7540: @391229
     /* 391229 */ GIM_Try, /*On fail goto*//*Label 7541*/ GIMT_Encode4(391274), // Rule ID 5853 //
     /* 391234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 391237 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391240 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391244 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391248 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391252 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391256 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 391260 */   // MIs[1] Operand 1
     /* 391260 */   // No operand predicates
     /* 391260 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391262 */   // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 391262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 391265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391267 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391269 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391272 */   GIR_RootConstrainSelectedInstOperands,
     /* 391273 */   // GIR_Coverage, 5853,
     /* 391273 */   GIR_EraseRootFromParent_Done,
     /* 391274 */ // Label 7541: @391274
     /* 391274 */ GIM_Try, /*On fail goto*//*Label 7542*/ GIMT_Encode4(391350), // Rule ID 11333 //
     /* 391279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391282 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 391285 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391292 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391296 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391300 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 391304 */   // MIs[1] Operand 1
     /* 391304 */   // No operand predicates
     /* 391304 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391306 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index), ssub:{ *:[i32] })
     /* 391306 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 391309 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 391313 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391318 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 391322 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 391325 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391327 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391330 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391332 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 391339 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391344 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 391349 */   // GIR_Coverage, 11333,
     /* 391349 */   GIR_EraseRootFromParent_Done,
     /* 391350 */ // Label 7542: @391350
     /* 391350 */ GIM_Try, /*On fail goto*//*Label 7543*/ GIMT_Encode4(391426), // Rule ID 11334 //
     /* 391355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391358 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 391361 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391368 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391372 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391376 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 391380 */   // MIs[1] Operand 1
     /* 391380 */   // No operand predicates
     /* 391380 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391382 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), ssub:{ *:[i32] })
     /* 391382 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 391385 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 391389 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391394 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 391398 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 391401 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391408 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 391415 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391420 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 391425 */   // GIR_Coverage, 11334,
     /* 391425 */   GIR_EraseRootFromParent_Done,
     /* 391426 */ // Label 7543: @391426
     /* 391426 */ GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(391502), // Rule ID 11335 //
     /* 391431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391434 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 391437 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391444 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391448 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391452 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 391456 */   // MIs[1] Operand 1
     /* 391456 */   // No operand predicates
     /* 391456 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391458 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
     /* 391458 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 391461 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 391465 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391470 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 391474 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 391477 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391482 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391484 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 391491 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391496 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 391501 */   // GIR_Coverage, 11335,
     /* 391501 */   GIR_EraseRootFromParent_Done,
     /* 391502 */ // Label 7544: @391502
     /* 391502 */ GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(391578), // Rule ID 11340 //
     /* 391507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 391513 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391520 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391524 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391528 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 391532 */   // MIs[1] Operand 1
     /* 391532 */   // No operand predicates
     /* 391532 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391534 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
     /* 391534 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 391537 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 391541 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391546 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 391550 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 391553 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391558 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391560 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 391567 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391572 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 391577 */   // GIR_Coverage, 11340,
     /* 391577 */   GIR_EraseRootFromParent_Done,
     /* 391578 */ // Label 7545: @391578
     /* 391578 */ GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(391654), // Rule ID 11341 //
     /* 391583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391586 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 391589 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391596 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391600 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391604 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 391608 */   // MIs[1] Operand 1
     /* 391608 */   // No operand predicates
     /* 391608 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391610 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), ssub:{ *:[i32] })
     /* 391610 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 391613 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 391617 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391622 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 391626 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 391629 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391636 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 391643 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391648 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 391653 */   // GIR_Coverage, 11341,
     /* 391653 */   GIR_EraseRootFromParent_Done,
     /* 391654 */ // Label 7546: @391654
     /* 391654 */ GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(391715), // Rule ID 11323 //
     /* 391659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391662 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 391665 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391668 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391672 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391676 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_B:{ *:[i32] } (WHILELS_PXX_B:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv16i8] }:$vec)
     /* 391676 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 391679 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
     /* 391683 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391688 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391694 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 391698 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 391701 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_B),
     /* 391706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391708 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391711 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 391713 */   GIR_RootConstrainSelectedInstOperands,
     /* 391714 */   // GIR_Coverage, 11323,
     /* 391714 */   GIR_EraseRootFromParent_Done,
     /* 391715 */ // Label 7547: @391715
     /* 391715 */ GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(391776), // Rule ID 11324 //
     /* 391720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391723 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 391726 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391733 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391737 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_H:{ *:[i32] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8i16] }:$vec)
     /* 391737 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 391740 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 391744 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391749 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391755 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 391759 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 391762 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_H),
     /* 391767 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391769 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391772 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 391774 */   GIR_RootConstrainSelectedInstOperands,
     /* 391775 */   // GIR_Coverage, 11324,
     /* 391775 */   GIR_EraseRootFromParent_Done,
     /* 391776 */ // Label 7548: @391776
     /* 391776 */ GIM_Try, /*On fail goto*//*Label 7549*/ GIMT_Encode4(391837), // Rule ID 11325 //
     /* 391781 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391784 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 391787 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 391794 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391798 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_S:{ *:[i32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4i32] }:$vec)
     /* 391798 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 391801 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 391805 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391810 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391816 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 391820 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 391823 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_S),
     /* 391828 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 391830 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391833 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 391835 */   GIR_RootConstrainSelectedInstOperands,
     /* 391836 */   // GIR_Coverage, 11325,
     /* 391836 */   GIR_EraseRootFromParent_Done,
     /* 391837 */ // Label 7549: @391837
     /* 391837 */ GIM_Try, /*On fail goto*//*Label 7550*/ GIMT_Encode4(391898), // Rule ID 11330 //
     /* 391842 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391845 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 391848 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391855 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391859 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f32] }:$vec)
     /* 391859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 391862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 391866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391871 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391877 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 391881 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 391884 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
     /* 391889 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 391891 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391894 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 391896 */   GIR_RootConstrainSelectedInstOperands,
     /* 391897 */   // GIR_Coverage, 11330,
     /* 391897 */   GIR_EraseRootFromParent_Done,
     /* 391898 */ // Label 7550: @391898
     /* 391898 */ GIM_Try, /*On fail goto*//*Label 7551*/ GIMT_Encode4(391959), // Rule ID 11331 //
     /* 391903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 391906 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 391909 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 391916 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391920 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f32] }:$vec)
     /* 391920 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 391923 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 391927 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391932 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391938 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 391942 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 391945 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
     /* 391950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 391952 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391955 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 391957 */   GIR_RootConstrainSelectedInstOperands,
     /* 391958 */   // GIR_Coverage, 11331,
     /* 391958 */   GIR_EraseRootFromParent_Done,
     /* 391959 */ // Label 7551: @391959
     /* 391959 */ GIM_Reject,
     /* 391960 */ // Label 7511: @391960
     /* 391960 */ GIM_Try, /*On fail goto*//*Label 7552*/ GIMT_Encode4(392005), // Rule ID 7037 //
     /* 391965 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 391968 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 391971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391975 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391979 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 391983 */   // (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$V, dsub:{ *:[i32] })
     /* 391983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 391986 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391988 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // V
     /* 391994 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391999 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392004 */   // GIR_Coverage, 7037,
     /* 392004 */   GIR_EraseRootFromParent_Done,
     /* 392005 */ // Label 7552: @392005
     /* 392005 */ GIM_Try, /*On fail goto*//*Label 7553*/ GIMT_Encode4(392049), // Rule ID 11361 //
     /* 392010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392013 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392016 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392023 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 392027 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$Zs, dsub:{ *:[i32] })
     /* 392027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392030 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392032 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Zs
     /* 392038 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392043 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392048 */   // GIR_Coverage, 11361,
     /* 392048 */   GIR_EraseRootFromParent_Done,
     /* 392049 */ // Label 7553: @392049
     /* 392049 */ GIM_Try, /*On fail goto*//*Label 7554*/ GIMT_Encode4(392093), // Rule ID 11367 //
     /* 392054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392057 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392060 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392067 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 392071 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$Zs, dsub:{ *:[i32] })
     /* 392071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392074 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392076 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Zs
     /* 392082 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392087 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392092 */   // GIR_Coverage, 11367,
     /* 392092 */   GIR_EraseRootFromParent_Done,
     /* 392093 */ // Label 7554: @392093
     /* 392093 */ GIM_Try, /*On fail goto*//*Label 7555*/ GIMT_Encode4(392138), // Rule ID 5849 //
     /* 392098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 392101 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392108 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392112 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 392116 */   // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] })
     /* 392116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392121 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 392127 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392132 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392137 */   // GIR_Coverage, 5849,
     /* 392137 */   GIR_EraseRootFromParent_Done,
     /* 392138 */ // Label 7555: @392138
     /* 392138 */ GIM_Try, /*On fail goto*//*Label 7556*/ GIMT_Encode4(392211), // Rule ID 11346 //
     /* 392143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 392146 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392149 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392156 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392160 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392164 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 392168 */   // MIs[1] Operand 1
     /* 392168 */   // No operand predicates
     /* 392168 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392170 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index)  =>  (UMOVvi64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index)
     /* 392170 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 392173 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392177 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392182 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 392188 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392193 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
     /* 392201 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 392203 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392206 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 392209 */   GIR_RootConstrainSelectedInstOperands,
     /* 392210 */   // GIR_Coverage, 11346,
     /* 392210 */   GIR_EraseRootFromParent_Done,
     /* 392211 */ // Label 7556: @392211
     /* 392211 */ GIM_Try, /*On fail goto*//*Label 7557*/ GIMT_Encode4(392259), // Rule ID 1933 //
     /* 392216 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 392219 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 392222 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392229 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392233 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392237 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392241 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 392245 */   // MIs[1] Operand 1
     /* 392245 */   // No operand predicates
     /* 392245 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392247 */   // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi64_idx0:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 392247 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64_idx0),
     /* 392250 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 392252 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 392254 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 392257 */   GIR_RootConstrainSelectedInstOperands,
     /* 392258 */   // GIR_Coverage, 1933,
     /* 392258 */   GIR_EraseRootFromParent_Done,
     /* 392259 */ // Label 7557: @392259
     /* 392259 */ GIM_Try, /*On fail goto*//*Label 7558*/ GIMT_Encode4(392307), // Rule ID 1937 //
     /* 392264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 392267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 392270 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392277 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392281 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392285 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392289 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 392293 */   // MIs[1] Operand 1
     /* 392293 */   // No operand predicates
     /* 392293 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392295 */   // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 392295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
     /* 392298 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 392300 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 392302 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 392305 */   GIR_RootConstrainSelectedInstOperands,
     /* 392306 */   // GIR_Coverage, 1937,
     /* 392306 */   GIR_EraseRootFromParent_Done,
     /* 392307 */ // Label 7558: @392307
     /* 392307 */ GIM_Try, /*On fail goto*//*Label 7559*/ GIMT_Encode4(392352), // Rule ID 5852 //
     /* 392312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 392315 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392322 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392326 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392330 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392334 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 392338 */   // MIs[1] Operand 1
     /* 392338 */   // No operand predicates
     /* 392338 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392340 */   // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (DUPi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 392340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 392343 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392345 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 392347 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 392350 */   GIR_RootConstrainSelectedInstOperands,
     /* 392351 */   // GIR_Coverage, 5852,
     /* 392351 */   GIR_EraseRootFromParent_Done,
     /* 392352 */ // Label 7559: @392352
     /* 392352 */ GIM_Try, /*On fail goto*//*Label 7560*/ GIMT_Encode4(392428), // Rule ID 11336 //
     /* 392357 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392360 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392363 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392370 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392374 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392378 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 392382 */   // MIs[1] Operand 1
     /* 392382 */   // No operand predicates
     /* 392382 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392384 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
     /* 392384 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 392387 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 392391 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392396 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 392400 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 392403 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392410 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 392417 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392422 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392427 */   // GIR_Coverage, 11336,
     /* 392427 */   GIR_EraseRootFromParent_Done,
     /* 392428 */ // Label 7560: @392428
     /* 392428 */ GIM_Try, /*On fail goto*//*Label 7561*/ GIMT_Encode4(392504), // Rule ID 11342 //
     /* 392433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392439 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392446 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 392450 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392454 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 392458 */   // MIs[1] Operand 1
     /* 392458 */   // No operand predicates
     /* 392458 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392460 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
     /* 392460 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 392463 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 392467 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392472 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 392476 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 392479 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 392484 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392486 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 392493 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392498 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392503 */   // GIR_Coverage, 11342,
     /* 392503 */   GIR_EraseRootFromParent_Done,
     /* 392504 */ // Label 7561: @392504
     /* 392504 */ GIM_Try, /*On fail goto*//*Label 7562*/ GIMT_Encode4(392565), // Rule ID 11326 //
     /* 392509 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392515 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392522 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392526 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_D:{ *:[i64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2i64] }:$vec)
     /* 392526 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 392529 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 392533 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392538 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 392544 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 392548 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 392551 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_D),
     /* 392556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 392558 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392561 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 392563 */   GIR_RootConstrainSelectedInstOperands,
     /* 392564 */   // GIR_Coverage, 11326,
     /* 392564 */   GIR_EraseRootFromParent_Done,
     /* 392565 */ // Label 7562: @392565
     /* 392565 */ GIM_Try, /*On fail goto*//*Label 7563*/ GIMT_Encode4(392626), // Rule ID 11332 //
     /* 392570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392573 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 392576 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 392579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392583 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 392587 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_D:{ *:[f64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f64] }:$vec)
     /* 392587 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 392590 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 392594 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392599 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 392605 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 392609 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 392612 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_D),
     /* 392617 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 392619 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392622 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 392624 */   GIR_RootConstrainSelectedInstOperands,
     /* 392625 */   // GIR_Coverage, 11332,
     /* 392625 */   GIR_EraseRootFromParent_Done,
     /* 392626 */ // Label 7563: @392626
     /* 392626 */ GIM_Reject,
     /* 392627 */ // Label 7512: @392627
     /* 392627 */ GIM_Reject,
     /* 392628 */ // Label 93: @392628
     /* 392628 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(14), GIMT_Encode2(24), /*)*//*default:*//*Label 7571*/ GIMT_Encode4(394947),
     /* 392639 */ /*GILLT_nxv2s16*//*Label 7564*/ GIMT_Encode4(392679),
     /* 392643 */ /*GILLT_nxv2s32*//*Label 7565*/ GIMT_Encode4(393038),
     /* 392647 */ /*GILLT_nxv2s64*//*Label 7566*/ GIMT_Encode4(393340), GIMT_Encode4(0),
     /* 392655 */ /*GILLT_nxv4s16*//*Label 7567*/ GIMT_Encode4(393715),
     /* 392659 */ /*GILLT_nxv4s32*//*Label 7568*/ GIMT_Encode4(394017), GIMT_Encode4(0),
     /* 392667 */ /*GILLT_nxv8s16*//*Label 7569*/ GIMT_Encode4(394392), GIMT_Encode4(0),
     /* 392675 */ /*GILLT_nxv16s8*//*Label 7570*/ GIMT_Encode4(394803),
     /* 392679 */ // Label 7564: @392679
     /* 392679 */ GIM_Try, /*On fail goto*//*Label 7572*/ GIMT_Encode4(393037),
     /* 392684 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 392687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392691 */   GIM_Try, /*On fail goto*//*Label 7573*/ GIMT_Encode4(392755), // Rule ID 6083 //
     /* 392696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 392699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 392707 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 392711 */     // MIs[1] Operand 1
     /* 392711 */     // No operand predicates
     /* 392711 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392713 */     // (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 392713 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 392716 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 392720 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392725 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 392728 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392738 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 392744 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392749 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 392754 */     // GIR_Coverage, 6083,
     /* 392754 */     GIR_EraseRootFromParent_Done,
     /* 392755 */   // Label 7573: @392755
     /* 392755 */   GIM_Try, /*On fail goto*//*Label 7574*/ GIMT_Encode4(392812), // Rule ID 2675 //
     /* 392760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 392771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 392775 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 392779 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392784 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 392788 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392792 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 392796 */     // MIs[2] Operand 1
     /* 392796 */     // No operand predicates
     /* 392796 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392798 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 392798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 392801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 392803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 392807 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 392810 */     GIR_RootConstrainSelectedInstOperands,
     /* 392811 */     // GIR_Coverage, 2675,
     /* 392811 */     GIR_EraseRootFromParent_Done,
     /* 392812 */   // Label 7574: @392812
     /* 392812 */   GIM_Try, /*On fail goto*//*Label 7575*/ GIMT_Encode4(392869), // Rule ID 2677 //
     /* 392817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 392828 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 392832 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 392836 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392841 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 392845 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392849 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 392853 */     // MIs[2] Operand 1
     /* 392853 */     // No operand predicates
     /* 392853 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392855 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f16] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 392855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 392858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 392860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 392864 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 392867 */     GIR_RootConstrainSelectedInstOperands,
     /* 392868 */     // GIR_Coverage, 2677,
     /* 392868 */     GIR_EraseRootFromParent_Done,
     /* 392869 */   // Label 7575: @392869
     /* 392869 */   GIM_Try, /*On fail goto*//*Label 7576*/ GIMT_Encode4(392926), // Rule ID 8464 //
     /* 392874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392877 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392881 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 392885 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 392889 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 392893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 392898 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 392902 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 392906 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 392910 */     // MIs[2] Operand 1
     /* 392910 */     // No operand predicates
     /* 392910 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392912 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv2f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 392912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 392915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 392917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 392921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 392924 */     GIR_RootConstrainSelectedInstOperands,
     /* 392925 */     // GIR_Coverage, 8464,
     /* 392925 */     GIR_EraseRootFromParent_Done,
     /* 392926 */   // Label 7576: @392926
     /* 392926 */   GIM_Try, /*On fail goto*//*Label 7577*/ GIMT_Encode4(392960), // Rule ID 8507 //
     /* 392931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 392942 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 392946 */     // MIs[1] Operand 1
     /* 392946 */     // No operand predicates
     /* 392946 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 392948 */     // (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv2f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 392948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 392951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 392953 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 392958 */     GIR_RootConstrainSelectedInstOperands,
     /* 392959 */     // GIR_Coverage, 8507,
     /* 392959 */     GIR_EraseRootFromParent_Done,
     /* 392960 */   // Label 7577: @392960
     /* 392960 */   GIM_Try, /*On fail goto*//*Label 7578*/ GIMT_Encode4(393036), // Rule ID 8485 //
     /* 392965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 392968 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392972 */     // (splat_vector:{ *:[nxv2f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv2f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 392972 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 392975 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 392979 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392984 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 392986 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 392989 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 392993 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392998 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393001 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 393005 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 393008 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393013 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393018 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 393026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393028 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393034 */     GIR_RootConstrainSelectedInstOperands,
     /* 393035 */     // GIR_Coverage, 8485,
     /* 393035 */     GIR_EraseRootFromParent_Done,
     /* 393036 */   // Label 7578: @393036
     /* 393036 */   GIM_Reject,
     /* 393037 */ // Label 7572: @393037
     /* 393037 */ GIM_Reject,
     /* 393038 */ // Label 7565: @393038
     /* 393038 */ GIM_Try, /*On fail goto*//*Label 7579*/ GIMT_Encode4(393339),
     /* 393043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 393046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393050 */   GIM_Try, /*On fail goto*//*Label 7580*/ GIMT_Encode4(393114), // Rule ID 6081 //
     /* 393055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 393058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393066 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 393070 */     // MIs[1] Operand 1
     /* 393070 */     // No operand predicates
     /* 393070 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393072 */     // (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 393072 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393075 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 393079 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393084 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 393087 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393097 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 393103 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393108 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393113 */     // GIR_Coverage, 6081,
     /* 393113 */     GIR_EraseRootFromParent_Done,
     /* 393114 */   // Label 7580: @393114
     /* 393114 */   GIM_Try, /*On fail goto*//*Label 7581*/ GIMT_Encode4(393171), // Rule ID 8473 //
     /* 393119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 393134 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393138 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393143 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393147 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393151 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 393155 */     // MIs[2] Operand 1
     /* 393155 */     // No operand predicates
     /* 393155 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393157 */     // (splat_vector:{ *:[nxv2f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 393157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 393160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393166 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393169 */     GIR_RootConstrainSelectedInstOperands,
     /* 393170 */     // GIR_Coverage, 8473,
     /* 393170 */     GIR_EraseRootFromParent_Done,
     /* 393171 */   // Label 7581: @393171
     /* 393171 */   GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(393228), // Rule ID 8482 //
     /* 393176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393179 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393183 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393187 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 393191 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393195 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393200 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393204 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393208 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 393212 */     // MIs[2] Operand 1
     /* 393212 */     // No operand predicates
     /* 393212 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393214 */     // (splat_vector:{ *:[nxv2f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f32] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 393214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 393217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393223 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393226 */     GIR_RootConstrainSelectedInstOperands,
     /* 393227 */     // GIR_Coverage, 8482,
     /* 393227 */     GIR_EraseRootFromParent_Done,
     /* 393228 */   // Label 7582: @393228
     /* 393228 */   GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(393262), // Rule ID 8509 //
     /* 393233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393236 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393240 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393244 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 393248 */     // MIs[1] Operand 1
     /* 393248 */     // No operand predicates
     /* 393248 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393250 */     // (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8)  =>  (FDUP_ZI_S:{ *:[nxv2f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 393250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_S),
     /* 393253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393255 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 393260 */     GIR_RootConstrainSelectedInstOperands,
     /* 393261 */     // GIR_Coverage, 8509,
     /* 393261 */     GIR_EraseRootFromParent_Done,
     /* 393262 */   // Label 7583: @393262
     /* 393262 */   GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(393338), // Rule ID 8487 //
     /* 393267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393270 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 393274 */     // (splat_vector:{ *:[nxv2f32] } FPR32:{ *:[f32] }:$src)  =>  (DUP_ZZI_S:{ *:[nxv2f32] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR32:{ *:[f32] }:$src, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 393274 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 393277 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 393281 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393286 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 393288 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 393291 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 393295 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393300 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393303 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 393307 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 393310 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393315 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393320 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 393325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 393328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393330 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393336 */     GIR_RootConstrainSelectedInstOperands,
     /* 393337 */     // GIR_Coverage, 8487,
     /* 393337 */     GIR_EraseRootFromParent_Done,
     /* 393338 */   // Label 7584: @393338
     /* 393338 */   GIM_Reject,
     /* 393339 */ // Label 7579: @393339
     /* 393339 */ GIM_Reject,
     /* 393340 */ // Label 7566: @393340
     /* 393340 */ GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(393714),
     /* 393345 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 393348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393352 */   GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(393406), // Rule ID 6076 //
     /* 393357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 393360 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 393364 */     // (splat_vector:{ *:[nxv2i64] } 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 393364 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393367 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 393371 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393376 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 393379 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393389 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 393395 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393400 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393405 */     // GIR_Coverage, 6076,
     /* 393405 */     GIR_EraseRootFromParent_Done,
     /* 393406 */   // Label 7586: @393406
     /* 393406 */   GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(393470), // Rule ID 6080 //
     /* 393411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 393414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393422 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 393426 */     // MIs[1] Operand 1
     /* 393426 */     // No operand predicates
     /* 393426 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393428 */     // (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 393428 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393431 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 393435 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393440 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 393443 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393453 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 393459 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393464 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393469 */     // GIR_Coverage, 6080,
     /* 393469 */     GIR_EraseRootFromParent_Done,
     /* 393470 */   // Label 7587: @393470
     /* 393470 */   GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(393527), // Rule ID 2672 //
     /* 393475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393482 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393486 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 393490 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393494 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393499 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393503 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393507 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 393511 */     // MIs[2] Operand 1
     /* 393511 */     // No operand predicates
     /* 393511 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393513 */     // (splat_vector:{ *:[nxv2i64] } (vector_extract:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 393513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 393516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393522 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393525 */     GIR_RootConstrainSelectedInstOperands,
     /* 393526 */     // GIR_Coverage, 2672,
     /* 393526 */     GIR_EraseRootFromParent_Done,
     /* 393527 */   // Label 7588: @393527
     /* 393527 */   GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(393584), // Rule ID 8479 //
     /* 393532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393535 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393539 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393543 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 393547 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393551 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393564 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 393568 */     // MIs[2] Operand 1
     /* 393568 */     // No operand predicates
     /* 393568 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393570 */     // (splat_vector:{ *:[nxv2f64] } (vector_extract:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f64] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 393570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 393573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393582 */     GIR_RootConstrainSelectedInstOperands,
     /* 393583 */     // GIR_Coverage, 8479,
     /* 393583 */     GIR_EraseRootFromParent_Done,
     /* 393584 */   // Label 7589: @393584
     /* 393584 */   GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(393618), // Rule ID 8510 //
     /* 393589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393600 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 393604 */     // MIs[1] Operand 1
     /* 393604 */     // No operand predicates
     /* 393604 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393606 */     // (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm8)  =>  (FDUP_ZI_D:{ *:[nxv2f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>>:$imm8))
     /* 393606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_D),
     /* 393609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393611 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm8
     /* 393616 */     GIR_RootConstrainSelectedInstOperands,
     /* 393617 */     // GIR_Coverage, 8510,
     /* 393617 */     GIR_EraseRootFromParent_Done,
     /* 393618 */   // Label 7590: @393618
     /* 393618 */   GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(393637), // Rule ID 2395 //
     /* 393623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393626 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 393630 */     // (splat_vector:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$Rn)  =>  (DUP_ZR_D:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 393630 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 393635 */     GIR_RootConstrainSelectedInstOperands,
     /* 393636 */     // GIR_Coverage, 2395,
     /* 393636 */     GIR_Done,
     /* 393637 */   // Label 7591: @393637
     /* 393637 */   GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(393713), // Rule ID 8488 //
     /* 393642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393645 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393649 */     // (splat_vector:{ *:[nxv2f64] } FPR64:{ *:[f64] }:$src)  =>  (DUP_ZZI_D:{ *:[nxv2f64] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR64:{ *:[f64] }:$src, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 393649 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 393652 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 393656 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393661 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 393663 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 393666 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 393670 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393675 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393678 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 393682 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 393685 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393690 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393695 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 393703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393705 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393711 */     GIR_RootConstrainSelectedInstOperands,
     /* 393712 */     // GIR_Coverage, 8488,
     /* 393712 */     GIR_EraseRootFromParent_Done,
     /* 393713 */   // Label 7592: @393713
     /* 393713 */   GIM_Reject,
     /* 393714 */ // Label 7585: @393714
     /* 393714 */ GIM_Reject,
     /* 393715 */ // Label 7567: @393715
     /* 393715 */ GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(394016),
     /* 393720 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 393723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393727 */   GIM_Try, /*On fail goto*//*Label 7594*/ GIMT_Encode4(393791), // Rule ID 6084 //
     /* 393732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 393735 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393739 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393743 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 393747 */     // MIs[1] Operand 1
     /* 393747 */     // No operand predicates
     /* 393747 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393749 */     // (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv4f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 393749 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393752 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 393756 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393761 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 393764 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393774 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 393780 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393785 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393790 */     // GIR_Coverage, 6084,
     /* 393790 */     GIR_EraseRootFromParent_Done,
     /* 393791 */   // Label 7594: @393791
     /* 393791 */   GIM_Try, /*On fail goto*//*Label 7595*/ GIMT_Encode4(393848), // Rule ID 2676 //
     /* 393796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 393811 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393815 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393828 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 393832 */     // MIs[2] Operand 1
     /* 393832 */     // No operand predicates
     /* 393832 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393834 */     // (splat_vector:{ *:[nxv4f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 393834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 393837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393843 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393846 */     GIR_RootConstrainSelectedInstOperands,
     /* 393847 */     // GIR_Coverage, 2676,
     /* 393847 */     GIR_EraseRootFromParent_Done,
     /* 393848 */   // Label 7595: @393848
     /* 393848 */   GIM_Try, /*On fail goto*//*Label 7596*/ GIMT_Encode4(393905), // Rule ID 8467 //
     /* 393853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 393868 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393872 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393877 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393881 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393885 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 393889 */     // MIs[2] Operand 1
     /* 393889 */     // No operand predicates
     /* 393889 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393891 */     // (splat_vector:{ *:[nxv4f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 393891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 393894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 393900 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 393903 */     GIR_RootConstrainSelectedInstOperands,
     /* 393904 */     // GIR_Coverage, 8467,
     /* 393904 */     GIR_EraseRootFromParent_Done,
     /* 393905 */   // Label 7596: @393905
     /* 393905 */   GIM_Try, /*On fail goto*//*Label 7597*/ GIMT_Encode4(393939), // Rule ID 8506 //
     /* 393910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 393921 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 393925 */     // MIs[1] Operand 1
     /* 393925 */     // No operand predicates
     /* 393925 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 393927 */     // (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv4f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 393927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 393930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 393932 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 393937 */     GIR_RootConstrainSelectedInstOperands,
     /* 393938 */     // GIR_Coverage, 8506,
     /* 393938 */     GIR_EraseRootFromParent_Done,
     /* 393939 */   // Label 7597: @393939
     /* 393939 */   GIM_Try, /*On fail goto*//*Label 7598*/ GIMT_Encode4(394015), // Rule ID 8484 //
     /* 393944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 393947 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393951 */     // (splat_vector:{ *:[nxv4f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv4f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 393951 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 393954 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 393958 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393963 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 393965 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 393968 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 393972 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393977 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393980 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 393984 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 393987 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393992 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 393997 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 394005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394007 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394013 */     GIR_RootConstrainSelectedInstOperands,
     /* 394014 */     // GIR_Coverage, 8484,
     /* 394014 */     GIR_EraseRootFromParent_Done,
     /* 394015 */   // Label 7598: @394015
     /* 394015 */   GIM_Reject,
     /* 394016 */ // Label 7593: @394016
     /* 394016 */ GIM_Reject,
     /* 394017 */ // Label 7568: @394017
     /* 394017 */ GIM_Try, /*On fail goto*//*Label 7599*/ GIMT_Encode4(394391),
     /* 394022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394029 */   GIM_Try, /*On fail goto*//*Label 7600*/ GIMT_Encode4(394083), // Rule ID 6077 //
     /* 394034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 394037 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 394041 */     // (splat_vector:{ *:[nxv4i32] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 394041 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394044 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 394048 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394053 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 394056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394066 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 394072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394077 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394082 */     // GIR_Coverage, 6077,
     /* 394082 */     GIR_EraseRootFromParent_Done,
     /* 394083 */   // Label 7600: @394083
     /* 394083 */   GIM_Try, /*On fail goto*//*Label 7601*/ GIMT_Encode4(394147), // Rule ID 6082 //
     /* 394088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 394091 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394095 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 394099 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 394103 */     // MIs[1] Operand 1
     /* 394103 */     // No operand predicates
     /* 394103 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394105 */     // (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 394105 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394108 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 394112 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394117 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 394120 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394130 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 394136 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394141 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394146 */     // GIR_Coverage, 6082,
     /* 394146 */     GIR_EraseRootFromParent_Done,
     /* 394147 */   // Label 7601: @394147
     /* 394147 */   GIM_Try, /*On fail goto*//*Label 7602*/ GIMT_Encode4(394204), // Rule ID 2669 //
     /* 394152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 394167 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394171 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394184 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 394188 */     // MIs[2] Operand 1
     /* 394188 */     // No operand predicates
     /* 394188 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394190 */     // (splat_vector:{ *:[nxv4i32] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 394190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 394193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 394199 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 394202 */     GIR_RootConstrainSelectedInstOperands,
     /* 394203 */     // GIR_Coverage, 2669,
     /* 394203 */     GIR_EraseRootFromParent_Done,
     /* 394204 */   // Label 7602: @394204
     /* 394204 */   GIM_Try, /*On fail goto*//*Label 7603*/ GIMT_Encode4(394261), // Rule ID 8476 //
     /* 394209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394212 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394220 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 394224 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394228 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394233 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394237 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394241 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 394245 */     // MIs[2] Operand 1
     /* 394245 */     // No operand predicates
     /* 394245 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394247 */     // (splat_vector:{ *:[nxv4f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 394247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 394250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 394256 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 394259 */     GIR_RootConstrainSelectedInstOperands,
     /* 394260 */     // GIR_Coverage, 8476,
     /* 394260 */     GIR_EraseRootFromParent_Done,
     /* 394261 */   // Label 7603: @394261
     /* 394261 */   GIM_Try, /*On fail goto*//*Label 7604*/ GIMT_Encode4(394295), // Rule ID 8508 //
     /* 394266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394273 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 394277 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 394281 */     // MIs[1] Operand 1
     /* 394281 */     // No operand predicates
     /* 394281 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394283 */     // (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8)  =>  (FDUP_ZI_S:{ *:[nxv4f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 394283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_S),
     /* 394286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394288 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 394293 */     GIR_RootConstrainSelectedInstOperands,
     /* 394294 */     // GIR_Coverage, 8508,
     /* 394294 */     GIR_EraseRootFromParent_Done,
     /* 394295 */   // Label 7604: @394295
     /* 394295 */   GIM_Try, /*On fail goto*//*Label 7605*/ GIMT_Encode4(394314), // Rule ID 2394 //
     /* 394300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394303 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 394307 */     // (splat_vector:{ *:[nxv4i32] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_S:{ *:[nxv4i32] } GPR32sp:{ *:[i32] }:$Rn)
     /* 394307 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 394312 */     GIR_RootConstrainSelectedInstOperands,
     /* 394313 */     // GIR_Coverage, 2394,
     /* 394313 */     GIR_Done,
     /* 394314 */   // Label 7605: @394314
     /* 394314 */   GIM_Try, /*On fail goto*//*Label 7606*/ GIMT_Encode4(394390), // Rule ID 8486 //
     /* 394319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 394326 */     // (splat_vector:{ *:[nxv4f32] } FPR32:{ *:[f32] }:$src)  =>  (DUP_ZZI_S:{ *:[nxv4f32] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR32:{ *:[f32] }:$src, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 394326 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 394329 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 394333 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394338 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 394340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 394343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 394347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394352 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394355 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 394359 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 394362 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394367 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394372 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 394377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 394380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394382 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394388 */     GIR_RootConstrainSelectedInstOperands,
     /* 394389 */     // GIR_Coverage, 8486,
     /* 394389 */     GIR_EraseRootFromParent_Done,
     /* 394390 */   // Label 7606: @394390
     /* 394390 */   GIM_Reject,
     /* 394391 */ // Label 7599: @394391
     /* 394391 */ GIM_Reject,
     /* 394392 */ // Label 7569: @394392
     /* 394392 */ GIM_Try, /*On fail goto*//*Label 7607*/ GIMT_Encode4(394453), // Rule ID 6078 //
     /* 394397 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 394400 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394403 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394407 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 394411 */   // (splat_vector:{ *:[nxv8i16] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 394411 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394414 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 394418 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394423 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 394426 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394431 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394433 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394436 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394439 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 394442 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394447 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394452 */   // GIR_Coverage, 6078,
     /* 394452 */   GIR_EraseRootFromParent_Done,
     /* 394453 */ // Label 7607: @394453
     /* 394453 */ GIM_Try, /*On fail goto*//*Label 7608*/ GIMT_Encode4(394524), // Rule ID 6085 //
     /* 394458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 394461 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 394464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394468 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394472 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 394476 */   GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 394480 */   // MIs[1] Operand 1
     /* 394480 */   // No operand predicates
     /* 394480 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394482 */   // (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 394482 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394485 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 394489 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394494 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 394497 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394502 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394504 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394507 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394510 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 394513 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394518 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394523 */   // GIR_Coverage, 6085,
     /* 394523 */   GIR_EraseRootFromParent_Done,
     /* 394524 */ // Label 7608: @394524
     /* 394524 */ GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(394588), // Rule ID 2666 //
     /* 394529 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394532 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394539 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394543 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394547 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 394551 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394555 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394560 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394564 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394568 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 394572 */   // MIs[2] Operand 1
     /* 394572 */   // No operand predicates
     /* 394572 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394574 */   // (splat_vector:{ *:[nxv8i16] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 394574 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 394577 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394579 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 394583 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 394586 */   GIR_RootConstrainSelectedInstOperands,
     /* 394587 */   // GIR_Coverage, 2666,
     /* 394587 */   GIR_EraseRootFromParent_Done,
     /* 394588 */ // Label 7609: @394588
     /* 394588 */ GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(394652), // Rule ID 8470 //
     /* 394593 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394596 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 394599 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394603 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394607 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394611 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 394615 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394619 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394624 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394628 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394632 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 394636 */   // MIs[2] Operand 1
     /* 394636 */   // No operand predicates
     /* 394636 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394638 */   // (splat_vector:{ *:[nxv8f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv8f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 394638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 394641 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394643 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 394647 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 394650 */   GIR_RootConstrainSelectedInstOperands,
     /* 394651 */   // GIR_Coverage, 8470,
     /* 394651 */   GIR_EraseRootFromParent_Done,
     /* 394652 */ // Label 7610: @394652
     /* 394652 */ GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(394693), // Rule ID 8505 //
     /* 394657 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394660 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 394663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394667 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394671 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 394675 */   GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 394679 */   // MIs[1] Operand 1
     /* 394679 */   // No operand predicates
     /* 394679 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394681 */   // (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv8f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 394681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 394684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394686 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 394691 */   GIR_RootConstrainSelectedInstOperands,
     /* 394692 */   // GIR_Coverage, 8505,
     /* 394692 */   GIR_EraseRootFromParent_Done,
     /* 394693 */ // Label 7611: @394693
     /* 394693 */ GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(394719), // Rule ID 2393 //
     /* 394698 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394701 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394708 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 394712 */   // (splat_vector:{ *:[nxv8i16] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_H:{ *:[nxv8i16] } GPR32sp:{ *:[i32] }:$Rn)
     /* 394712 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 394717 */   GIR_RootConstrainSelectedInstOperands,
     /* 394718 */   // GIR_Coverage, 2393,
     /* 394718 */   GIR_Done,
     /* 394719 */ // Label 7612: @394719
     /* 394719 */ GIM_Try, /*On fail goto*//*Label 7613*/ GIMT_Encode4(394802), // Rule ID 8483 //
     /* 394724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 394730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394734 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394738 */   // (splat_vector:{ *:[nxv8f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv8f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 394738 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 394741 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 394745 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394750 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 394752 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 394755 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 394759 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394764 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394767 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 394771 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 394774 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394779 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394784 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394789 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 394792 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394794 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394800 */   GIR_RootConstrainSelectedInstOperands,
     /* 394801 */   // GIR_Coverage, 8483,
     /* 394801 */   GIR_EraseRootFromParent_Done,
     /* 394802 */ // Label 7613: @394802
     /* 394802 */ GIM_Reject,
     /* 394803 */ // Label 7570: @394803
     /* 394803 */ GIM_Try, /*On fail goto*//*Label 7614*/ GIMT_Encode4(394946),
     /* 394808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394815 */   GIM_Try, /*On fail goto*//*Label 7615*/ GIMT_Encode4(394869), // Rule ID 6079 //
     /* 394820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 394823 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 394827 */     // (splat_vector:{ *:[nxv16i8] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 394827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 394834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394839 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 394842 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394852 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 394858 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394863 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394868 */     // GIR_Coverage, 6079,
     /* 394868 */     GIR_EraseRootFromParent_Done,
     /* 394869 */   // Label 7615: @394869
     /* 394869 */   GIM_Try, /*On fail goto*//*Label 7616*/ GIMT_Encode4(394926), // Rule ID 2663 //
     /* 394874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394877 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394881 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394885 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 394889 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 394898 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394902 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394906 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 394910 */     // MIs[2] Operand 1
     /* 394910 */     // No operand predicates
     /* 394910 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394912 */     // (splat_vector:{ *:[nxv16i8] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index))  =>  (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index)
     /* 394912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 394915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 394917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 394921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 394924 */     GIR_RootConstrainSelectedInstOperands,
     /* 394925 */     // GIR_Coverage, 2663,
     /* 394925 */     GIR_EraseRootFromParent_Done,
     /* 394926 */   // Label 7616: @394926
     /* 394926 */   GIM_Try, /*On fail goto*//*Label 7617*/ GIMT_Encode4(394945), // Rule ID 2392 //
     /* 394931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 394934 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 394938 */     // (splat_vector:{ *:[nxv16i8] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_B:{ *:[nxv16i8] } GPR32sp:{ *:[i32] }:$Rn)
     /* 394938 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_B),
     /* 394943 */     GIR_RootConstrainSelectedInstOperands,
     /* 394944 */     // GIR_Coverage, 2392,
     /* 394944 */     GIR_Done,
     /* 394945 */   // Label 7617: @394945
     /* 394945 */   GIM_Reject,
     /* 394946 */ // Label 7614: @394946
     /* 394946 */ GIM_Reject,
     /* 394947 */ // Label 7571: @394947
     /* 394947 */ GIM_Reject,
     /* 394948 */ // Label 94: @394948
     /* 394948 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 7620*/ GIMT_Encode4(395099),
     /* 394959 */ /*GILLT_s32*//*Label 7618*/ GIMT_Encode4(394967),
     /* 394963 */ /*GILLT_s64*//*Label 7619*/ GIMT_Encode4(395033),
     /* 394967 */ // Label 7618: @394967
     /* 394967 */ GIM_Try, /*On fail goto*//*Label 7621*/ GIMT_Encode4(395032),
     /* 394972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 394975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 394979 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 394983 */   GIM_Try, /*On fail goto*//*Label 7622*/ GIMT_Encode4(394998), // Rule ID 2325 //
     /* 394988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 394991 */     // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CTZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 394991 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZWr),
     /* 394996 */     GIR_RootConstrainSelectedInstOperands,
     /* 394997 */     // GIR_Coverage, 2325,
     /* 394997 */     GIR_Done,
     /* 394998 */   // Label 7622: @394998
     /* 394998 */   GIM_Try, /*On fail goto*//*Label 7623*/ GIMT_Encode4(395031), // Rule ID 4038 //
     /* 395003 */     // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn))
     /* 395003 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395006 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
     /* 395010 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395015 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 395019 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
     /* 395024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395026 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395029 */     GIR_RootConstrainSelectedInstOperands,
     /* 395030 */     // GIR_Coverage, 4038,
     /* 395030 */     GIR_EraseRootFromParent_Done,
     /* 395031 */   // Label 7623: @395031
     /* 395031 */   GIM_Reject,
     /* 395032 */ // Label 7621: @395032
     /* 395032 */ GIM_Reject,
     /* 395033 */ // Label 7619: @395033
     /* 395033 */ GIM_Try, /*On fail goto*//*Label 7624*/ GIMT_Encode4(395098),
     /* 395038 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 395041 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395045 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395049 */   GIM_Try, /*On fail goto*//*Label 7625*/ GIMT_Encode4(395064), // Rule ID 2326 //
     /* 395054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 395057 */     // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CTZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 395057 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZXr),
     /* 395062 */     GIR_RootConstrainSelectedInstOperands,
     /* 395063 */     // GIR_Coverage, 2326,
     /* 395063 */     GIR_Done,
     /* 395064 */   // Label 7625: @395064
     /* 395064 */   GIM_Try, /*On fail goto*//*Label 7626*/ GIMT_Encode4(395097), // Rule ID 4039 //
     /* 395069 */     // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn))
     /* 395069 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 395072 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
     /* 395076 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395081 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 395085 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
     /* 395090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395092 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395095 */     GIR_RootConstrainSelectedInstOperands,
     /* 395096 */     // GIR_Coverage, 4039,
     /* 395096 */     GIR_EraseRootFromParent_Done,
     /* 395097 */   // Label 7626: @395097
     /* 395097 */   GIM_Reject,
     /* 395098 */ // Label 7624: @395098
     /* 395098 */ GIM_Reject,
     /* 395099 */ // Label 7620: @395099
     /* 395099 */ GIM_Reject,
     /* 395100 */ // Label 95: @395100
     /* 395100 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7635*/ GIMT_Encode4(395773),
     /* 395111 */ /*GILLT_s32*//*Label 7627*/ GIMT_Encode4(395151),
     /* 395115 */ /*GILLT_s64*//*Label 7628*/ GIMT_Encode4(395381), GIMT_Encode4(0),
     /* 395123 */ /*GILLT_v2s32*//*Label 7629*/ GIMT_Encode4(395611), GIMT_Encode4(0),
     /* 395131 */ /*GILLT_v4s16*//*Label 7630*/ GIMT_Encode4(395638),
     /* 395135 */ /*GILLT_v4s32*//*Label 7631*/ GIMT_Encode4(395665),
     /* 395139 */ /*GILLT_v8s8*//*Label 7632*/ GIMT_Encode4(395692),
     /* 395143 */ /*GILLT_v8s16*//*Label 7633*/ GIMT_Encode4(395719),
     /* 395147 */ /*GILLT_v16s8*//*Label 7634*/ GIMT_Encode4(395746),
     /* 395151 */ // Label 7627: @395151
     /* 395151 */ GIM_Try, /*On fail goto*//*Label 7636*/ GIMT_Encode4(395380),
     /* 395156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 395159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395163 */   GIM_Try, /*On fail goto*//*Label 7637*/ GIMT_Encode4(395263), // Rule ID 4040 //
     /* 395168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 395176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 395180 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 395184 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 395188 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 395192 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 395196 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 395200 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 395204 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 395208 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 395212 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 395216 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 395220 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /* 395224 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 395228 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395233 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
     /* 395237 */     // MIs[3] Rn
     /* 395237 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /* 395242 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 395246 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 395250 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 395252 */     // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] }))  =>  (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 395252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
     /* 395255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /* 395261 */     GIR_RootConstrainSelectedInstOperands,
     /* 395262 */     // GIR_Coverage, 4040,
     /* 395262 */     GIR_EraseRootFromParent_Done,
     /* 395263 */   // Label 7637: @395263
     /* 395263 */   GIM_Try, /*On fail goto*//*Label 7638*/ GIMT_Encode4(395363), // Rule ID 14112 //
     /* 395268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 395276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 395280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 395284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 395288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 395292 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 395296 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 395300 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 395304 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 395308 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 395312 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /* 395316 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395321 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 395325 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 395329 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 395333 */     // MIs[4] Rn
     /* 395333 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 395338 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
     /* 395342 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 395346 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 395350 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 395352 */     // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] }))  =>  (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 395352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
     /* 395355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 395361 */     GIR_RootConstrainSelectedInstOperands,
     /* 395362 */     // GIR_Coverage, 14112,
     /* 395362 */     GIR_EraseRootFromParent_Done,
     /* 395363 */   // Label 7638: @395363
     /* 395363 */   GIM_Try, /*On fail goto*//*Label 7639*/ GIMT_Encode4(395379), // Rule ID 184 //
     /* 395368 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395372 */     // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 395372 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
     /* 395377 */     GIR_RootConstrainSelectedInstOperands,
     /* 395378 */     // GIR_Coverage, 184,
     /* 395378 */     GIR_Done,
     /* 395379 */   // Label 7639: @395379
     /* 395379 */   GIM_Reject,
     /* 395380 */ // Label 7636: @395380
     /* 395380 */ GIM_Reject,
     /* 395381 */ // Label 7628: @395381
     /* 395381 */ GIM_Try, /*On fail goto*//*Label 7640*/ GIMT_Encode4(395610),
     /* 395386 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 395389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395393 */   GIM_Try, /*On fail goto*//*Label 7641*/ GIMT_Encode4(395493), // Rule ID 4041 //
     /* 395398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 395406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 395410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 395414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 395418 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 395422 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 395426 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 395430 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 395434 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 395438 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 395442 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 395446 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 395450 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /* 395454 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 395458 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395463 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
     /* 395467 */     // MIs[3] Rn
     /* 395467 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /* 395472 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 395476 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 395480 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 395482 */     // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] }))  =>  (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 395482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
     /* 395485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /* 395491 */     GIR_RootConstrainSelectedInstOperands,
     /* 395492 */     // GIR_Coverage, 4041,
     /* 395492 */     GIR_EraseRootFromParent_Done,
     /* 395493 */   // Label 7641: @395493
     /* 395493 */   GIM_Try, /*On fail goto*//*Label 7642*/ GIMT_Encode4(395593), // Rule ID 14113 //
     /* 395498 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395502 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 395506 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 395510 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 395514 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 395518 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 395522 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 395526 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 395530 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 395534 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 395538 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 395542 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 395546 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395551 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 395555 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 395559 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 395563 */     // MIs[4] Rn
     /* 395563 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 395568 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
     /* 395572 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 395576 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 395580 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 395582 */     // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] }))  =>  (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 395582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
     /* 395585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 395587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 395591 */     GIR_RootConstrainSelectedInstOperands,
     /* 395592 */     // GIR_Coverage, 14113,
     /* 395592 */     GIR_EraseRootFromParent_Done,
     /* 395593 */   // Label 7642: @395593
     /* 395593 */   GIM_Try, /*On fail goto*//*Label 7643*/ GIMT_Encode4(395609), // Rule ID 185 //
     /* 395598 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395602 */     // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 395602 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
     /* 395607 */     GIR_RootConstrainSelectedInstOperands,
     /* 395608 */     // GIR_Coverage, 185,
     /* 395608 */     GIR_Done,
     /* 395609 */   // Label 7643: @395609
     /* 395609 */   GIM_Reject,
     /* 395610 */ // Label 7640: @395610
     /* 395610 */ GIM_Reject,
     /* 395611 */ // Label 7629: @395611
     /* 395611 */ GIM_Try, /*On fail goto*//*Label 7644*/ GIMT_Encode4(395637), // Rule ID 724 //
     /* 395616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395619 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 395622 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395626 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395630 */   // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 395630 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv2i32),
     /* 395635 */   GIR_RootConstrainSelectedInstOperands,
     /* 395636 */   // GIR_Coverage, 724,
     /* 395636 */   GIR_Done,
     /* 395637 */ // Label 7644: @395637
     /* 395637 */ GIM_Reject,
     /* 395638 */ // Label 7630: @395638
     /* 395638 */ GIM_Try, /*On fail goto*//*Label 7645*/ GIMT_Encode4(395664), // Rule ID 722 //
     /* 395643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395646 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 395649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395653 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395657 */   // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 395657 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i16),
     /* 395662 */   GIR_RootConstrainSelectedInstOperands,
     /* 395663 */   // GIR_Coverage, 722,
     /* 395663 */   GIR_Done,
     /* 395664 */ // Label 7645: @395664
     /* 395664 */ GIM_Reject,
     /* 395665 */ // Label 7631: @395665
     /* 395665 */ GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(395691), // Rule ID 725 //
     /* 395670 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395673 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 395676 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395680 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395684 */   // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 395684 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i32),
     /* 395689 */   GIR_RootConstrainSelectedInstOperands,
     /* 395690 */   // GIR_Coverage, 725,
     /* 395690 */   GIR_Done,
     /* 395691 */ // Label 7646: @395691
     /* 395691 */ GIM_Reject,
     /* 395692 */ // Label 7632: @395692
     /* 395692 */ GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(395718), // Rule ID 720 //
     /* 395697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 395703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395707 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395711 */   // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 395711 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i8),
     /* 395716 */   GIR_RootConstrainSelectedInstOperands,
     /* 395717 */   // GIR_Coverage, 720,
     /* 395717 */   GIR_Done,
     /* 395718 */ // Label 7647: @395718
     /* 395718 */ GIM_Reject,
     /* 395719 */ // Label 7633: @395719
     /* 395719 */ GIM_Try, /*On fail goto*//*Label 7648*/ GIMT_Encode4(395745), // Rule ID 723 //
     /* 395724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 395730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395734 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395738 */   // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 395738 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i16),
     /* 395743 */   GIR_RootConstrainSelectedInstOperands,
     /* 395744 */   // GIR_Coverage, 723,
     /* 395744 */   GIR_Done,
     /* 395745 */ // Label 7648: @395745
     /* 395745 */ GIM_Reject,
     /* 395746 */ // Label 7634: @395746
     /* 395746 */ GIM_Try, /*On fail goto*//*Label 7649*/ GIMT_Encode4(395772), // Rule ID 721 //
     /* 395751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395754 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 395757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395761 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395765 */   // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 395765 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv16i8),
     /* 395770 */   GIR_RootConstrainSelectedInstOperands,
     /* 395771 */   // GIR_Coverage, 721,
     /* 395771 */   GIR_Done,
     /* 395772 */ // Label 7649: @395772
     /* 395772 */ GIM_Reject,
     /* 395773 */ // Label 7635: @395773
     /* 395773 */ GIM_Reject,
     /* 395774 */ // Label 96: @395774
     /* 395774 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7654*/ GIMT_Encode4(395933),
     /* 395785 */ /*GILLT_s32*//*Label 7650*/ GIMT_Encode4(395825),
     /* 395789 */ /*GILLT_s64*//*Label 7651*/ GIMT_Encode4(395852), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 395813 */ /*GILLT_v8s8*//*Label 7652*/ GIMT_Encode4(395879), GIMT_Encode4(0),
     /* 395821 */ /*GILLT_v16s8*//*Label 7653*/ GIMT_Encode4(395906),
     /* 395825 */ // Label 7650: @395825
     /* 395825 */ GIM_Try, /*On fail goto*//*Label 7655*/ GIMT_Encode4(395851), // Rule ID 2323 //
     /* 395830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 395833 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 395836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395840 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395844 */   // (ctpop:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CNTWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 395844 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTWr),
     /* 395849 */   GIR_RootConstrainSelectedInstOperands,
     /* 395850 */   // GIR_Coverage, 2323,
     /* 395850 */   GIR_Done,
     /* 395851 */ // Label 7655: @395851
     /* 395851 */ GIM_Reject,
     /* 395852 */ // Label 7651: @395852
     /* 395852 */ GIM_Try, /*On fail goto*//*Label 7656*/ GIMT_Encode4(395878), // Rule ID 2324 //
     /* 395857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 395860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 395863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 395871 */   // (ctpop:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CNTXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 395871 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTXr),
     /* 395876 */   GIR_RootConstrainSelectedInstOperands,
     /* 395877 */   // GIR_Coverage, 2324,
     /* 395877 */   GIR_Done,
     /* 395878 */ // Label 7656: @395878
     /* 395878 */ GIM_Reject,
     /* 395879 */ // Label 7652: @395879
     /* 395879 */ GIM_Try, /*On fail goto*//*Label 7657*/ GIMT_Encode4(395905), // Rule ID 768 //
     /* 395884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395887 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 395890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395894 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395898 */   // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 395898 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv8i8),
     /* 395903 */   GIR_RootConstrainSelectedInstOperands,
     /* 395904 */   // GIR_Coverage, 768,
     /* 395904 */   GIR_Done,
     /* 395905 */ // Label 7657: @395905
     /* 395905 */ GIM_Reject,
     /* 395906 */ // Label 7653: @395906
     /* 395906 */ GIM_Try, /*On fail goto*//*Label 7658*/ GIMT_Encode4(395932), // Rule ID 769 //
     /* 395911 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 395914 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 395917 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395921 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395925 */   // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 395925 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv16i8),
     /* 395930 */   GIR_RootConstrainSelectedInstOperands,
     /* 395931 */   // GIR_Coverage, 769,
     /* 395931 */   GIR_Done,
     /* 395932 */ // Label 7658: @395932
     /* 395932 */ GIM_Reject,
     /* 395933 */ // Label 7654: @395933
     /* 395933 */ GIM_Reject,
     /* 395934 */ // Label 97: @395934
     /* 395934 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 7666*/ GIMT_Encode4(396247),
     /* 395945 */ /*GILLT_s32*//*Label 7659*/ GIMT_Encode4(395981),
     /* 395949 */ /*GILLT_s64*//*Label 7660*/ GIMT_Encode4(396054), GIMT_Encode4(0),
     /* 395957 */ /*GILLT_v2s32*//*Label 7661*/ GIMT_Encode4(396127),
     /* 395961 */ /*GILLT_v2s64*//*Label 7662*/ GIMT_Encode4(396151),
     /* 395965 */ /*GILLT_v4s16*//*Label 7663*/ GIMT_Encode4(396175),
     /* 395969 */ /*GILLT_v4s32*//*Label 7664*/ GIMT_Encode4(396199), GIMT_Encode4(0),
     /* 395977 */ /*GILLT_v8s16*//*Label 7665*/ GIMT_Encode4(396223),
     /* 395981 */ // Label 7659: @395981
     /* 395981 */ GIM_Try, /*On fail goto*//*Label 7667*/ GIMT_Encode4(396053),
     /* 395986 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 395989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395993 */   GIM_Try, /*On fail goto*//*Label 7668*/ GIMT_Encode4(396036), // Rule ID 4044 //
     /* 395998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
     /* 396006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 396010 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 396014 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 396019 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /* 396023 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 396025 */     // (bswap:{ *:[i32] } (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 16:{ *:[i64] }))  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 396025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 396028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 396030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 396034 */     GIR_RootConstrainSelectedInstOperands,
     /* 396035 */     // GIR_Coverage, 4044,
     /* 396035 */     GIR_EraseRootFromParent_Done,
     /* 396036 */   // Label 7668: @396036
     /* 396036 */   GIM_Try, /*On fail goto*//*Label 7669*/ GIMT_Encode4(396052), // Rule ID 189 //
     /* 396041 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 396045 */     // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 396045 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVWr),
     /* 396050 */     GIR_RootConstrainSelectedInstOperands,
     /* 396051 */     // GIR_Coverage, 189,
     /* 396051 */     GIR_Done,
     /* 396052 */   // Label 7669: @396052
     /* 396052 */   GIM_Reject,
     /* 396053 */ // Label 7667: @396053
     /* 396053 */ GIM_Reject,
     /* 396054 */ // Label 7660: @396054
     /* 396054 */ GIM_Try, /*On fail goto*//*Label 7670*/ GIMT_Encode4(396126),
     /* 396059 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 396062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 396066 */   GIM_Try, /*On fail goto*//*Label 7671*/ GIMT_Encode4(396109), // Rule ID 4045 //
     /* 396071 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396075 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
     /* 396079 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 396083 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 396087 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 396092 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 32,
     /* 396096 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 396098 */     // (bswap:{ *:[i64] } (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 32:{ *:[i64] }))  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 396098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 396101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 396103 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 396107 */     GIR_RootConstrainSelectedInstOperands,
     /* 396108 */     // GIR_Coverage, 4045,
     /* 396108 */     GIR_EraseRootFromParent_Done,
     /* 396109 */   // Label 7671: @396109
     /* 396109 */   GIM_Try, /*On fail goto*//*Label 7672*/ GIMT_Encode4(396125), // Rule ID 190 //
     /* 396114 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 396118 */     // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 396118 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVXr),
     /* 396123 */     GIR_RootConstrainSelectedInstOperands,
     /* 396124 */     // GIR_Coverage, 190,
     /* 396124 */     GIR_Done,
     /* 396125 */   // Label 7672: @396125
     /* 396125 */   GIM_Reject,
     /* 396126 */ // Label 7670: @396126
     /* 396126 */ GIM_Reject,
     /* 396127 */ // Label 7661: @396127
     /* 396127 */ GIM_Try, /*On fail goto*//*Label 7673*/ GIMT_Encode4(396150), // Rule ID 5057 //
     /* 396132 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 396135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396139 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396143 */   // (bswap:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (REV32v8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 396143 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 396148 */   GIR_RootConstrainSelectedInstOperands,
     /* 396149 */   // GIR_Coverage, 5057,
     /* 396149 */   GIR_Done,
     /* 396150 */ // Label 7673: @396150
     /* 396150 */ GIM_Reject,
     /* 396151 */ // Label 7662: @396151
     /* 396151 */ GIM_Try, /*On fail goto*//*Label 7674*/ GIMT_Encode4(396174), // Rule ID 5059 //
     /* 396156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 396159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396163 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396167 */   // (bswap:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)  =>  (REV64v16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 396167 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 396172 */   GIR_RootConstrainSelectedInstOperands,
     /* 396173 */   // GIR_Coverage, 5059,
     /* 396173 */   GIR_Done,
     /* 396174 */ // Label 7674: @396174
     /* 396174 */ GIM_Reject,
     /* 396175 */ // Label 7663: @396175
     /* 396175 */ GIM_Try, /*On fail goto*//*Label 7675*/ GIMT_Encode4(396198), // Rule ID 5055 //
     /* 396180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 396183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396187 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396191 */   // (bswap:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV16v8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 396191 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 396196 */   GIR_RootConstrainSelectedInstOperands,
     /* 396197 */   // GIR_Coverage, 5055,
     /* 396197 */   GIR_Done,
     /* 396198 */ // Label 7675: @396198
     /* 396198 */ GIM_Reject,
     /* 396199 */ // Label 7664: @396199
     /* 396199 */ GIM_Try, /*On fail goto*//*Label 7676*/ GIMT_Encode4(396222), // Rule ID 5058 //
     /* 396204 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 396207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396211 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396215 */   // (bswap:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (REV32v16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 396215 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 396220 */   GIR_RootConstrainSelectedInstOperands,
     /* 396221 */   // GIR_Coverage, 5058,
     /* 396221 */   GIR_Done,
     /* 396222 */ // Label 7676: @396222
     /* 396222 */ GIM_Reject,
     /* 396223 */ // Label 7665: @396223
     /* 396223 */ GIM_Try, /*On fail goto*//*Label 7677*/ GIMT_Encode4(396246), // Rule ID 5056 //
     /* 396228 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 396231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396235 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396239 */   // (bswap:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV16v16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 396239 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 396244 */   GIR_RootConstrainSelectedInstOperands,
     /* 396245 */   // GIR_Coverage, 5056,
     /* 396245 */   GIR_Done,
     /* 396246 */ // Label 7677: @396246
     /* 396246 */ GIM_Reject,
     /* 396247 */ // Label 7666: @396247
     /* 396247 */ GIM_Reject,
     /* 396248 */ // Label 98: @396248
     /* 396248 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7682*/ GIMT_Encode4(396401),
     /* 396259 */ /*GILLT_s32*//*Label 7678*/ GIMT_Encode4(396299),
     /* 396263 */ /*GILLT_s64*//*Label 7679*/ GIMT_Encode4(396323), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 396287 */ /*GILLT_v8s8*//*Label 7680*/ GIMT_Encode4(396347), GIMT_Encode4(0),
     /* 396295 */ /*GILLT_v16s8*//*Label 7681*/ GIMT_Encode4(396374),
     /* 396299 */ // Label 7678: @396299
     /* 396299 */ GIM_Try, /*On fail goto*//*Label 7683*/ GIMT_Encode4(396322), // Rule ID 186 //
     /* 396304 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 396307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 396311 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 396315 */   // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 396315 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
     /* 396320 */   GIR_RootConstrainSelectedInstOperands,
     /* 396321 */   // GIR_Coverage, 186,
     /* 396321 */   GIR_Done,
     /* 396322 */ // Label 7683: @396322
     /* 396322 */ GIM_Reject,
     /* 396323 */ // Label 7679: @396323
     /* 396323 */ GIM_Try, /*On fail goto*//*Label 7684*/ GIMT_Encode4(396346), // Rule ID 187 //
     /* 396328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 396331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 396335 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 396339 */   // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 396339 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
     /* 396344 */   GIR_RootConstrainSelectedInstOperands,
     /* 396345 */   // GIR_Coverage, 187,
     /* 396345 */   GIR_Done,
     /* 396346 */ // Label 7684: @396346
     /* 396346 */ GIM_Reject,
     /* 396347 */ // Label 7680: @396347
     /* 396347 */ GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(396373), // Rule ID 978 //
     /* 396352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 396355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 396358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396362 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396366 */   // (bitreverse:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 396366 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv8i8),
     /* 396371 */   GIR_RootConstrainSelectedInstOperands,
     /* 396372 */   // GIR_Coverage, 978,
     /* 396372 */   GIR_Done,
     /* 396373 */ // Label 7685: @396373
     /* 396373 */ GIM_Reject,
     /* 396374 */ // Label 7681: @396374
     /* 396374 */ GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(396400), // Rule ID 979 //
     /* 396379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 396382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 396385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396393 */   // (bitreverse:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 396393 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv16i8),
     /* 396398 */   GIR_RootConstrainSelectedInstOperands,
     /* 396399 */   // GIR_Coverage, 979,
     /* 396399 */   GIR_Done,
     /* 396400 */ // Label 7686: @396400
     /* 396400 */ GIM_Reject,
     /* 396401 */ // Label 7682: @396401
     /* 396401 */ GIM_Reject,
     /* 396402 */ // Label 99: @396402
     /* 396402 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7695*/ GIMT_Encode4(396892),
     /* 396413 */ /*GILLT_s16*//*Label 7687*/ GIMT_Encode4(396453),
     /* 396417 */ /*GILLT_s32*//*Label 7688*/ GIMT_Encode4(396484),
     /* 396421 */ /*GILLT_s64*//*Label 7689*/ GIMT_Encode4(396515), GIMT_Encode4(0),
     /* 396429 */ /*GILLT_v2s32*//*Label 7690*/ GIMT_Encode4(396546),
     /* 396433 */ /*GILLT_v2s64*//*Label 7691*/ GIMT_Encode4(396577),
     /* 396437 */ /*GILLT_v4s16*//*Label 7692*/ GIMT_Encode4(396608),
     /* 396441 */ /*GILLT_v4s32*//*Label 7693*/ GIMT_Encode4(396639), GIMT_Encode4(0),
     /* 396449 */ /*GILLT_v8s16*//*Label 7694*/ GIMT_Encode4(396670),
     /* 396453 */ // Label 7687: @396453
     /* 396453 */ GIM_Try, /*On fail goto*//*Label 7696*/ GIMT_Encode4(396483), // Rule ID 556 //
     /* 396458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 396461 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 396464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 396468 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 396472 */   // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 396472 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPHr),
     /* 396477 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396481 */   GIR_RootConstrainSelectedInstOperands,
     /* 396482 */   // GIR_Coverage, 556,
     /* 396482 */   GIR_Done,
     /* 396483 */ // Label 7696: @396483
     /* 396483 */ GIM_Reject,
     /* 396484 */ // Label 7688: @396484
     /* 396484 */ GIM_Try, /*On fail goto*//*Label 7697*/ GIMT_Encode4(396514), // Rule ID 558 //
     /* 396489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 396492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 396495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396499 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396503 */   // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 396503 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPSr),
     /* 396508 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396512 */   GIR_RootConstrainSelectedInstOperands,
     /* 396513 */   // GIR_Coverage, 558,
     /* 396513 */   GIR_Done,
     /* 396514 */ // Label 7697: @396514
     /* 396514 */ GIM_Reject,
     /* 396515 */ // Label 7689: @396515
     /* 396515 */ GIM_Try, /*On fail goto*//*Label 7698*/ GIMT_Encode4(396545), // Rule ID 560 //
     /* 396520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 396523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 396526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396534 */   // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 396534 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPDr),
     /* 396539 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396543 */   GIR_RootConstrainSelectedInstOperands,
     /* 396544 */   // GIR_Coverage, 560,
     /* 396544 */   GIR_Done,
     /* 396545 */ // Label 7698: @396545
     /* 396545 */ GIM_Reject,
     /* 396546 */ // Label 7690: @396546
     /* 396546 */ GIM_Try, /*On fail goto*//*Label 7699*/ GIMT_Encode4(396576), // Rule ID 917 //
     /* 396551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 396554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 396557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396565 */   // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 396565 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f32),
     /* 396570 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396574 */   GIR_RootConstrainSelectedInstOperands,
     /* 396575 */   // GIR_Coverage, 917,
     /* 396575 */   GIR_Done,
     /* 396576 */ // Label 7699: @396576
     /* 396576 */ GIM_Reject,
     /* 396577 */ // Label 7691: @396577
     /* 396577 */ GIM_Try, /*On fail goto*//*Label 7700*/ GIMT_Encode4(396607), // Rule ID 921 //
     /* 396582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 396585 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 396588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396592 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396596 */   // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 396596 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f64),
     /* 396601 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396605 */   GIR_RootConstrainSelectedInstOperands,
     /* 396606 */   // GIR_Coverage, 921,
     /* 396606 */   GIR_Done,
     /* 396607 */ // Label 7700: @396607
     /* 396607 */ GIM_Reject,
     /* 396608 */ // Label 7692: @396608
     /* 396608 */ GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(396638), // Rule ID 913 //
     /* 396613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 396616 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 396619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396623 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396627 */   // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 396627 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f16),
     /* 396632 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396636 */   GIR_RootConstrainSelectedInstOperands,
     /* 396637 */   // GIR_Coverage, 913,
     /* 396637 */   GIR_Done,
     /* 396638 */ // Label 7701: @396638
     /* 396638 */ GIM_Reject,
     /* 396639 */ // Label 7693: @396639
     /* 396639 */ GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(396669), // Rule ID 919 //
     /* 396644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 396647 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 396650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396654 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396658 */   // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 396658 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 396663 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396667 */   GIR_RootConstrainSelectedInstOperands,
     /* 396668 */   // GIR_Coverage, 919,
     /* 396668 */   GIR_Done,
     /* 396669 */ // Label 7702: @396669
     /* 396669 */ GIM_Reject,
     /* 396670 */ // Label 7694: @396670
     /* 396670 */ GIM_Try, /*On fail goto*//*Label 7703*/ GIMT_Encode4(396891),
     /* 396675 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 396678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396682 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396686 */   GIM_Try, /*On fail goto*//*Label 7704*/ GIMT_Encode4(396705), // Rule ID 915 //
     /* 396691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 396694 */     // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 396694 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv8f16),
     /* 396699 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396703 */     GIR_RootConstrainSelectedInstOperands,
     /* 396704 */     // GIR_Coverage, 915,
     /* 396704 */     GIR_Done,
     /* 396705 */   // Label 7704: @396705
     /* 396705 */   GIM_Try, /*On fail goto*//*Label 7705*/ GIMT_Encode4(396890), // Rule ID 7076 //
     /* 396710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 396713 */     // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTPv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTPv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 396713 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 396716 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 396720 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396725 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 396729 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 396731 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 396734 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 396738 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396743 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 396746 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 396748 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 396751 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 396755 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396760 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 396766 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396771 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396776 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 396779 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 396783 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396788 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 396791 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 396793 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 396796 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 396800 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396805 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 396808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 396810 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 396813 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 396817 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396822 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 396825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 396827 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 396830 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 396834 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396839 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 396841 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 396844 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 396848 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396853 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 396856 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 396859 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 396862 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396867 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396872 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 396877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 396880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396882 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396885 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 396888 */     GIR_RootConstrainSelectedInstOperands,
     /* 396889 */     // GIR_Coverage, 7076,
     /* 396889 */     GIR_EraseRootFromParent_Done,
     /* 396890 */   // Label 7705: @396890
     /* 396890 */   GIM_Reject,
     /* 396891 */ // Label 7703: @396891
     /* 396891 */ GIM_Reject,
     /* 396892 */ // Label 7695: @396892
     /* 396892 */ GIM_Reject,
     /* 396893 */ // Label 100: @396893
     /* 396893 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7714*/ GIMT_Encode4(397192),
     /* 396904 */ /*GILLT_s16*//*Label 7706*/ GIMT_Encode4(396944),
     /* 396908 */ /*GILLT_s32*//*Label 7707*/ GIMT_Encode4(396975),
     /* 396912 */ /*GILLT_s64*//*Label 7708*/ GIMT_Encode4(397006), GIMT_Encode4(0),
     /* 396920 */ /*GILLT_v2s32*//*Label 7709*/ GIMT_Encode4(397037),
     /* 396924 */ /*GILLT_v2s64*//*Label 7710*/ GIMT_Encode4(397068),
     /* 396928 */ /*GILLT_v4s16*//*Label 7711*/ GIMT_Encode4(397099),
     /* 396932 */ /*GILLT_v4s32*//*Label 7712*/ GIMT_Encode4(397130), GIMT_Encode4(0),
     /* 396940 */ /*GILLT_v8s16*//*Label 7713*/ GIMT_Encode4(397161),
     /* 396944 */ // Label 7706: @396944
     /* 396944 */ GIM_Try, /*On fail goto*//*Label 7715*/ GIMT_Encode4(396974), // Rule ID 574 //
     /* 396949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 396952 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 396955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 396959 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 396963 */   // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 396963 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
     /* 396968 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 396972 */   GIR_RootConstrainSelectedInstOperands,
     /* 396973 */   // GIR_Coverage, 574,
     /* 396973 */   GIR_Done,
     /* 396974 */ // Label 7715: @396974
     /* 396974 */ GIM_Reject,
     /* 396975 */ // Label 7707: @396975
     /* 396975 */ GIM_Try, /*On fail goto*//*Label 7716*/ GIMT_Encode4(397005), // Rule ID 576 //
     /* 396980 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 396983 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 396986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396990 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396994 */   // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 396994 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
     /* 396999 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397003 */   GIR_RootConstrainSelectedInstOperands,
     /* 397004 */   // GIR_Coverage, 576,
     /* 397004 */   GIR_Done,
     /* 397005 */ // Label 7716: @397005
     /* 397005 */ GIM_Reject,
     /* 397006 */ // Label 7708: @397006
     /* 397006 */ GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(397036), // Rule ID 578 //
     /* 397011 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 397014 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 397017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397021 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397025 */   // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 397025 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
     /* 397030 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397034 */   GIR_RootConstrainSelectedInstOperands,
     /* 397035 */   // GIR_Coverage, 578,
     /* 397035 */   GIR_Done,
     /* 397036 */ // Label 7717: @397036
     /* 397036 */ GIM_Reject,
     /* 397037 */ // Label 7709: @397037
     /* 397037 */ GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(397067), // Rule ID 964 //
     /* 397042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 397048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397052 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397056 */   // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 397056 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
     /* 397061 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397065 */   GIR_RootConstrainSelectedInstOperands,
     /* 397066 */   // GIR_Coverage, 964,
     /* 397066 */   GIR_Done,
     /* 397067 */ // Label 7718: @397067
     /* 397067 */ GIM_Reject,
     /* 397068 */ // Label 7710: @397068
     /* 397068 */ GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(397098), // Rule ID 968 //
     /* 397073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397076 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 397079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397083 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397087 */   // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 397087 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
     /* 397092 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397096 */   GIR_RootConstrainSelectedInstOperands,
     /* 397097 */   // GIR_Coverage, 968,
     /* 397097 */   GIR_Done,
     /* 397098 */ // Label 7719: @397098
     /* 397098 */ GIM_Reject,
     /* 397099 */ // Label 7711: @397099
     /* 397099 */ GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(397129), // Rule ID 960 //
     /* 397104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397107 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 397110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397114 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397118 */   // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 397118 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
     /* 397123 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397127 */   GIR_RootConstrainSelectedInstOperands,
     /* 397128 */   // GIR_Coverage, 960,
     /* 397128 */   GIR_Done,
     /* 397129 */ // Label 7720: @397129
     /* 397129 */ GIM_Reject,
     /* 397130 */ // Label 7712: @397130
     /* 397130 */ GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(397160), // Rule ID 966 //
     /* 397135 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397138 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397141 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397145 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397149 */   // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 397149 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
     /* 397154 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397158 */   GIR_RootConstrainSelectedInstOperands,
     /* 397159 */   // GIR_Coverage, 966,
     /* 397159 */   GIR_Done,
     /* 397160 */ // Label 7721: @397160
     /* 397160 */ GIM_Reject,
     /* 397161 */ // Label 7713: @397161
     /* 397161 */ GIM_Try, /*On fail goto*//*Label 7722*/ GIMT_Encode4(397191), // Rule ID 962 //
     /* 397166 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397169 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 397172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397176 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397180 */   // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 397180 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
     /* 397185 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397189 */   GIR_RootConstrainSelectedInstOperands,
     /* 397190 */   // GIR_Coverage, 962,
     /* 397190 */   GIR_Done,
     /* 397191 */ // Label 7722: @397191
     /* 397191 */ GIM_Reject,
     /* 397192 */ // Label 7714: @397192
     /* 397192 */ GIM_Reject,
     /* 397193 */ // Label 101: @397193
     /* 397193 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7731*/ GIMT_Encode4(397683),
     /* 397204 */ /*GILLT_s16*//*Label 7723*/ GIMT_Encode4(397244),
     /* 397208 */ /*GILLT_s32*//*Label 7724*/ GIMT_Encode4(397275),
     /* 397212 */ /*GILLT_s64*//*Label 7725*/ GIMT_Encode4(397306), GIMT_Encode4(0),
     /* 397220 */ /*GILLT_v2s32*//*Label 7726*/ GIMT_Encode4(397337),
     /* 397224 */ /*GILLT_v2s64*//*Label 7727*/ GIMT_Encode4(397368),
     /* 397228 */ /*GILLT_v4s16*//*Label 7728*/ GIMT_Encode4(397399),
     /* 397232 */ /*GILLT_v4s32*//*Label 7729*/ GIMT_Encode4(397430), GIMT_Encode4(0),
     /* 397240 */ /*GILLT_v8s16*//*Label 7730*/ GIMT_Encode4(397461),
     /* 397244 */ // Label 7723: @397244
     /* 397244 */ GIM_Try, /*On fail goto*//*Label 7732*/ GIMT_Encode4(397274), // Rule ID 544 //
     /* 397249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 397252 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 397255 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 397259 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 397263 */   // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 397263 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMHr),
     /* 397268 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397272 */   GIR_RootConstrainSelectedInstOperands,
     /* 397273 */   // GIR_Coverage, 544,
     /* 397273 */   GIR_Done,
     /* 397274 */ // Label 7732: @397274
     /* 397274 */ GIM_Reject,
     /* 397275 */ // Label 7724: @397275
     /* 397275 */ GIM_Try, /*On fail goto*//*Label 7733*/ GIMT_Encode4(397305), // Rule ID 546 //
     /* 397280 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 397283 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 397286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397290 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397294 */   // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 397294 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMSr),
     /* 397299 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397303 */   GIR_RootConstrainSelectedInstOperands,
     /* 397304 */   // GIR_Coverage, 546,
     /* 397304 */   GIR_Done,
     /* 397305 */ // Label 7733: @397305
     /* 397305 */ GIM_Reject,
     /* 397306 */ // Label 7725: @397306
     /* 397306 */ GIM_Try, /*On fail goto*//*Label 7734*/ GIMT_Encode4(397336), // Rule ID 548 //
     /* 397311 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 397314 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 397317 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397321 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397325 */   // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 397325 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMDr),
     /* 397330 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397334 */   GIR_RootConstrainSelectedInstOperands,
     /* 397335 */   // GIR_Coverage, 548,
     /* 397335 */   GIR_Done,
     /* 397336 */ // Label 7734: @397336
     /* 397336 */ GIM_Reject,
     /* 397337 */ // Label 7726: @397337
     /* 397337 */ GIM_Try, /*On fail goto*//*Label 7735*/ GIMT_Encode4(397367), // Rule ID 897 //
     /* 397342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397345 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 397348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397352 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397356 */   // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 397356 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f32),
     /* 397361 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397365 */   GIR_RootConstrainSelectedInstOperands,
     /* 397366 */   // GIR_Coverage, 897,
     /* 397366 */   GIR_Done,
     /* 397367 */ // Label 7735: @397367
     /* 397367 */ GIM_Reject,
     /* 397368 */ // Label 7727: @397368
     /* 397368 */ GIM_Try, /*On fail goto*//*Label 7736*/ GIMT_Encode4(397398), // Rule ID 901 //
     /* 397373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397376 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 397379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397383 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397387 */   // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 397387 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f64),
     /* 397392 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397396 */   GIR_RootConstrainSelectedInstOperands,
     /* 397397 */   // GIR_Coverage, 901,
     /* 397397 */   GIR_Done,
     /* 397398 */ // Label 7736: @397398
     /* 397398 */ GIM_Reject,
     /* 397399 */ // Label 7728: @397399
     /* 397399 */ GIM_Try, /*On fail goto*//*Label 7737*/ GIMT_Encode4(397429), // Rule ID 893 //
     /* 397404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397407 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 397410 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397414 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397418 */   // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 397418 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f16),
     /* 397423 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397427 */   GIR_RootConstrainSelectedInstOperands,
     /* 397428 */   // GIR_Coverage, 893,
     /* 397428 */   GIR_Done,
     /* 397429 */ // Label 7737: @397429
     /* 397429 */ GIM_Reject,
     /* 397430 */ // Label 7729: @397430
     /* 397430 */ GIM_Try, /*On fail goto*//*Label 7738*/ GIMT_Encode4(397460), // Rule ID 899 //
     /* 397435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397445 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397449 */   // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 397449 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 397454 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397458 */   GIR_RootConstrainSelectedInstOperands,
     /* 397459 */   // GIR_Coverage, 899,
     /* 397459 */   GIR_Done,
     /* 397460 */ // Label 7738: @397460
     /* 397460 */ GIM_Reject,
     /* 397461 */ // Label 7730: @397461
     /* 397461 */ GIM_Try, /*On fail goto*//*Label 7739*/ GIMT_Encode4(397682),
     /* 397466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 397469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397477 */   GIM_Try, /*On fail goto*//*Label 7740*/ GIMT_Encode4(397496), // Rule ID 895 //
     /* 397482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397485 */     // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 397485 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv8f16),
     /* 397490 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397494 */     GIR_RootConstrainSelectedInstOperands,
     /* 397495 */     // GIR_Coverage, 895,
     /* 397495 */     GIR_Done,
     /* 397496 */   // Label 7740: @397496
     /* 397496 */   GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(397681), // Rule ID 7078 //
     /* 397501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 397504 */     // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTMv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTMv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 397504 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 397507 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 397511 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397516 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 397520 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 397522 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 397525 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 397529 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397534 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 397537 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 397539 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 397542 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 397546 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397551 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 397557 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397562 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397567 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 397570 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 397574 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397579 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 397582 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 397584 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 397587 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 397591 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397596 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 397599 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 397601 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 397604 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 397608 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397613 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 397616 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 397618 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 397621 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 397625 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397630 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 397632 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 397635 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 397639 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397644 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 397647 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 397650 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 397653 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397658 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397663 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 397671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397676 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 397679 */     GIR_RootConstrainSelectedInstOperands,
     /* 397680 */     // GIR_Coverage, 7078,
     /* 397680 */     GIR_EraseRootFromParent_Done,
     /* 397681 */   // Label 7741: @397681
     /* 397681 */   GIM_Reject,
     /* 397682 */ // Label 7739: @397682
     /* 397682 */ GIM_Reject,
     /* 397683 */ // Label 7731: @397683
     /* 397683 */ GIM_Reject,
     /* 397684 */ // Label 102: @397684
     /* 397684 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7750*/ GIMT_Encode4(398174),
     /* 397695 */ /*GILLT_s16*//*Label 7742*/ GIMT_Encode4(397735),
     /* 397699 */ /*GILLT_s32*//*Label 7743*/ GIMT_Encode4(397766),
     /* 397703 */ /*GILLT_s64*//*Label 7744*/ GIMT_Encode4(397797), GIMT_Encode4(0),
     /* 397711 */ /*GILLT_v2s32*//*Label 7745*/ GIMT_Encode4(397828),
     /* 397715 */ /*GILLT_v2s64*//*Label 7746*/ GIMT_Encode4(397859),
     /* 397719 */ /*GILLT_v4s16*//*Label 7747*/ GIMT_Encode4(397890),
     /* 397723 */ /*GILLT_v4s32*//*Label 7748*/ GIMT_Encode4(397921), GIMT_Encode4(0),
     /* 397731 */ /*GILLT_v8s16*//*Label 7749*/ GIMT_Encode4(397952),
     /* 397735 */ // Label 7742: @397735
     /* 397735 */ GIM_Try, /*On fail goto*//*Label 7751*/ GIMT_Encode4(397765), // Rule ID 562 //
     /* 397740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 397743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 397746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 397750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 397754 */   // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 397754 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 397759 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397763 */   GIR_RootConstrainSelectedInstOperands,
     /* 397764 */   // GIR_Coverage, 562,
     /* 397764 */   GIR_Done,
     /* 397765 */ // Label 7751: @397765
     /* 397765 */ GIM_Reject,
     /* 397766 */ // Label 7743: @397766
     /* 397766 */ GIM_Try, /*On fail goto*//*Label 7752*/ GIMT_Encode4(397796), // Rule ID 564 //
     /* 397771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 397774 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 397777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397781 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397785 */   // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 397785 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 397790 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397794 */   GIR_RootConstrainSelectedInstOperands,
     /* 397795 */   // GIR_Coverage, 564,
     /* 397795 */   GIR_Done,
     /* 397796 */ // Label 7752: @397796
     /* 397796 */ GIM_Reject,
     /* 397797 */ // Label 7744: @397797
     /* 397797 */ GIM_Try, /*On fail goto*//*Label 7753*/ GIMT_Encode4(397827), // Rule ID 566 //
     /* 397802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 397805 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 397808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397812 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397816 */   // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 397816 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 397821 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397825 */   GIR_RootConstrainSelectedInstOperands,
     /* 397826 */   // GIR_Coverage, 566,
     /* 397826 */   GIR_Done,
     /* 397827 */ // Label 7753: @397827
     /* 397827 */ GIM_Reject,
     /* 397828 */ // Label 7745: @397828
     /* 397828 */ GIM_Try, /*On fail goto*//*Label 7754*/ GIMT_Encode4(397858), // Rule ID 927 //
     /* 397833 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 397839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397843 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397847 */   // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 397847 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f32),
     /* 397852 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397856 */   GIR_RootConstrainSelectedInstOperands,
     /* 397857 */   // GIR_Coverage, 927,
     /* 397857 */   GIR_Done,
     /* 397858 */ // Label 7754: @397858
     /* 397858 */ GIM_Reject,
     /* 397859 */ // Label 7746: @397859
     /* 397859 */ GIM_Try, /*On fail goto*//*Label 7755*/ GIMT_Encode4(397889), // Rule ID 931 //
     /* 397864 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397867 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 397870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397874 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397878 */   // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 397878 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f64),
     /* 397883 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397887 */   GIR_RootConstrainSelectedInstOperands,
     /* 397888 */   // GIR_Coverage, 931,
     /* 397888 */   GIR_Done,
     /* 397889 */ // Label 7755: @397889
     /* 397889 */ GIM_Reject,
     /* 397890 */ // Label 7747: @397890
     /* 397890 */ GIM_Try, /*On fail goto*//*Label 7756*/ GIMT_Encode4(397920), // Rule ID 923 //
     /* 397895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 397901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397905 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397909 */   // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 397909 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f16),
     /* 397914 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397918 */   GIR_RootConstrainSelectedInstOperands,
     /* 397919 */   // GIR_Coverage, 923,
     /* 397919 */   GIR_Done,
     /* 397920 */ // Label 7756: @397920
     /* 397920 */ GIM_Reject,
     /* 397921 */ // Label 7748: @397921
     /* 397921 */ GIM_Try, /*On fail goto*//*Label 7757*/ GIMT_Encode4(397951), // Rule ID 929 //
     /* 397926 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397929 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397936 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397940 */   // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 397940 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 397945 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397949 */   GIR_RootConstrainSelectedInstOperands,
     /* 397950 */   // GIR_Coverage, 929,
     /* 397950 */   GIR_Done,
     /* 397951 */ // Label 7757: @397951
     /* 397951 */ GIM_Reject,
     /* 397952 */ // Label 7749: @397952
     /* 397952 */ GIM_Try, /*On fail goto*//*Label 7758*/ GIMT_Encode4(398173),
     /* 397957 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 397960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397964 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397968 */   GIM_Try, /*On fail goto*//*Label 7759*/ GIMT_Encode4(397987), // Rule ID 925 //
     /* 397973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 397976 */     // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 397976 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv8f16),
     /* 397981 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 397985 */     GIR_RootConstrainSelectedInstOperands,
     /* 397986 */     // GIR_Coverage, 925,
     /* 397986 */     GIR_Done,
     /* 397987 */   // Label 7759: @397987
     /* 397987 */   GIM_Try, /*On fail goto*//*Label 7760*/ GIMT_Encode4(398172), // Rule ID 7086 //
     /* 397992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 397995 */     // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTXv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTXv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 397995 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 397998 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 398002 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398007 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 398011 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 398013 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 398016 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 398020 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398025 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 398028 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 398030 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 398033 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 398037 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398042 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 398048 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398053 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398058 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 398061 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 398065 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398070 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 398073 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 398075 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 398078 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 398082 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398087 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 398090 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 398092 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 398095 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 398099 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398104 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 398107 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 398109 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 398112 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 398116 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398121 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 398123 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 398126 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 398130 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398135 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 398138 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 398141 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 398144 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398149 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398154 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 398162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398164 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398167 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 398170 */     GIR_RootConstrainSelectedInstOperands,
     /* 398171 */     // GIR_Coverage, 7086,
     /* 398171 */     GIR_EraseRootFromParent_Done,
     /* 398172 */   // Label 7760: @398172
     /* 398172 */   GIM_Reject,
     /* 398173 */ // Label 7758: @398173
     /* 398173 */ GIM_Reject,
     /* 398174 */ // Label 7750: @398174
     /* 398174 */ GIM_Reject,
     /* 398175 */ // Label 103: @398175
     /* 398175 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7769*/ GIMT_Encode4(398665),
     /* 398186 */ /*GILLT_s16*//*Label 7761*/ GIMT_Encode4(398226),
     /* 398190 */ /*GILLT_s32*//*Label 7762*/ GIMT_Encode4(398257),
     /* 398194 */ /*GILLT_s64*//*Label 7763*/ GIMT_Encode4(398288), GIMT_Encode4(0),
     /* 398202 */ /*GILLT_v2s32*//*Label 7764*/ GIMT_Encode4(398319),
     /* 398206 */ /*GILLT_v2s64*//*Label 7765*/ GIMT_Encode4(398350),
     /* 398210 */ /*GILLT_v4s16*//*Label 7766*/ GIMT_Encode4(398381),
     /* 398214 */ /*GILLT_v4s32*//*Label 7767*/ GIMT_Encode4(398412), GIMT_Encode4(0),
     /* 398222 */ /*GILLT_v8s16*//*Label 7768*/ GIMT_Encode4(398443),
     /* 398226 */ // Label 7761: @398226
     /* 398226 */ GIM_Try, /*On fail goto*//*Label 7770*/ GIMT_Encode4(398256), // Rule ID 538 //
     /* 398231 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 398234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 398237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 398241 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 398245 */   // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 398245 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIHr),
     /* 398250 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398254 */   GIR_RootConstrainSelectedInstOperands,
     /* 398255 */   // GIR_Coverage, 538,
     /* 398255 */   GIR_Done,
     /* 398256 */ // Label 7770: @398256
     /* 398256 */ GIM_Reject,
     /* 398257 */ // Label 7762: @398257
     /* 398257 */ GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(398287), // Rule ID 540 //
     /* 398262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 398265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 398268 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398272 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398276 */   // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 398276 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTISr),
     /* 398281 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398285 */   GIR_RootConstrainSelectedInstOperands,
     /* 398286 */   // GIR_Coverage, 540,
     /* 398286 */   GIR_Done,
     /* 398287 */ // Label 7771: @398287
     /* 398287 */ GIM_Reject,
     /* 398288 */ // Label 7763: @398288
     /* 398288 */ GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(398318), // Rule ID 542 //
     /* 398293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 398296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 398299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398303 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398307 */   // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 398307 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIDr),
     /* 398312 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398316 */   GIR_RootConstrainSelectedInstOperands,
     /* 398317 */   // GIR_Coverage, 542,
     /* 398317 */   GIR_Done,
     /* 398318 */ // Label 7772: @398318
     /* 398318 */ GIM_Reject,
     /* 398319 */ // Label 7764: @398319
     /* 398319 */ GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(398349), // Rule ID 887 //
     /* 398324 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 398327 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 398330 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398334 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398338 */   // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 398338 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f32),
     /* 398343 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398347 */   GIR_RootConstrainSelectedInstOperands,
     /* 398348 */   // GIR_Coverage, 887,
     /* 398348 */   GIR_Done,
     /* 398349 */ // Label 7773: @398349
     /* 398349 */ GIM_Reject,
     /* 398350 */ // Label 7765: @398350
     /* 398350 */ GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(398380), // Rule ID 891 //
     /* 398355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 398358 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 398361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398365 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398369 */   // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 398369 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f64),
     /* 398374 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398378 */   GIR_RootConstrainSelectedInstOperands,
     /* 398379 */   // GIR_Coverage, 891,
     /* 398379 */   GIR_Done,
     /* 398380 */ // Label 7774: @398380
     /* 398380 */ GIM_Reject,
     /* 398381 */ // Label 7766: @398381
     /* 398381 */ GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(398411), // Rule ID 883 //
     /* 398386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 398389 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 398392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398396 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398400 */   // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 398400 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f16),
     /* 398405 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398409 */   GIR_RootConstrainSelectedInstOperands,
     /* 398410 */   // GIR_Coverage, 883,
     /* 398410 */   GIR_Done,
     /* 398411 */ // Label 7775: @398411
     /* 398411 */ GIM_Reject,
     /* 398412 */ // Label 7767: @398412
     /* 398412 */ GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(398442), // Rule ID 889 //
     /* 398417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 398420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 398423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398431 */   // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 398431 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 398436 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398440 */   GIR_RootConstrainSelectedInstOperands,
     /* 398441 */   // GIR_Coverage, 889,
     /* 398441 */   GIR_Done,
     /* 398442 */ // Label 7776: @398442
     /* 398442 */ GIM_Reject,
     /* 398443 */ // Label 7768: @398443
     /* 398443 */ GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(398664),
     /* 398448 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 398451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398455 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398459 */   GIM_Try, /*On fail goto*//*Label 7778*/ GIMT_Encode4(398478), // Rule ID 885 //
     /* 398464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 398467 */     // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 398467 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv8f16),
     /* 398472 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398476 */     GIR_RootConstrainSelectedInstOperands,
     /* 398477 */     // GIR_Coverage, 885,
     /* 398477 */     GIR_Done,
     /* 398478 */   // Label 7778: @398478
     /* 398478 */   GIM_Try, /*On fail goto*//*Label 7779*/ GIMT_Encode4(398663), // Rule ID 7080 //
     /* 398483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 398486 */     // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTIv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTIv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 398486 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 398489 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 398493 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398498 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 398502 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 398504 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 398507 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 398511 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398516 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 398519 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 398521 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 398524 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 398528 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398533 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 398539 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398544 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398549 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 398552 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 398556 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398561 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 398564 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 398566 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 398569 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 398573 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398578 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 398581 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 398583 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 398586 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 398590 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398595 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 398598 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 398600 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 398603 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 398607 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398612 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 398614 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 398617 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 398621 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398626 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 398629 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 398632 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 398635 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398640 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398645 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 398653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398655 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398658 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 398661 */     GIR_RootConstrainSelectedInstOperands,
     /* 398662 */     // GIR_Coverage, 7080,
     /* 398662 */     GIR_EraseRootFromParent_Done,
     /* 398663 */   // Label 7779: @398663
     /* 398663 */   GIM_Reject,
     /* 398664 */ // Label 7777: @398664
     /* 398664 */ GIM_Reject,
     /* 398665 */ // Label 7769: @398665
     /* 398665 */ GIM_Reject,
     /* 398666 */ // Label 104: @398666
     /* 398666 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7788*/ GIMT_Encode4(399791),
     /* 398677 */ /*GILLT_s16*//*Label 7780*/ GIMT_Encode4(398717),
     /* 398681 */ /*GILLT_s32*//*Label 7781*/ GIMT_Encode4(398943),
     /* 398685 */ /*GILLT_s64*//*Label 7782*/ GIMT_Encode4(399169), GIMT_Encode4(0),
     /* 398693 */ /*GILLT_v2s32*//*Label 7783*/ GIMT_Encode4(399341),
     /* 398697 */ /*GILLT_v2s64*//*Label 7784*/ GIMT_Encode4(399379),
     /* 398701 */ /*GILLT_v4s16*//*Label 7785*/ GIMT_Encode4(399417),
     /* 398705 */ /*GILLT_v4s32*//*Label 7786*/ GIMT_Encode4(399455), GIMT_Encode4(0),
     /* 398713 */ /*GILLT_v8s16*//*Label 7787*/ GIMT_Encode4(399493),
     /* 398717 */ // Label 7780: @398717
     /* 398717 */ GIM_Try, /*On fail goto*//*Label 7789*/ GIMT_Encode4(398942),
     /* 398722 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 398725 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 398728 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 398732 */   GIM_Try, /*On fail goto*//*Label 7790*/ GIMT_Encode4(398823), // Rule ID 6994 //
     /* 398737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 398749 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 398753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398758 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 398762 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398766 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398770 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 398774 */     // MIs[2] Rn
     /* 398774 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 398779 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 398783 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398785 */     // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 398785 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 398788 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 398792 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398797 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 398803 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398808 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 398816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 398818 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398821 */     GIR_RootConstrainSelectedInstOperands,
     /* 398822 */     // GIR_Coverage, 6994,
     /* 398822 */     GIR_EraseRootFromParent_Done,
     /* 398823 */   // Label 7790: @398823
     /* 398823 */   GIM_Try, /*On fail goto*//*Label 7791*/ GIMT_Encode4(398914), // Rule ID 14250 //
     /* 398828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398832 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398836 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 398840 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 398844 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398849 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 398853 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398857 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398861 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 398865 */     // MIs[2] Rn
     /* 398865 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 398870 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 398874 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398876 */     // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 398876 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 398879 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 398883 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398888 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 398894 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398899 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 398907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 398909 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398912 */     GIR_RootConstrainSelectedInstOperands,
     /* 398913 */     // GIR_Coverage, 14250,
     /* 398913 */     GIR_EraseRootFromParent_Done,
     /* 398914 */   // Label 7791: @398914
     /* 398914 */   GIM_Try, /*On fail goto*//*Label 7792*/ GIMT_Encode4(398941), // Rule ID 587 //
     /* 398919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 398922 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 398926 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 398930 */     // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 398930 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
     /* 398935 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 398939 */     GIR_RootConstrainSelectedInstOperands,
     /* 398940 */     // GIR_Coverage, 587,
     /* 398940 */     GIR_Done,
     /* 398941 */   // Label 7792: @398941
     /* 398941 */   GIM_Reject,
     /* 398942 */ // Label 7789: @398942
     /* 398942 */ GIM_Reject,
     /* 398943 */ // Label 7781: @398943
     /* 398943 */ GIM_Try, /*On fail goto*//*Label 7793*/ GIMT_Encode4(399168),
     /* 398948 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 398951 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 398954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398958 */   GIM_Try, /*On fail goto*//*Label 7794*/ GIMT_Encode4(399049), // Rule ID 6992 //
     /* 398963 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398967 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398971 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 398975 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 398979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398984 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 398988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398992 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 398996 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 399000 */     // MIs[2] Rn
     /* 399000 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 399005 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 399009 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399011 */     // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 399011 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 399014 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 399018 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399023 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 399029 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399034 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 399042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 399044 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399047 */     GIR_RootConstrainSelectedInstOperands,
     /* 399048 */     // GIR_Coverage, 6992,
     /* 399048 */     GIR_EraseRootFromParent_Done,
     /* 399049 */   // Label 7794: @399049
     /* 399049 */   GIM_Try, /*On fail goto*//*Label 7795*/ GIMT_Encode4(399140), // Rule ID 14248 //
     /* 399054 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399058 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399062 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 399066 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 399070 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399075 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 399079 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399083 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399087 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 399091 */     // MIs[2] Rn
     /* 399091 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 399096 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 399100 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399102 */     // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 399102 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 399105 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 399109 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399114 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 399120 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399125 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 399133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 399135 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399138 */     GIR_RootConstrainSelectedInstOperands,
     /* 399139 */     // GIR_Coverage, 14248,
     /* 399139 */     GIR_EraseRootFromParent_Done,
     /* 399140 */   // Label 7795: @399140
     /* 399140 */   GIM_Try, /*On fail goto*//*Label 7796*/ GIMT_Encode4(399167), // Rule ID 589 //
     /* 399145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 399148 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 399152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 399156 */     // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 399156 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
     /* 399161 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399165 */     GIR_RootConstrainSelectedInstOperands,
     /* 399166 */     // GIR_Coverage, 589,
     /* 399166 */     GIR_Done,
     /* 399167 */   // Label 7796: @399167
     /* 399167 */   GIM_Reject,
     /* 399168 */ // Label 7793: @399168
     /* 399168 */ GIM_Reject,
     /* 399169 */ // Label 7782: @399169
     /* 399169 */ GIM_Try, /*On fail goto*//*Label 7797*/ GIMT_Encode4(399340),
     /* 399174 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 399177 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 399180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399184 */   GIM_Try, /*On fail goto*//*Label 7798*/ GIMT_Encode4(399248), // Rule ID 6990 //
     /* 399189 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399193 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399197 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 399201 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 399205 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399210 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 399214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399218 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399222 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 399226 */     // MIs[2] Rn
     /* 399226 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 399231 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 399235 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399237 */     // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 399237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 399240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 399242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 399246 */     GIR_RootConstrainSelectedInstOperands,
     /* 399247 */     // GIR_Coverage, 6990,
     /* 399247 */     GIR_EraseRootFromParent_Done,
     /* 399248 */   // Label 7798: @399248
     /* 399248 */   GIM_Try, /*On fail goto*//*Label 7799*/ GIMT_Encode4(399312), // Rule ID 14246 //
     /* 399253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 399265 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 399269 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399274 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 399278 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399282 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 399286 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 399290 */     // MIs[2] Rn
     /* 399290 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 399295 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 399299 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399301 */     // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 399301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 399304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 399306 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 399310 */     GIR_RootConstrainSelectedInstOperands,
     /* 399311 */     // GIR_Coverage, 14246,
     /* 399311 */     GIR_EraseRootFromParent_Done,
     /* 399312 */   // Label 7799: @399312
     /* 399312 */   GIM_Try, /*On fail goto*//*Label 7800*/ GIMT_Encode4(399339), // Rule ID 591 //
     /* 399317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 399320 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399328 */     // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 399328 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
     /* 399333 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399337 */     GIR_RootConstrainSelectedInstOperands,
     /* 399338 */     // GIR_Coverage, 591,
     /* 399338 */     GIR_Done,
     /* 399339 */   // Label 7800: @399339
     /* 399339 */   GIM_Reject,
     /* 399340 */ // Label 7797: @399340
     /* 399340 */ GIM_Reject,
     /* 399341 */ // Label 7783: @399341
     /* 399341 */ GIM_Try, /*On fail goto*//*Label 7801*/ GIMT_Encode4(399378), // Rule ID 1206 //
     /* 399346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 399349 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 399352 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 399355 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399359 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399363 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399367 */   // (strict_fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 399367 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
     /* 399372 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399376 */   GIR_RootConstrainSelectedInstOperands,
     /* 399377 */   // GIR_Coverage, 1206,
     /* 399377 */   GIR_Done,
     /* 399378 */ // Label 7801: @399378
     /* 399378 */ GIM_Reject,
     /* 399379 */ // Label 7784: @399379
     /* 399379 */ GIM_Try, /*On fail goto*//*Label 7802*/ GIMT_Encode4(399416), // Rule ID 1210 //
     /* 399384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 399387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 399390 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 399393 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399397 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399401 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399405 */   // (strict_fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 399405 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
     /* 399410 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399414 */   GIR_RootConstrainSelectedInstOperands,
     /* 399415 */   // GIR_Coverage, 1210,
     /* 399415 */   GIR_Done,
     /* 399416 */ // Label 7802: @399416
     /* 399416 */ GIM_Reject,
     /* 399417 */ // Label 7785: @399417
     /* 399417 */ GIM_Try, /*On fail goto*//*Label 7803*/ GIMT_Encode4(399454), // Rule ID 1202 //
     /* 399422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 399425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 399428 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 399431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399435 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399439 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399443 */   // (strict_fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 399443 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
     /* 399448 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399452 */   GIR_RootConstrainSelectedInstOperands,
     /* 399453 */   // GIR_Coverage, 1202,
     /* 399453 */   GIR_Done,
     /* 399454 */ // Label 7803: @399454
     /* 399454 */ GIM_Reject,
     /* 399455 */ // Label 7786: @399455
     /* 399455 */ GIM_Try, /*On fail goto*//*Label 7804*/ GIMT_Encode4(399492), // Rule ID 1208 //
     /* 399460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 399463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 399466 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 399469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399477 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399481 */   // (strict_fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 399481 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 399486 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399490 */   GIR_RootConstrainSelectedInstOperands,
     /* 399491 */   // GIR_Coverage, 1208,
     /* 399491 */   GIR_Done,
     /* 399492 */ // Label 7804: @399492
     /* 399492 */ GIM_Reject,
     /* 399493 */ // Label 7787: @399493
     /* 399493 */ GIM_Try, /*On fail goto*//*Label 7805*/ GIMT_Encode4(399790),
     /* 399498 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 399501 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 399504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399508 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399512 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399516 */   GIM_Try, /*On fail goto*//*Label 7806*/ GIMT_Encode4(399535), // Rule ID 1204 //
     /* 399521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 399524 */     // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 399524 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
     /* 399529 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399533 */     GIR_RootConstrainSelectedInstOperands,
     /* 399534 */     // GIR_Coverage, 1204,
     /* 399534 */     GIR_Done,
     /* 399535 */   // Label 7806: @399535
     /* 399535 */   GIM_Try, /*On fail goto*//*Label 7807*/ GIMT_Encode4(399789), // Rule ID 7089 //
     /* 399540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 399543 */     // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 399543 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 399546 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 399550 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399555 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 399559 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 399561 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 399564 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 399568 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399573 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 399577 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 399579 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 399582 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 399586 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399591 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 399594 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 399597 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 399599 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 399602 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 399606 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399611 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 399617 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399622 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399627 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 399630 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 399634 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399639 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 399642 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 399644 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 399647 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 399651 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399656 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 399662 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399667 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399672 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 399675 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 399679 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399684 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 399687 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 399689 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 399692 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 399696 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399701 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 399704 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 399707 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 399709 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 399712 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 399716 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399721 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 399724 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 399726 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 399729 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 399733 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399738 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 399740 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 399743 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 399747 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399752 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 399755 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 399758 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 399761 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399766 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 399771 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 399779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399781 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399784 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 399787 */     GIR_RootConstrainSelectedInstOperands,
     /* 399788 */     // GIR_Coverage, 7089,
     /* 399788 */     GIR_EraseRootFromParent_Done,
     /* 399789 */   // Label 7807: @399789
     /* 399789 */   GIM_Reject,
     /* 399790 */ // Label 7805: @399790
     /* 399790 */ GIM_Reject,
     /* 399791 */ // Label 7788: @399791
     /* 399791 */ GIM_Reject,
     /* 399792 */ // Label 105: @399792
     /* 399792 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7816*/ GIMT_Encode4(400407),
     /* 399803 */ /*GILLT_s16*//*Label 7808*/ GIMT_Encode4(399843),
     /* 399807 */ /*GILLT_s32*//*Label 7809*/ GIMT_Encode4(399881),
     /* 399811 */ /*GILLT_s64*//*Label 7810*/ GIMT_Encode4(399919), GIMT_Encode4(0),
     /* 399819 */ /*GILLT_v2s32*//*Label 7811*/ GIMT_Encode4(399957),
     /* 399823 */ /*GILLT_v2s64*//*Label 7812*/ GIMT_Encode4(399995),
     /* 399827 */ /*GILLT_v4s16*//*Label 7813*/ GIMT_Encode4(400033),
     /* 399831 */ /*GILLT_v4s32*//*Label 7814*/ GIMT_Encode4(400071), GIMT_Encode4(0),
     /* 399839 */ /*GILLT_v8s16*//*Label 7815*/ GIMT_Encode4(400109),
     /* 399843 */ // Label 7808: @399843
     /* 399843 */ GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(399880), // Rule ID 635 //
     /* 399848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 399851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 399854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 399857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 399861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 399865 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 399869 */   // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 399869 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
     /* 399874 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399878 */   GIR_RootConstrainSelectedInstOperands,
     /* 399879 */   // GIR_Coverage, 635,
     /* 399879 */   GIR_Done,
     /* 399880 */ // Label 7817: @399880
     /* 399880 */ GIM_Reject,
     /* 399881 */ // Label 7809: @399881
     /* 399881 */ GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(399918), // Rule ID 637 //
     /* 399886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 399889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 399892 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 399895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 399899 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 399903 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 399907 */   // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 399907 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
     /* 399912 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399916 */   GIR_RootConstrainSelectedInstOperands,
     /* 399917 */   // GIR_Coverage, 637,
     /* 399917 */   GIR_Done,
     /* 399918 */ // Label 7818: @399918
     /* 399918 */ GIM_Reject,
     /* 399919 */ // Label 7810: @399919
     /* 399919 */ GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(399956), // Rule ID 639 //
     /* 399924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 399927 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 399930 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 399933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399937 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399941 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399945 */   // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 399945 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
     /* 399950 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399954 */   GIR_RootConstrainSelectedInstOperands,
     /* 399955 */   // GIR_Coverage, 639,
     /* 399955 */   GIR_Done,
     /* 399956 */ // Label 7819: @399956
     /* 399956 */ GIM_Reject,
     /* 399957 */ // Label 7811: @399957
     /* 399957 */ GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(399994), // Rule ID 1346 //
     /* 399962 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 399965 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 399968 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 399971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399975 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399979 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399983 */   // (strict_fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 399983 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
     /* 399988 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 399992 */   GIR_RootConstrainSelectedInstOperands,
     /* 399993 */   // GIR_Coverage, 1346,
     /* 399993 */   GIR_Done,
     /* 399994 */ // Label 7820: @399994
     /* 399994 */ GIM_Reject,
     /* 399995 */ // Label 7812: @399995
     /* 399995 */ GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(400032), // Rule ID 1350 //
     /* 400000 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 400003 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 400006 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 400009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400013 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400017 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400021 */   // (strict_fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 400021 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
     /* 400026 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 400030 */   GIR_RootConstrainSelectedInstOperands,
     /* 400031 */   // GIR_Coverage, 1350,
     /* 400031 */   GIR_Done,
     /* 400032 */ // Label 7821: @400032
     /* 400032 */ GIM_Reject,
     /* 400033 */ // Label 7813: @400033
     /* 400033 */ GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(400070), // Rule ID 1342 //
     /* 400038 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400041 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 400044 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 400047 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400051 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400055 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400059 */   // (strict_fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 400059 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
     /* 400064 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 400068 */   GIR_RootConstrainSelectedInstOperands,
     /* 400069 */   // GIR_Coverage, 1342,
     /* 400069 */   GIR_Done,
     /* 400070 */ // Label 7822: @400070
     /* 400070 */ GIM_Reject,
     /* 400071 */ // Label 7814: @400071
     /* 400071 */ GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(400108), // Rule ID 1348 //
     /* 400076 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 400079 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 400082 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 400085 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400089 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400093 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400097 */   // (strict_fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 400097 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 400102 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 400106 */   GIR_RootConstrainSelectedInstOperands,
     /* 400107 */   // GIR_Coverage, 1348,
     /* 400107 */   GIR_Done,
     /* 400108 */ // Label 7823: @400108
     /* 400108 */ GIM_Reject,
     /* 400109 */ // Label 7815: @400109
     /* 400109 */ GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(400406),
     /* 400114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400117 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 400120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400124 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400128 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400132 */   GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(400151), // Rule ID 1344 //
     /* 400137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400140 */     // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 400140 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
     /* 400145 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 400149 */     GIR_RootConstrainSelectedInstOperands,
     /* 400150 */     // GIR_Coverage, 1344,
     /* 400150 */     GIR_Done,
     /* 400151 */   // Label 7825: @400151
     /* 400151 */   GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(400405), // Rule ID 7095 //
     /* 400156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 400159 */     // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 400159 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 400162 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 400166 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400171 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 400175 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 400177 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 400180 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 400184 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400189 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 400193 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 400195 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 400198 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 400202 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400207 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 400210 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 400213 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 400215 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 400218 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400222 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400227 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 400233 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400238 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400243 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 400246 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 400250 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400255 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 400258 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 400260 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 400263 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400267 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400272 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 400278 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400283 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400288 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 400291 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 400295 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400300 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 400303 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 400305 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 400308 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 400312 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400317 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 400320 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 400323 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 400325 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 400328 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 400332 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400337 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 400340 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 400342 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 400345 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 400349 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400354 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 400356 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 400359 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 400363 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400368 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 400371 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 400374 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 400377 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400382 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400387 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 400395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400397 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400400 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 400403 */     GIR_RootConstrainSelectedInstOperands,
     /* 400404 */     // GIR_Coverage, 7095,
     /* 400404 */     GIR_EraseRootFromParent_Done,
     /* 400405 */   // Label 7826: @400405
     /* 400405 */   GIM_Reject,
     /* 400406 */ // Label 7824: @400406
     /* 400406 */ GIM_Reject,
     /* 400407 */ // Label 7816: @400407
     /* 400407 */ GIM_Reject,
     /* 400408 */ // Label 106: @400408
     /* 400408 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7835*/ GIMT_Encode4(404129),
     /* 400419 */ /*GILLT_s16*//*Label 7827*/ GIMT_Encode4(400459),
     /* 400423 */ /*GILLT_s32*//*Label 7828*/ GIMT_Encode4(401013),
     /* 400427 */ /*GILLT_s64*//*Label 7829*/ GIMT_Encode4(401561), GIMT_Encode4(0),
     /* 400435 */ /*GILLT_v2s32*//*Label 7830*/ GIMT_Encode4(402109),
     /* 400439 */ /*GILLT_v2s64*//*Label 7831*/ GIMT_Encode4(402639),
     /* 400443 */ /*GILLT_v4s16*//*Label 7832*/ GIMT_Encode4(402997),
     /* 400447 */ /*GILLT_v4s32*//*Label 7833*/ GIMT_Encode4(403339), GIMT_Encode4(0),
     /* 400455 */ /*GILLT_v8s16*//*Label 7834*/ GIMT_Encode4(403697),
     /* 400459 */ // Label 7827: @400459
     /* 400459 */ GIM_Try, /*On fail goto*//*Label 7836*/ GIMT_Encode4(401012),
     /* 400464 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 400467 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 400470 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400474 */   GIM_Try, /*On fail goto*//*Label 7837*/ GIMT_Encode4(400587), // Rule ID 6314 //
     /* 400479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400482 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400486 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400490 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400494 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400498 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400503 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 400507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 400511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400519 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 400523 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400528 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 400532 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400536 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 400540 */     // MIs[3] Operand 1
     /* 400540 */     // No operand predicates
     /* 400540 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400542 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 400542 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 400545 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400549 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400554 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 400560 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400565 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 400573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400575 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400578 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 400582 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 400585 */     GIR_RootConstrainSelectedInstOperands,
     /* 400586 */     // GIR_Coverage, 6314,
     /* 400586 */     GIR_EraseRootFromParent_Done,
     /* 400587 */   // Label 7837: @400587
     /* 400587 */   GIM_Try, /*On fail goto*//*Label 7838*/ GIMT_Encode4(400700), // Rule ID 14227 //
     /* 400592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400595 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400599 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400603 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400607 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400611 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400616 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400620 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400624 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 400628 */     // MIs[2] Operand 1
     /* 400628 */     // No operand predicates
     /* 400628 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 400632 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400636 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400640 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 400644 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400649 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 400653 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400655 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 400655 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 400658 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400662 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400667 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 400673 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400678 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 400686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400688 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400691 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 400695 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 400698 */     GIR_RootConstrainSelectedInstOperands,
     /* 400699 */     // GIR_Coverage, 14227,
     /* 400699 */     GIR_EraseRootFromParent_Done,
     /* 400700 */   // Label 7838: @400700
     /* 400700 */   GIM_Try, /*On fail goto*//*Label 7839*/ GIMT_Encode4(400779), // Rule ID 14161 //
     /* 400705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 400708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400712 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400716 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400724 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400729 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 400733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400737 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 400739 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 400739 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 400742 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400746 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400751 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 400757 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400762 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 400770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400772 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 400774 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400777 */     GIR_RootConstrainSelectedInstOperands,
     /* 400778 */     // GIR_Coverage, 14161,
     /* 400778 */     GIR_EraseRootFromParent_Done,
     /* 400779 */   // Label 7839: @400779
     /* 400779 */   GIM_Try, /*On fail goto*//*Label 7840*/ GIMT_Encode4(400858), // Rule ID 4871 //
     /* 400784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 400787 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400791 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400795 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400799 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400803 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400807 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400812 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 400816 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 400818 */     // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 400818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 400821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400830 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 400836 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400841 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 400849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400851 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 400853 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400856 */     GIR_RootConstrainSelectedInstOperands,
     /* 400857 */     // GIR_Coverage, 4871,
     /* 400857 */     GIR_EraseRootFromParent_Done,
     /* 400858 */   // Label 7840: @400858
     /* 400858 */   GIM_Try, /*On fail goto*//*Label 7841*/ GIMT_Encode4(400921), // Rule ID 13765 //
     /* 400863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400878 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 400887 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400891 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400895 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 400899 */     // MIs[2] Operand 1
     /* 400899 */     // No operand predicates
     /* 400899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400903 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 400905 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 400905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 400908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 400912 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 400916 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 400919 */     GIR_RootConstrainSelectedInstOperands,
     /* 400920 */     // GIR_Coverage, 13765,
     /* 400920 */     GIR_EraseRootFromParent_Done,
     /* 400921 */   // Label 7841: @400921
     /* 400921 */   GIM_Try, /*On fail goto*//*Label 7842*/ GIMT_Encode4(400984), // Rule ID 2015 //
     /* 400926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 400929 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 400945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400949 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 400954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400962 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 400966 */     // MIs[2] Operand 1
     /* 400966 */     // No operand predicates
     /* 400966 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 400968 */     // (strict_fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 400968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 400971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 400973 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 400975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 400979 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 400982 */     GIR_RootConstrainSelectedInstOperands,
     /* 400983 */     // GIR_Coverage, 2015,
     /* 400983 */     GIR_EraseRootFromParent_Done,
     /* 400984 */   // Label 7842: @400984
     /* 400984 */   GIM_Try, /*On fail goto*//*Label 7843*/ GIMT_Encode4(401011), // Rule ID 623 //
     /* 400989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 400992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 400996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 401000 */     // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 401000 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 401005 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 401009 */     GIR_RootConstrainSelectedInstOperands,
     /* 401010 */     // GIR_Coverage, 623,
     /* 401010 */     GIR_Done,
     /* 401011 */   // Label 7843: @401011
     /* 401011 */   GIM_Reject,
     /* 401012 */ // Label 7836: @401012
     /* 401012 */ GIM_Reject,
     /* 401013 */ // Label 7828: @401013
     /* 401013 */ GIM_Try, /*On fail goto*//*Label 7844*/ GIMT_Encode4(401560),
     /* 401018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 401021 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 401024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401028 */   GIM_Try, /*On fail goto*//*Label 7845*/ GIMT_Encode4(401141), // Rule ID 6316 //
     /* 401033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401052 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401057 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 401065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401069 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401073 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 401077 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401082 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 401086 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401090 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 401094 */     // MIs[3] Operand 1
     /* 401094 */     // No operand predicates
     /* 401094 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 401096 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 401096 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 401099 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401103 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401108 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 401114 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401119 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 401127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401129 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 401136 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 401139 */     GIR_RootConstrainSelectedInstOperands,
     /* 401140 */     // GIR_Coverage, 6316,
     /* 401140 */     GIR_EraseRootFromParent_Done,
     /* 401141 */   // Label 7845: @401141
     /* 401141 */   GIM_Try, /*On fail goto*//*Label 7846*/ GIMT_Encode4(401254), // Rule ID 14229 //
     /* 401146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401165 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401170 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 401174 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401178 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 401182 */     // MIs[2] Operand 1
     /* 401182 */     // No operand predicates
     /* 401182 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 401186 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401190 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401194 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 401198 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401203 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 401207 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 401209 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 401209 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 401212 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401216 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401221 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 401227 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401232 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 401240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401242 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401245 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 401249 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 401252 */     GIR_RootConstrainSelectedInstOperands,
     /* 401253 */     // GIR_Coverage, 14229,
     /* 401253 */     GIR_EraseRootFromParent_Done,
     /* 401254 */   // Label 7846: @401254
     /* 401254 */   GIM_Try, /*On fail goto*//*Label 7847*/ GIMT_Encode4(401330), // Rule ID 14163 //
     /* 401259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401280 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401288 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401290 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 401290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 401293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401302 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 401308 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401313 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 401321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 401325 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401328 */     GIR_RootConstrainSelectedInstOperands,
     /* 401329 */     // GIR_Coverage, 14163,
     /* 401329 */     GIR_EraseRootFromParent_Done,
     /* 401330 */   // Label 7847: @401330
     /* 401330 */   GIM_Try, /*On fail goto*//*Label 7848*/ GIMT_Encode4(401406), // Rule ID 4873 //
     /* 401335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 401343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401351 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401355 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401360 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401364 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401366 */     // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 401366 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 401369 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401373 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401378 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 401384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401389 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 401397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401399 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 401401 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401404 */     GIR_RootConstrainSelectedInstOperands,
     /* 401405 */     // GIR_Coverage, 4873,
     /* 401405 */     GIR_EraseRootFromParent_Done,
     /* 401406 */   // Label 7848: @401406
     /* 401406 */   GIM_Try, /*On fail goto*//*Label 7849*/ GIMT_Encode4(401469), // Rule ID 13767 //
     /* 401411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401426 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401435 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 401439 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401443 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 401447 */     // MIs[2] Operand 1
     /* 401447 */     // No operand predicates
     /* 401447 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401451 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401453 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 401453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 401456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 401460 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 401464 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 401467 */     GIR_RootConstrainSelectedInstOperands,
     /* 401468 */     // GIR_Coverage, 13767,
     /* 401468 */     GIR_EraseRootFromParent_Done,
     /* 401469 */   // Label 7849: @401469
     /* 401469 */   GIM_Try, /*On fail goto*//*Label 7850*/ GIMT_Encode4(401532), // Rule ID 2017 //
     /* 401474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 401485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401489 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 401493 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401497 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 401506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401510 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 401514 */     // MIs[2] Operand 1
     /* 401514 */     // No operand predicates
     /* 401514 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401516 */     // (strict_fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 401516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 401519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401521 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 401523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 401527 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 401530 */     GIR_RootConstrainSelectedInstOperands,
     /* 401531 */     // GIR_Coverage, 2017,
     /* 401531 */     GIR_EraseRootFromParent_Done,
     /* 401532 */   // Label 7850: @401532
     /* 401532 */   GIM_Try, /*On fail goto*//*Label 7851*/ GIMT_Encode4(401559), // Rule ID 625 //
     /* 401537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 401540 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401548 */     // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 401548 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 401553 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 401557 */     GIR_RootConstrainSelectedInstOperands,
     /* 401558 */     // GIR_Coverage, 625,
     /* 401558 */     GIR_Done,
     /* 401559 */   // Label 7851: @401559
     /* 401559 */   GIM_Reject,
     /* 401560 */ // Label 7844: @401560
     /* 401560 */ GIM_Reject,
     /* 401561 */ // Label 7829: @401561
     /* 401561 */ GIM_Try, /*On fail goto*//*Label 7852*/ GIMT_Encode4(402108),
     /* 401566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 401569 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 401572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401576 */   GIM_Try, /*On fail goto*//*Label 7853*/ GIMT_Encode4(401689), // Rule ID 6318 //
     /* 401581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401584 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401588 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401592 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401596 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401600 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401605 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 401613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401617 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401621 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 401625 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401630 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 401634 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401638 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 401642 */     // MIs[3] Operand 1
     /* 401642 */     // No operand predicates
     /* 401642 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 401644 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 401644 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 401647 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401651 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401656 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 401662 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401667 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 401675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401677 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 401684 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 401687 */     GIR_RootConstrainSelectedInstOperands,
     /* 401688 */     // GIR_Coverage, 6318,
     /* 401688 */     GIR_EraseRootFromParent_Done,
     /* 401689 */   // Label 7853: @401689
     /* 401689 */   GIM_Try, /*On fail goto*//*Label 7854*/ GIMT_Encode4(401802), // Rule ID 14231 //
     /* 401694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401713 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401718 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 401722 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401726 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 401730 */     // MIs[2] Operand 1
     /* 401730 */     // No operand predicates
     /* 401730 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 401734 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401738 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401742 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 401746 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401751 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 401755 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 401757 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 401757 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 401760 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401764 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401769 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 401775 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401780 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 401788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401790 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 401797 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 401800 */     GIR_RootConstrainSelectedInstOperands,
     /* 401801 */     // GIR_Coverage, 14231,
     /* 401801 */     GIR_EraseRootFromParent_Done,
     /* 401802 */   // Label 7854: @401802
     /* 401802 */   GIM_Try, /*On fail goto*//*Label 7855*/ GIMT_Encode4(401878), // Rule ID 14165 //
     /* 401807 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401811 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401815 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401819 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401823 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401828 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401832 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401836 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401838 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 401838 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 401841 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401845 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401850 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 401856 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401861 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 401869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401871 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 401873 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401876 */     GIR_RootConstrainSelectedInstOperands,
     /* 401877 */     // GIR_Coverage, 14165,
     /* 401877 */     GIR_EraseRootFromParent_Done,
     /* 401878 */   // Label 7855: @401878
     /* 401878 */   GIM_Try, /*On fail goto*//*Label 7856*/ GIMT_Encode4(401954), // Rule ID 4875 //
     /* 401883 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401887 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 401891 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401895 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401899 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401903 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401908 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 401912 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401914 */     // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 401914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 401917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401926 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 401932 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401937 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 401945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 401947 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 401949 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401952 */     GIR_RootConstrainSelectedInstOperands,
     /* 401953 */     // GIR_Coverage, 4875,
     /* 401953 */     GIR_EraseRootFromParent_Done,
     /* 401954 */   // Label 7856: @401954
     /* 401954 */   GIM_Try, /*On fail goto*//*Label 7857*/ GIMT_Encode4(402017), // Rule ID 13769 //
     /* 401959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 401962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 401970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 401974 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 401978 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401983 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 401987 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401991 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 401995 */     // MIs[2] Operand 1
     /* 401995 */     // No operand predicates
     /* 401995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401999 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402001 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 402004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402008 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402012 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402015 */     GIR_RootConstrainSelectedInstOperands,
     /* 402016 */     // GIR_Coverage, 13769,
     /* 402016 */     GIR_EraseRootFromParent_Done,
     /* 402017 */   // Label 7857: @402017
     /* 402017 */   GIM_Try, /*On fail goto*//*Label 7858*/ GIMT_Encode4(402080), // Rule ID 2019 //
     /* 402022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402025 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 402037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 402041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 402045 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402050 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 402054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402058 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 402062 */     // MIs[2] Operand 1
     /* 402062 */     // No operand predicates
     /* 402062 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402064 */     // (strict_fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 402067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402069 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402075 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402078 */     GIR_RootConstrainSelectedInstOperands,
     /* 402079 */     // GIR_Coverage, 2019,
     /* 402079 */     GIR_EraseRootFromParent_Done,
     /* 402080 */   // Label 7858: @402080
     /* 402080 */   GIM_Try, /*On fail goto*//*Label 7859*/ GIMT_Encode4(402107), // Rule ID 627 //
     /* 402085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 402088 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402096 */     // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 402096 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 402101 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 402105 */     GIR_RootConstrainSelectedInstOperands,
     /* 402106 */     // GIR_Coverage, 627,
     /* 402106 */     GIR_Done,
     /* 402107 */   // Label 7859: @402107
     /* 402107 */   GIM_Reject,
     /* 402108 */ // Label 7852: @402108
     /* 402108 */ GIM_Reject,
     /* 402109 */ // Label 7830: @402109
     /* 402109 */ GIM_Try, /*On fail goto*//*Label 7860*/ GIMT_Encode4(402638),
     /* 402114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 402117 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 402120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402124 */   GIM_Try, /*On fail goto*//*Label 7861*/ GIMT_Encode4(402210), // Rule ID 13757 //
     /* 402129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 402140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402144 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 402148 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 402152 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402156 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 402160 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402165 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 402169 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402173 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 402177 */     // MIs[3] Operand 1
     /* 402177 */     // No operand predicates
     /* 402177 */     // MIs[1] Operand 2
     /* 402177 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 402188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402192 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 402194 */     // (strict_fmul:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402199 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 402205 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 402208 */     GIR_RootConstrainSelectedInstOperands,
     /* 402209 */     // GIR_Coverage, 13757,
     /* 402209 */     GIR_EraseRootFromParent_Done,
     /* 402210 */   // Label 7861: @402210
     /* 402210 */   GIM_Try, /*On fail goto*//*Label 7862*/ GIMT_Encode4(402296), // Rule ID 2007 //
     /* 402215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402218 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402222 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402226 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 402230 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 402238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 402242 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402246 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 402250 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402255 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 402259 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402263 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 402267 */     // MIs[3] Operand 1
     /* 402267 */     // No operand predicates
     /* 402267 */     // MIs[1] Operand 2
     /* 402267 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 402278 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 402280 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402285 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402287 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 402291 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 402294 */     GIR_RootConstrainSelectedInstOperands,
     /* 402295 */     // GIR_Coverage, 2007,
     /* 402295 */     GIR_EraseRootFromParent_Done,
     /* 402296 */   // Label 7862: @402296
     /* 402296 */   GIM_Try, /*On fail goto*//*Label 7863*/ GIMT_Encode4(402359), // Rule ID 13758 //
     /* 402301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 402312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402316 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 402320 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402325 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 402329 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402333 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 402337 */     // MIs[2] Operand 1
     /* 402337 */     // No operand predicates
     /* 402337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402341 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402343 */     // (strict_fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402354 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402357 */     GIR_RootConstrainSelectedInstOperands,
     /* 402358 */     // GIR_Coverage, 13758,
     /* 402358 */     GIR_EraseRootFromParent_Done,
     /* 402359 */   // Label 7863: @402359
     /* 402359 */   GIM_Try, /*On fail goto*//*Label 7864*/ GIMT_Encode4(402422), // Rule ID 2008 //
     /* 402364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402367 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402371 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402375 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 402379 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 402383 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 402387 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402392 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 402396 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402400 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 402404 */     // MIs[2] Operand 1
     /* 402404 */     // No operand predicates
     /* 402404 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402406 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402411 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402413 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402417 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402420 */     GIR_RootConstrainSelectedInstOperands,
     /* 402421 */     // GIR_Coverage, 2008,
     /* 402421 */     GIR_EraseRootFromParent_Done,
     /* 402422 */   // Label 7864: @402422
     /* 402422 */   GIM_Try, /*On fail goto*//*Label 7865*/ GIMT_Encode4(402516), // Rule ID 14233 //
     /* 402427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 402435 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 402439 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 402444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402448 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 402450 */     // (strict_fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 402450 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 402453 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 402457 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 402464 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 402467 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 402471 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402476 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 402479 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402483 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 402486 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402491 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402496 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 402501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402514 */     GIR_RootConstrainSelectedInstOperands,
     /* 402515 */     // GIR_Coverage, 14233,
     /* 402515 */     GIR_EraseRootFromParent_Done,
     /* 402516 */   // Label 7865: @402516
     /* 402516 */   GIM_Try, /*On fail goto*//*Label 7866*/ GIMT_Encode4(402610), // Rule ID 6320 //
     /* 402521 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402525 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402529 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 402533 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 402537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 402542 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 402544 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 402544 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 402547 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 402551 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402556 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 402558 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 402561 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 402565 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402570 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 402573 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402577 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 402580 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402585 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402590 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 402595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 402598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402600 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402602 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402608 */     GIR_RootConstrainSelectedInstOperands,
     /* 402609 */     // GIR_Coverage, 6320,
     /* 402609 */     GIR_EraseRootFromParent_Done,
     /* 402610 */   // Label 7866: @402610
     /* 402610 */   GIM_Try, /*On fail goto*//*Label 7867*/ GIMT_Encode4(402637), // Rule ID 1326 //
     /* 402615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402618 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402622 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402626 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 402626 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
     /* 402631 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 402635 */     GIR_RootConstrainSelectedInstOperands,
     /* 402636 */     // GIR_Coverage, 1326,
     /* 402636 */     GIR_Done,
     /* 402637 */   // Label 7867: @402637
     /* 402637 */   GIM_Reject,
     /* 402638 */ // Label 7860: @402638
     /* 402638 */ GIM_Reject,
     /* 402639 */ // Label 7831: @402639
     /* 402639 */ GIM_Try, /*On fail goto*//*Label 7868*/ GIMT_Encode4(402996),
     /* 402644 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 402647 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 402650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402654 */   GIM_Try, /*On fail goto*//*Label 7869*/ GIMT_Encode4(402717), // Rule ID 13763 //
     /* 402659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 402670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 402674 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 402678 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 402687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402691 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 402695 */     // MIs[2] Operand 1
     /* 402695 */     // No operand predicates
     /* 402695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402699 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402701 */     // (strict_fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 402704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402706 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402712 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402715 */     GIR_RootConstrainSelectedInstOperands,
     /* 402716 */     // GIR_Coverage, 13763,
     /* 402716 */     GIR_EraseRootFromParent_Done,
     /* 402717 */   // Label 7869: @402717
     /* 402717 */   GIM_Try, /*On fail goto*//*Label 7870*/ GIMT_Encode4(402780), // Rule ID 2013 //
     /* 402722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402725 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402729 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402733 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 402737 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 402741 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 402745 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402750 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 402754 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 402758 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 402762 */     // MIs[2] Operand 1
     /* 402762 */     // No operand predicates
     /* 402762 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402764 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 402764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 402767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402769 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402771 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402775 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 402778 */     GIR_RootConstrainSelectedInstOperands,
     /* 402779 */     // GIR_Coverage, 2013,
     /* 402779 */     GIR_EraseRootFromParent_Done,
     /* 402780 */   // Label 7870: @402780
     /* 402780 */   GIM_Try, /*On fail goto*//*Label 7871*/ GIMT_Encode4(402874), // Rule ID 14237 //
     /* 402785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 402793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 402797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402802 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402806 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 402808 */     // (strict_fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 402808 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 402811 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 402815 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402820 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 402822 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 402825 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 402829 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402834 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 402837 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402841 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 402844 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402849 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402854 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 402862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 402866 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402872 */     GIR_RootConstrainSelectedInstOperands,
     /* 402873 */     // GIR_Coverage, 14237,
     /* 402873 */     GIR_EraseRootFromParent_Done,
     /* 402874 */   // Label 7871: @402874
     /* 402874 */   GIM_Try, /*On fail goto*//*Label 7872*/ GIMT_Encode4(402968), // Rule ID 6324 //
     /* 402879 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402883 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 402887 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 402891 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 402895 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402900 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 402902 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 402902 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 402905 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 402909 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402914 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 402916 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 402919 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 402923 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402928 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 402931 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 402935 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 402938 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402943 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402948 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 402953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 402956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 402958 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 402960 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402966 */     GIR_RootConstrainSelectedInstOperands,
     /* 402967 */     // GIR_Coverage, 6324,
     /* 402967 */     GIR_EraseRootFromParent_Done,
     /* 402968 */   // Label 7872: @402968
     /* 402968 */   GIM_Try, /*On fail goto*//*Label 7873*/ GIMT_Encode4(402995), // Rule ID 1330 //
     /* 402973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 402976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402984 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 402984 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
     /* 402989 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 402993 */     GIR_RootConstrainSelectedInstOperands,
     /* 402994 */     // GIR_Coverage, 1330,
     /* 402994 */     GIR_Done,
     /* 402995 */   // Label 7873: @402995
     /* 402995 */   GIM_Reject,
     /* 402996 */ // Label 7868: @402996
     /* 402996 */ GIM_Reject,
     /* 402997 */ // Label 7832: @402997
     /* 402997 */ GIM_Try, /*On fail goto*//*Label 7874*/ GIMT_Encode4(403338),
     /* 403002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 403005 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 403008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403012 */   GIM_Try, /*On fail goto*//*Label 7875*/ GIMT_Encode4(403098), // Rule ID 13751 //
     /* 403017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403020 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403024 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 403028 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403032 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 403036 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403040 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403044 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 403048 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403053 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 403057 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403061 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403065 */     // MIs[3] Operand 1
     /* 403065 */     // No operand predicates
     /* 403065 */     // MIs[1] Operand 2
     /* 403065 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 403076 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403080 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403082 */     // (strict_fmul:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 403085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 403089 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 403093 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 403096 */     GIR_RootConstrainSelectedInstOperands,
     /* 403097 */     // GIR_Coverage, 13751,
     /* 403097 */     GIR_EraseRootFromParent_Done,
     /* 403098 */   // Label 7875: @403098
     /* 403098 */   GIM_Try, /*On fail goto*//*Label 7876*/ GIMT_Encode4(403184), // Rule ID 2001 //
     /* 403103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403106 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 403118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403122 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 403126 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403130 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403134 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 403138 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403143 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 403147 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403151 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403155 */     // MIs[3] Operand 1
     /* 403155 */     // No operand predicates
     /* 403155 */     // MIs[1] Operand 2
     /* 403155 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 403166 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403168 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 403171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403173 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 403175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 403179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 403182 */     GIR_RootConstrainSelectedInstOperands,
     /* 403183 */     // GIR_Coverage, 2001,
     /* 403183 */     GIR_EraseRootFromParent_Done,
     /* 403184 */   // Label 7876: @403184
     /* 403184 */   GIM_Try, /*On fail goto*//*Label 7877*/ GIMT_Encode4(403247), // Rule ID 13752 //
     /* 403189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403192 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403196 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403200 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403204 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403208 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403213 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403217 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403221 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403225 */     // MIs[2] Operand 1
     /* 403225 */     // No operand predicates
     /* 403225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403229 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403231 */     // (strict_fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 403234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 403238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403242 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403245 */     GIR_RootConstrainSelectedInstOperands,
     /* 403246 */     // GIR_Coverage, 13752,
     /* 403246 */     GIR_EraseRootFromParent_Done,
     /* 403247 */   // Label 7877: @403247
     /* 403247 */   GIM_Try, /*On fail goto*//*Label 7878*/ GIMT_Encode4(403310), // Rule ID 2002 //
     /* 403252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403255 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403288 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403292 */     // MIs[2] Operand 1
     /* 403292 */     // No operand predicates
     /* 403292 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403294 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 403297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403299 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 403301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403305 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403308 */     GIR_RootConstrainSelectedInstOperands,
     /* 403309 */     // GIR_Coverage, 2002,
     /* 403309 */     GIR_EraseRootFromParent_Done,
     /* 403310 */   // Label 7878: @403310
     /* 403310 */   GIM_Try, /*On fail goto*//*Label 7879*/ GIMT_Encode4(403337), // Rule ID 1322 //
     /* 403315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403318 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403322 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403326 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 403326 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
     /* 403331 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 403335 */     GIR_RootConstrainSelectedInstOperands,
     /* 403336 */     // GIR_Coverage, 1322,
     /* 403336 */     GIR_Done,
     /* 403337 */   // Label 7879: @403337
     /* 403337 */   GIM_Reject,
     /* 403338 */ // Label 7874: @403338
     /* 403338 */ GIM_Reject,
     /* 403339 */ // Label 7833: @403339
     /* 403339 */ GIM_Try, /*On fail goto*//*Label 7880*/ GIMT_Encode4(403696),
     /* 403344 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 403347 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 403350 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403354 */   GIM_Try, /*On fail goto*//*Label 7881*/ GIMT_Encode4(403417), // Rule ID 13761 //
     /* 403359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 403362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 403370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 403374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403387 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403391 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 403395 */     // MIs[2] Operand 1
     /* 403395 */     // No operand predicates
     /* 403395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403401 */     // (strict_fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 403404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 403408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403412 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403415 */     GIR_RootConstrainSelectedInstOperands,
     /* 403416 */     // GIR_Coverage, 13761,
     /* 403416 */     GIR_EraseRootFromParent_Done,
     /* 403417 */   // Label 7881: @403417
     /* 403417 */   GIM_Try, /*On fail goto*//*Label 7882*/ GIMT_Encode4(403480), // Rule ID 2011 //
     /* 403422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 403425 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403429 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403433 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 403437 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 403441 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403445 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403450 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403454 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403458 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 403462 */     // MIs[2] Operand 1
     /* 403462 */     // No operand predicates
     /* 403462 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403464 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 403467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403469 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 403471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403475 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403478 */     GIR_RootConstrainSelectedInstOperands,
     /* 403479 */     // GIR_Coverage, 2011,
     /* 403479 */     GIR_EraseRootFromParent_Done,
     /* 403480 */   // Label 7882: @403480
     /* 403480 */   GIM_Try, /*On fail goto*//*Label 7883*/ GIMT_Encode4(403574), // Rule ID 14235 //
     /* 403485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 403493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 403497 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 403502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403506 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 403508 */     // (strict_fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 403508 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 403511 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 403515 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403520 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 403522 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 403525 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 403529 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403534 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 403537 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403541 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 403544 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403549 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403554 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 403559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 403562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 403566 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403572 */     GIR_RootConstrainSelectedInstOperands,
     /* 403573 */     // GIR_Coverage, 14235,
     /* 403573 */     GIR_EraseRootFromParent_Done,
     /* 403574 */   // Label 7883: @403574
     /* 403574 */   GIM_Try, /*On fail goto*//*Label 7884*/ GIMT_Encode4(403668), // Rule ID 6322 //
     /* 403579 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 403591 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 403595 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 403600 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 403602 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 403602 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 403605 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 403609 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403614 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 403616 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 403619 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 403623 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403628 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 403631 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403635 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 403638 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403643 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403648 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 403653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 403656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403658 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 403660 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403666 */     GIR_RootConstrainSelectedInstOperands,
     /* 403667 */     // GIR_Coverage, 6322,
     /* 403667 */     GIR_EraseRootFromParent_Done,
     /* 403668 */   // Label 7884: @403668
     /* 403668 */   GIM_Try, /*On fail goto*//*Label 7885*/ GIMT_Encode4(403695), // Rule ID 1328 //
     /* 403673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 403676 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403680 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403684 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 403684 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 403689 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 403693 */     GIR_RootConstrainSelectedInstOperands,
     /* 403694 */     // GIR_Coverage, 1328,
     /* 403694 */     GIR_Done,
     /* 403695 */   // Label 7885: @403695
     /* 403695 */   GIM_Reject,
     /* 403696 */ // Label 7880: @403696
     /* 403696 */ GIM_Reject,
     /* 403697 */ // Label 7834: @403697
     /* 403697 */ GIM_Try, /*On fail goto*//*Label 7886*/ GIMT_Encode4(404128),
     /* 403702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403705 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 403708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403712 */   GIM_Try, /*On fail goto*//*Label 7887*/ GIMT_Encode4(403775), // Rule ID 13755 //
     /* 403717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403736 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403741 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403745 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403749 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403753 */     // MIs[2] Operand 1
     /* 403753 */     // No operand predicates
     /* 403753 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403757 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403759 */     // (strict_fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 403762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 403766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403770 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403773 */     GIR_RootConstrainSelectedInstOperands,
     /* 403774 */     // GIR_Coverage, 13755,
     /* 403774 */     GIR_EraseRootFromParent_Done,
     /* 403775 */   // Label 7887: @403775
     /* 403775 */   GIM_Try, /*On fail goto*//*Label 7888*/ GIMT_Encode4(403838), // Rule ID 2005 //
     /* 403780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403783 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 403795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403799 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403803 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 403808 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403812 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403816 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403820 */     // MIs[2] Operand 1
     /* 403820 */     // No operand predicates
     /* 403820 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403822 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 403822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 403825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 403827 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 403829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 403833 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 403836 */     GIR_RootConstrainSelectedInstOperands,
     /* 403837 */     // GIR_Coverage, 2005,
     /* 403837 */     GIR_EraseRootFromParent_Done,
     /* 403838 */   // Label 7888: @403838
     /* 403838 */   GIM_Try, /*On fail goto*//*Label 7889*/ GIMT_Encode4(403865), // Rule ID 1324 //
     /* 403843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 403846 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403854 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 403854 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
     /* 403859 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 403863 */     GIR_RootConstrainSelectedInstOperands,
     /* 403864 */     // GIR_Coverage, 1324,
     /* 403864 */     GIR_Done,
     /* 403865 */   // Label 7889: @403865
     /* 403865 */   GIM_Try, /*On fail goto*//*Label 7890*/ GIMT_Encode4(404127), // Rule ID 7093 //
     /* 403870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 403873 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403881 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 403881 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 403884 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 403888 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403893 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 403897 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 403899 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 403902 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 403906 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403911 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 403915 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 403917 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 403920 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 403924 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403929 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 403932 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 403935 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 403937 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 403940 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 403944 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403949 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 403955 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 403960 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403965 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 403968 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 403972 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403977 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 403980 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 403982 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 403985 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 403989 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403994 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 404000 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404005 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404010 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 404013 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 404017 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404022 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 404025 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 404027 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 404030 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 404034 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404039 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 404042 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 404045 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 404047 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 404050 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 404054 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404059 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 404062 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 404064 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 404067 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 404071 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404076 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 404078 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 404081 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 404085 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404090 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 404093 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 404096 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 404099 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404104 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404109 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 404117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404119 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404122 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 404125 */     GIR_RootConstrainSelectedInstOperands,
     /* 404126 */     // GIR_Coverage, 7093,
     /* 404126 */     GIR_EraseRootFromParent_Done,
     /* 404127 */   // Label 7890: @404127
     /* 404127 */   GIM_Reject,
     /* 404128 */ // Label 7886: @404128
     /* 404128 */ GIM_Reject,
     /* 404129 */ // Label 7835: @404129
     /* 404129 */ GIM_Reject,
     /* 404130 */ // Label 107: @404130
     /* 404130 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7899*/ GIMT_Encode4(404745),
     /* 404141 */ /*GILLT_s16*//*Label 7891*/ GIMT_Encode4(404181),
     /* 404145 */ /*GILLT_s32*//*Label 7892*/ GIMT_Encode4(404219),
     /* 404149 */ /*GILLT_s64*//*Label 7893*/ GIMT_Encode4(404257), GIMT_Encode4(0),
     /* 404157 */ /*GILLT_v2s32*//*Label 7894*/ GIMT_Encode4(404295),
     /* 404161 */ /*GILLT_v2s64*//*Label 7895*/ GIMT_Encode4(404333),
     /* 404165 */ /*GILLT_v4s16*//*Label 7896*/ GIMT_Encode4(404371),
     /* 404169 */ /*GILLT_v4s32*//*Label 7897*/ GIMT_Encode4(404409), GIMT_Encode4(0),
     /* 404177 */ /*GILLT_v8s16*//*Label 7898*/ GIMT_Encode4(404447),
     /* 404181 */ // Label 7891: @404181
     /* 404181 */ GIM_Try, /*On fail goto*//*Label 7900*/ GIMT_Encode4(404218), // Rule ID 593 //
     /* 404186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 404189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 404192 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404199 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404203 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404207 */   // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 404207 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
     /* 404212 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404216 */   GIR_RootConstrainSelectedInstOperands,
     /* 404217 */   // GIR_Coverage, 593,
     /* 404217 */   GIR_Done,
     /* 404218 */ // Label 7900: @404218
     /* 404218 */ GIM_Reject,
     /* 404219 */ // Label 7892: @404219
     /* 404219 */ GIM_Try, /*On fail goto*//*Label 7901*/ GIMT_Encode4(404256), // Rule ID 595 //
     /* 404224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 404227 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 404230 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 404237 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 404241 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 404245 */   // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 404245 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
     /* 404250 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404254 */   GIR_RootConstrainSelectedInstOperands,
     /* 404255 */   // GIR_Coverage, 595,
     /* 404255 */   GIR_Done,
     /* 404256 */ // Label 7901: @404256
     /* 404256 */ GIM_Reject,
     /* 404257 */ // Label 7893: @404257
     /* 404257 */ GIM_Try, /*On fail goto*//*Label 7902*/ GIMT_Encode4(404294), // Rule ID 597 //
     /* 404262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 404265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 404268 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 404271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404275 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404279 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404283 */   // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 404283 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
     /* 404288 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404292 */   GIR_RootConstrainSelectedInstOperands,
     /* 404293 */   // GIR_Coverage, 597,
     /* 404293 */   GIR_Done,
     /* 404294 */ // Label 7902: @404294
     /* 404294 */ GIM_Reject,
     /* 404295 */ // Label 7894: @404295
     /* 404295 */ GIM_Try, /*On fail goto*//*Label 7903*/ GIMT_Encode4(404332), // Rule ID 1231 //
     /* 404300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 404303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 404306 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 404309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404313 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404317 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404321 */   // (strict_fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 404321 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
     /* 404326 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404330 */   GIR_RootConstrainSelectedInstOperands,
     /* 404331 */   // GIR_Coverage, 1231,
     /* 404331 */   GIR_Done,
     /* 404332 */ // Label 7903: @404332
     /* 404332 */ GIM_Reject,
     /* 404333 */ // Label 7895: @404333
     /* 404333 */ GIM_Try, /*On fail goto*//*Label 7904*/ GIMT_Encode4(404370), // Rule ID 1235 //
     /* 404338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 404341 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 404344 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 404347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404351 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404355 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404359 */   // (strict_fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 404359 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
     /* 404364 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404368 */   GIR_RootConstrainSelectedInstOperands,
     /* 404369 */   // GIR_Coverage, 1235,
     /* 404369 */   GIR_Done,
     /* 404370 */ // Label 7904: @404370
     /* 404370 */ GIM_Reject,
     /* 404371 */ // Label 7896: @404371
     /* 404371 */ GIM_Try, /*On fail goto*//*Label 7905*/ GIMT_Encode4(404408), // Rule ID 1227 //
     /* 404376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 404379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 404382 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 404385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404393 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404397 */   // (strict_fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 404397 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
     /* 404402 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404406 */   GIR_RootConstrainSelectedInstOperands,
     /* 404407 */   // GIR_Coverage, 1227,
     /* 404407 */   GIR_Done,
     /* 404408 */ // Label 7905: @404408
     /* 404408 */ GIM_Reject,
     /* 404409 */ // Label 7897: @404409
     /* 404409 */ GIM_Try, /*On fail goto*//*Label 7906*/ GIMT_Encode4(404446), // Rule ID 1233 //
     /* 404414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 404417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 404420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 404423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404431 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404435 */   // (strict_fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 404435 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 404440 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404444 */   GIR_RootConstrainSelectedInstOperands,
     /* 404445 */   // GIR_Coverage, 1233,
     /* 404445 */   GIR_Done,
     /* 404446 */ // Label 7906: @404446
     /* 404446 */ GIM_Reject,
     /* 404447 */ // Label 7898: @404447
     /* 404447 */ GIM_Try, /*On fail goto*//*Label 7907*/ GIMT_Encode4(404744),
     /* 404452 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404455 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 404458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404462 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404466 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404470 */   GIM_Try, /*On fail goto*//*Label 7908*/ GIMT_Encode4(404489), // Rule ID 1229 //
     /* 404475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 404478 */     // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 404478 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
     /* 404483 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 404487 */     GIR_RootConstrainSelectedInstOperands,
     /* 404488 */     // GIR_Coverage, 1229,
     /* 404488 */     GIR_Done,
     /* 404489 */   // Label 7908: @404489
     /* 404489 */   GIM_Try, /*On fail goto*//*Label 7909*/ GIMT_Encode4(404743), // Rule ID 7091 //
     /* 404494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 404497 */     // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 404497 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 404500 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 404504 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404509 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 404513 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 404515 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 404518 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 404522 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404527 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 404531 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 404533 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 404536 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 404540 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404545 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 404548 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 404551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 404553 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 404556 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404560 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404565 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 404571 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404576 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404581 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 404584 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 404588 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404593 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 404596 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 404598 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 404601 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404605 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404610 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 404616 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404621 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404626 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 404629 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 404633 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404638 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 404641 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 404643 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 404646 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 404650 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404655 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 404658 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 404661 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 404663 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 404666 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 404670 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404675 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 404678 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 404680 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 404683 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 404687 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404692 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 404694 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 404697 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 404701 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404706 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 404709 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 404712 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 404715 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404720 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404725 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 404733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404735 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404738 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 404741 */     GIR_RootConstrainSelectedInstOperands,
     /* 404742 */     // GIR_Coverage, 7091,
     /* 404742 */     GIR_EraseRootFromParent_Done,
     /* 404743 */   // Label 7909: @404743
     /* 404743 */   GIM_Reject,
     /* 404744 */ // Label 7907: @404744
     /* 404744 */ GIM_Reject,
     /* 404745 */ // Label 7899: @404745
     /* 404745 */ GIM_Reject,
     /* 404746 */ // Label 108: @404746
     /* 404746 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7918*/ GIMT_Encode4(420352),
     /* 404757 */ /*GILLT_s16*//*Label 7910*/ GIMT_Encode4(404797),
     /* 404761 */ /*GILLT_s32*//*Label 7911*/ GIMT_Encode4(407571),
     /* 404765 */ /*GILLT_s64*//*Label 7912*/ GIMT_Encode4(410501), GIMT_Encode4(0),
     /* 404773 */ /*GILLT_v2s32*//*Label 7913*/ GIMT_Encode4(413431),
     /* 404777 */ /*GILLT_v2s64*//*Label 7914*/ GIMT_Encode4(414952),
     /* 404781 */ /*GILLT_v4s16*//*Label 7915*/ GIMT_Encode4(416473),
     /* 404785 */ /*GILLT_v4s32*//*Label 7916*/ GIMT_Encode4(417652), GIMT_Encode4(0),
     /* 404793 */ /*GILLT_v8s16*//*Label 7917*/ GIMT_Encode4(419173),
     /* 404797 */ // Label 7910: @404797
     /* 404797 */ GIM_Try, /*On fail goto*//*Label 7919*/ GIMT_Encode4(407570),
     /* 404802 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 404805 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404808 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 404811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404815 */   GIM_Try, /*On fail goto*//*Label 7920*/ GIMT_Encode4(404965), // Rule ID 4933 //
     /* 404820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 404823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 404827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404839 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404844 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 404848 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 404852 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404856 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404860 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 404864 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404869 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 404873 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404877 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 404881 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 404885 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404890 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404892 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 404892 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 404895 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404899 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404904 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 404910 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404915 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404920 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 404923 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404927 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404932 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 404938 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404943 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 404951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 404953 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404956 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 404959 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 404963 */     GIR_RootConstrainSelectedInstOperands,
     /* 404964 */     // GIR_Coverage, 4933,
     /* 404964 */     GIR_EraseRootFromParent_Done,
     /* 404965 */   // Label 7920: @404965
     /* 404965 */   GIM_Try, /*On fail goto*//*Label 7921*/ GIMT_Encode4(405112), // Rule ID 4897 //
     /* 404970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 404973 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 404977 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404981 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404985 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404989 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404994 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 404998 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405002 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405006 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 405010 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 405014 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405018 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405022 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 405026 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405031 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 405035 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405039 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 405041 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 405041 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 405044 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405048 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405053 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 405059 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405064 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405069 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405072 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405076 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405081 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405087 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405092 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 405100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 405102 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405105 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 405108 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 405110 */     GIR_RootConstrainSelectedInstOperands,
     /* 405111 */     // GIR_Coverage, 4897,
     /* 405111 */     GIR_EraseRootFromParent_Done,
     /* 405112 */   // Label 7921: @405112
     /* 405112 */   GIM_Try, /*On fail goto*//*Label 7922*/ GIMT_Encode4(405259), // Rule ID 14174 //
     /* 405117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 405120 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405124 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405128 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 405132 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 405136 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405140 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405144 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 405148 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405153 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 405157 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 405161 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405165 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405169 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 405173 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405178 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 405182 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405186 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 405188 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 405188 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 405191 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405195 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405200 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 405206 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405211 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405216 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405219 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405223 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405228 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405234 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405239 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 405247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 405249 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405252 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 405255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 405257 */     GIR_RootConstrainSelectedInstOperands,
     /* 405258 */     // GIR_Coverage, 14174,
     /* 405258 */     GIR_EraseRootFromParent_Done,
     /* 405259 */   // Label 7922: @405259
     /* 405259 */   GIM_Try, /*On fail goto*//*Label 7923*/ GIMT_Encode4(405390), // Rule ID 6152 //
     /* 405264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 405267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 405283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405288 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 405292 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405296 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405300 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 405304 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 405308 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405312 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405316 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 405320 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 405325 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 405329 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405333 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405337 */     // MIs[4] Operand 1
     /* 405337 */     // No operand predicates
     /* 405337 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405341 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 405343 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 405343 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405346 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405350 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405355 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405361 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405366 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 405374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 405378 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 405385 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 405388 */     GIR_RootConstrainSelectedInstOperands,
     /* 405389 */     // GIR_Coverage, 6152,
     /* 405389 */     GIR_EraseRootFromParent_Done,
     /* 405390 */   // Label 7923: @405390
     /* 405390 */   GIM_Try, /*On fail goto*//*Label 7924*/ GIMT_Encode4(405521), // Rule ID 6184 //
     /* 405395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 405398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 405414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 405419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 405423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405427 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405431 */     // MIs[2] Operand 1
     /* 405431 */     // No operand predicates
     /* 405431 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 405435 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405439 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 405443 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 405447 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405451 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405455 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 405459 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405464 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 405468 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405472 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 405474 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 405474 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405477 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405481 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405486 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405492 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405497 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 405505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405507 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 405509 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 405516 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 405519 */     GIR_RootConstrainSelectedInstOperands,
     /* 405520 */     // GIR_Coverage, 6184,
     /* 405520 */     GIR_EraseRootFromParent_Done,
     /* 405521 */   // Label 7924: @405521
     /* 405521 */   GIM_Try, /*On fail goto*//*Label 7925*/ GIMT_Encode4(405652), // Rule ID 6248 //
     /* 405526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 405529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 405541 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 405545 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405549 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405553 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 405557 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405562 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 405566 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 405570 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405574 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405578 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 405582 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 405587 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 405591 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405595 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405599 */     // MIs[4] Operand 1
     /* 405599 */     // No operand predicates
     /* 405599 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405603 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 405605 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 405605 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405608 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405612 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405617 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405628 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 405636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 405640 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 405647 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 405650 */     GIR_RootConstrainSelectedInstOperands,
     /* 405651 */     // GIR_Coverage, 6248,
     /* 405651 */     GIR_EraseRootFromParent_Done,
     /* 405652 */   // Label 7925: @405652
     /* 405652 */   GIM_Try, /*On fail goto*//*Label 7926*/ GIMT_Encode4(405783), // Rule ID 6216 //
     /* 405657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 405660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 405668 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 405672 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 405676 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405680 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405684 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 405688 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 405693 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 405697 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405701 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405705 */     // MIs[3] Operand 1
     /* 405705 */     // No operand predicates
     /* 405705 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 405709 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405713 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405717 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 405721 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405726 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 405730 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405734 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 405736 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 405736 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405739 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405743 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405748 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405754 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405759 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 405767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405769 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 405771 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 405778 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 405781 */     GIR_RootConstrainSelectedInstOperands,
     /* 405782 */     // GIR_Coverage, 6216,
     /* 405782 */     GIR_EraseRootFromParent_Done,
     /* 405783 */   // Label 7926: @405783
     /* 405783 */   GIM_Try, /*On fail goto*//*Label 7927*/ GIMT_Encode4(405918), // Rule ID 2462 //
     /* 405788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 405791 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405795 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405799 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405803 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 405807 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405812 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 405816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405824 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405828 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 405832 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405837 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 405841 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405845 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405847 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 405847 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 405850 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405854 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405859 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 405865 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405870 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405875 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405878 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405882 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405887 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 405893 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405898 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 405906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 405908 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405911 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 405914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 405916 */     GIR_RootConstrainSelectedInstOperands,
     /* 405917 */     // GIR_Coverage, 2462,
     /* 405917 */     GIR_EraseRootFromParent_Done,
     /* 405918 */   // Label 7927: @405918
     /* 405918 */   GIM_Try, /*On fail goto*//*Label 7928*/ GIMT_Encode4(406037), // Rule ID 6120 //
     /* 405923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 405926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405934 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405938 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 405942 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405947 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 405951 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405955 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 405959 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 405963 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 405967 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 405972 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 405976 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405980 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405984 */     // MIs[3] Operand 1
     /* 405984 */     // No operand predicates
     /* 405984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405988 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 405990 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 405990 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 405993 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 405997 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406002 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 406008 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406013 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 406021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406023 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 406025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 406032 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 406035 */     GIR_RootConstrainSelectedInstOperands,
     /* 406036 */     // GIR_Coverage, 6120,
     /* 406036 */     GIR_EraseRootFromParent_Done,
     /* 406037 */   // Label 7928: @406037
     /* 406037 */   GIM_Try, /*On fail goto*//*Label 7929*/ GIMT_Encode4(406156), // Rule ID 2537 //
     /* 406042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 406045 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406049 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406053 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406057 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 406061 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 406066 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 406070 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 406074 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 406078 */     // MIs[2] Operand 1
     /* 406078 */     // No operand predicates
     /* 406078 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 406082 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406086 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406090 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 406094 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406099 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 406103 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406107 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 406109 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 406109 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406112 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406116 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406121 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 406127 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406132 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 406140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 406144 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406147 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 406151 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 406154 */     GIR_RootConstrainSelectedInstOperands,
     /* 406155 */     // GIR_Coverage, 2537,
     /* 406155 */     GIR_EraseRootFromParent_Done,
     /* 406156 */   // Label 7929: @406156
     /* 406156 */   GIM_Try, /*On fail goto*//*Label 7930*/ GIMT_Encode4(406256), // Rule ID 4895 //
     /* 406161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 406180 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406185 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 406189 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406193 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406197 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 406201 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406206 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406210 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406212 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 406212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406224 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 406230 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406235 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 406243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406245 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 406252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 406254 */     GIR_RootConstrainSelectedInstOperands,
     /* 406255 */     // GIR_Coverage, 4895,
     /* 406255 */     GIR_EraseRootFromParent_Done,
     /* 406256 */   // Label 7930: @406256
     /* 406256 */   GIM_Try, /*On fail goto*//*Label 7931*/ GIMT_Encode4(406356), // Rule ID 4931 //
     /* 406261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406264 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406268 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406272 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406276 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 406280 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406285 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 406289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406293 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 406297 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406301 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 406305 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406310 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406312 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 406312 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406315 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406319 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406324 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 406330 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406335 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 406343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406345 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 406350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 406354 */     GIR_RootConstrainSelectedInstOperands,
     /* 406355 */     // GIR_Coverage, 4931,
     /* 406355 */     GIR_EraseRootFromParent_Done,
     /* 406356 */   // Label 7931: @406356
     /* 406356 */   GIM_Try, /*On fail goto*//*Label 7932*/ GIMT_Encode4(406453), // Rule ID 14170 //
     /* 406361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 406376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 406380 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406384 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406388 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 406392 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406397 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 406401 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406405 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406409 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406411 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 406411 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406414 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406418 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406423 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 406429 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406434 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 406442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 406446 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406449 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 406451 */     GIR_RootConstrainSelectedInstOperands,
     /* 406452 */     // GIR_Coverage, 14170,
     /* 406452 */     GIR_EraseRootFromParent_Done,
     /* 406453 */   // Label 7932: @406453
     /* 406453 */   GIM_Try, /*On fail goto*//*Label 7933*/ GIMT_Encode4(406553), // Rule ID 14172 //
     /* 406458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 406473 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406478 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406482 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406486 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406490 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 406494 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406499 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 406503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406507 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406509 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 406509 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406512 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406516 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406521 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 406527 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406532 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 406540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406542 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 406549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 406551 */     GIR_RootConstrainSelectedInstOperands,
     /* 406552 */     // GIR_Coverage, 14172,
     /* 406552 */     GIR_EraseRootFromParent_Done,
     /* 406553 */   // Label 7933: @406553
     /* 406553 */   GIM_Try, /*On fail goto*//*Label 7934*/ GIMT_Encode4(406653), // Rule ID 4929 //
     /* 406558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 406569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 406581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406586 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 406590 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 406594 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406598 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 406602 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406607 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406609 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 406609 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406612 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406616 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406621 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 406627 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406632 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 406640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406642 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 406644 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 406651 */     GIR_RootConstrainSelectedInstOperands,
     /* 406652 */     // GIR_Coverage, 4929,
     /* 406652 */     GIR_EraseRootFromParent_Done,
     /* 406653 */   // Label 7934: @406653
     /* 406653 */   GIM_Try, /*On fail goto*//*Label 7935*/ GIMT_Encode4(406750), // Rule ID 4893 //
     /* 406658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 406661 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 406669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 406677 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 406681 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406685 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406689 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 406693 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406698 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 406702 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406706 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406708 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 406708 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 406711 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 406715 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406720 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 406726 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406731 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 406739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 406741 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 406743 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 406748 */     GIR_RootConstrainSelectedInstOperands,
     /* 406749 */     // GIR_Coverage, 4893,
     /* 406749 */     GIR_EraseRootFromParent_Done,
     /* 406750 */   // Label 7935: @406750
     /* 406750 */   GIM_Try, /*On fail goto*//*Label 7936*/ GIMT_Encode4(406834), // Rule ID 6182 //
     /* 406755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 406758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406770 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 406774 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 406779 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 406783 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 406787 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 406791 */     // MIs[2] Operand 1
     /* 406791 */     // No operand predicates
     /* 406791 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 406795 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406799 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 406803 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406808 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406812 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 406814 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 406814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 406817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406819 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 406821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 406825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 406829 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 406832 */     GIR_RootConstrainSelectedInstOperands,
     /* 406833 */     // GIR_Coverage, 6182,
     /* 406833 */     GIR_EraseRootFromParent_Done,
     /* 406834 */   // Label 7936: @406834
     /* 406834 */   GIM_Try, /*On fail goto*//*Label 7937*/ GIMT_Encode4(406915), // Rule ID 6214 //
     /* 406839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 406842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 406854 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 406858 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406862 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406866 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 406870 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 406875 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 406879 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 406883 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 406887 */     // MIs[3] Operand 1
     /* 406887 */     // No operand predicates
     /* 406887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406891 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406895 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 406897 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 406897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 406900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 406904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 406906 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 406910 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 406913 */     GIR_RootConstrainSelectedInstOperands,
     /* 406914 */     // GIR_Coverage, 6214,
     /* 406914 */     GIR_EraseRootFromParent_Done,
     /* 406915 */   // Label 7937: @406915
     /* 406915 */   GIM_Try, /*On fail goto*//*Label 7938*/ GIMT_Encode4(406999), // Rule ID 6246 //
     /* 406920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 406923 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406927 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 406931 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 406935 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406940 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406944 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 406948 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 406952 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 406956 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 406961 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 406965 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 406969 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 406973 */     // MIs[3] Operand 1
     /* 406973 */     // No operand predicates
     /* 406973 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 406977 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 406979 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 406979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 406982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406984 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 406986 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 406990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 406994 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 406997 */     GIR_RootConstrainSelectedInstOperands,
     /* 406998 */     // GIR_Coverage, 6246,
     /* 406998 */     GIR_EraseRootFromParent_Done,
     /* 406999 */   // Label 7938: @406999
     /* 406999 */   GIM_Try, /*On fail goto*//*Label 7939*/ GIMT_Encode4(407080), // Rule ID 6150 //
     /* 407004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 407007 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 407023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 407027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407031 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 407035 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 407039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 407044 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 407048 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407052 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 407056 */     // MIs[3] Operand 1
     /* 407056 */     // No operand predicates
     /* 407056 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407060 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407062 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 407062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 407065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 407069 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 407075 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 407078 */     GIR_RootConstrainSelectedInstOperands,
     /* 407079 */     // GIR_Coverage, 6150,
     /* 407079 */     GIR_EraseRootFromParent_Done,
     /* 407080 */   // Label 7939: @407080
     /* 407080 */   GIM_Try, /*On fail goto*//*Label 7940*/ GIMT_Encode4(407165), // Rule ID 2460 //
     /* 407085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 407100 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407104 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407109 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 407113 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407117 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407121 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407123 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 407123 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 407126 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407130 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407135 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 407141 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407146 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 407154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407156 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407159 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 407161 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 407163 */     GIR_RootConstrainSelectedInstOperands,
     /* 407164 */     // GIR_Coverage, 2460,
     /* 407164 */     GIR_EraseRootFromParent_Done,
     /* 407165 */   // Label 7940: @407165
     /* 407165 */   GIM_Try, /*On fail goto*//*Label 7941*/ GIMT_Encode4(407250), // Rule ID 2458 //
     /* 407170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407173 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 407189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407193 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407198 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 407202 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407206 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407208 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 407208 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 407211 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407215 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407220 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 407226 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 407239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407241 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407243 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407246 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 407248 */     GIR_RootConstrainSelectedInstOperands,
     /* 407249 */     // GIR_Coverage, 2458,
     /* 407249 */     GIR_EraseRootFromParent_Done,
     /* 407250 */   // Label 7941: @407250
     /* 407250 */   GIM_Try, /*On fail goto*//*Label 7942*/ GIMT_Encode4(407319), // Rule ID 2535 //
     /* 407255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 407258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 407270 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407274 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 407279 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407283 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407287 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 407291 */     // MIs[2] Operand 1
     /* 407291 */     // No operand predicates
     /* 407291 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407295 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407299 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 407301 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 407301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 407304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 407308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 407310 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 407314 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 407317 */     GIR_RootConstrainSelectedInstOperands,
     /* 407318 */     // GIR_Coverage, 2535,
     /* 407318 */     GIR_EraseRootFromParent_Done,
     /* 407319 */   // Label 7942: @407319
     /* 407319 */   GIM_Try, /*On fail goto*//*Label 7943*/ GIMT_Encode4(407388), // Rule ID 6118 //
     /* 407324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 407327 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 407343 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407347 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 407352 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407356 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407360 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 407364 */     // MIs[2] Operand 1
     /* 407364 */     // No operand predicates
     /* 407364 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407368 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 407370 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 407370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 407373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407375 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 407377 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 407383 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 407386 */     GIR_RootConstrainSelectedInstOperands,
     /* 407387 */     // GIR_Coverage, 6118,
     /* 407387 */     GIR_EraseRootFromParent_Done,
     /* 407388 */   // Label 7943: @407388
     /* 407388 */   GIM_Try, /*On fail goto*//*Label 7944*/ GIMT_Encode4(407438), // Rule ID 13601 //
     /* 407393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407396 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407400 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407404 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 407408 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407417 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407421 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407423 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 407423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 407426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 407430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 407434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 407436 */     GIR_RootConstrainSelectedInstOperands,
     /* 407437 */     // GIR_Coverage, 13601,
     /* 407437 */     GIR_EraseRootFromParent_Done,
     /* 407438 */   // Label 7944: @407438
     /* 407438 */   GIM_Try, /*On fail goto*//*Label 7945*/ GIMT_Encode4(407488), // Rule ID 647 //
     /* 407443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 407462 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407467 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407471 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407473 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 407473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 407476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407478 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 407484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 407486 */     GIR_RootConstrainSelectedInstOperands,
     /* 407487 */     // GIR_Coverage, 647,
     /* 407487 */     GIR_EraseRootFromParent_Done,
     /* 407488 */   // Label 7945: @407488
     /* 407488 */   GIM_Try, /*On fail goto*//*Label 7946*/ GIMT_Encode4(407538), // Rule ID 659 //
     /* 407493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407496 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407500 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 407508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 407516 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407521 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407523 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 407523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 407526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407528 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407530 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 407532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 407536 */     GIR_RootConstrainSelectedInstOperands,
     /* 407537 */     // GIR_Coverage, 659,
     /* 407537 */     GIR_EraseRootFromParent_Done,
     /* 407538 */   // Label 7946: @407538
     /* 407538 */   GIM_Try, /*On fail goto*//*Label 7947*/ GIMT_Encode4(407569), // Rule ID 641 //
     /* 407543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 407546 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407554 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 407558 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 407558 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 407563 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 407567 */     GIR_RootConstrainSelectedInstOperands,
     /* 407568 */     // GIR_Coverage, 641,
     /* 407568 */     GIR_Done,
     /* 407569 */   // Label 7947: @407569
     /* 407569 */   GIM_Reject,
     /* 407570 */ // Label 7919: @407570
     /* 407570 */ GIM_Reject,
     /* 407571 */ // Label 7911: @407571
     /* 407571 */ GIM_Try, /*On fail goto*//*Label 7948*/ GIMT_Encode4(410500),
     /* 407576 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 407579 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407582 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 407585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407589 */   GIM_Try, /*On fail goto*//*Label 7949*/ GIMT_Encode4(407739), // Rule ID 4939 //
     /* 407594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 407597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407609 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407613 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407618 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 407622 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 407626 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407630 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407634 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 407638 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407643 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 407647 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407651 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407655 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 407659 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407664 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407666 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 407666 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 407669 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407673 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407678 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 407684 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407689 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407694 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 407697 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407701 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407706 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 407712 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407717 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 407725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407727 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407730 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 407733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 407737 */     GIR_RootConstrainSelectedInstOperands,
     /* 407738 */     // GIR_Coverage, 4939,
     /* 407738 */     GIR_EraseRootFromParent_Done,
     /* 407739 */   // Label 7949: @407739
     /* 407739 */   GIM_Try, /*On fail goto*//*Label 7950*/ GIMT_Encode4(407886), // Rule ID 4903 //
     /* 407744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 407747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407751 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407755 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407759 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407763 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407768 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 407772 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 407776 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407780 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 407784 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 407788 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407792 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407796 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 407800 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407805 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 407809 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407813 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407815 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 407815 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 407818 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407822 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407827 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 407833 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407838 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407843 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 407846 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407850 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407855 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 407861 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407866 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 407874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 407876 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407879 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 407882 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 407884 */     GIR_RootConstrainSelectedInstOperands,
     /* 407885 */     // GIR_Coverage, 4903,
     /* 407885 */     GIR_EraseRootFromParent_Done,
     /* 407886 */   // Label 7950: @407886
     /* 407886 */   GIM_Try, /*On fail goto*//*Label 7951*/ GIMT_Encode4(408033), // Rule ID 14180 //
     /* 407891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 407894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 407902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 407906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 407910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407914 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407918 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 407922 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407927 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 407931 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 407935 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407939 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 407943 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 407947 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407952 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 407956 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407960 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407962 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 407962 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 407965 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407969 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407974 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 407980 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407985 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407990 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 407993 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407997 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408002 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408008 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408013 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 408021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 408023 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408026 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 408029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 408031 */     GIR_RootConstrainSelectedInstOperands,
     /* 408032 */     // GIR_Coverage, 14180,
     /* 408032 */     GIR_EraseRootFromParent_Done,
     /* 408033 */   // Label 7951: @408033
     /* 408033 */   GIM_Try, /*On fail goto*//*Label 7952*/ GIMT_Encode4(408164), // Rule ID 6168 //
     /* 408038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408045 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408049 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408053 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408057 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408062 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 408066 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408070 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 408074 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 408078 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 408082 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408086 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408090 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 408094 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408099 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 408103 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408107 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408111 */     // MIs[4] Operand 1
     /* 408111 */     // No operand predicates
     /* 408111 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408115 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 408117 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408117 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408120 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408124 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408129 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408135 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408140 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 408148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408150 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408152 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 408159 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 408162 */     GIR_RootConstrainSelectedInstOperands,
     /* 408163 */     // GIR_Coverage, 6168,
     /* 408163 */     GIR_EraseRootFromParent_Done,
     /* 408164 */   // Label 7952: @408164
     /* 408164 */   GIM_Try, /*On fail goto*//*Label 7953*/ GIMT_Encode4(408295), // Rule ID 6200 //
     /* 408169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408172 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408176 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408180 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408184 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408188 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408193 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 408197 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408201 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408205 */     // MIs[2] Operand 1
     /* 408205 */     // No operand predicates
     /* 408205 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 408209 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 408213 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 408217 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 408221 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408225 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408229 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 408233 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408238 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 408242 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408246 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 408248 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408248 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408251 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408255 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408260 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408266 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408271 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 408279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408281 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408283 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 408290 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 408293 */     GIR_RootConstrainSelectedInstOperands,
     /* 408294 */     // GIR_Coverage, 6200,
     /* 408294 */     GIR_EraseRootFromParent_Done,
     /* 408295 */   // Label 7953: @408295
     /* 408295 */   GIM_Try, /*On fail goto*//*Label 7954*/ GIMT_Encode4(408426), // Rule ID 6264 //
     /* 408300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408303 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408307 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 408311 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 408315 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 408319 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408323 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408327 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 408331 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408336 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 408340 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 408344 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408348 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408352 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 408356 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408361 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 408365 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408369 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408373 */     // MIs[4] Operand 1
     /* 408373 */     // No operand predicates
     /* 408373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408377 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 408379 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408379 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408382 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408386 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408391 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408397 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408402 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 408410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408412 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408414 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408417 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 408421 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 408424 */     GIR_RootConstrainSelectedInstOperands,
     /* 408425 */     // GIR_Coverage, 6264,
     /* 408425 */     GIR_EraseRootFromParent_Done,
     /* 408426 */   // Label 7954: @408426
     /* 408426 */   GIM_Try, /*On fail goto*//*Label 7955*/ GIMT_Encode4(408557), // Rule ID 6232 //
     /* 408431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 408442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 408446 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 408450 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408454 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408458 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 408462 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408467 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 408471 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408475 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408479 */     // MIs[3] Operand 1
     /* 408479 */     // No operand predicates
     /* 408479 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 408483 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408487 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408491 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 408495 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408500 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 408504 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408508 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 408510 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408510 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408513 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408517 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408522 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408528 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408533 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 408541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408543 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 408552 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 408555 */     GIR_RootConstrainSelectedInstOperands,
     /* 408556 */     // GIR_Coverage, 6232,
     /* 408556 */     GIR_EraseRootFromParent_Done,
     /* 408557 */   // Label 7955: @408557
     /* 408557 */   GIM_Try, /*On fail goto*//*Label 7956*/ GIMT_Encode4(408692), // Rule ID 2468 //
     /* 408562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 408565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408586 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 408590 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408594 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408598 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408602 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 408606 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408611 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 408615 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408619 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408621 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 408621 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 408624 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408628 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408633 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 408639 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408644 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408649 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408652 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408656 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408661 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408667 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408672 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 408680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 408682 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408685 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 408688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 408690 */     GIR_RootConstrainSelectedInstOperands,
     /* 408691 */     // GIR_Coverage, 2468,
     /* 408691 */     GIR_EraseRootFromParent_Done,
     /* 408692 */   // Label 7956: @408692
     /* 408692 */   GIM_Try, /*On fail goto*//*Label 7957*/ GIMT_Encode4(408811), // Rule ID 6136 //
     /* 408697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408712 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408716 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408721 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 408725 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408729 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408733 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408737 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 408741 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408746 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 408750 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408754 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408758 */     // MIs[3] Operand 1
     /* 408758 */     // No operand predicates
     /* 408758 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408762 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 408764 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408764 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408767 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408771 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408776 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408782 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408787 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 408795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408797 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408799 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 408806 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 408809 */     GIR_RootConstrainSelectedInstOperands,
     /* 408810 */     // GIR_Coverage, 6136,
     /* 408810 */     GIR_EraseRootFromParent_Done,
     /* 408811 */   // Label 7957: @408811
     /* 408811 */   GIM_Try, /*On fail goto*//*Label 7958*/ GIMT_Encode4(408930), // Rule ID 2553 //
     /* 408816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 408844 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408848 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 408852 */     // MIs[2] Operand 1
     /* 408852 */     // No operand predicates
     /* 408852 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 408856 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408860 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408864 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 408868 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408873 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 408877 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408881 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 408883 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 408883 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408886 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408890 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408895 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 408901 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408906 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 408914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408916 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 408918 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 408925 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 408928 */     GIR_RootConstrainSelectedInstOperands,
     /* 408929 */     // GIR_Coverage, 2553,
     /* 408929 */     GIR_EraseRootFromParent_Done,
     /* 408930 */   // Label 7958: @408930
     /* 408930 */   GIM_Try, /*On fail goto*//*Label 7959*/ GIMT_Encode4(409030), // Rule ID 4901 //
     /* 408935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 408938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 408946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 408950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 408954 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408959 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 408963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 408971 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 408975 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408980 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408984 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408986 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 408986 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 408989 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 408993 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408998 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 409004 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409009 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 409017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409019 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 409026 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 409028 */     GIR_RootConstrainSelectedInstOperands,
     /* 409029 */     // GIR_Coverage, 4901,
     /* 409029 */     GIR_EraseRootFromParent_Done,
     /* 409030 */   // Label 7959: @409030
     /* 409030 */   GIM_Try, /*On fail goto*//*Label 7960*/ GIMT_Encode4(409130), // Rule ID 4937 //
     /* 409035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 409038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409042 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409046 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409050 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 409054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409059 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 409063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409067 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 409071 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409075 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 409079 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409084 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409086 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 409086 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 409089 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 409093 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409098 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 409104 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409109 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 409117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409119 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 409124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 409128 */     GIR_RootConstrainSelectedInstOperands,
     /* 409129 */     // GIR_Coverage, 4937,
     /* 409129 */     GIR_EraseRootFromParent_Done,
     /* 409130 */   // Label 7960: @409130
     /* 409130 */   GIM_Try, /*On fail goto*//*Label 7961*/ GIMT_Encode4(409227), // Rule ID 14176 //
     /* 409135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 409138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409146 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409150 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409154 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409158 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409162 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409166 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409171 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 409175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409183 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409185 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 409185 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 409188 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 409192 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409197 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 409203 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409208 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 409216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 409220 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 409225 */     GIR_RootConstrainSelectedInstOperands,
     /* 409226 */     // GIR_Coverage, 14176,
     /* 409226 */     GIR_EraseRootFromParent_Done,
     /* 409227 */   // Label 7961: @409227
     /* 409227 */   GIM_Try, /*On fail goto*//*Label 7962*/ GIMT_Encode4(409327), // Rule ID 14178 //
     /* 409232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 409235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409247 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409252 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409256 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409260 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409264 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409268 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409273 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 409277 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409281 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409283 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 409283 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 409286 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 409290 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409295 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 409301 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409306 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 409314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409316 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409319 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 409323 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 409325 */     GIR_RootConstrainSelectedInstOperands,
     /* 409326 */     // GIR_Coverage, 14178,
     /* 409326 */     GIR_EraseRootFromParent_Done,
     /* 409327 */   // Label 7962: @409327
     /* 409327 */   GIM_Try, /*On fail goto*//*Label 7963*/ GIMT_Encode4(409427), // Rule ID 4935 //
     /* 409332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 409335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 409343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409351 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 409355 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409360 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 409364 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 409368 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409372 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 409376 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409381 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409383 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 409383 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 409386 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 409390 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409395 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 409401 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409406 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 409414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409416 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 409418 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 409425 */     GIR_RootConstrainSelectedInstOperands,
     /* 409426 */     // GIR_Coverage, 4935,
     /* 409426 */     GIR_EraseRootFromParent_Done,
     /* 409427 */   // Label 7963: @409427
     /* 409427 */   GIM_Try, /*On fail goto*//*Label 7964*/ GIMT_Encode4(409524), // Rule ID 4899 //
     /* 409432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 409435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 409443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409451 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409455 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409459 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409463 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409467 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409472 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 409476 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409480 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409482 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 409482 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 409485 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 409489 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409494 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 409500 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409505 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 409513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 409515 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 409517 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 409522 */     GIR_RootConstrainSelectedInstOperands,
     /* 409523 */     // GIR_Coverage, 4899,
     /* 409523 */     GIR_EraseRootFromParent_Done,
     /* 409524 */   // Label 7964: @409524
     /* 409524 */   GIM_Try, /*On fail goto*//*Label 7965*/ GIMT_Encode4(409602), // Rule ID 6286 //
     /* 409529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409541 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 409545 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409549 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409553 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409557 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409562 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 409566 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409570 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409574 */     // MIs[3] Operand 1
     /* 409574 */     // No operand predicates
     /* 409574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409578 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409582 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409584 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409589 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 409593 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 409597 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 409600 */     GIR_RootConstrainSelectedInstOperands,
     /* 409601 */     // GIR_Coverage, 6286,
     /* 409601 */     GIR_EraseRootFromParent_Done,
     /* 409602 */   // Label 7965: @409602
     /* 409602 */   GIM_Try, /*On fail goto*//*Label 7966*/ GIMT_Encode4(409686), // Rule ID 6198 //
     /* 409607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 409610 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409614 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409618 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409622 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 409626 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409631 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 409635 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409639 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409643 */     // MIs[2] Operand 1
     /* 409643 */     // No operand predicates
     /* 409643 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 409647 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409651 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 409655 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409660 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409664 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409666 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409671 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409673 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 409677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 409681 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 409684 */     GIR_RootConstrainSelectedInstOperands,
     /* 409685 */     // GIR_Coverage, 6198,
     /* 409685 */     GIR_EraseRootFromParent_Done,
     /* 409686 */   // Label 7966: @409686
     /* 409686 */   GIM_Try, /*On fail goto*//*Label 7967*/ GIMT_Encode4(409767), // Rule ID 6230 //
     /* 409691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 409694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409706 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409710 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409714 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409718 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409722 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409727 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 409731 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409735 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409739 */     // MIs[3] Operand 1
     /* 409739 */     // No operand predicates
     /* 409739 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409743 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409747 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409749 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409754 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 409758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 409762 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 409765 */     GIR_RootConstrainSelectedInstOperands,
     /* 409766 */     // GIR_Coverage, 6230,
     /* 409766 */     GIR_EraseRootFromParent_Done,
     /* 409767 */   // Label 7967: @409767
     /* 409767 */   GIM_Try, /*On fail goto*//*Label 7968*/ GIMT_Encode4(409851), // Rule ID 6262 //
     /* 409772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 409775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409783 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409787 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409800 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409804 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409808 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409813 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 409817 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409821 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409825 */     // MIs[3] Operand 1
     /* 409825 */     // No operand predicates
     /* 409825 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409829 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409831 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409836 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409838 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 409842 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 409846 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 409849 */     GIR_RootConstrainSelectedInstOperands,
     /* 409850 */     // GIR_Coverage, 6262,
     /* 409850 */     GIR_EraseRootFromParent_Done,
     /* 409851 */   // Label 7968: @409851
     /* 409851 */   GIM_Try, /*On fail goto*//*Label 7969*/ GIMT_Encode4(409929), // Rule ID 6308 //
     /* 409856 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409860 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 409864 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409868 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409872 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 409876 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409880 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409884 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409888 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409893 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 409897 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409901 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409905 */     // MIs[3] Operand 1
     /* 409905 */     // No operand predicates
     /* 409905 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409909 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409911 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409916 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409918 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 409920 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 409924 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 409927 */     GIR_RootConstrainSelectedInstOperands,
     /* 409928 */     // GIR_Coverage, 6308,
     /* 409928 */     GIR_EraseRootFromParent_Done,
     /* 409929 */   // Label 7969: @409929
     /* 409929 */   GIM_Try, /*On fail goto*//*Label 7970*/ GIMT_Encode4(410010), // Rule ID 6166 //
     /* 409934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 409937 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409941 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 409945 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 409949 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 409953 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 409957 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 409961 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 409965 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 409969 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 409974 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 409978 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 409982 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 409986 */     // MIs[3] Operand 1
     /* 409986 */     // No operand predicates
     /* 409986 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 409990 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 409992 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 409992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 409995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409997 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 409999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 410001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 410005 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 410008 */     GIR_RootConstrainSelectedInstOperands,
     /* 410009 */     // GIR_Coverage, 6166,
     /* 410009 */     GIR_EraseRootFromParent_Done,
     /* 410010 */   // Label 7970: @410010
     /* 410010 */   GIM_Try, /*On fail goto*//*Label 7971*/ GIMT_Encode4(410095), // Rule ID 2466 //
     /* 410015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 410030 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410034 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410039 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 410043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410047 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410051 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 410053 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 410053 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 410056 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410060 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410065 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 410071 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410076 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 410084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410086 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 410091 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410093 */     GIR_RootConstrainSelectedInstOperands,
     /* 410094 */     // GIR_Coverage, 2466,
     /* 410094 */     GIR_EraseRootFromParent_Done,
     /* 410095 */   // Label 7971: @410095
     /* 410095 */   GIM_Try, /*On fail goto*//*Label 7972*/ GIMT_Encode4(410180), // Rule ID 2464 //
     /* 410100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410103 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 410111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410115 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 410119 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410123 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410128 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 410132 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410136 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 410138 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 410138 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 410141 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410145 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410150 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 410156 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410161 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 410169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410171 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 410173 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410178 */     GIR_RootConstrainSelectedInstOperands,
     /* 410179 */     // GIR_Coverage, 2464,
     /* 410179 */     GIR_EraseRootFromParent_Done,
     /* 410180 */   // Label 7972: @410180
     /* 410180 */   GIM_Try, /*On fail goto*//*Label 7973*/ GIMT_Encode4(410249), // Rule ID 2551 //
     /* 410185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 410188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410196 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 410200 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410204 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410209 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 410213 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 410217 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 410221 */     // MIs[2] Operand 1
     /* 410221 */     // No operand predicates
     /* 410221 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410225 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410229 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410231 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 410231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 410234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 410238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 410240 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 410244 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 410247 */     GIR_RootConstrainSelectedInstOperands,
     /* 410248 */     // GIR_Coverage, 2551,
     /* 410248 */     GIR_EraseRootFromParent_Done,
     /* 410249 */   // Label 7973: @410249
     /* 410249 */   GIM_Try, /*On fail goto*//*Label 7974*/ GIMT_Encode4(410318), // Rule ID 6134 //
     /* 410254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 410257 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410261 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 410265 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410269 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 410273 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410277 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 410286 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 410290 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 410294 */     // MIs[2] Operand 1
     /* 410294 */     // No operand predicates
     /* 410294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410298 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410300 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 410300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 410303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 410307 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 410309 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 410313 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 410316 */     GIR_RootConstrainSelectedInstOperands,
     /* 410317 */     // GIR_Coverage, 6134,
     /* 410317 */     GIR_EraseRootFromParent_Done,
     /* 410318 */   // Label 7974: @410318
     /* 410318 */   GIM_Try, /*On fail goto*//*Label 7975*/ GIMT_Encode4(410368), // Rule ID 13603 //
     /* 410323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 410338 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410347 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410351 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 410353 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 410353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 410356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 410360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 410364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410366 */     GIR_RootConstrainSelectedInstOperands,
     /* 410367 */     // GIR_Coverage, 13603,
     /* 410367 */     GIR_EraseRootFromParent_Done,
     /* 410368 */   // Label 7975: @410368
     /* 410368 */   GIM_Try, /*On fail goto*//*Label 7976*/ GIMT_Encode4(410418), // Rule ID 649 //
     /* 410373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 410384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 410392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410397 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410401 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 410403 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 410403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 410406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410408 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 410410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 410414 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410416 */     GIR_RootConstrainSelectedInstOperands,
     /* 410417 */     // GIR_Coverage, 649,
     /* 410417 */     GIR_EraseRootFromParent_Done,
     /* 410418 */   // Label 7976: @410418
     /* 410418 */   GIM_Try, /*On fail goto*//*Label 7977*/ GIMT_Encode4(410468), // Rule ID 661 //
     /* 410423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 410438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 410446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 410453 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 410453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 410456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410458 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 410460 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 410462 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 410466 */     GIR_RootConstrainSelectedInstOperands,
     /* 410467 */     // GIR_Coverage, 661,
     /* 410467 */     GIR_EraseRootFromParent_Done,
     /* 410468 */   // Label 7977: @410468
     /* 410468 */   GIM_Try, /*On fail goto*//*Label 7978*/ GIMT_Encode4(410499), // Rule ID 643 //
     /* 410473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410476 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410480 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410484 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410488 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 410488 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 410493 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 410497 */     GIR_RootConstrainSelectedInstOperands,
     /* 410498 */     // GIR_Coverage, 643,
     /* 410498 */     GIR_Done,
     /* 410499 */   // Label 7978: @410499
     /* 410499 */   GIM_Reject,
     /* 410500 */ // Label 7948: @410500
     /* 410500 */ GIM_Reject,
     /* 410501 */ // Label 7912: @410501
     /* 410501 */ GIM_Try, /*On fail goto*//*Label 7979*/ GIMT_Encode4(413430),
     /* 410506 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 410509 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 410512 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 410515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410519 */   GIM_Try, /*On fail goto*//*Label 7980*/ GIMT_Encode4(410669), // Rule ID 4945 //
     /* 410524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410543 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410548 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 410552 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410556 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410560 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410564 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 410568 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410573 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 410577 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 410581 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410585 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 410589 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410594 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 410596 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 410596 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 410599 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410603 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410608 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 410614 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410619 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410624 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 410627 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410631 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410636 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 410642 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410647 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 410655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410657 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410660 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 410663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 410667 */     GIR_RootConstrainSelectedInstOperands,
     /* 410668 */     // GIR_Coverage, 4945,
     /* 410668 */     GIR_EraseRootFromParent_Done,
     /* 410669 */   // Label 7980: @410669
     /* 410669 */   GIM_Try, /*On fail goto*//*Label 7981*/ GIMT_Encode4(410816), // Rule ID 4909 //
     /* 410674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410677 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410681 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410685 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410689 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410693 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410698 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 410702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410710 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 410714 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 410718 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410722 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410726 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 410730 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410735 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 410739 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410743 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 410745 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 410745 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 410748 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410752 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410757 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 410763 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410768 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410773 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 410776 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410780 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410785 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 410791 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410796 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 410804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410806 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410809 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 410812 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410814 */     GIR_RootConstrainSelectedInstOperands,
     /* 410815 */     // GIR_Coverage, 4909,
     /* 410815 */     GIR_EraseRootFromParent_Done,
     /* 410816 */   // Label 7981: @410816
     /* 410816 */   GIM_Try, /*On fail goto*//*Label 7982*/ GIMT_Encode4(410963), // Rule ID 14186 //
     /* 410821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 410824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 410832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 410836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 410840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410844 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410848 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 410852 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410857 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 410861 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 410865 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410869 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410873 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 410877 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410882 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 410886 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410890 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 410892 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 410892 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 410895 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410899 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410904 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 410910 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410915 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410920 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 410923 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410927 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410932 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 410938 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410943 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 410951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 410953 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410956 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 410959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 410961 */     GIR_RootConstrainSelectedInstOperands,
     /* 410962 */     // GIR_Coverage, 14186,
     /* 410962 */     GIR_EraseRootFromParent_Done,
     /* 410963 */   // Label 7982: @410963
     /* 410963 */   GIM_Try, /*On fail goto*//*Label 7983*/ GIMT_Encode4(411094), // Rule ID 6172 //
     /* 410968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 410971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410979 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 410983 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 410987 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 410992 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 410996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 411004 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 411008 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 411012 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411016 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411020 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 411024 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411029 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 411033 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411037 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411041 */     // MIs[4] Operand 1
     /* 411041 */     // No operand predicates
     /* 411041 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411045 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 411047 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411059 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411065 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411070 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 411078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411082 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 411089 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 411092 */     GIR_RootConstrainSelectedInstOperands,
     /* 411093 */     // GIR_Coverage, 6172,
     /* 411093 */     GIR_EraseRootFromParent_Done,
     /* 411094 */   // Label 7983: @411094
     /* 411094 */   GIM_Try, /*On fail goto*//*Label 7984*/ GIMT_Encode4(411225), // Rule ID 6204 //
     /* 411099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 411102 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411110 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411114 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411118 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 411127 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411131 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411135 */     // MIs[2] Operand 1
     /* 411135 */     // No operand predicates
     /* 411135 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 411139 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 411143 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 411147 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 411151 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411155 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411159 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 411163 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411168 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 411172 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411176 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 411178 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411178 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411181 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411185 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411190 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411196 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411201 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 411209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411211 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411213 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 411220 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 411223 */     GIR_RootConstrainSelectedInstOperands,
     /* 411224 */     // GIR_Coverage, 6204,
     /* 411224 */     GIR_EraseRootFromParent_Done,
     /* 411225 */   // Label 7984: @411225
     /* 411225 */   GIM_Try, /*On fail goto*//*Label 7985*/ GIMT_Encode4(411356), // Rule ID 6268 //
     /* 411230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 411233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 411241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 411245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 411249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411257 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 411261 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411266 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 411270 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 411274 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411278 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411282 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 411286 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411291 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 411295 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411299 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411303 */     // MIs[4] Operand 1
     /* 411303 */     // No operand predicates
     /* 411303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411307 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 411309 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411309 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411312 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411316 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411321 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411327 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411332 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 411340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411342 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411344 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 411351 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 411354 */     GIR_RootConstrainSelectedInstOperands,
     /* 411355 */     // GIR_Coverage, 6268,
     /* 411355 */     GIR_EraseRootFromParent_Done,
     /* 411356 */   // Label 7985: @411356
     /* 411356 */   GIM_Try, /*On fail goto*//*Label 7986*/ GIMT_Encode4(411487), // Rule ID 6236 //
     /* 411361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 411364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 411372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 411376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 411380 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411384 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411388 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 411392 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411397 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 411401 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411405 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411409 */     // MIs[3] Operand 1
     /* 411409 */     // No operand predicates
     /* 411409 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 411413 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411417 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411421 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 411425 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411430 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 411434 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411438 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 411440 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411452 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411458 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411463 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 411471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411475 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 411482 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 411485 */     GIR_RootConstrainSelectedInstOperands,
     /* 411486 */     // GIR_Coverage, 6236,
     /* 411486 */     GIR_EraseRootFromParent_Done,
     /* 411487 */   // Label 7986: @411487
     /* 411487 */   GIM_Try, /*On fail goto*//*Label 7987*/ GIMT_Encode4(411622), // Rule ID 2474 //
     /* 411492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 411495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411507 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411516 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 411520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411528 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411532 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 411536 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411541 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 411545 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411549 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411551 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 411551 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 411554 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411558 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411563 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 411569 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411574 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411579 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411582 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411586 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411591 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411597 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411602 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 411610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 411612 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411615 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 411618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 411620 */     GIR_RootConstrainSelectedInstOperands,
     /* 411621 */     // GIR_Coverage, 2474,
     /* 411621 */     GIR_EraseRootFromParent_Done,
     /* 411622 */   // Label 7987: @411622
     /* 411622 */   GIM_Try, /*On fail goto*//*Label 7988*/ GIMT_Encode4(411741), // Rule ID 6140 //
     /* 411627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 411630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411646 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411651 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 411655 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411659 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411663 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411667 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 411671 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411676 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 411680 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411684 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411688 */     // MIs[3] Operand 1
     /* 411688 */     // No operand predicates
     /* 411688 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411692 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 411694 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411694 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411697 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411701 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411706 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411712 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411717 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 411725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411727 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411729 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 411736 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 411739 */     GIR_RootConstrainSelectedInstOperands,
     /* 411740 */     // GIR_Coverage, 6140,
     /* 411740 */     GIR_EraseRootFromParent_Done,
     /* 411741 */   // Label 7988: @411741
     /* 411741 */   GIM_Try, /*On fail goto*//*Label 7989*/ GIMT_Encode4(411860), // Rule ID 2557 //
     /* 411746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 411749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411761 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411770 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 411774 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 411778 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 411782 */     // MIs[2] Operand 1
     /* 411782 */     // No operand predicates
     /* 411782 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 411786 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411790 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411794 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 411798 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411803 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 411807 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411811 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 411813 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 411813 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411816 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411820 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411825 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411831 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411836 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 411844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 411848 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 411855 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 411858 */     GIR_RootConstrainSelectedInstOperands,
     /* 411859 */     // GIR_Coverage, 2557,
     /* 411859 */     GIR_EraseRootFromParent_Done,
     /* 411860 */   // Label 7989: @411860
     /* 411860 */   GIM_Try, /*On fail goto*//*Label 7990*/ GIMT_Encode4(411960), // Rule ID 4907 //
     /* 411865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 411868 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411872 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411876 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411880 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411884 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411889 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 411893 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411897 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 411901 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 411905 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411910 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411914 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411916 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 411916 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 411919 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 411923 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411928 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 411934 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411939 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 411947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 411949 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 411956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 411958 */     GIR_RootConstrainSelectedInstOperands,
     /* 411959 */     // GIR_Coverage, 4907,
     /* 411959 */     GIR_EraseRootFromParent_Done,
     /* 411960 */   // Label 7990: @411960
     /* 411960 */   GIM_Try, /*On fail goto*//*Label 7991*/ GIMT_Encode4(412060), // Rule ID 4943 //
     /* 411965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 411968 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411972 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 411976 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 411980 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 411984 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 411989 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 411993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 411997 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 412001 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412005 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 412009 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412014 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412016 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 412016 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412019 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412023 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412028 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 412034 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412039 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 412047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 412049 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 412054 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 412058 */     GIR_RootConstrainSelectedInstOperands,
     /* 412059 */     // GIR_Coverage, 4943,
     /* 412059 */     GIR_EraseRootFromParent_Done,
     /* 412060 */   // Label 7991: @412060
     /* 412060 */   GIM_Try, /*On fail goto*//*Label 7992*/ GIMT_Encode4(412157), // Rule ID 14182 //
     /* 412065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 412068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412076 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412080 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412084 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412088 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412092 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412096 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412101 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 412105 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412109 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412113 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412115 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 412115 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412122 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412127 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 412133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412138 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 412146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 412148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 412150 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 412155 */     GIR_RootConstrainSelectedInstOperands,
     /* 412156 */     // GIR_Coverage, 14182,
     /* 412156 */     GIR_EraseRootFromParent_Done,
     /* 412157 */   // Label 7992: @412157
     /* 412157 */   GIM_Try, /*On fail goto*//*Label 7993*/ GIMT_Encode4(412257), // Rule ID 14184 //
     /* 412162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 412165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412177 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412182 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412186 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412190 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412194 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412198 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412203 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 412207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412211 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412213 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 412213 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412216 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412220 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412225 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 412231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412236 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 412244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 412246 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 412253 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 412255 */     GIR_RootConstrainSelectedInstOperands,
     /* 412256 */     // GIR_Coverage, 14184,
     /* 412256 */     GIR_EraseRootFromParent_Done,
     /* 412257 */   // Label 7993: @412257
     /* 412257 */   GIM_Try, /*On fail goto*//*Label 7994*/ GIMT_Encode4(412357), // Rule ID 4941 //
     /* 412262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 412265 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 412273 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412277 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412281 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 412285 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412290 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 412294 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 412298 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412302 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 412306 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412311 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412313 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 412313 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412316 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412320 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412325 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 412331 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412336 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 412344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 412346 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 412348 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 412355 */     GIR_RootConstrainSelectedInstOperands,
     /* 412356 */     // GIR_Coverage, 4941,
     /* 412356 */     GIR_EraseRootFromParent_Done,
     /* 412357 */   // Label 7994: @412357
     /* 412357 */   GIM_Try, /*On fail goto*//*Label 7995*/ GIMT_Encode4(412454), // Rule ID 4905 //
     /* 412362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 412365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 412373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412389 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412393 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412397 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412402 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 412406 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412410 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412412 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 412412 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412415 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412419 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412424 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 412430 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412435 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 412443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 412445 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 412447 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 412452 */     GIR_RootConstrainSelectedInstOperands,
     /* 412453 */     // GIR_Coverage, 4905,
     /* 412453 */     GIR_EraseRootFromParent_Done,
     /* 412454 */   // Label 7995: @412454
     /* 412454 */   GIM_Try, /*On fail goto*//*Label 7996*/ GIMT_Encode4(412532), // Rule ID 6290 //
     /* 412459 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412463 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412467 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412471 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 412475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412483 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412487 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412492 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 412496 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412500 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 412504 */     // MIs[3] Operand 1
     /* 412504 */     // No operand predicates
     /* 412504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412508 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412512 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412514 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 412514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412519 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 412523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 412527 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 412530 */     GIR_RootConstrainSelectedInstOperands,
     /* 412531 */     // GIR_Coverage, 6290,
     /* 412531 */     GIR_EraseRootFromParent_Done,
     /* 412532 */   // Label 7996: @412532
     /* 412532 */   GIM_Try, /*On fail goto*//*Label 7997*/ GIMT_Encode4(412616), // Rule ID 6202 //
     /* 412537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 412540 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412544 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412548 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412552 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 412556 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412561 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 412565 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412569 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 412573 */     // MIs[2] Operand 1
     /* 412573 */     // No operand predicates
     /* 412573 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 412577 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412581 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 412585 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412590 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412594 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412596 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 412596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412601 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 412607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 412611 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 412614 */     GIR_RootConstrainSelectedInstOperands,
     /* 412615 */     // GIR_Coverage, 6202,
     /* 412615 */     GIR_EraseRootFromParent_Done,
     /* 412616 */   // Label 7997: @412616
     /* 412616 */   GIM_Try, /*On fail goto*//*Label 7998*/ GIMT_Encode4(412697), // Rule ID 6234 //
     /* 412621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 412624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412636 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412640 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412644 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412648 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412652 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412657 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 412661 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412665 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 412669 */     // MIs[3] Operand 1
     /* 412669 */     // No operand predicates
     /* 412669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412673 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412677 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412679 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 412679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 412688 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 412692 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 412695 */     GIR_RootConstrainSelectedInstOperands,
     /* 412696 */     // GIR_Coverage, 6234,
     /* 412696 */     GIR_EraseRootFromParent_Done,
     /* 412697 */   // Label 7998: @412697
     /* 412697 */   GIM_Try, /*On fail goto*//*Label 7999*/ GIMT_Encode4(412781), // Rule ID 6266 //
     /* 412702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 412705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412722 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412726 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412730 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412734 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412738 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412743 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 412747 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412751 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 412755 */     // MIs[3] Operand 1
     /* 412755 */     // No operand predicates
     /* 412755 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412759 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412761 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 412761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412768 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 412772 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 412776 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 412779 */     GIR_RootConstrainSelectedInstOperands,
     /* 412780 */     // GIR_Coverage, 6266,
     /* 412780 */     GIR_EraseRootFromParent_Done,
     /* 412781 */   // Label 7999: @412781
     /* 412781 */   GIM_Try, /*On fail goto*//*Label 8000*/ GIMT_Encode4(412859), // Rule ID 6312 //
     /* 412786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412790 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 412794 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412798 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412802 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 412806 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412810 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412814 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412823 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 412827 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412831 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 412835 */     // MIs[3] Operand 1
     /* 412835 */     // No operand predicates
     /* 412835 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412839 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412841 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 412841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412848 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 412850 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 412854 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 412857 */     GIR_RootConstrainSelectedInstOperands,
     /* 412858 */     // GIR_Coverage, 6312,
     /* 412858 */     GIR_EraseRootFromParent_Done,
     /* 412859 */   // Label 8000: @412859
     /* 412859 */   GIM_Try, /*On fail goto*//*Label 8001*/ GIMT_Encode4(412940), // Rule ID 6170 //
     /* 412864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 412867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 412875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 412879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 412883 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 412887 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412891 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412895 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412899 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412904 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 412908 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412912 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 412916 */     // MIs[3] Operand 1
     /* 412916 */     // No operand predicates
     /* 412916 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412920 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412922 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 412922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 412925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412927 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 412929 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 412931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 412935 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 412938 */     GIR_RootConstrainSelectedInstOperands,
     /* 412939 */     // GIR_Coverage, 6170,
     /* 412939 */     GIR_EraseRootFromParent_Done,
     /* 412940 */   // Label 8001: @412940
     /* 412940 */   GIM_Try, /*On fail goto*//*Label 8002*/ GIMT_Encode4(413025), // Rule ID 2472 //
     /* 412945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 412948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412956 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 412960 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 412964 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 412969 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 412973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412977 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 412981 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 412983 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 412983 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 412986 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412990 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412995 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 413001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413006 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 413014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 413016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413019 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 413021 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 413023 */     GIR_RootConstrainSelectedInstOperands,
     /* 413024 */     // GIR_Coverage, 2472,
     /* 413024 */     GIR_EraseRootFromParent_Done,
     /* 413025 */   // Label 8002: @413025
     /* 413025 */   GIM_Try, /*On fail goto*//*Label 8003*/ GIMT_Encode4(413110), // Rule ID 2470 //
     /* 413030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 413033 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413037 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 413041 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 413045 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 413049 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413053 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413058 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 413062 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413066 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 413068 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 413068 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 413071 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 413075 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413080 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 413086 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413091 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 413099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 413101 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413103 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413106 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 413108 */     GIR_RootConstrainSelectedInstOperands,
     /* 413109 */     // GIR_Coverage, 2470,
     /* 413109 */     GIR_EraseRootFromParent_Done,
     /* 413110 */   // Label 8003: @413110
     /* 413110 */   GIM_Try, /*On fail goto*//*Label 8004*/ GIMT_Encode4(413179), // Rule ID 2555 //
     /* 413115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413118 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413122 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 413126 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 413130 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413134 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413139 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 413143 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413147 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 413151 */     // MIs[2] Operand 1
     /* 413151 */     // No operand predicates
     /* 413151 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413155 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413159 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413161 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 413161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 413164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 413170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413174 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 413177 */     GIR_RootConstrainSelectedInstOperands,
     /* 413178 */     // GIR_Coverage, 2555,
     /* 413178 */     GIR_EraseRootFromParent_Done,
     /* 413179 */   // Label 8004: @413179
     /* 413179 */   GIM_Try, /*On fail goto*//*Label 8005*/ GIMT_Encode4(413248), // Rule ID 6138 //
     /* 413184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413187 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413191 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 413195 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 413199 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 413203 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413207 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413212 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 413216 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413220 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 413224 */     // MIs[2] Operand 1
     /* 413224 */     // No operand predicates
     /* 413224 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413228 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413230 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 413230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 413233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413237 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413243 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 413246 */     GIR_RootConstrainSelectedInstOperands,
     /* 413247 */     // GIR_Coverage, 6138,
     /* 413247 */     GIR_EraseRootFromParent_Done,
     /* 413248 */   // Label 8005: @413248
     /* 413248 */   GIM_Try, /*On fail goto*//*Label 8006*/ GIMT_Encode4(413298), // Rule ID 13605 //
     /* 413253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 413256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413260 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413264 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 413268 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413273 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413277 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413281 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 413283 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 413283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 413286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 413288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 413290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 413296 */     GIR_RootConstrainSelectedInstOperands,
     /* 413297 */     // GIR_Coverage, 13605,
     /* 413297 */     GIR_EraseRootFromParent_Done,
     /* 413298 */   // Label 8006: @413298
     /* 413298 */   GIM_Try, /*On fail goto*//*Label 8007*/ GIMT_Encode4(413348), // Rule ID 651 //
     /* 413303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 413306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 413314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 413322 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413327 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413331 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 413333 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 413333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 413336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 413338 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 413346 */     GIR_RootConstrainSelectedInstOperands,
     /* 413347 */     // GIR_Coverage, 651,
     /* 413347 */     GIR_EraseRootFromParent_Done,
     /* 413348 */   // Label 8007: @413348
     /* 413348 */   GIM_Try, /*On fail goto*//*Label 8008*/ GIMT_Encode4(413398), // Rule ID 663 //
     /* 413353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 413356 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 413368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 413376 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413381 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 413383 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 413383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 413386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 413388 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 413392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 413396 */     GIR_RootConstrainSelectedInstOperands,
     /* 413397 */     // GIR_Coverage, 663,
     /* 413397 */     GIR_EraseRootFromParent_Done,
     /* 413398 */   // Label 8008: @413398
     /* 413398 */   GIM_Try, /*On fail goto*//*Label 8009*/ GIMT_Encode4(413429), // Rule ID 645 //
     /* 413403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 413406 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413414 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413418 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 413418 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 413423 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 413427 */     GIR_RootConstrainSelectedInstOperands,
     /* 413428 */     // GIR_Coverage, 645,
     /* 413428 */     GIR_Done,
     /* 413429 */   // Label 8009: @413429
     /* 413429 */   GIM_Reject,
     /* 413430 */ // Label 7979: @413430
     /* 413430 */ GIM_Reject,
     /* 413431 */ // Label 7913: @413431
     /* 413431 */ GIM_Try, /*On fail goto*//*Label 8010*/ GIMT_Encode4(414951),
     /* 413436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 413439 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 413442 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 413445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413449 */   GIM_Try, /*On fail goto*//*Label 8011*/ GIMT_Encode4(413527), // Rule ID 6270 //
     /* 413454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413466 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413470 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 413474 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413478 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413482 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413487 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 413491 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413495 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413499 */     // MIs[3] Operand 1
     /* 413499 */     // No operand predicates
     /* 413499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413507 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413509 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413514 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 413518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 413522 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 413525 */     GIR_RootConstrainSelectedInstOperands,
     /* 413526 */     // GIR_Coverage, 6270,
     /* 413526 */     GIR_EraseRootFromParent_Done,
     /* 413527 */   // Label 8011: @413527
     /* 413527 */   GIM_Try, /*On fail goto*//*Label 8012*/ GIMT_Encode4(413611), // Rule ID 6186 //
     /* 413532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413535 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413539 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413543 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413547 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413551 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 413560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413564 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413568 */     // MIs[2] Operand 1
     /* 413568 */     // No operand predicates
     /* 413568 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 413572 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413576 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 413580 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413585 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413589 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413591 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413596 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413598 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 413602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413606 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 413609 */     GIR_RootConstrainSelectedInstOperands,
     /* 413610 */     // GIR_Coverage, 6186,
     /* 413610 */     GIR_EraseRootFromParent_Done,
     /* 413611 */   // Label 8012: @413611
     /* 413611 */   GIM_Try, /*On fail goto*//*Label 8013*/ GIMT_Encode4(413692), // Rule ID 6218 //
     /* 413616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413619 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413623 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413627 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 413631 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 413635 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413639 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413643 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 413647 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413652 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 413656 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413660 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413664 */     // MIs[3] Operand 1
     /* 413664 */     // No operand predicates
     /* 413664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413668 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413672 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413674 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413679 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 413683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 413687 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 413690 */     GIR_RootConstrainSelectedInstOperands,
     /* 413691 */     // GIR_Coverage, 6218,
     /* 413691 */     GIR_EraseRootFromParent_Done,
     /* 413692 */   // Label 8013: @413692
     /* 413692 */   GIM_Try, /*On fail goto*//*Label 8014*/ GIMT_Encode4(413776), // Rule ID 6250 //
     /* 413697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 413712 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413717 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413721 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413725 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413729 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 413733 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413738 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 413742 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413746 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413750 */     // MIs[3] Operand 1
     /* 413750 */     // No operand predicates
     /* 413750 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413754 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413756 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413761 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 413767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 413771 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 413774 */     GIR_RootConstrainSelectedInstOperands,
     /* 413775 */     // GIR_Coverage, 6250,
     /* 413775 */     GIR_EraseRootFromParent_Done,
     /* 413776 */   // Label 8014: @413776
     /* 413776 */   GIM_Try, /*On fail goto*//*Label 8015*/ GIMT_Encode4(413854), // Rule ID 6292 //
     /* 413781 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 413789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413797 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413801 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 413805 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413809 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413813 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413818 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 413822 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413826 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413830 */     // MIs[3] Operand 1
     /* 413830 */     // No operand predicates
     /* 413830 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413834 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413836 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 413849 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 413852 */     GIR_RootConstrainSelectedInstOperands,
     /* 413853 */     // GIR_Coverage, 6292,
     /* 413853 */     GIR_EraseRootFromParent_Done,
     /* 413854 */   // Label 8015: @413854
     /* 413854 */   GIM_Try, /*On fail goto*//*Label 8016*/ GIMT_Encode4(413935), // Rule ID 6154 //
     /* 413859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413862 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 413870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 413874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 413878 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 413882 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413886 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413890 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 413894 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413899 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 413903 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413907 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413911 */     // MIs[3] Operand 1
     /* 413911 */     // No operand predicates
     /* 413911 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413915 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 413917 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 413920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413924 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 413926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 413930 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 413933 */     GIR_RootConstrainSelectedInstOperands,
     /* 413934 */     // GIR_Coverage, 6154,
     /* 413934 */     GIR_EraseRootFromParent_Done,
     /* 413935 */   // Label 8016: @413935
     /* 413935 */   GIM_Try, /*On fail goto*//*Label 8017*/ GIMT_Encode4(414004), // Rule ID 2539 //
     /* 413940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 413943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 413951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 413955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 413959 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 413964 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 413968 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 413972 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 413976 */     // MIs[2] Operand 1
     /* 413976 */     // No operand predicates
     /* 413976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413980 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 413984 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413986 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 413986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 413989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 413993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 413995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 413999 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 414002 */     GIR_RootConstrainSelectedInstOperands,
     /* 414003 */     // GIR_Coverage, 2539,
     /* 414003 */     GIR_EraseRootFromParent_Done,
     /* 414004 */   // Label 8017: @414004
     /* 414004 */   GIM_Try, /*On fail goto*//*Label 8018*/ GIMT_Encode4(414073), // Rule ID 6122 //
     /* 414009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 414020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 414024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 414028 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 414032 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414037 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 414041 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 414045 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 414049 */     // MIs[2] Operand 1
     /* 414049 */     // No operand predicates
     /* 414049 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414053 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414055 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 414055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 414058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414060 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414062 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 414064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414068 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 414071 */     GIR_RootConstrainSelectedInstOperands,
     /* 414072 */     // GIR_Coverage, 6122,
     /* 414072 */     GIR_EraseRootFromParent_Done,
     /* 414073 */   // Label 8018: @414073
     /* 414073 */   GIM_Try, /*On fail goto*//*Label 8019*/ GIMT_Encode4(414166), // Rule ID 6274 //
     /* 414078 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414082 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 414086 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 414090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 414094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414098 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 414102 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414107 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414111 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414115 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414117 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414117 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414120 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414124 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414129 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414132 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 414136 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414139 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414144 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 414158 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414164 */     GIR_RootConstrainSelectedInstOperands,
     /* 414165 */     // GIR_Coverage, 6274,
     /* 414165 */     GIR_EraseRootFromParent_Done,
     /* 414166 */   // Label 8019: @414166
     /* 414166 */   GIM_Try, /*On fail goto*//*Label 8020*/ GIMT_Encode4(414265), // Rule ID 6188 //
     /* 414171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 414182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 414186 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414191 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414195 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414199 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414203 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414208 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414212 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414214 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414214 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414217 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414221 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414226 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414229 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414233 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414236 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414241 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 414257 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414263 */     GIR_RootConstrainSelectedInstOperands,
     /* 414264 */     // GIR_Coverage, 6188,
     /* 414264 */     GIR_EraseRootFromParent_Done,
     /* 414265 */   // Label 8020: @414265
     /* 414265 */   GIM_Try, /*On fail goto*//*Label 8021*/ GIMT_Encode4(414361), // Rule ID 6220 //
     /* 414270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414281 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414285 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 414289 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 414293 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 414297 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414306 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414310 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414312 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414312 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414315 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414319 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414324 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414327 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 414331 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414334 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414339 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414349 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414351 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 414353 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414359 */     GIR_RootConstrainSelectedInstOperands,
     /* 414360 */     // GIR_Coverage, 6220,
     /* 414360 */     GIR_EraseRootFromParent_Done,
     /* 414361 */   // Label 8021: @414361
     /* 414361 */   GIM_Try, /*On fail goto*//*Label 8022*/ GIMT_Encode4(414460), // Rule ID 6252 //
     /* 414366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 414394 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 414398 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414403 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414407 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414409 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414409 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414412 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414416 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414421 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414424 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 414428 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414431 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414436 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414446 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414448 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 414452 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414458 */     GIR_RootConstrainSelectedInstOperands,
     /* 414459 */     // GIR_Coverage, 6252,
     /* 414459 */     GIR_EraseRootFromParent_Done,
     /* 414460 */   // Label 8022: @414460
     /* 414460 */   GIM_Try, /*On fail goto*//*Label 8023*/ GIMT_Encode4(414553), // Rule ID 6296 //
     /* 414465 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414469 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 414473 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 414477 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 414481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 414485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414489 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 414493 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414498 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414502 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414504 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414504 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414507 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414511 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414516 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 414523 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414531 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414541 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414543 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 414545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414551 */     GIR_RootConstrainSelectedInstOperands,
     /* 414552 */     // GIR_Coverage, 6296,
     /* 414552 */     GIR_EraseRootFromParent_Done,
     /* 414553 */   // Label 8023: @414553
     /* 414553 */   GIM_Try, /*On fail goto*//*Label 8024*/ GIMT_Encode4(414649), // Rule ID 6156 //
     /* 414558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 414569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414577 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 414581 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 414585 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 414589 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414594 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414598 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414600 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414600 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414603 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414607 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414612 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414615 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 414619 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414622 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414627 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 414635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414637 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414639 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 414641 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414647 */     GIR_RootConstrainSelectedInstOperands,
     /* 414648 */     // GIR_Coverage, 6156,
     /* 414648 */     GIR_EraseRootFromParent_Done,
     /* 414649 */   // Label 8024: @414649
     /* 414649 */   GIM_Try, /*On fail goto*//*Label 8025*/ GIMT_Encode4(414733), // Rule ID 2541 //
     /* 414654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 414665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 414669 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414674 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414678 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414682 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 414684 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414684 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414687 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414691 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414696 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414699 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414703 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414706 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414711 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 414719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 414725 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414731 */     GIR_RootConstrainSelectedInstOperands,
     /* 414732 */     // GIR_Coverage, 2541,
     /* 414732 */     GIR_EraseRootFromParent_Done,
     /* 414733 */   // Label 8025: @414733
     /* 414733 */   GIM_Try, /*On fail goto*//*Label 8026*/ GIMT_Encode4(414783), // Rule ID 13635 //
     /* 414738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414741 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414745 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414749 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414758 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414762 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414766 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 414768 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 414768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 414771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 414777 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414781 */     GIR_RootConstrainSelectedInstOperands,
     /* 414782 */     // GIR_Coverage, 13635,
     /* 414782 */     GIR_EraseRootFromParent_Done,
     /* 414783 */   // Label 8026: @414783
     /* 414783 */   GIM_Try, /*On fail goto*//*Label 8027*/ GIMT_Encode4(414867), // Rule ID 6124 //
     /* 414788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414791 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 414799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 414803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 414807 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414812 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414816 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 414818 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 414818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 414821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414830 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 414833 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414837 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 414840 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414845 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 414850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 414853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414855 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414857 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 414859 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414865 */     GIR_RootConstrainSelectedInstOperands,
     /* 414866 */     // GIR_Coverage, 6124,
     /* 414866 */     GIR_EraseRootFromParent_Done,
     /* 414867 */   // Label 8027: @414867
     /* 414867 */   GIM_Try, /*On fail goto*//*Label 8028*/ GIMT_Encode4(414917), // Rule ID 1311 //
     /* 414872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 414883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414887 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 414891 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414896 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414900 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 414902 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 414902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 414905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414909 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 414911 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 414915 */     GIR_RootConstrainSelectedInstOperands,
     /* 414916 */     // GIR_Coverage, 1311,
     /* 414916 */     GIR_EraseRootFromParent_Done,
     /* 414917 */   // Label 8028: @414917
     /* 414917 */   GIM_Try, /*On fail goto*//*Label 8029*/ GIMT_Encode4(414950), // Rule ID 1301 //
     /* 414922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 414925 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 414937 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 414937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
     /* 414940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 414944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 414946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 414948 */     GIR_RootConstrainSelectedInstOperands,
     /* 414949 */     // GIR_Coverage, 1301,
     /* 414949 */     GIR_EraseRootFromParent_Done,
     /* 414950 */   // Label 8029: @414950
     /* 414950 */   GIM_Reject,
     /* 414951 */ // Label 8010: @414951
     /* 414951 */ GIM_Reject,
     /* 414952 */ // Label 7914: @414952
     /* 414952 */ GIM_Try, /*On fail goto*//*Label 8030*/ GIMT_Encode4(416472),
     /* 414957 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 414960 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 414963 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 414966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 414970 */   GIM_Try, /*On fail goto*//*Label 8031*/ GIMT_Encode4(415048), // Rule ID 6282 //
     /* 414975 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414979 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 414983 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 414987 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 414991 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 414995 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 414999 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415003 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415008 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 415012 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415016 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415020 */     // MIs[3] Operand 1
     /* 415020 */     // No operand predicates
     /* 415020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415024 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415028 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415030 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 415039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415043 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 415046 */     GIR_RootConstrainSelectedInstOperands,
     /* 415047 */     // GIR_Coverage, 6282,
     /* 415047 */     GIR_EraseRootFromParent_Done,
     /* 415048 */   // Label 8031: @415048
     /* 415048 */   GIM_Try, /*On fail goto*//*Label 8032*/ GIMT_Encode4(415132), // Rule ID 6194 //
     /* 415053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415068 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 415072 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415077 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 415081 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415085 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415089 */     // MIs[2] Operand 1
     /* 415089 */     // No operand predicates
     /* 415089 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 415093 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415097 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415101 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415106 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415110 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415112 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415117 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 415123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 415127 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 415130 */     GIR_RootConstrainSelectedInstOperands,
     /* 415131 */     // GIR_Coverage, 6194,
     /* 415131 */     GIR_EraseRootFromParent_Done,
     /* 415132 */   // Label 8032: @415132
     /* 415132 */   GIM_Try, /*On fail goto*//*Label 8033*/ GIMT_Encode4(415213), // Rule ID 6226 //
     /* 415137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415140 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415144 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415148 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415152 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 415156 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415160 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415164 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 415168 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415173 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 415177 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415181 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415185 */     // MIs[3] Operand 1
     /* 415185 */     // No operand predicates
     /* 415185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415189 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415193 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415195 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415200 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415202 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 415204 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415208 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 415211 */     GIR_RootConstrainSelectedInstOperands,
     /* 415212 */     // GIR_Coverage, 6226,
     /* 415212 */     GIR_EraseRootFromParent_Done,
     /* 415213 */   // Label 8033: @415213
     /* 415213 */   GIM_Try, /*On fail goto*//*Label 8034*/ GIMT_Encode4(415297), // Rule ID 6258 //
     /* 415218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415233 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415238 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415242 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415246 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415250 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 415254 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415259 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 415263 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415267 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415271 */     // MIs[3] Operand 1
     /* 415271 */     // No operand predicates
     /* 415271 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415275 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415277 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415282 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415284 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 415288 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415292 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 415295 */     GIR_RootConstrainSelectedInstOperands,
     /* 415296 */     // GIR_Coverage, 6258,
     /* 415296 */     GIR_EraseRootFromParent_Done,
     /* 415297 */   // Label 8034: @415297
     /* 415297 */   GIM_Try, /*On fail goto*//*Label 8035*/ GIMT_Encode4(415375), // Rule ID 6304 //
     /* 415302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 415310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415314 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415318 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 415322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 415326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415330 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415334 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415339 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 415343 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415347 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415351 */     // MIs[3] Operand 1
     /* 415351 */     // No operand predicates
     /* 415351 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415355 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415357 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415364 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 415366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415370 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 415373 */     GIR_RootConstrainSelectedInstOperands,
     /* 415374 */     // GIR_Coverage, 6304,
     /* 415374 */     GIR_EraseRootFromParent_Done,
     /* 415375 */   // Label 8035: @415375
     /* 415375 */   GIM_Try, /*On fail goto*//*Label 8036*/ GIMT_Encode4(415456), // Rule ID 6162 //
     /* 415380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415383 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 415391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415399 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 415403 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415407 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415411 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 415415 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415420 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 415424 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415428 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415432 */     // MIs[3] Operand 1
     /* 415432 */     // No operand predicates
     /* 415432 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415436 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 415438 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415443 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415445 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 415447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415451 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 415454 */     GIR_RootConstrainSelectedInstOperands,
     /* 415455 */     // GIR_Coverage, 6162,
     /* 415455 */     GIR_EraseRootFromParent_Done,
     /* 415456 */   // Label 8036: @415456
     /* 415456 */   GIM_Try, /*On fail goto*//*Label 8037*/ GIMT_Encode4(415525), // Rule ID 2547 //
     /* 415461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415476 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 415480 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415485 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 415489 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415493 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415497 */     // MIs[2] Operand 1
     /* 415497 */     // No operand predicates
     /* 415497 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415501 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415505 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415507 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 415510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 415516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 415520 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 415523 */     GIR_RootConstrainSelectedInstOperands,
     /* 415524 */     // GIR_Coverage, 2547,
     /* 415524 */     GIR_EraseRootFromParent_Done,
     /* 415525 */   // Label 8037: @415525
     /* 415525 */   GIM_Try, /*On fail goto*//*Label 8038*/ GIMT_Encode4(415594), // Rule ID 6130 //
     /* 415530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415533 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 415541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 415545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 415553 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 415562 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 415566 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 415570 */     // MIs[2] Operand 1
     /* 415570 */     // No operand predicates
     /* 415570 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415574 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415576 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 415576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 415579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415581 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415583 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 415585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 415589 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 415592 */     GIR_RootConstrainSelectedInstOperands,
     /* 415593 */     // GIR_Coverage, 6130,
     /* 415593 */     GIR_EraseRootFromParent_Done,
     /* 415594 */   // Label 8038: @415594
     /* 415594 */   GIM_Try, /*On fail goto*//*Label 8039*/ GIMT_Encode4(415687), // Rule ID 6284 //
     /* 415599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 415607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 415611 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 415615 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415619 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 415623 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415632 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415636 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415638 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 415638 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 415641 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415645 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415650 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 415653 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415657 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 415660 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415665 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 415679 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415685 */     GIR_RootConstrainSelectedInstOperands,
     /* 415686 */     // GIR_Coverage, 6284,
     /* 415686 */     GIR_EraseRootFromParent_Done,
     /* 415687 */   // Label 8039: @415687
     /* 415687 */   GIM_Try, /*On fail goto*//*Label 8040*/ GIMT_Encode4(415786), // Rule ID 6196 //
     /* 415692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 415703 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 415707 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415712 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415716 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415720 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415724 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415729 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415733 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415735 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 415735 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 415738 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415742 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415747 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 415750 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 415754 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 415757 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415762 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 415778 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415784 */     GIR_RootConstrainSelectedInstOperands,
     /* 415785 */     // GIR_Coverage, 6196,
     /* 415785 */     GIR_EraseRootFromParent_Done,
     /* 415786 */   // Label 8040: @415786
     /* 415786 */   GIM_Try, /*On fail goto*//*Label 8041*/ GIMT_Encode4(415882), // Rule ID 6228 //
     /* 415791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415806 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 415810 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 415814 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 415818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415823 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415827 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415831 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415833 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 415833 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 415836 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415840 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415845 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 415848 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415852 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 415855 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415860 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415870 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 415874 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415880 */     GIR_RootConstrainSelectedInstOperands,
     /* 415881 */     // GIR_Coverage, 6228,
     /* 415881 */     GIR_EraseRootFromParent_Done,
     /* 415882 */   // Label 8041: @415882
     /* 415882 */   GIM_Try, /*On fail goto*//*Label 8042*/ GIMT_Encode4(415981), // Rule ID 6260 //
     /* 415887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 415890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 415898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 415902 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415907 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415911 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 415915 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 415919 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415924 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415928 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415930 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 415930 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 415933 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415937 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415942 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 415945 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 415949 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 415952 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415957 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 415962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 415965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415967 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 415969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 415973 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415979 */     GIR_RootConstrainSelectedInstOperands,
     /* 415980 */     // GIR_Coverage, 6260,
     /* 415980 */     GIR_EraseRootFromParent_Done,
     /* 415981 */   // Label 8042: @415981
     /* 415981 */   GIM_Try, /*On fail goto*//*Label 8043*/ GIMT_Encode4(416074), // Rule ID 6306 //
     /* 415986 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 415990 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 415994 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 415998 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 416002 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 416006 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416010 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 416014 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416019 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416023 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416025 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 416025 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 416028 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416032 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416037 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 416040 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 416044 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 416047 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416052 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 416060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416064 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416066 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416072 */     GIR_RootConstrainSelectedInstOperands,
     /* 416073 */     // GIR_Coverage, 6306,
     /* 416073 */     GIR_EraseRootFromParent_Done,
     /* 416074 */   // Label 8043: @416074
     /* 416074 */   GIM_Try, /*On fail goto*//*Label 8044*/ GIMT_Encode4(416170), // Rule ID 6164 //
     /* 416079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 416090 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416094 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 416098 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 416102 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 416106 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 416110 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416115 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416119 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416121 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 416121 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 416124 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416128 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416133 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 416136 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 416140 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 416143 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416148 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 416156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416160 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416162 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416168 */     GIR_RootConstrainSelectedInstOperands,
     /* 416169 */     // GIR_Coverage, 6164,
     /* 416169 */     GIR_EraseRootFromParent_Done,
     /* 416170 */   // Label 8044: @416170
     /* 416170 */   GIM_Try, /*On fail goto*//*Label 8045*/ GIMT_Encode4(416254), // Rule ID 2549 //
     /* 416175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416178 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416182 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 416186 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 416190 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416199 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416203 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 416205 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 416205 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 416208 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416212 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416217 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 416220 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416224 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 416227 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416232 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 416240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416242 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416244 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 416246 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416252 */     GIR_RootConstrainSelectedInstOperands,
     /* 416253 */     // GIR_Coverage, 2549,
     /* 416253 */     GIR_EraseRootFromParent_Done,
     /* 416254 */   // Label 8045: @416254
     /* 416254 */   GIM_Try, /*On fail goto*//*Label 8046*/ GIMT_Encode4(416304), // Rule ID 13639 //
     /* 416259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 416274 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416279 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416283 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416287 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 416289 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 416289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 416292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 416298 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416302 */     GIR_RootConstrainSelectedInstOperands,
     /* 416303 */     // GIR_Coverage, 13639,
     /* 416303 */     GIR_EraseRootFromParent_Done,
     /* 416304 */   // Label 8046: @416304
     /* 416304 */   GIM_Try, /*On fail goto*//*Label 8047*/ GIMT_Encode4(416388), // Rule ID 6132 //
     /* 416309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416312 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416316 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 416320 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 416324 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 416328 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416333 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416337 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 416339 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 416339 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 416342 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416346 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416351 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 416354 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416358 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 416361 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416366 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 416374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416380 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416386 */     GIR_RootConstrainSelectedInstOperands,
     /* 416387 */     // GIR_Coverage, 6132,
     /* 416387 */     GIR_EraseRootFromParent_Done,
     /* 416388 */   // Label 8047: @416388
     /* 416388 */   GIM_Try, /*On fail goto*//*Label 8048*/ GIMT_Encode4(416438), // Rule ID 1315 //
     /* 416393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416396 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 416404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 416412 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416417 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416421 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 416423 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 416423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 416426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416428 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416430 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416436 */     GIR_RootConstrainSelectedInstOperands,
     /* 416437 */     // GIR_Coverage, 1315,
     /* 416437 */     GIR_EraseRootFromParent_Done,
     /* 416438 */   // Label 8048: @416438
     /* 416438 */   GIM_Try, /*On fail goto*//*Label 8049*/ GIMT_Encode4(416471), // Rule ID 1305 //
     /* 416443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 416446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416454 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 416458 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 416458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
     /* 416461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416463 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416465 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 416467 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 416469 */     GIR_RootConstrainSelectedInstOperands,
     /* 416470 */     // GIR_Coverage, 1305,
     /* 416470 */     GIR_EraseRootFromParent_Done,
     /* 416471 */   // Label 8049: @416471
     /* 416471 */   GIM_Reject,
     /* 416472 */ // Label 8030: @416472
     /* 416472 */ GIM_Reject,
     /* 416473 */ // Label 7915: @416473
     /* 416473 */ GIM_Try, /*On fail goto*//*Label 8050*/ GIMT_Encode4(417651),
     /* 416478 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416481 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 416484 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 416487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416491 */   GIM_Try, /*On fail goto*//*Label 8051*/ GIMT_Encode4(416575), // Rule ID 6178 //
     /* 416496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416511 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 416515 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 416524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416528 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416532 */     // MIs[2] Operand 1
     /* 416532 */     // No operand predicates
     /* 416532 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 416536 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416540 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416544 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416549 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416553 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 416555 */     // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 416558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 416566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416570 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 416573 */     GIR_RootConstrainSelectedInstOperands,
     /* 416574 */     // GIR_Coverage, 6178,
     /* 416574 */     GIR_EraseRootFromParent_Done,
     /* 416575 */   // Label 8051: @416575
     /* 416575 */   GIM_Try, /*On fail goto*//*Label 8052*/ GIMT_Encode4(416656), // Rule ID 6210 //
     /* 416580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416591 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416595 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 416599 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416603 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416607 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 416611 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416616 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 416620 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416624 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416628 */     // MIs[3] Operand 1
     /* 416628 */     // No operand predicates
     /* 416628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416632 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416636 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 416638 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 416641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416643 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 416647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 416651 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 416654 */     GIR_RootConstrainSelectedInstOperands,
     /* 416655 */     // GIR_Coverage, 6210,
     /* 416655 */     GIR_EraseRootFromParent_Done,
     /* 416656 */   // Label 8052: @416656
     /* 416656 */   GIM_Try, /*On fail goto*//*Label 8053*/ GIMT_Encode4(416740), // Rule ID 6242 //
     /* 416661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416676 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416681 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416685 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416689 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416693 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 416697 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416702 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 416706 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416710 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416714 */     // MIs[3] Operand 1
     /* 416714 */     // No operand predicates
     /* 416714 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416718 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 416720 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 416723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 416731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 416735 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 416738 */     GIR_RootConstrainSelectedInstOperands,
     /* 416739 */     // GIR_Coverage, 6242,
     /* 416739 */     GIR_EraseRootFromParent_Done,
     /* 416740 */   // Label 8053: @416740
     /* 416740 */   GIM_Try, /*On fail goto*//*Label 8054*/ GIMT_Encode4(416821), // Rule ID 6146 //
     /* 416745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416748 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 416756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416764 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 416768 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416772 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416776 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 416780 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416785 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 416789 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416793 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416797 */     // MIs[3] Operand 1
     /* 416797 */     // No operand predicates
     /* 416797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416801 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 416803 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 416806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416810 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416812 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 416816 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 416819 */     GIR_RootConstrainSelectedInstOperands,
     /* 416820 */     // GIR_Coverage, 6146,
     /* 416820 */     GIR_EraseRootFromParent_Done,
     /* 416821 */   // Label 8054: @416821
     /* 416821 */   GIM_Try, /*On fail goto*//*Label 8055*/ GIMT_Encode4(416890), // Rule ID 2531 //
     /* 416826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416841 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 416845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416850 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 416854 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416858 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416862 */     // MIs[2] Operand 1
     /* 416862 */     // No operand predicates
     /* 416862 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416866 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416872 */     // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 416875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416877 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416879 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 416881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416885 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 416888 */     GIR_RootConstrainSelectedInstOperands,
     /* 416889 */     // GIR_Coverage, 2531,
     /* 416889 */     GIR_EraseRootFromParent_Done,
     /* 416890 */   // Label 8055: @416890
     /* 416890 */   GIM_Try, /*On fail goto*//*Label 8056*/ GIMT_Encode4(416959), // Rule ID 6114 //
     /* 416895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 416906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 416910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 416914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 416918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 416923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 416927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416931 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 416935 */     // MIs[2] Operand 1
     /* 416935 */     // No operand predicates
     /* 416935 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 416939 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416941 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 416941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 416944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 416948 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 416950 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 416954 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 416957 */     GIR_RootConstrainSelectedInstOperands,
     /* 416958 */     // GIR_Coverage, 6114,
     /* 416958 */     GIR_EraseRootFromParent_Done,
     /* 416959 */   // Label 8056: @416959
     /* 416959 */   GIM_Try, /*On fail goto*//*Label 8057*/ GIMT_Encode4(417058), // Rule ID 6180 //
     /* 416964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 416967 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416971 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 416975 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 416979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 416984 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416988 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 416992 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 416996 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417001 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417005 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 417007 */     // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417007 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417010 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417014 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417019 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417022 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417026 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417029 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417034 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 417042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417044 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 417050 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417056 */     GIR_RootConstrainSelectedInstOperands,
     /* 417057 */     // GIR_Coverage, 6180,
     /* 417057 */     GIR_EraseRootFromParent_Done,
     /* 417058 */   // Label 8057: @417058
     /* 417058 */   GIM_Try, /*On fail goto*//*Label 8058*/ GIMT_Encode4(417154), // Rule ID 6212 //
     /* 417063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417074 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 417078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 417082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 417086 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 417090 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417099 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 417105 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417105 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417108 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417112 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417117 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417120 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417124 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417127 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417132 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 417140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417152 */     GIR_RootConstrainSelectedInstOperands,
     /* 417153 */     // GIR_Coverage, 6212,
     /* 417153 */     GIR_EraseRootFromParent_Done,
     /* 417154 */   // Label 8058: @417154
     /* 417154 */   GIM_Try, /*On fail goto*//*Label 8059*/ GIMT_Encode4(417253), // Rule ID 6244 //
     /* 417159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417162 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417166 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417170 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 417174 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417179 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 417183 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 417187 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 417191 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417196 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417200 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 417202 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417202 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417205 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417209 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417214 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417217 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417221 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417224 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417229 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 417237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 417245 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417251 */     GIR_RootConstrainSelectedInstOperands,
     /* 417252 */     // GIR_Coverage, 6244,
     /* 417252 */     GIR_EraseRootFromParent_Done,
     /* 417253 */   // Label 8059: @417253
     /* 417253 */   GIM_Try, /*On fail goto*//*Label 8060*/ GIMT_Encode4(417349), // Rule ID 6148 //
     /* 417258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417261 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 417277 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 417281 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 417285 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 417289 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417298 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 417300 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417300 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417303 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417307 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417312 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417315 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417319 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417322 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417327 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 417335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417337 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417339 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 417341 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417347 */     GIR_RootConstrainSelectedInstOperands,
     /* 417348 */     // GIR_Coverage, 6148,
     /* 417348 */     GIR_EraseRootFromParent_Done,
     /* 417349 */   // Label 8060: @417349
     /* 417349 */   GIM_Try, /*On fail goto*//*Label 8061*/ GIMT_Encode4(417433), // Rule ID 2533 //
     /* 417354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 417365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 417369 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417374 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417378 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417382 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417384 */     // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417384 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417387 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417391 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417396 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417399 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417403 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417406 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417411 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 417419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417421 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417425 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417431 */     GIR_RootConstrainSelectedInstOperands,
     /* 417432 */     // GIR_Coverage, 2533,
     /* 417432 */     GIR_EraseRootFromParent_Done,
     /* 417433 */   // Label 8061: @417433
     /* 417433 */   GIM_Try, /*On fail goto*//*Label 8062*/ GIMT_Encode4(417483), // Rule ID 13631 //
     /* 417438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417441 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417445 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417449 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 417453 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417462 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417466 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417468 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 417468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 417471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417475 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417481 */     GIR_RootConstrainSelectedInstOperands,
     /* 417482 */     // GIR_Coverage, 13631,
     /* 417482 */     GIR_EraseRootFromParent_Done,
     /* 417483 */   // Label 8062: @417483
     /* 417483 */   GIM_Try, /*On fail goto*//*Label 8063*/ GIMT_Encode4(417567), // Rule ID 6116 //
     /* 417488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417491 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 417503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 417507 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417512 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417516 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417518 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 417518 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 417521 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 417525 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417530 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 417533 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417537 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 417540 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417545 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 417550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 417553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 417559 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 417565 */     GIR_RootConstrainSelectedInstOperands,
     /* 417566 */     // GIR_Coverage, 6116,
     /* 417566 */     GIR_EraseRootFromParent_Done,
     /* 417567 */   // Label 8063: @417567
     /* 417567 */   GIM_Try, /*On fail goto*//*Label 8064*/ GIMT_Encode4(417617), // Rule ID 1307 //
     /* 417572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417575 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417579 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417583 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417587 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 417591 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417596 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417600 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417602 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 417602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 417605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417607 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417609 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 417611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417615 */     GIR_RootConstrainSelectedInstOperands,
     /* 417616 */     // GIR_Coverage, 1307,
     /* 417616 */     GIR_EraseRootFromParent_Done,
     /* 417617 */   // Label 8064: @417617
     /* 417617 */   GIM_Try, /*On fail goto*//*Label 8065*/ GIMT_Encode4(417650), // Rule ID 1297 //
     /* 417622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 417625 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417629 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417633 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417637 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 417637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
     /* 417640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417642 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417646 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 417648 */     GIR_RootConstrainSelectedInstOperands,
     /* 417649 */     // GIR_Coverage, 1297,
     /* 417649 */     GIR_EraseRootFromParent_Done,
     /* 417650 */   // Label 8065: @417650
     /* 417650 */   GIM_Reject,
     /* 417651 */ // Label 8050: @417651
     /* 417651 */ GIM_Reject,
     /* 417652 */ // Label 7916: @417652
     /* 417652 */ GIM_Try, /*On fail goto*//*Label 8066*/ GIMT_Encode4(419172),
     /* 417657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417660 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 417663 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 417666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417670 */   GIM_Try, /*On fail goto*//*Label 8067*/ GIMT_Encode4(417748), // Rule ID 6276 //
     /* 417675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 417683 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417687 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 417691 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 417695 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417699 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417703 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417708 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 417712 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417716 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 417720 */     // MIs[3] Operand 1
     /* 417720 */     // No operand predicates
     /* 417720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417724 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417728 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 417730 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 417730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 417733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417735 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417743 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 417746 */     GIR_RootConstrainSelectedInstOperands,
     /* 417747 */     // GIR_Coverage, 6276,
     /* 417747 */     GIR_EraseRootFromParent_Done,
     /* 417748 */   // Label 8067: @417748
     /* 417748 */   GIM_Try, /*On fail goto*//*Label 8068*/ GIMT_Encode4(417832), // Rule ID 6190 //
     /* 417753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 417756 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417760 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 417764 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417768 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 417772 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417777 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 417781 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417785 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 417789 */     // MIs[2] Operand 1
     /* 417789 */     // No operand predicates
     /* 417789 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 417793 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417797 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417801 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417806 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417810 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 417812 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 417812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 417815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417819 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 417823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 417827 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 417830 */     GIR_RootConstrainSelectedInstOperands,
     /* 417831 */     // GIR_Coverage, 6190,
     /* 417831 */     GIR_EraseRootFromParent_Done,
     /* 417832 */   // Label 8068: @417832
     /* 417832 */   GIM_Try, /*On fail goto*//*Label 8069*/ GIMT_Encode4(417913), // Rule ID 6222 //
     /* 417837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 417840 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417844 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417848 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417852 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 417856 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 417860 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417864 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 417868 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417873 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 417877 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417881 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 417885 */     // MIs[3] Operand 1
     /* 417885 */     // No operand predicates
     /* 417885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417889 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417893 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 417895 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 417895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 417898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417900 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 417904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 417911 */     GIR_RootConstrainSelectedInstOperands,
     /* 417912 */     // GIR_Coverage, 6222,
     /* 417912 */     GIR_EraseRootFromParent_Done,
     /* 417913 */   // Label 8069: @417913
     /* 417913 */   GIM_Try, /*On fail goto*//*Label 8070*/ GIMT_Encode4(417997), // Rule ID 6254 //
     /* 417918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 417921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 417925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 417929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417933 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417938 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 417942 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 417946 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417950 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 417954 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417959 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 417963 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417967 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 417971 */     // MIs[3] Operand 1
     /* 417971 */     // No operand predicates
     /* 417971 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417975 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 417977 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 417977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 417980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 417984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 417988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 417992 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 417995 */     GIR_RootConstrainSelectedInstOperands,
     /* 417996 */     // GIR_Coverage, 6254,
     /* 417996 */     GIR_EraseRootFromParent_Done,
     /* 417997 */   // Label 8070: @417997
     /* 417997 */   GIM_Try, /*On fail goto*//*Label 8071*/ GIMT_Encode4(418075), // Rule ID 6298 //
     /* 418002 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 418014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 418022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418026 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418030 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418034 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418039 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 418043 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418047 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418051 */     // MIs[3] Operand 1
     /* 418051 */     // No operand predicates
     /* 418051 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418055 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 418057 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 418057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418064 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418066 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418070 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 418073 */     GIR_RootConstrainSelectedInstOperands,
     /* 418074 */     // GIR_Coverage, 6298,
     /* 418074 */     GIR_EraseRootFromParent_Done,
     /* 418075 */   // Label 8071: @418075
     /* 418075 */   GIM_Try, /*On fail goto*//*Label 8072*/ GIMT_Encode4(418156), // Rule ID 6158 //
     /* 418080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418083 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418087 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418091 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418095 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418099 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418103 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 418107 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418111 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 418115 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418120 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 418124 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418128 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418132 */     // MIs[3] Operand 1
     /* 418132 */     // No operand predicates
     /* 418132 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418136 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 418138 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 418138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418145 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418147 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418151 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 418154 */     GIR_RootConstrainSelectedInstOperands,
     /* 418155 */     // GIR_Coverage, 6158,
     /* 418155 */     GIR_EraseRootFromParent_Done,
     /* 418156 */   // Label 8072: @418156
     /* 418156 */   GIM_Try, /*On fail goto*//*Label 8073*/ GIMT_Encode4(418225), // Rule ID 2543 //
     /* 418161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 418172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 418180 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418185 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 418189 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418193 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418197 */     // MIs[2] Operand 1
     /* 418197 */     // No operand predicates
     /* 418197 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418201 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418205 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418207 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 418207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 418210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418212 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 418216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 418220 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 418223 */     GIR_RootConstrainSelectedInstOperands,
     /* 418224 */     // GIR_Coverage, 2543,
     /* 418224 */     GIR_EraseRootFromParent_Done,
     /* 418225 */   // Label 8073: @418225
     /* 418225 */   GIM_Try, /*On fail goto*//*Label 8074*/ GIMT_Encode4(418294), // Rule ID 6126 //
     /* 418230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 418245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418249 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 418253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 418262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418266 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418270 */     // MIs[2] Operand 1
     /* 418270 */     // No operand predicates
     /* 418270 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418274 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418276 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 418276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 418279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418281 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418283 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418285 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 418289 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 418292 */     GIR_RootConstrainSelectedInstOperands,
     /* 418293 */     // GIR_Coverage, 6126,
     /* 418293 */     GIR_EraseRootFromParent_Done,
     /* 418294 */   // Label 8074: @418294
     /* 418294 */   GIM_Try, /*On fail goto*//*Label 8075*/ GIMT_Encode4(418387), // Rule ID 6280 //
     /* 418299 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418303 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 418307 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 418311 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418315 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418319 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 418323 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418336 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418338 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418338 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418341 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418345 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418350 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418353 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418357 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418360 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418365 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418375 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 418379 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418385 */     GIR_RootConstrainSelectedInstOperands,
     /* 418386 */     // GIR_Coverage, 6280,
     /* 418386 */     GIR_EraseRootFromParent_Done,
     /* 418387 */   // Label 8075: @418387
     /* 418387 */   GIM_Try, /*On fail goto*//*Label 8076*/ GIMT_Encode4(418486), // Rule ID 6192 //
     /* 418392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418395 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418399 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 418403 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 418407 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418412 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 418416 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418420 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418424 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418429 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418433 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418435 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418435 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418438 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418442 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418447 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418450 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 418454 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418457 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418462 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418472 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418474 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 418478 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418484 */     GIR_RootConstrainSelectedInstOperands,
     /* 418485 */     // GIR_Coverage, 6192,
     /* 418485 */     GIR_EraseRootFromParent_Done,
     /* 418486 */   // Label 8076: @418486
     /* 418486 */   GIM_Try, /*On fail goto*//*Label 8077*/ GIMT_Encode4(418582), // Rule ID 6224 //
     /* 418491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418498 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418502 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 418514 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 418518 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418527 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418531 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418533 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418533 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418536 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418540 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418545 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418548 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418552 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418555 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418560 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 418574 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418580 */     GIR_RootConstrainSelectedInstOperands,
     /* 418581 */     // GIR_Coverage, 6224,
     /* 418581 */     GIR_EraseRootFromParent_Done,
     /* 418582 */   // Label 8077: @418582
     /* 418582 */   GIM_Try, /*On fail goto*//*Label 8078*/ GIMT_Encode4(418681), // Rule ID 6256 //
     /* 418587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418590 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418594 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418598 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418602 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 418611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 418615 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 418619 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418624 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418628 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418630 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418630 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418633 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418637 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418642 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418645 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418649 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418652 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418657 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418667 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418669 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 418673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418679 */     GIR_RootConstrainSelectedInstOperands,
     /* 418680 */     // GIR_Coverage, 6256,
     /* 418680 */     GIR_EraseRootFromParent_Done,
     /* 418681 */   // Label 8078: @418681
     /* 418681 */   GIM_Try, /*On fail goto*//*Label 8079*/ GIMT_Encode4(418774), // Rule ID 6302 //
     /* 418686 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 418698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 418702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418710 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 418714 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418719 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418723 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418725 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418725 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418728 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418732 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418737 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418740 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418744 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418747 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418752 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418762 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418764 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418766 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418772 */     GIR_RootConstrainSelectedInstOperands,
     /* 418773 */     // GIR_Coverage, 6302,
     /* 418773 */     GIR_EraseRootFromParent_Done,
     /* 418774 */   // Label 8079: @418774
     /* 418774 */   GIM_Try, /*On fail goto*//*Label 8080*/ GIMT_Encode4(418870), // Rule ID 6160 //
     /* 418779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418782 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418786 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418790 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418794 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418798 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 418802 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 418806 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 418810 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418815 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 418821 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418821 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418824 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418828 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418833 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418836 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 418840 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418843 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418848 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 418856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418860 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418862 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418868 */     GIR_RootConstrainSelectedInstOperands,
     /* 418869 */     // GIR_Coverage, 6160,
     /* 418869 */     GIR_EraseRootFromParent_Done,
     /* 418870 */   // Label 8080: @418870
     /* 418870 */   GIM_Try, /*On fail goto*//*Label 8081*/ GIMT_Encode4(418954), // Rule ID 2545 //
     /* 418875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418878 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418882 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 418886 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 418890 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418899 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418903 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418905 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 418905 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 418908 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 418912 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418917 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 418920 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 418924 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 418927 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418932 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 418940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 418946 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 418952 */     GIR_RootConstrainSelectedInstOperands,
     /* 418953 */     // GIR_Coverage, 2545,
     /* 418953 */     GIR_EraseRootFromParent_Done,
     /* 418954 */   // Label 8081: @418954
     /* 418954 */   GIM_Try, /*On fail goto*//*Label 8082*/ GIMT_Encode4(419004), // Rule ID 13637 //
     /* 418959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 418966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 418970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418974 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418983 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418987 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418989 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 418989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 418992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418994 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 418996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 418998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419002 */     GIR_RootConstrainSelectedInstOperands,
     /* 419003 */     // GIR_Coverage, 13637,
     /* 419003 */     GIR_EraseRootFromParent_Done,
     /* 419004 */   // Label 8082: @419004
     /* 419004 */   GIM_Try, /*On fail goto*//*Label 8083*/ GIMT_Encode4(419088), // Rule ID 6128 //
     /* 419009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 419012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 419024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 419028 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 419033 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419037 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419039 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 419039 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 419042 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 419046 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419051 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 419054 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419058 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 419061 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419066 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 419071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 419074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419076 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419078 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419080 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419083 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 419086 */     GIR_RootConstrainSelectedInstOperands,
     /* 419087 */     // GIR_Coverage, 6128,
     /* 419087 */     GIR_EraseRootFromParent_Done,
     /* 419088 */   // Label 8083: @419088
     /* 419088 */   GIM_Try, /*On fail goto*//*Label 8084*/ GIMT_Encode4(419138), // Rule ID 1313 //
     /* 419093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 419096 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 419112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419117 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419121 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419123 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 419123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 419126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419130 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419136 */     GIR_RootConstrainSelectedInstOperands,
     /* 419137 */     // GIR_Coverage, 1313,
     /* 419137 */     GIR_EraseRootFromParent_Done,
     /* 419138 */   // Label 8084: @419138
     /* 419138 */   GIM_Try, /*On fail goto*//*Label 8085*/ GIMT_Encode4(419171), // Rule ID 1303 //
     /* 419143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 419146 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419158 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 419158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
     /* 419161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 419167 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 419169 */     GIR_RootConstrainSelectedInstOperands,
     /* 419170 */     // GIR_Coverage, 1303,
     /* 419170 */     GIR_EraseRootFromParent_Done,
     /* 419171 */   // Label 8085: @419171
     /* 419171 */   GIM_Reject,
     /* 419172 */ // Label 8066: @419172
     /* 419172 */ GIM_Reject,
     /* 419173 */ // Label 7917: @419173
     /* 419173 */ GIM_Try, /*On fail goto*//*Label 8086*/ GIMT_Encode4(420351),
     /* 419178 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419181 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 419184 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 419187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419191 */   GIM_Try, /*On fail goto*//*Label 8087*/ GIMT_Encode4(419275), // Rule ID 6174 //
     /* 419196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419211 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 419215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 419224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419228 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419232 */     // MIs[2] Operand 1
     /* 419232 */     // No operand predicates
     /* 419232 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 419236 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419240 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419244 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419249 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419253 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 419255 */     // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 419266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419270 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 419273 */     GIR_RootConstrainSelectedInstOperands,
     /* 419274 */     // GIR_Coverage, 6174,
     /* 419274 */     GIR_EraseRootFromParent_Done,
     /* 419275 */   // Label 8087: @419275
     /* 419275 */   GIM_Try, /*On fail goto*//*Label 8088*/ GIMT_Encode4(419356), // Rule ID 6206 //
     /* 419280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419291 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419295 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 419299 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419303 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419307 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 419311 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419316 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 419320 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419324 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419328 */     // MIs[3] Operand 1
     /* 419328 */     // No operand predicates
     /* 419328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419336 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 419338 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419343 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 419347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 419351 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 419354 */     GIR_RootConstrainSelectedInstOperands,
     /* 419355 */     // GIR_Coverage, 6206,
     /* 419355 */     GIR_EraseRootFromParent_Done,
     /* 419356 */   // Label 8088: @419356
     /* 419356 */   GIM_Try, /*On fail goto*//*Label 8089*/ GIMT_Encode4(419440), // Rule ID 6238 //
     /* 419361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419376 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 419385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419389 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419393 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 419397 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419402 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 419406 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419410 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419414 */     // MIs[3] Operand 1
     /* 419414 */     // No operand predicates
     /* 419414 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419418 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 419420 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 419431 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 419435 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 419438 */     GIR_RootConstrainSelectedInstOperands,
     /* 419439 */     // GIR_Coverage, 6238,
     /* 419439 */     GIR_EraseRootFromParent_Done,
     /* 419440 */   // Label 8089: @419440
     /* 419440 */   GIM_Try, /*On fail goto*//*Label 8090*/ GIMT_Encode4(419521), // Rule ID 6142 //
     /* 419445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419448 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419464 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 419468 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419472 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419476 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 419480 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419485 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 419489 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419493 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419497 */     // MIs[3] Operand 1
     /* 419497 */     // No operand predicates
     /* 419497 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419501 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 419503 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419508 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419510 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 419516 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 419519 */     GIR_RootConstrainSelectedInstOperands,
     /* 419520 */     // GIR_Coverage, 6142,
     /* 419520 */     GIR_EraseRootFromParent_Done,
     /* 419521 */   // Label 8090: @419521
     /* 419521 */   GIM_Try, /*On fail goto*//*Label 8091*/ GIMT_Encode4(419590), // Rule ID 2527 //
     /* 419526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419541 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 419545 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419550 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 419554 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419558 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419562 */     // MIs[2] Operand 1
     /* 419562 */     // No operand predicates
     /* 419562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419566 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419570 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 419572 */     // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 419575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419577 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419579 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 419581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419585 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 419588 */     GIR_RootConstrainSelectedInstOperands,
     /* 419589 */     // GIR_Coverage, 2527,
     /* 419589 */     GIR_EraseRootFromParent_Done,
     /* 419590 */   // Label 8091: @419590
     /* 419590 */   GIM_Try, /*On fail goto*//*Label 8092*/ GIMT_Encode4(419659), // Rule ID 6110 //
     /* 419595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419598 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419602 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419606 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 419610 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419614 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 419618 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 419623 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 419627 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419631 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 419635 */     // MIs[2] Operand 1
     /* 419635 */     // No operand predicates
     /* 419635 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419639 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 419641 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 419641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 419644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419648 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419650 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419654 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 419657 */     GIR_RootConstrainSelectedInstOperands,
     /* 419658 */     // GIR_Coverage, 6110,
     /* 419658 */     GIR_EraseRootFromParent_Done,
     /* 419659 */   // Label 8092: @419659
     /* 419659 */   GIM_Try, /*On fail goto*//*Label 8093*/ GIMT_Encode4(419758), // Rule ID 6176 //
     /* 419664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 419675 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 419679 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419684 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 419688 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419692 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419696 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419701 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419705 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 419707 */     // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 419707 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 419710 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 419714 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419719 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 419722 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 419726 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 419729 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419734 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 419750 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 419756 */     GIR_RootConstrainSelectedInstOperands,
     /* 419757 */     // GIR_Coverage, 6176,
     /* 419757 */     GIR_EraseRootFromParent_Done,
     /* 419758 */   // Label 8093: @419758
     /* 419758 */   GIM_Try, /*On fail goto*//*Label 8094*/ GIMT_Encode4(419854), // Rule ID 6208 //
     /* 419763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419766 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419770 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419774 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419778 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 419782 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 419786 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 419790 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419799 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419803 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 419805 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 419805 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 419808 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 419812 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419817 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 419820 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 419824 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 419827 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419832 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419842 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419844 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 419846 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 419852 */     GIR_RootConstrainSelectedInstOperands,
     /* 419853 */     // GIR_Coverage, 6208,
     /* 419853 */     GIR_EraseRootFromParent_Done,
     /* 419854 */   // Label 8094: @419854
     /* 419854 */   GIM_Try, /*On fail goto*//*Label 8095*/ GIMT_Encode4(419953), // Rule ID 6240 //
     /* 419859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 419866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419874 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 419883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 419887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 419891 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419896 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419900 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 419902 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 419902 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 419905 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 419909 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419914 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 419917 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 419921 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 419924 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419929 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 419937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419939 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 419941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 419945 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 419951 */     GIR_RootConstrainSelectedInstOperands,
     /* 419952 */     // GIR_Coverage, 6240,
     /* 419952 */     GIR_EraseRootFromParent_Done,
     /* 419953 */   // Label 8095: @419953
     /* 419953 */   GIM_Try, /*On fail goto*//*Label 8096*/ GIMT_Encode4(420049), // Rule ID 6144 //
     /* 419958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 419961 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419969 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 419973 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 419977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 419981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 419985 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 419989 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 419994 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419998 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420000 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 420000 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 420003 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420007 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420012 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420015 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 420019 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 420022 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420027 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 420032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 420035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420039 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 420041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420047 */     GIR_RootConstrainSelectedInstOperands,
     /* 420048 */     // GIR_Coverage, 6144,
     /* 420048 */     GIR_EraseRootFromParent_Done,
     /* 420049 */   // Label 8096: @420049
     /* 420049 */   GIM_Try, /*On fail goto*//*Label 8097*/ GIMT_Encode4(420133), // Rule ID 2529 //
     /* 420054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420057 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420061 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 420065 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 420069 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 420074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420078 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420082 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420084 */     // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 420084 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 420087 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420091 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420096 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420099 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 420103 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 420106 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420111 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 420116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 420119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420121 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 420125 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420131 */     GIR_RootConstrainSelectedInstOperands,
     /* 420132 */     // GIR_Coverage, 2529,
     /* 420132 */     GIR_EraseRootFromParent_Done,
     /* 420133 */   // Label 8097: @420133
     /* 420133 */   GIM_Try, /*On fail goto*//*Label 8098*/ GIMT_Encode4(420183), // Rule ID 13633 //
     /* 420138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 420149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 420153 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420158 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420162 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420166 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420168 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 420168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 420171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420173 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 420177 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 420181 */     GIR_RootConstrainSelectedInstOperands,
     /* 420182 */     // GIR_Coverage, 13633,
     /* 420182 */     GIR_EraseRootFromParent_Done,
     /* 420183 */   // Label 8098: @420183
     /* 420183 */   GIM_Try, /*On fail goto*//*Label 8099*/ GIMT_Encode4(420267), // Rule ID 6112 //
     /* 420188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420191 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 420199 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 420203 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 420207 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 420212 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420216 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420218 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 420218 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 420221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420225 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420230 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420233 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 420237 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 420240 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420245 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 420250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 420253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420257 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 420259 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420265 */     GIR_RootConstrainSelectedInstOperands,
     /* 420266 */     // GIR_Coverage, 6112,
     /* 420266 */     GIR_EraseRootFromParent_Done,
     /* 420267 */   // Label 8099: @420267
     /* 420267 */   GIM_Try, /*On fail goto*//*Label 8100*/ GIMT_Encode4(420317), // Rule ID 1309 //
     /* 420272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420275 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 420283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 420287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 420291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420296 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420300 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420302 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 420302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 420305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420307 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420309 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 420311 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 420315 */     GIR_RootConstrainSelectedInstOperands,
     /* 420316 */     // GIR_Coverage, 1309,
     /* 420316 */     GIR_EraseRootFromParent_Done,
     /* 420317 */   // Label 8100: @420317
     /* 420317 */   GIM_Try, /*On fail goto*//*Label 8101*/ GIMT_Encode4(420350), // Rule ID 1299 //
     /* 420322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420325 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420329 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420333 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420337 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 420337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
     /* 420340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420342 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 420344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 420346 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 420348 */     GIR_RootConstrainSelectedInstOperands,
     /* 420349 */     // GIR_Coverage, 1299,
     /* 420349 */     GIR_EraseRootFromParent_Done,
     /* 420350 */   // Label 8101: @420350
     /* 420350 */   GIM_Reject,
     /* 420351 */ // Label 8086: @420351
     /* 420351 */ GIM_Reject,
     /* 420352 */ // Label 7918: @420352
     /* 420352 */ GIM_Reject,
     /* 420353 */ // Label 109: @420353
     /* 420353 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8110*/ GIMT_Encode4(420652),
     /* 420364 */ /*GILLT_s16*//*Label 8102*/ GIMT_Encode4(420404),
     /* 420368 */ /*GILLT_s32*//*Label 8103*/ GIMT_Encode4(420435),
     /* 420372 */ /*GILLT_s64*//*Label 8104*/ GIMT_Encode4(420466), GIMT_Encode4(0),
     /* 420380 */ /*GILLT_v2s32*//*Label 8105*/ GIMT_Encode4(420497),
     /* 420384 */ /*GILLT_v2s64*//*Label 8106*/ GIMT_Encode4(420528),
     /* 420388 */ /*GILLT_v4s16*//*Label 8107*/ GIMT_Encode4(420559),
     /* 420392 */ /*GILLT_v4s32*//*Label 8108*/ GIMT_Encode4(420590), GIMT_Encode4(0),
     /* 420400 */ /*GILLT_v8s16*//*Label 8109*/ GIMT_Encode4(420621),
     /* 420404 */ // Label 8102: @420404
     /* 420404 */ GIM_Try, /*On fail goto*//*Label 8111*/ GIMT_Encode4(420434), // Rule ID 573 //
     /* 420409 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 420412 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 420415 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420419 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420423 */   // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 420423 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
     /* 420428 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420432 */   GIR_RootConstrainSelectedInstOperands,
     /* 420433 */   // GIR_Coverage, 573,
     /* 420433 */   GIR_Done,
     /* 420434 */ // Label 8111: @420434
     /* 420434 */ GIM_Reject,
     /* 420435 */ // Label 8103: @420435
     /* 420435 */ GIM_Try, /*On fail goto*//*Label 8112*/ GIMT_Encode4(420465), // Rule ID 575 //
     /* 420440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 420443 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 420446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420450 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420454 */   // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 420454 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
     /* 420459 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420463 */   GIR_RootConstrainSelectedInstOperands,
     /* 420464 */   // GIR_Coverage, 575,
     /* 420464 */   GIR_Done,
     /* 420465 */ // Label 8112: @420465
     /* 420465 */ GIM_Reject,
     /* 420466 */ // Label 8104: @420466
     /* 420466 */ GIM_Try, /*On fail goto*//*Label 8113*/ GIMT_Encode4(420496), // Rule ID 577 //
     /* 420471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 420474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 420477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420481 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420485 */   // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 420485 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
     /* 420490 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420494 */   GIR_RootConstrainSelectedInstOperands,
     /* 420495 */   // GIR_Coverage, 577,
     /* 420495 */   GIR_Done,
     /* 420496 */ // Label 8113: @420496
     /* 420496 */ GIM_Reject,
     /* 420497 */ // Label 8105: @420497
     /* 420497 */ GIM_Try, /*On fail goto*//*Label 8114*/ GIMT_Encode4(420527), // Rule ID 963 //
     /* 420502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420505 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 420508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420512 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420516 */   // (strict_fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 420516 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
     /* 420521 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420525 */   GIR_RootConstrainSelectedInstOperands,
     /* 420526 */   // GIR_Coverage, 963,
     /* 420526 */   GIR_Done,
     /* 420527 */ // Label 8114: @420527
     /* 420527 */ GIM_Reject,
     /* 420528 */ // Label 8106: @420528
     /* 420528 */ GIM_Try, /*On fail goto*//*Label 8115*/ GIMT_Encode4(420558), // Rule ID 967 //
     /* 420533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 420539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420543 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420547 */   // (strict_fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 420547 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
     /* 420552 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420556 */   GIR_RootConstrainSelectedInstOperands,
     /* 420557 */   // GIR_Coverage, 967,
     /* 420557 */   GIR_Done,
     /* 420558 */ // Label 8115: @420558
     /* 420558 */ GIM_Reject,
     /* 420559 */ // Label 8107: @420559
     /* 420559 */ GIM_Try, /*On fail goto*//*Label 8116*/ GIMT_Encode4(420589), // Rule ID 959 //
     /* 420564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 420570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420574 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420578 */   // (strict_fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 420578 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
     /* 420583 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420587 */   GIR_RootConstrainSelectedInstOperands,
     /* 420588 */   // GIR_Coverage, 959,
     /* 420588 */   GIR_Done,
     /* 420589 */ // Label 8116: @420589
     /* 420589 */ GIM_Reject,
     /* 420590 */ // Label 8108: @420590
     /* 420590 */ GIM_Try, /*On fail goto*//*Label 8117*/ GIMT_Encode4(420620), // Rule ID 965 //
     /* 420595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 420601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420605 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420609 */   // (strict_fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 420609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
     /* 420614 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420618 */   GIR_RootConstrainSelectedInstOperands,
     /* 420619 */   // GIR_Coverage, 965,
     /* 420619 */   GIR_Done,
     /* 420620 */ // Label 8117: @420620
     /* 420620 */ GIM_Reject,
     /* 420621 */ // Label 8109: @420621
     /* 420621 */ GIM_Try, /*On fail goto*//*Label 8118*/ GIMT_Encode4(420651), // Rule ID 961 //
     /* 420626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 420629 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 420632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420636 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420640 */   // (strict_fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 420640 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
     /* 420645 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420649 */   GIR_RootConstrainSelectedInstOperands,
     /* 420650 */   // GIR_Coverage, 961,
     /* 420650 */   GIR_Done,
     /* 420651 */ // Label 8118: @420651
     /* 420651 */ GIM_Reject,
     /* 420652 */ // Label 8110: @420652
     /* 420652 */ GIM_Reject,
     /* 420653 */ // Label 110: @420653
     /* 420653 */ GIM_Try, /*On fail goto*//*Label 8119*/ GIMT_Encode4(420666), // Rule ID 6599 //
     /* 420658 */   // (trap)  =>  (BRK 1:{ *:[i32] })
     /* 420658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 420661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 420664 */   GIR_RootConstrainSelectedInstOperands,
     /* 420665 */   // GIR_Coverage, 6599,
     /* 420665 */   GIR_EraseRootFromParent_Done,
     /* 420666 */ // Label 8119: @420666
     /* 420666 */ GIM_Reject,
     /* 420667 */ // Label 111: @420667
     /* 420667 */ GIM_Try, /*On fail goto*//*Label 8120*/ GIMT_Encode4(420687), // Rule ID 6600 //
     /* 420672 */   // (debugtrap)  =>  (BRK 61440:{ *:[i32] })
     /* 420672 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 420675 */   GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(61440),
     /* 420685 */   GIR_RootConstrainSelectedInstOperands,
     /* 420686 */   // GIR_Coverage, 6600,
     /* 420686 */   GIR_EraseRootFromParent_Done,
     /* 420687 */ // Label 8120: @420687
     /* 420687 */ GIM_Reject,
     /* 420688 */ // Label 112: @420688
     /* 420688 */ GIM_Try, /*On fail goto*//*Label 8121*/ GIMT_Encode4(420712), // Rule ID 6601 //
     /* 420693 */   // MIs[0] kind
     /* 420693 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 420696 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_ubsan_trap_imm),
     /* 420701 */   // (ubsantrap (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>><<X:ubsan_trap_xform>>:$kind)  =>  (BRK (ubsan_trap_xform:{ *:[i32] } (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>>:$kind))
     /* 420701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 420704 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, /*OperandRenderer*/GIMT_Encode2(GICR_renderUbsanTrap), // kind
     /* 420710 */   GIR_RootConstrainSelectedInstOperands,
     /* 420711 */   // GIR_Coverage, 6601,
     /* 420711 */   GIR_EraseRootFromParent_Done,
     /* 420712 */ // Label 8121: @420712
     /* 420712 */ GIM_Reject,
     /* 420713 */ // Label 113: @420713
     /* 420713 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8125*/ GIMT_Encode4(421022),
     /* 420724 */ /*GILLT_s16*//*Label 8122*/ GIMT_Encode4(420736),
     /* 420728 */ /*GILLT_s32*//*Label 8123*/ GIMT_Encode4(420889),
     /* 420732 */ /*GILLT_s64*//*Label 8124*/ GIMT_Encode4(420994),
     /* 420736 */ // Label 8122: @420736
     /* 420736 */ GIM_Try, /*On fail goto*//*Label 8126*/ GIMT_Encode4(420837), // Rule ID 5654 //
     /* 420741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 420744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 420747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420751 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420755 */   // (vecreduce_fadd:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv8f16:{ *:[f128] } (FADDPv8f16:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rn), dsub:{ *:[i32] }))
     /* 420755 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 420758 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 420762 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420767 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420771 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420775 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 420777 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 420780 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 420784 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420789 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 420792 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420796 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 420798 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 420801 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 420805 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420810 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 420817 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420822 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 420830 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 420832 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420835 */   GIR_RootConstrainSelectedInstOperands,
     /* 420836 */   // GIR_Coverage, 5654,
     /* 420836 */   GIR_EraseRootFromParent_Done,
     /* 420837 */ // Label 8126: @420837
     /* 420837 */ GIM_Try, /*On fail goto*//*Label 8127*/ GIMT_Encode4(420888), // Rule ID 5655 //
     /* 420842 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 420845 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 420848 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420852 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420856 */   // (vecreduce_fadd:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FADDPv2i16p:{ *:[f16] } (FADDPv4f16:{ *:[i64] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rn))
     /* 420856 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 420859 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
     /* 420863 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420868 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420872 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420876 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 420881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 420883 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420886 */   GIR_RootConstrainSelectedInstOperands,
     /* 420887 */   // GIR_Coverage, 5655,
     /* 420887 */   GIR_EraseRootFromParent_Done,
     /* 420888 */ // Label 8127: @420888
     /* 420888 */ GIM_Reject,
     /* 420889 */ // Label 8123: @420889
     /* 420889 */ GIM_Try, /*On fail goto*//*Label 8128*/ GIMT_Encode4(420966), // Rule ID 5656 //
     /* 420894 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 420897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420901 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420905 */   // (vecreduce_fadd:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
     /* 420905 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 420908 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 420912 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420917 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420921 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 420925 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 420927 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 420930 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 420934 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420939 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 420946 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420951 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420956 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 420959 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 420961 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420964 */   GIR_RootConstrainSelectedInstOperands,
     /* 420965 */   // GIR_Coverage, 5656,
     /* 420965 */   GIR_EraseRootFromParent_Done,
     /* 420966 */ // Label 8128: @420966
     /* 420966 */ GIM_Try, /*On fail goto*//*Label 8129*/ GIMT_Encode4(420993), // Rule ID 5657 //
     /* 420971 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 420974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 420982 */   // (vecreduce_fadd:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 420982 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 420987 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 420991 */   GIR_RootConstrainSelectedInstOperands,
     /* 420992 */   // GIR_Coverage, 5657,
     /* 420992 */   GIR_Done,
     /* 420993 */ // Label 8129: @420993
     /* 420993 */ GIM_Reject,
     /* 420994 */ // Label 8124: @420994
     /* 420994 */ GIM_Try, /*On fail goto*//*Label 8130*/ GIMT_Encode4(421021), // Rule ID 5658 //
     /* 420999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 421002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421006 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421010 */   // (vecreduce_fadd:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 421010 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 421015 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421019 */   GIR_RootConstrainSelectedInstOperands,
     /* 421020 */   // GIR_Coverage, 5658,
     /* 421020 */   GIR_Done,
     /* 421021 */ // Label 8130: @421021
     /* 421021 */ GIM_Reject,
     /* 421022 */ // Label 8125: @421022
     /* 421022 */ GIM_Reject,
     /* 421023 */ // Label 114: @421023
     /* 421023 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8134*/ GIMT_Encode4(421193),
     /* 421034 */ /*GILLT_s16*//*Label 8131*/ GIMT_Encode4(421046),
     /* 421038 */ /*GILLT_s32*//*Label 8132*/ GIMT_Encode4(421107),
     /* 421042 */ /*GILLT_s64*//*Label 8133*/ GIMT_Encode4(421165),
     /* 421046 */ // Label 8131: @421046
     /* 421046 */ GIM_Try, /*On fail goto*//*Label 8135*/ GIMT_Encode4(421076), // Rule ID 1946 //
     /* 421051 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421054 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421057 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421061 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421065 */   // (vecreduce_fmax:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 421065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
     /* 421070 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421074 */   GIR_RootConstrainSelectedInstOperands,
     /* 421075 */   // GIR_Coverage, 1946,
     /* 421075 */   GIR_Done,
     /* 421076 */ // Label 8135: @421076
     /* 421076 */ GIM_Try, /*On fail goto*//*Label 8136*/ GIMT_Encode4(421106), // Rule ID 1948 //
     /* 421081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421084 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421091 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421095 */   // (vecreduce_fmax:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 421095 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
     /* 421100 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421104 */   GIR_RootConstrainSelectedInstOperands,
     /* 421105 */   // GIR_Coverage, 1948,
     /* 421105 */   GIR_Done,
     /* 421106 */ // Label 8136: @421106
     /* 421106 */ GIM_Reject,
     /* 421107 */ // Label 8132: @421107
     /* 421107 */ GIM_Try, /*On fail goto*//*Label 8137*/ GIMT_Encode4(421137), // Rule ID 1950 //
     /* 421112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 421118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421122 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421126 */   // (vecreduce_fmax:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 421126 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
     /* 421131 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421135 */   GIR_RootConstrainSelectedInstOperands,
     /* 421136 */   // GIR_Coverage, 1950,
     /* 421136 */   GIR_Done,
     /* 421137 */ // Label 8137: @421137
     /* 421137 */ GIM_Try, /*On fail goto*//*Label 8138*/ GIMT_Encode4(421164), // Rule ID 5664 //
     /* 421142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 421145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421149 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421153 */   // (vecreduce_fmax:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 421153 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
     /* 421158 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421162 */   GIR_RootConstrainSelectedInstOperands,
     /* 421163 */   // GIR_Coverage, 5664,
     /* 421163 */   GIR_Done,
     /* 421164 */ // Label 8138: @421164
     /* 421164 */ GIM_Reject,
     /* 421165 */ // Label 8133: @421165
     /* 421165 */ GIM_Try, /*On fail goto*//*Label 8139*/ GIMT_Encode4(421192), // Rule ID 5666 //
     /* 421170 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 421173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421177 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421181 */   // (vecreduce_fmax:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 421181 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
     /* 421186 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421190 */   GIR_RootConstrainSelectedInstOperands,
     /* 421191 */   // GIR_Coverage, 5666,
     /* 421191 */   GIR_Done,
     /* 421192 */ // Label 8139: @421192
     /* 421192 */ GIM_Reject,
     /* 421193 */ // Label 8134: @421193
     /* 421193 */ GIM_Reject,
     /* 421194 */ // Label 115: @421194
     /* 421194 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8143*/ GIMT_Encode4(421364),
     /* 421205 */ /*GILLT_s16*//*Label 8140*/ GIMT_Encode4(421217),
     /* 421209 */ /*GILLT_s32*//*Label 8141*/ GIMT_Encode4(421278),
     /* 421213 */ /*GILLT_s64*//*Label 8142*/ GIMT_Encode4(421336),
     /* 421217 */ // Label 8140: @421217
     /* 421217 */ GIM_Try, /*On fail goto*//*Label 8144*/ GIMT_Encode4(421247), // Rule ID 1958 //
     /* 421222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421225 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421232 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421236 */   // (vecreduce_fmin:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 421236 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
     /* 421241 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421245 */   GIR_RootConstrainSelectedInstOperands,
     /* 421246 */   // GIR_Coverage, 1958,
     /* 421246 */   GIR_Done,
     /* 421247 */ // Label 8144: @421247
     /* 421247 */ GIM_Try, /*On fail goto*//*Label 8145*/ GIMT_Encode4(421277), // Rule ID 1960 //
     /* 421252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421255 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421262 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421266 */   // (vecreduce_fmin:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 421266 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
     /* 421271 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421275 */   GIR_RootConstrainSelectedInstOperands,
     /* 421276 */   // GIR_Coverage, 1960,
     /* 421276 */   GIR_Done,
     /* 421277 */ // Label 8145: @421277
     /* 421277 */ GIM_Reject,
     /* 421278 */ // Label 8141: @421278
     /* 421278 */ GIM_Try, /*On fail goto*//*Label 8146*/ GIMT_Encode4(421308), // Rule ID 1962 //
     /* 421283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 421289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421293 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421297 */   // (vecreduce_fmin:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 421297 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
     /* 421302 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421306 */   GIR_RootConstrainSelectedInstOperands,
     /* 421307 */   // GIR_Coverage, 1962,
     /* 421307 */   GIR_Done,
     /* 421308 */ // Label 8146: @421308
     /* 421308 */ GIM_Try, /*On fail goto*//*Label 8147*/ GIMT_Encode4(421335), // Rule ID 5672 //
     /* 421313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 421316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421320 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421324 */   // (vecreduce_fmin:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 421324 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
     /* 421329 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421333 */   GIR_RootConstrainSelectedInstOperands,
     /* 421334 */   // GIR_Coverage, 5672,
     /* 421334 */   GIR_Done,
     /* 421335 */ // Label 8147: @421335
     /* 421335 */ GIM_Reject,
     /* 421336 */ // Label 8142: @421336
     /* 421336 */ GIM_Try, /*On fail goto*//*Label 8148*/ GIMT_Encode4(421363), // Rule ID 5674 //
     /* 421341 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 421344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421348 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421352 */   // (vecreduce_fmin:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 421352 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
     /* 421357 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421361 */   GIR_RootConstrainSelectedInstOperands,
     /* 421362 */   // GIR_Coverage, 5674,
     /* 421362 */   GIR_Done,
     /* 421363 */ // Label 8148: @421363
     /* 421363 */ GIM_Reject,
     /* 421364 */ // Label 8143: @421364
     /* 421364 */ GIM_Reject,
     /* 421365 */ // Label 116: @421365
     /* 421365 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8152*/ GIMT_Encode4(421535),
     /* 421376 */ /*GILLT_s16*//*Label 8149*/ GIMT_Encode4(421388),
     /* 421380 */ /*GILLT_s32*//*Label 8150*/ GIMT_Encode4(421449),
     /* 421384 */ /*GILLT_s64*//*Label 8151*/ GIMT_Encode4(421507),
     /* 421388 */ // Label 8149: @421388
     /* 421388 */ GIM_Try, /*On fail goto*//*Label 8153*/ GIMT_Encode4(421418), // Rule ID 1952 //
     /* 421393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421403 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421407 */   // (vecreduce_fmaximum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 421407 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
     /* 421412 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421416 */   GIR_RootConstrainSelectedInstOperands,
     /* 421417 */   // GIR_Coverage, 1952,
     /* 421417 */   GIR_Done,
     /* 421418 */ // Label 8153: @421418
     /* 421418 */ GIM_Try, /*On fail goto*//*Label 8154*/ GIMT_Encode4(421448), // Rule ID 1954 //
     /* 421423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421426 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421433 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421437 */   // (vecreduce_fmaximum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 421437 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
     /* 421442 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421446 */   GIR_RootConstrainSelectedInstOperands,
     /* 421447 */   // GIR_Coverage, 1954,
     /* 421447 */   GIR_Done,
     /* 421448 */ // Label 8154: @421448
     /* 421448 */ GIM_Reject,
     /* 421449 */ // Label 8150: @421449
     /* 421449 */ GIM_Try, /*On fail goto*//*Label 8155*/ GIMT_Encode4(421479), // Rule ID 1956 //
     /* 421454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421457 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 421460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421464 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421468 */   // (vecreduce_fmaximum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 421468 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
     /* 421473 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421477 */   GIR_RootConstrainSelectedInstOperands,
     /* 421478 */   // GIR_Coverage, 1956,
     /* 421478 */   GIR_Done,
     /* 421479 */ // Label 8155: @421479
     /* 421479 */ GIM_Try, /*On fail goto*//*Label 8156*/ GIMT_Encode4(421506), // Rule ID 5668 //
     /* 421484 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 421487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421491 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421495 */   // (vecreduce_fmaximum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 421495 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
     /* 421500 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421504 */   GIR_RootConstrainSelectedInstOperands,
     /* 421505 */   // GIR_Coverage, 5668,
     /* 421505 */   GIR_Done,
     /* 421506 */ // Label 8156: @421506
     /* 421506 */ GIM_Reject,
     /* 421507 */ // Label 8151: @421507
     /* 421507 */ GIM_Try, /*On fail goto*//*Label 8157*/ GIMT_Encode4(421534), // Rule ID 5670 //
     /* 421512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 421515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421519 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421523 */   // (vecreduce_fmaximum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 421523 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
     /* 421528 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421532 */   GIR_RootConstrainSelectedInstOperands,
     /* 421533 */   // GIR_Coverage, 5670,
     /* 421533 */   GIR_Done,
     /* 421534 */ // Label 8157: @421534
     /* 421534 */ GIM_Reject,
     /* 421535 */ // Label 8152: @421535
     /* 421535 */ GIM_Reject,
     /* 421536 */ // Label 117: @421536
     /* 421536 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8161*/ GIMT_Encode4(421706),
     /* 421547 */ /*GILLT_s16*//*Label 8158*/ GIMT_Encode4(421559),
     /* 421551 */ /*GILLT_s32*//*Label 8159*/ GIMT_Encode4(421620),
     /* 421555 */ /*GILLT_s64*//*Label 8160*/ GIMT_Encode4(421678),
     /* 421559 */ // Label 8158: @421559
     /* 421559 */ GIM_Try, /*On fail goto*//*Label 8162*/ GIMT_Encode4(421589), // Rule ID 1964 //
     /* 421564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421574 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421578 */   // (vecreduce_fminimum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 421578 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
     /* 421583 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421587 */   GIR_RootConstrainSelectedInstOperands,
     /* 421588 */   // GIR_Coverage, 1964,
     /* 421588 */   GIR_Done,
     /* 421589 */ // Label 8162: @421589
     /* 421589 */ GIM_Try, /*On fail goto*//*Label 8163*/ GIMT_Encode4(421619), // Rule ID 1966 //
     /* 421594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 421597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421604 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421608 */   // (vecreduce_fminimum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 421608 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
     /* 421613 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421617 */   GIR_RootConstrainSelectedInstOperands,
     /* 421618 */   // GIR_Coverage, 1966,
     /* 421618 */   GIR_Done,
     /* 421619 */ // Label 8163: @421619
     /* 421619 */ GIM_Reject,
     /* 421620 */ // Label 8159: @421620
     /* 421620 */ GIM_Try, /*On fail goto*//*Label 8164*/ GIMT_Encode4(421650), // Rule ID 1968 //
     /* 421625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 421631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421639 */   // (vecreduce_fminimum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 421639 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
     /* 421644 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421648 */   GIR_RootConstrainSelectedInstOperands,
     /* 421649 */   // GIR_Coverage, 1968,
     /* 421649 */   GIR_Done,
     /* 421650 */ // Label 8164: @421650
     /* 421650 */ GIM_Try, /*On fail goto*//*Label 8165*/ GIMT_Encode4(421677), // Rule ID 5676 //
     /* 421655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 421658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421662 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421666 */   // (vecreduce_fminimum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 421666 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
     /* 421671 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421675 */   GIR_RootConstrainSelectedInstOperands,
     /* 421676 */   // GIR_Coverage, 5676,
     /* 421676 */   GIR_Done,
     /* 421677 */ // Label 8165: @421677
     /* 421677 */ GIM_Reject,
     /* 421678 */ // Label 8160: @421678
     /* 421678 */ GIM_Try, /*On fail goto*//*Label 8166*/ GIMT_Encode4(421705), // Rule ID 5678 //
     /* 421683 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 421686 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421690 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421694 */   // (vecreduce_fminimum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 421694 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
     /* 421699 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 421703 */   GIR_RootConstrainSelectedInstOperands,
     /* 421704 */   // GIR_Coverage, 5678,
     /* 421704 */   GIR_Done,
     /* 421705 */ // Label 8166: @421705
     /* 421705 */ GIM_Reject,
     /* 421706 */ // Label 8161: @421706
     /* 421706 */ GIM_Reject,
     /* 421707 */ // Label 118: @421707
     /* 421707 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(4), /*)*//*default:*//*Label 8171*/ GIMT_Encode4(422835),
     /* 421718 */ /*GILLT_s8*//*Label 8167*/ GIMT_Encode4(421734),
     /* 421722 */ /*GILLT_s16*//*Label 8168*/ GIMT_Encode4(421781),
     /* 421726 */ /*GILLT_s32*//*Label 8169*/ GIMT_Encode4(422196),
     /* 421730 */ /*GILLT_s64*//*Label 8170*/ GIMT_Encode4(422649),
     /* 421734 */ // Label 8167: @421734
     /* 421734 */ GIM_Try, /*On fail goto*//*Label 8172*/ GIMT_Encode4(421757), // Rule ID 5963 //
     /* 421739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 421742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 421746 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421750 */   // (vecreduce_add:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 421750 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 421755 */   GIR_RootConstrainSelectedInstOperands,
     /* 421756 */   // GIR_Coverage, 5963,
     /* 421756 */   GIR_Done,
     /* 421757 */ // Label 8172: @421757
     /* 421757 */ GIM_Try, /*On fail goto*//*Label 8173*/ GIMT_Encode4(421780), // Rule ID 5964 //
     /* 421762 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 421765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 421769 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421773 */   // (vecreduce_add:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 421773 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 421778 */   GIR_RootConstrainSelectedInstOperands,
     /* 421779 */   // GIR_Coverage, 5964,
     /* 421779 */   GIR_Done,
     /* 421780 */ // Label 8173: @421780
     /* 421780 */ GIM_Reject,
     /* 421781 */ // Label 8168: @421781
     /* 421781 */ GIM_Try, /*On fail goto*//*Label 8174*/ GIMT_Encode4(421831), // Rule ID 5910 //
     /* 421786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421793 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421797 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 421801 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 421804 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 421809 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 421813 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421818 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421820 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 735:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 421820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 421823 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 421825 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 421829 */   GIR_RootConstrainSelectedInstOperands,
     /* 421830 */   // GIR_Coverage, 5910,
     /* 421830 */   GIR_EraseRootFromParent_Done,
     /* 421831 */ // Label 8174: @421831
     /* 421831 */ GIM_Try, /*On fail goto*//*Label 8175*/ GIMT_Encode4(421881), // Rule ID 5912 //
     /* 421836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421843 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421847 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 421851 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 421854 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 421859 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 421863 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421868 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421870 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 735:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 421870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 421873 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 421875 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 421879 */   GIR_RootConstrainSelectedInstOperands,
     /* 421880 */   // GIR_Coverage, 5912,
     /* 421880 */   GIR_EraseRootFromParent_Done,
     /* 421881 */ // Label 8175: @421881
     /* 421881 */ GIM_Try, /*On fail goto*//*Label 8176*/ GIMT_Encode4(421931), // Rule ID 5920 //
     /* 421886 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421893 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421897 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 421901 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 421904 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 421909 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 421913 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421918 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421920 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 670:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 421920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 421923 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 421925 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 421929 */   GIR_RootConstrainSelectedInstOperands,
     /* 421930 */   // GIR_Coverage, 5920,
     /* 421930 */   GIR_EraseRootFromParent_Done,
     /* 421931 */ // Label 8176: @421931
     /* 421931 */ GIM_Try, /*On fail goto*//*Label 8177*/ GIMT_Encode4(421981), // Rule ID 5922 //
     /* 421936 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 421939 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421943 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421947 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 421951 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 421954 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 421959 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 421963 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421968 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421970 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 670:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 421970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 421973 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 421975 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 421979 */   GIR_RootConstrainSelectedInstOperands,
     /* 421980 */   // GIR_Coverage, 5922,
     /* 421980 */   GIR_EraseRootFromParent_Done,
     /* 421981 */ // Label 8177: @421981
     /* 421981 */ GIM_Try, /*On fail goto*//*Label 8178*/ GIMT_Encode4(422023), // Rule ID 5919 //
     /* 421986 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 421989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421993 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421997 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 422001 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 422005 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422010 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422012 */   // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 422012 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 422015 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422017 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422021 */   GIR_RootConstrainSelectedInstOperands,
     /* 422022 */   // GIR_Coverage, 5919,
     /* 422022 */   GIR_EraseRootFromParent_Done,
     /* 422023 */ // Label 8178: @422023
     /* 422023 */ GIM_Try, /*On fail goto*//*Label 8179*/ GIMT_Encode4(422065), // Rule ID 5921 //
     /* 422028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422035 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422039 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 422043 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 422047 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422052 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422054 */   // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 422054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 422057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422059 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422063 */   GIR_RootConstrainSelectedInstOperands,
     /* 422064 */   // GIR_Coverage, 5921,
     /* 422064 */   GIR_EraseRootFromParent_Done,
     /* 422065 */ // Label 8179: @422065
     /* 422065 */ GIM_Try, /*On fail goto*//*Label 8180*/ GIMT_Encode4(422107), // Rule ID 5909 //
     /* 422070 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 422073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422077 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422081 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 422085 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 422089 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422094 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422096 */   // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 422096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 422099 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422101 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422105 */   GIR_RootConstrainSelectedInstOperands,
     /* 422106 */   // GIR_Coverage, 5909,
     /* 422106 */   GIR_EraseRootFromParent_Done,
     /* 422107 */ // Label 8180: @422107
     /* 422107 */ GIM_Try, /*On fail goto*//*Label 8181*/ GIMT_Encode4(422149), // Rule ID 5911 //
     /* 422112 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422119 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422123 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 422127 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 422131 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422136 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422138 */   // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 422138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 422141 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422143 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422147 */   GIR_RootConstrainSelectedInstOperands,
     /* 422148 */   // GIR_Coverage, 5911,
     /* 422148 */   GIR_EraseRootFromParent_Done,
     /* 422149 */ // Label 8181: @422149
     /* 422149 */ GIM_Try, /*On fail goto*//*Label 8182*/ GIMT_Encode4(422172), // Rule ID 5965 //
     /* 422154 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 422157 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422161 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422165 */   // (vecreduce_add:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 422165 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 422170 */   GIR_RootConstrainSelectedInstOperands,
     /* 422171 */   // GIR_Coverage, 5965,
     /* 422171 */   GIR_Done,
     /* 422172 */ // Label 8182: @422172
     /* 422172 */ GIM_Try, /*On fail goto*//*Label 8183*/ GIMT_Encode4(422195), // Rule ID 5966 //
     /* 422177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422184 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422188 */   // (vecreduce_add:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 422188 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 422193 */   GIR_RootConstrainSelectedInstOperands,
     /* 422194 */   // GIR_Coverage, 5966,
     /* 422194 */   GIR_Done,
     /* 422195 */ // Label 8183: @422195
     /* 422195 */ GIM_Reject,
     /* 422196 */ // Label 8169: @422196
     /* 422196 */ GIM_Try, /*On fail goto*//*Label 8184*/ GIMT_Encode4(422246), // Rule ID 5914 //
     /* 422201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422208 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422212 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422216 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422219 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 422224 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 422228 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422233 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422235 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 735:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 422235 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 422238 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422240 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422244 */   GIR_RootConstrainSelectedInstOperands,
     /* 422245 */   // GIR_Coverage, 5914,
     /* 422245 */   GIR_EraseRootFromParent_Done,
     /* 422246 */ // Label 8184: @422246
     /* 422246 */ GIM_Try, /*On fail goto*//*Label 8185*/ GIMT_Encode4(422296), // Rule ID 5916 //
     /* 422251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422258 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422262 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422266 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422269 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 422274 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 422278 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422283 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422285 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 735:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 422285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 422288 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422290 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422294 */   GIR_RootConstrainSelectedInstOperands,
     /* 422295 */   // GIR_Coverage, 5916,
     /* 422295 */   GIR_EraseRootFromParent_Done,
     /* 422296 */ // Label 8185: @422296
     /* 422296 */ GIM_Try, /*On fail goto*//*Label 8186*/ GIMT_Encode4(422346), // Rule ID 5924 //
     /* 422301 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422316 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422319 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 422324 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 422328 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422333 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422335 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 670:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 422335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 422338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422340 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422344 */   GIR_RootConstrainSelectedInstOperands,
     /* 422345 */   // GIR_Coverage, 5924,
     /* 422345 */   GIR_EraseRootFromParent_Done,
     /* 422346 */ // Label 8186: @422346
     /* 422346 */ GIM_Try, /*On fail goto*//*Label 8187*/ GIMT_Encode4(422396), // Rule ID 5926 //
     /* 422351 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422354 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422358 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422362 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422366 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422369 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 422374 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 422378 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422383 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422385 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 670:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 422385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 422388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422390 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422394 */   GIR_RootConstrainSelectedInstOperands,
     /* 422395 */   // GIR_Coverage, 5926,
     /* 422395 */   GIR_EraseRootFromParent_Done,
     /* 422396 */ // Label 8187: @422396
     /* 422396 */ GIM_Try, /*On fail goto*//*Label 8188*/ GIMT_Encode4(422438), // Rule ID 5923 //
     /* 422401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422408 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422412 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 422416 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422420 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422425 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422427 */   // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 422427 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 422430 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422432 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422436 */   GIR_RootConstrainSelectedInstOperands,
     /* 422437 */   // GIR_Coverage, 5923,
     /* 422437 */   GIR_EraseRootFromParent_Done,
     /* 422438 */ // Label 8188: @422438
     /* 422438 */ GIM_Try, /*On fail goto*//*Label 8189*/ GIMT_Encode4(422480), // Rule ID 5925 //
     /* 422443 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422450 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422454 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 422458 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 422462 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422467 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422469 */   // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 422469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 422472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422474 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422478 */   GIR_RootConstrainSelectedInstOperands,
     /* 422479 */   // GIR_Coverage, 5925,
     /* 422479 */   GIR_EraseRootFromParent_Done,
     /* 422480 */ // Label 8189: @422480
     /* 422480 */ GIM_Try, /*On fail goto*//*Label 8190*/ GIMT_Encode4(422522), // Rule ID 5913 //
     /* 422485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422492 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422496 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 422500 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422504 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422509 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422511 */   // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 422511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 422514 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422516 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422520 */   GIR_RootConstrainSelectedInstOperands,
     /* 422521 */   // GIR_Coverage, 5913,
     /* 422521 */   GIR_EraseRootFromParent_Done,
     /* 422522 */ // Label 8190: @422522
     /* 422522 */ GIM_Try, /*On fail goto*//*Label 8191*/ GIMT_Encode4(422564), // Rule ID 5915 //
     /* 422527 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422534 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422538 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 422542 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 422546 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422551 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422553 */   // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 422553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 422556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422558 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422562 */   GIR_RootConstrainSelectedInstOperands,
     /* 422563 */   // GIR_Coverage, 5915,
     /* 422563 */   GIR_EraseRootFromParent_Done,
     /* 422564 */ // Label 8191: @422564
     /* 422564 */ GIM_Try, /*On fail goto*//*Label 8192*/ GIMT_Encode4(422625), // Rule ID 5967 //
     /* 422569 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422576 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422580 */   // (vecreduce_add:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 422580 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 422583 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 422587 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422592 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 422596 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 422600 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 422602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 422605 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 422607 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 422614 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422619 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422624 */   // GIR_Coverage, 5967,
     /* 422624 */   GIR_EraseRootFromParent_Done,
     /* 422625 */ // Label 8192: @422625
     /* 422625 */ GIM_Try, /*On fail goto*//*Label 8193*/ GIMT_Encode4(422648), // Rule ID 5968 //
     /* 422630 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422637 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422641 */   // (vecreduce_add:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 422641 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 422646 */   GIR_RootConstrainSelectedInstOperands,
     /* 422647 */   // GIR_Coverage, 5968,
     /* 422647 */   GIR_Done,
     /* 422648 */ // Label 8193: @422648
     /* 422648 */ GIM_Reject,
     /* 422649 */ // Label 8170: @422649
     /* 422649 */ GIM_Try, /*On fail goto*//*Label 8194*/ GIMT_Encode4(422834),
     /* 422654 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 422657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422661 */   GIM_Try, /*On fail goto*//*Label 8195*/ GIMT_Encode4(422704), // Rule ID 5918 //
     /* 422666 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422670 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422674 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422677 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 422682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 422686 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422691 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422693 */     // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 735:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 422693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 422696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422702 */     GIR_RootConstrainSelectedInstOperands,
     /* 422703 */     // GIR_Coverage, 5918,
     /* 422703 */     GIR_EraseRootFromParent_Done,
     /* 422704 */   // Label 8195: @422704
     /* 422704 */   GIM_Try, /*On fail goto*//*Label 8196*/ GIMT_Encode4(422747), // Rule ID 5928 //
     /* 422709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 422717 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 422720 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 422725 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 422729 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422736 */     // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 670:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 422736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 422739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 422745 */     GIR_RootConstrainSelectedInstOperands,
     /* 422746 */     // GIR_Coverage, 5928,
     /* 422746 */     GIR_EraseRootFromParent_Done,
     /* 422747 */   // Label 8196: @422747
     /* 422747 */   GIM_Try, /*On fail goto*//*Label 8197*/ GIMT_Encode4(422782), // Rule ID 5927 //
     /* 422752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 422760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422764 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422769 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422771 */     // (vecreduce_add:{ *:[i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 422771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 422774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422780 */     GIR_RootConstrainSelectedInstOperands,
     /* 422781 */     // GIR_Coverage, 5927,
     /* 422781 */     GIR_EraseRootFromParent_Done,
     /* 422782 */   // Label 8197: @422782
     /* 422782 */   GIM_Try, /*On fail goto*//*Label 8198*/ GIMT_Encode4(422817), // Rule ID 5917 //
     /* 422787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 422795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422799 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422804 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422806 */     // (vecreduce_add:{ *:[i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 422806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 422809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 422815 */     GIR_RootConstrainSelectedInstOperands,
     /* 422816 */     // GIR_Coverage, 5917,
     /* 422816 */     GIR_EraseRootFromParent_Done,
     /* 422817 */   // Label 8198: @422817
     /* 422817 */   GIM_Try, /*On fail goto*//*Label 8199*/ GIMT_Encode4(422833), // Rule ID 5969 //
     /* 422822 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422826 */     // (vecreduce_add:{ *:[i64] } V128:{ *:[v2i64] }:$Rn)  =>  (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn)
     /* 422826 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 422831 */     GIR_RootConstrainSelectedInstOperands,
     /* 422832 */     // GIR_Coverage, 5969,
     /* 422832 */     GIR_Done,
     /* 422833 */   // Label 8199: @422833
     /* 422833 */   GIM_Reject,
     /* 422834 */ // Label 8194: @422834
     /* 422834 */ GIM_Reject,
     /* 422835 */ // Label 8171: @422835
     /* 422835 */ GIM_Reject,
     /* 422836 */ // Label 119: @422836
     /* 422836 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8203*/ GIMT_Encode4(423038),
     /* 422847 */ /*GILLT_s8*//*Label 8200*/ GIMT_Encode4(422859),
     /* 422851 */ /*GILLT_s16*//*Label 8201*/ GIMT_Encode4(422906),
     /* 422855 */ /*GILLT_s32*//*Label 8202*/ GIMT_Encode4(422953),
     /* 422859 */ // Label 8200: @422859
     /* 422859 */ GIM_Try, /*On fail goto*//*Label 8204*/ GIMT_Encode4(422882), // Rule ID 6060 //
     /* 422864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 422867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 422871 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422875 */   // (vecreduce_smax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (SMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 422875 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 422880 */   GIR_RootConstrainSelectedInstOperands,
     /* 422881 */   // GIR_Coverage, 6060,
     /* 422881 */   GIR_Done,
     /* 422882 */ // Label 8204: @422882
     /* 422882 */ GIM_Try, /*On fail goto*//*Label 8205*/ GIMT_Encode4(422905), // Rule ID 6061 //
     /* 422887 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 422890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 422894 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422898 */   // (vecreduce_smax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (SMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 422898 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 422903 */   GIR_RootConstrainSelectedInstOperands,
     /* 422904 */   // GIR_Coverage, 6061,
     /* 422904 */   GIR_Done,
     /* 422905 */ // Label 8205: @422905
     /* 422905 */ GIM_Reject,
     /* 422906 */ // Label 8201: @422906
     /* 422906 */ GIM_Try, /*On fail goto*//*Label 8206*/ GIMT_Encode4(422929), // Rule ID 6062 //
     /* 422911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 422914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422922 */   // (vecreduce_smax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (SMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 422922 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 422927 */   GIR_RootConstrainSelectedInstOperands,
     /* 422928 */   // GIR_Coverage, 6062,
     /* 422928 */   GIR_Done,
     /* 422929 */ // Label 8206: @422929
     /* 422929 */ GIM_Try, /*On fail goto*//*Label 8207*/ GIMT_Encode4(422952), // Rule ID 6063 //
     /* 422934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 422937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422941 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422945 */   // (vecreduce_smax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (SMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 422945 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 422950 */   GIR_RootConstrainSelectedInstOperands,
     /* 422951 */   // GIR_Coverage, 6063,
     /* 422951 */   GIR_Done,
     /* 422952 */ // Label 8207: @422952
     /* 422952 */ GIM_Reject,
     /* 422953 */ // Label 8202: @422953
     /* 422953 */ GIM_Try, /*On fail goto*//*Label 8208*/ GIMT_Encode4(422976), // Rule ID 6064 //
     /* 422958 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 422961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422965 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422969 */   // (vecreduce_smax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 422969 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
     /* 422974 */   GIR_RootConstrainSelectedInstOperands,
     /* 422975 */   // GIR_Coverage, 6064,
     /* 422975 */   GIR_Done,
     /* 422976 */ // Label 8208: @422976
     /* 422976 */ GIM_Try, /*On fail goto*//*Label 8209*/ GIMT_Encode4(423037), // Rule ID 6065 //
     /* 422981 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 422984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 422988 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 422992 */   // (vecreduce_smax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 422992 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 422995 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 422999 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 423004 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423008 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423012 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 423014 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 423017 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 423019 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 423026 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423031 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423036 */   // GIR_Coverage, 6065,
     /* 423036 */   GIR_EraseRootFromParent_Done,
     /* 423037 */ // Label 8209: @423037
     /* 423037 */ GIM_Reject,
     /* 423038 */ // Label 8203: @423038
     /* 423038 */ GIM_Reject,
     /* 423039 */ // Label 120: @423039
     /* 423039 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8213*/ GIMT_Encode4(423241),
     /* 423050 */ /*GILLT_s8*//*Label 8210*/ GIMT_Encode4(423062),
     /* 423054 */ /*GILLT_s16*//*Label 8211*/ GIMT_Encode4(423109),
     /* 423058 */ /*GILLT_s32*//*Label 8212*/ GIMT_Encode4(423156),
     /* 423062 */ // Label 8210: @423062
     /* 423062 */ GIM_Try, /*On fail goto*//*Label 8214*/ GIMT_Encode4(423085), // Rule ID 6054 //
     /* 423067 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423074 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423078 */   // (vecreduce_smin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (SMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 423078 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 423083 */   GIR_RootConstrainSelectedInstOperands,
     /* 423084 */   // GIR_Coverage, 6054,
     /* 423084 */   GIR_Done,
     /* 423085 */ // Label 8214: @423085
     /* 423085 */ GIM_Try, /*On fail goto*//*Label 8215*/ GIMT_Encode4(423108), // Rule ID 6055 //
     /* 423090 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423097 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423101 */   // (vecreduce_smin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (SMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 423101 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 423106 */   GIR_RootConstrainSelectedInstOperands,
     /* 423107 */   // GIR_Coverage, 6055,
     /* 423107 */   GIR_Done,
     /* 423108 */ // Label 8215: @423108
     /* 423108 */ GIM_Reject,
     /* 423109 */ // Label 8211: @423109
     /* 423109 */ GIM_Try, /*On fail goto*//*Label 8216*/ GIMT_Encode4(423132), // Rule ID 6056 //
     /* 423114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 423117 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423121 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423125 */   // (vecreduce_smin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (SMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 423125 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 423130 */   GIR_RootConstrainSelectedInstOperands,
     /* 423131 */   // GIR_Coverage, 6056,
     /* 423131 */   GIR_Done,
     /* 423132 */ // Label 8216: @423132
     /* 423132 */ GIM_Try, /*On fail goto*//*Label 8217*/ GIMT_Encode4(423155), // Rule ID 6057 //
     /* 423137 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 423140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423144 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423148 */   // (vecreduce_smin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (SMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 423148 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 423153 */   GIR_RootConstrainSelectedInstOperands,
     /* 423154 */   // GIR_Coverage, 6057,
     /* 423154 */   GIR_Done,
     /* 423155 */ // Label 8217: @423155
     /* 423155 */ GIM_Reject,
     /* 423156 */ // Label 8212: @423156
     /* 423156 */ GIM_Try, /*On fail goto*//*Label 8218*/ GIMT_Encode4(423179), // Rule ID 6058 //
     /* 423161 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 423164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423168 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423172 */   // (vecreduce_smin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 423172 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
     /* 423177 */   GIR_RootConstrainSelectedInstOperands,
     /* 423178 */   // GIR_Coverage, 6058,
     /* 423178 */   GIR_Done,
     /* 423179 */ // Label 8218: @423179
     /* 423179 */ GIM_Try, /*On fail goto*//*Label 8219*/ GIMT_Encode4(423240), // Rule ID 6059 //
     /* 423184 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423191 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423195 */   // (vecreduce_smin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 423195 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 423198 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 423202 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 423207 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423211 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423215 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 423217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 423220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 423222 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 423229 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423234 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423239 */   // GIR_Coverage, 6059,
     /* 423239 */   GIR_EraseRootFromParent_Done,
     /* 423240 */ // Label 8219: @423240
     /* 423240 */ GIM_Reject,
     /* 423241 */ // Label 8213: @423241
     /* 423241 */ GIM_Reject,
     /* 423242 */ // Label 121: @423242
     /* 423242 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8223*/ GIMT_Encode4(423444),
     /* 423253 */ /*GILLT_s8*//*Label 8220*/ GIMT_Encode4(423265),
     /* 423257 */ /*GILLT_s16*//*Label 8221*/ GIMT_Encode4(423312),
     /* 423261 */ /*GILLT_s32*//*Label 8222*/ GIMT_Encode4(423359),
     /* 423265 */ // Label 8220: @423265
     /* 423265 */ GIM_Try, /*On fail goto*//*Label 8224*/ GIMT_Encode4(423288), // Rule ID 6048 //
     /* 423270 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423277 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423281 */   // (vecreduce_umax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (UMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 423281 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 423286 */   GIR_RootConstrainSelectedInstOperands,
     /* 423287 */   // GIR_Coverage, 6048,
     /* 423287 */   GIR_Done,
     /* 423288 */ // Label 8224: @423288
     /* 423288 */ GIM_Try, /*On fail goto*//*Label 8225*/ GIMT_Encode4(423311), // Rule ID 6049 //
     /* 423293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423300 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423304 */   // (vecreduce_umax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (UMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 423304 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 423309 */   GIR_RootConstrainSelectedInstOperands,
     /* 423310 */   // GIR_Coverage, 6049,
     /* 423310 */   GIR_Done,
     /* 423311 */ // Label 8225: @423311
     /* 423311 */ GIM_Reject,
     /* 423312 */ // Label 8221: @423312
     /* 423312 */ GIM_Try, /*On fail goto*//*Label 8226*/ GIMT_Encode4(423335), // Rule ID 6050 //
     /* 423317 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 423320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423324 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423328 */   // (vecreduce_umax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (UMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 423328 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 423333 */   GIR_RootConstrainSelectedInstOperands,
     /* 423334 */   // GIR_Coverage, 6050,
     /* 423334 */   GIR_Done,
     /* 423335 */ // Label 8226: @423335
     /* 423335 */ GIM_Try, /*On fail goto*//*Label 8227*/ GIMT_Encode4(423358), // Rule ID 6051 //
     /* 423340 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 423343 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423347 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423351 */   // (vecreduce_umax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (UMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 423351 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 423356 */   GIR_RootConstrainSelectedInstOperands,
     /* 423357 */   // GIR_Coverage, 6051,
     /* 423357 */   GIR_Done,
     /* 423358 */ // Label 8227: @423358
     /* 423358 */ GIM_Reject,
     /* 423359 */ // Label 8222: @423359
     /* 423359 */ GIM_Try, /*On fail goto*//*Label 8228*/ GIMT_Encode4(423382), // Rule ID 6052 //
     /* 423364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 423367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423371 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423375 */   // (vecreduce_umax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 423375 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
     /* 423380 */   GIR_RootConstrainSelectedInstOperands,
     /* 423381 */   // GIR_Coverage, 6052,
     /* 423381 */   GIR_Done,
     /* 423382 */ // Label 8228: @423382
     /* 423382 */ GIM_Try, /*On fail goto*//*Label 8229*/ GIMT_Encode4(423443), // Rule ID 6053 //
     /* 423387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423394 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423398 */   // (vecreduce_umax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 423398 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 423401 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 423405 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 423410 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423414 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423418 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 423420 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 423423 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 423425 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 423432 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423437 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423442 */   // GIR_Coverage, 6053,
     /* 423442 */   GIR_EraseRootFromParent_Done,
     /* 423443 */ // Label 8229: @423443
     /* 423443 */ GIM_Reject,
     /* 423444 */ // Label 8223: @423444
     /* 423444 */ GIM_Reject,
     /* 423445 */ // Label 122: @423445
     /* 423445 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8233*/ GIMT_Encode4(423647),
     /* 423456 */ /*GILLT_s8*//*Label 8230*/ GIMT_Encode4(423468),
     /* 423460 */ /*GILLT_s16*//*Label 8231*/ GIMT_Encode4(423515),
     /* 423464 */ /*GILLT_s32*//*Label 8232*/ GIMT_Encode4(423562),
     /* 423468 */ // Label 8230: @423468
     /* 423468 */ GIM_Try, /*On fail goto*//*Label 8234*/ GIMT_Encode4(423491), // Rule ID 6042 //
     /* 423473 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423480 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423484 */   // (vecreduce_umin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (UMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 423484 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 423489 */   GIR_RootConstrainSelectedInstOperands,
     /* 423490 */   // GIR_Coverage, 6042,
     /* 423490 */   GIR_Done,
     /* 423491 */ // Label 8234: @423491
     /* 423491 */ GIM_Try, /*On fail goto*//*Label 8235*/ GIMT_Encode4(423514), // Rule ID 6043 //
     /* 423496 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 423503 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423507 */   // (vecreduce_umin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (UMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 423507 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 423512 */   GIR_RootConstrainSelectedInstOperands,
     /* 423513 */   // GIR_Coverage, 6043,
     /* 423513 */   GIR_Done,
     /* 423514 */ // Label 8235: @423514
     /* 423514 */ GIM_Reject,
     /* 423515 */ // Label 8231: @423515
     /* 423515 */ GIM_Try, /*On fail goto*//*Label 8236*/ GIMT_Encode4(423538), // Rule ID 6044 //
     /* 423520 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 423523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423527 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423531 */   // (vecreduce_umin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (UMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 423531 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 423536 */   GIR_RootConstrainSelectedInstOperands,
     /* 423537 */   // GIR_Coverage, 6044,
     /* 423537 */   GIR_Done,
     /* 423538 */ // Label 8236: @423538
     /* 423538 */ GIM_Try, /*On fail goto*//*Label 8237*/ GIMT_Encode4(423561), // Rule ID 6045 //
     /* 423543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 423546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423550 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423554 */   // (vecreduce_umin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (UMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 423554 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 423559 */   GIR_RootConstrainSelectedInstOperands,
     /* 423560 */   // GIR_Coverage, 6045,
     /* 423560 */   GIR_Done,
     /* 423561 */ // Label 8237: @423561
     /* 423561 */ GIM_Reject,
     /* 423562 */ // Label 8232: @423562
     /* 423562 */ GIM_Try, /*On fail goto*//*Label 8238*/ GIMT_Encode4(423585), // Rule ID 6046 //
     /* 423567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 423570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423574 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423578 */   // (vecreduce_umin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 423578 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
     /* 423583 */   GIR_RootConstrainSelectedInstOperands,
     /* 423584 */   // GIR_Coverage, 6046,
     /* 423584 */   GIR_Done,
     /* 423585 */ // Label 8238: @423585
     /* 423585 */ GIM_Try, /*On fail goto*//*Label 8239*/ GIMT_Encode4(423646), // Rule ID 6047 //
     /* 423590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423597 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423601 */   // (vecreduce_umin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 423601 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 423604 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 423608 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 423613 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423617 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 423621 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 423623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 423626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 423628 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 423635 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423640 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423645 */   // GIR_Coverage, 6047,
     /* 423645 */   GIR_EraseRootFromParent_Done,
     /* 423646 */ // Label 8239: @423646
     /* 423646 */ GIM_Reject,
     /* 423647 */ // Label 8233: @423647
     /* 423647 */ GIM_Reject,
     /* 423648 */ // Label 123: @423648
     /* 423648 */ GIM_Try, /*On fail goto*//*Label 8240*/ GIMT_Encode4(423787),
     /* 423653 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 423656 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 423660 */   GIM_Try, /*On fail goto*//*Label 8241*/ GIMT_Encode4(423694), // Rule ID 261 //
     /* 423665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 423672 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))  =>  (PRFMroW (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 423672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroW),
     /* 423675 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 423677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 423682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 423687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 423692 */     GIR_RootConstrainSelectedInstOperands,
     /* 423693 */     // GIR_Coverage, 261,
     /* 423693 */     GIR_EraseRootFromParent_Done,
     /* 423694 */   // Label 8241: @423694
     /* 423694 */   GIM_Try, /*On fail goto*//*Label 8242*/ GIMT_Encode4(423728), // Rule ID 262 //
     /* 423699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 423706 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))  =>  (PRFMroX (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 423706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroX),
     /* 423709 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 423711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 423716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 423721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 423726 */     GIR_RootConstrainSelectedInstOperands,
     /* 423727 */     // GIR_Coverage, 262,
     /* 423727 */     GIR_EraseRootFromParent_Done,
     /* 423728 */   // Label 8242: @423728
     /* 423728 */   GIM_Try, /*On fail goto*//*Label 8243*/ GIMT_Encode4(423757), // Rule ID 277 //
     /* 423733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 423740 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))  =>  (PRFMui (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 423740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMui),
     /* 423743 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 423745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 423750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 423755 */     GIR_RootConstrainSelectedInstOperands,
     /* 423756 */     // GIR_Coverage, 277,
     /* 423756 */     GIR_EraseRootFromParent_Done,
     /* 423757 */   // Label 8243: @423757
     /* 423757 */   GIM_Try, /*On fail goto*//*Label 8244*/ GIMT_Encode4(423786), // Rule ID 298 //
     /* 423762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 423769 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))  =>  (PRFUMi (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 423769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFUMi),
     /* 423772 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 423774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 423779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 423784 */     GIR_RootConstrainSelectedInstOperands,
     /* 423785 */     // GIR_Coverage, 298,
     /* 423785 */     GIR_EraseRootFromParent_Done,
     /* 423786 */   // Label 8244: @423786
     /* 423786 */   GIM_Reject,
     /* 423787 */ // Label 8240: @423787
     /* 423787 */ GIM_Reject,
     /* 423788 */ // Label 124: @423788
     /* 423788 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 8257*/ GIMT_Encode4(424775),
     /* 423799 */ /*GILLT_s64*//*Label 8245*/ GIMT_Encode4(423883), GIMT_Encode4(0),
     /* 423807 */ /*GILLT_v2s32*//*Label 8246*/ GIMT_Encode4(423921),
     /* 423811 */ /*GILLT_v2s64*//*Label 8247*/ GIMT_Encode4(423959),
     /* 423815 */ /*GILLT_v4s16*//*Label 8248*/ GIMT_Encode4(423997),
     /* 423819 */ /*GILLT_v4s32*//*Label 8249*/ GIMT_Encode4(424035),
     /* 423823 */ /*GILLT_v8s8*//*Label 8250*/ GIMT_Encode4(424073),
     /* 423827 */ /*GILLT_v8s16*//*Label 8251*/ GIMT_Encode4(424111),
     /* 423831 */ /*GILLT_v16s8*//*Label 8252*/ GIMT_Encode4(424149), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 423851 */ /*GILLT_nxv2s64*//*Label 8253*/ GIMT_Encode4(424187), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 423863 */ /*GILLT_nxv4s32*//*Label 8254*/ GIMT_Encode4(424334), GIMT_Encode4(0),
     /* 423871 */ /*GILLT_nxv8s16*//*Label 8255*/ GIMT_Encode4(424481), GIMT_Encode4(0),
     /* 423879 */ /*GILLT_nxv16s8*//*Label 8256*/ GIMT_Encode4(424628),
     /* 423883 */ // Label 8245: @423883
     /* 423883 */ GIM_Try, /*On fail goto*//*Label 8258*/ GIMT_Encode4(423920), // Rule ID 5117 //
     /* 423888 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 423891 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 423894 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 423897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423901 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423905 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423909 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423913 */   // (AArch64bsp:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)
     /* 423913 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 423918 */   GIR_RootConstrainSelectedInstOperands,
     /* 423919 */   // GIR_Coverage, 5117,
     /* 423919 */   GIR_Done,
     /* 423920 */ // Label 8258: @423920
     /* 423920 */ GIM_Reject,
     /* 423921 */ // Label 8246: @423921
     /* 423921 */ GIM_Try, /*On fail goto*//*Label 8259*/ GIMT_Encode4(423958), // Rule ID 5116 //
     /* 423926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423929 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 423932 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 423935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423939 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423943 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423947 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423951 */   // (AArch64bsp:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 423951 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 423956 */   GIR_RootConstrainSelectedInstOperands,
     /* 423957 */   // GIR_Coverage, 5116,
     /* 423957 */   GIR_Done,
     /* 423958 */ // Label 8259: @423958
     /* 423958 */ GIM_Reject,
     /* 423959 */ // Label 8247: @423959
     /* 423959 */ GIM_Try, /*On fail goto*//*Label 8260*/ GIMT_Encode4(423996), // Rule ID 5121 //
     /* 423964 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 423967 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 423970 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 423973 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423977 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423981 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423985 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423989 */   // (AArch64bsp:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 423989 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 423994 */   GIR_RootConstrainSelectedInstOperands,
     /* 423995 */   // GIR_Coverage, 5121,
     /* 423995 */   GIR_Done,
     /* 423996 */ // Label 8260: @423996
     /* 423996 */ GIM_Reject,
     /* 423997 */ // Label 8248: @423997
     /* 423997 */ GIM_Try, /*On fail goto*//*Label 8261*/ GIMT_Encode4(424034), // Rule ID 5115 //
     /* 424002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 424005 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 424008 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 424011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424015 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424019 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424023 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424027 */   // (AArch64bsp:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 424027 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 424032 */   GIR_RootConstrainSelectedInstOperands,
     /* 424033 */   // GIR_Coverage, 5115,
     /* 424033 */   GIR_Done,
     /* 424034 */ // Label 8261: @424034
     /* 424034 */ GIM_Reject,
     /* 424035 */ // Label 8249: @424035
     /* 424035 */ GIM_Try, /*On fail goto*//*Label 8262*/ GIMT_Encode4(424072), // Rule ID 5120 //
     /* 424040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 424043 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 424046 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 424049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424053 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424057 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424061 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424065 */   // (AArch64bsp:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 424065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 424070 */   GIR_RootConstrainSelectedInstOperands,
     /* 424071 */   // GIR_Coverage, 5120,
     /* 424071 */   GIR_Done,
     /* 424072 */ // Label 8262: @424072
     /* 424072 */ GIM_Reject,
     /* 424073 */ // Label 8250: @424073
     /* 424073 */ GIM_Try, /*On fail goto*//*Label 8263*/ GIMT_Encode4(424110), // Rule ID 5114 //
     /* 424078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 424081 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 424084 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 424087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424091 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424095 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424099 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424103 */   // (AArch64bsp:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 424103 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 424108 */   GIR_RootConstrainSelectedInstOperands,
     /* 424109 */   // GIR_Coverage, 5114,
     /* 424109 */   GIR_Done,
     /* 424110 */ // Label 8263: @424110
     /* 424110 */ GIM_Reject,
     /* 424111 */ // Label 8251: @424111
     /* 424111 */ GIM_Try, /*On fail goto*//*Label 8264*/ GIMT_Encode4(424148), // Rule ID 5119 //
     /* 424116 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 424119 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 424122 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 424125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424129 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424133 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424137 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424141 */   // (AArch64bsp:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 424141 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 424146 */   GIR_RootConstrainSelectedInstOperands,
     /* 424147 */   // GIR_Coverage, 5119,
     /* 424147 */   GIR_Done,
     /* 424148 */ // Label 8264: @424148
     /* 424148 */ GIM_Reject,
     /* 424149 */ // Label 8252: @424149
     /* 424149 */ GIM_Try, /*On fail goto*//*Label 8265*/ GIMT_Encode4(424186), // Rule ID 5118 //
     /* 424154 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 424157 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 424160 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 424163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424167 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424171 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424175 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424179 */   // (AArch64bsp:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 424179 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 424184 */   GIR_RootConstrainSelectedInstOperands,
     /* 424185 */   // GIR_Coverage, 5118,
     /* 424185 */   GIR_Done,
     /* 424186 */ // Label 8265: @424186
     /* 424186 */ GIM_Reject,
     /* 424187 */ // Label 8253: @424187
     /* 424187 */ GIM_Try, /*On fail goto*//*Label 8266*/ GIMT_Encode4(424333),
     /* 424192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 424195 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 424198 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 424201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 424205 */   GIM_Try, /*On fail goto*//*Label 8267*/ GIMT_Encode4(424258), // Rule ID 12070 //
     /* 424210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424213 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 424217 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424221 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 424225 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 424229 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424233 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424239 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424241 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424243 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 424243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 424246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 424252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424254 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424256 */     GIR_RootConstrainSelectedInstOperands,
     /* 424257 */     // GIR_Coverage, 12070,
     /* 424257 */     GIR_EraseRootFromParent_Done,
     /* 424258 */   // Label 8267: @424258
     /* 424258 */   GIM_Try, /*On fail goto*//*Label 8268*/ GIMT_Encode4(424311), // Rule ID 12097 //
     /* 424263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 424270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 424278 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 424282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424286 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424292 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424294 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424296 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 424296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 424299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 424307 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424309 */     GIR_RootConstrainSelectedInstOperands,
     /* 424310 */     // GIR_Coverage, 12097,
     /* 424310 */     GIR_EraseRootFromParent_Done,
     /* 424311 */   // Label 8268: @424311
     /* 424311 */   GIM_Try, /*On fail goto*//*Label 8269*/ GIMT_Encode4(424332), // Rule ID 12046 //
     /* 424316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424319 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 424319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 424322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424328 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424330 */     GIR_RootConstrainSelectedInstOperands,
     /* 424331 */     // GIR_Coverage, 12046,
     /* 424331 */     GIR_EraseRootFromParent_Done,
     /* 424332 */   // Label 8269: @424332
     /* 424332 */   GIM_Reject,
     /* 424333 */ // Label 8266: @424333
     /* 424333 */ GIM_Reject,
     /* 424334 */ // Label 8254: @424334
     /* 424334 */ GIM_Try, /*On fail goto*//*Label 8270*/ GIMT_Encode4(424480),
     /* 424339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 424342 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 424345 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 424348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 424352 */   GIM_Try, /*On fail goto*//*Label 8271*/ GIMT_Encode4(424405), // Rule ID 12068 //
     /* 424357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424360 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 424364 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424368 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 424372 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 424376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424380 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424386 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424388 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424390 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 424390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 424393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 424399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424401 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424403 */     GIR_RootConstrainSelectedInstOperands,
     /* 424404 */     // GIR_Coverage, 12068,
     /* 424404 */     GIR_EraseRootFromParent_Done,
     /* 424405 */   // Label 8271: @424405
     /* 424405 */   GIM_Try, /*On fail goto*//*Label 8272*/ GIMT_Encode4(424458), // Rule ID 12094 //
     /* 424410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 424417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 424425 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 424429 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424433 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424439 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424441 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424443 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 424443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 424446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 424454 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424456 */     GIR_RootConstrainSelectedInstOperands,
     /* 424457 */     // GIR_Coverage, 12094,
     /* 424457 */     GIR_EraseRootFromParent_Done,
     /* 424458 */   // Label 8272: @424458
     /* 424458 */   GIM_Try, /*On fail goto*//*Label 8273*/ GIMT_Encode4(424479), // Rule ID 12044 //
     /* 424463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424466 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 424466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 424469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424475 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424477 */     GIR_RootConstrainSelectedInstOperands,
     /* 424478 */     // GIR_Coverage, 12044,
     /* 424478 */     GIR_EraseRootFromParent_Done,
     /* 424479 */   // Label 8273: @424479
     /* 424479 */   GIM_Reject,
     /* 424480 */ // Label 8270: @424480
     /* 424480 */ GIM_Reject,
     /* 424481 */ // Label 8255: @424481
     /* 424481 */ GIM_Try, /*On fail goto*//*Label 8274*/ GIMT_Encode4(424627),
     /* 424486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 424489 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 424492 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 424495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 424499 */   GIM_Try, /*On fail goto*//*Label 8275*/ GIMT_Encode4(424552), // Rule ID 12066 //
     /* 424504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424507 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 424511 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424515 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 424519 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 424523 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424527 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424533 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424535 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424537 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 424537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 424540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 424546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424548 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424550 */     GIR_RootConstrainSelectedInstOperands,
     /* 424551 */     // GIR_Coverage, 12066,
     /* 424551 */     GIR_EraseRootFromParent_Done,
     /* 424552 */   // Label 8275: @424552
     /* 424552 */   GIM_Try, /*On fail goto*//*Label 8276*/ GIMT_Encode4(424605), // Rule ID 12091 //
     /* 424557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 424564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424568 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 424572 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 424576 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424580 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424586 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424588 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424590 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 424590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 424593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424597 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 424601 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424603 */     GIR_RootConstrainSelectedInstOperands,
     /* 424604 */     // GIR_Coverage, 12091,
     /* 424604 */     GIR_EraseRootFromParent_Done,
     /* 424605 */   // Label 8276: @424605
     /* 424605 */   GIM_Try, /*On fail goto*//*Label 8277*/ GIMT_Encode4(424626), // Rule ID 12042 //
     /* 424610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424613 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 424613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 424616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424622 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424624 */     GIR_RootConstrainSelectedInstOperands,
     /* 424625 */     // GIR_Coverage, 12042,
     /* 424625 */     GIR_EraseRootFromParent_Done,
     /* 424626 */   // Label 8277: @424626
     /* 424626 */   GIM_Reject,
     /* 424627 */ // Label 8274: @424627
     /* 424627 */ GIM_Reject,
     /* 424628 */ // Label 8256: @424628
     /* 424628 */ GIM_Try, /*On fail goto*//*Label 8278*/ GIMT_Encode4(424774),
     /* 424633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 424636 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 424639 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 424642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 424646 */   GIM_Try, /*On fail goto*//*Label 8279*/ GIMT_Encode4(424699), // Rule ID 12064 //
     /* 424651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 424658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424662 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 424666 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 424670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424674 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424680 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424682 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424684 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 424684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 424687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 424693 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424695 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424697 */     GIR_RootConstrainSelectedInstOperands,
     /* 424698 */     // GIR_Coverage, 12064,
     /* 424698 */     GIR_EraseRootFromParent_Done,
     /* 424699 */   // Label 8279: @424699
     /* 424699 */   GIM_Try, /*On fail goto*//*Label 8280*/ GIMT_Encode4(424752), // Rule ID 12088 //
     /* 424704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424707 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 424711 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 424715 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 424719 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 424723 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 424727 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 424733 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 424735 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 424737 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 424737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 424740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424744 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 424748 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424750 */     GIR_RootConstrainSelectedInstOperands,
     /* 424751 */     // GIR_Coverage, 12088,
     /* 424751 */     GIR_EraseRootFromParent_Done,
     /* 424752 */   // Label 8280: @424752
     /* 424752 */   GIM_Try, /*On fail goto*//*Label 8281*/ GIMT_Encode4(424773), // Rule ID 12040 //
     /* 424757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 424760 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 424760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 424763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 424765 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 424767 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 424769 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 424771 */     GIR_RootConstrainSelectedInstOperands,
     /* 424772 */     // GIR_Coverage, 12040,
     /* 424772 */     GIR_EraseRootFromParent_Done,
     /* 424773 */   // Label 8281: @424773
     /* 424773 */   GIM_Reject,
     /* 424774 */ // Label 8278: @424774
     /* 424774 */ GIM_Reject,
     /* 424775 */ // Label 8257: @424775
     /* 424775 */ GIM_Reject,
     /* 424776 */ // Label 125: @424776
     /* 424776 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 8290*/ GIMT_Encode4(426758),
     /* 424787 */ /*GILLT_s64*//*Label 8282*/ GIMT_Encode4(424823), GIMT_Encode4(0),
     /* 424795 */ /*GILLT_v2s32*//*Label 8283*/ GIMT_Encode4(425018),
     /* 424799 */ /*GILLT_v2s64*//*Label 8284*/ GIMT_Encode4(425265),
     /* 424803 */ /*GILLT_v4s16*//*Label 8285*/ GIMT_Encode4(425512),
     /* 424807 */ /*GILLT_v4s32*//*Label 8286*/ GIMT_Encode4(425788),
     /* 424811 */ /*GILLT_v8s8*//*Label 8287*/ GIMT_Encode4(426035),
     /* 424815 */ /*GILLT_v8s16*//*Label 8288*/ GIMT_Encode4(426260),
     /* 424819 */ /*GILLT_v16s8*//*Label 8289*/ GIMT_Encode4(426536),
     /* 424823 */ // Label 8282: @424823
     /* 424823 */ GIM_Try, /*On fail goto*//*Label 8291*/ GIMT_Encode4(425017),
     /* 424828 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 424831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424835 */   GIM_Try, /*On fail goto*//*Label 8292*/ GIMT_Encode4(424882), // Rule ID 6495 //
     /* 424840 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 424844 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 424848 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 424851 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 424855 */     // MIs[1] Rn
     /* 424855 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 424859 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 424864 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 424866 */     // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 424866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 424869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 424871 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 424875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 424880 */     GIR_RootConstrainSelectedInstOperands,
     /* 424881 */     // GIR_Coverage, 6495,
     /* 424881 */     GIR_EraseRootFromParent_Done,
     /* 424882 */   // Label 8292: @424882
     /* 424882 */   GIM_Try, /*On fail goto*//*Label 8293*/ GIMT_Encode4(424929), // Rule ID 6506 //
     /* 424887 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 424891 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 424895 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 424898 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 424902 */     // MIs[1] Rn
     /* 424902 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 424906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 424911 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 424913 */     // (AArch64dup:{ *:[v1f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 424913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 424916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 424918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 424922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 424927 */     GIR_RootConstrainSelectedInstOperands,
     /* 424928 */     // GIR_Coverage, 6506,
     /* 424928 */     GIR_EraseRootFromParent_Done,
     /* 424929 */   // Label 8293: @424929
     /* 424929 */   GIM_Try, /*On fail goto*//*Label 8294*/ GIMT_Encode4(424976), // Rule ID 13502 //
     /* 424934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 424938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 424942 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 424945 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 424949 */     // MIs[1] Rn
     /* 424949 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 424953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 424958 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 424960 */     // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 424960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 424963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 424965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 424969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 424974 */     GIR_RootConstrainSelectedInstOperands,
     /* 424975 */     // GIR_Coverage, 13502,
     /* 424975 */     GIR_EraseRootFromParent_Done,
     /* 424976 */   // Label 8294: @424976
     /* 424976 */   GIM_Try, /*On fail goto*//*Label 8295*/ GIMT_Encode4(424996), // Rule ID 5680 //
     /* 424981 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 424985 */     // (AArch64dup:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i32] })
     /* 424985 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 424990 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424995 */     // GIR_Coverage, 5680,
     /* 424995 */     GIR_Done,
     /* 424996 */   // Label 8295: @424996
     /* 424996 */   GIM_Try, /*On fail goto*//*Label 8296*/ GIMT_Encode4(425016), // Rule ID 5681 //
     /* 425001 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425005 */     // (AArch64dup:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[i32] })
     /* 425005 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 425010 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425015 */     // GIR_Coverage, 5681,
     /* 425015 */     GIR_Done,
     /* 425016 */   // Label 8296: @425016
     /* 425016 */   GIM_Reject,
     /* 425017 */ // Label 8291: @425017
     /* 425017 */ GIM_Reject,
     /* 425018 */ // Label 8283: @425018
     /* 425018 */ GIM_Try, /*On fail goto*//*Label 8297*/ GIMT_Encode4(425264),
     /* 425023 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425030 */   GIM_Try, /*On fail goto*//*Label 8298*/ GIMT_Encode4(425077), // Rule ID 6492 //
     /* 425035 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425039 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425043 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425046 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425050 */     // MIs[1] Rn
     /* 425050 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425059 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425061 */     // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 425064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425066 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425075 */     GIR_RootConstrainSelectedInstOperands,
     /* 425076 */     // GIR_Coverage, 6492,
     /* 425076 */     GIR_EraseRootFromParent_Done,
     /* 425077 */   // Label 8298: @425077
     /* 425077 */   GIM_Try, /*On fail goto*//*Label 8299*/ GIMT_Encode4(425124), // Rule ID 6503 //
     /* 425082 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425086 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425090 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425093 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425097 */     // MIs[1] Rn
     /* 425097 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425101 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425106 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425108 */     // (AArch64dup:{ *:[v2f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 425111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425122 */     GIR_RootConstrainSelectedInstOperands,
     /* 425123 */     // GIR_Coverage, 6503,
     /* 425123 */     GIR_EraseRootFromParent_Done,
     /* 425124 */   // Label 8299: @425124
     /* 425124 */   GIM_Try, /*On fail goto*//*Label 8300*/ GIMT_Encode4(425171), // Rule ID 13499 //
     /* 425129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425137 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425140 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425144 */     // MIs[1] Rn
     /* 425144 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425148 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425153 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425155 */     // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 425158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425169 */     GIR_RootConstrainSelectedInstOperands,
     /* 425170 */     // GIR_Coverage, 13499,
     /* 425170 */     GIR_EraseRootFromParent_Done,
     /* 425171 */   // Label 8300: @425171
     /* 425171 */   GIM_Try, /*On fail goto*//*Label 8301*/ GIMT_Encode4(425190), // Rule ID 1920 //
     /* 425176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425179 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 425183 */     // (AArch64dup:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv2i32gpr:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn)
     /* 425183 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32gpr),
     /* 425188 */     GIR_RootConstrainSelectedInstOperands,
     /* 425189 */     // GIR_Coverage, 1920,
     /* 425189 */     GIR_Done,
     /* 425190 */   // Label 8301: @425190
     /* 425190 */   GIM_Try, /*On fail goto*//*Label 8302*/ GIMT_Encode4(425263), // Rule ID 5682 //
     /* 425195 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425199 */     // (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rn)  =>  (DUPv2i32lane:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 425199 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 425202 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425206 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425211 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425213 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 425216 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425220 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425225 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425228 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 425232 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 425235 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425240 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425245 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 425253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 425255 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 425258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 425261 */     GIR_RootConstrainSelectedInstOperands,
     /* 425262 */     // GIR_Coverage, 5682,
     /* 425262 */     GIR_EraseRootFromParent_Done,
     /* 425263 */   // Label 8302: @425263
     /* 425263 */   GIM_Reject,
     /* 425264 */ // Label 8297: @425264
     /* 425264 */ GIM_Reject,
     /* 425265 */ // Label 8284: @425265
     /* 425265 */ GIM_Try, /*On fail goto*//*Label 8303*/ GIMT_Encode4(425511),
     /* 425270 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 425273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425277 */   GIM_Try, /*On fail goto*//*Label 8304*/ GIMT_Encode4(425324), // Rule ID 6494 //
     /* 425282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425290 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425293 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425297 */     // MIs[1] Rn
     /* 425297 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425301 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425306 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425308 */     // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 425311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425313 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425322 */     GIR_RootConstrainSelectedInstOperands,
     /* 425323 */     // GIR_Coverage, 6494,
     /* 425323 */     GIR_EraseRootFromParent_Done,
     /* 425324 */   // Label 8304: @425324
     /* 425324 */   GIM_Try, /*On fail goto*//*Label 8305*/ GIMT_Encode4(425371), // Rule ID 6505 //
     /* 425329 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425333 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425337 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425340 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425344 */     // MIs[1] Rn
     /* 425344 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425348 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425353 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425355 */     // (AArch64dup:{ *:[v2f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 425358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425369 */     GIR_RootConstrainSelectedInstOperands,
     /* 425370 */     // GIR_Coverage, 6505,
     /* 425370 */     GIR_EraseRootFromParent_Done,
     /* 425371 */   // Label 8305: @425371
     /* 425371 */   GIM_Try, /*On fail goto*//*Label 8306*/ GIMT_Encode4(425418), // Rule ID 13501 //
     /* 425376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425380 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425384 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425387 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425391 */     // MIs[1] Rn
     /* 425391 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425395 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425400 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425402 */     // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 425405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425416 */     GIR_RootConstrainSelectedInstOperands,
     /* 425417 */     // GIR_Coverage, 13501,
     /* 425417 */     GIR_EraseRootFromParent_Done,
     /* 425418 */   // Label 8306: @425418
     /* 425418 */   GIM_Try, /*On fail goto*//*Label 8307*/ GIMT_Encode4(425437), // Rule ID 1922 //
     /* 425423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 425430 */     // (AArch64dup:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn)  =>  (DUPv2i64gpr:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn)
     /* 425430 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64gpr),
     /* 425435 */     GIR_RootConstrainSelectedInstOperands,
     /* 425436 */     // GIR_Coverage, 1922,
     /* 425436 */     GIR_Done,
     /* 425437 */   // Label 8307: @425437
     /* 425437 */   GIM_Try, /*On fail goto*//*Label 8308*/ GIMT_Encode4(425510), // Rule ID 5684 //
     /* 425442 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425446 */     // (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rn)  =>  (DUPv2i64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 425446 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 425449 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425453 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425460 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 425463 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425467 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425472 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425475 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 425479 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 425482 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425487 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425492 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 425500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 425502 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 425505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 425508 */     GIR_RootConstrainSelectedInstOperands,
     /* 425509 */     // GIR_Coverage, 5684,
     /* 425509 */     GIR_EraseRootFromParent_Done,
     /* 425510 */   // Label 8308: @425510
     /* 425510 */   GIM_Reject,
     /* 425511 */ // Label 8303: @425511
     /* 425511 */ GIM_Reject,
     /* 425512 */ // Label 8285: @425512
     /* 425512 */ GIM_Try, /*On fail goto*//*Label 8309*/ GIMT_Encode4(425573), // Rule ID 6490 //
     /* 425517 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425524 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425528 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425532 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425535 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425539 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 425546 */   // MIs[1] Rn
     /* 425546 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425550 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425555 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425557 */   // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>)  =>  (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 425560 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425562 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425566 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425571 */   GIR_RootConstrainSelectedInstOperands,
     /* 425572 */   // GIR_Coverage, 6490,
     /* 425572 */   GIR_EraseRootFromParent_Done,
     /* 425573 */ // Label 8309: @425573
     /* 425573 */ GIM_Try, /*On fail goto*//*Label 8310*/ GIMT_Encode4(425627), // Rule ID 6507 //
     /* 425578 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 425581 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425585 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425589 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425593 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425596 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425600 */   // MIs[1] Rn
     /* 425600 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425604 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425609 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425611 */   // (AArch64dup:{ *:[v4f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4h:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 425614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425616 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425620 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425625 */   GIR_RootConstrainSelectedInstOperands,
     /* 425626 */   // GIR_Coverage, 6507,
     /* 425626 */   GIR_EraseRootFromParent_Done,
     /* 425627 */ // Label 8310: @425627
     /* 425627 */ GIM_Try, /*On fail goto*//*Label 8311*/ GIMT_Encode4(425681), // Rule ID 13497 //
     /* 425632 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 425635 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425639 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425643 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425647 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425650 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425654 */   // MIs[1] Rn
     /* 425654 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425658 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425663 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425665 */   // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 425668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425670 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425679 */   GIR_RootConstrainSelectedInstOperands,
     /* 425680 */   // GIR_Coverage, 13497,
     /* 425680 */   GIR_EraseRootFromParent_Done,
     /* 425681 */ // Label 8311: @425681
     /* 425681 */ GIM_Try, /*On fail goto*//*Label 8312*/ GIMT_Encode4(425707), // Rule ID 1918 //
     /* 425686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425689 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425692 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425696 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 425700 */   // (AArch64dup:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv4i16gpr:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn)
     /* 425700 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16gpr),
     /* 425705 */   GIR_RootConstrainSelectedInstOperands,
     /* 425706 */   // GIR_Coverage, 1918,
     /* 425706 */   GIR_Done,
     /* 425707 */ // Label 8312: @425707
     /* 425707 */ GIM_Try, /*On fail goto*//*Label 8313*/ GIMT_Encode4(425787), // Rule ID 5685 //
     /* 425712 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 425715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425719 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425723 */   // (AArch64dup:{ *:[v4f16] } FPR16:{ *:[f16] }:$Rn)  =>  (DUPv4i16lane:{ *:[v4f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 425723 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 425726 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425730 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425735 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425737 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 425740 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425744 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425749 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425752 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 425756 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 425759 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425764 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425769 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 425777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 425779 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 425782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 425785 */   GIR_RootConstrainSelectedInstOperands,
     /* 425786 */   // GIR_Coverage, 5685,
     /* 425786 */   GIR_EraseRootFromParent_Done,
     /* 425787 */ // Label 8313: @425787
     /* 425787 */ GIM_Reject,
     /* 425788 */ // Label 8286: @425788
     /* 425788 */ GIM_Try, /*On fail goto*//*Label 8314*/ GIMT_Encode4(426034),
     /* 425793 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425800 */   GIM_Try, /*On fail goto*//*Label 8315*/ GIMT_Encode4(425847), // Rule ID 6493 //
     /* 425805 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425809 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425813 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425816 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425820 */     // MIs[1] Rn
     /* 425820 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425824 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425829 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425831 */     // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 425834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425845 */     GIR_RootConstrainSelectedInstOperands,
     /* 425846 */     // GIR_Coverage, 6493,
     /* 425846 */     GIR_EraseRootFromParent_Done,
     /* 425847 */   // Label 8315: @425847
     /* 425847 */   GIM_Try, /*On fail goto*//*Label 8316*/ GIMT_Encode4(425894), // Rule ID 6504 //
     /* 425852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425860 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425863 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425867 */     // MIs[1] Rn
     /* 425867 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425876 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425878 */     // (AArch64dup:{ *:[v4f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 425881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425892 */     GIR_RootConstrainSelectedInstOperands,
     /* 425893 */     // GIR_Coverage, 6504,
     /* 425893 */     GIR_EraseRootFromParent_Done,
     /* 425894 */   // Label 8316: @425894
     /* 425894 */   GIM_Try, /*On fail goto*//*Label 8317*/ GIMT_Encode4(425941), // Rule ID 13500 //
     /* 425899 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 425903 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 425907 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 425910 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 425914 */     // MIs[1] Rn
     /* 425914 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 425918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 425923 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 425925 */     // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 425925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 425928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 425930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 425934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 425939 */     GIR_RootConstrainSelectedInstOperands,
     /* 425940 */     // GIR_Coverage, 13500,
     /* 425940 */     GIR_EraseRootFromParent_Done,
     /* 425941 */   // Label 8317: @425941
     /* 425941 */   GIM_Try, /*On fail goto*//*Label 8318*/ GIMT_Encode4(425960), // Rule ID 1921 //
     /* 425946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425949 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 425953 */     // (AArch64dup:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv4i32gpr:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn)
     /* 425953 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32gpr),
     /* 425958 */     GIR_RootConstrainSelectedInstOperands,
     /* 425959 */     // GIR_Coverage, 1921,
     /* 425959 */     GIR_Done,
     /* 425960 */   // Label 8318: @425960
     /* 425960 */   GIM_Try, /*On fail goto*//*Label 8319*/ GIMT_Encode4(426033), // Rule ID 5683 //
     /* 425965 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425969 */     // (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rn)  =>  (DUPv4i32lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 425969 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 425972 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425976 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425981 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425983 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 425986 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425990 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425995 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425998 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 426002 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 426005 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426010 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426015 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 426020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 426023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 426031 */     GIR_RootConstrainSelectedInstOperands,
     /* 426032 */     // GIR_Coverage, 5683,
     /* 426032 */     GIR_EraseRootFromParent_Done,
     /* 426033 */   // Label 8319: @426033
     /* 426033 */   GIM_Reject,
     /* 426034 */ // Label 8314: @426034
     /* 426034 */ GIM_Reject,
     /* 426035 */ // Label 8287: @426035
     /* 426035 */ GIM_Try, /*On fail goto*//*Label 8320*/ GIMT_Encode4(426092), // Rule ID 13495 //
     /* 426040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 426043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426047 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426051 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426055 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426058 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426062 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 426066 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426068 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 426075 */   // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
     /* 426078 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 426085 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426090 */   GIR_RootConstrainSelectedInstOperands,
     /* 426091 */   // GIR_Coverage, 13495,
     /* 426091 */   GIR_EraseRootFromParent_Done,
     /* 426092 */ // Label 8320: @426092
     /* 426092 */ GIM_Try, /*On fail goto*//*Label 8321*/ GIMT_Encode4(426153), // Rule ID 6488 //
     /* 426097 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426100 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426104 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426108 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426112 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426115 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426119 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 426126 */   // MIs[1] Rn
     /* 426126 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426130 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426135 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426137 */   // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>)  =>  (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426137 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
     /* 426140 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426142 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426151 */   GIR_RootConstrainSelectedInstOperands,
     /* 426152 */   // GIR_Coverage, 6488,
     /* 426152 */   GIR_EraseRootFromParent_Done,
     /* 426153 */ // Label 8321: @426153
     /* 426153 */ GIM_Try, /*On fail goto*//*Label 8322*/ GIMT_Encode4(426179), // Rule ID 1916 //
     /* 426158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426161 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426168 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 426172 */   // (AArch64dup:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv8i8gpr:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn)
     /* 426172 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8gpr),
     /* 426177 */   GIR_RootConstrainSelectedInstOperands,
     /* 426178 */   // GIR_Coverage, 1916,
     /* 426178 */   GIR_Done,
     /* 426179 */ // Label 8322: @426179
     /* 426179 */ GIM_Try, /*On fail goto*//*Label 8323*/ GIMT_Encode4(426259), // Rule ID 5687 //
     /* 426184 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 426187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426191 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 426195 */   // (AArch64dup:{ *:[v8i8] } FPR8:{ *:[i8] }:$Rn)  =>  (DUPv8i8lane:{ *:[v8i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rn, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 426195 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 426198 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 426202 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426207 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 426209 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 426212 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 426216 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426221 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 426224 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 426228 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 426231 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426236 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426241 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 426246 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8lane),
     /* 426249 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426251 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426254 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 426257 */   GIR_RootConstrainSelectedInstOperands,
     /* 426258 */   // GIR_Coverage, 5687,
     /* 426258 */   GIR_EraseRootFromParent_Done,
     /* 426259 */ // Label 8323: @426259
     /* 426259 */ GIM_Reject,
     /* 426260 */ // Label 8288: @426260
     /* 426260 */ GIM_Try, /*On fail goto*//*Label 8324*/ GIMT_Encode4(426321), // Rule ID 6491 //
     /* 426265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426268 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426272 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426276 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426280 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426283 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426287 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 426294 */   // MIs[1] Rn
     /* 426294 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426298 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426303 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426305 */   // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>)  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 426308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426310 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426319 */   GIR_RootConstrainSelectedInstOperands,
     /* 426320 */   // GIR_Coverage, 6491,
     /* 426320 */   GIR_EraseRootFromParent_Done,
     /* 426321 */ // Label 8324: @426321
     /* 426321 */ GIM_Try, /*On fail goto*//*Label 8325*/ GIMT_Encode4(426375), // Rule ID 6508 //
     /* 426326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 426329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426333 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426337 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426341 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426344 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426348 */   // MIs[1] Rn
     /* 426348 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426352 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426357 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426359 */   // (AArch64dup:{ *:[v8f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8h:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 426362 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426364 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426373 */   GIR_RootConstrainSelectedInstOperands,
     /* 426374 */   // GIR_Coverage, 6508,
     /* 426374 */   GIR_EraseRootFromParent_Done,
     /* 426375 */ // Label 8325: @426375
     /* 426375 */ GIM_Try, /*On fail goto*//*Label 8326*/ GIMT_Encode4(426429), // Rule ID 13498 //
     /* 426380 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 426383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426387 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426391 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426395 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426398 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426402 */   // MIs[1] Rn
     /* 426402 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426406 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426411 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426413 */   // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 426416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426418 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426427 */   GIR_RootConstrainSelectedInstOperands,
     /* 426428 */   // GIR_Coverage, 13498,
     /* 426428 */   GIR_EraseRootFromParent_Done,
     /* 426429 */ // Label 8326: @426429
     /* 426429 */ GIM_Try, /*On fail goto*//*Label 8327*/ GIMT_Encode4(426455), // Rule ID 1919 //
     /* 426434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426444 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 426448 */   // (AArch64dup:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv8i16gpr:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn)
     /* 426448 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16gpr),
     /* 426453 */   GIR_RootConstrainSelectedInstOperands,
     /* 426454 */   // GIR_Coverage, 1919,
     /* 426454 */   GIR_Done,
     /* 426455 */ // Label 8327: @426455
     /* 426455 */ GIM_Try, /*On fail goto*//*Label 8328*/ GIMT_Encode4(426535), // Rule ID 5686 //
     /* 426460 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 426463 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426467 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 426471 */   // (AArch64dup:{ *:[v8f16] } FPR16:{ *:[f16] }:$Rn)  =>  (DUPv8i16lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 426471 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 426474 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 426478 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426483 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 426485 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 426488 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 426492 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426497 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 426500 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 426504 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 426507 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426512 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426517 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 426522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 426525 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426527 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 426533 */   GIR_RootConstrainSelectedInstOperands,
     /* 426534 */   // GIR_Coverage, 5686,
     /* 426534 */   GIR_EraseRootFromParent_Done,
     /* 426535 */ // Label 8328: @426535
     /* 426535 */ GIM_Reject,
     /* 426536 */ // Label 8289: @426536
     /* 426536 */ GIM_Try, /*On fail goto*//*Label 8329*/ GIMT_Encode4(426597), // Rule ID 6489 //
     /* 426541 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426544 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426548 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426552 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426556 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426559 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426563 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 426570 */   // MIs[1] Rn
     /* 426570 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426574 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426579 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426581 */   // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>)  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 426584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426586 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426595 */   GIR_RootConstrainSelectedInstOperands,
     /* 426596 */   // GIR_Coverage, 6489,
     /* 426596 */   GIR_EraseRootFromParent_Done,
     /* 426597 */ // Label 8329: @426597
     /* 426597 */ GIM_Try, /*On fail goto*//*Label 8330*/ GIMT_Encode4(426651), // Rule ID 13496 //
     /* 426602 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 426605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426609 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426613 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426617 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426620 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426624 */   // MIs[1] Rn
     /* 426624 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426628 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426633 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426635 */   // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 426638 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426640 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426649 */   GIR_RootConstrainSelectedInstOperands,
     /* 426650 */   // GIR_Coverage, 13496,
     /* 426650 */   GIR_EraseRootFromParent_Done,
     /* 426651 */ // Label 8330: @426651
     /* 426651 */ GIM_Try, /*On fail goto*//*Label 8331*/ GIMT_Encode4(426677), // Rule ID 1917 //
     /* 426656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426666 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 426670 */   // (AArch64dup:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv16i8gpr:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn)
     /* 426670 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8gpr),
     /* 426675 */   GIR_RootConstrainSelectedInstOperands,
     /* 426676 */   // GIR_Coverage, 1917,
     /* 426676 */   GIR_Done,
     /* 426677 */ // Label 8331: @426677
     /* 426677 */ GIM_Try, /*On fail goto*//*Label 8332*/ GIMT_Encode4(426757), // Rule ID 5688 //
     /* 426682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 426685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426689 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 426693 */   // (AArch64dup:{ *:[v16i8] } FPR8:{ *:[i8] }:$Rn)  =>  (DUPv16i8lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rn, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 426693 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 426696 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 426700 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426705 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 426707 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 426710 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 426714 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426719 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 426722 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 426726 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 426729 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426734 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426739 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 426744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8lane),
     /* 426747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426749 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426752 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 426755 */   GIR_RootConstrainSelectedInstOperands,
     /* 426756 */   // GIR_Coverage, 5688,
     /* 426756 */   GIR_EraseRootFromParent_Done,
     /* 426757 */ // Label 8332: @426757
     /* 426757 */ GIM_Reject,
     /* 426758 */ // Label 8290: @426758
     /* 426758 */ GIM_Reject,
     /* 426759 */ // Label 126: @426759
     /* 426759 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 8335*/ GIMT_Encode4(427013),
     /* 426770 */ /*GILLT_v4s16*//*Label 8333*/ GIMT_Encode4(426786), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 426782 */ /*GILLT_v8s16*//*Label 8334*/ GIMT_Encode4(426872),
     /* 426786 */ // Label 8333: @426786
     /* 426786 */ GIM_Try, /*On fail goto*//*Label 8336*/ GIMT_Encode4(426871),
     /* 426791 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 426794 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 426797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426801 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426805 */   GIM_Try, /*On fail goto*//*Label 8337*/ GIMT_Encode4(426839), // Rule ID 1926 //
     /* 426810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 426817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 426821 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 426825 */     // MIs[1] Operand 1
     /* 426825 */     // No operand predicates
     /* 426825 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426827 */     // (AArch64duplane16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPv4i16lane:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 426827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 426830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426832 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 426834 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 426837 */     GIR_RootConstrainSelectedInstOperands,
     /* 426838 */     // GIR_Coverage, 1926,
     /* 426838 */     GIR_EraseRootFromParent_Done,
     /* 426839 */   // Label 8337: @426839
     /* 426839 */   GIM_Try, /*On fail goto*//*Label 8338*/ GIMT_Encode4(426870), // Rule ID 5689 //
     /* 426844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 426848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 426852 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 426856 */     // MIs[1] Operand 1
     /* 426856 */     // No operand predicates
     /* 426856 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426858 */     // (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (DUPv4i16lane:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
     /* 426858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 426861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426863 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 426865 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 426868 */     GIR_RootConstrainSelectedInstOperands,
     /* 426869 */     // GIR_Coverage, 5689,
     /* 426869 */     GIR_EraseRootFromParent_Done,
     /* 426870 */   // Label 8338: @426870
     /* 426870 */   GIM_Reject,
     /* 426871 */ // Label 8336: @426871
     /* 426871 */ GIM_Reject,
     /* 426872 */ // Label 8334: @426872
     /* 426872 */ GIM_Try, /*On fail goto*//*Label 8339*/ GIMT_Encode4(427012),
     /* 426877 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 426880 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 426883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426887 */   GIM_Try, /*On fail goto*//*Label 8340*/ GIMT_Encode4(426938), // Rule ID 6499 //
     /* 426892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426896 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 426900 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 426903 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 426907 */     // MIs[1] Rn
     /* 426907 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 426911 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 426916 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 426920 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426922 */     // (AArch64duplane16:{ *:[v8i16] } (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 426922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 426925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 426927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 426936 */     GIR_RootConstrainSelectedInstOperands,
     /* 426937 */     // GIR_Coverage, 6499,
     /* 426937 */     GIR_EraseRootFromParent_Done,
     /* 426938 */   // Label 8340: @426938
     /* 426938 */   GIM_Try, /*On fail goto*//*Label 8341*/ GIMT_Encode4(426976), // Rule ID 1927 //
     /* 426943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426946 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 426954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 426958 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 426962 */     // MIs[1] Operand 1
     /* 426962 */     // No operand predicates
     /* 426962 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426964 */     // (AArch64duplane16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPv8i16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 426964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 426967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426969 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 426971 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 426974 */     GIR_RootConstrainSelectedInstOperands,
     /* 426975 */     // GIR_Coverage, 1927,
     /* 426975 */     GIR_EraseRootFromParent_Done,
     /* 426976 */   // Label 8341: @426976
     /* 426976 */   GIM_Try, /*On fail goto*//*Label 8342*/ GIMT_Encode4(427011), // Rule ID 5690 //
     /* 426981 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426985 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 426989 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 426993 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 426997 */     // MIs[1] Operand 1
     /* 426997 */     // No operand predicates
     /* 426997 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 426999 */     // (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (DUPv8i16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
     /* 426999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 427002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427004 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427006 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 427009 */     GIR_RootConstrainSelectedInstOperands,
     /* 427010 */     // GIR_Coverage, 5690,
     /* 427010 */     GIR_EraseRootFromParent_Done,
     /* 427011 */   // Label 8342: @427011
     /* 427011 */   GIM_Reject,
     /* 427012 */ // Label 8339: @427012
     /* 427012 */ GIM_Reject,
     /* 427013 */ // Label 8335: @427013
     /* 427013 */ GIM_Reject,
     /* 427014 */ // Label 127: @427014
     /* 427014 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(9), /*)*//*default:*//*Label 8345*/ GIMT_Encode4(427268),
     /* 427025 */ /*GILLT_v2s32*//*Label 8343*/ GIMT_Encode4(427041), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 427037 */ /*GILLT_v4s32*//*Label 8344*/ GIMT_Encode4(427127),
     /* 427041 */ // Label 8343: @427041
     /* 427041 */ GIM_Try, /*On fail goto*//*Label 8346*/ GIMT_Encode4(427126),
     /* 427046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 427049 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427056 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427060 */   GIM_Try, /*On fail goto*//*Label 8347*/ GIMT_Encode4(427094), // Rule ID 1924 //
     /* 427065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427076 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 427080 */     // MIs[1] Operand 1
     /* 427080 */     // No operand predicates
     /* 427080 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427082 */     // (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPv2i32lane:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 427082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 427085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427087 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427089 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 427092 */     GIR_RootConstrainSelectedInstOperands,
     /* 427093 */     // GIR_Coverage, 1924,
     /* 427093 */     GIR_EraseRootFromParent_Done,
     /* 427094 */   // Label 8347: @427094
     /* 427094 */   GIM_Try, /*On fail goto*//*Label 8348*/ GIMT_Encode4(427125), // Rule ID 5691 //
     /* 427099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427107 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 427111 */     // MIs[1] Operand 1
     /* 427111 */     // No operand predicates
     /* 427111 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427113 */     // (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (DUPv2i32lane:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
     /* 427113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 427116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427118 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427120 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 427123 */     GIR_RootConstrainSelectedInstOperands,
     /* 427124 */     // GIR_Coverage, 5691,
     /* 427124 */     GIR_EraseRootFromParent_Done,
     /* 427125 */   // Label 8348: @427125
     /* 427125 */   GIM_Reject,
     /* 427126 */ // Label 8346: @427126
     /* 427126 */ GIM_Reject,
     /* 427127 */ // Label 8344: @427127
     /* 427127 */ GIM_Try, /*On fail goto*//*Label 8349*/ GIMT_Encode4(427267),
     /* 427132 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 427135 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427142 */   GIM_Try, /*On fail goto*//*Label 8350*/ GIMT_Encode4(427193), // Rule ID 6501 //
     /* 427147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 427155 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 427158 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 427162 */     // MIs[1] Rn
     /* 427162 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 427166 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 427171 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 427175 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427177 */     // (AArch64duplane32:{ *:[v4i32] } (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 427177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 427180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 427182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 427191 */     GIR_RootConstrainSelectedInstOperands,
     /* 427192 */     // GIR_Coverage, 6501,
     /* 427192 */     GIR_EraseRootFromParent_Done,
     /* 427193 */   // Label 8350: @427193
     /* 427193 */   GIM_Try, /*On fail goto*//*Label 8351*/ GIMT_Encode4(427231), // Rule ID 1925 //
     /* 427198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427201 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427205 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427209 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427213 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 427217 */     // MIs[1] Operand 1
     /* 427217 */     // No operand predicates
     /* 427217 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427219 */     // (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPv4i32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 427219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 427222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427224 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427226 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 427229 */     GIR_RootConstrainSelectedInstOperands,
     /* 427230 */     // GIR_Coverage, 1925,
     /* 427230 */     GIR_EraseRootFromParent_Done,
     /* 427231 */   // Label 8351: @427231
     /* 427231 */   GIM_Try, /*On fail goto*//*Label 8352*/ GIMT_Encode4(427266), // Rule ID 5692 //
     /* 427236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427240 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427244 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427248 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 427252 */     // MIs[1] Operand 1
     /* 427252 */     // No operand predicates
     /* 427252 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427254 */     // (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (DUPv4i32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
     /* 427254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 427257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427259 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427261 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 427264 */     GIR_RootConstrainSelectedInstOperands,
     /* 427265 */     // GIR_Coverage, 5692,
     /* 427265 */     GIR_EraseRootFromParent_Done,
     /* 427266 */   // Label 8352: @427266
     /* 427266 */   GIM_Reject,
     /* 427267 */ // Label 8349: @427267
     /* 427267 */ GIM_Reject,
     /* 427268 */ // Label 8345: @427268
     /* 427268 */ GIM_Reject,
     /* 427269 */ // Label 128: @427269
     /* 427269 */ GIM_Try, /*On fail goto*//*Label 8353*/ GIMT_Encode4(427414),
     /* 427274 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 427277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 427280 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427287 */   GIM_Try, /*On fail goto*//*Label 8354*/ GIMT_Encode4(427338), // Rule ID 6502 //
     /* 427292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 427300 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 427303 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 427307 */     // MIs[1] Rn
     /* 427307 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 427311 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 427316 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 427320 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427322 */     // (AArch64duplane64:{ *:[v2i64] } (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 427322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 427325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 427327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 427336 */     GIR_RootConstrainSelectedInstOperands,
     /* 427337 */     // GIR_Coverage, 6502,
     /* 427337 */     GIR_EraseRootFromParent_Done,
     /* 427338 */   // Label 8354: @427338
     /* 427338 */   GIM_Try, /*On fail goto*//*Label 8355*/ GIMT_Encode4(427413),
     /* 427343 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427347 */     GIM_Try, /*On fail goto*//*Label 8356*/ GIMT_Encode4(427381), // Rule ID 1923 //
     /* 427352 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427355 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427359 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427363 */       GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 427367 */       // MIs[1] Operand 1
     /* 427367 */       // No operand predicates
     /* 427367 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427369 */       // (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (DUPv2i64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 427369 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 427372 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427374 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427376 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 427379 */       GIR_RootConstrainSelectedInstOperands,
     /* 427380 */       // GIR_Coverage, 1923,
     /* 427380 */       GIR_EraseRootFromParent_Done,
     /* 427381 */     // Label 8356: @427381
     /* 427381 */     GIM_Try, /*On fail goto*//*Label 8357*/ GIMT_Encode4(427412), // Rule ID 5693 //
     /* 427386 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427390 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427394 */       GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 427398 */       // MIs[1] Operand 1
     /* 427398 */       // No operand predicates
     /* 427398 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427400 */       // (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (DUPv2i64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)
     /* 427400 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 427403 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427405 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427407 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 427410 */       GIR_RootConstrainSelectedInstOperands,
     /* 427411 */       // GIR_Coverage, 5693,
     /* 427411 */       GIR_EraseRootFromParent_Done,
     /* 427412 */     // Label 8357: @427412
     /* 427412 */     GIM_Reject,
     /* 427413 */   // Label 8355: @427413
     /* 427413 */   GIM_Reject,
     /* 427414 */ // Label 8353: @427414
     /* 427414 */ GIM_Reject,
     /* 427415 */ // Label 129: @427415
     /* 427415 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 8360*/ GIMT_Encode4(427593),
     /* 427426 */ /*GILLT_v8s8*//*Label 8358*/ GIMT_Encode4(427438), GIMT_Encode4(0),
     /* 427434 */ /*GILLT_v16s8*//*Label 8359*/ GIMT_Encode4(427487),
     /* 427438 */ // Label 8358: @427438
     /* 427438 */ GIM_Try, /*On fail goto*//*Label 8361*/ GIMT_Encode4(427486), // Rule ID 1928 //
     /* 427443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427446 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 427449 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427456 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427460 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427464 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427468 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 427472 */   // MIs[1] Operand 1
     /* 427472 */   // No operand predicates
     /* 427472 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427474 */   // (AArch64duplane8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (DUPv8i8lane:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 427474 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8lane),
     /* 427477 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427479 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427481 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 427484 */   GIR_RootConstrainSelectedInstOperands,
     /* 427485 */   // GIR_Coverage, 1928,
     /* 427485 */   GIR_EraseRootFromParent_Done,
     /* 427486 */ // Label 8361: @427486
     /* 427486 */ GIM_Reject,
     /* 427487 */ // Label 8359: @427487
     /* 427487 */ GIM_Try, /*On fail goto*//*Label 8362*/ GIMT_Encode4(427592),
     /* 427492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 427495 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427502 */   GIM_Try, /*On fail goto*//*Label 8363*/ GIMT_Encode4(427553), // Rule ID 6497 //
     /* 427507 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427511 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 427515 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 427518 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 427522 */     // MIs[1] Rn
     /* 427522 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 427526 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 427531 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 427535 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427537 */     // (AArch64duplane8:{ *:[v16i8] } (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 427537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 427540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 427542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 427551 */     GIR_RootConstrainSelectedInstOperands,
     /* 427552 */     // GIR_Coverage, 6497,
     /* 427552 */     GIR_EraseRootFromParent_Done,
     /* 427553 */   // Label 8363: @427553
     /* 427553 */   GIM_Try, /*On fail goto*//*Label 8364*/ GIMT_Encode4(427591), // Rule ID 1929 //
     /* 427558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 427569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427573 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 427577 */     // MIs[1] Operand 1
     /* 427577 */     // No operand predicates
     /* 427577 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427579 */     // (AArch64duplane8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (DUPv16i8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 427579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8lane),
     /* 427582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427584 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427586 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 427589 */     GIR_RootConstrainSelectedInstOperands,
     /* 427590 */     // GIR_Coverage, 1929,
     /* 427590 */     GIR_EraseRootFromParent_Done,
     /* 427591 */   // Label 8364: @427591
     /* 427591 */   GIM_Reject,
     /* 427592 */ // Label 8362: @427592
     /* 427592 */ GIM_Reject,
     /* 427593 */ // Label 8360: @427593
     /* 427593 */ GIM_Reject,
     /* 427594 */ // Label 130: @427594
     /* 427594 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 8374*/ GIMT_Encode4(429243),
     /* 427605 */ /*GILLT_s64*//*Label 8365*/ GIMT_Encode4(427689), GIMT_Encode4(0),
     /* 427613 */ /*GILLT_v2s32*//*Label 8366*/ GIMT_Encode4(428010),
     /* 427617 */ /*GILLT_v2s64*//*Label 8367*/ GIMT_Encode4(428331),
     /* 427621 */ /*GILLT_v4s16*//*Label 8368*/ GIMT_Encode4(428414),
     /* 427625 */ /*GILLT_v4s32*//*Label 8369*/ GIMT_Encode4(428735),
     /* 427629 */ /*GILLT_v8s8*//*Label 8370*/ GIMT_Encode4(428818),
     /* 427633 */ /*GILLT_v8s16*//*Label 8371*/ GIMT_Encode4(429027),
     /* 427637 */ /*GILLT_v16s8*//*Label 8372*/ GIMT_Encode4(429110), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 427685 */ /*GILLT_nxv16s8*//*Label 8373*/ GIMT_Encode4(429196),
     /* 427689 */ // Label 8365: @427689
     /* 427689 */ GIM_Try, /*On fail goto*//*Label 8375*/ GIMT_Encode4(428009),
     /* 427694 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 427697 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427700 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427704 */   GIM_Try, /*On fail goto*//*Label 8376*/ GIMT_Encode4(427819), // Rule ID 5508 //
     /* 427709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 427717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 427721 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427726 */     // MIs[1] Operand 2
     /* 427726 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 427737 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 427741 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 427745 */     // MIs[2] Rn
     /* 427745 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 427750 */     // MIs[2] Operand 2
     /* 427750 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(1),
     /* 427761 */     // MIs[0] imm
     /* 427761 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 427765 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427769 */     // MIs[3] Operand 1
     /* 427769 */     // No operand predicates
     /* 427769 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 427771 */     // (AArch64ext:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 427771 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 427774 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 427778 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427783 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427787 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427791 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 427794 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 427796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 427801 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 427808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427813 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427818 */     // GIR_Coverage, 5508,
     /* 427818 */     GIR_EraseRootFromParent_Done,
     /* 427819 */   // Label 8376: @427819
     /* 427819 */   GIM_Try, /*On fail goto*//*Label 8377*/ GIMT_Encode4(427934), // Rule ID 5513 //
     /* 427824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 427832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 427836 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427841 */     // MIs[1] Operand 2
     /* 427841 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 427852 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 427856 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 427860 */     // MIs[2] Rn
     /* 427860 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 427865 */     // MIs[2] Operand 2
     /* 427865 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(1),
     /* 427876 */     // MIs[0] imm
     /* 427876 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 427880 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427884 */     // MIs[3] Operand 1
     /* 427884 */     // No operand predicates
     /* 427884 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 427886 */     // (AArch64ext:{ *:[v1f64] } (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 427886 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 427889 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 427893 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427898 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427902 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 427906 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 427909 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 427911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 427916 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 427923 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427928 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427933 */     // GIR_Coverage, 5513,
     /* 427933 */     GIR_EraseRootFromParent_Done,
     /* 427934 */   // Label 8377: @427934
     /* 427934 */   GIM_Try, /*On fail goto*//*Label 8378*/ GIMT_Encode4(427971), // Rule ID 5505 //
     /* 427939 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427943 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427947 */     // MIs[0] imm
     /* 427947 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 427951 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427955 */     // MIs[1] Operand 1
     /* 427955 */     // No operand predicates
     /* 427955 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427957 */     // (AArch64ext:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 427957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 427960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427962 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 427964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 427966 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 427969 */     GIR_RootConstrainSelectedInstOperands,
     /* 427970 */     // GIR_Coverage, 5505,
     /* 427970 */     GIR_EraseRootFromParent_Done,
     /* 427971 */   // Label 8378: @427971
     /* 427971 */   GIM_Try, /*On fail goto*//*Label 8379*/ GIMT_Encode4(428008), // Rule ID 5510 //
     /* 427976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427984 */     // MIs[0] imm
     /* 427984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 427988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427992 */     // MIs[1] Operand 1
     /* 427992 */     // No operand predicates
     /* 427992 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 427994 */     // (AArch64ext:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 427994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 427997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428003 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428006 */     GIR_RootConstrainSelectedInstOperands,
     /* 428007 */     // GIR_Coverage, 5510,
     /* 428007 */     GIR_EraseRootFromParent_Done,
     /* 428008 */   // Label 8379: @428008
     /* 428008 */   GIM_Reject,
     /* 428009 */ // Label 8375: @428009
     /* 428009 */ GIM_Reject,
     /* 428010 */ // Label 8366: @428010
     /* 428010 */ GIM_Try, /*On fail goto*//*Label 8380*/ GIMT_Encode4(428330),
     /* 428015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 428018 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 428021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428025 */   GIM_Try, /*On fail goto*//*Label 8381*/ GIMT_Encode4(428140), // Rule ID 5498 //
     /* 428030 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428034 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428038 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428042 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428047 */     // MIs[1] Operand 2
     /* 428047 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 428058 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428066 */     // MIs[2] Rn
     /* 428066 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 428071 */     // MIs[2] Operand 2
     /* 428071 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 428082 */     // MIs[0] imm
     /* 428082 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 428086 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428090 */     // MIs[3] Operand 1
     /* 428090 */     // No operand predicates
     /* 428090 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428092 */     // (AArch64ext:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 428092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 428095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428104 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428108 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428112 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 428115 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 428117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 428122 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 428129 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428134 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428139 */     // GIR_Coverage, 5498,
     /* 428139 */     GIR_EraseRootFromParent_Done,
     /* 428140 */   // Label 8381: @428140
     /* 428140 */   GIM_Try, /*On fail goto*//*Label 8382*/ GIMT_Encode4(428255), // Rule ID 5503 //
     /* 428145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428153 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428157 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428162 */     // MIs[1] Operand 2
     /* 428162 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 428173 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428177 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428181 */     // MIs[2] Rn
     /* 428181 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 428186 */     // MIs[2] Operand 2
     /* 428186 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 428197 */     // MIs[0] imm
     /* 428197 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 428201 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428205 */     // MIs[3] Operand 1
     /* 428205 */     // No operand predicates
     /* 428205 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428207 */     // (AArch64ext:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 428207 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 428210 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428214 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428219 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428223 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428227 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 428230 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 428232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 428237 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 428244 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428249 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428254 */     // GIR_Coverage, 5503,
     /* 428254 */     GIR_EraseRootFromParent_Done,
     /* 428255 */   // Label 8382: @428255
     /* 428255 */   GIM_Try, /*On fail goto*//*Label 8383*/ GIMT_Encode4(428292), // Rule ID 5495 //
     /* 428260 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428268 */     // MIs[0] imm
     /* 428268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428276 */     // MIs[1] Operand 1
     /* 428276 */     // No operand predicates
     /* 428276 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428278 */     // (AArch64ext:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 428281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428283 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428287 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428290 */     GIR_RootConstrainSelectedInstOperands,
     /* 428291 */     // GIR_Coverage, 5495,
     /* 428291 */     GIR_EraseRootFromParent_Done,
     /* 428292 */   // Label 8383: @428292
     /* 428292 */   GIM_Try, /*On fail goto*//*Label 8384*/ GIMT_Encode4(428329), // Rule ID 5500 //
     /* 428297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428301 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428305 */     // MIs[0] imm
     /* 428305 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428309 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428313 */     // MIs[1] Operand 1
     /* 428313 */     // No operand predicates
     /* 428313 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428315 */     // (AArch64ext:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 428318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428324 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428327 */     GIR_RootConstrainSelectedInstOperands,
     /* 428328 */     // GIR_Coverage, 5500,
     /* 428328 */     GIR_EraseRootFromParent_Done,
     /* 428329 */   // Label 8384: @428329
     /* 428329 */   GIM_Reject,
     /* 428330 */ // Label 8380: @428330
     /* 428330 */ GIM_Reject,
     /* 428331 */ // Label 8367: @428331
     /* 428331 */ GIM_Try, /*On fail goto*//*Label 8385*/ GIMT_Encode4(428413),
     /* 428336 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 428339 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 428342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428346 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428350 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428354 */   GIM_Try, /*On fail goto*//*Label 8386*/ GIMT_Encode4(428383), // Rule ID 5506 //
     /* 428359 */     // MIs[0] imm
     /* 428359 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428363 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428367 */     // MIs[1] Operand 1
     /* 428367 */     // No operand predicates
     /* 428367 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428369 */     // (AArch64ext:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428374 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428378 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428381 */     GIR_RootConstrainSelectedInstOperands,
     /* 428382 */     // GIR_Coverage, 5506,
     /* 428382 */     GIR_EraseRootFromParent_Done,
     /* 428383 */   // Label 8386: @428383
     /* 428383 */   GIM_Try, /*On fail goto*//*Label 8387*/ GIMT_Encode4(428412), // Rule ID 5511 //
     /* 428388 */     // MIs[0] imm
     /* 428388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428396 */     // MIs[1] Operand 1
     /* 428396 */     // No operand predicates
     /* 428396 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428398 */     // (AArch64ext:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428403 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428407 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428410 */     GIR_RootConstrainSelectedInstOperands,
     /* 428411 */     // GIR_Coverage, 5511,
     /* 428411 */     GIR_EraseRootFromParent_Done,
     /* 428412 */   // Label 8387: @428412
     /* 428412 */   GIM_Reject,
     /* 428413 */ // Label 8385: @428413
     /* 428413 */ GIM_Reject,
     /* 428414 */ // Label 8368: @428414
     /* 428414 */ GIM_Try, /*On fail goto*//*Label 8388*/ GIMT_Encode4(428734),
     /* 428419 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 428422 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 428425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428429 */   GIM_Try, /*On fail goto*//*Label 8389*/ GIMT_Encode4(428544), // Rule ID 5488 //
     /* 428434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428451 */     // MIs[1] Operand 2
     /* 428451 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 428462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428470 */     // MIs[2] Rn
     /* 428470 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 428475 */     // MIs[2] Operand 2
     /* 428475 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 428486 */     // MIs[0] imm
     /* 428486 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 428490 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428494 */     // MIs[3] Operand 1
     /* 428494 */     // No operand predicates
     /* 428494 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428496 */     // (AArch64ext:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 428496 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 428499 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428503 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428508 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428512 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428516 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 428519 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 428521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 428526 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 428533 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428538 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428543 */     // GIR_Coverage, 5488,
     /* 428543 */     GIR_EraseRootFromParent_Done,
     /* 428544 */   // Label 8389: @428544
     /* 428544 */   GIM_Try, /*On fail goto*//*Label 8390*/ GIMT_Encode4(428659), // Rule ID 5493 //
     /* 428549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428557 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428561 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428566 */     // MIs[1] Operand 2
     /* 428566 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 428577 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428581 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428585 */     // MIs[2] Rn
     /* 428585 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 428590 */     // MIs[2] Operand 2
     /* 428590 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 428601 */     // MIs[0] imm
     /* 428601 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 428605 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428609 */     // MIs[3] Operand 1
     /* 428609 */     // No operand predicates
     /* 428609 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428611 */     // (AArch64ext:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 428611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 428614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428623 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428627 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428631 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 428634 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 428636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 428641 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 428648 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428653 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428658 */     // GIR_Coverage, 5493,
     /* 428658 */     GIR_EraseRootFromParent_Done,
     /* 428659 */   // Label 8390: @428659
     /* 428659 */   GIM_Try, /*On fail goto*//*Label 8391*/ GIMT_Encode4(428696), // Rule ID 5485 //
     /* 428664 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428668 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428672 */     // MIs[0] imm
     /* 428672 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428676 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428680 */     // MIs[1] Operand 1
     /* 428680 */     // No operand predicates
     /* 428680 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428682 */     // (AArch64ext:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 428685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428687 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428691 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428694 */     GIR_RootConstrainSelectedInstOperands,
     /* 428695 */     // GIR_Coverage, 5485,
     /* 428695 */     GIR_EraseRootFromParent_Done,
     /* 428696 */   // Label 8391: @428696
     /* 428696 */   GIM_Try, /*On fail goto*//*Label 8392*/ GIMT_Encode4(428733), // Rule ID 5490 //
     /* 428701 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428709 */     // MIs[0] imm
     /* 428709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428717 */     // MIs[1] Operand 1
     /* 428717 */     // No operand predicates
     /* 428717 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428719 */     // (AArch64ext:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 428722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428724 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428728 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428731 */     GIR_RootConstrainSelectedInstOperands,
     /* 428732 */     // GIR_Coverage, 5490,
     /* 428732 */     GIR_EraseRootFromParent_Done,
     /* 428733 */   // Label 8392: @428733
     /* 428733 */   GIM_Reject,
     /* 428734 */ // Label 8388: @428734
     /* 428734 */ GIM_Reject,
     /* 428735 */ // Label 8369: @428735
     /* 428735 */ GIM_Try, /*On fail goto*//*Label 8393*/ GIMT_Encode4(428817),
     /* 428740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428743 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 428746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428754 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428758 */   GIM_Try, /*On fail goto*//*Label 8394*/ GIMT_Encode4(428787), // Rule ID 5496 //
     /* 428763 */     // MIs[0] imm
     /* 428763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428771 */     // MIs[1] Operand 1
     /* 428771 */     // No operand predicates
     /* 428771 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428773 */     // (AArch64ext:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428778 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428785 */     GIR_RootConstrainSelectedInstOperands,
     /* 428786 */     // GIR_Coverage, 5496,
     /* 428786 */     GIR_EraseRootFromParent_Done,
     /* 428787 */   // Label 8394: @428787
     /* 428787 */   GIM_Try, /*On fail goto*//*Label 8395*/ GIMT_Encode4(428816), // Rule ID 5501 //
     /* 428792 */     // MIs[0] imm
     /* 428792 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428796 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428800 */     // MIs[1] Operand 1
     /* 428800 */     // No operand predicates
     /* 428800 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428802 */     // (AArch64ext:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428807 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428809 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428811 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428814 */     GIR_RootConstrainSelectedInstOperands,
     /* 428815 */     // GIR_Coverage, 5501,
     /* 428815 */     GIR_EraseRootFromParent_Done,
     /* 428816 */   // Label 8395: @428816
     /* 428816 */   GIM_Reject,
     /* 428817 */ // Label 8393: @428817
     /* 428817 */ GIM_Reject,
     /* 428818 */ // Label 8370: @428818
     /* 428818 */ GIM_Try, /*On fail goto*//*Label 8396*/ GIMT_Encode4(429026),
     /* 428823 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 428826 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 428829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428833 */   GIM_Try, /*On fail goto*//*Label 8397*/ GIMT_Encode4(428948), // Rule ID 5483 //
     /* 428838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428846 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 428850 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428855 */     // MIs[1] Operand 2
     /* 428855 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 428866 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428870 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 428874 */     // MIs[2] Rn
     /* 428874 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 428879 */     // MIs[2] Operand 2
     /* 428879 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 428890 */     // MIs[0] imm
     /* 428890 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 428894 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428898 */     // MIs[3] Operand 1
     /* 428898 */     // No operand predicates
     /* 428898 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428900 */     // (AArch64ext:{ *:[v8i8] } (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EXTv16i8:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 428900 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 428903 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 428907 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428912 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428916 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 428920 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 428923 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 428925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 428930 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 428937 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428942 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428947 */     // GIR_Coverage, 5483,
     /* 428947 */     GIR_EraseRootFromParent_Done,
     /* 428948 */   // Label 8397: @428948
     /* 428948 */   GIM_Try, /*On fail goto*//*Label 8398*/ GIMT_Encode4(428988), // Rule ID 1872 //
     /* 428953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428956 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428960 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428964 */     // MIs[0] imm
     /* 428964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 428968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428972 */     // MIs[1] Operand 1
     /* 428972 */     // No operand predicates
     /* 428972 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428974 */     // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 428974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 428977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428979 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 428983 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 428986 */     GIR_RootConstrainSelectedInstOperands,
     /* 428987 */     // GIR_Coverage, 1872,
     /* 428987 */     GIR_EraseRootFromParent_Done,
     /* 428988 */   // Label 8398: @428988
     /* 428988 */   GIM_Try, /*On fail goto*//*Label 8399*/ GIMT_Encode4(429025), // Rule ID 5480 //
     /* 428993 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429001 */     // MIs[0] imm
     /* 429001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429009 */     // MIs[1] Operand 1
     /* 429009 */     // No operand predicates
     /* 429009 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429011 */     // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 429011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 429014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429016 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 429020 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 429023 */     GIR_RootConstrainSelectedInstOperands,
     /* 429024 */     // GIR_Coverage, 5480,
     /* 429024 */     GIR_EraseRootFromParent_Done,
     /* 429025 */   // Label 8399: @429025
     /* 429025 */   GIM_Reject,
     /* 429026 */ // Label 8396: @429026
     /* 429026 */ GIM_Reject,
     /* 429027 */ // Label 8371: @429027
     /* 429027 */ GIM_Try, /*On fail goto*//*Label 8400*/ GIMT_Encode4(429109),
     /* 429032 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 429035 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 429038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429042 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429046 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429050 */   GIM_Try, /*On fail goto*//*Label 8401*/ GIMT_Encode4(429079), // Rule ID 5486 //
     /* 429055 */     // MIs[0] imm
     /* 429055 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429059 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429063 */     // MIs[1] Operand 1
     /* 429063 */     // No operand predicates
     /* 429063 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429065 */     // (AArch64ext:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 429065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 429068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429070 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 429074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 429077 */     GIR_RootConstrainSelectedInstOperands,
     /* 429078 */     // GIR_Coverage, 5486,
     /* 429078 */     GIR_EraseRootFromParent_Done,
     /* 429079 */   // Label 8401: @429079
     /* 429079 */   GIM_Try, /*On fail goto*//*Label 8402*/ GIMT_Encode4(429108), // Rule ID 5491 //
     /* 429084 */     // MIs[0] imm
     /* 429084 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429088 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429092 */     // MIs[1] Operand 1
     /* 429092 */     // No operand predicates
     /* 429092 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429094 */     // (AArch64ext:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 429094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 429097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429099 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429101 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 429103 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 429106 */     GIR_RootConstrainSelectedInstOperands,
     /* 429107 */     // GIR_Coverage, 5491,
     /* 429107 */     GIR_EraseRootFromParent_Done,
     /* 429108 */   // Label 8402: @429108
     /* 429108 */   GIM_Reject,
     /* 429109 */ // Label 8400: @429109
     /* 429109 */ GIM_Reject,
     /* 429110 */ // Label 8372: @429110
     /* 429110 */ GIM_Try, /*On fail goto*//*Label 8403*/ GIMT_Encode4(429195),
     /* 429115 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 429118 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 429121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429125 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429129 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429133 */   GIM_Try, /*On fail goto*//*Label 8404*/ GIMT_Encode4(429165), // Rule ID 1873 //
     /* 429138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429141 */     // MIs[0] imm
     /* 429141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429149 */     // MIs[1] Operand 1
     /* 429149 */     // No operand predicates
     /* 429149 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429151 */     // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 429151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 429154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429156 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 429160 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 429163 */     GIR_RootConstrainSelectedInstOperands,
     /* 429164 */     // GIR_Coverage, 1873,
     /* 429164 */     GIR_EraseRootFromParent_Done,
     /* 429165 */   // Label 8404: @429165
     /* 429165 */   GIM_Try, /*On fail goto*//*Label 8405*/ GIMT_Encode4(429194), // Rule ID 5481 //
     /* 429170 */     // MIs[0] imm
     /* 429170 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429174 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429178 */     // MIs[1] Operand 1
     /* 429178 */     // No operand predicates
     /* 429178 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429180 */     // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 429180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 429183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429185 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 429189 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 429192 */     GIR_RootConstrainSelectedInstOperands,
     /* 429193 */     // GIR_Coverage, 5481,
     /* 429193 */     GIR_EraseRootFromParent_Done,
     /* 429194 */   // Label 8405: @429194
     /* 429194 */   GIM_Reject,
     /* 429195 */ // Label 8403: @429195
     /* 429195 */ GIM_Reject,
     /* 429196 */ // Label 8373: @429196
     /* 429196 */ GIM_Try, /*On fail goto*//*Label 8406*/ GIMT_Encode4(429242), // Rule ID 2733 //
     /* 429201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 429204 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 429207 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 429210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 429214 */   // MIs[0] Op3
     /* 429214 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 429218 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429222 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
     /* 429226 */   // MIs[1] Operand 1
     /* 429226 */   // No operand predicates
     /* 429226 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429228 */   // (AArch64ext:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3)  =>  (EXT_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3)
     /* 429228 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXT_ZZI),
     /* 429231 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 429233 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 429235 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /* 429237 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // Op3
     /* 429240 */   GIR_RootConstrainSelectedInstOperands,
     /* 429241 */   // GIR_Coverage, 2733,
     /* 429241 */   GIR_EraseRootFromParent_Done,
     /* 429242 */ // Label 8406: @429242
     /* 429242 */ GIM_Reject,
     /* 429243 */ // Label 8374: @429243
     /* 429243 */ GIM_Reject,
     /* 429244 */ // Label 131: @429244
     /* 429244 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 8414*/ GIMT_Encode4(429802),
     /* 429255 */ /*GILLT_s32*//*Label 8407*/ GIMT_Encode4(429291),
     /* 429259 */ /*GILLT_s64*//*Label 8408*/ GIMT_Encode4(429329), GIMT_Encode4(0),
     /* 429267 */ /*GILLT_v2s32*//*Label 8409*/ GIMT_Encode4(429427),
     /* 429271 */ /*GILLT_v2s64*//*Label 8410*/ GIMT_Encode4(429502),
     /* 429275 */ /*GILLT_v4s16*//*Label 8411*/ GIMT_Encode4(429577),
     /* 429279 */ /*GILLT_v4s32*//*Label 8412*/ GIMT_Encode4(429652), GIMT_Encode4(0),
     /* 429287 */ /*GILLT_v8s16*//*Label 8413*/ GIMT_Encode4(429727),
     /* 429291 */ // Label 8407: @429291
     /* 429291 */ GIM_Try, /*On fail goto*//*Label 8415*/ GIMT_Encode4(429328), // Rule ID 1626 //
     /* 429296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429299 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 429302 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 429305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429309 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429313 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429317 */   // (AArch64fcmeq:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMEQ32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 429317 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ32),
     /* 429322 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429326 */   GIR_RootConstrainSelectedInstOperands,
     /* 429327 */   // GIR_Coverage, 1626,
     /* 429327 */   GIR_Done,
     /* 429328 */ // Label 8415: @429328
     /* 429328 */ GIM_Reject,
     /* 429329 */ // Label 8408: @429329
     /* 429329 */ GIM_Try, /*On fail goto*//*Label 8416*/ GIMT_Encode4(429426),
     /* 429334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 429337 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 429340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429344 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429348 */   GIM_Try, /*On fail goto*//*Label 8417*/ GIMT_Encode4(429379), // Rule ID 2513 //
     /* 429353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429360 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429366 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429368 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429370 */     // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 429370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv1i64rz),
     /* 429373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429375 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429377 */     GIR_RootConstrainSelectedInstOperands,
     /* 429378 */     // GIR_Coverage, 2513,
     /* 429378 */     GIR_EraseRootFromParent_Done,
     /* 429379 */   // Label 8417: @429379
     /* 429379 */   GIM_Try, /*On fail goto*//*Label 8418*/ GIMT_Encode4(429402), // Rule ID 1625 //
     /* 429384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429387 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429391 */     // (AArch64fcmeq:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMEQ64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 429391 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
     /* 429396 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429400 */     GIR_RootConstrainSelectedInstOperands,
     /* 429401 */     // GIR_Coverage, 1625,
     /* 429401 */     GIR_Done,
     /* 429402 */   // Label 8418: @429402
     /* 429402 */   GIM_Try, /*On fail goto*//*Label 8419*/ GIMT_Encode4(429425), // Rule ID 5260 //
     /* 429407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429414 */     // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMEQ64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 429414 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
     /* 429419 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429423 */     GIR_RootConstrainSelectedInstOperands,
     /* 429424 */     // GIR_Coverage, 5260,
     /* 429424 */     GIR_Done,
     /* 429425 */   // Label 8419: @429425
     /* 429425 */   GIM_Reject,
     /* 429426 */ // Label 8416: @429426
     /* 429426 */ GIM_Reject,
     /* 429427 */ // Label 8409: @429427
     /* 429427 */ GIM_Try, /*On fail goto*//*Label 8420*/ GIMT_Encode4(429501),
     /* 429432 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 429435 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 429438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429442 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429446 */   GIM_Try, /*On fail goto*//*Label 8421*/ GIMT_Encode4(429477), // Rule ID 777 //
     /* 429451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429458 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429464 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429466 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429468 */     // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 429468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i32rz),
     /* 429471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429473 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429475 */     GIR_RootConstrainSelectedInstOperands,
     /* 429476 */     // GIR_Coverage, 777,
     /* 429476 */     GIR_EraseRootFromParent_Done,
     /* 429477 */   // Label 8421: @429477
     /* 429477 */   GIM_Try, /*On fail goto*//*Label 8422*/ GIMT_Encode4(429500), // Rule ID 1214 //
     /* 429482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429485 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429489 */     // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMEQv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 429489 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f32),
     /* 429494 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429498 */     GIR_RootConstrainSelectedInstOperands,
     /* 429499 */     // GIR_Coverage, 1214,
     /* 429499 */     GIR_Done,
     /* 429500 */   // Label 8422: @429500
     /* 429500 */   GIM_Reject,
     /* 429501 */ // Label 8420: @429501
     /* 429501 */ GIM_Reject,
     /* 429502 */ // Label 8410: @429502
     /* 429502 */ GIM_Try, /*On fail goto*//*Label 8423*/ GIMT_Encode4(429576),
     /* 429507 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 429513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429521 */   GIM_Try, /*On fail goto*//*Label 8424*/ GIMT_Encode4(429552), // Rule ID 779 //
     /* 429526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429533 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429539 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429541 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429543 */     // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 429543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i64rz),
     /* 429546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429548 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429550 */     GIR_RootConstrainSelectedInstOperands,
     /* 429551 */     // GIR_Coverage, 779,
     /* 429551 */     GIR_EraseRootFromParent_Done,
     /* 429552 */   // Label 8424: @429552
     /* 429552 */   GIM_Try, /*On fail goto*//*Label 8425*/ GIMT_Encode4(429575), // Rule ID 1216 //
     /* 429557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429564 */     // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMEQv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 429564 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f64),
     /* 429569 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429573 */     GIR_RootConstrainSelectedInstOperands,
     /* 429574 */     // GIR_Coverage, 1216,
     /* 429574 */     GIR_Done,
     /* 429575 */   // Label 8425: @429575
     /* 429575 */   GIM_Reject,
     /* 429576 */ // Label 8423: @429576
     /* 429576 */ GIM_Reject,
     /* 429577 */ // Label 8411: @429577
     /* 429577 */ GIM_Try, /*On fail goto*//*Label 8426*/ GIMT_Encode4(429651),
     /* 429582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 429585 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 429588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429592 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429596 */   GIM_Try, /*On fail goto*//*Label 8427*/ GIMT_Encode4(429627), // Rule ID 775 //
     /* 429601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 429604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429608 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429614 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429616 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429618 */     // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 429618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i16rz),
     /* 429621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429623 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429625 */     GIR_RootConstrainSelectedInstOperands,
     /* 429626 */     // GIR_Coverage, 775,
     /* 429626 */     GIR_EraseRootFromParent_Done,
     /* 429627 */   // Label 8427: @429627
     /* 429627 */   GIM_Try, /*On fail goto*//*Label 8428*/ GIMT_Encode4(429650), // Rule ID 1212 //
     /* 429632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 429635 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429639 */     // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMEQv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 429639 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f16),
     /* 429644 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429648 */     GIR_RootConstrainSelectedInstOperands,
     /* 429649 */     // GIR_Coverage, 1212,
     /* 429649 */     GIR_Done,
     /* 429650 */   // Label 8428: @429650
     /* 429650 */   GIM_Reject,
     /* 429651 */ // Label 8426: @429651
     /* 429651 */ GIM_Reject,
     /* 429652 */ // Label 8412: @429652
     /* 429652 */ GIM_Try, /*On fail goto*//*Label 8429*/ GIMT_Encode4(429726),
     /* 429657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429660 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 429663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429667 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429671 */   GIM_Try, /*On fail goto*//*Label 8430*/ GIMT_Encode4(429702), // Rule ID 778 //
     /* 429676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429679 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429683 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429689 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429691 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429693 */     // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 429693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i32rz),
     /* 429696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429698 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429700 */     GIR_RootConstrainSelectedInstOperands,
     /* 429701 */     // GIR_Coverage, 778,
     /* 429701 */     GIR_EraseRootFromParent_Done,
     /* 429702 */   // Label 8430: @429702
     /* 429702 */   GIM_Try, /*On fail goto*//*Label 8431*/ GIMT_Encode4(429725), // Rule ID 1215 //
     /* 429707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429710 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429714 */     // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMEQv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 429714 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
     /* 429719 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429723 */     GIR_RootConstrainSelectedInstOperands,
     /* 429724 */     // GIR_Coverage, 1215,
     /* 429724 */     GIR_Done,
     /* 429725 */   // Label 8431: @429725
     /* 429725 */   GIM_Reject,
     /* 429726 */ // Label 8429: @429726
     /* 429726 */ GIM_Reject,
     /* 429727 */ // Label 8413: @429727
     /* 429727 */ GIM_Try, /*On fail goto*//*Label 8432*/ GIMT_Encode4(429801),
     /* 429732 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 429735 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 429738 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429742 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429746 */   GIM_Try, /*On fail goto*//*Label 8433*/ GIMT_Encode4(429777), // Rule ID 776 //
     /* 429751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 429754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429758 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429764 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429766 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429768 */     // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 429768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8i16rz),
     /* 429771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429773 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429775 */     GIR_RootConstrainSelectedInstOperands,
     /* 429776 */     // GIR_Coverage, 776,
     /* 429776 */     GIR_EraseRootFromParent_Done,
     /* 429777 */   // Label 8433: @429777
     /* 429777 */   GIM_Try, /*On fail goto*//*Label 8434*/ GIMT_Encode4(429800), // Rule ID 1213 //
     /* 429782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 429785 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429789 */     // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMEQv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 429789 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8f16),
     /* 429794 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429798 */     GIR_RootConstrainSelectedInstOperands,
     /* 429799 */     // GIR_Coverage, 1213,
     /* 429799 */     GIR_Done,
     /* 429800 */   // Label 8434: @429800
     /* 429800 */   GIM_Reject,
     /* 429801 */ // Label 8432: @429801
     /* 429801 */ GIM_Reject,
     /* 429802 */ // Label 8414: @429802
     /* 429802 */ GIM_Reject,
     /* 429803 */ // Label 132: @429803
     /* 429803 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 8442*/ GIMT_Encode4(430894),
     /* 429814 */ /*GILLT_s32*//*Label 8435*/ GIMT_Encode4(429850),
     /* 429818 */ /*GILLT_s64*//*Label 8436*/ GIMT_Encode4(429888), GIMT_Encode4(0),
     /* 429826 */ /*GILLT_v2s32*//*Label 8437*/ GIMT_Encode4(430029),
     /* 429830 */ /*GILLT_v2s64*//*Label 8438*/ GIMT_Encode4(430202),
     /* 429834 */ /*GILLT_v4s16*//*Label 8439*/ GIMT_Encode4(430375),
     /* 429838 */ /*GILLT_v4s32*//*Label 8440*/ GIMT_Encode4(430548), GIMT_Encode4(0),
     /* 429846 */ /*GILLT_v8s16*//*Label 8441*/ GIMT_Encode4(430721),
     /* 429850 */ // Label 8435: @429850
     /* 429850 */ GIM_Try, /*On fail goto*//*Label 8443*/ GIMT_Encode4(429887), // Rule ID 1628 //
     /* 429855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429858 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 429861 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 429864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429868 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429872 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429876 */   // (AArch64fcmge:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 429876 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE32),
     /* 429881 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429885 */   GIR_RootConstrainSelectedInstOperands,
     /* 429886 */   // GIR_Coverage, 1628,
     /* 429886 */   GIR_Done,
     /* 429887 */ // Label 8443: @429887
     /* 429887 */ GIM_Reject,
     /* 429888 */ // Label 8436: @429888
     /* 429888 */ GIM_Try, /*On fail goto*//*Label 8444*/ GIMT_Encode4(430028),
     /* 429893 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 429896 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 429899 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429903 */   GIM_Try, /*On fail goto*//*Label 8445*/ GIMT_Encode4(429938), // Rule ID 5294 //
     /* 429908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429915 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429921 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429927 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429929 */     // (AArch64fcmge:{ *:[v1i64] } immAllZerosV:{ *:[v1f64] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 429929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv1i64rz),
     /* 429932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429936 */     GIR_RootConstrainSelectedInstOperands,
     /* 429937 */     // GIR_Coverage, 5294,
     /* 429937 */     GIR_EraseRootFromParent_Done,
     /* 429938 */   // Label 8445: @429938
     /* 429938 */   GIM_Try, /*On fail goto*//*Label 8446*/ GIMT_Encode4(429973), // Rule ID 5292 //
     /* 429943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429946 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429954 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 429960 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 429962 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429964 */     // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 429964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv1i64rz),
     /* 429967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429969 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429971 */     GIR_RootConstrainSelectedInstOperands,
     /* 429972 */     // GIR_Coverage, 5292,
     /* 429972 */     GIR_EraseRootFromParent_Done,
     /* 429973 */   // Label 8446: @429973
     /* 429973 */   GIM_Try, /*On fail goto*//*Label 8447*/ GIMT_Encode4(430000), // Rule ID 1627 //
     /* 429978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429981 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429989 */     // (AArch64fcmge:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 429989 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
     /* 429994 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429998 */     GIR_RootConstrainSelectedInstOperands,
     /* 429999 */     // GIR_Coverage, 1627,
     /* 429999 */     GIR_Done,
     /* 430000 */   // Label 8447: @430000
     /* 430000 */   GIM_Try, /*On fail goto*//*Label 8448*/ GIMT_Encode4(430027), // Rule ID 5261 //
     /* 430005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430008 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430012 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430016 */     // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 430016 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
     /* 430021 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430025 */     GIR_RootConstrainSelectedInstOperands,
     /* 430026 */     // GIR_Coverage, 5261,
     /* 430026 */     GIR_Done,
     /* 430027 */   // Label 8448: @430027
     /* 430027 */   GIM_Reject,
     /* 430028 */ // Label 8444: @430028
     /* 430028 */ GIM_Reject,
     /* 430029 */ // Label 8437: @430029
     /* 430029 */ GIM_Try, /*On fail goto*//*Label 8449*/ GIMT_Encode4(430201),
     /* 430034 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 430037 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 430040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430044 */   GIM_Try, /*On fail goto*//*Label 8450*/ GIMT_Encode4(430103), // Rule ID 1176 //
     /* 430049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 430064 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 430073 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430077 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 430081 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430086 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430088 */     // (AArch64fcmge:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 430088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
     /* 430091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430093 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 430097 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430101 */     GIR_RootConstrainSelectedInstOperands,
     /* 430102 */     // GIR_Coverage, 1176,
     /* 430102 */     GIR_EraseRootFromParent_Done,
     /* 430103 */   // Label 8450: @430103
     /* 430103 */   GIM_Try, /*On fail goto*//*Label 8451*/ GIMT_Encode4(430138), // Rule ID 792 //
     /* 430108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430115 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430121 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430123 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430127 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430129 */     // (AArch64fcmge:{ *:[v2i32] } immAllZerosV:{ *:[v2f32] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 430129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i32rz),
     /* 430132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430136 */     GIR_RootConstrainSelectedInstOperands,
     /* 430137 */     // GIR_Coverage, 792,
     /* 430137 */     GIR_EraseRootFromParent_Done,
     /* 430138 */   // Label 8451: @430138
     /* 430138 */   GIM_Try, /*On fail goto*//*Label 8452*/ GIMT_Encode4(430173), // Rule ID 782 //
     /* 430143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430146 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430154 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430160 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430162 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430164 */     // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 430164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i32rz),
     /* 430167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430169 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430171 */     GIR_RootConstrainSelectedInstOperands,
     /* 430172 */     // GIR_Coverage, 782,
     /* 430172 */     GIR_EraseRootFromParent_Done,
     /* 430173 */   // Label 8452: @430173
     /* 430173 */   GIM_Try, /*On fail goto*//*Label 8453*/ GIMT_Encode4(430200), // Rule ID 1219 //
     /* 430178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430189 */     // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 430189 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f32),
     /* 430194 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430198 */     GIR_RootConstrainSelectedInstOperands,
     /* 430199 */     // GIR_Coverage, 1219,
     /* 430199 */     GIR_Done,
     /* 430200 */   // Label 8453: @430200
     /* 430200 */   GIM_Reject,
     /* 430201 */ // Label 8449: @430201
     /* 430201 */ GIM_Reject,
     /* 430202 */ // Label 8438: @430202
     /* 430202 */ GIM_Try, /*On fail goto*//*Label 8454*/ GIMT_Encode4(430374),
     /* 430207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430210 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 430213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430217 */   GIM_Try, /*On fail goto*//*Label 8455*/ GIMT_Encode4(430276), // Rule ID 1180 //
     /* 430222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430225 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430229 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430233 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 430246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430250 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430254 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430259 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430261 */     // (AArch64fcmge:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 430261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
     /* 430264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 430270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430274 */     GIR_RootConstrainSelectedInstOperands,
     /* 430275 */     // GIR_Coverage, 1180,
     /* 430275 */     GIR_EraseRootFromParent_Done,
     /* 430276 */   // Label 8455: @430276
     /* 430276 */   GIM_Try, /*On fail goto*//*Label 8456*/ GIMT_Encode4(430311), // Rule ID 794 //
     /* 430281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430288 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430294 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430300 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430302 */     // (AArch64fcmge:{ *:[v2i64] } immAllZerosV:{ *:[v2f64] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 430302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i64rz),
     /* 430305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430309 */     GIR_RootConstrainSelectedInstOperands,
     /* 430310 */     // GIR_Coverage, 794,
     /* 430310 */     GIR_EraseRootFromParent_Done,
     /* 430311 */   // Label 8456: @430311
     /* 430311 */   GIM_Try, /*On fail goto*//*Label 8457*/ GIMT_Encode4(430346), // Rule ID 784 //
     /* 430316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430319 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430323 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430327 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430333 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430335 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430337 */     // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 430337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i64rz),
     /* 430340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430342 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430344 */     GIR_RootConstrainSelectedInstOperands,
     /* 430345 */     // GIR_Coverage, 784,
     /* 430345 */     GIR_EraseRootFromParent_Done,
     /* 430346 */   // Label 8457: @430346
     /* 430346 */   GIM_Try, /*On fail goto*//*Label 8458*/ GIMT_Encode4(430373), // Rule ID 1221 //
     /* 430351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430354 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430362 */     // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 430362 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f64),
     /* 430367 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430371 */     GIR_RootConstrainSelectedInstOperands,
     /* 430372 */     // GIR_Coverage, 1221,
     /* 430372 */     GIR_Done,
     /* 430373 */   // Label 8458: @430373
     /* 430373 */   GIM_Reject,
     /* 430374 */ // Label 8454: @430374
     /* 430374 */ GIM_Reject,
     /* 430375 */ // Label 8439: @430375
     /* 430375 */ GIM_Try, /*On fail goto*//*Label 8459*/ GIMT_Encode4(430547),
     /* 430380 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 430383 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 430386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430390 */   GIM_Try, /*On fail goto*//*Label 8460*/ GIMT_Encode4(430449), // Rule ID 1172 //
     /* 430395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 430410 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430415 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 430419 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430423 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 430427 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430432 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430434 */     // (AArch64fcmge:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 430434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
     /* 430437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 430443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430447 */     GIR_RootConstrainSelectedInstOperands,
     /* 430448 */     // GIR_Coverage, 1172,
     /* 430448 */     GIR_EraseRootFromParent_Done,
     /* 430449 */   // Label 8460: @430449
     /* 430449 */   GIM_Try, /*On fail goto*//*Label 8461*/ GIMT_Encode4(430484), // Rule ID 790 //
     /* 430454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430457 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430461 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430467 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430469 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430473 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430475 */     // (AArch64fcmge:{ *:[v4i16] } immAllZerosV:{ *:[v4f16] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 430475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i16rz),
     /* 430478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430482 */     GIR_RootConstrainSelectedInstOperands,
     /* 430483 */     // GIR_Coverage, 790,
     /* 430483 */     GIR_EraseRootFromParent_Done,
     /* 430484 */   // Label 8461: @430484
     /* 430484 */   GIM_Try, /*On fail goto*//*Label 8462*/ GIMT_Encode4(430519), // Rule ID 780 //
     /* 430489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430492 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430500 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430506 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430508 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430510 */     // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 430510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i16rz),
     /* 430513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430515 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430517 */     GIR_RootConstrainSelectedInstOperands,
     /* 430518 */     // GIR_Coverage, 780,
     /* 430518 */     GIR_EraseRootFromParent_Done,
     /* 430519 */   // Label 8462: @430519
     /* 430519 */   GIM_Try, /*On fail goto*//*Label 8463*/ GIMT_Encode4(430546), // Rule ID 1217 //
     /* 430524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430527 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430535 */     // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 430535 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f16),
     /* 430540 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430544 */     GIR_RootConstrainSelectedInstOperands,
     /* 430545 */     // GIR_Coverage, 1217,
     /* 430545 */     GIR_Done,
     /* 430546 */   // Label 8463: @430546
     /* 430546 */   GIM_Reject,
     /* 430547 */ // Label 8459: @430547
     /* 430547 */ GIM_Reject,
     /* 430548 */ // Label 8440: @430548
     /* 430548 */ GIM_Try, /*On fail goto*//*Label 8464*/ GIMT_Encode4(430720),
     /* 430553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430556 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 430559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430563 */   GIM_Try, /*On fail goto*//*Label 8465*/ GIMT_Encode4(430622), // Rule ID 1178 //
     /* 430568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430583 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 430592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430596 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430600 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430605 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430607 */     // (AArch64fcmge:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 430607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
     /* 430610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 430616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430620 */     GIR_RootConstrainSelectedInstOperands,
     /* 430621 */     // GIR_Coverage, 1178,
     /* 430621 */     GIR_EraseRootFromParent_Done,
     /* 430622 */   // Label 8465: @430622
     /* 430622 */   GIM_Try, /*On fail goto*//*Label 8466*/ GIMT_Encode4(430657), // Rule ID 793 //
     /* 430627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430634 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430640 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430642 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430646 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430648 */     // (AArch64fcmge:{ *:[v4i32] } immAllZerosV:{ *:[v4f32] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 430648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i32rz),
     /* 430651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430655 */     GIR_RootConstrainSelectedInstOperands,
     /* 430656 */     // GIR_Coverage, 793,
     /* 430656 */     GIR_EraseRootFromParent_Done,
     /* 430657 */   // Label 8466: @430657
     /* 430657 */   GIM_Try, /*On fail goto*//*Label 8467*/ GIMT_Encode4(430692), // Rule ID 783 //
     /* 430662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430665 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430673 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430679 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430681 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430683 */     // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 430683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i32rz),
     /* 430686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430688 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430690 */     GIR_RootConstrainSelectedInstOperands,
     /* 430691 */     // GIR_Coverage, 783,
     /* 430691 */     GIR_EraseRootFromParent_Done,
     /* 430692 */   // Label 8467: @430692
     /* 430692 */   GIM_Try, /*On fail goto*//*Label 8468*/ GIMT_Encode4(430719), // Rule ID 1220 //
     /* 430697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430700 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430704 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430708 */     // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 430708 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f32),
     /* 430713 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430717 */     GIR_RootConstrainSelectedInstOperands,
     /* 430718 */     // GIR_Coverage, 1220,
     /* 430718 */     GIR_Done,
     /* 430719 */   // Label 8468: @430719
     /* 430719 */   GIM_Reject,
     /* 430720 */ // Label 8464: @430720
     /* 430720 */ GIM_Reject,
     /* 430721 */ // Label 8441: @430721
     /* 430721 */ GIM_Try, /*On fail goto*//*Label 8469*/ GIMT_Encode4(430893),
     /* 430726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430729 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 430732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430736 */   GIM_Try, /*On fail goto*//*Label 8470*/ GIMT_Encode4(430795), // Rule ID 1174 //
     /* 430741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430756 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 430765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 430769 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430773 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430778 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430780 */     // (AArch64fcmge:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 430780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
     /* 430783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430785 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 430789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430793 */     GIR_RootConstrainSelectedInstOperands,
     /* 430794 */     // GIR_Coverage, 1174,
     /* 430794 */     GIR_EraseRootFromParent_Done,
     /* 430795 */   // Label 8470: @430795
     /* 430795 */   GIM_Try, /*On fail goto*//*Label 8471*/ GIMT_Encode4(430830), // Rule ID 791 //
     /* 430800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430803 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430807 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430813 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430819 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430821 */     // (AArch64fcmge:{ *:[v8i16] } immAllZerosV:{ *:[v8f16] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 430821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv8i16rz),
     /* 430824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430828 */     GIR_RootConstrainSelectedInstOperands,
     /* 430829 */     // GIR_Coverage, 791,
     /* 430829 */     GIR_EraseRootFromParent_Done,
     /* 430830 */   // Label 8471: @430830
     /* 430830 */   GIM_Try, /*On fail goto*//*Label 8472*/ GIMT_Encode4(430865), // Rule ID 781 //
     /* 430835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430846 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 430852 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 430854 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430856 */     // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 430856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8i16rz),
     /* 430859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430861 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430863 */     GIR_RootConstrainSelectedInstOperands,
     /* 430864 */     // GIR_Coverage, 781,
     /* 430864 */     GIR_EraseRootFromParent_Done,
     /* 430865 */   // Label 8472: @430865
     /* 430865 */   GIM_Try, /*On fail goto*//*Label 8473*/ GIMT_Encode4(430892), // Rule ID 1218 //
     /* 430870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430873 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430881 */     // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 430881 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8f16),
     /* 430886 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430890 */     GIR_RootConstrainSelectedInstOperands,
     /* 430891 */     // GIR_Coverage, 1218,
     /* 430891 */     GIR_Done,
     /* 430892 */   // Label 8473: @430892
     /* 430892 */   GIM_Reject,
     /* 430893 */ // Label 8469: @430893
     /* 430893 */ GIM_Reject,
     /* 430894 */ // Label 8442: @430894
     /* 430894 */ GIM_Reject,
     /* 430895 */ // Label 133: @430895
     /* 430895 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 8481*/ GIMT_Encode4(431986),
     /* 430906 */ /*GILLT_s32*//*Label 8474*/ GIMT_Encode4(430942),
     /* 430910 */ /*GILLT_s64*//*Label 8475*/ GIMT_Encode4(430980), GIMT_Encode4(0),
     /* 430918 */ /*GILLT_v2s32*//*Label 8476*/ GIMT_Encode4(431121),
     /* 430922 */ /*GILLT_v2s64*//*Label 8477*/ GIMT_Encode4(431294),
     /* 430926 */ /*GILLT_v4s16*//*Label 8478*/ GIMT_Encode4(431467),
     /* 430930 */ /*GILLT_v4s32*//*Label 8479*/ GIMT_Encode4(431640), GIMT_Encode4(0),
     /* 430938 */ /*GILLT_v8s16*//*Label 8480*/ GIMT_Encode4(431813),
     /* 430942 */ // Label 8474: @430942
     /* 430942 */ GIM_Try, /*On fail goto*//*Label 8482*/ GIMT_Encode4(430979), // Rule ID 1630 //
     /* 430947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430950 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 430953 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 430956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430960 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430964 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430968 */   // (AArch64fcmgt:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 430968 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT32),
     /* 430973 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430977 */   GIR_RootConstrainSelectedInstOperands,
     /* 430978 */   // GIR_Coverage, 1630,
     /* 430978 */   GIR_Done,
     /* 430979 */ // Label 8482: @430979
     /* 430979 */ GIM_Reject,
     /* 430980 */ // Label 8475: @430980
     /* 430980 */ GIM_Try, /*On fail goto*//*Label 8483*/ GIMT_Encode4(431120),
     /* 430985 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 430988 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 430991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430995 */   GIM_Try, /*On fail goto*//*Label 8484*/ GIMT_Encode4(431030), // Rule ID 5295 //
     /* 431000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431003 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431007 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431013 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431019 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431021 */     // (AArch64fcmgt:{ *:[v1i64] } immAllZerosV:{ *:[v1f64] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 431021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv1i64rz),
     /* 431024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431028 */     GIR_RootConstrainSelectedInstOperands,
     /* 431029 */     // GIR_Coverage, 5295,
     /* 431029 */     GIR_EraseRootFromParent_Done,
     /* 431030 */   // Label 8484: @431030
     /* 431030 */   GIM_Try, /*On fail goto*//*Label 8485*/ GIMT_Encode4(431065), // Rule ID 5293 //
     /* 431035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431038 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431046 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431052 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431054 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431056 */     // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 431056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv1i64rz),
     /* 431059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431061 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431063 */     GIR_RootConstrainSelectedInstOperands,
     /* 431064 */     // GIR_Coverage, 5293,
     /* 431064 */     GIR_EraseRootFromParent_Done,
     /* 431065 */   // Label 8485: @431065
     /* 431065 */   GIM_Try, /*On fail goto*//*Label 8486*/ GIMT_Encode4(431092), // Rule ID 1629 //
     /* 431070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431073 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431077 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431081 */     // (AArch64fcmgt:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 431081 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
     /* 431086 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431090 */     GIR_RootConstrainSelectedInstOperands,
     /* 431091 */     // GIR_Coverage, 1629,
     /* 431091 */     GIR_Done,
     /* 431092 */   // Label 8486: @431092
     /* 431092 */   GIM_Try, /*On fail goto*//*Label 8487*/ GIMT_Encode4(431119), // Rule ID 5262 //
     /* 431097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431100 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431108 */     // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 431108 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
     /* 431113 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431117 */     GIR_RootConstrainSelectedInstOperands,
     /* 431118 */     // GIR_Coverage, 5262,
     /* 431118 */     GIR_Done,
     /* 431119 */   // Label 8487: @431119
     /* 431119 */   GIM_Reject,
     /* 431120 */ // Label 8483: @431120
     /* 431120 */ GIM_Reject,
     /* 431121 */ // Label 8476: @431121
     /* 431121 */ GIM_Try, /*On fail goto*//*Label 8488*/ GIMT_Encode4(431293),
     /* 431126 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 431129 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 431132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431136 */   GIM_Try, /*On fail goto*//*Label 8489*/ GIMT_Encode4(431195), // Rule ID 1186 //
     /* 431141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 431156 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431161 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 431165 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431169 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 431173 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431178 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431180 */     // (AArch64fcmgt:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 431180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
     /* 431183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 431189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 431193 */     GIR_RootConstrainSelectedInstOperands,
     /* 431194 */     // GIR_Coverage, 1186,
     /* 431194 */     GIR_EraseRootFromParent_Done,
     /* 431195 */   // Label 8489: @431195
     /* 431195 */   GIM_Try, /*On fail goto*//*Label 8490*/ GIMT_Encode4(431230), // Rule ID 797 //
     /* 431200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431207 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431213 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431215 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431219 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431221 */     // (AArch64fcmgt:{ *:[v2i32] } immAllZerosV:{ *:[v2f32] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 431221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i32rz),
     /* 431224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431228 */     GIR_RootConstrainSelectedInstOperands,
     /* 431229 */     // GIR_Coverage, 797,
     /* 431229 */     GIR_EraseRootFromParent_Done,
     /* 431230 */   // Label 8490: @431230
     /* 431230 */   GIM_Try, /*On fail goto*//*Label 8491*/ GIMT_Encode4(431265), // Rule ID 787 //
     /* 431235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431238 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431242 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431246 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431252 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431254 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431256 */     // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 431256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i32rz),
     /* 431259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431261 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431263 */     GIR_RootConstrainSelectedInstOperands,
     /* 431264 */     // GIR_Coverage, 787,
     /* 431264 */     GIR_EraseRootFromParent_Done,
     /* 431265 */   // Label 8491: @431265
     /* 431265 */   GIM_Try, /*On fail goto*//*Label 8492*/ GIMT_Encode4(431292), // Rule ID 1224 //
     /* 431270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431273 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431277 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431281 */     // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 431281 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f32),
     /* 431286 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431290 */     GIR_RootConstrainSelectedInstOperands,
     /* 431291 */     // GIR_Coverage, 1224,
     /* 431291 */     GIR_Done,
     /* 431292 */   // Label 8492: @431292
     /* 431292 */   GIM_Reject,
     /* 431293 */ // Label 8488: @431293
     /* 431293 */ GIM_Reject,
     /* 431294 */ // Label 8477: @431294
     /* 431294 */ GIM_Try, /*On fail goto*//*Label 8493*/ GIMT_Encode4(431466),
     /* 431299 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 431302 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 431305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431309 */   GIM_Try, /*On fail goto*//*Label 8494*/ GIMT_Encode4(431368), // Rule ID 1190 //
     /* 431314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431317 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431325 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 431329 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 431338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431342 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 431346 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431353 */     // (AArch64fcmgt:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 431353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
     /* 431356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 431362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 431366 */     GIR_RootConstrainSelectedInstOperands,
     /* 431367 */     // GIR_Coverage, 1190,
     /* 431367 */     GIR_EraseRootFromParent_Done,
     /* 431368 */   // Label 8494: @431368
     /* 431368 */   GIM_Try, /*On fail goto*//*Label 8495*/ GIMT_Encode4(431403), // Rule ID 799 //
     /* 431373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431380 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431386 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431392 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431394 */     // (AArch64fcmgt:{ *:[v2i64] } immAllZerosV:{ *:[v2f64] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 431394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i64rz),
     /* 431397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431401 */     GIR_RootConstrainSelectedInstOperands,
     /* 431402 */     // GIR_Coverage, 799,
     /* 431402 */     GIR_EraseRootFromParent_Done,
     /* 431403 */   // Label 8495: @431403
     /* 431403 */   GIM_Try, /*On fail goto*//*Label 8496*/ GIMT_Encode4(431438), // Rule ID 789 //
     /* 431408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431411 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431415 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431419 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431425 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431427 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431429 */     // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 431429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i64rz),
     /* 431432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431434 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431436 */     GIR_RootConstrainSelectedInstOperands,
     /* 431437 */     // GIR_Coverage, 789,
     /* 431437 */     GIR_EraseRootFromParent_Done,
     /* 431438 */   // Label 8496: @431438
     /* 431438 */   GIM_Try, /*On fail goto*//*Label 8497*/ GIMT_Encode4(431465), // Rule ID 1226 //
     /* 431443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431454 */     // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 431454 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f64),
     /* 431459 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431463 */     GIR_RootConstrainSelectedInstOperands,
     /* 431464 */     // GIR_Coverage, 1226,
     /* 431464 */     GIR_Done,
     /* 431465 */   // Label 8497: @431465
     /* 431465 */   GIM_Reject,
     /* 431466 */ // Label 8493: @431466
     /* 431466 */ GIM_Reject,
     /* 431467 */ // Label 8478: @431467
     /* 431467 */ GIM_Try, /*On fail goto*//*Label 8498*/ GIMT_Encode4(431639),
     /* 431472 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 431475 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 431478 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431482 */   GIM_Try, /*On fail goto*//*Label 8499*/ GIMT_Encode4(431541), // Rule ID 1182 //
     /* 431487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 431502 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 431511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 431519 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431524 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431526 */     // (AArch64fcmgt:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 431526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
     /* 431529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 431535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 431539 */     GIR_RootConstrainSelectedInstOperands,
     /* 431540 */     // GIR_Coverage, 1182,
     /* 431540 */     GIR_EraseRootFromParent_Done,
     /* 431541 */   // Label 8499: @431541
     /* 431541 */   GIM_Try, /*On fail goto*//*Label 8500*/ GIMT_Encode4(431576), // Rule ID 795 //
     /* 431546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431553 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431559 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431561 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431565 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431567 */     // (AArch64fcmgt:{ *:[v4i16] } immAllZerosV:{ *:[v4f16] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 431567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i16rz),
     /* 431570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431574 */     GIR_RootConstrainSelectedInstOperands,
     /* 431575 */     // GIR_Coverage, 795,
     /* 431575 */     GIR_EraseRootFromParent_Done,
     /* 431576 */   // Label 8500: @431576
     /* 431576 */   GIM_Try, /*On fail goto*//*Label 8501*/ GIMT_Encode4(431611), // Rule ID 785 //
     /* 431581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431584 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431592 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431598 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431600 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431602 */     // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 431602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i16rz),
     /* 431605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431607 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431609 */     GIR_RootConstrainSelectedInstOperands,
     /* 431610 */     // GIR_Coverage, 785,
     /* 431610 */     GIR_EraseRootFromParent_Done,
     /* 431611 */   // Label 8501: @431611
     /* 431611 */   GIM_Try, /*On fail goto*//*Label 8502*/ GIMT_Encode4(431638), // Rule ID 1222 //
     /* 431616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431623 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431627 */     // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 431627 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f16),
     /* 431632 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431636 */     GIR_RootConstrainSelectedInstOperands,
     /* 431637 */     // GIR_Coverage, 1222,
     /* 431637 */     GIR_Done,
     /* 431638 */   // Label 8502: @431638
     /* 431638 */   GIM_Reject,
     /* 431639 */ // Label 8498: @431639
     /* 431639 */ GIM_Reject,
     /* 431640 */ // Label 8479: @431640
     /* 431640 */ GIM_Try, /*On fail goto*//*Label 8503*/ GIMT_Encode4(431812),
     /* 431645 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 431648 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 431651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431655 */   GIM_Try, /*On fail goto*//*Label 8504*/ GIMT_Encode4(431714), // Rule ID 1188 //
     /* 431660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 431675 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 431684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 431692 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431697 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431699 */     // (AArch64fcmgt:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 431699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
     /* 431702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 431708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 431712 */     GIR_RootConstrainSelectedInstOperands,
     /* 431713 */     // GIR_Coverage, 1188,
     /* 431713 */     GIR_EraseRootFromParent_Done,
     /* 431714 */   // Label 8504: @431714
     /* 431714 */   GIM_Try, /*On fail goto*//*Label 8505*/ GIMT_Encode4(431749), // Rule ID 798 //
     /* 431719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431726 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431732 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431740 */     // (AArch64fcmgt:{ *:[v4i32] } immAllZerosV:{ *:[v4f32] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 431740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i32rz),
     /* 431743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431747 */     GIR_RootConstrainSelectedInstOperands,
     /* 431748 */     // GIR_Coverage, 798,
     /* 431748 */     GIR_EraseRootFromParent_Done,
     /* 431749 */   // Label 8505: @431749
     /* 431749 */   GIM_Try, /*On fail goto*//*Label 8506*/ GIMT_Encode4(431784), // Rule ID 788 //
     /* 431754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431757 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431765 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431771 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431773 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431775 */     // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 431775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i32rz),
     /* 431778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431780 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431782 */     GIR_RootConstrainSelectedInstOperands,
     /* 431783 */     // GIR_Coverage, 788,
     /* 431783 */     GIR_EraseRootFromParent_Done,
     /* 431784 */   // Label 8506: @431784
     /* 431784 */   GIM_Try, /*On fail goto*//*Label 8507*/ GIMT_Encode4(431811), // Rule ID 1225 //
     /* 431789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431792 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431796 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431800 */     // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 431800 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f32),
     /* 431805 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431809 */     GIR_RootConstrainSelectedInstOperands,
     /* 431810 */     // GIR_Coverage, 1225,
     /* 431810 */     GIR_Done,
     /* 431811 */   // Label 8507: @431811
     /* 431811 */   GIM_Reject,
     /* 431812 */ // Label 8503: @431812
     /* 431812 */ GIM_Reject,
     /* 431813 */ // Label 8480: @431813
     /* 431813 */ GIM_Try, /*On fail goto*//*Label 8508*/ GIMT_Encode4(431985),
     /* 431818 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431821 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 431824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431828 */   GIM_Try, /*On fail goto*//*Label 8509*/ GIMT_Encode4(431887), // Rule ID 1184 //
     /* 431833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431848 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431853 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 431857 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 431861 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431865 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431872 */     // (AArch64fcmgt:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 431872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
     /* 431875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 431881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 431885 */     GIR_RootConstrainSelectedInstOperands,
     /* 431886 */     // GIR_Coverage, 1184,
     /* 431886 */     GIR_EraseRootFromParent_Done,
     /* 431887 */   // Label 8509: @431887
     /* 431887 */   GIM_Try, /*On fail goto*//*Label 8510*/ GIMT_Encode4(431922), // Rule ID 796 //
     /* 431892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431895 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431899 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431905 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431907 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431911 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431913 */     // (AArch64fcmgt:{ *:[v8i16] } immAllZerosV:{ *:[v8f16] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 431913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv8i16rz),
     /* 431916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431920 */     GIR_RootConstrainSelectedInstOperands,
     /* 431921 */     // GIR_Coverage, 796,
     /* 431921 */     GIR_EraseRootFromParent_Done,
     /* 431922 */   // Label 8510: @431922
     /* 431922 */   GIM_Try, /*On fail goto*//*Label 8511*/ GIMT_Encode4(431957), // Rule ID 786 //
     /* 431927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431930 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431938 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 431944 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 431946 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431948 */     // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 431948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8i16rz),
     /* 431951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431953 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431955 */     GIR_RootConstrainSelectedInstOperands,
     /* 431956 */     // GIR_Coverage, 786,
     /* 431956 */     GIR_EraseRootFromParent_Done,
     /* 431957 */   // Label 8511: @431957
     /* 431957 */   GIM_Try, /*On fail goto*//*Label 8512*/ GIMT_Encode4(431984), // Rule ID 1223 //
     /* 431962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431965 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431969 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431973 */     // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 431973 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8f16),
     /* 431978 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431982 */     GIR_RootConstrainSelectedInstOperands,
     /* 431983 */     // GIR_Coverage, 1223,
     /* 431983 */     GIR_Done,
     /* 431984 */   // Label 8512: @431984
     /* 431984 */   GIM_Reject,
     /* 431985 */ // Label 8508: @431985
     /* 431985 */ GIM_Reject,
     /* 431986 */ // Label 8481: @431986
     /* 431986 */ GIM_Reject,
     /* 431987 */ // Label 134: @431987
     /* 431987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 8517*/ GIMT_Encode4(432140),
     /* 431998 */ /*GILLT_s32*//*Label 8513*/ GIMT_Encode4(432038),
     /* 432002 */ /*GILLT_s64*//*Label 8514*/ GIMT_Encode4(432062), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 432026 */ /*GILLT_v8s8*//*Label 8515*/ GIMT_Encode4(432086), GIMT_Encode4(0),
     /* 432034 */ /*GILLT_v16s8*//*Label 8516*/ GIMT_Encode4(432113),
     /* 432038 */ // Label 8513: @432038
     /* 432038 */ GIM_Try, /*On fail goto*//*Label 8518*/ GIMT_Encode4(432061), // Rule ID 4048 //
     /* 432043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 432046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 432050 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 432054 */   // (AArch64rev16:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 432054 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 432059 */   GIR_RootConstrainSelectedInstOperands,
     /* 432060 */   // GIR_Coverage, 4048,
     /* 432060 */   GIR_Done,
     /* 432061 */ // Label 8518: @432061
     /* 432061 */ GIM_Reject,
     /* 432062 */ // Label 8514: @432062
     /* 432062 */ GIM_Try, /*On fail goto*//*Label 8519*/ GIMT_Encode4(432085), // Rule ID 4049 //
     /* 432067 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 432070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 432074 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 432078 */   // (AArch64rev16:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 432078 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /* 432083 */   GIR_RootConstrainSelectedInstOperands,
     /* 432084 */   // GIR_Coverage, 4049,
     /* 432084 */   GIR_Done,
     /* 432085 */ // Label 8519: @432085
     /* 432085 */ GIM_Reject,
     /* 432086 */ // Label 8515: @432086
     /* 432086 */ GIM_Try, /*On fail goto*//*Label 8520*/ GIMT_Encode4(432112), // Rule ID 980 //
     /* 432091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432094 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 432097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432101 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432105 */   // (AArch64rev16:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV16v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 432105 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 432110 */   GIR_RootConstrainSelectedInstOperands,
     /* 432111 */   // GIR_Coverage, 980,
     /* 432111 */   GIR_Done,
     /* 432112 */ // Label 8520: @432112
     /* 432112 */ GIM_Reject,
     /* 432113 */ // Label 8516: @432113
     /* 432113 */ GIM_Try, /*On fail goto*//*Label 8521*/ GIMT_Encode4(432139), // Rule ID 981 //
     /* 432118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432121 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 432124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432128 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432132 */   // (AArch64rev16:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV16v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 432132 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 432137 */   GIR_RootConstrainSelectedInstOperands,
     /* 432138 */   // GIR_Coverage, 981,
     /* 432138 */   GIR_Done,
     /* 432139 */ // Label 8521: @432139
     /* 432139 */ GIM_Reject,
     /* 432140 */ // Label 8517: @432140
     /* 432140 */ GIM_Reject,
     /* 432141 */ // Label 135: @432141
     /* 432141 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 8526*/ GIMT_Encode4(432316),
     /* 432152 */ /*GILLT_v4s16*//*Label 8522*/ GIMT_Encode4(432172), GIMT_Encode4(0),
     /* 432160 */ /*GILLT_v8s8*//*Label 8523*/ GIMT_Encode4(432217),
     /* 432164 */ /*GILLT_v8s16*//*Label 8524*/ GIMT_Encode4(432244),
     /* 432168 */ /*GILLT_v16s8*//*Label 8525*/ GIMT_Encode4(432289),
     /* 432172 */ // Label 8522: @432172
     /* 432172 */ GIM_Try, /*On fail goto*//*Label 8527*/ GIMT_Encode4(432216),
     /* 432177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 432180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432184 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432188 */   GIM_Try, /*On fail goto*//*Label 8528*/ GIMT_Encode4(432203), // Rule ID 984 //
     /* 432193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432196 */     // (AArch64rev32:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV32v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 432196 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 432201 */     GIR_RootConstrainSelectedInstOperands,
     /* 432202 */     // GIR_Coverage, 984,
     /* 432202 */     GIR_Done,
     /* 432203 */   // Label 8528: @432203
     /* 432203 */   GIM_Try, /*On fail goto*//*Label 8529*/ GIMT_Encode4(432215), // Rule ID 5031 //
     /* 432208 */     // (AArch64rev32:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (REV32v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 432208 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 432213 */     GIR_RootConstrainSelectedInstOperands,
     /* 432214 */     // GIR_Coverage, 5031,
     /* 432214 */     GIR_Done,
     /* 432215 */   // Label 8529: @432215
     /* 432215 */   GIM_Reject,
     /* 432216 */ // Label 8527: @432216
     /* 432216 */ GIM_Reject,
     /* 432217 */ // Label 8523: @432217
     /* 432217 */ GIM_Try, /*On fail goto*//*Label 8530*/ GIMT_Encode4(432243), // Rule ID 982 //
     /* 432222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432225 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 432228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432232 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432236 */   // (AArch64rev32:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV32v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 432236 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 432241 */   GIR_RootConstrainSelectedInstOperands,
     /* 432242 */   // GIR_Coverage, 982,
     /* 432242 */   GIR_Done,
     /* 432243 */ // Label 8530: @432243
     /* 432243 */ GIM_Reject,
     /* 432244 */ // Label 8524: @432244
     /* 432244 */ GIM_Try, /*On fail goto*//*Label 8531*/ GIMT_Encode4(432288),
     /* 432249 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432252 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432256 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432260 */   GIM_Try, /*On fail goto*//*Label 8532*/ GIMT_Encode4(432275), // Rule ID 985 //
     /* 432265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432268 */     // (AArch64rev32:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV32v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 432268 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 432273 */     GIR_RootConstrainSelectedInstOperands,
     /* 432274 */     // GIR_Coverage, 985,
     /* 432274 */     GIR_Done,
     /* 432275 */   // Label 8532: @432275
     /* 432275 */   GIM_Try, /*On fail goto*//*Label 8533*/ GIMT_Encode4(432287), // Rule ID 5033 //
     /* 432280 */     // (AArch64rev32:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (REV32v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 432280 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 432285 */     GIR_RootConstrainSelectedInstOperands,
     /* 432286 */     // GIR_Coverage, 5033,
     /* 432286 */     GIR_Done,
     /* 432287 */   // Label 8533: @432287
     /* 432287 */   GIM_Reject,
     /* 432288 */ // Label 8531: @432288
     /* 432288 */ GIM_Reject,
     /* 432289 */ // Label 8525: @432289
     /* 432289 */ GIM_Try, /*On fail goto*//*Label 8534*/ GIMT_Encode4(432315), // Rule ID 983 //
     /* 432294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 432300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432308 */   // (AArch64rev32:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV32v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 432308 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 432313 */   GIR_RootConstrainSelectedInstOperands,
     /* 432314 */   // GIR_Coverage, 983,
     /* 432314 */   GIR_Done,
     /* 432315 */ // Label 8534: @432315
     /* 432315 */ GIM_Reject,
     /* 432316 */ // Label 8526: @432316
     /* 432316 */ GIM_Reject,
     /* 432317 */ // Label 136: @432317
     /* 432317 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 8541*/ GIMT_Encode4(432590),
     /* 432328 */ /*GILLT_v2s32*//*Label 8535*/ GIMT_Encode4(432356), GIMT_Encode4(0),
     /* 432336 */ /*GILLT_v4s16*//*Label 8536*/ GIMT_Encode4(432401),
     /* 432340 */ /*GILLT_v4s32*//*Label 8537*/ GIMT_Encode4(432446),
     /* 432344 */ /*GILLT_v8s8*//*Label 8538*/ GIMT_Encode4(432491),
     /* 432348 */ /*GILLT_v8s16*//*Label 8539*/ GIMT_Encode4(432518),
     /* 432352 */ /*GILLT_v16s8*//*Label 8540*/ GIMT_Encode4(432563),
     /* 432356 */ // Label 8535: @432356
     /* 432356 */ GIM_Try, /*On fail goto*//*Label 8542*/ GIMT_Encode4(432400),
     /* 432361 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 432364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432368 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432372 */   GIM_Try, /*On fail goto*//*Label 8543*/ GIMT_Encode4(432387), // Rule ID 990 //
     /* 432377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432380 */     // (AArch64rev64:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (REV64v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 432380 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 432385 */     GIR_RootConstrainSelectedInstOperands,
     /* 432386 */     // GIR_Coverage, 990,
     /* 432386 */     GIR_Done,
     /* 432387 */   // Label 8543: @432387
     /* 432387 */   GIM_Try, /*On fail goto*//*Label 8544*/ GIMT_Encode4(432399), // Rule ID 5035 //
     /* 432392 */     // (AArch64rev64:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (REV64v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 432392 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 432397 */     GIR_RootConstrainSelectedInstOperands,
     /* 432398 */     // GIR_Coverage, 5035,
     /* 432398 */     GIR_Done,
     /* 432399 */   // Label 8544: @432399
     /* 432399 */   GIM_Reject,
     /* 432400 */ // Label 8542: @432400
     /* 432400 */ GIM_Reject,
     /* 432401 */ // Label 8536: @432401
     /* 432401 */ GIM_Try, /*On fail goto*//*Label 8545*/ GIMT_Encode4(432445),
     /* 432406 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 432409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432413 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432417 */   GIM_Try, /*On fail goto*//*Label 8546*/ GIMT_Encode4(432432), // Rule ID 988 //
     /* 432422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432425 */     // (AArch64rev64:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV64v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 432425 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 432430 */     GIR_RootConstrainSelectedInstOperands,
     /* 432431 */     // GIR_Coverage, 988,
     /* 432431 */     GIR_Done,
     /* 432432 */   // Label 8546: @432432
     /* 432432 */   GIM_Try, /*On fail goto*//*Label 8547*/ GIMT_Encode4(432444), // Rule ID 5032 //
     /* 432437 */     // (AArch64rev64:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (REV64v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 432437 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 432442 */     GIR_RootConstrainSelectedInstOperands,
     /* 432443 */     // GIR_Coverage, 5032,
     /* 432443 */     GIR_Done,
     /* 432444 */   // Label 8547: @432444
     /* 432444 */   GIM_Reject,
     /* 432445 */ // Label 8545: @432445
     /* 432445 */ GIM_Reject,
     /* 432446 */ // Label 8537: @432446
     /* 432446 */ GIM_Try, /*On fail goto*//*Label 8548*/ GIMT_Encode4(432490),
     /* 432451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 432454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432458 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432462 */   GIM_Try, /*On fail goto*//*Label 8549*/ GIMT_Encode4(432477), // Rule ID 991 //
     /* 432467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432470 */     // (AArch64rev64:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (REV64v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 432470 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 432475 */     GIR_RootConstrainSelectedInstOperands,
     /* 432476 */     // GIR_Coverage, 991,
     /* 432476 */     GIR_Done,
     /* 432477 */   // Label 8549: @432477
     /* 432477 */   GIM_Try, /*On fail goto*//*Label 8550*/ GIMT_Encode4(432489), // Rule ID 5036 //
     /* 432482 */     // (AArch64rev64:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (REV64v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 432482 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 432487 */     GIR_RootConstrainSelectedInstOperands,
     /* 432488 */     // GIR_Coverage, 5036,
     /* 432488 */     GIR_Done,
     /* 432489 */   // Label 8550: @432489
     /* 432489 */   GIM_Reject,
     /* 432490 */ // Label 8548: @432490
     /* 432490 */ GIM_Reject,
     /* 432491 */ // Label 8538: @432491
     /* 432491 */ GIM_Try, /*On fail goto*//*Label 8551*/ GIMT_Encode4(432517), // Rule ID 986 //
     /* 432496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 432502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432506 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432510 */   // (AArch64rev64:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV64v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 432510 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 432515 */   GIR_RootConstrainSelectedInstOperands,
     /* 432516 */   // GIR_Coverage, 986,
     /* 432516 */   GIR_Done,
     /* 432517 */ // Label 8551: @432517
     /* 432517 */ GIM_Reject,
     /* 432518 */ // Label 8539: @432518
     /* 432518 */ GIM_Try, /*On fail goto*//*Label 8552*/ GIMT_Encode4(432562),
     /* 432523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432534 */   GIM_Try, /*On fail goto*//*Label 8553*/ GIMT_Encode4(432549), // Rule ID 989 //
     /* 432539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432542 */     // (AArch64rev64:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV64v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 432542 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 432547 */     GIR_RootConstrainSelectedInstOperands,
     /* 432548 */     // GIR_Coverage, 989,
     /* 432548 */     GIR_Done,
     /* 432549 */   // Label 8553: @432549
     /* 432549 */   GIM_Try, /*On fail goto*//*Label 8554*/ GIMT_Encode4(432561), // Rule ID 5034 //
     /* 432554 */     // (AArch64rev64:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (REV64v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 432554 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 432559 */     GIR_RootConstrainSelectedInstOperands,
     /* 432560 */     // GIR_Coverage, 5034,
     /* 432560 */     GIR_Done,
     /* 432561 */   // Label 8554: @432561
     /* 432561 */   GIM_Reject,
     /* 432562 */ // Label 8552: @432562
     /* 432562 */ GIM_Reject,
     /* 432563 */ // Label 8540: @432563
     /* 432563 */ GIM_Try, /*On fail goto*//*Label 8555*/ GIMT_Encode4(432589), // Rule ID 987 //
     /* 432568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432571 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 432574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432578 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432582 */   // (AArch64rev64:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV64v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 432582 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 432587 */   GIR_RootConstrainSelectedInstOperands,
     /* 432588 */   // GIR_Coverage, 987,
     /* 432588 */   GIR_Done,
     /* 432589 */ // Label 8555: @432589
     /* 432589 */ GIM_Reject,
     /* 432590 */ // Label 8541: @432590
     /* 432590 */ GIM_Reject,
     /* 432591 */ // Label 137: @432591
     /* 432591 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 8562*/ GIMT_Encode4(432796),
     /* 432602 */ /*GILLT_s64*//*Label 8556*/ GIMT_Encode4(432634), GIMT_Encode4(0),
     /* 432610 */ /*GILLT_v2s32*//*Label 8557*/ GIMT_Encode4(432661),
     /* 432614 */ /*GILLT_v2s64*//*Label 8558*/ GIMT_Encode4(432688),
     /* 432618 */ /*GILLT_v4s16*//*Label 8559*/ GIMT_Encode4(432715),
     /* 432622 */ /*GILLT_v4s32*//*Label 8560*/ GIMT_Encode4(432742), GIMT_Encode4(0),
     /* 432630 */ /*GILLT_v8s16*//*Label 8561*/ GIMT_Encode4(432769),
     /* 432634 */ // Label 8556: @432634
     /* 432634 */ GIM_Try, /*On fail goto*//*Label 8563*/ GIMT_Encode4(432660), // Rule ID 1012 //
     /* 432639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 432645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432649 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432653 */   // (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)  =>  (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 432653 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 432658 */   GIR_RootConstrainSelectedInstOperands,
     /* 432659 */   // GIR_Coverage, 1012,
     /* 432659 */   GIR_Done,
     /* 432660 */ // Label 8563: @432660
     /* 432660 */ GIM_Reject,
     /* 432661 */ // Label 8557: @432661
     /* 432661 */ GIM_Try, /*On fail goto*//*Label 8564*/ GIMT_Encode4(432687), // Rule ID 1008 //
     /* 432666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432669 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 432672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432676 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432680 */   // (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 432680 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
     /* 432685 */   GIR_RootConstrainSelectedInstOperands,
     /* 432686 */   // GIR_Coverage, 1008,
     /* 432686 */   GIR_Done,
     /* 432687 */ // Label 8564: @432687
     /* 432687 */ GIM_Reject,
     /* 432688 */ // Label 8558: @432688
     /* 432688 */ GIM_Try, /*On fail goto*//*Label 8565*/ GIMT_Encode4(432714), // Rule ID 1014 //
     /* 432693 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432696 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 432699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432703 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432707 */   // (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 432707 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
     /* 432712 */   GIR_RootConstrainSelectedInstOperands,
     /* 432713 */   // GIR_Coverage, 1014,
     /* 432713 */   GIR_Done,
     /* 432714 */ // Label 8565: @432714
     /* 432714 */ GIM_Reject,
     /* 432715 */ // Label 8559: @432715
     /* 432715 */ GIM_Try, /*On fail goto*//*Label 8566*/ GIMT_Encode4(432741), // Rule ID 1004 //
     /* 432720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432723 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 432726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432730 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432734 */   // (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)  =>  (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 432734 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
     /* 432739 */   GIR_RootConstrainSelectedInstOperands,
     /* 432740 */   // GIR_Coverage, 1004,
     /* 432740 */   GIR_Done,
     /* 432741 */ // Label 8566: @432741
     /* 432741 */ GIM_Reject,
     /* 432742 */ // Label 8560: @432742
     /* 432742 */ GIM_Try, /*On fail goto*//*Label 8567*/ GIMT_Encode4(432768), // Rule ID 1010 //
     /* 432747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432757 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432761 */   // (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 432761 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
     /* 432766 */   GIR_RootConstrainSelectedInstOperands,
     /* 432767 */   // GIR_Coverage, 1010,
     /* 432767 */   GIR_Done,
     /* 432768 */ // Label 8567: @432768
     /* 432768 */ GIM_Reject,
     /* 432769 */ // Label 8561: @432769
     /* 432769 */ GIM_Try, /*On fail goto*//*Label 8568*/ GIMT_Encode4(432795), // Rule ID 1006 //
     /* 432774 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 432777 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 432780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432784 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432788 */   // (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)  =>  (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 432788 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
     /* 432793 */   GIR_RootConstrainSelectedInstOperands,
     /* 432794 */   // GIR_Coverage, 1006,
     /* 432794 */   GIR_Done,
     /* 432795 */ // Label 8568: @432795
     /* 432795 */ GIM_Reject,
     /* 432796 */ // Label 8562: @432796
     /* 432796 */ GIM_Reject,
     /* 432797 */ // Label 138: @432797
     /* 432797 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 8571*/ GIMT_Encode4(433195),
     /* 432808 */ /*GILLT_v2s64*//*Label 8569*/ GIMT_Encode4(432820), GIMT_Encode4(0),
     /* 432816 */ /*GILLT_v4s32*//*Label 8570*/ GIMT_Encode4(432958),
     /* 432820 */ // Label 8569: @432820
     /* 432820 */ GIM_Try, /*On fail goto*//*Label 8572*/ GIMT_Encode4(432879), // Rule ID 5944 //
     /* 432825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 432828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432832 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432836 */   // (AArch64saddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 432836 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 432839 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 432843 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432848 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 432852 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 432854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 432857 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432859 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 432862 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432865 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 432868 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432873 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432878 */   // GIR_Coverage, 5944,
     /* 432878 */   GIR_EraseRootFromParent_Done,
     /* 432879 */ // Label 8572: @432879
     /* 432879 */ GIM_Try, /*On fail goto*//*Label 8573*/ GIMT_Encode4(432957), // Rule ID 6066 //
     /* 432884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 432887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432891 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432895 */   // (AArch64saddlv:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (SADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 432895 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 432898 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 432902 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432907 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 432911 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 432913 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 432916 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 432920 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432925 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 432927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 432930 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432932 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432935 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 432938 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 432941 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432946 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432951 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432956 */   // GIR_Coverage, 6066,
     /* 432956 */   GIR_EraseRootFromParent_Done,
     /* 432957 */ // Label 8573: @432957
     /* 432957 */ GIM_Reject,
     /* 432958 */ // Label 8570: @432958
     /* 432958 */ GIM_Try, /*On fail goto*//*Label 8574*/ GIMT_Encode4(433017), // Rule ID 5940 //
     /* 432963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 432966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432970 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432974 */   // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
     /* 432974 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432977 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 432981 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432986 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 432990 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 432992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 432995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432997 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 433000 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 433006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433011 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433016 */   // GIR_Coverage, 5940,
     /* 433016 */   GIR_EraseRootFromParent_Done,
     /* 433017 */ // Label 8574: @433017
     /* 433017 */ GIM_Try, /*On fail goto*//*Label 8575*/ GIMT_Encode4(433076), // Rule ID 5941 //
     /* 433022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 433025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433029 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433033 */   // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
     /* 433033 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 433036 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 433040 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433045 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 433049 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 433051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 433054 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 433059 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433062 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 433065 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433070 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 433075 */   // GIR_Coverage, 5941,
     /* 433075 */   GIR_EraseRootFromParent_Done,
     /* 433076 */ // Label 8575: @433076
     /* 433076 */ GIM_Try, /*On fail goto*//*Label 8576*/ GIMT_Encode4(433135), // Rule ID 5942 //
     /* 433081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 433084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433088 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433092 */   // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
     /* 433092 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433095 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 433099 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433104 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 433108 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 433110 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 433113 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433115 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 433118 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 433124 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433129 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433134 */   // GIR_Coverage, 5942,
     /* 433134 */   GIR_EraseRootFromParent_Done,
     /* 433135 */ // Label 8576: @433135
     /* 433135 */ GIM_Try, /*On fail goto*//*Label 8577*/ GIMT_Encode4(433194), // Rule ID 5943 //
     /* 433140 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433147 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433151 */   // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
     /* 433151 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 433154 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 433158 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433163 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 433167 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 433169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 433172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 433177 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 433183 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433188 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 433193 */   // GIR_Coverage, 5943,
     /* 433193 */   GIR_EraseRootFromParent_Done,
     /* 433194 */ // Label 8577: @433194
     /* 433194 */ GIM_Reject,
     /* 433195 */ // Label 8571: @433195
     /* 433195 */ GIM_Reject,
     /* 433196 */ // Label 139: @433196
     /* 433196 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 8582*/ GIMT_Encode4(433565),
     /* 433207 */ /*GILLT_v2s32*//*Label 8578*/ GIMT_Encode4(433267), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 433219 */ /*GILLT_v4s32*//*Label 8579*/ GIMT_Encode4(433387), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 433251 */ /*GILLT_nxv2s64*//*Label 8580*/ GIMT_Encode4(433507), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 433263 */ /*GILLT_nxv4s32*//*Label 8581*/ GIMT_Encode4(433536),
     /* 433267 */ // Label 8578: @433267
     /* 433267 */ GIM_Try, /*On fail goto*//*Label 8583*/ GIMT_Encode4(433386),
     /* 433272 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 433275 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 433278 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 433281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433285 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433289 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433293 */   GIM_Try, /*On fail goto*//*Label 8584*/ GIMT_Encode4(433366), // Rule ID 26 //
     /* 433298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 433301 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 433305 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 433309 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 433313 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433317 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 433321 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433325 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433329 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433334 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433338 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433342 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 433346 */     // MIs[3] Operand 1
     /* 433346 */     // No operand predicates
     /* 433346 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433348 */     // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 433348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev8i8),
     /* 433351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433353 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 433355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 433357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433361 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433364 */     GIR_RootConstrainSelectedInstOperands,
     /* 433365 */     // GIR_Coverage, 26,
     /* 433365 */     GIR_EraseRootFromParent_Done,
     /* 433366 */   // Label 8584: @433366
     /* 433366 */   GIM_Try, /*On fail goto*//*Label 8585*/ GIMT_Encode4(433385), // Rule ID 22 //
     /* 433371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 433374 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433378 */     // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 433378 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv8i8),
     /* 433383 */     GIR_RootConstrainSelectedInstOperands,
     /* 433384 */     // GIR_Coverage, 22,
     /* 433384 */     GIR_Done,
     /* 433385 */   // Label 8585: @433385
     /* 433385 */   GIM_Reject,
     /* 433386 */ // Label 8583: @433386
     /* 433386 */ GIM_Reject,
     /* 433387 */ // Label 8579: @433387
     /* 433387 */ GIM_Try, /*On fail goto*//*Label 8586*/ GIMT_Encode4(433506),
     /* 433392 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433395 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 433398 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 433401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433409 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433413 */   GIM_Try, /*On fail goto*//*Label 8587*/ GIMT_Encode4(433486), // Rule ID 27 //
     /* 433418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 433421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 433425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 433429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433433 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433437 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 433441 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433445 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433449 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433454 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433458 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433462 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 433466 */     // MIs[3] Operand 1
     /* 433466 */     // No operand predicates
     /* 433466 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433468 */     // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 433468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev16i8),
     /* 433471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433473 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 433475 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 433477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433481 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433484 */     GIR_RootConstrainSelectedInstOperands,
     /* 433485 */     // GIR_Coverage, 27,
     /* 433485 */     GIR_EraseRootFromParent_Done,
     /* 433486 */   // Label 8587: @433486
     /* 433486 */   GIM_Try, /*On fail goto*//*Label 8588*/ GIMT_Encode4(433505), // Rule ID 23 //
     /* 433491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 433494 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433498 */     // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 433498 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv16i8),
     /* 433503 */     GIR_RootConstrainSelectedInstOperands,
     /* 433504 */     // GIR_Coverage, 23,
     /* 433504 */     GIR_Done,
     /* 433505 */   // Label 8588: @433505
     /* 433505 */   GIM_Reject,
     /* 433506 */ // Label 8586: @433506
     /* 433506 */ GIM_Reject,
     /* 433507 */ // Label 8580: @433507
     /* 433507 */ GIM_Try, /*On fail goto*//*Label 8589*/ GIMT_Encode4(433535), // Rule ID 3001 //
     /* 433512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 433515 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 433518 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 433521 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 433524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 433528 */   // (AArch64sdot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SDOT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 433528 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_D),
     /* 433533 */   GIR_RootConstrainSelectedInstOperands,
     /* 433534 */   // GIR_Coverage, 3001,
     /* 433534 */   GIR_Done,
     /* 433535 */ // Label 8589: @433535
     /* 433535 */ GIM_Reject,
     /* 433536 */ // Label 8581: @433536
     /* 433536 */ GIM_Try, /*On fail goto*//*Label 8590*/ GIMT_Encode4(433564), // Rule ID 3000 //
     /* 433541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 433544 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 433547 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 433550 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 433553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 433557 */   // (AArch64sdot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SDOT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 433557 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_S),
     /* 433562 */   GIR_RootConstrainSelectedInstOperands,
     /* 433563 */   // GIR_Coverage, 3000,
     /* 433563 */   GIR_Done,
     /* 433564 */ // Label 8590: @433564
     /* 433564 */ GIM_Reject,
     /* 433565 */ // Label 8582: @433565
     /* 433565 */ GIM_Reject,
     /* 433566 */ // Label 140: @433566
     /* 433566 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8594*/ GIMT_Encode4(433682),
     /* 433577 */ /*GILLT_s16*//*Label 8591*/ GIMT_Encode4(433589),
     /* 433581 */ /*GILLT_s32*//*Label 8592*/ GIMT_Encode4(433620),
     /* 433585 */ /*GILLT_s64*//*Label 8593*/ GIMT_Encode4(433651),
     /* 433589 */ // Label 8591: @433589
     /* 433589 */ GIM_Try, /*On fail goto*//*Label 8595*/ GIMT_Encode4(433619), // Rule ID 1662 //
     /* 433594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 433597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 433600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433604 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433608 */   // (AArch64sitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (SCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 433608 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 433613 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 433617 */   GIR_RootConstrainSelectedInstOperands,
     /* 433618 */   // GIR_Coverage, 1662,
     /* 433618 */   GIR_Done,
     /* 433619 */ // Label 8595: @433619
     /* 433619 */ GIM_Reject,
     /* 433620 */ // Label 8592: @433620
     /* 433620 */ GIM_Try, /*On fail goto*//*Label 8596*/ GIMT_Encode4(433650), // Rule ID 1661 //
     /* 433625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 433628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 433631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 433635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 433639 */   // (AArch64sitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 433639 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 433644 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 433648 */   GIR_RootConstrainSelectedInstOperands,
     /* 433649 */   // GIR_Coverage, 1661,
     /* 433649 */   GIR_Done,
     /* 433650 */ // Label 8596: @433650
     /* 433650 */ GIM_Reject,
     /* 433651 */ // Label 8593: @433651
     /* 433651 */ GIM_Try, /*On fail goto*//*Label 8597*/ GIMT_Encode4(433681), // Rule ID 1660 //
     /* 433656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 433659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 433662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433666 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433670 */   // (AArch64sitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 433670 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 433675 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 433679 */   GIR_RootConstrainSelectedInstOperands,
     /* 433680 */   // GIR_Coverage, 1660,
     /* 433680 */   GIR_Done,
     /* 433681 */ // Label 8597: @433681
     /* 433681 */ GIM_Reject,
     /* 433682 */ // Label 8594: @433682
     /* 433682 */ GIM_Reject,
     /* 433683 */ // Label 141: @433683
     /* 433683 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 8601*/ GIMT_Encode4(434915),
     /* 433694 */ /*GILLT_v2s64*//*Label 8598*/ GIMT_Encode4(433714), GIMT_Encode4(0),
     /* 433702 */ /*GILLT_v4s32*//*Label 8599*/ GIMT_Encode4(434275), GIMT_Encode4(0),
     /* 433710 */ /*GILLT_v8s16*//*Label 8600*/ GIMT_Encode4(434836),
     /* 433714 */ // Label 8598: @433714
     /* 433714 */ GIM_Try, /*On fail goto*//*Label 8602*/ GIMT_Encode4(434274),
     /* 433719 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 433722 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 433725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433729 */   GIM_Try, /*On fail goto*//*Label 8603*/ GIMT_Encode4(433821), // Rule ID 2058 //
     /* 433734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 433737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 433741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 433745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 433757 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433761 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433765 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433770 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433774 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433778 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 433782 */     // MIs[3] Operand 1
     /* 433782 */     // No operand predicates
     /* 433782 */     // MIs[1] Operand 2
     /* 433782 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 433793 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 433802 */     // (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (SMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 433802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_indexed),
     /* 433805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 433812 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433816 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433819 */     GIR_RootConstrainSelectedInstOperands,
     /* 433820 */     // GIR_Coverage, 2058,
     /* 433820 */     GIR_EraseRootFromParent_Done,
     /* 433821 */   // Label 8603: @433821
     /* 433821 */   GIM_Try, /*On fail goto*//*Label 8604*/ GIMT_Encode4(433913), // Rule ID 13806 //
     /* 433826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 433829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 433837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433841 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433845 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 433849 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433853 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433857 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433862 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433866 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433870 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 433874 */     // MIs[3] Operand 1
     /* 433874 */     // No operand predicates
     /* 433874 */     // MIs[1] Operand 2
     /* 433874 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 433885 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 433894 */     // (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (SMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 433894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_indexed),
     /* 433897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 433904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433911 */     GIR_RootConstrainSelectedInstOperands,
     /* 433912 */     // GIR_Coverage, 13806,
     /* 433912 */     GIR_EraseRootFromParent_Done,
     /* 433913 */   // Label 8604: @433913
     /* 433913 */   GIM_Try, /*On fail goto*//*Label 8605*/ GIMT_Encode4(433999), // Rule ID 13804 //
     /* 433918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 433921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 433929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433933 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433937 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 433941 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 433945 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433949 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433954 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433958 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433962 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 433966 */     // MIs[3] Operand 1
     /* 433966 */     // No operand predicates
     /* 433966 */     // MIs[1] Operand 2
     /* 433966 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 433977 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 433981 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433983 */     // (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 433983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 433986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 433990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433994 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433997 */     GIR_RootConstrainSelectedInstOperands,
     /* 433998 */     // GIR_Coverage, 13804,
     /* 433998 */     GIR_EraseRootFromParent_Done,
     /* 433999 */   // Label 8605: @433999
     /* 433999 */   GIM_Try, /*On fail goto*//*Label 8606*/ GIMT_Encode4(434085), // Rule ID 2056 //
     /* 434004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434007 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 434019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 434023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 434031 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 434035 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434044 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434048 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434052 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 434056 */     // MIs[3] Operand 1
     /* 434056 */     // No operand predicates
     /* 434056 */     // MIs[1] Operand 2
     /* 434056 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 434067 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434069 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 434072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434074 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434076 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434080 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434083 */     GIR_RootConstrainSelectedInstOperands,
     /* 434084 */     // GIR_Coverage, 2056,
     /* 434084 */     GIR_EraseRootFromParent_Done,
     /* 434085 */   // Label 8606: @434085
     /* 434085 */   GIM_Try, /*On fail goto*//*Label 8607*/ GIMT_Encode4(434124), // Rule ID 1745 //
     /* 434090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 434100 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 434107 */     // (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (SMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 434107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
     /* 434110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 434117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 434122 */     GIR_RootConstrainSelectedInstOperands,
     /* 434123 */     // GIR_Coverage, 1745,
     /* 434123 */     GIR_EraseRootFromParent_Done,
     /* 434124 */   // Label 8607: @434124
     /* 434124 */   GIM_Try, /*On fail goto*//*Label 8608*/ GIMT_Encode4(434187), // Rule ID 13805 //
     /* 434129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 434140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 434144 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434148 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434161 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 434165 */     // MIs[2] Operand 1
     /* 434165 */     // No operand predicates
     /* 434165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434169 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434171 */     // (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 434174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434182 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434185 */     GIR_RootConstrainSelectedInstOperands,
     /* 434186 */     // GIR_Coverage, 13805,
     /* 434186 */     GIR_EraseRootFromParent_Done,
     /* 434187 */   // Label 8608: @434187
     /* 434187 */   GIM_Try, /*On fail goto*//*Label 8609*/ GIMT_Encode4(434250), // Rule ID 2057 //
     /* 434192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434195 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 434207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 434211 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434228 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 434232 */     // MIs[2] Operand 1
     /* 434232 */     // No operand predicates
     /* 434232 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434234 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 434237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434239 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434245 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434248 */     GIR_RootConstrainSelectedInstOperands,
     /* 434249 */     // GIR_Coverage, 2057,
     /* 434249 */     GIR_EraseRootFromParent_Done,
     /* 434250 */   // Label 8609: @434250
     /* 434250 */   GIM_Try, /*On fail goto*//*Label 8610*/ GIMT_Encode4(434273), // Rule ID 1744 //
     /* 434255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434266 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 434266 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
     /* 434271 */     GIR_RootConstrainSelectedInstOperands,
     /* 434272 */     // GIR_Coverage, 1744,
     /* 434272 */     GIR_Done,
     /* 434273 */   // Label 8610: @434273
     /* 434273 */   GIM_Reject,
     /* 434274 */ // Label 8602: @434274
     /* 434274 */ GIM_Reject,
     /* 434275 */ // Label 8599: @434275
     /* 434275 */ GIM_Try, /*On fail goto*//*Label 8611*/ GIMT_Encode4(434835),
     /* 434280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 434283 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 434286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434290 */   GIM_Try, /*On fail goto*//*Label 8612*/ GIMT_Encode4(434382), // Rule ID 2055 //
     /* 434295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 434306 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434310 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434314 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434318 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434322 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434326 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434331 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434335 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434339 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434343 */     // MIs[3] Operand 1
     /* 434343 */     // No operand predicates
     /* 434343 */     // MIs[1] Operand 2
     /* 434343 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 434354 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 434363 */     // (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (SMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_indexed),
     /* 434366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 434373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434377 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434380 */     GIR_RootConstrainSelectedInstOperands,
     /* 434381 */     // GIR_Coverage, 2055,
     /* 434381 */     GIR_EraseRootFromParent_Done,
     /* 434382 */   // Label 8612: @434382
     /* 434382 */   GIM_Try, /*On fail goto*//*Label 8613*/ GIMT_Encode4(434474), // Rule ID 13803 //
     /* 434387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 434398 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434402 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434406 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434410 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434414 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434418 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434423 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434427 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434431 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434435 */     // MIs[3] Operand 1
     /* 434435 */     // No operand predicates
     /* 434435 */     // MIs[1] Operand 2
     /* 434435 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 434446 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 434455 */     // (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (SMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_indexed),
     /* 434458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 434465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434469 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434472 */     GIR_RootConstrainSelectedInstOperands,
     /* 434473 */     // GIR_Coverage, 13803,
     /* 434473 */     GIR_EraseRootFromParent_Done,
     /* 434474 */   // Label 8613: @434474
     /* 434474 */   GIM_Try, /*On fail goto*//*Label 8614*/ GIMT_Encode4(434560), // Rule ID 13801 //
     /* 434479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434482 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434486 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 434490 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434494 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434498 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434502 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434506 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434510 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434515 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434519 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434523 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434527 */     // MIs[3] Operand 1
     /* 434527 */     // No operand predicates
     /* 434527 */     // MIs[1] Operand 2
     /* 434527 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 434538 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434542 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434544 */     // (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 434547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434549 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434551 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434555 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434558 */     GIR_RootConstrainSelectedInstOperands,
     /* 434559 */     // GIR_Coverage, 13801,
     /* 434559 */     GIR_EraseRootFromParent_Done,
     /* 434560 */   // Label 8614: @434560
     /* 434560 */   GIM_Try, /*On fail goto*//*Label 8615*/ GIMT_Encode4(434646), // Rule ID 2053 //
     /* 434565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434568 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 434580 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434592 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434596 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434600 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434605 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434609 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434613 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434617 */     // MIs[3] Operand 1
     /* 434617 */     // No operand predicates
     /* 434617 */     // MIs[1] Operand 2
     /* 434617 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 434628 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434630 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 434633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434635 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434641 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434644 */     GIR_RootConstrainSelectedInstOperands,
     /* 434645 */     // GIR_Coverage, 2053,
     /* 434645 */     GIR_EraseRootFromParent_Done,
     /* 434646 */   // Label 8615: @434646
     /* 434646 */   GIM_Try, /*On fail goto*//*Label 8616*/ GIMT_Encode4(434685), // Rule ID 1743 //
     /* 434651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 434661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 434668 */     // (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (SMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 434668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
     /* 434671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 434678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 434683 */     GIR_RootConstrainSelectedInstOperands,
     /* 434684 */     // GIR_Coverage, 1743,
     /* 434684 */     GIR_EraseRootFromParent_Done,
     /* 434685 */   // Label 8616: @434685
     /* 434685 */   GIM_Try, /*On fail goto*//*Label 8617*/ GIMT_Encode4(434748), // Rule ID 13802 //
     /* 434690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434701 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434705 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434722 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434726 */     // MIs[2] Operand 1
     /* 434726 */     // No operand predicates
     /* 434726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434730 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434732 */     // (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 434735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434743 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434746 */     GIR_RootConstrainSelectedInstOperands,
     /* 434747 */     // GIR_Coverage, 13802,
     /* 434747 */     GIR_EraseRootFromParent_Done,
     /* 434748 */   // Label 8617: @434748
     /* 434748 */   GIM_Try, /*On fail goto*//*Label 8618*/ GIMT_Encode4(434811), // Rule ID 2054 //
     /* 434753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434756 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434760 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434764 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 434768 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434772 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434776 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434789 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434793 */     // MIs[2] Operand 1
     /* 434793 */     // No operand predicates
     /* 434793 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434795 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 434795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 434798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434800 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434806 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434809 */     GIR_RootConstrainSelectedInstOperands,
     /* 434810 */     // GIR_Coverage, 2054,
     /* 434810 */     GIR_EraseRootFromParent_Done,
     /* 434811 */   // Label 8618: @434811
     /* 434811 */   GIM_Try, /*On fail goto*//*Label 8619*/ GIMT_Encode4(434834), // Rule ID 1742 //
     /* 434816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434819 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434823 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434827 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 434827 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
     /* 434832 */     GIR_RootConstrainSelectedInstOperands,
     /* 434833 */     // GIR_Coverage, 1742,
     /* 434833 */     GIR_Done,
     /* 434834 */   // Label 8619: @434834
     /* 434834 */   GIM_Reject,
     /* 434835 */ // Label 8611: @434835
     /* 434835 */ GIM_Reject,
     /* 434836 */ // Label 8600: @434836
     /* 434836 */ GIM_Try, /*On fail goto*//*Label 8620*/ GIMT_Encode4(434914),
     /* 434841 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 434844 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 434847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434851 */   GIM_Try, /*On fail goto*//*Label 8621*/ GIMT_Encode4(434890), // Rule ID 1741 //
     /* 434856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 434866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 434873 */     // (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (SMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 434873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
     /* 434876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 434883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 434888 */     GIR_RootConstrainSelectedInstOperands,
     /* 434889 */     // GIR_Coverage, 1741,
     /* 434889 */     GIR_EraseRootFromParent_Done,
     /* 434890 */   // Label 8621: @434890
     /* 434890 */   GIM_Try, /*On fail goto*//*Label 8622*/ GIMT_Encode4(434913), // Rule ID 1740 //
     /* 434895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 434898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 434906 */     // (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 434906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
     /* 434911 */     GIR_RootConstrainSelectedInstOperands,
     /* 434912 */     // GIR_Coverage, 1740,
     /* 434912 */     GIR_Done,
     /* 434913 */   // Label 8622: @434913
     /* 434913 */   GIM_Reject,
     /* 434914 */ // Label 8620: @434914
     /* 434914 */ GIM_Reject,
     /* 434915 */ // Label 8601: @434915
     /* 434915 */ GIM_Reject,
     /* 434916 */ // Label 142: @434916
     /* 434916 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 8641*/ GIMT_Encode4(435695),
     /* 434927 */ /*GILLT_v2s32*//*Label 8623*/ GIMT_Encode4(435003),
     /* 434931 */ /*GILLT_v2s64*//*Label 8624*/ GIMT_Encode4(435058),
     /* 434935 */ /*GILLT_v4s16*//*Label 8625*/ GIMT_Encode4(435113),
     /* 434939 */ /*GILLT_v4s32*//*Label 8626*/ GIMT_Encode4(435168),
     /* 434943 */ /*GILLT_v8s8*//*Label 8627*/ GIMT_Encode4(435223),
     /* 434947 */ /*GILLT_v8s16*//*Label 8628*/ GIMT_Encode4(435257),
     /* 434951 */ /*GILLT_v16s8*//*Label 8629*/ GIMT_Encode4(435312), GIMT_Encode4(0),
     /* 434959 */ /*GILLT_nxv2s1*//*Label 8630*/ GIMT_Encode4(435346),
     /* 434963 */ /*GILLT_nxv2s16*//*Label 8631*/ GIMT_Encode4(435372),
     /* 434967 */ /*GILLT_nxv2s32*//*Label 8632*/ GIMT_Encode4(435398),
     /* 434971 */ /*GILLT_nxv2s64*//*Label 8633*/ GIMT_Encode4(435424),
     /* 434975 */ /*GILLT_nxv4s1*//*Label 8634*/ GIMT_Encode4(435471),
     /* 434979 */ /*GILLT_nxv4s16*//*Label 8635*/ GIMT_Encode4(435497),
     /* 434983 */ /*GILLT_nxv4s32*//*Label 8636*/ GIMT_Encode4(435523),
     /* 434987 */ /*GILLT_nxv8s1*//*Label 8637*/ GIMT_Encode4(435570),
     /* 434991 */ /*GILLT_nxv8s16*//*Label 8638*/ GIMT_Encode4(435596),
     /* 434995 */ /*GILLT_nxv16s1*//*Label 8639*/ GIMT_Encode4(435643),
     /* 434999 */ /*GILLT_nxv16s8*//*Label 8640*/ GIMT_Encode4(435669),
     /* 435003 */ // Label 8623: @435003
     /* 435003 */ GIM_Try, /*On fail goto*//*Label 8642*/ GIMT_Encode4(435057),
     /* 435008 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 435011 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 435014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435018 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435022 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435026 */   GIM_Try, /*On fail goto*//*Label 8643*/ GIMT_Encode4(435041), // Rule ID 1878 //
     /* 435031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435034 */     // (AArch64trn1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (TRN1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 435034 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
     /* 435039 */     GIR_RootConstrainSelectedInstOperands,
     /* 435040 */     // GIR_Coverage, 1878,
     /* 435040 */     GIR_Done,
     /* 435041 */   // Label 8643: @435041
     /* 435041 */   GIM_Try, /*On fail goto*//*Label 8644*/ GIMT_Encode4(435056), // Rule ID 2505 //
     /* 435046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435049 */     // (AArch64trn1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (TRN1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 435049 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
     /* 435054 */     GIR_RootConstrainSelectedInstOperands,
     /* 435055 */     // GIR_Coverage, 2505,
     /* 435055 */     GIR_Done,
     /* 435056 */   // Label 8644: @435056
     /* 435056 */   GIM_Reject,
     /* 435057 */ // Label 8642: @435057
     /* 435057 */ GIM_Reject,
     /* 435058 */ // Label 8624: @435058
     /* 435058 */ GIM_Try, /*On fail goto*//*Label 8645*/ GIMT_Encode4(435112),
     /* 435063 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 435066 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 435069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435073 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435077 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435081 */   GIM_Try, /*On fail goto*//*Label 8646*/ GIMT_Encode4(435096), // Rule ID 1880 //
     /* 435086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435089 */     // (AArch64trn1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (TRN1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 435089 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
     /* 435094 */     GIR_RootConstrainSelectedInstOperands,
     /* 435095 */     // GIR_Coverage, 1880,
     /* 435095 */     GIR_Done,
     /* 435096 */   // Label 8646: @435096
     /* 435096 */   GIM_Try, /*On fail goto*//*Label 8647*/ GIMT_Encode4(435111), // Rule ID 2507 //
     /* 435101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435104 */     // (AArch64trn1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (TRN1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 435104 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
     /* 435109 */     GIR_RootConstrainSelectedInstOperands,
     /* 435110 */     // GIR_Coverage, 2507,
     /* 435110 */     GIR_Done,
     /* 435111 */   // Label 8647: @435111
     /* 435111 */   GIM_Reject,
     /* 435112 */ // Label 8645: @435112
     /* 435112 */ GIM_Reject,
     /* 435113 */ // Label 8625: @435113
     /* 435113 */ GIM_Try, /*On fail goto*//*Label 8648*/ GIMT_Encode4(435167),
     /* 435118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 435121 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 435124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435128 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435132 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435136 */   GIM_Try, /*On fail goto*//*Label 8649*/ GIMT_Encode4(435151), // Rule ID 1876 //
     /* 435141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435144 */     // (AArch64trn1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (TRN1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 435144 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
     /* 435149 */     GIR_RootConstrainSelectedInstOperands,
     /* 435150 */     // GIR_Coverage, 1876,
     /* 435150 */     GIR_Done,
     /* 435151 */   // Label 8649: @435151
     /* 435151 */   GIM_Try, /*On fail goto*//*Label 8650*/ GIMT_Encode4(435166), // Rule ID 2503 //
     /* 435156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435159 */     // (AArch64trn1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (TRN1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 435159 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
     /* 435164 */     GIR_RootConstrainSelectedInstOperands,
     /* 435165 */     // GIR_Coverage, 2503,
     /* 435165 */     GIR_Done,
     /* 435166 */   // Label 8650: @435166
     /* 435166 */   GIM_Reject,
     /* 435167 */ // Label 8648: @435167
     /* 435167 */ GIM_Reject,
     /* 435168 */ // Label 8626: @435168
     /* 435168 */ GIM_Try, /*On fail goto*//*Label 8651*/ GIMT_Encode4(435222),
     /* 435173 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435176 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 435179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435183 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435187 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435191 */   GIM_Try, /*On fail goto*//*Label 8652*/ GIMT_Encode4(435206), // Rule ID 1879 //
     /* 435196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435199 */     // (AArch64trn1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (TRN1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 435199 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
     /* 435204 */     GIR_RootConstrainSelectedInstOperands,
     /* 435205 */     // GIR_Coverage, 1879,
     /* 435205 */     GIR_Done,
     /* 435206 */   // Label 8652: @435206
     /* 435206 */   GIM_Try, /*On fail goto*//*Label 8653*/ GIMT_Encode4(435221), // Rule ID 2506 //
     /* 435211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435214 */     // (AArch64trn1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (TRN1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 435214 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
     /* 435219 */     GIR_RootConstrainSelectedInstOperands,
     /* 435220 */     // GIR_Coverage, 2506,
     /* 435220 */     GIR_Done,
     /* 435221 */   // Label 8653: @435221
     /* 435221 */   GIM_Reject,
     /* 435222 */ // Label 8651: @435222
     /* 435222 */ GIM_Reject,
     /* 435223 */ // Label 8627: @435223
     /* 435223 */ GIM_Try, /*On fail goto*//*Label 8654*/ GIMT_Encode4(435256), // Rule ID 1874 //
     /* 435228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435231 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 435234 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 435237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435241 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435245 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435249 */   // (AArch64trn1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (TRN1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 435249 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i8),
     /* 435254 */   GIR_RootConstrainSelectedInstOperands,
     /* 435255 */   // GIR_Coverage, 1874,
     /* 435255 */   GIR_Done,
     /* 435256 */ // Label 8654: @435256
     /* 435256 */ GIM_Reject,
     /* 435257 */ // Label 8628: @435257
     /* 435257 */ GIM_Try, /*On fail goto*//*Label 8655*/ GIMT_Encode4(435311),
     /* 435262 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 435265 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 435268 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435272 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435276 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435280 */   GIM_Try, /*On fail goto*//*Label 8656*/ GIMT_Encode4(435295), // Rule ID 1877 //
     /* 435285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435288 */     // (AArch64trn1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (TRN1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 435288 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
     /* 435293 */     GIR_RootConstrainSelectedInstOperands,
     /* 435294 */     // GIR_Coverage, 1877,
     /* 435294 */     GIR_Done,
     /* 435295 */   // Label 8656: @435295
     /* 435295 */   GIM_Try, /*On fail goto*//*Label 8657*/ GIMT_Encode4(435310), // Rule ID 2504 //
     /* 435300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435303 */     // (AArch64trn1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (TRN1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 435303 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
     /* 435308 */     GIR_RootConstrainSelectedInstOperands,
     /* 435309 */     // GIR_Coverage, 2504,
     /* 435309 */     GIR_Done,
     /* 435310 */   // Label 8657: @435310
     /* 435310 */   GIM_Reject,
     /* 435311 */ // Label 8655: @435311
     /* 435311 */ GIM_Reject,
     /* 435312 */ // Label 8629: @435312
     /* 435312 */ GIM_Try, /*On fail goto*//*Label 8658*/ GIMT_Encode4(435345), // Rule ID 1875 //
     /* 435317 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435320 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 435323 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 435326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435330 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435334 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435338 */   // (AArch64trn1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (TRN1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 435338 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v16i8),
     /* 435343 */   GIR_RootConstrainSelectedInstOperands,
     /* 435344 */   // GIR_Coverage, 1875,
     /* 435344 */   GIR_Done,
     /* 435345 */ // Label 8658: @435345
     /* 435345 */ GIM_Reject,
     /* 435346 */ // Label 8630: @435346
     /* 435346 */ GIM_Try, /*On fail goto*//*Label 8659*/ GIMT_Encode4(435371), // Rule ID 9090 //
     /* 435351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 435357 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 435360 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 435364 */   // (AArch64trn1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (TRN1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 435364 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
     /* 435369 */   GIR_RootConstrainSelectedInstOperands,
     /* 435370 */   // GIR_Coverage, 9090,
     /* 435370 */   GIR_Done,
     /* 435371 */ // Label 8659: @435371
     /* 435371 */ GIM_Reject,
     /* 435372 */ // Label 8631: @435372
     /* 435372 */ GIM_Try, /*On fail goto*//*Label 8660*/ GIMT_Encode4(435397), // Rule ID 9066 //
     /* 435377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435380 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 435383 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 435386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435390 */   // (AArch64trn1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 435390 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 435395 */   GIR_RootConstrainSelectedInstOperands,
     /* 435396 */   // GIR_Coverage, 9066,
     /* 435396 */   GIR_Done,
     /* 435397 */ // Label 8660: @435397
     /* 435397 */ GIM_Reject,
     /* 435398 */ // Label 8632: @435398
     /* 435398 */ GIM_Try, /*On fail goto*//*Label 8661*/ GIMT_Encode4(435423), // Rule ID 9067 //
     /* 435403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435406 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 435409 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 435412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435416 */   // (AArch64trn1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 435416 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 435421 */   GIR_RootConstrainSelectedInstOperands,
     /* 435422 */   // GIR_Coverage, 9067,
     /* 435422 */   GIR_Done,
     /* 435423 */ // Label 8661: @435423
     /* 435423 */ GIM_Reject,
     /* 435424 */ // Label 8633: @435424
     /* 435424 */ GIM_Try, /*On fail goto*//*Label 8662*/ GIMT_Encode4(435470),
     /* 435429 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 435432 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 435435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435439 */   GIM_Try, /*On fail goto*//*Label 8663*/ GIMT_Encode4(435454), // Rule ID 9062 //
     /* 435444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435447 */     // (AArch64trn1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 435447 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 435452 */     GIR_RootConstrainSelectedInstOperands,
     /* 435453 */     // GIR_Coverage, 9062,
     /* 435453 */     GIR_Done,
     /* 435454 */   // Label 8663: @435454
     /* 435454 */   GIM_Try, /*On fail goto*//*Label 8664*/ GIMT_Encode4(435469), // Rule ID 9068 //
     /* 435459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435462 */     // (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 435462 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 435467 */     GIR_RootConstrainSelectedInstOperands,
     /* 435468 */     // GIR_Coverage, 9068,
     /* 435468 */     GIR_Done,
     /* 435469 */   // Label 8664: @435469
     /* 435469 */   GIM_Reject,
     /* 435470 */ // Label 8662: @435470
     /* 435470 */ GIM_Reject,
     /* 435471 */ // Label 8634: @435471
     /* 435471 */ GIM_Try, /*On fail goto*//*Label 8665*/ GIMT_Encode4(435496), // Rule ID 9089 //
     /* 435476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 435482 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 435485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 435489 */   // (AArch64trn1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (TRN1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 435489 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
     /* 435494 */   GIR_RootConstrainSelectedInstOperands,
     /* 435495 */   // GIR_Coverage, 9089,
     /* 435495 */   GIR_Done,
     /* 435496 */ // Label 8665: @435496
     /* 435496 */ GIM_Reject,
     /* 435497 */ // Label 8635: @435497
     /* 435497 */ GIM_Try, /*On fail goto*//*Label 8666*/ GIMT_Encode4(435522), // Rule ID 9064 //
     /* 435502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435505 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 435508 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 435511 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435515 */   // (AArch64trn1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 435515 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 435520 */   GIR_RootConstrainSelectedInstOperands,
     /* 435521 */   // GIR_Coverage, 9064,
     /* 435521 */   GIR_Done,
     /* 435522 */ // Label 8666: @435522
     /* 435522 */ GIM_Reject,
     /* 435523 */ // Label 8636: @435523
     /* 435523 */ GIM_Try, /*On fail goto*//*Label 8667*/ GIMT_Encode4(435569),
     /* 435528 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 435531 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 435534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435538 */   GIM_Try, /*On fail goto*//*Label 8668*/ GIMT_Encode4(435553), // Rule ID 9061 //
     /* 435543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435546 */     // (AArch64trn1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 435546 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 435551 */     GIR_RootConstrainSelectedInstOperands,
     /* 435552 */     // GIR_Coverage, 9061,
     /* 435552 */     GIR_Done,
     /* 435553 */   // Label 8668: @435553
     /* 435553 */   GIM_Try, /*On fail goto*//*Label 8669*/ GIMT_Encode4(435568), // Rule ID 9065 //
     /* 435558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435561 */     // (AArch64trn1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 435561 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 435566 */     GIR_RootConstrainSelectedInstOperands,
     /* 435567 */     // GIR_Coverage, 9065,
     /* 435567 */     GIR_Done,
     /* 435568 */   // Label 8669: @435568
     /* 435568 */   GIM_Reject,
     /* 435569 */ // Label 8667: @435569
     /* 435569 */ GIM_Reject,
     /* 435570 */ // Label 8637: @435570
     /* 435570 */ GIM_Try, /*On fail goto*//*Label 8670*/ GIMT_Encode4(435595), // Rule ID 9088 //
     /* 435575 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435578 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 435581 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 435584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 435588 */   // (AArch64trn1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (TRN1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 435588 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
     /* 435593 */   GIR_RootConstrainSelectedInstOperands,
     /* 435594 */   // GIR_Coverage, 9088,
     /* 435594 */   GIR_Done,
     /* 435595 */ // Label 8670: @435595
     /* 435595 */ GIM_Reject,
     /* 435596 */ // Label 8638: @435596
     /* 435596 */ GIM_Try, /*On fail goto*//*Label 8671*/ GIMT_Encode4(435642),
     /* 435601 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 435604 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 435607 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435611 */   GIM_Try, /*On fail goto*//*Label 8672*/ GIMT_Encode4(435626), // Rule ID 9060 //
     /* 435616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435619 */     // (AArch64trn1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 435619 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
     /* 435624 */     GIR_RootConstrainSelectedInstOperands,
     /* 435625 */     // GIR_Coverage, 9060,
     /* 435625 */     GIR_Done,
     /* 435626 */   // Label 8672: @435626
     /* 435626 */   GIM_Try, /*On fail goto*//*Label 8673*/ GIMT_Encode4(435641), // Rule ID 9063 //
     /* 435631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435634 */     // (AArch64trn1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 435634 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
     /* 435639 */     GIR_RootConstrainSelectedInstOperands,
     /* 435640 */     // GIR_Coverage, 9063,
     /* 435640 */     GIR_Done,
     /* 435641 */   // Label 8673: @435641
     /* 435641 */   GIM_Reject,
     /* 435642 */ // Label 8671: @435642
     /* 435642 */ GIM_Reject,
     /* 435643 */ // Label 8639: @435643
     /* 435643 */ GIM_Try, /*On fail goto*//*Label 8674*/ GIMT_Encode4(435668), // Rule ID 2418 //
     /* 435648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 435654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 435657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 435661 */   // (AArch64trn1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 435661 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_B),
     /* 435666 */   GIR_RootConstrainSelectedInstOperands,
     /* 435667 */   // GIR_Coverage, 2418,
     /* 435667 */   GIR_Done,
     /* 435668 */ // Label 8674: @435668
     /* 435668 */ GIM_Reject,
     /* 435669 */ // Label 8640: @435669
     /* 435669 */ GIM_Try, /*On fail goto*//*Label 8675*/ GIMT_Encode4(435694), // Rule ID 9059 //
     /* 435674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 435677 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 435680 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 435683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 435687 */   // (AArch64trn1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 435687 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_B),
     /* 435692 */   GIR_RootConstrainSelectedInstOperands,
     /* 435693 */   // GIR_Coverage, 9059,
     /* 435693 */   GIR_Done,
     /* 435694 */ // Label 8675: @435694
     /* 435694 */ GIM_Reject,
     /* 435695 */ // Label 8641: @435695
     /* 435695 */ GIM_Reject,
     /* 435696 */ // Label 143: @435696
     /* 435696 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 8694*/ GIMT_Encode4(436475),
     /* 435707 */ /*GILLT_v2s32*//*Label 8676*/ GIMT_Encode4(435783),
     /* 435711 */ /*GILLT_v2s64*//*Label 8677*/ GIMT_Encode4(435838),
     /* 435715 */ /*GILLT_v4s16*//*Label 8678*/ GIMT_Encode4(435893),
     /* 435719 */ /*GILLT_v4s32*//*Label 8679*/ GIMT_Encode4(435948),
     /* 435723 */ /*GILLT_v8s8*//*Label 8680*/ GIMT_Encode4(436003),
     /* 435727 */ /*GILLT_v8s16*//*Label 8681*/ GIMT_Encode4(436037),
     /* 435731 */ /*GILLT_v16s8*//*Label 8682*/ GIMT_Encode4(436092), GIMT_Encode4(0),
     /* 435739 */ /*GILLT_nxv2s1*//*Label 8683*/ GIMT_Encode4(436126),
     /* 435743 */ /*GILLT_nxv2s16*//*Label 8684*/ GIMT_Encode4(436152),
     /* 435747 */ /*GILLT_nxv2s32*//*Label 8685*/ GIMT_Encode4(436178),
     /* 435751 */ /*GILLT_nxv2s64*//*Label 8686*/ GIMT_Encode4(436204),
     /* 435755 */ /*GILLT_nxv4s1*//*Label 8687*/ GIMT_Encode4(436251),
     /* 435759 */ /*GILLT_nxv4s16*//*Label 8688*/ GIMT_Encode4(436277),
     /* 435763 */ /*GILLT_nxv4s32*//*Label 8689*/ GIMT_Encode4(436303),
     /* 435767 */ /*GILLT_nxv8s1*//*Label 8690*/ GIMT_Encode4(436350),
     /* 435771 */ /*GILLT_nxv8s16*//*Label 8691*/ GIMT_Encode4(436376),
     /* 435775 */ /*GILLT_nxv16s1*//*Label 8692*/ GIMT_Encode4(436423),
     /* 435779 */ /*GILLT_nxv16s8*//*Label 8693*/ GIMT_Encode4(436449),
     /* 435783 */ // Label 8676: @435783
     /* 435783 */ GIM_Try, /*On fail goto*//*Label 8695*/ GIMT_Encode4(435837),
     /* 435788 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 435791 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 435794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435798 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435802 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435806 */   GIM_Try, /*On fail goto*//*Label 8696*/ GIMT_Encode4(435821), // Rule ID 1885 //
     /* 435811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435814 */     // (AArch64trn2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (TRN2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 435814 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
     /* 435819 */     GIR_RootConstrainSelectedInstOperands,
     /* 435820 */     // GIR_Coverage, 1885,
     /* 435820 */     GIR_Done,
     /* 435821 */   // Label 8696: @435821
     /* 435821 */   GIM_Try, /*On fail goto*//*Label 8697*/ GIMT_Encode4(435836), // Rule ID 5517 //
     /* 435826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435829 */     // (AArch64trn2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (TRN2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 435829 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
     /* 435834 */     GIR_RootConstrainSelectedInstOperands,
     /* 435835 */     // GIR_Coverage, 5517,
     /* 435835 */     GIR_Done,
     /* 435836 */   // Label 8697: @435836
     /* 435836 */   GIM_Reject,
     /* 435837 */ // Label 8695: @435837
     /* 435837 */ GIM_Reject,
     /* 435838 */ // Label 8677: @435838
     /* 435838 */ GIM_Try, /*On fail goto*//*Label 8698*/ GIMT_Encode4(435892),
     /* 435843 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 435846 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 435849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435853 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435857 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435861 */   GIM_Try, /*On fail goto*//*Label 8699*/ GIMT_Encode4(435876), // Rule ID 1887 //
     /* 435866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435869 */     // (AArch64trn2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (TRN2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 435869 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
     /* 435874 */     GIR_RootConstrainSelectedInstOperands,
     /* 435875 */     // GIR_Coverage, 1887,
     /* 435875 */     GIR_Done,
     /* 435876 */   // Label 8699: @435876
     /* 435876 */   GIM_Try, /*On fail goto*//*Label 8700*/ GIMT_Encode4(435891), // Rule ID 5519 //
     /* 435881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435884 */     // (AArch64trn2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (TRN2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 435884 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
     /* 435889 */     GIR_RootConstrainSelectedInstOperands,
     /* 435890 */     // GIR_Coverage, 5519,
     /* 435890 */     GIR_Done,
     /* 435891 */   // Label 8700: @435891
     /* 435891 */   GIM_Reject,
     /* 435892 */ // Label 8698: @435892
     /* 435892 */ GIM_Reject,
     /* 435893 */ // Label 8678: @435893
     /* 435893 */ GIM_Try, /*On fail goto*//*Label 8701*/ GIMT_Encode4(435947),
     /* 435898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 435901 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 435904 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435908 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435912 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 435916 */   GIM_Try, /*On fail goto*//*Label 8702*/ GIMT_Encode4(435931), // Rule ID 1883 //
     /* 435921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435924 */     // (AArch64trn2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (TRN2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 435924 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
     /* 435929 */     GIR_RootConstrainSelectedInstOperands,
     /* 435930 */     // GIR_Coverage, 1883,
     /* 435930 */     GIR_Done,
     /* 435931 */   // Label 8702: @435931
     /* 435931 */   GIM_Try, /*On fail goto*//*Label 8703*/ GIMT_Encode4(435946), // Rule ID 5515 //
     /* 435936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435939 */     // (AArch64trn2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (TRN2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 435939 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
     /* 435944 */     GIR_RootConstrainSelectedInstOperands,
     /* 435945 */     // GIR_Coverage, 5515,
     /* 435945 */     GIR_Done,
     /* 435946 */   // Label 8703: @435946
     /* 435946 */   GIM_Reject,
     /* 435947 */ // Label 8701: @435947
     /* 435947 */ GIM_Reject,
     /* 435948 */ // Label 8679: @435948
     /* 435948 */ GIM_Try, /*On fail goto*//*Label 8704*/ GIMT_Encode4(436002),
     /* 435953 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435956 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 435959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435963 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435967 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435971 */   GIM_Try, /*On fail goto*//*Label 8705*/ GIMT_Encode4(435986), // Rule ID 1886 //
     /* 435976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435979 */     // (AArch64trn2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (TRN2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 435979 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
     /* 435984 */     GIR_RootConstrainSelectedInstOperands,
     /* 435985 */     // GIR_Coverage, 1886,
     /* 435985 */     GIR_Done,
     /* 435986 */   // Label 8705: @435986
     /* 435986 */   GIM_Try, /*On fail goto*//*Label 8706*/ GIMT_Encode4(436001), // Rule ID 5518 //
     /* 435991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435994 */     // (AArch64trn2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (TRN2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 435994 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
     /* 435999 */     GIR_RootConstrainSelectedInstOperands,
     /* 436000 */     // GIR_Coverage, 5518,
     /* 436000 */     GIR_Done,
     /* 436001 */   // Label 8706: @436001
     /* 436001 */   GIM_Reject,
     /* 436002 */ // Label 8704: @436002
     /* 436002 */ GIM_Reject,
     /* 436003 */ // Label 8680: @436003
     /* 436003 */ GIM_Try, /*On fail goto*//*Label 8707*/ GIMT_Encode4(436036), // Rule ID 1881 //
     /* 436008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 436014 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 436017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436021 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436025 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436029 */   // (AArch64trn2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (TRN2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 436029 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i8),
     /* 436034 */   GIR_RootConstrainSelectedInstOperands,
     /* 436035 */   // GIR_Coverage, 1881,
     /* 436035 */   GIR_Done,
     /* 436036 */ // Label 8707: @436036
     /* 436036 */ GIM_Reject,
     /* 436037 */ // Label 8681: @436037
     /* 436037 */ GIM_Try, /*On fail goto*//*Label 8708*/ GIMT_Encode4(436091),
     /* 436042 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 436045 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 436048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436052 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436056 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436060 */   GIM_Try, /*On fail goto*//*Label 8709*/ GIMT_Encode4(436075), // Rule ID 1884 //
     /* 436065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436068 */     // (AArch64trn2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (TRN2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 436068 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
     /* 436073 */     GIR_RootConstrainSelectedInstOperands,
     /* 436074 */     // GIR_Coverage, 1884,
     /* 436074 */     GIR_Done,
     /* 436075 */   // Label 8709: @436075
     /* 436075 */   GIM_Try, /*On fail goto*//*Label 8710*/ GIMT_Encode4(436090), // Rule ID 5516 //
     /* 436080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436083 */     // (AArch64trn2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (TRN2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 436083 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
     /* 436088 */     GIR_RootConstrainSelectedInstOperands,
     /* 436089 */     // GIR_Coverage, 5516,
     /* 436089 */     GIR_Done,
     /* 436090 */   // Label 8710: @436090
     /* 436090 */   GIM_Reject,
     /* 436091 */ // Label 8708: @436091
     /* 436091 */ GIM_Reject,
     /* 436092 */ // Label 8682: @436092
     /* 436092 */ GIM_Try, /*On fail goto*//*Label 8711*/ GIMT_Encode4(436125), // Rule ID 1882 //
     /* 436097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436100 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 436103 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 436106 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436110 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436114 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436118 */   // (AArch64trn2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (TRN2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 436118 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v16i8),
     /* 436123 */   GIR_RootConstrainSelectedInstOperands,
     /* 436124 */   // GIR_Coverage, 1882,
     /* 436124 */   GIR_Done,
     /* 436125 */ // Label 8711: @436125
     /* 436125 */ GIM_Reject,
     /* 436126 */ // Label 8683: @436126
     /* 436126 */ GIM_Try, /*On fail goto*//*Label 8712*/ GIMT_Encode4(436151), // Rule ID 9093 //
     /* 436131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436134 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 436137 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 436140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 436144 */   // (AArch64trn2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (TRN2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 436144 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
     /* 436149 */   GIR_RootConstrainSelectedInstOperands,
     /* 436150 */   // GIR_Coverage, 9093,
     /* 436150 */   GIR_Done,
     /* 436151 */ // Label 8712: @436151
     /* 436151 */ GIM_Reject,
     /* 436152 */ // Label 8684: @436152
     /* 436152 */ GIM_Try, /*On fail goto*//*Label 8713*/ GIMT_Encode4(436177), // Rule ID 9076 //
     /* 436157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436160 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 436163 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 436166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436170 */   // (AArch64trn2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 436170 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 436175 */   GIR_RootConstrainSelectedInstOperands,
     /* 436176 */   // GIR_Coverage, 9076,
     /* 436176 */   GIR_Done,
     /* 436177 */ // Label 8713: @436177
     /* 436177 */ GIM_Reject,
     /* 436178 */ // Label 8685: @436178
     /* 436178 */ GIM_Try, /*On fail goto*//*Label 8714*/ GIMT_Encode4(436203), // Rule ID 9077 //
     /* 436183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436186 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 436189 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 436192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436196 */   // (AArch64trn2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 436196 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 436201 */   GIR_RootConstrainSelectedInstOperands,
     /* 436202 */   // GIR_Coverage, 9077,
     /* 436202 */   GIR_Done,
     /* 436203 */ // Label 8714: @436203
     /* 436203 */ GIM_Reject,
     /* 436204 */ // Label 8686: @436204
     /* 436204 */ GIM_Try, /*On fail goto*//*Label 8715*/ GIMT_Encode4(436250),
     /* 436209 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 436212 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 436215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436219 */   GIM_Try, /*On fail goto*//*Label 8716*/ GIMT_Encode4(436234), // Rule ID 9072 //
     /* 436224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436227 */     // (AArch64trn2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 436227 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 436232 */     GIR_RootConstrainSelectedInstOperands,
     /* 436233 */     // GIR_Coverage, 9072,
     /* 436233 */     GIR_Done,
     /* 436234 */   // Label 8716: @436234
     /* 436234 */   GIM_Try, /*On fail goto*//*Label 8717*/ GIMT_Encode4(436249), // Rule ID 9078 //
     /* 436239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436242 */     // (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 436242 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 436247 */     GIR_RootConstrainSelectedInstOperands,
     /* 436248 */     // GIR_Coverage, 9078,
     /* 436248 */     GIR_Done,
     /* 436249 */   // Label 8717: @436249
     /* 436249 */   GIM_Reject,
     /* 436250 */ // Label 8715: @436250
     /* 436250 */ GIM_Reject,
     /* 436251 */ // Label 8687: @436251
     /* 436251 */ GIM_Try, /*On fail goto*//*Label 8718*/ GIMT_Encode4(436276), // Rule ID 9092 //
     /* 436256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 436262 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 436265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 436269 */   // (AArch64trn2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (TRN2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 436269 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
     /* 436274 */   GIR_RootConstrainSelectedInstOperands,
     /* 436275 */   // GIR_Coverage, 9092,
     /* 436275 */   GIR_Done,
     /* 436276 */ // Label 8718: @436276
     /* 436276 */ GIM_Reject,
     /* 436277 */ // Label 8688: @436277
     /* 436277 */ GIM_Try, /*On fail goto*//*Label 8719*/ GIMT_Encode4(436302), // Rule ID 9074 //
     /* 436282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436285 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 436288 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 436291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436295 */   // (AArch64trn2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 436295 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 436300 */   GIR_RootConstrainSelectedInstOperands,
     /* 436301 */   // GIR_Coverage, 9074,
     /* 436301 */   GIR_Done,
     /* 436302 */ // Label 8719: @436302
     /* 436302 */ GIM_Reject,
     /* 436303 */ // Label 8689: @436303
     /* 436303 */ GIM_Try, /*On fail goto*//*Label 8720*/ GIMT_Encode4(436349),
     /* 436308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 436311 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 436314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436318 */   GIM_Try, /*On fail goto*//*Label 8721*/ GIMT_Encode4(436333), // Rule ID 9071 //
     /* 436323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436326 */     // (AArch64trn2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 436326 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 436331 */     GIR_RootConstrainSelectedInstOperands,
     /* 436332 */     // GIR_Coverage, 9071,
     /* 436332 */     GIR_Done,
     /* 436333 */   // Label 8721: @436333
     /* 436333 */   GIM_Try, /*On fail goto*//*Label 8722*/ GIMT_Encode4(436348), // Rule ID 9075 //
     /* 436338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436341 */     // (AArch64trn2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 436341 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 436346 */     GIR_RootConstrainSelectedInstOperands,
     /* 436347 */     // GIR_Coverage, 9075,
     /* 436347 */     GIR_Done,
     /* 436348 */   // Label 8722: @436348
     /* 436348 */   GIM_Reject,
     /* 436349 */ // Label 8720: @436349
     /* 436349 */ GIM_Reject,
     /* 436350 */ // Label 8690: @436350
     /* 436350 */ GIM_Try, /*On fail goto*//*Label 8723*/ GIMT_Encode4(436375), // Rule ID 9091 //
     /* 436355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436358 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 436361 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 436364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 436368 */   // (AArch64trn2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (TRN2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 436368 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
     /* 436373 */   GIR_RootConstrainSelectedInstOperands,
     /* 436374 */   // GIR_Coverage, 9091,
     /* 436374 */   GIR_Done,
     /* 436375 */ // Label 8723: @436375
     /* 436375 */ GIM_Reject,
     /* 436376 */ // Label 8691: @436376
     /* 436376 */ GIM_Try, /*On fail goto*//*Label 8724*/ GIMT_Encode4(436422),
     /* 436381 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 436384 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 436387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436391 */   GIM_Try, /*On fail goto*//*Label 8725*/ GIMT_Encode4(436406), // Rule ID 9070 //
     /* 436396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436399 */     // (AArch64trn2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 436399 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
     /* 436404 */     GIR_RootConstrainSelectedInstOperands,
     /* 436405 */     // GIR_Coverage, 9070,
     /* 436405 */     GIR_Done,
     /* 436406 */   // Label 8725: @436406
     /* 436406 */   GIM_Try, /*On fail goto*//*Label 8726*/ GIMT_Encode4(436421), // Rule ID 9073 //
     /* 436411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436414 */     // (AArch64trn2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 436414 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
     /* 436419 */     GIR_RootConstrainSelectedInstOperands,
     /* 436420 */     // GIR_Coverage, 9073,
     /* 436420 */     GIR_Done,
     /* 436421 */   // Label 8726: @436421
     /* 436421 */   GIM_Reject,
     /* 436422 */ // Label 8724: @436422
     /* 436422 */ GIM_Reject,
     /* 436423 */ // Label 8692: @436423
     /* 436423 */ GIM_Try, /*On fail goto*//*Label 8727*/ GIMT_Encode4(436448), // Rule ID 2422 //
     /* 436428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436431 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 436434 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 436437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 436441 */   // (AArch64trn2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 436441 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_B),
     /* 436446 */   GIR_RootConstrainSelectedInstOperands,
     /* 436447 */   // GIR_Coverage, 2422,
     /* 436447 */   GIR_Done,
     /* 436448 */ // Label 8727: @436448
     /* 436448 */ GIM_Reject,
     /* 436449 */ // Label 8693: @436449
     /* 436449 */ GIM_Try, /*On fail goto*//*Label 8728*/ GIMT_Encode4(436474), // Rule ID 9069 //
     /* 436454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 436457 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 436460 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 436463 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 436467 */   // (AArch64trn2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 436467 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_B),
     /* 436472 */   GIR_RootConstrainSelectedInstOperands,
     /* 436473 */   // GIR_Coverage, 9069,
     /* 436473 */   GIR_Done,
     /* 436474 */ // Label 8728: @436474
     /* 436474 */ GIM_Reject,
     /* 436475 */ // Label 8694: @436475
     /* 436475 */ GIM_Reject,
     /* 436476 */ // Label 144: @436476
     /* 436476 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 8735*/ GIMT_Encode4(436681),
     /* 436487 */ /*GILLT_s64*//*Label 8729*/ GIMT_Encode4(436519), GIMT_Encode4(0),
     /* 436495 */ /*GILLT_v2s32*//*Label 8730*/ GIMT_Encode4(436546),
     /* 436499 */ /*GILLT_v2s64*//*Label 8731*/ GIMT_Encode4(436573),
     /* 436503 */ /*GILLT_v4s16*//*Label 8732*/ GIMT_Encode4(436600),
     /* 436507 */ /*GILLT_v4s32*//*Label 8733*/ GIMT_Encode4(436627), GIMT_Encode4(0),
     /* 436515 */ /*GILLT_v8s16*//*Label 8734*/ GIMT_Encode4(436654),
     /* 436519 */ // Label 8729: @436519
     /* 436519 */ GIM_Try, /*On fail goto*//*Label 8736*/ GIMT_Encode4(436545), // Rule ID 1073 //
     /* 436524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436527 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 436530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436534 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436538 */   // (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)  =>  (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 436538 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 436543 */   GIR_RootConstrainSelectedInstOperands,
     /* 436544 */   // GIR_Coverage, 1073,
     /* 436544 */   GIR_Done,
     /* 436545 */ // Label 8736: @436545
     /* 436545 */ GIM_Reject,
     /* 436546 */ // Label 8730: @436546
     /* 436546 */ GIM_Try, /*On fail goto*//*Label 8737*/ GIMT_Encode4(436572), // Rule ID 1069 //
     /* 436551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 436557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436565 */   // (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)  =>  (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 436565 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
     /* 436570 */   GIR_RootConstrainSelectedInstOperands,
     /* 436571 */   // GIR_Coverage, 1069,
     /* 436571 */   GIR_Done,
     /* 436572 */ // Label 8737: @436572
     /* 436572 */ GIM_Reject,
     /* 436573 */ // Label 8731: @436573
     /* 436573 */ GIM_Try, /*On fail goto*//*Label 8738*/ GIMT_Encode4(436599), // Rule ID 1075 //
     /* 436578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436581 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436588 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436592 */   // (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 436592 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
     /* 436597 */   GIR_RootConstrainSelectedInstOperands,
     /* 436598 */   // GIR_Coverage, 1075,
     /* 436598 */   GIR_Done,
     /* 436599 */ // Label 8738: @436599
     /* 436599 */ GIM_Reject,
     /* 436600 */ // Label 8732: @436600
     /* 436600 */ GIM_Try, /*On fail goto*//*Label 8739*/ GIMT_Encode4(436626), // Rule ID 1065 //
     /* 436605 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436608 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 436611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436615 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436619 */   // (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)  =>  (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 436619 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
     /* 436624 */   GIR_RootConstrainSelectedInstOperands,
     /* 436625 */   // GIR_Coverage, 1065,
     /* 436625 */   GIR_Done,
     /* 436626 */ // Label 8739: @436626
     /* 436626 */ GIM_Reject,
     /* 436627 */ // Label 8733: @436627
     /* 436627 */ GIM_Try, /*On fail goto*//*Label 8740*/ GIMT_Encode4(436653), // Rule ID 1071 //
     /* 436632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436635 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 436638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436642 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436646 */   // (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 436646 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
     /* 436651 */   GIR_RootConstrainSelectedInstOperands,
     /* 436652 */   // GIR_Coverage, 1071,
     /* 436652 */   GIR_Done,
     /* 436653 */ // Label 8740: @436653
     /* 436653 */ GIM_Reject,
     /* 436654 */ // Label 8734: @436654
     /* 436654 */ GIM_Try, /*On fail goto*//*Label 8741*/ GIMT_Encode4(436680), // Rule ID 1067 //
     /* 436659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436662 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 436665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436669 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436673 */   // (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)  =>  (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 436673 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
     /* 436678 */   GIR_RootConstrainSelectedInstOperands,
     /* 436679 */   // GIR_Coverage, 1067,
     /* 436679 */   GIR_Done,
     /* 436680 */ // Label 8741: @436680
     /* 436680 */ GIM_Reject,
     /* 436681 */ // Label 8735: @436681
     /* 436681 */ GIM_Reject,
     /* 436682 */ // Label 145: @436682
     /* 436682 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 8744*/ GIMT_Encode4(437548),
     /* 436693 */ /*GILLT_v2s64*//*Label 8742*/ GIMT_Encode4(436705), GIMT_Encode4(0),
     /* 436701 */ /*GILLT_v4s32*//*Label 8743*/ GIMT_Encode4(436999),
     /* 436705 */ // Label 8742: @436705
     /* 436705 */ GIM_Try, /*On fail goto*//*Label 8745*/ GIMT_Encode4(436787), // Rule ID 5930 //
     /* 436710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436717 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436721 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 436725 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 436728 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 436733 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 436737 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436742 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 436744 */   // (AArch64uaddlv:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v4i32] } 735:{ *:[iPTR] }, V128:{ *:[v8i16] }:$op))  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
     /* 436744 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436747 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 436751 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436756 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 436760 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 436762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 436765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436767 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 436770 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 436776 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436781 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436786 */   // GIR_Coverage, 5930,
     /* 436786 */   GIR_EraseRootFromParent_Done,
     /* 436787 */ // Label 8745: @436787
     /* 436787 */ GIM_Try, /*On fail goto*//*Label 8746*/ GIMT_Encode4(436861), // Rule ID 5929 //
     /* 436792 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436799 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436803 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 436807 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 436811 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436816 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 436818 */   // (AArch64uaddlv:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$op))  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
     /* 436818 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436821 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 436825 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436830 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 436834 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 436836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 436839 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 436844 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436847 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 436850 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436855 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436860 */   // GIR_Coverage, 5929,
     /* 436860 */   GIR_EraseRootFromParent_Done,
     /* 436861 */ // Label 8746: @436861
     /* 436861 */ GIM_Try, /*On fail goto*//*Label 8747*/ GIMT_Encode4(436920), // Rule ID 5939 //
     /* 436866 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436873 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436877 */   // (AArch64uaddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 436877 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 436880 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 436884 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436889 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 436893 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 436895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 436898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436900 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 436903 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 436909 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436914 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436919 */   // GIR_Coverage, 5939,
     /* 436919 */   GIR_EraseRootFromParent_Done,
     /* 436920 */ // Label 8747: @436920
     /* 436920 */ GIM_Try, /*On fail goto*//*Label 8748*/ GIMT_Encode4(436998), // Rule ID 6067 //
     /* 436925 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 436928 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436932 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436936 */   // (AArch64uaddlv:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (UADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 436936 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 436939 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 436943 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436948 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 436952 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 436954 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 436957 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 436961 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436966 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 436968 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 436971 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436973 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436976 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 436979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 436982 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436987 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436992 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 436997 */   // GIR_Coverage, 6067,
     /* 436997 */   GIR_EraseRootFromParent_Done,
     /* 436998 */ // Label 8748: @436998
     /* 436998 */ GIM_Reject,
     /* 436999 */ // Label 8743: @436999
     /* 436999 */ GIM_Try, /*On fail goto*//*Label 8749*/ GIMT_Encode4(437081), // Rule ID 5932 //
     /* 437004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 437007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437011 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437015 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 437019 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 437022 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 437027 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 437031 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437036 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437038 */   // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v8i16] } 735:{ *:[iPTR] }, V128:{ *:[v16i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
     /* 437038 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437041 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 437045 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437050 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 437054 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437056 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437059 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437061 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437064 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437070 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437075 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437080 */   // GIR_Coverage, 5932,
     /* 437080 */   GIR_EraseRootFromParent_Done,
     /* 437081 */ // Label 8749: @437081
     /* 437081 */ GIM_Try, /*On fail goto*//*Label 8750*/ GIMT_Encode4(437163), // Rule ID 5934 //
     /* 437086 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 437089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437093 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437097 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 437101 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 437104 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 437109 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 437113 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437118 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437120 */   // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 735:{ *:[iPTR] }, V64:{ *:[v8i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
     /* 437120 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437123 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 437127 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437132 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 437136 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437141 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437146 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437152 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437157 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437162 */   // GIR_Coverage, 5934,
     /* 437162 */   GIR_EraseRootFromParent_Done,
     /* 437163 */ // Label 8750: @437163
     /* 437163 */ GIM_Try, /*On fail goto*//*Label 8751*/ GIMT_Encode4(437237), // Rule ID 5931 //
     /* 437168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 437171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437175 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437179 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 437183 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 437187 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437192 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437194 */   // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
     /* 437194 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437197 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 437201 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437206 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 437210 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437215 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437217 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437220 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437223 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437226 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437231 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437236 */   // GIR_Coverage, 5931,
     /* 437236 */   GIR_EraseRootFromParent_Done,
     /* 437237 */ // Label 8751: @437237
     /* 437237 */ GIM_Try, /*On fail goto*//*Label 8752*/ GIMT_Encode4(437311), // Rule ID 5933 //
     /* 437242 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 437245 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437249 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437253 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 437257 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 437261 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437266 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437268 */   // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
     /* 437268 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437271 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 437275 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437280 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 437284 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437291 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437294 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437300 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437305 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437310 */   // GIR_Coverage, 5933,
     /* 437310 */   GIR_EraseRootFromParent_Done,
     /* 437311 */ // Label 8752: @437311
     /* 437311 */ GIM_Try, /*On fail goto*//*Label 8753*/ GIMT_Encode4(437370), // Rule ID 5935 //
     /* 437316 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 437319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437323 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437327 */   // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
     /* 437327 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437330 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 437334 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437339 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 437343 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437348 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437350 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437353 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437359 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437364 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437369 */   // GIR_Coverage, 5935,
     /* 437369 */   GIR_EraseRootFromParent_Done,
     /* 437370 */ // Label 8753: @437370
     /* 437370 */ GIM_Try, /*On fail goto*//*Label 8754*/ GIMT_Encode4(437429), // Rule ID 5936 //
     /* 437375 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 437378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437382 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437386 */   // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
     /* 437386 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 437389 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 437393 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437398 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 437402 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437407 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437412 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 437418 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437423 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437428 */   // GIR_Coverage, 5936,
     /* 437428 */   GIR_EraseRootFromParent_Done,
     /* 437429 */ // Label 8754: @437429
     /* 437429 */ GIM_Try, /*On fail goto*//*Label 8755*/ GIMT_Encode4(437488), // Rule ID 5937 //
     /* 437434 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 437437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437441 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437445 */   // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
     /* 437445 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 437448 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 437452 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437457 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 437461 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437471 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437474 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 437477 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437482 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437487 */   // GIR_Coverage, 5937,
     /* 437487 */   GIR_EraseRootFromParent_Done,
     /* 437488 */ // Label 8755: @437488
     /* 437488 */ GIM_Try, /*On fail goto*//*Label 8756*/ GIMT_Encode4(437547), // Rule ID 5938 //
     /* 437493 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 437496 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437500 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437504 */   // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
     /* 437504 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 437507 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 437511 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437516 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 437520 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 437522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 437525 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 437530 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437533 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 437536 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437541 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437546 */   // GIR_Coverage, 5938,
     /* 437546 */   GIR_EraseRootFromParent_Done,
     /* 437547 */ // Label 8756: @437547
     /* 437547 */ GIM_Reject,
     /* 437548 */ // Label 8744: @437548
     /* 437548 */ GIM_Reject,
     /* 437549 */ // Label 146: @437549
     /* 437549 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 8761*/ GIMT_Encode4(437918),
     /* 437560 */ /*GILLT_v2s32*//*Label 8757*/ GIMT_Encode4(437620), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 437572 */ /*GILLT_v4s32*//*Label 8758*/ GIMT_Encode4(437740), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 437604 */ /*GILLT_nxv2s64*//*Label 8759*/ GIMT_Encode4(437860), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 437616 */ /*GILLT_nxv4s32*//*Label 8760*/ GIMT_Encode4(437889),
     /* 437620 */ // Label 8757: @437620
     /* 437620 */ GIM_Try, /*On fail goto*//*Label 8762*/ GIMT_Encode4(437739),
     /* 437625 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 437628 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 437631 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 437634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437638 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437642 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437646 */   GIM_Try, /*On fail goto*//*Label 8763*/ GIMT_Encode4(437719), // Rule ID 28 //
     /* 437651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 437654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 437658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 437662 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 437666 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 437670 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 437674 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437678 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437682 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437687 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 437691 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437695 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437699 */     // MIs[3] Operand 1
     /* 437699 */     // No operand predicates
     /* 437699 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437701 */     // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 437701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev8i8),
     /* 437704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437706 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 437708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 437710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437714 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437717 */     GIR_RootConstrainSelectedInstOperands,
     /* 437718 */     // GIR_Coverage, 28,
     /* 437718 */     GIR_EraseRootFromParent_Done,
     /* 437719 */   // Label 8763: @437719
     /* 437719 */   GIM_Try, /*On fail goto*//*Label 8764*/ GIMT_Encode4(437738), // Rule ID 24 //
     /* 437724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 437727 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437731 */     // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 437731 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv8i8),
     /* 437736 */     GIR_RootConstrainSelectedInstOperands,
     /* 437737 */     // GIR_Coverage, 24,
     /* 437737 */     GIR_Done,
     /* 437738 */   // Label 8764: @437738
     /* 437738 */   GIM_Reject,
     /* 437739 */ // Label 8762: @437739
     /* 437739 */ GIM_Reject,
     /* 437740 */ // Label 8758: @437740
     /* 437740 */ GIM_Try, /*On fail goto*//*Label 8765*/ GIMT_Encode4(437859),
     /* 437745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437748 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 437751 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 437754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437758 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437762 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437766 */   GIM_Try, /*On fail goto*//*Label 8766*/ GIMT_Encode4(437839), // Rule ID 29 //
     /* 437771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 437774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 437778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 437782 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 437790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 437794 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437798 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437802 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437807 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 437811 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437815 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437819 */     // MIs[3] Operand 1
     /* 437819 */     // No operand predicates
     /* 437819 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437821 */     // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 437821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev16i8),
     /* 437824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437826 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 437828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 437830 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437834 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437837 */     GIR_RootConstrainSelectedInstOperands,
     /* 437838 */     // GIR_Coverage, 29,
     /* 437838 */     GIR_EraseRootFromParent_Done,
     /* 437839 */   // Label 8766: @437839
     /* 437839 */   GIM_Try, /*On fail goto*//*Label 8767*/ GIMT_Encode4(437858), // Rule ID 25 //
     /* 437844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 437847 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437851 */     // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 437851 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv16i8),
     /* 437856 */     GIR_RootConstrainSelectedInstOperands,
     /* 437857 */     // GIR_Coverage, 25,
     /* 437857 */     GIR_Done,
     /* 437858 */   // Label 8767: @437858
     /* 437858 */   GIM_Reject,
     /* 437859 */ // Label 8765: @437859
     /* 437859 */ GIM_Reject,
     /* 437860 */ // Label 8759: @437860
     /* 437860 */ GIM_Try, /*On fail goto*//*Label 8768*/ GIMT_Encode4(437888), // Rule ID 7751 //
     /* 437865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 437868 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 437871 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 437874 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 437877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 437881 */   // (AArch64udot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UDOT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 437881 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_D),
     /* 437886 */   GIR_RootConstrainSelectedInstOperands,
     /* 437887 */   // GIR_Coverage, 7751,
     /* 437887 */   GIR_Done,
     /* 437888 */ // Label 8768: @437888
     /* 437888 */ GIM_Reject,
     /* 437889 */ // Label 8760: @437889
     /* 437889 */ GIM_Try, /*On fail goto*//*Label 8769*/ GIMT_Encode4(437917), // Rule ID 7750 //
     /* 437894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 437897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 437900 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 437903 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 437906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 437910 */   // (AArch64udot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UDOT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 437910 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_S),
     /* 437915 */   GIR_RootConstrainSelectedInstOperands,
     /* 437916 */   // GIR_Coverage, 7750,
     /* 437916 */   GIR_Done,
     /* 437917 */ // Label 8769: @437917
     /* 437917 */ GIM_Reject,
     /* 437918 */ // Label 8761: @437918
     /* 437918 */ GIM_Reject,
     /* 437919 */ // Label 147: @437919
     /* 437919 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8773*/ GIMT_Encode4(438035),
     /* 437930 */ /*GILLT_s16*//*Label 8770*/ GIMT_Encode4(437942),
     /* 437934 */ /*GILLT_s32*//*Label 8771*/ GIMT_Encode4(437973),
     /* 437938 */ /*GILLT_s64*//*Label 8772*/ GIMT_Encode4(438004),
     /* 437942 */ // Label 8770: @437942
     /* 437942 */ GIM_Try, /*On fail goto*//*Label 8774*/ GIMT_Encode4(437972), // Rule ID 1673 //
     /* 437947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 437950 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 437953 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437957 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 437961 */   // (AArch64uitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (UCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 437961 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 437966 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 437970 */   GIR_RootConstrainSelectedInstOperands,
     /* 437971 */   // GIR_Coverage, 1673,
     /* 437971 */   GIR_Done,
     /* 437972 */ // Label 8774: @437972
     /* 437972 */ GIM_Reject,
     /* 437973 */ // Label 8771: @437973
     /* 437973 */ GIM_Try, /*On fail goto*//*Label 8775*/ GIMT_Encode4(438003), // Rule ID 1672 //
     /* 437978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 437981 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 437984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437988 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437992 */   // (AArch64uitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 437992 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 437997 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 438001 */   GIR_RootConstrainSelectedInstOperands,
     /* 438002 */   // GIR_Coverage, 1672,
     /* 438002 */   GIR_Done,
     /* 438003 */ // Label 8775: @438003
     /* 438003 */ GIM_Reject,
     /* 438004 */ // Label 8772: @438004
     /* 438004 */ GIM_Try, /*On fail goto*//*Label 8776*/ GIMT_Encode4(438034), // Rule ID 1671 //
     /* 438009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 438012 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 438015 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438019 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438023 */   // (AArch64uitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 438023 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 438028 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 438032 */   GIR_RootConstrainSelectedInstOperands,
     /* 438033 */   // GIR_Coverage, 1671,
     /* 438033 */   GIR_Done,
     /* 438034 */ // Label 8776: @438034
     /* 438034 */ GIM_Reject,
     /* 438035 */ // Label 8773: @438035
     /* 438035 */ GIM_Reject,
     /* 438036 */ // Label 148: @438036
     /* 438036 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 8780*/ GIMT_Encode4(439268),
     /* 438047 */ /*GILLT_v2s64*//*Label 8777*/ GIMT_Encode4(438067), GIMT_Encode4(0),
     /* 438055 */ /*GILLT_v4s32*//*Label 8778*/ GIMT_Encode4(438628), GIMT_Encode4(0),
     /* 438063 */ /*GILLT_v8s16*//*Label 8779*/ GIMT_Encode4(439189),
     /* 438067 */ // Label 8777: @438067
     /* 438067 */ GIM_Try, /*On fail goto*//*Label 8781*/ GIMT_Encode4(438627),
     /* 438072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 438075 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 438078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438082 */   GIM_Try, /*On fail goto*//*Label 8782*/ GIMT_Encode4(438174), // Rule ID 2110 //
     /* 438087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 438094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438098 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438102 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438106 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438110 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438114 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438118 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438123 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438127 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438131 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438135 */     // MIs[3] Operand 1
     /* 438135 */     // No operand predicates
     /* 438135 */     // MIs[1] Operand 2
     /* 438135 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 438146 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 438155 */     // (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (UMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_indexed),
     /* 438158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 438165 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438169 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438172 */     GIR_RootConstrainSelectedInstOperands,
     /* 438173 */     // GIR_Coverage, 2110,
     /* 438173 */     GIR_EraseRootFromParent_Done,
     /* 438174 */   // Label 8782: @438174
     /* 438174 */   GIM_Try, /*On fail goto*//*Label 8783*/ GIMT_Encode4(438266), // Rule ID 13842 //
     /* 438179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438194 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438198 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438202 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438206 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438210 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438215 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438219 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438223 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438227 */     // MIs[3] Operand 1
     /* 438227 */     // No operand predicates
     /* 438227 */     // MIs[1] Operand 2
     /* 438227 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 438238 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 438247 */     // (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (UMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_indexed),
     /* 438250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 438257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438261 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438264 */     GIR_RootConstrainSelectedInstOperands,
     /* 438265 */     // GIR_Coverage, 13842,
     /* 438265 */     GIR_EraseRootFromParent_Done,
     /* 438266 */   // Label 8783: @438266
     /* 438266 */   GIM_Try, /*On fail goto*//*Label 8784*/ GIMT_Encode4(438352), // Rule ID 13840 //
     /* 438271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438274 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438278 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438282 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438294 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438298 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438302 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438307 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438311 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438315 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438319 */     // MIs[3] Operand 1
     /* 438319 */     // No operand predicates
     /* 438319 */     // MIs[1] Operand 2
     /* 438319 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 438330 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438334 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438336 */     // (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 438339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 438343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438347 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438350 */     GIR_RootConstrainSelectedInstOperands,
     /* 438351 */     // GIR_Coverage, 13840,
     /* 438351 */     GIR_EraseRootFromParent_Done,
     /* 438352 */   // Label 8784: @438352
     /* 438352 */   GIM_Try, /*On fail goto*//*Label 8785*/ GIMT_Encode4(438438), // Rule ID 2108 //
     /* 438357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438360 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 438368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438380 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438384 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438388 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438392 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438397 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438401 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438405 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438409 */     // MIs[3] Operand 1
     /* 438409 */     // No operand predicates
     /* 438409 */     // MIs[1] Operand 2
     /* 438409 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 438420 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438422 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 438425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438427 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 438429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438433 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438436 */     GIR_RootConstrainSelectedInstOperands,
     /* 438437 */     // GIR_Coverage, 2108,
     /* 438437 */     GIR_EraseRootFromParent_Done,
     /* 438438 */   // Label 8785: @438438
     /* 438438 */   GIM_Try, /*On fail goto*//*Label 8786*/ GIMT_Encode4(438477), // Rule ID 1835 //
     /* 438443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438446 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 438453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 438460 */     // (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (UMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 438460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
     /* 438463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 438470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 438475 */     GIR_RootConstrainSelectedInstOperands,
     /* 438476 */     // GIR_Coverage, 1835,
     /* 438476 */     GIR_EraseRootFromParent_Done,
     /* 438477 */   // Label 8786: @438477
     /* 438477 */   GIM_Try, /*On fail goto*//*Label 8787*/ GIMT_Encode4(438540), // Rule ID 13841 //
     /* 438482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438497 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438501 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 438510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438514 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438518 */     // MIs[2] Operand 1
     /* 438518 */     // No operand predicates
     /* 438518 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438522 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 438524 */     // (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 438527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 438531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 438535 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 438538 */     GIR_RootConstrainSelectedInstOperands,
     /* 438539 */     // GIR_Coverage, 13841,
     /* 438539 */     GIR_EraseRootFromParent_Done,
     /* 438540 */   // Label 8787: @438540
     /* 438540 */   GIM_Try, /*On fail goto*//*Label 8788*/ GIMT_Encode4(438603), // Rule ID 2109 //
     /* 438545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438548 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438552 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 438556 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 438560 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 438564 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438568 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438573 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 438577 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438581 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 438585 */     // MIs[2] Operand 1
     /* 438585 */     // No operand predicates
     /* 438585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 438587 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 438590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438592 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 438594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 438598 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 438601 */     GIR_RootConstrainSelectedInstOperands,
     /* 438602 */     // GIR_Coverage, 2109,
     /* 438602 */     GIR_EraseRootFromParent_Done,
     /* 438603 */   // Label 8788: @438603
     /* 438603 */   GIM_Try, /*On fail goto*//*Label 8789*/ GIMT_Encode4(438626), // Rule ID 1834 //
     /* 438608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438611 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438619 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 438619 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
     /* 438624 */     GIR_RootConstrainSelectedInstOperands,
     /* 438625 */     // GIR_Coverage, 1834,
     /* 438625 */     GIR_Done,
     /* 438626 */   // Label 8789: @438626
     /* 438626 */   GIM_Reject,
     /* 438627 */ // Label 8781: @438627
     /* 438627 */ GIM_Reject,
     /* 438628 */ // Label 8778: @438628
     /* 438628 */ GIM_Try, /*On fail goto*//*Label 8790*/ GIMT_Encode4(439188),
     /* 438633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 438636 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 438639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438643 */   GIM_Try, /*On fail goto*//*Label 8791*/ GIMT_Encode4(438735), // Rule ID 2107 //
     /* 438648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 438655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438663 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438667 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 438671 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438675 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438679 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 438684 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438688 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438692 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 438696 */     // MIs[3] Operand 1
     /* 438696 */     // No operand predicates
     /* 438696 */     // MIs[1] Operand 2
     /* 438696 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 438707 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 438716 */     // (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (UMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_indexed),
     /* 438719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 438726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438730 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438733 */     GIR_RootConstrainSelectedInstOperands,
     /* 438734 */     // GIR_Coverage, 2107,
     /* 438734 */     GIR_EraseRootFromParent_Done,
     /* 438735 */   // Label 8791: @438735
     /* 438735 */   GIM_Try, /*On fail goto*//*Label 8792*/ GIMT_Encode4(438827), // Rule ID 13839 //
     /* 438740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438755 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438759 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 438763 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438767 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438771 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 438776 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438780 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438784 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 438788 */     // MIs[3] Operand 1
     /* 438788 */     // No operand predicates
     /* 438788 */     // MIs[1] Operand 2
     /* 438788 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 438799 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 438808 */     // (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (UMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_indexed),
     /* 438811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 438818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438822 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438825 */     GIR_RootConstrainSelectedInstOperands,
     /* 438826 */     // GIR_Coverage, 13839,
     /* 438826 */     GIR_EraseRootFromParent_Done,
     /* 438827 */   // Label 8792: @438827
     /* 438827 */   GIM_Try, /*On fail goto*//*Label 8793*/ GIMT_Encode4(438913), // Rule ID 13837 //
     /* 438832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438847 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438851 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 438855 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438859 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438863 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 438868 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438872 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438876 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 438880 */     // MIs[3] Operand 1
     /* 438880 */     // No operand predicates
     /* 438880 */     // MIs[1] Operand 2
     /* 438880 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 438891 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438895 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438897 */     // (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 438900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 438904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438911 */     GIR_RootConstrainSelectedInstOperands,
     /* 438912 */     // GIR_Coverage, 13837,
     /* 438912 */     GIR_EraseRootFromParent_Done,
     /* 438913 */   // Label 8793: @438913
     /* 438913 */   GIM_Try, /*On fail goto*//*Label 8794*/ GIMT_Encode4(438999), // Rule ID 2105 //
     /* 438918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438921 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 438929 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 438933 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 438945 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 438949 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438953 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 438958 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438962 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438966 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 438970 */     // MIs[3] Operand 1
     /* 438970 */     // No operand predicates
     /* 438970 */     // MIs[1] Operand 2
     /* 438970 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 438981 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438983 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 438983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 438986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438988 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 438990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438994 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438997 */     GIR_RootConstrainSelectedInstOperands,
     /* 438998 */     // GIR_Coverage, 2105,
     /* 438998 */     GIR_EraseRootFromParent_Done,
     /* 438999 */   // Label 8794: @438999
     /* 438999 */   GIM_Try, /*On fail goto*//*Label 8795*/ GIMT_Encode4(439038), // Rule ID 1833 //
     /* 439004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 439014 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 439021 */     // (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (UMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 439021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
     /* 439024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 439031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 439036 */     GIR_RootConstrainSelectedInstOperands,
     /* 439037 */     // GIR_Coverage, 1833,
     /* 439037 */     GIR_EraseRootFromParent_Done,
     /* 439038 */   // Label 8795: @439038
     /* 439038 */   GIM_Try, /*On fail goto*//*Label 8796*/ GIMT_Encode4(439101), // Rule ID 13838 //
     /* 439043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 439054 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 439058 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439062 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 439067 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 439071 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439075 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 439079 */     // MIs[2] Operand 1
     /* 439079 */     // No operand predicates
     /* 439079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439083 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439085 */     // (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 439085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 439088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439090 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 439092 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 439096 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 439099 */     GIR_RootConstrainSelectedInstOperands,
     /* 439100 */     // GIR_Coverage, 13838,
     /* 439100 */     GIR_EraseRootFromParent_Done,
     /* 439101 */   // Label 8796: @439101
     /* 439101 */   GIM_Try, /*On fail goto*//*Label 8797*/ GIMT_Encode4(439164), // Rule ID 2106 //
     /* 439106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439109 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 439117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 439121 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 439125 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439129 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 439134 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 439138 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439142 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 439146 */     // MIs[2] Operand 1
     /* 439146 */     // No operand predicates
     /* 439146 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439148 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 439148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 439151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439153 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 439155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 439159 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 439162 */     GIR_RootConstrainSelectedInstOperands,
     /* 439163 */     // GIR_Coverage, 2106,
     /* 439163 */     GIR_EraseRootFromParent_Done,
     /* 439164 */   // Label 8797: @439164
     /* 439164 */   GIM_Try, /*On fail goto*//*Label 8798*/ GIMT_Encode4(439187), // Rule ID 1832 //
     /* 439169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439172 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439176 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439180 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 439180 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
     /* 439185 */     GIR_RootConstrainSelectedInstOperands,
     /* 439186 */     // GIR_Coverage, 1832,
     /* 439186 */     GIR_Done,
     /* 439187 */   // Label 8798: @439187
     /* 439187 */   GIM_Reject,
     /* 439188 */ // Label 8790: @439188
     /* 439188 */ GIM_Reject,
     /* 439189 */ // Label 8779: @439189
     /* 439189 */ GIM_Try, /*On fail goto*//*Label 8799*/ GIMT_Encode4(439267),
     /* 439194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 439197 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 439200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439204 */   GIM_Try, /*On fail goto*//*Label 8800*/ GIMT_Encode4(439243), // Rule ID 1831 //
     /* 439209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 439219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 439226 */     // (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (UMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 439226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
     /* 439229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 439236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 439241 */     GIR_RootConstrainSelectedInstOperands,
     /* 439242 */     // GIR_Coverage, 1831,
     /* 439242 */     GIR_EraseRootFromParent_Done,
     /* 439243 */   // Label 8800: @439243
     /* 439243 */   GIM_Try, /*On fail goto*//*Label 8801*/ GIMT_Encode4(439266), // Rule ID 1830 //
     /* 439248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439251 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439259 */     // (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 439259 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
     /* 439264 */     GIR_RootConstrainSelectedInstOperands,
     /* 439265 */     // GIR_Coverage, 1830,
     /* 439265 */     GIR_Done,
     /* 439266 */   // Label 8801: @439266
     /* 439266 */   GIM_Reject,
     /* 439267 */ // Label 8799: @439267
     /* 439267 */ GIM_Reject,
     /* 439268 */ // Label 8780: @439268
     /* 439268 */ GIM_Reject,
     /* 439269 */ // Label 149: @439269
     /* 439269 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 8820*/ GIMT_Encode4(440048),
     /* 439280 */ /*GILLT_v2s32*//*Label 8802*/ GIMT_Encode4(439356),
     /* 439284 */ /*GILLT_v2s64*//*Label 8803*/ GIMT_Encode4(439411),
     /* 439288 */ /*GILLT_v4s16*//*Label 8804*/ GIMT_Encode4(439466),
     /* 439292 */ /*GILLT_v4s32*//*Label 8805*/ GIMT_Encode4(439521),
     /* 439296 */ /*GILLT_v8s8*//*Label 8806*/ GIMT_Encode4(439576),
     /* 439300 */ /*GILLT_v8s16*//*Label 8807*/ GIMT_Encode4(439610),
     /* 439304 */ /*GILLT_v16s8*//*Label 8808*/ GIMT_Encode4(439665), GIMT_Encode4(0),
     /* 439312 */ /*GILLT_nxv2s1*//*Label 8809*/ GIMT_Encode4(439699),
     /* 439316 */ /*GILLT_nxv2s16*//*Label 8810*/ GIMT_Encode4(439725),
     /* 439320 */ /*GILLT_nxv2s32*//*Label 8811*/ GIMT_Encode4(439751),
     /* 439324 */ /*GILLT_nxv2s64*//*Label 8812*/ GIMT_Encode4(439777),
     /* 439328 */ /*GILLT_nxv4s1*//*Label 8813*/ GIMT_Encode4(439824),
     /* 439332 */ /*GILLT_nxv4s16*//*Label 8814*/ GIMT_Encode4(439850),
     /* 439336 */ /*GILLT_nxv4s32*//*Label 8815*/ GIMT_Encode4(439876),
     /* 439340 */ /*GILLT_nxv8s1*//*Label 8816*/ GIMT_Encode4(439923),
     /* 439344 */ /*GILLT_nxv8s16*//*Label 8817*/ GIMT_Encode4(439949),
     /* 439348 */ /*GILLT_nxv16s1*//*Label 8818*/ GIMT_Encode4(439996),
     /* 439352 */ /*GILLT_nxv16s8*//*Label 8819*/ GIMT_Encode4(440022),
     /* 439356 */ // Label 8802: @439356
     /* 439356 */ GIM_Try, /*On fail goto*//*Label 8821*/ GIMT_Encode4(439410),
     /* 439361 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 439364 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 439367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439371 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439375 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439379 */   GIM_Try, /*On fail goto*//*Label 8822*/ GIMT_Encode4(439394), // Rule ID 1892 //
     /* 439384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439387 */     // (AArch64uzp1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UZP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 439387 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
     /* 439392 */     GIR_RootConstrainSelectedInstOperands,
     /* 439393 */     // GIR_Coverage, 1892,
     /* 439393 */     GIR_Done,
     /* 439394 */   // Label 8822: @439394
     /* 439394 */   GIM_Try, /*On fail goto*//*Label 8823*/ GIMT_Encode4(439409), // Rule ID 5522 //
     /* 439399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439402 */     // (AArch64uzp1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (UZP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 439402 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
     /* 439407 */     GIR_RootConstrainSelectedInstOperands,
     /* 439408 */     // GIR_Coverage, 5522,
     /* 439408 */     GIR_Done,
     /* 439409 */   // Label 8823: @439409
     /* 439409 */   GIM_Reject,
     /* 439410 */ // Label 8821: @439410
     /* 439410 */ GIM_Reject,
     /* 439411 */ // Label 8803: @439411
     /* 439411 */ GIM_Try, /*On fail goto*//*Label 8824*/ GIMT_Encode4(439465),
     /* 439416 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439419 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 439422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439426 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439430 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439434 */   GIM_Try, /*On fail goto*//*Label 8825*/ GIMT_Encode4(439449), // Rule ID 1894 //
     /* 439439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439442 */     // (AArch64uzp1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UZP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 439442 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
     /* 439447 */     GIR_RootConstrainSelectedInstOperands,
     /* 439448 */     // GIR_Coverage, 1894,
     /* 439448 */     GIR_Done,
     /* 439449 */   // Label 8825: @439449
     /* 439449 */   GIM_Try, /*On fail goto*//*Label 8826*/ GIMT_Encode4(439464), // Rule ID 5524 //
     /* 439454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439457 */     // (AArch64uzp1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (UZP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 439457 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
     /* 439462 */     GIR_RootConstrainSelectedInstOperands,
     /* 439463 */     // GIR_Coverage, 5524,
     /* 439463 */     GIR_Done,
     /* 439464 */   // Label 8826: @439464
     /* 439464 */   GIM_Reject,
     /* 439465 */ // Label 8824: @439465
     /* 439465 */ GIM_Reject,
     /* 439466 */ // Label 8804: @439466
     /* 439466 */ GIM_Try, /*On fail goto*//*Label 8827*/ GIMT_Encode4(439520),
     /* 439471 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 439474 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 439477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439481 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439485 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439489 */   GIM_Try, /*On fail goto*//*Label 8828*/ GIMT_Encode4(439504), // Rule ID 1890 //
     /* 439494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439497 */     // (AArch64uzp1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 439497 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 439502 */     GIR_RootConstrainSelectedInstOperands,
     /* 439503 */     // GIR_Coverage, 1890,
     /* 439503 */     GIR_Done,
     /* 439504 */   // Label 8828: @439504
     /* 439504 */   GIM_Try, /*On fail goto*//*Label 8829*/ GIMT_Encode4(439519), // Rule ID 5520 //
     /* 439509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439512 */     // (AArch64uzp1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (UZP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 439512 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 439517 */     GIR_RootConstrainSelectedInstOperands,
     /* 439518 */     // GIR_Coverage, 5520,
     /* 439518 */     GIR_Done,
     /* 439519 */   // Label 8829: @439519
     /* 439519 */   GIM_Reject,
     /* 439520 */ // Label 8827: @439520
     /* 439520 */ GIM_Reject,
     /* 439521 */ // Label 8805: @439521
     /* 439521 */ GIM_Try, /*On fail goto*//*Label 8830*/ GIMT_Encode4(439575),
     /* 439526 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 439529 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 439532 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439536 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439540 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439544 */   GIM_Try, /*On fail goto*//*Label 8831*/ GIMT_Encode4(439559), // Rule ID 1893 //
     /* 439549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439552 */     // (AArch64uzp1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 439552 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 439557 */     GIR_RootConstrainSelectedInstOperands,
     /* 439558 */     // GIR_Coverage, 1893,
     /* 439558 */     GIR_Done,
     /* 439559 */   // Label 8831: @439559
     /* 439559 */   GIM_Try, /*On fail goto*//*Label 8832*/ GIMT_Encode4(439574), // Rule ID 5523 //
     /* 439564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439567 */     // (AArch64uzp1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (UZP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 439567 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 439572 */     GIR_RootConstrainSelectedInstOperands,
     /* 439573 */     // GIR_Coverage, 5523,
     /* 439573 */     GIR_Done,
     /* 439574 */   // Label 8832: @439574
     /* 439574 */   GIM_Reject,
     /* 439575 */ // Label 8830: @439575
     /* 439575 */ GIM_Reject,
     /* 439576 */ // Label 8806: @439576
     /* 439576 */ GIM_Try, /*On fail goto*//*Label 8833*/ GIMT_Encode4(439609), // Rule ID 1888 //
     /* 439581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439584 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 439587 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 439590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439594 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439598 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439602 */   // (AArch64uzp1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 439602 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
     /* 439607 */   GIR_RootConstrainSelectedInstOperands,
     /* 439608 */   // GIR_Coverage, 1888,
     /* 439608 */   GIR_Done,
     /* 439609 */ // Label 8833: @439609
     /* 439609 */ GIM_Reject,
     /* 439610 */ // Label 8807: @439610
     /* 439610 */ GIM_Try, /*On fail goto*//*Label 8834*/ GIMT_Encode4(439664),
     /* 439615 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 439618 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 439621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439625 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439629 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439633 */   GIM_Try, /*On fail goto*//*Label 8835*/ GIMT_Encode4(439648), // Rule ID 1891 //
     /* 439638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439641 */     // (AArch64uzp1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 439641 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 439646 */     GIR_RootConstrainSelectedInstOperands,
     /* 439647 */     // GIR_Coverage, 1891,
     /* 439647 */     GIR_Done,
     /* 439648 */   // Label 8835: @439648
     /* 439648 */   GIM_Try, /*On fail goto*//*Label 8836*/ GIMT_Encode4(439663), // Rule ID 5521 //
     /* 439653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439656 */     // (AArch64uzp1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (UZP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 439656 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 439661 */     GIR_RootConstrainSelectedInstOperands,
     /* 439662 */     // GIR_Coverage, 5521,
     /* 439662 */     GIR_Done,
     /* 439663 */   // Label 8836: @439663
     /* 439663 */   GIM_Reject,
     /* 439664 */ // Label 8834: @439664
     /* 439664 */ GIM_Reject,
     /* 439665 */ // Label 8808: @439665
     /* 439665 */ GIM_Try, /*On fail goto*//*Label 8837*/ GIMT_Encode4(439698), // Rule ID 1889 //
     /* 439670 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439673 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 439676 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 439679 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439683 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439687 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439691 */   // (AArch64uzp1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 439691 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
     /* 439696 */   GIR_RootConstrainSelectedInstOperands,
     /* 439697 */   // GIR_Coverage, 1889,
     /* 439697 */   GIR_Done,
     /* 439698 */ // Label 8837: @439698
     /* 439698 */ GIM_Reject,
     /* 439699 */ // Label 8809: @439699
     /* 439699 */ GIM_Try, /*On fail goto*//*Label 8838*/ GIMT_Encode4(439724), // Rule ID 9084 //
     /* 439704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 439710 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 439713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 439717 */   // (AArch64uzp1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 439717 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 439722 */   GIR_RootConstrainSelectedInstOperands,
     /* 439723 */   // GIR_Coverage, 9084,
     /* 439723 */   GIR_Done,
     /* 439724 */ // Label 8838: @439724
     /* 439724 */ GIM_Reject,
     /* 439725 */ // Label 8810: @439725
     /* 439725 */ GIM_Try, /*On fail goto*//*Label 8839*/ GIMT_Encode4(439750), // Rule ID 9046 //
     /* 439730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439733 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 439736 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 439739 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439743 */   // (AArch64uzp1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 439743 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 439748 */   GIR_RootConstrainSelectedInstOperands,
     /* 439749 */   // GIR_Coverage, 9046,
     /* 439749 */   GIR_Done,
     /* 439750 */ // Label 8839: @439750
     /* 439750 */ GIM_Reject,
     /* 439751 */ // Label 8811: @439751
     /* 439751 */ GIM_Try, /*On fail goto*//*Label 8840*/ GIMT_Encode4(439776), // Rule ID 9047 //
     /* 439756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439759 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 439762 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 439765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439769 */   // (AArch64uzp1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 439769 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 439774 */   GIR_RootConstrainSelectedInstOperands,
     /* 439775 */   // GIR_Coverage, 9047,
     /* 439775 */   GIR_Done,
     /* 439776 */ // Label 8840: @439776
     /* 439776 */ GIM_Reject,
     /* 439777 */ // Label 8812: @439777
     /* 439777 */ GIM_Try, /*On fail goto*//*Label 8841*/ GIMT_Encode4(439823),
     /* 439782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 439785 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 439788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439792 */   GIM_Try, /*On fail goto*//*Label 8842*/ GIMT_Encode4(439807), // Rule ID 9042 //
     /* 439797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439800 */     // (AArch64uzp1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 439800 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 439805 */     GIR_RootConstrainSelectedInstOperands,
     /* 439806 */     // GIR_Coverage, 9042,
     /* 439806 */     GIR_Done,
     /* 439807 */   // Label 8842: @439807
     /* 439807 */   GIM_Try, /*On fail goto*//*Label 8843*/ GIMT_Encode4(439822), // Rule ID 9048 //
     /* 439812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439815 */     // (AArch64uzp1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 439815 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 439820 */     GIR_RootConstrainSelectedInstOperands,
     /* 439821 */     // GIR_Coverage, 9048,
     /* 439821 */     GIR_Done,
     /* 439822 */   // Label 8843: @439822
     /* 439822 */   GIM_Reject,
     /* 439823 */ // Label 8841: @439823
     /* 439823 */ GIM_Reject,
     /* 439824 */ // Label 8813: @439824
     /* 439824 */ GIM_Try, /*On fail goto*//*Label 8844*/ GIMT_Encode4(439849), // Rule ID 9083 //
     /* 439829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439832 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 439835 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 439838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 439842 */   // (AArch64uzp1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 439842 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 439847 */   GIR_RootConstrainSelectedInstOperands,
     /* 439848 */   // GIR_Coverage, 9083,
     /* 439848 */   GIR_Done,
     /* 439849 */ // Label 8844: @439849
     /* 439849 */ GIM_Reject,
     /* 439850 */ // Label 8814: @439850
     /* 439850 */ GIM_Try, /*On fail goto*//*Label 8845*/ GIMT_Encode4(439875), // Rule ID 9044 //
     /* 439855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439858 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 439861 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 439864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439868 */   // (AArch64uzp1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 439868 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 439873 */   GIR_RootConstrainSelectedInstOperands,
     /* 439874 */   // GIR_Coverage, 9044,
     /* 439874 */   GIR_Done,
     /* 439875 */ // Label 8845: @439875
     /* 439875 */ GIM_Reject,
     /* 439876 */ // Label 8815: @439876
     /* 439876 */ GIM_Try, /*On fail goto*//*Label 8846*/ GIMT_Encode4(439922),
     /* 439881 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 439884 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 439887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439891 */   GIM_Try, /*On fail goto*//*Label 8847*/ GIMT_Encode4(439906), // Rule ID 9041 //
     /* 439896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439899 */     // (AArch64uzp1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 439899 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 439904 */     GIR_RootConstrainSelectedInstOperands,
     /* 439905 */     // GIR_Coverage, 9041,
     /* 439905 */     GIR_Done,
     /* 439906 */   // Label 8847: @439906
     /* 439906 */   GIM_Try, /*On fail goto*//*Label 8848*/ GIMT_Encode4(439921), // Rule ID 9045 //
     /* 439911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439914 */     // (AArch64uzp1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 439914 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 439919 */     GIR_RootConstrainSelectedInstOperands,
     /* 439920 */     // GIR_Coverage, 9045,
     /* 439920 */     GIR_Done,
     /* 439921 */   // Label 8848: @439921
     /* 439921 */   GIM_Reject,
     /* 439922 */ // Label 8846: @439922
     /* 439922 */ GIM_Reject,
     /* 439923 */ // Label 8816: @439923
     /* 439923 */ GIM_Try, /*On fail goto*//*Label 8849*/ GIMT_Encode4(439948), // Rule ID 9082 //
     /* 439928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439931 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 439934 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 439937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 439941 */   // (AArch64uzp1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 439941 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 439946 */   GIR_RootConstrainSelectedInstOperands,
     /* 439947 */   // GIR_Coverage, 9082,
     /* 439947 */   GIR_Done,
     /* 439948 */ // Label 8849: @439948
     /* 439948 */ GIM_Reject,
     /* 439949 */ // Label 8817: @439949
     /* 439949 */ GIM_Try, /*On fail goto*//*Label 8850*/ GIMT_Encode4(439995),
     /* 439954 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 439957 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 439960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 439964 */   GIM_Try, /*On fail goto*//*Label 8851*/ GIMT_Encode4(439979), // Rule ID 9040 //
     /* 439969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439972 */     // (AArch64uzp1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 439972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 439977 */     GIR_RootConstrainSelectedInstOperands,
     /* 439978 */     // GIR_Coverage, 9040,
     /* 439978 */     GIR_Done,
     /* 439979 */   // Label 8851: @439979
     /* 439979 */   GIM_Try, /*On fail goto*//*Label 8852*/ GIMT_Encode4(439994), // Rule ID 9043 //
     /* 439984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 439987 */     // (AArch64uzp1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 439987 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 439992 */     GIR_RootConstrainSelectedInstOperands,
     /* 439993 */     // GIR_Coverage, 9043,
     /* 439993 */     GIR_Done,
     /* 439994 */   // Label 8852: @439994
     /* 439994 */   GIM_Reject,
     /* 439995 */ // Label 8850: @439995
     /* 439995 */ GIM_Reject,
     /* 439996 */ // Label 8818: @439996
     /* 439996 */ GIM_Try, /*On fail goto*//*Label 8853*/ GIMT_Encode4(440021), // Rule ID 2410 //
     /* 440001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 440007 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 440010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 440014 */   // (AArch64uzp1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 440014 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
     /* 440019 */   GIR_RootConstrainSelectedInstOperands,
     /* 440020 */   // GIR_Coverage, 2410,
     /* 440020 */   GIR_Done,
     /* 440021 */ // Label 8853: @440021
     /* 440021 */ GIM_Reject,
     /* 440022 */ // Label 8819: @440022
     /* 440022 */ GIM_Try, /*On fail goto*//*Label 8854*/ GIMT_Encode4(440047), // Rule ID 9039 //
     /* 440027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440030 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 440033 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 440036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440040 */   // (AArch64uzp1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 440040 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_B),
     /* 440045 */   GIR_RootConstrainSelectedInstOperands,
     /* 440046 */   // GIR_Coverage, 9039,
     /* 440046 */   GIR_Done,
     /* 440047 */ // Label 8854: @440047
     /* 440047 */ GIM_Reject,
     /* 440048 */ // Label 8820: @440048
     /* 440048 */ GIM_Reject,
     /* 440049 */ // Label 150: @440049
     /* 440049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 8873*/ GIMT_Encode4(440828),
     /* 440060 */ /*GILLT_v2s32*//*Label 8855*/ GIMT_Encode4(440136),
     /* 440064 */ /*GILLT_v2s64*//*Label 8856*/ GIMT_Encode4(440191),
     /* 440068 */ /*GILLT_v4s16*//*Label 8857*/ GIMT_Encode4(440246),
     /* 440072 */ /*GILLT_v4s32*//*Label 8858*/ GIMT_Encode4(440301),
     /* 440076 */ /*GILLT_v8s8*//*Label 8859*/ GIMT_Encode4(440356),
     /* 440080 */ /*GILLT_v8s16*//*Label 8860*/ GIMT_Encode4(440390),
     /* 440084 */ /*GILLT_v16s8*//*Label 8861*/ GIMT_Encode4(440445), GIMT_Encode4(0),
     /* 440092 */ /*GILLT_nxv2s1*//*Label 8862*/ GIMT_Encode4(440479),
     /* 440096 */ /*GILLT_nxv2s16*//*Label 8863*/ GIMT_Encode4(440505),
     /* 440100 */ /*GILLT_nxv2s32*//*Label 8864*/ GIMT_Encode4(440531),
     /* 440104 */ /*GILLT_nxv2s64*//*Label 8865*/ GIMT_Encode4(440557),
     /* 440108 */ /*GILLT_nxv4s1*//*Label 8866*/ GIMT_Encode4(440604),
     /* 440112 */ /*GILLT_nxv4s16*//*Label 8867*/ GIMT_Encode4(440630),
     /* 440116 */ /*GILLT_nxv4s32*//*Label 8868*/ GIMT_Encode4(440656),
     /* 440120 */ /*GILLT_nxv8s1*//*Label 8869*/ GIMT_Encode4(440703),
     /* 440124 */ /*GILLT_nxv8s16*//*Label 8870*/ GIMT_Encode4(440729),
     /* 440128 */ /*GILLT_nxv16s1*//*Label 8871*/ GIMT_Encode4(440776),
     /* 440132 */ /*GILLT_nxv16s8*//*Label 8872*/ GIMT_Encode4(440802),
     /* 440136 */ // Label 8855: @440136
     /* 440136 */ GIM_Try, /*On fail goto*//*Label 8874*/ GIMT_Encode4(440190),
     /* 440141 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 440144 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 440147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440151 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440155 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440159 */   GIM_Try, /*On fail goto*//*Label 8875*/ GIMT_Encode4(440174), // Rule ID 1899 //
     /* 440164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440167 */     // (AArch64uzp2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UZP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 440167 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
     /* 440172 */     GIR_RootConstrainSelectedInstOperands,
     /* 440173 */     // GIR_Coverage, 1899,
     /* 440173 */     GIR_Done,
     /* 440174 */   // Label 8875: @440174
     /* 440174 */   GIM_Try, /*On fail goto*//*Label 8876*/ GIMT_Encode4(440189), // Rule ID 5527 //
     /* 440179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440182 */     // (AArch64uzp2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (UZP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 440182 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
     /* 440187 */     GIR_RootConstrainSelectedInstOperands,
     /* 440188 */     // GIR_Coverage, 5527,
     /* 440188 */     GIR_Done,
     /* 440189 */   // Label 8876: @440189
     /* 440189 */   GIM_Reject,
     /* 440190 */ // Label 8874: @440190
     /* 440190 */ GIM_Reject,
     /* 440191 */ // Label 8856: @440191
     /* 440191 */ GIM_Try, /*On fail goto*//*Label 8877*/ GIMT_Encode4(440245),
     /* 440196 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440199 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 440202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440206 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440210 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440214 */   GIM_Try, /*On fail goto*//*Label 8878*/ GIMT_Encode4(440229), // Rule ID 1901 //
     /* 440219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440222 */     // (AArch64uzp2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UZP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 440222 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
     /* 440227 */     GIR_RootConstrainSelectedInstOperands,
     /* 440228 */     // GIR_Coverage, 1901,
     /* 440228 */     GIR_Done,
     /* 440229 */   // Label 8878: @440229
     /* 440229 */   GIM_Try, /*On fail goto*//*Label 8879*/ GIMT_Encode4(440244), // Rule ID 5529 //
     /* 440234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440237 */     // (AArch64uzp2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (UZP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 440237 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
     /* 440242 */     GIR_RootConstrainSelectedInstOperands,
     /* 440243 */     // GIR_Coverage, 5529,
     /* 440243 */     GIR_Done,
     /* 440244 */   // Label 8879: @440244
     /* 440244 */   GIM_Reject,
     /* 440245 */ // Label 8877: @440245
     /* 440245 */ GIM_Reject,
     /* 440246 */ // Label 8857: @440246
     /* 440246 */ GIM_Try, /*On fail goto*//*Label 8880*/ GIMT_Encode4(440300),
     /* 440251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 440254 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 440257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440261 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440265 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440269 */   GIM_Try, /*On fail goto*//*Label 8881*/ GIMT_Encode4(440284), // Rule ID 1897 //
     /* 440274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440277 */     // (AArch64uzp2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UZP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 440277 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
     /* 440282 */     GIR_RootConstrainSelectedInstOperands,
     /* 440283 */     // GIR_Coverage, 1897,
     /* 440283 */     GIR_Done,
     /* 440284 */   // Label 8881: @440284
     /* 440284 */   GIM_Try, /*On fail goto*//*Label 8882*/ GIMT_Encode4(440299), // Rule ID 5525 //
     /* 440289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440292 */     // (AArch64uzp2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (UZP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 440292 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
     /* 440297 */     GIR_RootConstrainSelectedInstOperands,
     /* 440298 */     // GIR_Coverage, 5525,
     /* 440298 */     GIR_Done,
     /* 440299 */   // Label 8882: @440299
     /* 440299 */   GIM_Reject,
     /* 440300 */ // Label 8880: @440300
     /* 440300 */ GIM_Reject,
     /* 440301 */ // Label 8858: @440301
     /* 440301 */ GIM_Try, /*On fail goto*//*Label 8883*/ GIMT_Encode4(440355),
     /* 440306 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 440309 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 440312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440316 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440320 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440324 */   GIM_Try, /*On fail goto*//*Label 8884*/ GIMT_Encode4(440339), // Rule ID 1900 //
     /* 440329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440332 */     // (AArch64uzp2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 440332 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 440337 */     GIR_RootConstrainSelectedInstOperands,
     /* 440338 */     // GIR_Coverage, 1900,
     /* 440338 */     GIR_Done,
     /* 440339 */   // Label 8884: @440339
     /* 440339 */   GIM_Try, /*On fail goto*//*Label 8885*/ GIMT_Encode4(440354), // Rule ID 5528 //
     /* 440344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440347 */     // (AArch64uzp2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 440347 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 440352 */     GIR_RootConstrainSelectedInstOperands,
     /* 440353 */     // GIR_Coverage, 5528,
     /* 440353 */     GIR_Done,
     /* 440354 */   // Label 8885: @440354
     /* 440354 */   GIM_Reject,
     /* 440355 */ // Label 8883: @440355
     /* 440355 */ GIM_Reject,
     /* 440356 */ // Label 8859: @440356
     /* 440356 */ GIM_Try, /*On fail goto*//*Label 8886*/ GIMT_Encode4(440389), // Rule ID 1895 //
     /* 440361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 440367 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 440370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440378 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440382 */   // (AArch64uzp2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UZP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 440382 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i8),
     /* 440387 */   GIR_RootConstrainSelectedInstOperands,
     /* 440388 */   // GIR_Coverage, 1895,
     /* 440388 */   GIR_Done,
     /* 440389 */ // Label 8886: @440389
     /* 440389 */ GIM_Reject,
     /* 440390 */ // Label 8860: @440390
     /* 440390 */ GIM_Try, /*On fail goto*//*Label 8887*/ GIMT_Encode4(440444),
     /* 440395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 440398 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 440401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440409 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440413 */   GIM_Try, /*On fail goto*//*Label 8888*/ GIMT_Encode4(440428), // Rule ID 1898 //
     /* 440418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440421 */     // (AArch64uzp2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 440421 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 440426 */     GIR_RootConstrainSelectedInstOperands,
     /* 440427 */     // GIR_Coverage, 1898,
     /* 440427 */     GIR_Done,
     /* 440428 */   // Label 8888: @440428
     /* 440428 */   GIM_Try, /*On fail goto*//*Label 8889*/ GIMT_Encode4(440443), // Rule ID 5526 //
     /* 440433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440436 */     // (AArch64uzp2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 440436 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 440441 */     GIR_RootConstrainSelectedInstOperands,
     /* 440442 */     // GIR_Coverage, 5526,
     /* 440442 */     GIR_Done,
     /* 440443 */   // Label 8889: @440443
     /* 440443 */   GIM_Reject,
     /* 440444 */ // Label 8887: @440444
     /* 440444 */ GIM_Reject,
     /* 440445 */ // Label 8861: @440445
     /* 440445 */ GIM_Try, /*On fail goto*//*Label 8890*/ GIMT_Encode4(440478), // Rule ID 1896 //
     /* 440450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440453 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 440456 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 440459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440463 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440467 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440471 */   // (AArch64uzp2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 440471 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 440476 */   GIR_RootConstrainSelectedInstOperands,
     /* 440477 */   // GIR_Coverage, 1896,
     /* 440477 */   GIR_Done,
     /* 440478 */ // Label 8890: @440478
     /* 440478 */ GIM_Reject,
     /* 440479 */ // Label 8862: @440479
     /* 440479 */ GIM_Try, /*On fail goto*//*Label 8891*/ GIMT_Encode4(440504), // Rule ID 9087 //
     /* 440484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440487 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 440490 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 440493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 440497 */   // (AArch64uzp2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UZP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 440497 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
     /* 440502 */   GIR_RootConstrainSelectedInstOperands,
     /* 440503 */   // GIR_Coverage, 9087,
     /* 440503 */   GIR_Done,
     /* 440504 */ // Label 8891: @440504
     /* 440504 */ GIM_Reject,
     /* 440505 */ // Label 8863: @440505
     /* 440505 */ GIM_Try, /*On fail goto*//*Label 8892*/ GIMT_Encode4(440530), // Rule ID 9056 //
     /* 440510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 440516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 440519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440523 */   // (AArch64uzp2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 440523 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 440528 */   GIR_RootConstrainSelectedInstOperands,
     /* 440529 */   // GIR_Coverage, 9056,
     /* 440529 */   GIR_Done,
     /* 440530 */ // Label 8892: @440530
     /* 440530 */ GIM_Reject,
     /* 440531 */ // Label 8864: @440531
     /* 440531 */ GIM_Try, /*On fail goto*//*Label 8893*/ GIMT_Encode4(440556), // Rule ID 9057 //
     /* 440536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 440542 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 440545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440549 */   // (AArch64uzp2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 440549 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 440554 */   GIR_RootConstrainSelectedInstOperands,
     /* 440555 */   // GIR_Coverage, 9057,
     /* 440555 */   GIR_Done,
     /* 440556 */ // Label 8893: @440556
     /* 440556 */ GIM_Reject,
     /* 440557 */ // Label 8865: @440557
     /* 440557 */ GIM_Try, /*On fail goto*//*Label 8894*/ GIMT_Encode4(440603),
     /* 440562 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 440565 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 440568 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440572 */   GIM_Try, /*On fail goto*//*Label 8895*/ GIMT_Encode4(440587), // Rule ID 9052 //
     /* 440577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440580 */     // (AArch64uzp2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 440580 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 440585 */     GIR_RootConstrainSelectedInstOperands,
     /* 440586 */     // GIR_Coverage, 9052,
     /* 440586 */     GIR_Done,
     /* 440587 */   // Label 8895: @440587
     /* 440587 */   GIM_Try, /*On fail goto*//*Label 8896*/ GIMT_Encode4(440602), // Rule ID 9058 //
     /* 440592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440595 */     // (AArch64uzp2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 440595 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 440600 */     GIR_RootConstrainSelectedInstOperands,
     /* 440601 */     // GIR_Coverage, 9058,
     /* 440601 */     GIR_Done,
     /* 440602 */   // Label 8896: @440602
     /* 440602 */   GIM_Reject,
     /* 440603 */ // Label 8894: @440603
     /* 440603 */ GIM_Reject,
     /* 440604 */ // Label 8866: @440604
     /* 440604 */ GIM_Try, /*On fail goto*//*Label 8897*/ GIMT_Encode4(440629), // Rule ID 9086 //
     /* 440609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440612 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 440615 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 440618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 440622 */   // (AArch64uzp2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UZP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 440622 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
     /* 440627 */   GIR_RootConstrainSelectedInstOperands,
     /* 440628 */   // GIR_Coverage, 9086,
     /* 440628 */   GIR_Done,
     /* 440629 */ // Label 8897: @440629
     /* 440629 */ GIM_Reject,
     /* 440630 */ // Label 8867: @440630
     /* 440630 */ GIM_Try, /*On fail goto*//*Label 8898*/ GIMT_Encode4(440655), // Rule ID 9054 //
     /* 440635 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440638 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 440641 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 440644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440648 */   // (AArch64uzp2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 440648 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 440653 */   GIR_RootConstrainSelectedInstOperands,
     /* 440654 */   // GIR_Coverage, 9054,
     /* 440654 */   GIR_Done,
     /* 440655 */ // Label 8898: @440655
     /* 440655 */ GIM_Reject,
     /* 440656 */ // Label 8868: @440656
     /* 440656 */ GIM_Try, /*On fail goto*//*Label 8899*/ GIMT_Encode4(440702),
     /* 440661 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 440664 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 440667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440671 */   GIM_Try, /*On fail goto*//*Label 8900*/ GIMT_Encode4(440686), // Rule ID 9051 //
     /* 440676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440679 */     // (AArch64uzp2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 440679 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 440684 */     GIR_RootConstrainSelectedInstOperands,
     /* 440685 */     // GIR_Coverage, 9051,
     /* 440685 */     GIR_Done,
     /* 440686 */   // Label 8900: @440686
     /* 440686 */   GIM_Try, /*On fail goto*//*Label 8901*/ GIMT_Encode4(440701), // Rule ID 9055 //
     /* 440691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440694 */     // (AArch64uzp2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 440694 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 440699 */     GIR_RootConstrainSelectedInstOperands,
     /* 440700 */     // GIR_Coverage, 9055,
     /* 440700 */     GIR_Done,
     /* 440701 */   // Label 8901: @440701
     /* 440701 */   GIM_Reject,
     /* 440702 */ // Label 8899: @440702
     /* 440702 */ GIM_Reject,
     /* 440703 */ // Label 8869: @440703
     /* 440703 */ GIM_Try, /*On fail goto*//*Label 8902*/ GIMT_Encode4(440728), // Rule ID 9085 //
     /* 440708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 440714 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 440717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 440721 */   // (AArch64uzp2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UZP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 440721 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
     /* 440726 */   GIR_RootConstrainSelectedInstOperands,
     /* 440727 */   // GIR_Coverage, 9085,
     /* 440727 */   GIR_Done,
     /* 440728 */ // Label 8902: @440728
     /* 440728 */ GIM_Reject,
     /* 440729 */ // Label 8870: @440729
     /* 440729 */ GIM_Try, /*On fail goto*//*Label 8903*/ GIMT_Encode4(440775),
     /* 440734 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 440737 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 440740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440744 */   GIM_Try, /*On fail goto*//*Label 8904*/ GIMT_Encode4(440759), // Rule ID 9050 //
     /* 440749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440752 */     // (AArch64uzp2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 440752 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
     /* 440757 */     GIR_RootConstrainSelectedInstOperands,
     /* 440758 */     // GIR_Coverage, 9050,
     /* 440758 */     GIR_Done,
     /* 440759 */   // Label 8904: @440759
     /* 440759 */   GIM_Try, /*On fail goto*//*Label 8905*/ GIMT_Encode4(440774), // Rule ID 9053 //
     /* 440764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440767 */     // (AArch64uzp2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 440767 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
     /* 440772 */     GIR_RootConstrainSelectedInstOperands,
     /* 440773 */     // GIR_Coverage, 9053,
     /* 440773 */     GIR_Done,
     /* 440774 */   // Label 8905: @440774
     /* 440774 */   GIM_Reject,
     /* 440775 */ // Label 8903: @440775
     /* 440775 */ GIM_Reject,
     /* 440776 */ // Label 8871: @440776
     /* 440776 */ GIM_Try, /*On fail goto*//*Label 8906*/ GIMT_Encode4(440801), // Rule ID 2414 //
     /* 440781 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440784 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 440787 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 440790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 440794 */   // (AArch64uzp2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 440794 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_B),
     /* 440799 */   GIR_RootConstrainSelectedInstOperands,
     /* 440800 */   // GIR_Coverage, 2414,
     /* 440800 */   GIR_Done,
     /* 440801 */ // Label 8906: @440801
     /* 440801 */ GIM_Reject,
     /* 440802 */ // Label 8872: @440802
     /* 440802 */ GIM_Try, /*On fail goto*//*Label 8907*/ GIMT_Encode4(440827), // Rule ID 9049 //
     /* 440807 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 440810 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 440813 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 440816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 440820 */   // (AArch64uzp2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 440820 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_B),
     /* 440825 */   GIR_RootConstrainSelectedInstOperands,
     /* 440826 */   // GIR_Coverage, 9049,
     /* 440826 */   GIR_Done,
     /* 440827 */ // Label 8907: @440827
     /* 440827 */ GIM_Reject,
     /* 440828 */ // Label 8873: @440828
     /* 440828 */ GIM_Reject,
     /* 440829 */ // Label 151: @440829
     /* 440829 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 8916*/ GIMT_Encode4(441526),
     /* 440840 */ /*GILLT_s64*//*Label 8908*/ GIMT_Encode4(440876), GIMT_Encode4(0),
     /* 440848 */ /*GILLT_v2s32*//*Label 8909*/ GIMT_Encode4(440987),
     /* 440852 */ /*GILLT_v2s64*//*Label 8910*/ GIMT_Encode4(441064),
     /* 440856 */ /*GILLT_v4s16*//*Label 8911*/ GIMT_Encode4(441141),
     /* 440860 */ /*GILLT_v4s32*//*Label 8912*/ GIMT_Encode4(441218),
     /* 440864 */ /*GILLT_v8s8*//*Label 8913*/ GIMT_Encode4(441295),
     /* 440868 */ /*GILLT_v8s16*//*Label 8914*/ GIMT_Encode4(441372),
     /* 440872 */ /*GILLT_v16s8*//*Label 8915*/ GIMT_Encode4(441449),
     /* 440876 */ // Label 8908: @440876
     /* 440876 */ GIM_Try, /*On fail goto*//*Label 8917*/ GIMT_Encode4(440986),
     /* 440881 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 440884 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440888 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440892 */   GIM_Try, /*On fail goto*//*Label 8918*/ GIMT_Encode4(440917), // Rule ID 5299 //
     /* 440897 */     // MIs[0] Operand 2
     /* 440897 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
     /* 440908 */     // (AArch64vashr:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, 63:{ *:[i32] })  =>  (CMLTv1i64rz:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
     /* 440908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv1i64rz),
     /* 440911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440913 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440915 */     GIR_RootConstrainSelectedInstOperands,
     /* 440916 */     // GIR_Coverage, 5299,
     /* 440916 */     GIR_EraseRootFromParent_Done,
     /* 440917 */   // Label 8918: @440917
     /* 440917 */   GIM_Try, /*On fail goto*//*Label 8919*/ GIMT_Encode4(440951), // Rule ID 2124 //
     /* 440922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440925 */     // MIs[0] imm
     /* 440925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440929 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440933 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 440937 */     // MIs[1] Operand 1
     /* 440937 */     // No operand predicates
     /* 440937 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440939 */     // (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 440939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
     /* 440942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440944 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440946 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 440949 */     GIR_RootConstrainSelectedInstOperands,
     /* 440950 */     // GIR_Coverage, 2124,
     /* 440950 */     GIR_EraseRootFromParent_Done,
     /* 440951 */   // Label 8919: @440951
     /* 440951 */   GIM_Try, /*On fail goto*//*Label 8920*/ GIMT_Encode4(440985), // Rule ID 6363 //
     /* 440956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440959 */     // MIs[0] imm
     /* 440959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440967 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 440971 */     // MIs[1] Operand 1
     /* 440971 */     // No operand predicates
     /* 440971 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440973 */     // (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 440973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
     /* 440976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440978 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440980 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 440983 */     GIR_RootConstrainSelectedInstOperands,
     /* 440984 */     // GIR_Coverage, 6363,
     /* 440984 */     GIR_EraseRootFromParent_Done,
     /* 440985 */   // Label 8920: @440985
     /* 440985 */   GIM_Reject,
     /* 440986 */ // Label 8917: @440986
     /* 440986 */ GIM_Reject,
     /* 440987 */ // Label 8909: @440987
     /* 440987 */ GIM_Try, /*On fail goto*//*Label 8921*/ GIMT_Encode4(441063),
     /* 440992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 440995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440999 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441003 */   GIM_Try, /*On fail goto*//*Label 8922*/ GIMT_Encode4(441028), // Rule ID 4961 //
     /* 441008 */     // MIs[0] Operand 2
     /* 441008 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
     /* 441019 */     // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, 31:{ *:[i32] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 441019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 441022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441024 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441026 */     GIR_RootConstrainSelectedInstOperands,
     /* 441027 */     // GIR_Coverage, 4961,
     /* 441027 */     GIR_EraseRootFromParent_Done,
     /* 441028 */   // Label 8922: @441028
     /* 441028 */   GIM_Try, /*On fail goto*//*Label 8923*/ GIMT_Encode4(441062), // Rule ID 2231 //
     /* 441033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441036 */     // MIs[0] imm
     /* 441036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441044 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 441048 */     // MIs[1] Operand 1
     /* 441048 */     // No operand predicates
     /* 441048 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441050 */     // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i32_shift),
     /* 441053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441055 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441057 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441060 */     GIR_RootConstrainSelectedInstOperands,
     /* 441061 */     // GIR_Coverage, 2231,
     /* 441061 */     GIR_EraseRootFromParent_Done,
     /* 441062 */   // Label 8923: @441062
     /* 441062 */   GIM_Reject,
     /* 441063 */ // Label 8921: @441063
     /* 441063 */ GIM_Reject,
     /* 441064 */ // Label 8910: @441064
     /* 441064 */ GIM_Try, /*On fail goto*//*Label 8924*/ GIMT_Encode4(441140),
     /* 441069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 441072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441076 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441080 */   GIM_Try, /*On fail goto*//*Label 8925*/ GIMT_Encode4(441105), // Rule ID 4965 //
     /* 441085 */     // MIs[0] Operand 2
     /* 441085 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
     /* 441096 */     // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, 63:{ *:[i32] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 441096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 441099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441101 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441103 */     GIR_RootConstrainSelectedInstOperands,
     /* 441104 */     // GIR_Coverage, 4965,
     /* 441104 */     GIR_EraseRootFromParent_Done,
     /* 441105 */   // Label 8925: @441105
     /* 441105 */   GIM_Try, /*On fail goto*//*Label 8926*/ GIMT_Encode4(441139), // Rule ID 2233 //
     /* 441110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441113 */     // MIs[0] imm
     /* 441113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441121 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 441125 */     // MIs[1] Operand 1
     /* 441125 */     // No operand predicates
     /* 441125 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441127 */     // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i64_shift),
     /* 441130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441132 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441134 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441137 */     GIR_RootConstrainSelectedInstOperands,
     /* 441138 */     // GIR_Coverage, 2233,
     /* 441138 */     GIR_EraseRootFromParent_Done,
     /* 441139 */   // Label 8926: @441139
     /* 441139 */   GIM_Reject,
     /* 441140 */ // Label 8924: @441140
     /* 441140 */ GIM_Reject,
     /* 441141 */ // Label 8911: @441141
     /* 441141 */ GIM_Try, /*On fail goto*//*Label 8927*/ GIMT_Encode4(441217),
     /* 441146 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 441149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441153 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441157 */   GIM_Try, /*On fail goto*//*Label 8928*/ GIMT_Encode4(441182), // Rule ID 4960 //
     /* 441162 */     // MIs[0] Operand 2
     /* 441162 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 441173 */     // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, 15:{ *:[i32] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 441173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 441176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441178 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441180 */     GIR_RootConstrainSelectedInstOperands,
     /* 441181 */     // GIR_Coverage, 4960,
     /* 441181 */     GIR_EraseRootFromParent_Done,
     /* 441182 */   // Label 8928: @441182
     /* 441182 */   GIM_Try, /*On fail goto*//*Label 8929*/ GIMT_Encode4(441216), // Rule ID 2229 //
     /* 441187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441190 */     // MIs[0] imm
     /* 441190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441198 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 441202 */     // MIs[1] Operand 1
     /* 441202 */     // No operand predicates
     /* 441202 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441204 */     // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i16_shift),
     /* 441207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441211 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441214 */     GIR_RootConstrainSelectedInstOperands,
     /* 441215 */     // GIR_Coverage, 2229,
     /* 441215 */     GIR_EraseRootFromParent_Done,
     /* 441216 */   // Label 8929: @441216
     /* 441216 */   GIM_Reject,
     /* 441217 */ // Label 8927: @441217
     /* 441217 */ GIM_Reject,
     /* 441218 */ // Label 8912: @441218
     /* 441218 */ GIM_Try, /*On fail goto*//*Label 8930*/ GIMT_Encode4(441294),
     /* 441223 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441230 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441234 */   GIM_Try, /*On fail goto*//*Label 8931*/ GIMT_Encode4(441259), // Rule ID 4964 //
     /* 441239 */     // MIs[0] Operand 2
     /* 441239 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
     /* 441250 */     // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, 31:{ *:[i32] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 441250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 441253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441255 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441257 */     GIR_RootConstrainSelectedInstOperands,
     /* 441258 */     // GIR_Coverage, 4964,
     /* 441258 */     GIR_EraseRootFromParent_Done,
     /* 441259 */   // Label 8931: @441259
     /* 441259 */   GIM_Try, /*On fail goto*//*Label 8932*/ GIMT_Encode4(441293), // Rule ID 2232 //
     /* 441264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441267 */     // MIs[0] imm
     /* 441267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441275 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 441279 */     // MIs[1] Operand 1
     /* 441279 */     // No operand predicates
     /* 441279 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441281 */     // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i32_shift),
     /* 441284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441286 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441288 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441291 */     GIR_RootConstrainSelectedInstOperands,
     /* 441292 */     // GIR_Coverage, 2232,
     /* 441292 */     GIR_EraseRootFromParent_Done,
     /* 441293 */   // Label 8932: @441293
     /* 441293 */   GIM_Reject,
     /* 441294 */ // Label 8930: @441294
     /* 441294 */ GIM_Reject,
     /* 441295 */ // Label 8913: @441295
     /* 441295 */ GIM_Try, /*On fail goto*//*Label 8933*/ GIMT_Encode4(441371),
     /* 441300 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 441303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441307 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441311 */   GIM_Try, /*On fail goto*//*Label 8934*/ GIMT_Encode4(441336), // Rule ID 4959 //
     /* 441316 */     // MIs[0] Operand 2
     /* 441316 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 441327 */     // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, 7:{ *:[i32] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 441327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 441330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441332 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441334 */     GIR_RootConstrainSelectedInstOperands,
     /* 441335 */     // GIR_Coverage, 4959,
     /* 441335 */     GIR_EraseRootFromParent_Done,
     /* 441336 */   // Label 8934: @441336
     /* 441336 */   GIM_Try, /*On fail goto*//*Label 8935*/ GIMT_Encode4(441370), // Rule ID 2227 //
     /* 441341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441344 */     // MIs[0] imm
     /* 441344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441348 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441352 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 441356 */     // MIs[1] Operand 1
     /* 441356 */     // No operand predicates
     /* 441356 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441358 */     // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i8_shift),
     /* 441361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441363 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441365 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441368 */     GIR_RootConstrainSelectedInstOperands,
     /* 441369 */     // GIR_Coverage, 2227,
     /* 441369 */     GIR_EraseRootFromParent_Done,
     /* 441370 */   // Label 8935: @441370
     /* 441370 */   GIM_Reject,
     /* 441371 */ // Label 8933: @441371
     /* 441371 */ GIM_Reject,
     /* 441372 */ // Label 8914: @441372
     /* 441372 */ GIM_Try, /*On fail goto*//*Label 8936*/ GIMT_Encode4(441448),
     /* 441377 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 441380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441384 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441388 */   GIM_Try, /*On fail goto*//*Label 8937*/ GIMT_Encode4(441413), // Rule ID 4963 //
     /* 441393 */     // MIs[0] Operand 2
     /* 441393 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 441404 */     // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, 15:{ *:[i32] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 441404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 441407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441409 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441411 */     GIR_RootConstrainSelectedInstOperands,
     /* 441412 */     // GIR_Coverage, 4963,
     /* 441412 */     GIR_EraseRootFromParent_Done,
     /* 441413 */   // Label 8937: @441413
     /* 441413 */   GIM_Try, /*On fail goto*//*Label 8938*/ GIMT_Encode4(441447), // Rule ID 2230 //
     /* 441418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441421 */     // MIs[0] imm
     /* 441421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441429 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 441433 */     // MIs[1] Operand 1
     /* 441433 */     // No operand predicates
     /* 441433 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441435 */     // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i16_shift),
     /* 441438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441440 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441442 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441445 */     GIR_RootConstrainSelectedInstOperands,
     /* 441446 */     // GIR_Coverage, 2230,
     /* 441446 */     GIR_EraseRootFromParent_Done,
     /* 441447 */   // Label 8938: @441447
     /* 441447 */   GIM_Reject,
     /* 441448 */ // Label 8936: @441448
     /* 441448 */ GIM_Reject,
     /* 441449 */ // Label 8915: @441449
     /* 441449 */ GIM_Try, /*On fail goto*//*Label 8939*/ GIMT_Encode4(441525),
     /* 441454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 441457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441461 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441465 */   GIM_Try, /*On fail goto*//*Label 8940*/ GIMT_Encode4(441490), // Rule ID 4962 //
     /* 441470 */     // MIs[0] Operand 2
     /* 441470 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 441481 */     // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, 7:{ *:[i32] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 441481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 441484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441486 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441488 */     GIR_RootConstrainSelectedInstOperands,
     /* 441489 */     // GIR_Coverage, 4962,
     /* 441489 */     GIR_EraseRootFromParent_Done,
     /* 441490 */   // Label 8940: @441490
     /* 441490 */   GIM_Try, /*On fail goto*//*Label 8941*/ GIMT_Encode4(441524), // Rule ID 2228 //
     /* 441495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441498 */     // MIs[0] imm
     /* 441498 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441502 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441506 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 441510 */     // MIs[1] Operand 1
     /* 441510 */     // No operand predicates
     /* 441510 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441512 */     // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv16i8_shift),
     /* 441515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441517 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441519 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441522 */     GIR_RootConstrainSelectedInstOperands,
     /* 441523 */     // GIR_Coverage, 2228,
     /* 441523 */     GIR_EraseRootFromParent_Done,
     /* 441524 */   // Label 8941: @441524
     /* 441524 */   GIM_Reject,
     /* 441525 */ // Label 8939: @441525
     /* 441525 */ GIM_Reject,
     /* 441526 */ // Label 8916: @441526
     /* 441526 */ GIM_Reject,
     /* 441527 */ // Label 152: @441527
     /* 441527 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 8950*/ GIMT_Encode4(441982),
     /* 441538 */ /*GILLT_s64*//*Label 8942*/ GIMT_Encode4(441574), GIMT_Encode4(0),
     /* 441546 */ /*GILLT_v2s32*//*Label 8943*/ GIMT_Encode4(441660),
     /* 441550 */ /*GILLT_v2s64*//*Label 8944*/ GIMT_Encode4(441706),
     /* 441554 */ /*GILLT_v4s16*//*Label 8945*/ GIMT_Encode4(441752),
     /* 441558 */ /*GILLT_v4s32*//*Label 8946*/ GIMT_Encode4(441798),
     /* 441562 */ /*GILLT_v8s8*//*Label 8947*/ GIMT_Encode4(441844),
     /* 441566 */ /*GILLT_v8s16*//*Label 8948*/ GIMT_Encode4(441890),
     /* 441570 */ /*GILLT_v16s8*//*Label 8949*/ GIMT_Encode4(441936),
     /* 441574 */ // Label 8942: @441574
     /* 441574 */ GIM_Try, /*On fail goto*//*Label 8951*/ GIMT_Encode4(441659),
     /* 441579 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 441582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441586 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441590 */   GIM_Try, /*On fail goto*//*Label 8952*/ GIMT_Encode4(441624), // Rule ID 2133 //
     /* 441595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441598 */     // MIs[0] imm
     /* 441598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441606 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 441610 */     // MIs[1] Operand 1
     /* 441610 */     // No operand predicates
     /* 441610 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441612 */     // (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
     /* 441615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441617 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441619 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441622 */     GIR_RootConstrainSelectedInstOperands,
     /* 441623 */     // GIR_Coverage, 2133,
     /* 441623 */     GIR_EraseRootFromParent_Done,
     /* 441624 */   // Label 8952: @441624
     /* 441624 */   GIM_Try, /*On fail goto*//*Label 8953*/ GIMT_Encode4(441658), // Rule ID 6366 //
     /* 441629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441632 */     // MIs[0] imm
     /* 441632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441640 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 441644 */     // MIs[1] Operand 1
     /* 441644 */     // No operand predicates
     /* 441644 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441646 */     // (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 441646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
     /* 441649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441651 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441653 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441656 */     GIR_RootConstrainSelectedInstOperands,
     /* 441657 */     // GIR_Coverage, 6366,
     /* 441657 */     GIR_EraseRootFromParent_Done,
     /* 441658 */   // Label 8953: @441658
     /* 441658 */   GIM_Reject,
     /* 441659 */ // Label 8951: @441659
     /* 441659 */ GIM_Reject,
     /* 441660 */ // Label 8943: @441660
     /* 441660 */ GIM_Try, /*On fail goto*//*Label 8954*/ GIMT_Encode4(441705), // Rule ID 2290 //
     /* 441665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441668 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441675 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441679 */   // MIs[0] imm
     /* 441679 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441683 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441687 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 441691 */   // MIs[1] Operand 1
     /* 441691 */   // No operand predicates
     /* 441691 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441693 */   // (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (USHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441693 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i32_shift),
     /* 441696 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441698 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441700 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441703 */   GIR_RootConstrainSelectedInstOperands,
     /* 441704 */   // GIR_Coverage, 2290,
     /* 441704 */   GIR_EraseRootFromParent_Done,
     /* 441705 */ // Label 8954: @441705
     /* 441705 */ GIM_Reject,
     /* 441706 */ // Label 8944: @441706
     /* 441706 */ GIM_Try, /*On fail goto*//*Label 8955*/ GIMT_Encode4(441751), // Rule ID 2292 //
     /* 441711 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441714 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 441717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441721 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441725 */   // MIs[0] imm
     /* 441725 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441729 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441733 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 441737 */   // MIs[1] Operand 1
     /* 441737 */   // No operand predicates
     /* 441737 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441739 */   // (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i64_shift),
     /* 441742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441744 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441746 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441749 */   GIR_RootConstrainSelectedInstOperands,
     /* 441750 */   // GIR_Coverage, 2292,
     /* 441750 */   GIR_EraseRootFromParent_Done,
     /* 441751 */ // Label 8955: @441751
     /* 441751 */ GIM_Reject,
     /* 441752 */ // Label 8945: @441752
     /* 441752 */ GIM_Try, /*On fail goto*//*Label 8956*/ GIMT_Encode4(441797), // Rule ID 2288 //
     /* 441757 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441760 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 441763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441767 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441771 */   // MIs[0] imm
     /* 441771 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441775 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441779 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 441783 */   // MIs[1] Operand 1
     /* 441783 */   // No operand predicates
     /* 441783 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441785 */   // (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (USHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i16_shift),
     /* 441788 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441790 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441792 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441795 */   GIR_RootConstrainSelectedInstOperands,
     /* 441796 */   // GIR_Coverage, 2288,
     /* 441796 */   GIR_EraseRootFromParent_Done,
     /* 441797 */ // Label 8956: @441797
     /* 441797 */ GIM_Reject,
     /* 441798 */ // Label 8946: @441798
     /* 441798 */ GIM_Try, /*On fail goto*//*Label 8957*/ GIMT_Encode4(441843), // Rule ID 2291 //
     /* 441803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441806 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441809 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441813 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441817 */   // MIs[0] imm
     /* 441817 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441821 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441825 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 441829 */   // MIs[1] Operand 1
     /* 441829 */   // No operand predicates
     /* 441829 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441831 */   // (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (USHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
     /* 441834 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441836 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441838 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441841 */   GIR_RootConstrainSelectedInstOperands,
     /* 441842 */   // GIR_Coverage, 2291,
     /* 441842 */   GIR_EraseRootFromParent_Done,
     /* 441843 */ // Label 8957: @441843
     /* 441843 */ GIM_Reject,
     /* 441844 */ // Label 8947: @441844
     /* 441844 */ GIM_Try, /*On fail goto*//*Label 8958*/ GIMT_Encode4(441889), // Rule ID 2286 //
     /* 441849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 441855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441859 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441863 */   // MIs[0] imm
     /* 441863 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441867 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441871 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 441875 */   // MIs[1] Operand 1
     /* 441875 */   // No operand predicates
     /* 441875 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441877 */   // (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (USHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i8_shift),
     /* 441880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441882 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441884 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441887 */   GIR_RootConstrainSelectedInstOperands,
     /* 441888 */   // GIR_Coverage, 2286,
     /* 441888 */   GIR_EraseRootFromParent_Done,
     /* 441889 */ // Label 8958: @441889
     /* 441889 */ GIM_Reject,
     /* 441890 */ // Label 8948: @441890
     /* 441890 */ GIM_Try, /*On fail goto*//*Label 8959*/ GIMT_Encode4(441935), // Rule ID 2289 //
     /* 441895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 441901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441905 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441909 */   // MIs[0] imm
     /* 441909 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441913 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441917 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 441921 */   // MIs[1] Operand 1
     /* 441921 */   // No operand predicates
     /* 441921 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441923 */   // (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (USHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i16_shift),
     /* 441926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441928 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441930 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441933 */   GIR_RootConstrainSelectedInstOperands,
     /* 441934 */   // GIR_Coverage, 2289,
     /* 441934 */   GIR_EraseRootFromParent_Done,
     /* 441935 */ // Label 8959: @441935
     /* 441935 */ GIM_Reject,
     /* 441936 */ // Label 8949: @441936
     /* 441936 */ GIM_Try, /*On fail goto*//*Label 8960*/ GIMT_Encode4(441981), // Rule ID 2287 //
     /* 441941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441944 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 441947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441955 */   // MIs[0] imm
     /* 441955 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441959 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441963 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 441967 */   // MIs[1] Operand 1
     /* 441967 */   // No operand predicates
     /* 441967 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 441969 */   // (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (USHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 441969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv16i8_shift),
     /* 441972 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 441974 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441976 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 441979 */   GIR_RootConstrainSelectedInstOperands,
     /* 441980 */   // GIR_Coverage, 2287,
     /* 441980 */   GIR_EraseRootFromParent_Done,
     /* 441981 */ // Label 8960: @441981
     /* 441981 */ GIM_Reject,
     /* 441982 */ // Label 8950: @441982
     /* 441982 */ GIM_Reject,
     /* 441983 */ // Label 153: @441983
     /* 441983 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 8979*/ GIMT_Encode4(442762),
     /* 441994 */ /*GILLT_v2s32*//*Label 8961*/ GIMT_Encode4(442070),
     /* 441998 */ /*GILLT_v2s64*//*Label 8962*/ GIMT_Encode4(442125),
     /* 442002 */ /*GILLT_v4s16*//*Label 8963*/ GIMT_Encode4(442180),
     /* 442006 */ /*GILLT_v4s32*//*Label 8964*/ GIMT_Encode4(442235),
     /* 442010 */ /*GILLT_v8s8*//*Label 8965*/ GIMT_Encode4(442290),
     /* 442014 */ /*GILLT_v8s16*//*Label 8966*/ GIMT_Encode4(442324),
     /* 442018 */ /*GILLT_v16s8*//*Label 8967*/ GIMT_Encode4(442379), GIMT_Encode4(0),
     /* 442026 */ /*GILLT_nxv2s1*//*Label 8968*/ GIMT_Encode4(442413),
     /* 442030 */ /*GILLT_nxv2s16*//*Label 8969*/ GIMT_Encode4(442439),
     /* 442034 */ /*GILLT_nxv2s32*//*Label 8970*/ GIMT_Encode4(442465),
     /* 442038 */ /*GILLT_nxv2s64*//*Label 8971*/ GIMT_Encode4(442491),
     /* 442042 */ /*GILLT_nxv4s1*//*Label 8972*/ GIMT_Encode4(442538),
     /* 442046 */ /*GILLT_nxv4s16*//*Label 8973*/ GIMT_Encode4(442564),
     /* 442050 */ /*GILLT_nxv4s32*//*Label 8974*/ GIMT_Encode4(442590),
     /* 442054 */ /*GILLT_nxv8s1*//*Label 8975*/ GIMT_Encode4(442637),
     /* 442058 */ /*GILLT_nxv8s16*//*Label 8976*/ GIMT_Encode4(442663),
     /* 442062 */ /*GILLT_nxv16s1*//*Label 8977*/ GIMT_Encode4(442710),
     /* 442066 */ /*GILLT_nxv16s8*//*Label 8978*/ GIMT_Encode4(442736),
     /* 442070 */ // Label 8961: @442070
     /* 442070 */ GIM_Try, /*On fail goto*//*Label 8980*/ GIMT_Encode4(442124),
     /* 442075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 442078 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 442081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442085 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442089 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442093 */   GIM_Try, /*On fail goto*//*Label 8981*/ GIMT_Encode4(442108), // Rule ID 1906 //
     /* 442098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442101 */     // (AArch64zip1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ZIP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 442101 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 442106 */     GIR_RootConstrainSelectedInstOperands,
     /* 442107 */     // GIR_Coverage, 1906,
     /* 442107 */     GIR_Done,
     /* 442108 */   // Label 8981: @442108
     /* 442108 */   GIM_Try, /*On fail goto*//*Label 8982*/ GIMT_Encode4(442123), // Rule ID 5532 //
     /* 442113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442116 */     // (AArch64zip1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (ZIP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 442116 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 442121 */     GIR_RootConstrainSelectedInstOperands,
     /* 442122 */     // GIR_Coverage, 5532,
     /* 442122 */     GIR_Done,
     /* 442123 */   // Label 8982: @442123
     /* 442123 */   GIM_Reject,
     /* 442124 */ // Label 8980: @442124
     /* 442124 */ GIM_Reject,
     /* 442125 */ // Label 8962: @442125
     /* 442125 */ GIM_Try, /*On fail goto*//*Label 8983*/ GIMT_Encode4(442179),
     /* 442130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442133 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 442136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442140 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442144 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442148 */   GIM_Try, /*On fail goto*//*Label 8984*/ GIMT_Encode4(442163), // Rule ID 1908 //
     /* 442153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442156 */     // (AArch64zip1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ZIP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 442156 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
     /* 442161 */     GIR_RootConstrainSelectedInstOperands,
     /* 442162 */     // GIR_Coverage, 1908,
     /* 442162 */     GIR_Done,
     /* 442163 */   // Label 8984: @442163
     /* 442163 */   GIM_Try, /*On fail goto*//*Label 8985*/ GIMT_Encode4(442178), // Rule ID 5534 //
     /* 442168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442171 */     // (AArch64zip1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (ZIP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 442171 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
     /* 442176 */     GIR_RootConstrainSelectedInstOperands,
     /* 442177 */     // GIR_Coverage, 5534,
     /* 442177 */     GIR_Done,
     /* 442178 */   // Label 8985: @442178
     /* 442178 */   GIM_Reject,
     /* 442179 */ // Label 8983: @442179
     /* 442179 */ GIM_Reject,
     /* 442180 */ // Label 8963: @442180
     /* 442180 */ GIM_Try, /*On fail goto*//*Label 8986*/ GIMT_Encode4(442234),
     /* 442185 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 442188 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 442191 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442195 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442199 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442203 */   GIM_Try, /*On fail goto*//*Label 8987*/ GIMT_Encode4(442218), // Rule ID 1904 //
     /* 442208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442211 */     // (AArch64zip1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ZIP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 442211 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 442216 */     GIR_RootConstrainSelectedInstOperands,
     /* 442217 */     // GIR_Coverage, 1904,
     /* 442217 */     GIR_Done,
     /* 442218 */   // Label 8987: @442218
     /* 442218 */   GIM_Try, /*On fail goto*//*Label 8988*/ GIMT_Encode4(442233), // Rule ID 5530 //
     /* 442223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442226 */     // (AArch64zip1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (ZIP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 442226 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 442231 */     GIR_RootConstrainSelectedInstOperands,
     /* 442232 */     // GIR_Coverage, 5530,
     /* 442232 */     GIR_Done,
     /* 442233 */   // Label 8988: @442233
     /* 442233 */   GIM_Reject,
     /* 442234 */ // Label 8986: @442234
     /* 442234 */ GIM_Reject,
     /* 442235 */ // Label 8964: @442235
     /* 442235 */ GIM_Try, /*On fail goto*//*Label 8989*/ GIMT_Encode4(442289),
     /* 442240 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 442243 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 442246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442250 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442254 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442258 */   GIM_Try, /*On fail goto*//*Label 8990*/ GIMT_Encode4(442273), // Rule ID 1907 //
     /* 442263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442266 */     // (AArch64zip1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ZIP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 442266 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
     /* 442271 */     GIR_RootConstrainSelectedInstOperands,
     /* 442272 */     // GIR_Coverage, 1907,
     /* 442272 */     GIR_Done,
     /* 442273 */   // Label 8990: @442273
     /* 442273 */   GIM_Try, /*On fail goto*//*Label 8991*/ GIMT_Encode4(442288), // Rule ID 5533 //
     /* 442278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442281 */     // (AArch64zip1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (ZIP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 442281 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
     /* 442286 */     GIR_RootConstrainSelectedInstOperands,
     /* 442287 */     // GIR_Coverage, 5533,
     /* 442287 */     GIR_Done,
     /* 442288 */   // Label 8991: @442288
     /* 442288 */   GIM_Reject,
     /* 442289 */ // Label 8989: @442289
     /* 442289 */ GIM_Reject,
     /* 442290 */ // Label 8965: @442290
     /* 442290 */ GIM_Try, /*On fail goto*//*Label 8992*/ GIMT_Encode4(442323), // Rule ID 1902 //
     /* 442295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442298 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 442301 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 442304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442308 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442312 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442316 */   // (AArch64zip1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ZIP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 442316 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i8),
     /* 442321 */   GIR_RootConstrainSelectedInstOperands,
     /* 442322 */   // GIR_Coverage, 1902,
     /* 442322 */   GIR_Done,
     /* 442323 */ // Label 8992: @442323
     /* 442323 */ GIM_Reject,
     /* 442324 */ // Label 8966: @442324
     /* 442324 */ GIM_Try, /*On fail goto*//*Label 8993*/ GIMT_Encode4(442378),
     /* 442329 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 442332 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 442335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442339 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442343 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442347 */   GIM_Try, /*On fail goto*//*Label 8994*/ GIMT_Encode4(442362), // Rule ID 1905 //
     /* 442352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442355 */     // (AArch64zip1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ZIP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 442355 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
     /* 442360 */     GIR_RootConstrainSelectedInstOperands,
     /* 442361 */     // GIR_Coverage, 1905,
     /* 442361 */     GIR_Done,
     /* 442362 */   // Label 8994: @442362
     /* 442362 */   GIM_Try, /*On fail goto*//*Label 8995*/ GIMT_Encode4(442377), // Rule ID 5531 //
     /* 442367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442370 */     // (AArch64zip1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (ZIP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 442370 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
     /* 442375 */     GIR_RootConstrainSelectedInstOperands,
     /* 442376 */     // GIR_Coverage, 5531,
     /* 442376 */     GIR_Done,
     /* 442377 */   // Label 8995: @442377
     /* 442377 */   GIM_Reject,
     /* 442378 */ // Label 8993: @442378
     /* 442378 */ GIM_Reject,
     /* 442379 */ // Label 8967: @442379
     /* 442379 */ GIM_Try, /*On fail goto*//*Label 8996*/ GIMT_Encode4(442412), // Rule ID 1903 //
     /* 442384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 442390 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 442393 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442397 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442401 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442405 */   // (AArch64zip1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ZIP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 442405 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v16i8),
     /* 442410 */   GIR_RootConstrainSelectedInstOperands,
     /* 442411 */   // GIR_Coverage, 1903,
     /* 442411 */   GIR_Done,
     /* 442412 */ // Label 8996: @442412
     /* 442412 */ GIM_Reject,
     /* 442413 */ // Label 8968: @442413
     /* 442413 */ GIM_Try, /*On fail goto*//*Label 8997*/ GIMT_Encode4(442438), // Rule ID 3367 //
     /* 442418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442421 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 442424 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 442427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 442431 */   // (AArch64zip1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (ZIP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 442431 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
     /* 442436 */   GIR_RootConstrainSelectedInstOperands,
     /* 442437 */   // GIR_Coverage, 3367,
     /* 442437 */   GIR_Done,
     /* 442438 */ // Label 8997: @442438
     /* 442438 */ GIM_Reject,
     /* 442439 */ // Label 8969: @442439
     /* 442439 */ GIM_Try, /*On fail goto*//*Label 8998*/ GIMT_Encode4(442464), // Rule ID 2894 //
     /* 442444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442447 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 442450 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 442453 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442457 */   // (AArch64zip1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 442457 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 442462 */   GIR_RootConstrainSelectedInstOperands,
     /* 442463 */   // GIR_Coverage, 2894,
     /* 442463 */   GIR_Done,
     /* 442464 */ // Label 8998: @442464
     /* 442464 */ GIM_Reject,
     /* 442465 */ // Label 8970: @442465
     /* 442465 */ GIM_Try, /*On fail goto*//*Label 8999*/ GIMT_Encode4(442490), // Rule ID 2895 //
     /* 442470 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442473 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 442476 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 442479 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442483 */   // (AArch64zip1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 442483 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 442488 */   GIR_RootConstrainSelectedInstOperands,
     /* 442489 */   // GIR_Coverage, 2895,
     /* 442489 */   GIR_Done,
     /* 442490 */ // Label 8999: @442490
     /* 442490 */ GIM_Reject,
     /* 442491 */ // Label 8971: @442491
     /* 442491 */ GIM_Try, /*On fail goto*//*Label 9000*/ GIMT_Encode4(442537),
     /* 442496 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 442499 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 442502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442506 */   GIM_Try, /*On fail goto*//*Label 9001*/ GIMT_Encode4(442521), // Rule ID 2890 //
     /* 442511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442514 */     // (AArch64zip1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 442514 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 442519 */     GIR_RootConstrainSelectedInstOperands,
     /* 442520 */     // GIR_Coverage, 2890,
     /* 442520 */     GIR_Done,
     /* 442521 */   // Label 9001: @442521
     /* 442521 */   GIM_Try, /*On fail goto*//*Label 9002*/ GIMT_Encode4(442536), // Rule ID 2896 //
     /* 442526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442529 */     // (AArch64zip1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 442529 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 442534 */     GIR_RootConstrainSelectedInstOperands,
     /* 442535 */     // GIR_Coverage, 2896,
     /* 442535 */     GIR_Done,
     /* 442536 */   // Label 9002: @442536
     /* 442536 */   GIM_Reject,
     /* 442537 */ // Label 9000: @442537
     /* 442537 */ GIM_Reject,
     /* 442538 */ // Label 8972: @442538
     /* 442538 */ GIM_Try, /*On fail goto*//*Label 9003*/ GIMT_Encode4(442563), // Rule ID 3366 //
     /* 442543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 442549 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 442552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 442556 */   // (AArch64zip1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (ZIP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 442556 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
     /* 442561 */   GIR_RootConstrainSelectedInstOperands,
     /* 442562 */   // GIR_Coverage, 3366,
     /* 442562 */   GIR_Done,
     /* 442563 */ // Label 9003: @442563
     /* 442563 */ GIM_Reject,
     /* 442564 */ // Label 8973: @442564
     /* 442564 */ GIM_Try, /*On fail goto*//*Label 9004*/ GIMT_Encode4(442589), // Rule ID 2892 //
     /* 442569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442572 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 442575 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 442578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442582 */   // (AArch64zip1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 442582 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 442587 */   GIR_RootConstrainSelectedInstOperands,
     /* 442588 */   // GIR_Coverage, 2892,
     /* 442588 */   GIR_Done,
     /* 442589 */ // Label 9004: @442589
     /* 442589 */ GIM_Reject,
     /* 442590 */ // Label 8974: @442590
     /* 442590 */ GIM_Try, /*On fail goto*//*Label 9005*/ GIMT_Encode4(442636),
     /* 442595 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 442598 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 442601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442605 */   GIM_Try, /*On fail goto*//*Label 9006*/ GIMT_Encode4(442620), // Rule ID 2889 //
     /* 442610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442613 */     // (AArch64zip1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 442613 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 442618 */     GIR_RootConstrainSelectedInstOperands,
     /* 442619 */     // GIR_Coverage, 2889,
     /* 442619 */     GIR_Done,
     /* 442620 */   // Label 9006: @442620
     /* 442620 */   GIM_Try, /*On fail goto*//*Label 9007*/ GIMT_Encode4(442635), // Rule ID 2893 //
     /* 442625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442628 */     // (AArch64zip1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 442628 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 442633 */     GIR_RootConstrainSelectedInstOperands,
     /* 442634 */     // GIR_Coverage, 2893,
     /* 442634 */     GIR_Done,
     /* 442635 */   // Label 9007: @442635
     /* 442635 */   GIM_Reject,
     /* 442636 */ // Label 9005: @442636
     /* 442636 */ GIM_Reject,
     /* 442637 */ // Label 8975: @442637
     /* 442637 */ GIM_Try, /*On fail goto*//*Label 9008*/ GIMT_Encode4(442662), // Rule ID 3365 //
     /* 442642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442645 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 442648 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 442651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 442655 */   // (AArch64zip1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (ZIP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 442655 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
     /* 442660 */   GIR_RootConstrainSelectedInstOperands,
     /* 442661 */   // GIR_Coverage, 3365,
     /* 442661 */   GIR_Done,
     /* 442662 */ // Label 9008: @442662
     /* 442662 */ GIM_Reject,
     /* 442663 */ // Label 8976: @442663
     /* 442663 */ GIM_Try, /*On fail goto*//*Label 9009*/ GIMT_Encode4(442709),
     /* 442668 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 442671 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 442674 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442678 */   GIM_Try, /*On fail goto*//*Label 9010*/ GIMT_Encode4(442693), // Rule ID 2888 //
     /* 442683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442686 */     // (AArch64zip1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 442686 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
     /* 442691 */     GIR_RootConstrainSelectedInstOperands,
     /* 442692 */     // GIR_Coverage, 2888,
     /* 442692 */     GIR_Done,
     /* 442693 */   // Label 9010: @442693
     /* 442693 */   GIM_Try, /*On fail goto*//*Label 9011*/ GIMT_Encode4(442708), // Rule ID 2891 //
     /* 442698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442701 */     // (AArch64zip1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 442701 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
     /* 442706 */     GIR_RootConstrainSelectedInstOperands,
     /* 442707 */     // GIR_Coverage, 2891,
     /* 442707 */     GIR_Done,
     /* 442708 */   // Label 9011: @442708
     /* 442708 */   GIM_Reject,
     /* 442709 */ // Label 9009: @442709
     /* 442709 */ GIM_Reject,
     /* 442710 */ // Label 8977: @442710
     /* 442710 */ GIM_Try, /*On fail goto*//*Label 9012*/ GIMT_Encode4(442735), // Rule ID 2402 //
     /* 442715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 442721 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 442724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 442728 */   // (AArch64zip1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 442728 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_B),
     /* 442733 */   GIR_RootConstrainSelectedInstOperands,
     /* 442734 */   // GIR_Coverage, 2402,
     /* 442734 */   GIR_Done,
     /* 442735 */ // Label 9012: @442735
     /* 442735 */ GIM_Reject,
     /* 442736 */ // Label 8978: @442736
     /* 442736 */ GIM_Try, /*On fail goto*//*Label 9013*/ GIMT_Encode4(442761), // Rule ID 2887 //
     /* 442741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 442744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 442747 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 442750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 442754 */   // (AArch64zip1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 442754 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_B),
     /* 442759 */   GIR_RootConstrainSelectedInstOperands,
     /* 442760 */   // GIR_Coverage, 2887,
     /* 442760 */   GIR_Done,
     /* 442761 */ // Label 9013: @442761
     /* 442761 */ GIM_Reject,
     /* 442762 */ // Label 8979: @442762
     /* 442762 */ GIM_Reject,
     /* 442763 */ // Label 154: @442763
     /* 442763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9032*/ GIMT_Encode4(443542),
     /* 442774 */ /*GILLT_v2s32*//*Label 9014*/ GIMT_Encode4(442850),
     /* 442778 */ /*GILLT_v2s64*//*Label 9015*/ GIMT_Encode4(442905),
     /* 442782 */ /*GILLT_v4s16*//*Label 9016*/ GIMT_Encode4(442960),
     /* 442786 */ /*GILLT_v4s32*//*Label 9017*/ GIMT_Encode4(443015),
     /* 442790 */ /*GILLT_v8s8*//*Label 9018*/ GIMT_Encode4(443070),
     /* 442794 */ /*GILLT_v8s16*//*Label 9019*/ GIMT_Encode4(443104),
     /* 442798 */ /*GILLT_v16s8*//*Label 9020*/ GIMT_Encode4(443159), GIMT_Encode4(0),
     /* 442806 */ /*GILLT_nxv2s1*//*Label 9021*/ GIMT_Encode4(443193),
     /* 442810 */ /*GILLT_nxv2s16*//*Label 9022*/ GIMT_Encode4(443219),
     /* 442814 */ /*GILLT_nxv2s32*//*Label 9023*/ GIMT_Encode4(443245),
     /* 442818 */ /*GILLT_nxv2s64*//*Label 9024*/ GIMT_Encode4(443271),
     /* 442822 */ /*GILLT_nxv4s1*//*Label 9025*/ GIMT_Encode4(443318),
     /* 442826 */ /*GILLT_nxv4s16*//*Label 9026*/ GIMT_Encode4(443344),
     /* 442830 */ /*GILLT_nxv4s32*//*Label 9027*/ GIMT_Encode4(443370),
     /* 442834 */ /*GILLT_nxv8s1*//*Label 9028*/ GIMT_Encode4(443417),
     /* 442838 */ /*GILLT_nxv8s16*//*Label 9029*/ GIMT_Encode4(443443),
     /* 442842 */ /*GILLT_nxv16s1*//*Label 9030*/ GIMT_Encode4(443490),
     /* 442846 */ /*GILLT_nxv16s8*//*Label 9031*/ GIMT_Encode4(443516),
     /* 442850 */ // Label 9014: @442850
     /* 442850 */ GIM_Try, /*On fail goto*//*Label 9033*/ GIMT_Encode4(442904),
     /* 442855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 442858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 442861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442865 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442869 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442873 */   GIM_Try, /*On fail goto*//*Label 9034*/ GIMT_Encode4(442888), // Rule ID 1913 //
     /* 442878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442881 */     // (AArch64zip2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ZIP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 442881 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 442886 */     GIR_RootConstrainSelectedInstOperands,
     /* 442887 */     // GIR_Coverage, 1913,
     /* 442887 */     GIR_Done,
     /* 442888 */   // Label 9034: @442888
     /* 442888 */   GIM_Try, /*On fail goto*//*Label 9035*/ GIMT_Encode4(442903), // Rule ID 5537 //
     /* 442893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442896 */     // (AArch64zip2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (ZIP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 442896 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 442901 */     GIR_RootConstrainSelectedInstOperands,
     /* 442902 */     // GIR_Coverage, 5537,
     /* 442902 */     GIR_Done,
     /* 442903 */   // Label 9035: @442903
     /* 442903 */   GIM_Reject,
     /* 442904 */ // Label 9033: @442904
     /* 442904 */ GIM_Reject,
     /* 442905 */ // Label 9015: @442905
     /* 442905 */ GIM_Try, /*On fail goto*//*Label 9036*/ GIMT_Encode4(442959),
     /* 442910 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442913 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 442916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442920 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442924 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442928 */   GIM_Try, /*On fail goto*//*Label 9037*/ GIMT_Encode4(442943), // Rule ID 1915 //
     /* 442933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442936 */     // (AArch64zip2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ZIP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 442936 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
     /* 442941 */     GIR_RootConstrainSelectedInstOperands,
     /* 442942 */     // GIR_Coverage, 1915,
     /* 442942 */     GIR_Done,
     /* 442943 */   // Label 9037: @442943
     /* 442943 */   GIM_Try, /*On fail goto*//*Label 9038*/ GIMT_Encode4(442958), // Rule ID 5539 //
     /* 442948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442951 */     // (AArch64zip2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (ZIP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 442951 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
     /* 442956 */     GIR_RootConstrainSelectedInstOperands,
     /* 442957 */     // GIR_Coverage, 5539,
     /* 442957 */     GIR_Done,
     /* 442958 */   // Label 9038: @442958
     /* 442958 */   GIM_Reject,
     /* 442959 */ // Label 9036: @442959
     /* 442959 */ GIM_Reject,
     /* 442960 */ // Label 9016: @442960
     /* 442960 */ GIM_Try, /*On fail goto*//*Label 9039*/ GIMT_Encode4(443014),
     /* 442965 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 442968 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 442971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442975 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442979 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442983 */   GIM_Try, /*On fail goto*//*Label 9040*/ GIMT_Encode4(442998), // Rule ID 1911 //
     /* 442988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442991 */     // (AArch64zip2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ZIP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 442991 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 442996 */     GIR_RootConstrainSelectedInstOperands,
     /* 442997 */     // GIR_Coverage, 1911,
     /* 442997 */     GIR_Done,
     /* 442998 */   // Label 9040: @442998
     /* 442998 */   GIM_Try, /*On fail goto*//*Label 9041*/ GIMT_Encode4(443013), // Rule ID 5535 //
     /* 443003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443006 */     // (AArch64zip2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (ZIP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 443006 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 443011 */     GIR_RootConstrainSelectedInstOperands,
     /* 443012 */     // GIR_Coverage, 5535,
     /* 443012 */     GIR_Done,
     /* 443013 */   // Label 9041: @443013
     /* 443013 */   GIM_Reject,
     /* 443014 */ // Label 9039: @443014
     /* 443014 */ GIM_Reject,
     /* 443015 */ // Label 9017: @443015
     /* 443015 */ GIM_Try, /*On fail goto*//*Label 9042*/ GIMT_Encode4(443069),
     /* 443020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 443023 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 443026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443030 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443034 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443038 */   GIM_Try, /*On fail goto*//*Label 9043*/ GIMT_Encode4(443053), // Rule ID 1914 //
     /* 443043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443046 */     // (AArch64zip2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ZIP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 443046 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
     /* 443051 */     GIR_RootConstrainSelectedInstOperands,
     /* 443052 */     // GIR_Coverage, 1914,
     /* 443052 */     GIR_Done,
     /* 443053 */   // Label 9043: @443053
     /* 443053 */   GIM_Try, /*On fail goto*//*Label 9044*/ GIMT_Encode4(443068), // Rule ID 5538 //
     /* 443058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443061 */     // (AArch64zip2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (ZIP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 443061 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
     /* 443066 */     GIR_RootConstrainSelectedInstOperands,
     /* 443067 */     // GIR_Coverage, 5538,
     /* 443067 */     GIR_Done,
     /* 443068 */   // Label 9044: @443068
     /* 443068 */   GIM_Reject,
     /* 443069 */ // Label 9042: @443069
     /* 443069 */ GIM_Reject,
     /* 443070 */ // Label 9018: @443070
     /* 443070 */ GIM_Try, /*On fail goto*//*Label 9045*/ GIMT_Encode4(443103), // Rule ID 1909 //
     /* 443075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 443081 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 443084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443088 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443092 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443096 */   // (AArch64zip2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ZIP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 443096 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i8),
     /* 443101 */   GIR_RootConstrainSelectedInstOperands,
     /* 443102 */   // GIR_Coverage, 1909,
     /* 443102 */   GIR_Done,
     /* 443103 */ // Label 9045: @443103
     /* 443103 */ GIM_Reject,
     /* 443104 */ // Label 9019: @443104
     /* 443104 */ GIM_Try, /*On fail goto*//*Label 9046*/ GIMT_Encode4(443158),
     /* 443109 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 443112 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 443115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443119 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443123 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443127 */   GIM_Try, /*On fail goto*//*Label 9047*/ GIMT_Encode4(443142), // Rule ID 1912 //
     /* 443132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443135 */     // (AArch64zip2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ZIP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 443135 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
     /* 443140 */     GIR_RootConstrainSelectedInstOperands,
     /* 443141 */     // GIR_Coverage, 1912,
     /* 443141 */     GIR_Done,
     /* 443142 */   // Label 9047: @443142
     /* 443142 */   GIM_Try, /*On fail goto*//*Label 9048*/ GIMT_Encode4(443157), // Rule ID 5536 //
     /* 443147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443150 */     // (AArch64zip2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (ZIP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 443150 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
     /* 443155 */     GIR_RootConstrainSelectedInstOperands,
     /* 443156 */     // GIR_Coverage, 5536,
     /* 443156 */     GIR_Done,
     /* 443157 */   // Label 9048: @443157
     /* 443157 */   GIM_Reject,
     /* 443158 */ // Label 9046: @443158
     /* 443158 */ GIM_Reject,
     /* 443159 */ // Label 9020: @443159
     /* 443159 */ GIM_Try, /*On fail goto*//*Label 9049*/ GIMT_Encode4(443192), // Rule ID 1910 //
     /* 443164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 443170 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 443173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443177 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443181 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443185 */   // (AArch64zip2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ZIP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 443185 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v16i8),
     /* 443190 */   GIR_RootConstrainSelectedInstOperands,
     /* 443191 */   // GIR_Coverage, 1910,
     /* 443191 */   GIR_Done,
     /* 443192 */ // Label 9049: @443192
     /* 443192 */ GIM_Reject,
     /* 443193 */ // Label 9021: @443193
     /* 443193 */ GIM_Try, /*On fail goto*//*Label 9050*/ GIMT_Encode4(443218), // Rule ID 9081 //
     /* 443198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 443204 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 443207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 443211 */   // (AArch64zip2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (ZIP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 443211 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
     /* 443216 */   GIR_RootConstrainSelectedInstOperands,
     /* 443217 */   // GIR_Coverage, 9081,
     /* 443217 */   GIR_Done,
     /* 443218 */ // Label 9050: @443218
     /* 443218 */ GIM_Reject,
     /* 443219 */ // Label 9022: @443219
     /* 443219 */ GIM_Try, /*On fail goto*//*Label 9051*/ GIMT_Encode4(443244), // Rule ID 9036 //
     /* 443224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443227 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 443230 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 443233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443237 */   // (AArch64zip2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 443237 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 443242 */   GIR_RootConstrainSelectedInstOperands,
     /* 443243 */   // GIR_Coverage, 9036,
     /* 443243 */   GIR_Done,
     /* 443244 */ // Label 9051: @443244
     /* 443244 */ GIM_Reject,
     /* 443245 */ // Label 9023: @443245
     /* 443245 */ GIM_Try, /*On fail goto*//*Label 9052*/ GIMT_Encode4(443270), // Rule ID 9037 //
     /* 443250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443253 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 443256 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 443259 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443263 */   // (AArch64zip2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 443263 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 443268 */   GIR_RootConstrainSelectedInstOperands,
     /* 443269 */   // GIR_Coverage, 9037,
     /* 443269 */   GIR_Done,
     /* 443270 */ // Label 9052: @443270
     /* 443270 */ GIM_Reject,
     /* 443271 */ // Label 9024: @443271
     /* 443271 */ GIM_Try, /*On fail goto*//*Label 9053*/ GIMT_Encode4(443317),
     /* 443276 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 443279 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 443282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443286 */   GIM_Try, /*On fail goto*//*Label 9054*/ GIMT_Encode4(443301), // Rule ID 9032 //
     /* 443291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443294 */     // (AArch64zip2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 443294 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 443299 */     GIR_RootConstrainSelectedInstOperands,
     /* 443300 */     // GIR_Coverage, 9032,
     /* 443300 */     GIR_Done,
     /* 443301 */   // Label 9054: @443301
     /* 443301 */   GIM_Try, /*On fail goto*//*Label 9055*/ GIMT_Encode4(443316), // Rule ID 9038 //
     /* 443306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443309 */     // (AArch64zip2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 443309 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 443314 */     GIR_RootConstrainSelectedInstOperands,
     /* 443315 */     // GIR_Coverage, 9038,
     /* 443315 */     GIR_Done,
     /* 443316 */   // Label 9055: @443316
     /* 443316 */   GIM_Reject,
     /* 443317 */ // Label 9053: @443317
     /* 443317 */ GIM_Reject,
     /* 443318 */ // Label 9025: @443318
     /* 443318 */ GIM_Try, /*On fail goto*//*Label 9056*/ GIMT_Encode4(443343), // Rule ID 9080 //
     /* 443323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 443329 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 443332 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 443336 */   // (AArch64zip2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (ZIP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 443336 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
     /* 443341 */   GIR_RootConstrainSelectedInstOperands,
     /* 443342 */   // GIR_Coverage, 9080,
     /* 443342 */   GIR_Done,
     /* 443343 */ // Label 9056: @443343
     /* 443343 */ GIM_Reject,
     /* 443344 */ // Label 9026: @443344
     /* 443344 */ GIM_Try, /*On fail goto*//*Label 9057*/ GIMT_Encode4(443369), // Rule ID 9034 //
     /* 443349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443352 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 443355 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 443358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443362 */   // (AArch64zip2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 443362 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 443367 */   GIR_RootConstrainSelectedInstOperands,
     /* 443368 */   // GIR_Coverage, 9034,
     /* 443368 */   GIR_Done,
     /* 443369 */ // Label 9057: @443369
     /* 443369 */ GIM_Reject,
     /* 443370 */ // Label 9027: @443370
     /* 443370 */ GIM_Try, /*On fail goto*//*Label 9058*/ GIMT_Encode4(443416),
     /* 443375 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 443378 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 443381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443385 */   GIM_Try, /*On fail goto*//*Label 9059*/ GIMT_Encode4(443400), // Rule ID 9031 //
     /* 443390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443393 */     // (AArch64zip2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 443393 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 443398 */     GIR_RootConstrainSelectedInstOperands,
     /* 443399 */     // GIR_Coverage, 9031,
     /* 443399 */     GIR_Done,
     /* 443400 */   // Label 9059: @443400
     /* 443400 */   GIM_Try, /*On fail goto*//*Label 9060*/ GIMT_Encode4(443415), // Rule ID 9035 //
     /* 443405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443408 */     // (AArch64zip2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 443408 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 443413 */     GIR_RootConstrainSelectedInstOperands,
     /* 443414 */     // GIR_Coverage, 9035,
     /* 443414 */     GIR_Done,
     /* 443415 */   // Label 9060: @443415
     /* 443415 */   GIM_Reject,
     /* 443416 */ // Label 9058: @443416
     /* 443416 */ GIM_Reject,
     /* 443417 */ // Label 9028: @443417
     /* 443417 */ GIM_Try, /*On fail goto*//*Label 9061*/ GIMT_Encode4(443442), // Rule ID 9079 //
     /* 443422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 443428 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 443431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 443435 */   // (AArch64zip2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (ZIP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 443435 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
     /* 443440 */   GIR_RootConstrainSelectedInstOperands,
     /* 443441 */   // GIR_Coverage, 9079,
     /* 443441 */   GIR_Done,
     /* 443442 */ // Label 9061: @443442
     /* 443442 */ GIM_Reject,
     /* 443443 */ // Label 9029: @443443
     /* 443443 */ GIM_Try, /*On fail goto*//*Label 9062*/ GIMT_Encode4(443489),
     /* 443448 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 443451 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 443454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443458 */   GIM_Try, /*On fail goto*//*Label 9063*/ GIMT_Encode4(443473), // Rule ID 9030 //
     /* 443463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443466 */     // (AArch64zip2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 443466 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
     /* 443471 */     GIR_RootConstrainSelectedInstOperands,
     /* 443472 */     // GIR_Coverage, 9030,
     /* 443472 */     GIR_Done,
     /* 443473 */   // Label 9063: @443473
     /* 443473 */   GIM_Try, /*On fail goto*//*Label 9064*/ GIMT_Encode4(443488), // Rule ID 9033 //
     /* 443478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443481 */     // (AArch64zip2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 443481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
     /* 443486 */     GIR_RootConstrainSelectedInstOperands,
     /* 443487 */     // GIR_Coverage, 9033,
     /* 443487 */     GIR_Done,
     /* 443488 */   // Label 9064: @443488
     /* 443488 */   GIM_Reject,
     /* 443489 */ // Label 9062: @443489
     /* 443489 */ GIM_Reject,
     /* 443490 */ // Label 9030: @443490
     /* 443490 */ GIM_Try, /*On fail goto*//*Label 9065*/ GIMT_Encode4(443515), // Rule ID 2406 //
     /* 443495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443498 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 443501 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 443504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 443508 */   // (AArch64zip2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 443508 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_B),
     /* 443513 */   GIR_RootConstrainSelectedInstOperands,
     /* 443514 */   // GIR_Coverage, 2406,
     /* 443514 */   GIR_Done,
     /* 443515 */ // Label 9065: @443515
     /* 443515 */ GIM_Reject,
     /* 443516 */ // Label 9031: @443516
     /* 443516 */ GIM_Try, /*On fail goto*//*Label 9066*/ GIMT_Encode4(443541), // Rule ID 9029 //
     /* 443521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 443524 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 443527 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 443530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 443534 */   // (AArch64zip2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 443534 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_B),
     /* 443539 */   GIR_RootConstrainSelectedInstOperands,
     /* 443540 */   // GIR_Coverage, 9029,
     /* 443540 */   GIR_Done,
     /* 443541 */ // Label 9066: @443541
     /* 443541 */ GIM_Reject,
     /* 443542 */ // Label 9032: @443542
     /* 443542 */ GIM_Reject,
     /* 443543 */ // Label 155: @443543
     /* 443543 */ GIM_Reject,
     /* 443544 */ }; // Size: 443544 bytes
  return MatchTable0;
}
#undef GIMT_Encode2
#undef GIMT_Encode4
#undef GIMT_Encode8

#endif // ifdef GET_GLOBALISEL_IMPL

#ifdef GET_GLOBALISEL_PREDICATES_DECL
PredicateBitset AvailableModuleFeatures;
mutable PredicateBitset AvailableFunctionFeatures;
PredicateBitset getAvailableFeatures() const {
  return AvailableModuleFeatures | AvailableFunctionFeatures;
}
PredicateBitset
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const;
PredicateBitset
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget,
                                 const MachineFunction *MF) const;
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
#ifdef GET_GLOBALISEL_PREDICATES_INIT
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
AvailableFunctionFeatures()
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
